igneum/tools/chip-model/rtl/flow/sim.sh
2026-10-08 14:32:44 +00:00

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#!/usr/bin/env bash
# sim.sh <design-nickname> <tag> [plusargs...] : gate-level random-input simulation -> /work/sim/<name>/<tag>.vcd
set -euo pipefail
name=$1; tag=$2; shift 2
out=/work/sim/$name
simcells=$(yosys-config --datdir)/simcells.v
iverilog -g2005 -I /work/tb -o $out/sim_$tag $out/sim_net.v /work/tb/tb_$(sed -n "s/^$name \([^ ]*\) .*/\1/p" /work/flow/designs.txt).v $simcells
( cd $out && vvp -n sim_$tag "$@" | tee sim_$tag.log && mv dump.vcd $tag.vcd )
ls -la $out/$tag.vcd