igneum/tools/chip-model/rtl/flow/core32.mk
2026-10-08 14:32:44 +00:00

15 lines
654 B
Makefile

# ORFS design config for the programmable shadow core (core32: core_v6_32), ASAP7.
export PLATFORM = asap7
export DESIGN_NAME = core_v6_32
export DESIGN_NICKNAME = core32
export VERILOG_FILES = /work/rtl/core_v6_32.v
export VERILOG_INCLUDE_DIRS = /work/rtl
export SDC_FILE = /work/flow/core32.sdc
export CORE_UTILIZATION = 40
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 0.5
export PLACE_DENSITY = 0.55
export CORNER = TC
export SKIP_LAST_GASP = 1
export WORK_HOME = /work/out/core32
export SYNTH_MEMORY_MAX_BITS = 2000000