Counter ASIC 3.0
Counter ASIC 3.0: the class v4 rehearsal
Six phases from the specification to a fair launch. Each closes at its gate, a measurement published whether it passes or fails, so there is no date to slip. Below the phases, the latest entries of the engineering log.
Mining generator, shard proving, finality rules, written for external review
Mining program proven on Apple, NVIDIA and AMD; shard proving benchmark on consumer cards still to run
Gate: A fixed published workload, job received to accepted proof on a declared consumer card, sustained with no growing backlog, reproduced by three independent operators
BlockDAG node mining on the new program, GPU miners on three vendors, EVM execution in build
Gate: 1 block a second held with proofs under 60 s behind the tip
Sustained-mining finality, external proving jobs, miner client with auto-switching
Gate: Finality design passes external review
Three seed nodes and the public RPC are up; the one-click miner app on Windows, macOS and Linux, HiveOS, pools, the first rollup as a proving customer, no coin yet
Gate: 1,000 independent miners run 30 days and rollup proofs are delivered on time
Genesis with no premine, 30-day ramp. No listing is arranged, promised or sought by the project
Counter ASIC 3.0: the class v4 rehearsal
Counter ASIC 3.0 item 2: the per-day derivation
Counter ASIC 3.0 item 8: program work in the latency shadow
Counter ASIC 3.0 item 6: the reserve families' step costs
16:01Z: Ember run 6 on the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT)
07:12Z to 07:17Z, the host's chain mode with --save-shards records and --prev, on the Apple M5 Max's CPU
07:52Z to 08:24Z, the segment-aligned prover beside the miner on the RTX 5090 Windows rig's RTX 5090
12:25 to 13:20Z, the finality route: why 26 fresh nodes lost the seed every checkpoint
Ember Tune: the two-knob efficiency tune, the fleet prior, and what the three-card Windows rig could measure tonight
The SP1 CPU prover on the three-card Windows rig beside the miners, and the backend survey: no zkVM proves on AMD
The 9070 XT on the eGPU: why 17.9 MH/s, and what moved
Ember Tune: the two-knob efficiency tune, the fleet prior, and what the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) could measure tonight
Read width of the lottery hash: 4, 16 and 64-byte loads, a per-load mix, a written scratch; three cards
The hot table on the M5 Max: a second table sized to GPU cache beside the 1 GiB dataset
Mixer x4 and the cache growth rule: the class v3 dataset construction, with the x8 candidate
The SP1 CPU prover on the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) beside the miners, and the backend survey: no zkVM proves on AMD
Proving v1: segment records, the chain rule, the unproven rule; what was measured tonight
Dp4a-class throughput on the M5 Max: the dot4 emulation against the ALU chain
Epoch length as an era parameter : the Apple M5 Max's compile-ahead per program
Aggregation cost on the RTX 5090: what a per-block aggregation spends and what each lever gives
EVM transaction relay: three nodes in a chain, every transaction sent to one end included by the other two miners
The prover carries both fee tables and the height switch: one pinned guest on either side of DAA 210,000
Live devnet: real transactions, the first non-empty shard proven and paid, and the exporter's block structure fixed
The program id split: why the Apple M5 Max rejected the RTX 5090 Windows rig's proofs, and the verifier at 114 s
One-click Windows workers: what the Apple M5 Max could measure
First finality lock on the live devnet: checkpoint 242 at 77.4% of all weight, two hours after genesis
The gfx1036 worker fault and what the Apple M5 Max could and could not reproduce
First machine on the Igneum Miner app: the RTX 5090 Windows rig's RTX 5090 at 118 MH/s, via Setup.exe
Difficulty rule v2: the live oscillation, its cause, the DAG replay, the fix behind a height switch
The observer stored nothing for 78 minutes, then 7,022 blocks in two minutes
Nothing in the log matches that.
Every entry is a dated heading of the engineering log, where the commands and the hardware are. The phases and their gates are the litepaper’s roadmap.