igneum-labs
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ec0c36f611
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Counter ASIC 2.0 status 21:23: the era package, the V3_CLASS composition rule
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2026-10-05 21:23:38 +00:00 |
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igneum-labs
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123af2d107
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Counter ASIC 2.0 status 21:23: the installer build republished, PC 1 order
|
2026-10-05 21:23:10 +00:00 |
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igneum-labs
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877b45a116
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Counter ASIC 2.0 status 21:22: the installer build job failed in 2 s, PC 1 decision pending
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2026-10-05 21:22:37 +00:00 |
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igneum-labs
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ced3b703d4
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Counter ASIC 2.0 status 21:22: Ember Tune queued
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2026-10-05 21:22:20 +00:00 |
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igneum-labs
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e8547b1bcb
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Counter ASIC 2.0 status 21:21: PC 2 to agg-cost-pc2-2 until 21:45, the PC 1 order
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2026-10-05 21:21:27 +00:00 |
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igneum-labs
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41afd097cd
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Counter ASIC 2.0 status 21:20: the added-form hot table on the Mac, the decision rule for layer 5
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2026-10-05 21:20:53 +00:00 |
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igneum-labs
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8420f074d5
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Counter ASIC 2.0 status 21:20: layer 9 complete with the compile-ahead table and the floor
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2026-10-05 21:20:25 +00:00 |
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igneum-labs
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5a6c30560a
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Counter ASIC 2.0: the proving v1 app branch final 6dc686a; the 0.3.11 tree composition; status 21:20
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2026-10-05 21:20:13 +00:00 |
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igneum-labs
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451b02ea42
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Counter ASIC 2.0 status 21:11: the 9070 XT back on the bus, PC 1 to the 0.3.10 build, the playbook parse-gate rule
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2026-10-05 21:11:19 +00:00 |
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igneum-labs
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1319adf588
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Counter ASIC 2.0 status 21:05: the node merge ba43cf0f, the hot-table package, unproven_daa at fast time
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2026-10-05 21:05:20 +00:00 |
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igneum-labs
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006b2fe585
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Counter ASIC 2.0: proving v1 handoff recorded in the rollout plan; status 21:04
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2026-10-05 21:04:35 +00:00 |
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igneum-labs
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4366c6ad90
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Counter ASIC 2.0 status 21:02: the measure lock convoy, found by lsof
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2026-10-05 21:02:13 +00:00 |
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igneum-labs
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64ab9ce8d0
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Counter ASIC 2.0 status 21:01: the 0.3.10 installer build takes PC 1 after the repro run
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2026-10-05 21:01:20 +00:00 |
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igneum-labs
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b93d1897eb
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Counter ASIC 2.0 status 21:00: PC 1 to the repro run, PC 2 to agg-cost, the CPU fallback numbers, the S_p shard dropped
|
2026-10-05 21:00:58 +00:00 |
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igneum-labs
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2abdb56194
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Counter ASIC 2.0 status 20:58: PC 1 and PC 2 occupancy
|
2026-10-05 20:58:57 +00:00 |
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igneum-labs
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b4e94a482d
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Counter ASIC 2.0 status 20:57: the mixer construction committed, MX4 is V3_CLASS
|
2026-10-05 20:57:12 +00:00 |
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igneum-labs
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88740ce75e
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Counter ASIC 2.0 status 20:56: PC 2 released, the proving fork tip, the S_p curve with the miner on
|
2026-10-05 20:56:23 +00:00 |
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igneum-labs
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3e237db050
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counter-asic-2.md: layer 9 row and the decisions table of 5 October 2026 (night)
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2026-10-05 20:53:45 +00:00 |
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igneum-labs
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9eee20f97c
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Counter ASIC 2.0 status 20:53: spec text applied for layers 6, 7, 9; what still lands from the branches
|
2026-10-05 20:53:12 +00:00 |
|
igneum-labs
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cf0839a231
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Counter ASIC 2.0 status 20:51: chain_dataset_day wired in the node, evidence row 22
|
2026-10-05 20:51:52 +00:00 |
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igneum-labs
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4a7b72da9b
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Litepaper hardware line on the step schedule; status 20:51: public copy applied, level 1 and the limits bullet wait for the chip row
|
2026-10-05 20:51:26 +00:00 |
|
igneum-labs
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949c4582e1
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Counter ASIC 2.0 status: readwidth head hash corrected to 06dcb31
|
2026-10-05 20:50:30 +00:00 |
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igneum-labs
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4f042f37dc
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Counter ASIC 2.0 status 20:50: the measure lock holder, the with-lock status defect
|
2026-10-05 20:50:05 +00:00 |
|
igneum-labs
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4a1f872cb6
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Counter ASIC 2.0 status 20:49: mixer construction, the lock cleared, PC 2 state, one merged-tree suite job
|
2026-10-05 20:49:39 +00:00 |
|
igneum-labs
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27471633c7
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Counter ASIC 2.0 status: heading times 20:42 to 20:47 corrected to the commit clock
|
2026-10-05 20:48:20 +00:00 |
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igneum-labs
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9343d96a98
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Counter ASIC 2.0 status 21:15: the Sonnet box off the link, PC 1 facts corrected, the queue
|
2026-10-05 20:47:57 +00:00 |
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igneum-labs
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c8f0fe7472
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Counter ASIC 2.0: the G1 ruling (gfx1036 as the AMD vendor tonight), hardware events section for the morning
|
2026-10-05 20:46:20 +00:00 |
|
igneum-labs
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fbeb3bb94d
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Counter ASIC 2.0 status 21:05: the 9070 XT absent on PC 1, app restart facts, era package ETA
|
2026-10-05 20:45:35 +00:00 |
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igneum-labs
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878c0581ef
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Counter ASIC 2.0 status 21:00: the Metal pack path, the --prepare-packs app item, the seam signatures, the build queue
|
2026-10-05 20:44:16 +00:00 |
|
igneum-labs
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0e337349d0
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Counter ASIC 2.0 rollout: the rig miners' exit-42 path on the next-cut list as a layer 9 precondition
|
2026-10-05 20:42:03 +00:00 |
|
igneum-labs
|
3e3b12b505
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Counter ASIC 2.0: C18 per-pound correction struck everywhere, C19 and C20 routed
|
2026-10-05 20:41:50 +00:00 |
|
igneum-labs
|
3f9bf60576
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Counter ASIC 2.0 status 20:45: the node switch written, the Metal worker gate item, PC 1 gaps
|
2026-10-05 20:41:37 +00:00 |
|
igneum-labs
|
33713368b6
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Counter ASIC 2.0 status: heading times corrected to the commit clock (UTC)
|
2026-10-05 20:41:03 +00:00 |
|
igneum-labs
|
7f3201f533
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Counter ASIC 2.0: rig-install follow-ups on the next-cut list, the CPU fixture in the PC 1 gap, no more agents
|
2026-10-05 20:39:44 +00:00 |
|
igneum-labs
|
9dcb9697cf
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Counter ASIC 2.0 status 23:20: the PC 1 queue
|
2026-10-05 20:39:03 +00:00 |
|
igneum-labs
|
4ce31bbbe0
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Counter ASIC 2.0 status 23:10: layer 7 PC rows, PC 1 free
|
2026-10-05 20:38:08 +00:00 |
|
igneum-labs
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3f33c6fd00
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Counter ASIC 2.0 status 23:00: layer 9 agent, PC queues
|
2026-10-05 20:32:53 +00:00 |
|
igneum-labs
|
770145f7be
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Counter ASIC 2.0: card lifetime merged, cache freed after the build, growth mapping (b) recommended, public lines listed
|
2026-10-05 20:31:48 +00:00 |
|
igneum-labs
|
fa5a69148b
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Merge branch 'card-lifetime' into ca2-coord
|
2026-10-05 20:31:25 +00:00 |
|
igneum-labs
|
efeab4b23d
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Counter ASIC 2.0 rollout: ota-k2 commit on the next-cut list
|
2026-10-05 20:29:37 +00:00 |
|
igneum-labs
|
35b3e38d2a
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Counter ASIC 2.0 status 22:40: C1 decision and the 16:00Z check, one packfile.h fix
|
2026-10-05 20:29:09 +00:00 |
|
igneum-labs
|
724c5eee37
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Counter ASIC 2.0: layer 9 row, C1 constraint, era mid-way and the attempt-aware packfile bug, C10 and C11 answers
|
2026-10-05 20:27:58 +00:00 |
|
igneum-labs
|
fff1994c8a
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Counter ASIC 2.0: layers 1, 2, 3 decided from the readwidth table, layer 5 Mac rows and the added-form redesign, user tiers, public level 2 edit
|
2026-10-05 20:27:01 +00:00 |
|
igneum-labs
|
6a9b7c1283
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Counter ASIC 2.0: the mixer x4 decision into v3, ca2-mixer agent, status 22:00
|
2026-10-05 20:27:01 +00:00 |
|
igneum-labs
|
f4fc651512
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Counter ASIC 2.0: layer 3 decided (scratch share 0, chip 2.4x at every share), the claim qualified, public level 3 headline
|
2026-10-05 20:27:01 +00:00 |
|
igneum-labs
|
5c3a35c6de
|
Counter ASIC 2.0 status 21:35: the corrected SRAM mirror table
|
2026-10-05 20:27:01 +00:00 |
|
igneum-labs
|
bcb3f20bd9
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Counter ASIC 2.0 status 21:25: proving v1 state, PC 2 queue
|
2026-10-05 20:27:01 +00:00 |
|
igneum-labs
|
cbbc81f002
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Counter ASIC 2.0: the shipped-density correction to the SRAM mirror (130 to 165 mm^2), carried into the rollout and public docs
|
2026-10-05 20:27:01 +00:00 |
|
igneum-labs
|
b258094890
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Counter ASIC 2.0: layer 6 option C and layer 7 R1 decided (delegated), the chip headline rule for the scratch share
|
2026-10-05 20:27:01 +00:00 |
|
igneum-labs
|
ece48696f3
|
Counter ASIC 2.0 status 20:55: layers 6 and 7, node agent, 0.3.11 scope with proving v1
|
2026-10-05 20:27:01 +00:00 |
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