PC 2 job run-ca3-shadow-pc2-20261006 (card empty, every pack bit-exact against the Mac): the 5090 holds its rate to
150,800 ops per hash and loses 2.7 percent at 199,600 under the app's 431 W cap, which binds from 102,100 ops up and
takes the clock from 3,037 to 1,834 MHz (86 MH/s at 330,700 ops); 350 W at the control, 2.65 to 3.27 microjoules per
hash; marginal ALU energy 10 to 13 pJ per counted op. Clock rows OWED (nvidia-smi refused -lgc without rights). Chip
side at N = 100,000 and k = 1: 2.1x over the 5090 on GDDR7, 0.9x over the M5 Max. GO at mx8+sh256x27.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
The mean over every present id let one paused-and-resumed card (the Mac, a 178% step) push
every other residual the same way in the epochs it was off, which read as an r = 0.94 edge
between two honest 5090 keys on the merged tree (window 41 to 46). The factor is now the
median over ids that are steady and present in every window epoch (median over all present
when the core is under 3): the same window reads max r 0.10. README: the three calibration
readings (the edge, the factor-of-two from identities=2, the unsteady Mac) answered.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
The M5 Max ladder (Metal, packbench, IOReport GPU and DRAM watts without root): latency-bound to about 100,000 ops per
hash, the 5 percent point about 130,000, 11 to 27 W GPU at 100,000 ops, 0.78 to 1.40 microjoules per hash; the
verifier's law 2.06 ms + 3.2 us per 1,000 shadow instructions per warp on one core; every pack bit-exact. The
analysis file with the knob, the chip side (k = 1, 1.5, 0.3), the gates and the consequences; the bench-log entry;
the 5090 rows pending the PC 2 job (the playbook now carries the core-clock rows and the sh256x40 rung).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
A shadow block of S ALU instructions run R times at the end of every iteration, drawn from the program stream after
the 64 base instructions, behind LoadClass::shadow: v2 and v3 draw nothing and emit nothing (the pinned packs are
byte-identical, cargo test 54 + 4 + 19 + 7 green). The interpreter, the three kernel dialects (both kernels each),
program.h and program.json carry it; the acceptance rule interprets the base program only. Packs for seed
igneum-genesis over class mx8 at 4,096 to 180,224 shadow instructions per hash (proto-cuda/packs-ca3-shadow), and
the PC 2 bench playbook tools/ca3-shadow/pc2-shadow-bench.ps1 (passes the publisher's three checks).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
docs/plans/counter-asic-3-derivation.md (the design, the acceptance test, the interpreter, the allowance argument,
the measurements, the PROPOSED reserve entry R0 for 1.13.2, what is owed), docs/analysis/chip-model-v3.md section 6
(the per-day derivation rows at 1.0x to 3x allowances), the bench-log entry, relay/playbooks/ca3-derive-pc2.ps1
(one PC 2 job: self-fetched packs zip, the installed worker through NVRTC, the card off only under test with its
key from settings.json). Verifier 4.875 / 4.944 ms per unit on one M5 Max core under the measure lock against
x8's 2.061 / 2.063; Metal build 29 ms against 22; hash rate equal; bit-exact on Metal and Apple OpenCL.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
docs/plans/funding.md rule 5: the bounty is escrowed and the benchmark live before daily
issuance crosses USD 20,000 a day, with the price-per-IGN table per halving period.
docs/plans/epoch-length.md section 11: the detector alert held 6 net windows recommends
the next shorter ladder step, per-tier costs at 2,400 and 600, the adversary's share per
compile class. Section 12: HBM FPGA parts with sources, reads in flight per watt against
the RTX 5090 (0.3x to 0.4x at Shuhai's measured rate, up to 1.9x at the unmeasured bank
ceiling), the two FPGA lanes in one table, and the ranking: layer 9 above layer 7.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
tools/observer/detector.mjs: per-program implied rate per miner id from blue work over
wall seconds (the chain's own estimate rule restricted to one id), excess spread above
Poisson, epoch-start share, nonce chi-square and increasing-fraction tests, card bands
from the log intake, two-way residual correlations and cliques; a design_candidate clique
held 6 net windows is the alert, written to live_state.detector and live_events kind
detector. One hook in observer.mjs (every 60 s) and one jsonb column. node:test file
with a fabricated fixed design (fires) and a fabricated honest population (quiet); the
live devnet in --dry mode is quiet with its baseline recorded in the README.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
A prototype behind a new LoadClass field (derive_len) and Shape field, Shape::for_class_day: every mixer slot of
the item derivation runs a straight-line program of 736 instructions drawn from the day key stream (the same
SplitMix64 stream, after the 40 mixer draws), twelve two-register forms, the chain rule of SuperscalarHash made
strict (every instruction reads the register the previous one wrote), an acceptance test with the x8 mixer's
operation and multiply counts from the code as floors (72 x 144 as written, 72 x 128 hoisted, 1,152 multiplies).
The verifier runs the program with a word-major (SoA) interpreter over the 32 items of a load, dispatching on
instruction pairs; no JIT. The emitter writes mh_round_0..8 into memhard.h, memhard.metal and kernel.cl. Packs
dr736-genesis and dr736-devnet-epoch0 under proto-cuda/packs-ca3-derive. The v2 and v3 paths are untouched: every
pinned pack re-exports byte for byte (tests/packs.rs), cargo test -p igneum-pow 58 + 7 + 4 + 19 + 7 green.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
f = 0, 0.25, 0.5, 0.75, 1 on GDDR7 (the 5090's board), one HBM3 stack and eight HBM3 stacks, scored in energy per
hash, reads in flight per watt, rate per chip and dollars per MH/s against the RTX 5090 at 136.1 MH/s and 326 W.
The curve is monotone toward f = 1; the f = 1 chip reads 5.1x (GDDR7) to 9.2x (HBM3) per joule in the model and
2.1x to 4.8x by the Ethash precedent: over 2x. The mixer and item 2 do not touch it; the levers named are the
5090's watts under a power cap (a PC 2 job, owed) and program work in the latency shadow. Inputs cited with URLs
read 6 October 2026; the mixer counted from memhard.rs at 128 hoisted / 144 unhoisted ops per application.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
One row in the funding table (USD 80,000 to 160,000 for two independent reviews, basis the four RandomX reviews of 2019 at their published per-firm prices and person-days) and a section "The mixer cryptanalysis brief (Counter ASIC 3.0 item 3)": the target shape from memhard.rs and accept.rs, the ranked break list with the chip-model number each moves, deliverables and timebox, the soundness suite to re-run, acceptance criteria in the RandomX audit style, candidate reviewers with citations, the risk column against the two-publish rollout, the timing against the testnet go checklist, and the consequences per user tier. Nothing else in the file is touched.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
