igneum-labs
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c9daf50004
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C29 and D11: the verifier line on the fixed crate, the bounty struck until escrowed, the final-class rates in the public tables; status 22:25
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2026-10-05 22:25:02 +00:00 |
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igneum-labs
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4f75b7cdfb
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Site and litepaper: level 1 on the hero and abstract, the chip bullet on the measured row; the level 3 table filled; status 22:18
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2026-10-05 22:18:39 +00:00 |
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igneum-labs
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10421ff814
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Counter ASIC 2.0: the iGPU restart-per-epoch statement, dataset reuse on the next-cut list, the gate's script fix; status 21:32
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2026-10-05 21:32:35 +00:00 |
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igneum-labs
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6386291e32
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Counter ASIC 2.0: C18 per-pound correction struck everywhere, C19 and C20 routed
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2026-10-05 20:41:50 +00:00 |
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igneum-labs
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cafb38c3e5
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Counter ASIC 2.0: layers 1, 2, 3 decided from the readwidth table, layer 5 Mac rows and the added-form redesign, user tiers, public level 2 edit
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2026-10-05 20:27:01 +00:00 |
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igneum-labs
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3f67b31280
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Counter ASIC 2.0: the mixer x4 decision into v3, ca2-mixer agent, status 22:00
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2026-10-05 20:27:01 +00:00 |
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igneum-labs
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76df7f7c91
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Counter ASIC 2.0: layer 3 decided (scratch share 0, chip 2.4x at every share), the claim qualified, public level 3 headline
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2026-10-05 20:27:01 +00:00 |
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igneum-labs
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2144eefa3d
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Counter ASIC 2.0: the shipped-density correction to the SRAM mirror (130 to 165 mm^2), carried into the rollout and public docs
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2026-10-05 20:27:01 +00:00 |
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igneum-labs
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d061ab5c06
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Counter ASIC: the public description in four levels (levels 1 and 2 as copy, 3 and 4 with owed markers)
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2026-10-05 20:27:01 +00:00 |
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