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igneum-labs
be1ff694ca Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8} 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:14:50 +00:00
igneum-labs
a07d693710 Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:12:47 +00:00
igneum-labs
e458519a34 Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:04:29 +00:00
igneum-labs
2fc3377cd0 Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:00:21 +00:00
igneum-labs
93a5e401b1 Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 07:13:00 +00:00
igneum-labs
963235c7cf Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:02:48 +00:00
igneum-labs
fc16c2ef14 Counter ASIC 4.0 research: 15.1a the microbench rows (20 probes on the 5090 at both states) and the correction they force: a tile is 32 MACs per lane, not 1,024, so the int8 MAC costs 1.5 to 4 pJ measured (the 6 October 4090 figure 1.8, not 0.056); the tensor shadow is the worse lever (k 0.03 to 0.3); the shuffle at 55.8 pJ per op is the card's dearest instruction (the re-weight's GPU side against it); an L2 hit at 2.4 nJ kills the hot-table lever; the first sentence and the ranking corrected 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:02:04 +00:00
igneum-labs
100d50aab7 Counter ASIC 4.0 research: 20.3b the SM-sparse reading (a quarter of the SMs holds 98 percent of the rate at the same draw; the draw follows the work, not the SM count): rank 2 dead on measured rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 05:16:12 +00:00
igneum-labs
9422f42a7d Counter ASIC 4.0 research: 20.4 names the 1,430-tile point as the one the k column was priced at, the Apple side open, nothing served moving 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:27:11 +00:00
igneum-labs
8522caca0e Counter ASIC 4.0 research: 20.3 the card rows of the seven packs (the tile block carries the ALU shadow's premium at the same rate, 14 percent cheaper at the knee; 0.048 to 0.091 pJ per MAC measured on the 5090), 20.4 the chip-model rows, the first sentence on measured rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:26:42 +00:00
igneum-labs
0b0151b554 Counter ASIC 4.0 research: --bench honours --variant through the pinned race (the SM-sparse run of 00:22 to 00:41 UTC served base on all 48 rows); RESULT carries variant, sparse_blocks and block_warps, variant_not_installed is the known-failed line; 20.3a records the run and its knee rows (v4 309.9 W, v3 219.4 W, premium 90.5 W at 1,300 MHz) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 00:44:35 +00:00
igneum-labs
4072cd7f07 Counter ASIC 4.0 research: 20.2a-close, the per-load 16 x 27 construction dead as a chain class (1.4 percent acceptance, 42 of 64 seeds without a program), the sound form named, rank 4 marked 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 22:53:36 +00:00
igneum-labs
d267043677 Counter ASIC 4.0 research: 20.2a the per-load fault fixed with clock readings, the drawn-era census (0 pairs across 16 eras), the Metal fingerprints (the tile reference bit-exact; the Apple emulation costs 35 and 78 percent of rate at 1,024 and 4,096 tiles per hash); 20.2b the biased-product-bits requirement from adv-cache-2 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 22:33:15 +00:00
igneum-labs
598fd20f02 Counter ASIC 4.0 research: 20.2 the verifier rows (AVX2 tile path 0.047 us per tile per unit, mm1430 10.14 ms loaded; the per-load placement derives 11 percent fewer distinct items per warp: a uniformity fault as drawn, with its fix) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 22:08:58 +00:00
igneum-labs
1a7689e1b2 Counter ASIC 4.0 research: section 20, the two prototypes built (what, where, gates; the verifier and card rows pending) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 21:55:14 +00:00
igneum-labs
e767701097 Counter ASIC 4.0 research, second pass: the k-above-1 hunt, the capex lever and the re-ranked list 
Sections 15 to 19: every GPU block gaming and AI paid for, priced against the best public 4 to 5 nm chip figure with its k band, verifier cost and the edge at the measured premium (the one-sentence answer: nothing reads k above 1 with certainty; the int8 tensor tile is the only block near or above 1, so the tensor shadow with a SIMD byte-dot verifier is the new rank 3); the capex column added to the chip model (both sides capex-dominated at 7x to 10x their electricity; the per-unit capex wall unreachable by 3x to 7x; the project wall doubled from USD 100 M to about USD 200 M of break-even cap by the shadow-per-load design, the mission lane's method); the microbench of 20 probes documented as built (section 18); the owed list.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 21:26:19 +00:00
igneum-labs
30c2d2211f Counter ASIC 4.0 research: clock stamps in UTC (the box compile at 20:48 UTC, the knee reading at 20:5x UTC) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 20:56:11 +00:00
igneum-labs
5abb666aea Counter ASIC 4.0 research: the identity that forbids a zero-premium chip lever, the ranked designs, and the SM-sparse worker variant 
docs/analysis/counter-asic-4-research.md (excluded from the public export): edge = (E_card + F) / (E_mem + k F); at zero premium the stored-dataset chip keeps E_card / E_mem, 3.6x on a 5090 locked at 1,400 MHz (measured card, modelled chip), about 2x at that card's idle-plus-memory bound, 1.7x on the M5 Max; class v5 at zero shadow leaves it at 5.1x to 9.1x; the shadow buys 2.1x at k = 1 for the measured 88 W (81.8 W at the knee) and turns against us below 1.8 pJ per op; per-card classes, the refresh as a cost, proof of useful work, memory shaping and the tensor block priced out with their arithmetic; ten designs ranked with the chip edge, the 5090 and 4070 premiums, the verifier cost, agent hours and what breaks each; the recommendation in five sentences; consequences per tier.

proto-cuda/nvrtc/worker.cpp: opt-in SM-sparse variants sp<N> and sp<N>-w<W> (a persistent grid of N blocks of W warps over the dispatch's nonces; the bound kernel rewritten at compile time with exact anchors into a unit function plus a wrapper of the kernel's name; made on demand by name, never in the default race; refused on variant-5 packs and with minBlocks). Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra, 22:48 UTC; exe sha256 ee8d0e70dd101f125f42c0c7cf07481a794ee18a1317acf68561b37ea18d72be; unrun on a card (the hash lane's PC 1 job run-ca4-pc1-ca4sparse-5090-20261007 is its first run).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 20:55:27 +00:00
igneum-labs
151e3d88ae Counter ASIC 3.0 status: sub-version 2's final verdict (55 of 64, nine one-site seeds), sub-version 3's first commit ddacfbd3, p23's localisation (an AND-mask idiom, 0.84 of uniform at site 7), the 0.3.22 cost lines 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:23:58 +00:00
igneum-labs
da915621ea Merge ca3-coord 48ca9ac7 into master (gate: green on 48ca9ac7, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:23:09 +00:00
igneum-labs
5b681643f6 Merge peer-directory b3187c91 into master (gate: green on b3187c91, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:22:24 +00:00
igneum-labs
48ca9ac726 Counter ASIC 3.0 status: the N15 drift fix done for 0.3.21 (numbering-fix d8bceca5) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:19:37 +00:00
igneum-labs
bdb96688d1 Merge ca3-coord 81d7a666 into master (gate: green on 81d7a666, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:19:01 +00:00
igneum-labs
b3187c91b0 Merge remote-tracking branch 'origin/master' into peer-directory 
# Conflicts:
#	infra/fast-time/fork-gate.mjs
#	infra/fast-time/override-60x.json
 2026-10-07 14:18:50 +00:00
igneum-labs
9d76a4b5ee Merge horizon a87a9c42 into master (gate: green on a87a9c42, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:17:38 +00:00
igneum-labs
81d7a66692 Counter ASIC 3.0 status: sub-version 3's build result (the bounds do not reach the class under the real dataset), the decision (0.3.21 byte 5, sub-version 3 for 0.3.22) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:15:26 +00:00
igneum-labs
3f8fef9b6f Merge ca3-coord 5f0fc19b into master (gate: green on 5f0fc19b, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:14:20 +00:00
igneum-labs
2cbdce6d4d Merge genesis-forward 7f624df3 into master (gate: green on 7f624df3, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:10:57 +00:00
igneum-labs
5f0fc19b03 Counter ASIC 3.0 status: AP-F8-3, the acceptance never ran the shadow block (the root of the residual classes), the sub-version 3 fix 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:10:46 +00:00
igneum-labs
14d9722466 Merge ca3-coord 1e0af8f2 into master (gate: green on 1e0af8f2, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:09:56 +00:00
igneum-labs
40b1f33134 Merge site-ui-5 ce8ad8ca into master (gate: green on ce8ad8ca, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:09:28 +00:00
igneum-labs
422f9fae6d Merge remote-tracking branch 'origin/master' into peer-directory 2026-10-07 14:07:42 +00:00
igneum-labs
1e0af8f266 Counter ASIC 3.0 status: main's acceptance of the plan, AP-F8-2's exhaustion half closed at 10^6, the exec chain-number drift finding (N15) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:06:58 +00:00
igneum-labs
ce8ad8ca66 site-ui-5: /live sizes its scene box through the renderer (2.0.4 autoHeight, cd4f17b7); the padding constants leave the page. The home fold keeps its CSS height (a backdrop), so autoHeight stays off there by the renderer's own rule. 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:06:56 +00:00
igneum-labs
7f624df375 Merge branch 'master' of https://github.com/igneum-network/igneum into genesis-forward 2026-10-07 14:06:24 +00:00
igneum-labs
a87a9c423a Merge remote-tracking branch 'origin/master' into horizon 2026-10-07 14:05:21 +00:00
igneum-labs
a6fba517d5 Counter ASIC 3.0 status: the hot-set gate in numbers (ratio_w, the reach as per-site index entropy, the null's tail), the line for sub-version 3 (distinct-values bound at 2^20 plus the repeat bound) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:04:00 +00:00
igneum-labs
bee63dab06 Merge ca3-coord 2a41d491 into master (gate: green on 2a41d491, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:02:29 +00:00
igneum-labs
efd60ea938 Genesis forward-compatibility: key hashes in the harness summaries cut to 16 hex characters (the no-secrets gate reads committed summaries; the writer redacts at write time) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:02:24 +00:00
igneum-labs
e5de1b0400 Merge ship-docs-0320 2fa15d7e into master (gate: green on 2fa15d7e, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:01:33 +00:00
igneum-labs
db82208a54 Genesis forward-compatibility: the suite row closed (114 passed twice on build-2 at f95178a1) and section 6a, the two-node UnexpectedDifficulty class found and fixed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:01:11 +00:00
igneum-labs
127433d5fa Merge site-ui-5 7a7a987b into master (gate: green on 7a7a987b, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 14:01:01 +00:00
igneum-labs
2a41d4914c Counter ASIC 3.0 status: the self-operand ban void (value equality from the shadow block), the dynamic bound's reach, the plan (0.3.21 on byte 5, sub-version 3 against a defined gate), 0.3.21's staging facts 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 14:00:44 +00:00
igneum-labs
7a7a987bb6 site-ui-5: the capture set, every route at 390 and 1440, dark and light, rendered on igneum-build-2 against the live feed (docs/plans/site-ui-5-shots, 80 PNGs) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 13:59:11 +00:00
igneum-labs
fedff4f7a4 Counter ASIC 3.0 status: sub-version 2's eight seeds (five lineage-fresh constants, three the null's tail), the exhaustion half passing, the gate threshold question, the sub-version 3 shape and clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 13:57:43 +00:00
igneum-labs
2fa15d7ea5 release plans and rules on master: the 0.3.20 plan (sections 1 to 37, the pin c4459193 and its lines), docs/plans/release-rules.md (rules 1 to 13 with 4a, 4b, 4c), the 0.3.21 plan as staged 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 13:57:35 +00:00
igneum-labs
9926cb8188 Mission items 4 and 12 status: the live digest eada4bda read on the hub's file from both branch binaries (unchanged) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 13:56:48 +00:00
igneum-labs
91194f0492 Mission items 4 and 12 status: the 0.3.21 rebase tips (437f0438, 2e32d5f6), suite lines, the digest reading 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 13:55:34 +00:00
igneum-labs
3d67fa10fc Counter ASIC 3.0 status: the 64-seed gate on sub-version 2 heading to FAIL (8 of 39 over 1.2x, worst 4.82x), the earlier none-over line withdrawn 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 13:55:27 +00:00
igneum-labs
45bec67062 Counter ASIC 3.0 status: the wipe canary on c4459193 PASS (c19-1, the restart stopping at once); the pin's set complete bar CASES END 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 13:52:36 +00:00