igneum-labs
b8f8105af4
evidence.md: the card-lifetime claim as a designed row under the step schedule
2026-10-05 20:51:38 +00:00
igneum-labs
4a7b72da9b
Litepaper hardware line on the step schedule; status 20:51: public copy applied, level 1 and the limits bullet wait for the chip row
2026-10-05 20:51:26 +00:00
igneum-labs
949c4582e1
Counter ASIC 2.0 status: readwidth head hash corrected to 06dcb31
2026-10-05 20:50:30 +00:00
igneum-labs
4f042f37dc
Counter ASIC 2.0 status 20:50: the measure lock holder, the with-lock status defect
2026-10-05 20:50:05 +00:00
igneum-labs
4a1f872cb6
Counter ASIC 2.0 status 20:49: mixer construction, the lock cleared, PC 2 state, one merged-tree suite job
2026-10-05 20:49:39 +00:00
igneum-labs
27471633c7
Counter ASIC 2.0 status: heading times 20:42 to 20:47 corrected to the commit clock
2026-10-05 20:48:20 +00:00
igneum-labs
9343d96a98
Counter ASIC 2.0 status 21:15: the Sonnet box off the link, PC 1 facts corrected, the queue
2026-10-05 20:47:57 +00:00
igneum-labs
c8f0fe7472
Counter ASIC 2.0: the G1 ruling (gfx1036 as the AMD vendor tonight), hardware events section for the morning
2026-10-05 20:46:20 +00:00
igneum-labs
fbeb3bb94d
Counter ASIC 2.0 status 21:05: the 9070 XT absent on PC 1, app restart facts, era package ETA
2026-10-05 20:45:35 +00:00
igneum-labs
878c0581ef
Counter ASIC 2.0 status 21:00: the Metal pack path, the --prepare-packs app item, the seam signatures, the build queue
2026-10-05 20:44:16 +00:00
igneum-labs
0e337349d0
Counter ASIC 2.0 rollout: the rig miners' exit-42 path on the next-cut list as a layer 9 precondition
2026-10-05 20:42:03 +00:00
igneum-labs
3e3b12b505
Counter ASIC 2.0: C18 per-pound correction struck everywhere, C19 and C20 routed
2026-10-05 20:41:50 +00:00
igneum-labs
3f9bf60576
Counter ASIC 2.0 status 20:45: the node switch written, the Metal worker gate item, PC 1 gaps
2026-10-05 20:41:37 +00:00
igneum-labs
33713368b6
Counter ASIC 2.0 status: heading times corrected to the commit clock (UTC)
2026-10-05 20:41:03 +00:00
igneum-labs
7f3201f533
Counter ASIC 2.0: rig-install follow-ups on the next-cut list, the CPU fixture in the PC 1 gap, no more agents
2026-10-05 20:39:44 +00:00
igneum-labs
9dcb9697cf
Counter ASIC 2.0 status 23:20: the PC 1 queue
2026-10-05 20:39:03 +00:00
igneum-labs
4ce31bbbe0
Counter ASIC 2.0 status 23:10: layer 7 PC rows, PC 1 free
2026-10-05 20:38:08 +00:00
igneum-labs
3f33c6fd00
Counter ASIC 2.0 status 23:00: layer 9 agent, PC queues
2026-10-05 20:32:53 +00:00
igneum-labs
770145f7be
Counter ASIC 2.0: card lifetime merged, cache freed after the build, growth mapping (b) recommended, public lines listed
2026-10-05 20:31:48 +00:00
igneum-labs
fa5a69148b
Merge branch 'card-lifetime' into ca2-coord
2026-10-05 20:31:25 +00:00
igneum-labs
99ab478f1e
docs/analysis/card-lifetime-2026-10-05.md: years each card tier keeps mining under the dataset schedule and the working-set rule, against the site and litepaper claims
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:30:46 +00:00
igneum-labs
efeab4b23d
Counter ASIC 2.0 rollout: ota-k2 commit on the next-cut list
2026-10-05 20:29:37 +00:00
igneum-labs
35b3e38d2a
Counter ASIC 2.0 status 22:40: C1 decision and the 16:00Z check, one packfile.h fix
2026-10-05 20:29:09 +00:00
igneum-labs
724c5eee37
Counter ASIC 2.0: layer 9 row, C1 constraint, era mid-way and the attempt-aware packfile bug, C10 and C11 answers
2026-10-05 20:27:58 +00:00
igneum-labs
fff1994c8a
Counter ASIC 2.0: layers 1, 2, 3 decided from the readwidth table, layer 5 Mac rows and the added-form redesign, user tiers, public level 2 edit
2026-10-05 20:27:01 +00:00
igneum-labs
6a9b7c1283
Counter ASIC 2.0: the mixer x4 decision into v3, ca2-mixer agent, status 22:00
2026-10-05 20:27:01 +00:00
igneum-labs
f4fc651512
Counter ASIC 2.0: layer 3 decided (scratch share 0, chip 2.4x at every share), the claim qualified, public level 3 headline
2026-10-05 20:27:01 +00:00
igneum-labs
5c3a35c6de
Counter ASIC 2.0 status 21:35: the corrected SRAM mirror table
2026-10-05 20:27:01 +00:00
igneum-labs
bcb3f20bd9
Counter ASIC 2.0 status 21:25: proving v1 state, PC 2 queue
2026-10-05 20:27:01 +00:00
igneum-labs
cbbc81f002
Counter ASIC 2.0: the shipped-density correction to the SRAM mirror (130 to 165 mm^2), carried into the rollout and public docs
2026-10-05 20:27:01 +00:00
igneum-labs
b258094890
Counter ASIC 2.0: layer 6 option C and layer 7 R1 decided (delegated), the chip headline rule for the scratch share
2026-10-05 20:27:01 +00:00
igneum-labs
ece48696f3
Counter ASIC 2.0 status 20:55: layers 6 and 7, node agent, 0.3.11 scope with proving v1
2026-10-05 20:27:01 +00:00
igneum-labs
002c455eaa
Counter ASIC 2.0 status: the four-level public description deliverable
2026-10-05 20:27:01 +00:00
igneum-labs
7262df1964
Counter ASIC: the public description in four levels (levels 1 and 2 as copy, 3 and 4 with owed markers)
2026-10-05 20:27:01 +00:00
igneum-labs
1509a2c477
Counter ASIC 2.0 status 20:35: readwidth round 2, probe ceilings, width arithmetic
2026-10-05 20:27:01 +00:00
igneum-labs
045e8e5708
Counter ASIC 2.0 status 20:25: 0.3.10 blocked on GitHub, node fork convention, 0.3.11 inputs
2026-10-05 20:27:01 +00:00
igneum-labs
4b11f3a0cb
Counter ASIC 2.0 status 20:15: the devnet mandate, gates, node path note
2026-10-05 20:27:01 +00:00
igneum-labs
34ba9cd92e
Counter ASIC 2.0 rollout: the project lead's devnet decision rules, the six gates, the 0.3.11 release path
2026-10-05 20:27:01 +00:00
igneum-labs
b3b935f69f
Counter ASIC 2.0 status 20:05: readwidth PC jobs, the capped-scratch finding
2026-10-05 20:27:01 +00:00
igneum-labs
8988f9e03c
Counter ASIC 2.0: rollout plan draft (program_class_v3 height switch, digest first, decisions table)
2026-10-05 20:27:00 +00:00
igneum-labs
14303e9bf8
Counter ASIC 2.0 status: agents respawned, first readwidth Mac rows
2026-10-05 20:27:00 +00:00
igneum-labs
68e9c9fd29
Counter ASIC 2.0 status: restart after the credit cut-off, the 6 GB working-set budget
2026-10-05 20:27:00 +00:00
igneum-labs
578a903b36
Counter ASIC 2.0: coordinator status file, first entry
2026-10-05 20:27:00 +00:00
igneum-labs
2d04a1c553
read-width: bench-log entry and docs/plans/read-width.md (three cards, probes, widths, the per-load mix, the scratch at 32 and 128 KiB, chip model, recommendation: keep v2; w16 the only width that passes the rules and closes nothing); test multiply made wrapping (dev-profile overflow check)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:24:40 +00:00
igneum-labs
52d9a110be
docs: Counter ASIC 2.0, the second set of chip-resistance layers and the plan to measure and decide them
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 19:40:33 +00:00
igneum-labs
e0fce822b6
docs/plans/explorer.md: Etherscan, Blockscout and Otterscan compared, Blockscout's requirements against the fork's RPC, the recommendation, the load and supply measurements, the pool item; screenshots
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 19:35:40 +00:00
igneum-labs
48d987cfb4
Public stats API: /api/stats and /api/supply, documented with live examples, contract test and a live check
...
The numbers profitability sites and pool software read (WhatToMine's form: explorer or pool with an API, the halving
schedule, a source for total coins). Reward and supply from the emission rule at the node's DAA score; the halving table
(33 rows), the 30-day ramp and the observer's coinbase check. Cached 10 s, CORS open. FIELDS in each handler is the
contract; public-stats.test.mjs checks it from a fixture, tools/ci/public-api-check.mjs checks a deployment.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 19:35:40 +00:00
igneum-labs
995769d0e6
finality-v3-devnet-publish.md: the app nodes, the sweep (every live node on 1f4b4425), the Mac app's external-node finding, the checkpoint read
2026-10-05 18:19:03 +00:00
igneum-labs
2260a43053
docs/plans/finality-v3-devnet-publish.md: N3 = 135,200, digest 1f4b4425, the hand nodes, the seed and the three manifests
2026-10-05 18:09:05 +00:00
igneum-labs
135f67ab2a
Merge remote-tracking branch 'origin/master' into release-0.3.9
2026-10-05 17:55:57 +00:00