igneum-labs
8b3b9cbd2e
class v5 harness: the attempt-3 read's standalone path (--a3-only, --a3-known-failed) and the runner's stdout line; the check's live EQUAL on the rebuilt pair and the known-failed DIFFER on the page with the logs
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:18:19 +00:00
igneum-labs
2b34c7c8a4
class v5 harness: the pairing rule's fixed attempt-3 seed read on every run (kaspa-pow program-id beside the run's CLI, attempt and id against the record; an unreadable side fails the check); the seed's inputs pinned under the harness dir; the page row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:09:23 +00:00
igneum-labs
c8b65c08ff
class v5 design page: the pin's FAIL seed re-read (the freeze draws 1f1cf82877f46ee6 at attempt 3; both FAIL ids were foreign crates; the seeded attempt-3 case next)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:01:28 +00:00
igneum-labs
3af0a6a7b4
Merge remote-tracking branch 'build/master' into class-v5
2026-10-08 12:57:31 +00:00
igneum-labs
b1cbcec0a6
class v5 design page: the pairing read-back on the rebuilt 0.3.25 pair (PASS, id for id on epochs 8 to 10 against the freeze CLI at exactly f2267bb6; no attempt-3 seed in the run, the seeded case next), the logs
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:57:30 +00:00
igneum-labs
53f1e65b7f
Merge class-v6-floor-sram-docs 8c201157 into master (gate: green on 8c201157, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:55:14 +00:00
igneum-labs
de2a7e43e2
Merge ca3-coord-record bbb7bfcb into master (gate: green on bbb7bfcb, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:54:19 +00:00
igneum-labs
bbb7bfcb32
Counter ASIC 3.0 status: the STOP on the pin at 13:29 (the fast-time pairing FAIL on an attempt-3 seed), its cause (the 0.3.25 worktree's pre-freeze igneum-pow copy under the paths override; the live network fingerprinted ON the freeze, cbc5bd0a), rule 19 (the build-time fingerprint refusal, packaging/pow-freeze.txt), the rebuilt shas 6ccaf9e9 and c9ad753a with the 90,000 ceiling and digest 2066aa57, the testnet re-cut 3ffcf83b, lane D's fan-out, the attack pass's twelve-chunk split, the explorer re-pointed at node1-dn3 and the 4464 chain id served, the counter-asic-4 docs landing 2db1ba3b
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:47:21 +00:00
igneum-labs
b891188261
Merge build/master into build-programme (the 4464 fact landed on both sides; this branch's wording and the second PASS line kept; the pages rebuilt)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:46:10 +00:00
igneum-labs
9a794fa2d5
Merge spec-accept-23 8b9fb311 into master (gate: green on 8b9fb311, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 12:39:06 +00:00
igneum-labs
e15464ac58
Builder pages and faucet: Devnet 3 chain id 4464 since the class v5 floor (8 October 2026, 13:27 BST reading)
...
- the faucet reads eth_chainId from its node on every send and in its status (a fixed id signed refused transactions once the floor crossed); FAUCET_CHAIN_ID is gone from the env; the faucet now reads node1-dn3's EVM, the node the public RPC fronts
- /build, /faucet, docs/build/first-contract.md, rpc.md and faucet.md: 4464 with the floor note, "read it, never fix it"
- a second walkthrough PASS on the 4464 chain from build-2 through the public RPC and faucet: Counter at block 29878, 12 s end to end
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:38:51 +00:00
igneum-labs
0d172a1af5
Merge dex-devnet3 319d63f4 into master (gate: green on 319d63f4, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:37:18 +00:00
igneum-labs
909eec84f4
class v5 design page: the 0.3.25 pin's pairing STOP (the attempt-3 seed divergence, the embedded crate path), the pairing rule's attempt-3 line, the read-back plan
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:36:47 +00:00
igneum-labs
2db1ba3b07
Merge counter-asic-4-docs 0e23ca3f into master (gate: green on 0e23ca3f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:35:08 +00:00
igneum-labs
8b9fb311c7
Devnet 3's chain id is 4464 since its class v5 floor crossed at DAA 68,400 on 8 October 2026 (eth_chainId 0x1170 on the public RPC): /metamask's devnet card, by-hand list, builders' snippet and one-click entry (chainId 0x1170, rpcUrls the public RPC, the explorer as block explorer; the local node named beside it), /faucet's two lines, the build pages' network table and walkthrough notes (docs/build), the nav pill's title on every page
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:32:22 +00:00
igneum-labs
319d63f4d9
Swap page: the chain id read from eth_chainId at load (4464 from the class v5 floor at DAA 68,400, 4463 before it), never fixed in the page; devnet-3.json notes both
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:30:51 +00:00
igneum-labs
8c201157c1
Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
6a1943efc0
Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
d057c76304
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
783f8fb664
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
de85e8f848
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
75430525e7
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
0e23ca3f89
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
270aebfc9b
Class v6: the last two 20:00 and 19:30 references pulled to the close
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 086411627 (counter-asic-4) for the box mirror master
2026-10-08 12:28:21 +00:00
igneum-labs
aae3ef5246
Class v6: the coordinator's 13:30 UK clocks (floor rows by 15:30, the synthesis on master by 16:30; the decision stays the founder's)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 931798ead
2026-10-08 12:28:21 +00:00
igneum-labs
ebe0467309
Class v6 10.1: the 5090 SM ladder on four rented hosts (the ceiling held to 43 of 170 SMs, the occupancy 1.3 to 3.9 percent at best), the H100 power decomposition, the fraction a chip cannot strip per tier
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f21f256a0
2026-10-08 12:28:21 +00:00
igneum-labs
105fa65d5e
Class v6 10.4: the honest denominator per tier (floor lane 4: the 16 GB Blackwell card at its knee is the honest NVIDIA floor, the 5080 2.06 measured; the only lever the operating point; the Ember tier table); the close table gains the 5080 row
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9629fd8db
2026-10-08 12:28:21 +00:00
igneum-labs
f2b13d062f
Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b351f3fdf
2026-10-08 12:28:21 +00:00
igneum-labs
1cbf16eb37
Class v6: 10.1 SM-sparse measured dead on the 4090, H100 and 5090 (the residual is the clock domain); lane 3's close rows (the capex wall on the corrected project floor: USD 23 M and 340 M a year; W = 16 per chip; the SRAM rows on the synthesised core); 10.0 carries them with the 4090 and H100 rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 00890f9cc
2026-10-08 12:28:21 +00:00
igneum-labs
cbaa34c9ff
Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f0146c2c2
2026-10-08 12:28:21 +00:00
igneum-labs
d4d2ac5791
Class v6: 10.5 invention lane's KEEP/KILL table (the second sector conditional on the w64 job; everything else killed with its number); 10.2 reframed as per-unit floors with the sequencer-core row owed as the headline and k 0.5 the default; lane D's complete lossy curve and ring-C progress in 5.1b
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 89ea64861
2026-10-08 12:28:20 +00:00
igneum-labs
62ccca7d3b
Class v6 10.2: the shadow's k from RTL (floor lane 2: k 0.18 at the lock at N3 absolute, a floor; the GDDR7 chip with the class v4 shadow 4.0x at the knee and 5.8x at stock against the served 2.1x; mulhi the worst lever on the card by 6x); the lead and the served-line review carry it
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 4e7bac031
2026-10-08 12:28:20 +00:00
igneum-labs
13a8ae3159
Class v6 layer 4: lane D's 17:00 cut as 5.1b (24,000 drawn eras: the op-mix band's known-failed test reads 0 of 3,000 under the cap; the lossy curve's edge at +2 to +3; the (c''') per-width calibration; the bit-R bias law; the measured bound n)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of dd692978a
2026-10-08 12:28:20 +00:00
igneum-labs
1dd00f838c
Class v6 layer 1: kit c, the multiply-heavy base table measured (three tables within 7 W unlocked and 0.6 W at the lock on the 5090)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 3f6ee5878
2026-10-08 12:28:20 +00:00
igneum-labs
d0968f6703
Class v6 10.3: the SRAM die's lock rows in both conventions, absolute first (2.0x at k 1, 3.7x to 4.0x at k 0.5, every read width; floor lane 3 d550dadd)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1bce62079
2026-10-08 12:28:20 +00:00
igneum-labs
65ef3ebcf3
Class v6: the k convention rule for the floor and the served-line review (absolute rows the headline, the record's beside them marked; the k lane's rows re-fold lane 3's shadowed rows before the close)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ac0fe332f
2026-10-08 12:28:20 +00:00
igneum-labs
ef1f5ee8b7
Class v6: kit b rows (the mixer draw costs the card nothing, measured; the shuffle-heavy base table 7 W under stock; the 5090 at the knee pays 4 / 8 / 10 percent more energy per hash at 2 / 4 / 8 GiB, replacing size-independent); floor lane 3's W = 8 and k-convention update
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 91cb431a9
2026-10-08 12:28:20 +00:00
igneum-labs
b1cabb8b37
Class v6: 10.3 the SRAM die and the dataset floor (floor lane 3: the read width the only wire lever, 66x at 4 bytes at zero shadow, the shadow the whole hold at 2.7x to 3.0x at k = 1; W pinned at 4 words at genesis; the floor as a ticket, 5.5 / 8.5 / 11.5 GiB; the capex wall's p* table)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 78457959f
2026-10-08 12:28:19 +00:00
igneum-labs
074509e874
Class v6: section 10, the floor (the five floor lanes' terms, what the document already holds measured for each, the default at 19:30 and the row owed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5b7e219da
2026-10-08 12:28:19 +00:00
igneum-labs
7835d342a2
Class v6: the sound per-load form's 5090 rows measured (shl4096x1 at class v4's count: 116 W over class v3 against the whole block's 152 unlocked, 59 against 84 at the knee; shl2304x3 19 W and 6.6 W over the whole block)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a10fa0d5e
2026-10-08 12:28:19 +00:00
igneum-labs
ac94670313
Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 77be72c11
2026-10-08 12:28:19 +00:00
igneum-labs
8fe7a731cd
Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d8b2e2ee6
2026-10-08 12:28:19 +00:00
igneum-labs
321184e321
Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 837576edc
2026-10-08 12:28:19 +00:00
igneum-labs
b9dc2dac42
Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0182c50dc
2026-10-08 12:28:18 +00:00
igneum-labs
f310ac4e86
Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8}
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of be1ff694c
2026-10-08 12:28:18 +00:00
igneum-labs
441a2b89b7
Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a07d69371
2026-10-08 12:28:18 +00:00
igneum-labs
12d36b2208
Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e458519a3
2026-10-08 12:28:18 +00:00
igneum-labs
424596d046
Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2fc3377cd
2026-10-08 12:28:18 +00:00
igneum-labs
070d319ce6
Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 93a5e401b
2026-10-08 12:28:18 +00:00
igneum-labs
f5f34eb36e
Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 963235c7c
2026-10-08 12:28:18 +00:00
