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Author SHA1 Message Date
igneum-josh
7ddb8f44bd Spec 01 1.4.5 and 1.4.6: generator 3, the class and era seed in the pack and on the job line, the refusal rule 2026-10-05 20:53:26 +00:00
igneum-josh
8d6a641139 Counter ASIC 2.0 status 20:53: spec text applied for layers 6, 7, 9; what still lands from the branches 2026-10-05 20:53:12 +00:00
igneum-josh
9b1f8495d0 Spec 01 and 04: layer 9 epoch_len (1.12, 1.13.1, 4.3), reserve family R1 and the emulation rule (1.13.2), the cache growth rule option C and the step mapping (1.13.3), the mixer_mult row 2026-10-05 20:52:58 +00:00
igneum-josh
c9941ca8b6 Counter ASIC 2.0 status 20:51: chain_dataset_day wired in the node, evidence row 22 2026-10-05 20:51:52 +00:00
igneum-josh
3dc29fe3a1 evidence.md: the card-lifetime claim as a designed row under the step schedule 2026-10-05 20:51:38 +00:00
igneum-josh
3758b56088 Litepaper hardware line on the step schedule; status 20:51: public copy applied, level 1 and the limits bullet wait for the chip row 2026-10-05 20:51:26 +00:00
igneum-josh
3233588bd7 Counter ASIC 2.0 status: readwidth head hash corrected to 30ff674 2026-10-05 21:50:30 +01:00
igneum-josh
432068c222 Counter ASIC 2.0 status 20:50: the measure lock holder, the with-lock status defect 2026-10-05 20:50:05 +00:00
igneum-josh
75336388c7 Counter ASIC 2.0 status 20:49: mixer construction, the lock cleared, PC 2 state, one merged-tree suite job 2026-10-05 20:49:39 +00:00
igneum-josh
42f861ce48 Counter ASIC 2.0 status: heading times 20:42 to 20:47 corrected to the commit clock 2026-10-05 20:48:20 +00:00
igneum-josh
97e3611cc7 Counter ASIC 2.0 status 21:15: the Sonnet box off the link, PC 1 facts corrected, the queue 2026-10-05 20:47:57 +00:00
igneum-josh
dc4863748f Counter ASIC 2.0: the G1 ruling (gfx1036 as the AMD vendor tonight), hardware events section for the morning 2026-10-05 20:46:20 +00:00
igneum-josh
65dafce979 Counter ASIC 2.0 status 21:05: the 9070 XT absent on PC 1, app restart facts, era package ETA 2026-10-05 20:45:35 +00:00
igneum-josh
1d5e0c8785 Counter ASIC 2.0 status 21:00: the Metal pack path, the --prepare-packs app item, the seam signatures, the build queue 2026-10-05 20:44:16 +00:00
igneum-josh
50b3e8edbb Counter ASIC 2.0 rollout: the rig miners' exit-42 path on the next-cut list as a layer 9 precondition 2026-10-05 20:42:03 +00:00
igneum-josh
6b07776cd2 Counter ASIC 2.0: C18 per-pound correction struck everywhere, C19 and C20 routed 2026-10-05 20:41:50 +00:00
igneum-josh
622c93a237 Counter ASIC 2.0 status 20:45: the node switch written, the Metal worker gate item, PC 1 gaps 2026-10-05 20:41:37 +00:00
igneum-josh
4a293103fc Counter ASIC 2.0 status: heading times corrected to the commit clock (UTC) 2026-10-05 20:41:03 +00:00
igneum-josh
710b4dfbed Counter ASIC 2.0: rig-install follow-ups on the next-cut list, the CPU fixture in the PC 1 gap, no more agents 2026-10-05 20:39:44 +00:00
igneum-josh
d0ce7b6b2f Counter ASIC 2.0 status 23:20: the PC 1 queue 2026-10-05 20:39:03 +00:00
igneum-josh
49dc21360f Counter ASIC 2.0 status 23:10: layer 7 PC rows, PC 1 free 2026-10-05 20:38:08 +00:00
igneum-josh
c62ef08b0b Counter ASIC 2.0 status 23:00: layer 9 agent, PC queues 2026-10-05 20:32:53 +00:00
igneum-josh
db204381f2 Counter ASIC 2.0: card lifetime merged, cache freed after the build, growth mapping (b) recommended, public lines listed 2026-10-05 20:31:48 +00:00
igneum-josh
ab502a2378 Merge branch 'card-lifetime' into ca2-coord 2026-10-05 21:31:25 +01:00
igneum-josh
1fecfe26c4 docs/analysis/card-lifetime-2026-10-05.md: years each card tier keeps mining under the dataset schedule and the working-set rule, against the site and litepaper claims 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:30:46 +00:00
igneum-josh
7587570005 Counter ASIC 2.0 rollout: ota-k2 commit on the next-cut list 2026-10-05 20:29:37 +00:00
igneum-josh
e554d53de1 Counter ASIC 2.0 status 22:40: C1 decision and the 16:00Z check, one packfile.h fix 2026-10-05 20:29:09 +00:00
igneum-josh
7a0e8a2b78 Counter ASIC 2.0: layer 9 row, C1 constraint, era mid-way and the attempt-aware packfile bug, C10 and C11 answers 2026-10-05 20:27:58 +00:00
igneum-josh
ea323d97c5 Counter ASIC 2.0: layers 1, 2, 3 decided from the readwidth table, layer 5 Mac rows and the added-form redesign, user tiers, public level 2 edit 2026-10-05 20:27:01 +00:00
igneum-josh
4b550fa6d1 Counter ASIC 2.0: the mixer x4 decision into v3, ca2-mixer agent, status 22:00 2026-10-05 21:27:01 +01:00
igneum-josh
ff65d41dfc Counter ASIC 2.0: layer 3 decided (scratch share 0, chip 2.4x at every share), the claim qualified, public level 3 headline 2026-10-05 21:27:01 +01:00
igneum-josh
09e75e9ae9 Counter ASIC 2.0 status 21:35: the corrected SRAM mirror table 2026-10-05 21:27:01 +01:00
igneum-josh
adbf070ce0 Counter ASIC 2.0 status 21:25: proving v1 state, PC 2 queue 2026-10-05 21:27:01 +01:00
igneum-josh
874968a643 Counter ASIC 2.0: the shipped-density correction to the SRAM mirror (130 to 165 mm^2), carried into the rollout and public docs 2026-10-05 21:27:01 +01:00
igneum-josh
bdfb7a3467 Counter ASIC 2.0: layer 6 option C and layer 7 R1 decided (delegated), the chip headline rule for the scratch share 2026-10-05 21:27:01 +01:00
igneum-josh
38c113e957 Counter ASIC 2.0 status 20:55: layers 6 and 7, node agent, 0.3.11 scope with proving v1 2026-10-05 21:27:01 +01:00
igneum-josh
4d00935dbd Counter ASIC 2.0 status: the four-level public description deliverable 2026-10-05 21:27:01 +01:00
igneum-josh
7e6ad57433 Counter ASIC: the public description in four levels (levels 1 and 2 as copy, 3 and 4 with owed markers) 2026-10-05 21:27:01 +01:00
igneum-josh
1a651a06be Counter ASIC 2.0 status 20:35: readwidth round 2, probe ceilings, width arithmetic 2026-10-05 21:27:01 +01:00
igneum-josh
1e5502f88e Counter ASIC 2.0 status 20:25: 0.3.10 blocked on GitHub, node fork convention, 0.3.11 inputs 2026-10-05 21:27:01 +01:00
igneum-josh
652f2501a5 Counter ASIC 2.0 status 20:15: the devnet mandate, gates, node path note 2026-10-05 21:27:01 +01:00
igneum-josh
ad0b726325 Counter ASIC 2.0 rollout: Josh's devnet decision rules, the six gates, the 0.3.11 release path 2026-10-05 21:27:01 +01:00
igneum-josh
a7362c3cf6 Counter ASIC 2.0 status 20:05: readwidth PC jobs, the capped-scratch finding 2026-10-05 21:27:01 +01:00
igneum-josh
4a746e7fca Counter ASIC 2.0: rollout plan draft (program_class_v3 height switch, digest first, decisions table) 2026-10-05 21:27:00 +01:00
igneum-josh
dec14ca1b5 Counter ASIC 2.0 status: agents respawned, first readwidth Mac rows 2026-10-05 21:27:00 +01:00
igneum-josh
cf8490d000 Counter ASIC 2.0 status: restart after the credit cut-off, the 6 GB working-set budget 2026-10-05 21:27:00 +01:00
igneum-josh
c92b0fcc23 Counter ASIC 2.0: coordinator status file, first entry 2026-10-05 21:27:00 +01:00
igneum-josh
e752fc7d45 read-width: bench-log entry and docs/plans/read-width.md (three cards, probes, widths, the per-load mix, the scratch at 32 and 128 KiB, chip model, recommendation: keep v2; w16 the only width that passes the rules and closes nothing); test multiply made wrapping (dev-profile overflow check) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:24:40 +01:00
igneum-josh
be4b29507b docs: Counter ASIC 2.0, the second set of chip-resistance layers and the plan to measure and decide them 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 19:40:33 +00:00
igneum-josh
9746391242 docs/plans/explorer.md: Etherscan, Blockscout and Otterscan compared, Blockscout's requirements against the fork's RPC, the recommendation, the load and supply measurements, the pool item; screenshots 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:35:40 +01:00