2 commits

Author	SHA1	Message	Date
igneum-labs	16cfea717a	Counter ASIC 2.0 layer 6, revision 2: shipped cache-die density (AMD V-Cache 64 MB on 41 mm^2 at 7 nm, Hot Chips 33) as the headline column beside the bit-cell lower bound; mirror 106 to 164 mm^2 and $30 to $56 per die at 256 MiB; year 0 to 10, hot-table and option tables redone; latency citations section (MEMSYS 2018, Chang 2017, mining-chip memory types) ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>	2026-10-05 20:20:46 +00:00
igneum-labs	32944d12d4	Counter ASIC 2.0 layer 6: SRAM mirror analysis (cited bit cells N7 to N2 and 18A, area and cost per node, no cache growth rule in the spec, options A to E for the project lead); layer 7 dp4a probes for Metal, CUDA and OpenCL (standalone, no lottery kernel) ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>	2026-10-05 20:09:10 +00:00