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igneum-labs
73f2c0768e Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:19:15 +00:00
igneum-labs
650c2ad56a Class v6: 10.5 invention lane's KEEP/KILL table (the second sector conditional on the w64 job; everything else killed with its number); 10.2 reframed as per-unit floors with the sequencer-core row owed as the headline and k 0.5 the default; lane D's complete lossy curve and ring-C progress in 5.1b 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:17:42 +00:00
igneum-labs
fb93859c7d Class v6 10.2: the shadow's k from RTL (floor lane 2: k 0.18 at the lock at N3 absolute, a floor; the GDDR7 chip with the class v4 shadow 4.0x at the knee and 5.8x at stock against the served 2.1x; mulhi the worst lever on the card by 6x); the lead and the served-line review carry it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:15:47 +00:00
igneum-labs
a836fcf507 Class v6 layer 4: lane D's 17:00 cut as 5.1b (24,000 drawn eras: the op-mix band's known-failed test reads 0 of 3,000 under the cap; the lossy curve's edge at +2 to +3; the (c''') per-width calibration; the bit-R bias law; the measured bound n) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:14:25 +00:00
igneum-labs
3585efb9d0 Class v6 layer 1: kit c, the multiply-heavy base table measured (three tables within 7 W unlocked and 0.6 W at the lock on the 5090) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:13:02 +00:00
igneum-labs
fcea9a0dfa Class v6 10.3: the SRAM die's lock rows in both conventions, absolute first (2.0x at k 1, 3.7x to 4.0x at k 0.5, every read width; floor lane 3 d550dadd) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:10:23 +00:00
igneum-labs
afad20f1f5 Class v6: the k convention rule for the floor and the served-line review (absolute rows the headline, the record's beside them marked; the k lane's rows re-fold lane 3's shadowed rows before the close) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:08:18 +00:00
igneum-labs
1989495c13 Class v6: kit b rows (the mixer draw costs the card nothing, measured; the shuffle-heavy base table 7 W under stock; the 5090 at the knee pays 4 / 8 / 10 percent more energy per hash at 2 / 4 / 8 GiB, replacing size-independent); floor lane 3's W = 8 and k-convention update 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:07:08 +00:00
igneum-labs
7aa9f18987 Class v6: 10.3 the SRAM die and the dataset floor (floor lane 3: the read width the only wire lever, 66x at 4 bytes at zero shadow, the shadow the whole hold at 2.7x to 3.0x at k = 1; W pinned at 4 words at genesis; the floor as a ticket, 5.5 / 8.5 / 11.5 GiB; the capex wall's p* table) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:03:48 +00:00
igneum-labs
35e9600908 Class v6: section 10, the floor (the five floor lanes' terms, what the document already holds measured for each, the default at 19:30 and the row owed) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:49:10 +00:00
igneum-labs
6cc3bfec87 Class v6: the sound per-load form's 5090 rows measured (shl4096x1 at class v4's count: 116 W over class v3 against the whole block's 152 unlocked, 59 against 84 at the knee; shl2304x3 19 W and 6.6 W over the whole block) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:44:21 +00:00
igneum-labs
2ae69eb4d4 Merge build/master into counter-asic-4 (the sub-version 3 line, the derivation recorder, master's re-exported packs); chip-model 5.12; class v6 sections; the per-load bias test judges the window's bits only 
The merge: accept.rs takes master's shadow pass in run_unit (the per-load sub-blocks keep their place inside the loop; the end-of-iteration pass is empty for that class) and its Acc fields beside site_bit_ones; generator.rs records the per-load and tile id bytes through master's recorder (r.lit "perload", r.lit "mm8/" and the tiles field), nothing for the class v4 shape; export-exclude keeps both sides.

The fix (the invention lane's finding, 8 October 2026, 10:48 UTC): BiasedIndexBit judged every index bit, and under an era a narrow-window site's top k bits are fixed by design, so every per-load form read 0 of 256 under any drawn era for the instrument's reason; it now judges only the bits inside each site's window mask (verify::window) and the (c'') pass, which runs the unit with no table, accumulates nothing. The research file's 20.2a-close reads REOPENED (the 16 x 27 form dead on the no-era census on both instruments; the sound form mx8+shl4096x1 accepts 234 of 256 seeds no-era; its drawn-era verdict the invention lane's 15:00 BST read); chip-model-v3 5.11 the same.

chip-model-v3 5.12 (main's order, 11:3x UK): the 2 GiB SRAM full store on one N2 reticle (17x at zero shadow, 2.7x to 4.8x with it, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M) and the custom HBM4E base die (6.5x to 14x, untouched by the four layers), per-bank PIM's structural blindness, the M5 Max at 0.78 microjoules as the honest denominator; lane B's figures, labelled.

docs/design/class-v6-rotating-family.md: section 0's lead on the SRAM store, 0.1 the per-tier schedule table, layers 2 to 4 with lane A's priced schedule (5.5 / 8 / 11 GiB), lane D's three rings and the op-mix band (B = 4 on the injecting families, the lossy sum capped; 8 of 663 eras exhausting at the uncapped corner), the index fold as a layer-1 rule, the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB), the 5070 Ti stock pair, the x16 mixer rows with build-3's sibling-loaded method (11.4 ms, admissible false on the measurement), 7a lane B, 7b lane A, 7c lane C's layers 5 to 7, section 9 the served-line review for main's 20:00 word.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:32:09 +00:00
igneum-labs
8e15f35ae3 Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:27:47 +00:00
igneum-labs
fa8e742f67 Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:26:35 +00:00
igneum-labs
eb71eaf399 Merge class-v6-history 2b76937c into master (gate: green on 2b76937c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:26:13 +00:00
igneum-labs
fde5957287 Merge class-v6-hardware 93e55f9d into master (gate: green on 93e55f9d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:24:52 +00:00
igneum-labs
71f30fc806 Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:24:51 +00:00
igneum-labs
2b76937caf Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6 
docs/analysis/class-v6/history.md: 21 chip rows by mechanism (what each chip specialised, what the design missed, the timeline, the v6 layer, closed or not, the per-joule number); in-depth sections for Ethash (the E3's DDR3, Linzhi's 4.4 GB beside 64 compute units, the Jasminer X4's DRAM hybrid-bonded onto a 40/45 nm die, the E9), ProgPoW (the Least Authority and Rao audits read from the PDFs, Kik, Linzhi's claim, the adopters), RandomX (the X5's RISC-V board at 1.46x, the X9 announced December 2025 and withdrawn May 2026 with zero units, RandomX v2 released 25 March 2026 with activation pending, the Qubic episode as the detector's lesson), Cuckoo (the GRN1's 512 MiB SRAM die, the G32, the iPollo G1, the 2025 bounty), Equihash (the Z9's single die, the Fudan parameter-following design), Scrypt and Argon2 (the BM1485's on-die scratchpads, Percival's lookup gap, MTP), the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows. The four layers against the history layer by layer, with the E3's death dates, Autolykos's growth rule, the design-cycle and FPGA-compile clocks, and the honest verdict that the stored-dataset chip (class C) is not closed by any layer: 5.1x per joule at zero premium, 2.1x with the shadow at k = 1. Two corrections to the 5 October file (the X9, RandomX v2) and one claim marked unverified (the 5x fork-surviving chip). First cut for 15:00 UK; the full report by 09:00 UK on 9 October.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:19:10 +00:00
igneum-labs
93e55f9d43 Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file) 
docs/analysis/class-v6/hardware-future.md: one table over PIM and PNM (HBM-PIM, AiM, LPDDR5X-PIM, UPMEM), HBM3E, HBM4 and the custom HBM4E base die, fine-grained DRAM on logic, LPDDR6, 3D DRAM, RLDRAM 3 and Folded Banks, FPGA with HBM2e, wafer-scale, CXL, optical I/O, chiplets and UCIe, and SRAM at N2: energy per dependent read, latency, cost per GB, availability to a non-hyperscaler, the k_read and shadow k bands, the edge per joule at zero shadow against the 5090 and the M5 Max, and the one layer of the four that blunts each with a number. The three findings: a 2 GiB SRAM full store on one N2 reticle is the strongest five-year chip (13x to 17x per joule, about USD 0.3 per MH/s) and no layer reaches it (layer 2 moves its capex, not its joules; the shadow at k = 0.5 holds 4.8x); per-bank PIM is blind (1.6 percent of reads in-bank at 2 GiB) and the custom HBM4E base die is the f = 1 chip with its controller in the stack (6.5x to 14x), untouched by layers 1 to 4; the denominator is the wrong card (the M5 Max at 0.78 microjoules halves to thirds every chip edge). Section 5 carries the k bands for the research lane's chip rows; section 7 the four decisions with defaults and deadlines; section 9 the sources with URLs and dates. tools/ci/export-exclude.txt: docs/analysis/class-v6 is research, not public export.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:17:50 +00:00
igneum-labs
8fee73f29b Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:16:17 +00:00
igneum-labs
0d7ecc6432 Counter ASIC 3.0 status: the founder's load order on the four boxes and its placement (lane D's family sampling, the attack families at scale, lane C's packs, the pin matrix, the cross builds), the drift class settled by a fresh-walk node, the pin candidate e0644958 confirmed, the Windows installer class and the detach fix, the tiers' class-flip pair gated (081b3ba7), the rpc up, two reds on the release line from the first ten minutes of the load order (the missing 60x field; the detach's test literal) with their fixes and defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:14:50 +00:00
igneum-labs
029744b7e6 Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8} 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:14:50 +00:00
igneum-labs
91af4721e2 Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:12:47 +00:00
igneum-labs
04074f5bdc Merge ship-docs-0321 dea360cc into master (gate: green on dea360cc, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 10:12:42 +00:00
igneum-labs
d94c3e0716 Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:04:29 +00:00
igneum-labs
dea360cc65 release record section 24: the first lock on cc902690 (checkpoint 1931, 10:06:32 BST), the move's count and the three puller faults closed, 0.3.24 Windows take 2 (Inno stopped the app and copied nothing; the /IGNOTA=1 rule), 0.3.25 opened (tip 78dfe65e, the ceiling cut e0644958, digest 1b37cb9d, the DMG 501ba293 staged, the clock), the tiers at the class flip, the signed apps pipeline (Igneum Labs LLC) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:03:40 +00:00
igneum-labs
fe940213a6 Counter ASIC 3.0 status: the 0.3.25 pairs and app tip (78dfe65e on the ceiling cut e0644958, its fast-time PASS at 10:54), the tiers' class-flip UI half (d949e274), the four builder lanes and the class v6 declaration with its four research lanes spawned and the outline on the mirror, the Arc re-read and v5lock jobs live, the held-push cause (the branch's own hook predating the per-process fix) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:01:24 +00:00
igneum-labs
0467872a63 Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:00:21 +00:00
igneum-labs
d96faddae4 Counter ASIC 3.0 status: the 0.3.25 pairs on 7bd2940f and the re-pointed app tip 9b1ec8dc (every input green at 10:33 bar the pin's gates and the crossing), main's sweep finding (class v5 17 percent under v4 on a power-capped A4000; a knee-locked card may lose a few percent at the crossing until Ember re-tunes) and its two orders with their defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:48:45 +00:00
igneum-labs
25c0d75bab Counter ASIC 3.0 status: the 10:05 move's read-back (36 of 36 on the pin by 10:12, the first lock 10:06:32, carrying resumed; three fault classes named), the tiers gated (d3d0704a), the knob's tip e2962b89, the 0.3.25 app line assembled at 10:29 (e0d4425f), the node line's tip 7bd2940f with the one-shot gossip fix and the drift item reclassified 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:31:37 +00:00
igneum-labs
de551552dd Counter ASIC 3.0 status: the 0.3.25 plan (the shipper's), main's word (the tiers both halves, gated) and the founder's word (0.3.25 today: the app line by 12:30, the pin by 13:00, the move after the 68,400 crossing reads clean, about 13:30), card-in ready, the tiers' UI half merged, the second deploy (d12e0684), the node line placeable ahead of its minute (c6629572), the knob's tip e2962b89, the Hetzner boxes on the founder's word 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:20:01 +00:00
igneum-labs
01d2e123c0 Counter ASIC 3.0 status: the site deployed (1e21bbac at 10:00 BST), row 17's floor sentence and the Arc row restored (96c7c7db), the 0.3.25 node build's shape and main's word on the fee ceiling (no second object cut today), class-v5 8f481459 gated with the Intel fix, the per-process gh fix on master (12f6f9a8), the AMD knob for tonight's cut, the 0.3.24 move FIRED at 10:05:00 BST (the Mac entry and the hive live 10:08:35, the three nodes on the pin, class v5 at 68,400 about 12:54) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:11:58 +00:00
igneum-labs
8b0a5a8a40 release rules 11 extended (never a kill pattern the shell carries; a kept datadir's locks); release 0.3.22 section 23: the move executed, 0.3.24 Mac and HiveOS LIVE 10:08:35 BST, the Windows chain on PC 2 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:11:06 +00:00
igneum-labs
d12e0684c6 Merge ca3-coord-record 5ebeff23 into master (gate: green on 5ebeff23, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 09:07:55 +00:00
igneum-labs
5ebeff2342 Counter ASIC 3.0 status: the gh switch owned by the attack-pass lane and the rule to every lane, the Intel fix on master (7616ccd4), the pairs on the pin, class-v5 a55fcc10 and the rebuilt kit (65b47211), the AMD grid prepared, the AP-F8-1 record line (4026be32) and the card-in job, the in-house pass's last landing (1bf68cdf), the attack-pass tail (8a2fc793), the signal-15 hook note 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:01:49 +00:00
igneum-labs
96c7c7db7e Merge spec-accept-23 1ac664e3 into master (gate: green on 1ac664e3, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 08:59:34 +00:00
igneum-labs
1e21bbacea Merge ca3-coord-record d0ea857d into master (gate: green on d0ea857d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:58:40 +00:00
igneum-labs
8a2fc79398 Merge attack-pass 29239a22 into master (gate: green on 29239a22, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 08:55:29 +00:00
igneum-labs
1bf68cdf29 Merge crypto-engage f1c86098 into master (gate: green on f1c86098, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:54:42 +00:00
igneum-labs
4026be326d Merge ca3-v4-amend 8a63248c into master (gate: green on 8a63248c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:54:04 +00:00
igneum-labs
1ac664e3b6 Merge build/master 7616ccd4 into spec-accept-23 (the Intel rotr worker fix taken; /miners rebuilt from the merged bench data) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:52:59 +00:00
igneum-labs
d0ea857d77 Counter ASIC 3.0 status: the move's readings and the pin line on 5b673577, the founder's standing rule (defaults and deadlines; the shipper's clocks mirrored) and its distribution, the Arc self-test read (the shipped workers right, the kit lacking the Intel rotate fix), the AMD knob opened (a002732a), the F8 tail attributed on the Mac (a per-site bucket concentration), the fast-time PASS and the minute 10:05:00 BST, the gh exception on the Mac, adv-accept closed (BOUND, no BREAK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:51:32 +00:00
igneum-labs
9b057c02ed release 0.3.22: THE MINUTE 10:05 BST set in m5b67-1, the pairs and the hive on the pin, what moves at the minute 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:49:41 +00:00
igneum-labs
29239a2296 attack-pass: the status board, F8 row, gate line and re-gate paragraph read the tail as attributed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:49:21 +00:00
igneum-labs
f1c860983e in-house-pass.md: adv-accept closed (15.1 box-hours, 796,042 accepted programs, BOUND, no BREAK); the pass's totals final 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:48:22 +00:00
igneum-labs
7ac25503ed attack-pass: AP-F8-1 tail attributed (p4, p8, p10, p34 as per-site bucket concentration at a narrow-window site; the largest-bucket bound named for a next class) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:48:03 +00:00
igneum-labs
8a63248c68 ledger AP-F8-1: the four-seed tail attributed (8 October 2026 Mac read at 2^24): one narrow-window site per seed, a quarter-bit bucket concentration from a mad, xor or sub writer, no lossy source, no chip consequence; the per-site bucket bound is a morning item 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:47:41 +00:00
igneum-labs
33addc3f94 release 0.3.22 section 22: the morning (main's word, the founder's rule, the fifth cut 5b673577, the move staged, the fleet's reading, the Arc answer) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:46:22 +00:00
igneum-labs
645ddb2014 Counter ASIC 3.0 status: main's morning words (the look landed, the floor sentence to row 17, CA4 parked, the Mac rule lifted for the F8 tail, route (A) at 10:45 BST), the build-server lane's honest state and the deploy and pairs plan, the fourth cut 5b673577 (floor 68,400), the Arc B580's self-test fault on both classes and the Intel kit held out of 0.3.24, the design pass on master (d8459e79) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:40:46 +00:00
igneum-labs
ca5151eef5 Evidence row 17: the in-house pass's floor reading beside its sentence (nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test; measured 8 October 2026, ledger AP-F8-1 and AP-F8-6); /evidence rebuilt 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:33:21 +00:00