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346 commits

Author SHA1 Message Date
igneum-labs
7209999cae Counter ASIC 2.0 status 21:41: the era draw's Mac spread 0.8%, the final package, the merges 2026-10-05 21:41:42 +00:00
igneum-labs
b80e268222 Counter ASIC 2.0 status 21:41: the mixer timing session, x8 provisional 2026-10-05 21:41:15 +00:00
igneum-labs
2b89e00baa Counter ASIC 2.0 status 21:40: x8 built and bit-exact, the mixer PC job 2026-10-05 21:40:50 +00:00
igneum-labs
8228ec544d Counter ASIC 2.0: gate G4 run 1 PASS recorded; status 21:39 2026-10-05 21:39:01 +00:00
igneum-labs
32ed55bccc Counter ASIC 2.0 status 21:38: ca2-cache final 2de19e5 2026-10-05 21:38:34 +00:00
igneum-labs
d58e2cb05e Counter ASIC 2.0: layer 5 decided OUT on the PC rows; status 21:36 2026-10-05 21:36:30 +00:00
igneum-labs
eab7c54c69 Counter ASIC 2.0 status 21:34: PC 2 timing, the suites after the restart 2026-10-05 21:34:16 +00:00
igneum-labs
10421ff814 Counter ASIC 2.0: the iGPU restart-per-epoch statement, dataset reuse on the next-cut list, the gate's script fix; status 21:32 2026-10-05 21:32:35 +00:00
igneum-labs
255e1e3585 Counter ASIC 2.0 status 21:31: the runner recovered, the 0.3.10 rollout, the restart rule 2026-10-05 21:31:32 +00:00
igneum-labs
5a8f75d97f Counter ASIC 2.0 status 21:31: C23 and C24 2026-10-05 21:31:06 +00:00
igneum-labs
971a04475a Counter ASIC 2.0: the x8 refinement in the rollout plan; status 21:28: hot-table go, installer attempt 3 failed, PC 1 order 2026-10-05 21:28:07 +00:00
igneum-labs
f789fcee5f Counter ASIC 2.0: the x4/x8 decision rule recorded (delegated); status 21:27 2026-10-05 21:27:46 +00:00
igneum-labs
5814b5f92a Counter ASIC 2.0 status 21:27: installer attempt 3, the fast-failure rule 2026-10-05 21:27:00 +00:00
igneum-labs
aadd0787bf Counter ASIC 2.0: G6 state and the expected 0.3.11 digest; status 21:25 2026-10-05 21:25:28 +00:00
igneum-labs
1b8c273ff1 Counter ASIC 2.0 status 21:25: the mixer x4 bit-exact on the Mac, the chip row 1.84x, the hot table's effect on the row 2026-10-05 21:25:03 +00:00
igneum-labs
8abfe7afe3 Counter ASIC 2.0 status 21:24: the third eGPU drop, the miners are mining, the installer build running 2026-10-05 21:24:45 +00:00
igneum-labs
9447e13124 Counter ASIC 2.0 status 21:23: the era package, the V3_CLASS composition rule 2026-10-05 21:23:38 +00:00
igneum-labs
98dc15d65a Counter ASIC 2.0 status 21:23: the installer build republished, PC 1 order 2026-10-05 21:23:10 +00:00
igneum-labs
3bf95d793a Counter ASIC 2.0 status 21:22: the installer build job failed in 2 s, PC 1 decision pending 2026-10-05 21:22:37 +00:00
igneum-labs
bef07ba00a Counter ASIC 2.0 status 21:22: Ember Tune queued 2026-10-05 21:22:20 +00:00
igneum-labs
022c41a86e Counter ASIC 2.0 status 21:21: PC 2 to agg-cost-pc2-2 until 21:45, the PC 1 order 2026-10-05 21:21:27 +00:00
igneum-labs
45ac20d2fe Counter ASIC 2.0 status 21:20: the added-form hot table on the Mac, the decision rule for layer 5 2026-10-05 21:20:53 +00:00
igneum-labs
0ec5698785 Counter ASIC 2.0 status 21:20: layer 9 complete with the compile-ahead table and the floor 2026-10-05 21:20:25 +00:00
igneum-labs
ebbf2794a1 Counter ASIC 2.0: the proving v1 app branch final 6dc686a; the 0.3.11 tree composition; status 21:20 2026-10-05 21:20:13 +00:00
igneum-labs
db4b309b8f Counter ASIC 2.0 status 21:11: the 9070 XT back on the bus, PC 1 to the 0.3.10 build, the playbook parse-gate rule 2026-10-05 21:11:19 +00:00
igneum-labs
d34f69a537 Counter ASIC 2.0 status 21:05: the node merge ba43cf0f, the hot-table package, unproven_daa at fast time 2026-10-05 21:05:20 +00:00
igneum-labs
37e31bfefa Counter ASIC 2.0: proving v1 handoff recorded in the rollout plan; status 21:04 2026-10-05 21:04:35 +00:00
igneum-labs
d618926da8 Merge branch 'amd-prove' into ca2-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-05 21:03:58 +00:00
igneum-labs
2642f16998 docs/analysis/amd-proving.md: no zkVM proves on AMD (SP1, RISC Zero, Jolt, OpenVM, ICICLE cited), the SP1 CPU prover measured on PC 1 beside the miners (282 s a shard at any size, 30 GB RSS: no CPU tier), the tier consequences and the public line; PC 1 job scripts with the bash -n gate; bench-log entry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:02:59 +00:00
igneum-labs
3458355cec Counter ASIC 2.0 status 21:02: the measure lock convoy, found by lsof 2026-10-05 21:02:13 +00:00
igneum-labs
ab6a3fac59 Counter ASIC 2.0 status 21:01: the 0.3.10 installer build takes PC 1 after the repro run 2026-10-05 21:01:20 +00:00
igneum-labs
b15b3b84cc Counter ASIC 2.0 status 21:00: PC 1 to the repro run, PC 2 to agg-cost, the CPU fallback numbers, the S_p shard dropped 2026-10-05 21:00:58 +00:00
igneum-labs
78cf974b93 Counter ASIC 2.0 status 20:58: PC 1 and PC 2 occupancy 2026-10-05 20:58:57 +00:00
igneum-labs
f906991d0c Counter ASIC 2.0 status 20:57: the mixer construction committed, MX4 is V3_CLASS 2026-10-05 20:57:12 +00:00
igneum-labs
227186f790 Counter ASIC 2.0 status 20:56: PC 2 released, the proving fork tip, the S_p curve with the miner on 2026-10-05 20:56:23 +00:00
igneum-labs
b964c866b1 counter-asic-2.md: layer 9 row and the decisions table of 5 October 2026 (night) 2026-10-05 20:53:45 +00:00
igneum-labs
53f104298e Spec 01 1.4.5 and 1.4.6: generator 3, the class and era seed in the pack and on the job line, the refusal rule 2026-10-05 20:53:26 +00:00
igneum-labs
bc49229237 Counter ASIC 2.0 status 20:53: spec text applied for layers 6, 7, 9; what still lands from the branches 2026-10-05 20:53:12 +00:00
igneum-labs
c34af5f27d Spec 01 and 04: layer 9 epoch_len (1.12, 1.13.1, 4.3), reserve family R1 and the emulation rule (1.13.2), the cache growth rule option C and the step mapping (1.13.3), the mixer_mult row 2026-10-05 20:52:58 +00:00
igneum-labs
d0cb69288b Counter ASIC 2.0 status 20:51: chain_dataset_day wired in the node, evidence row 22 2026-10-05 20:51:52 +00:00
igneum-labs
3ac9114d1f evidence.md: the card-lifetime claim as a designed row under the step schedule 2026-10-05 20:51:38 +00:00
igneum-labs
00ded867a4 Litepaper hardware line on the step schedule; status 20:51: public copy applied, level 1 and the limits bullet wait for the chip row 2026-10-05 20:51:26 +00:00
igneum-labs
6d61cde831 Counter ASIC 2.0 status: readwidth head hash corrected to 05a5a9c 2026-10-05 20:50:30 +00:00
igneum-labs
844b2f38df Counter ASIC 2.0 status 20:50: the measure lock holder, the with-lock status defect 2026-10-05 20:50:05 +00:00
igneum-labs
dd7852065b Counter ASIC 2.0 status 20:49: mixer construction, the lock cleared, PC 2 state, one merged-tree suite job 2026-10-05 20:49:39 +00:00
igneum-labs
a7fa5766ff Counter ASIC 2.0 status: heading times 20:42 to 20:47 corrected to the commit clock 2026-10-05 20:48:20 +00:00
igneum-labs
f3f7ce9305 Counter ASIC 2.0 status 21:15: the Sonnet box off the link, PC 1 facts corrected, the queue 2026-10-05 20:47:57 +00:00
igneum-labs
d3f5acdc32 Counter ASIC 2.0: the G1 ruling (gfx1036 as the AMD vendor tonight), hardware events section for the morning 2026-10-05 20:46:20 +00:00
igneum-labs
cca6e10cd1 Counter ASIC 2.0 status 21:05: the 9070 XT absent on PC 1, app restart facts, era package ETA 2026-10-05 20:45:35 +00:00
igneum-labs
3ce4ad6661 Counter ASIC 2.0 status 21:00: the Metal pack path, the --prepare-packs app item, the seam signatures, the build queue 2026-10-05 20:44:16 +00:00