igneum-network/igneum
1
0
Fork 0
Code Issues Pull requests Releases Activity
937 commits 216 branches 0 tags 857 MiB
Commit graph

627 commits

Author SHA1 Message Date
igneum-labs
31814153ee Spec 01: class v3's mixer x8 form in 1.8.5 with the measured costs, the class v3 vectors in 1.17, the cache note in 1.5 2026-10-05 22:17:33 +00:00
igneum-labs
4fa1320a0a Counter ASIC 2.0: gate G6 green; status 22:16 2026-10-05 22:16:50 +00:00
igneum-labs
a6be364c87 Counter ASIC 2.0 status 22:16: the 5090 power sweep, the G2 job go 2026-10-05 22:16:15 +00:00
igneum-labs
37dab3f5a5 counter-asic-2-node.md: the verifier before/after table (the mixer fix), class v3 = x8, the merges and checks on d5070e7 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:15:18 +00:00
igneum-labs
0f82258d7d Counter ASIC 2.0: the final-vectors package, the bash-body-check branch in the 0.3.11 tree; status 22:15 2026-10-05 22:15:07 +00:00
igneum-labs
6bbe8fbdb4 Consequences ledger: C24 and C27 closed on branch bash-body-check (7adb1ca, 6805125) with the merge notes 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:14:37 +00:00
igneum-labs
271db8e5ac Counter ASIC 2.0 status 22:13: suite job 4 published on the final tree 2026-10-05 22:13:25 +00:00
igneum-labs
199c974f3d Counter ASIC 2.0: the verifier fix and the x8 class committed; status 22:11 2026-10-05 22:11:49 +00:00
igneum-labs
d5070e744d Merge branch 'ca2-mixer' into ca2-v3 2026-10-05 22:11:29 +00:00
igneum-labs
1402989cdd Prover floor: SP1 6.8.1 GPU server memory model from source (the 24 GB panic, the threshold-sized trace buffers), the floor patch for sp1-gpu, the PC 2 toolchain, build and sweep playbooks 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:11:24 +00:00
igneum-labs
615837dbd0 Counter ASIC 2.0 status 22:11: the toolchain check, the build held behind job 4, C26 and C27 2026-10-05 22:11:10 +00:00
igneum-labs
ac2a4f9862 Consequences ledger: C26 taken into the proving plan 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:11:05 +00:00
igneum-labs
e041fb5e73 plan: the self-built CUDA server's packaging row before 0.3.12 (arch list, builder, signing, DMG and WSL2 placement, evidence note, rebuild at each SP1 upgrade, the verifying keys unchanged) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:10:55 +00:00
igneum-labs
9597374c4d verifier regression of e08909f fixed (derive_items out of line, one instance per cache size with the line mask a constant: v2 0.609 ms per unit against readwidth's 0.607, was 1.33); x8 into class v3 under the delegated rule (V3_CLASS = MX8; mx8-genesis and mx8-devnet-epoch0 re-exported through the seam, the devnet one with the era inside; the mx4 packs kept as the x4 record, generator 2); tests/packs.rs and tests/mixer.rs on the x8 class; mixer-x4.md 6.2a, 6.4a, 6.5 decision, 6.6 the regression; chip-model-v3.md headline x8 (0.92x with the factor); bench-log addendum with the PC 1 build rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:10:55 +00:00
igneum-labs
2b13281324 Consequences ledger: C26 with the prover-floor agent, C27 wiring rules 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:10:47 +00:00
igneum-labs
57249583d5 Consequences ledger round 4: C26 the rebuilt SP1 server's arch list and packaging, C27 checks at publish time; sweep 8 notes; D5 x8 decided 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:10:16 +00:00
igneum-labs
c597a7dcdb Counter ASIC 2.0 status 22:09: the fork test fixed at 89dfcb95 2026-10-05 22:09:59 +00:00
igneum-labs
c302a5738e counter-asic-2-node.md: suite job 3's result (kaspa-pow test rewritten for the era-in-class rule), the G6 reading corrected (the PC runs the feature-gated tests) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:08:44 +00:00
igneum-labs
90589ff60c Counter ASIC 2.0: G6 job 3 failed on a stale fork test, job 4 on the final tree; status 22:08 2026-10-05 22:08:07 +00:00
igneum-labs
a941b8b467 Counter ASIC 2.0: mixer x8 decided into v3 on the PC build rows; status 22:06 2026-10-05 22:06:59 +00:00
igneum-labs
f2d3dcaf3b Merge branch 'ca2-mixer' into ca2-v3 2026-10-05 22:05:05 +00:00
igneum-labs
92ab4582b3 counter-asic-2-node.md: the three PC 2 suite jobs (the flake, the kaspa-consensus rerun passed, job 3 pending) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:04:29 +00:00
igneum-labs
27a7ca6550 Counter ASIC 2.0 status 22:03: the PC 2 prover back, suite job 3 published 2026-10-05 22:03:35 +00:00
igneum-labs
4f0b9f5475 bench-log: the root-socket recurrence of 21:25Z and the fix job of 22:01Z (the prover proved again at 22:02Z) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:03:06 +00:00
igneum-labs
829687b1ab mixer x4: the measure session (v2 / x4 / x8 verifier 1.33 / 1.94 / 2.79 ms per unit on a loaded core, 1.45x and 2.1x; the 256 MiB fill 172 to 175 ms; the Metal 1 GiB build flat at 21 ms, latency-bound), the verification-throughput consequences (C19), what is unverified and what is owed; the bench-log entry; the PC 1 two-card playbook; the measured verifier row in the chip model 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:02:28 +00:00
igneum-labs
d2d5f5d6f2 mixer-x4.md: the x8 packs' Metal and Apple OpenCL rows, the daily-build table per tier (5090, 9070 XT, M5 Max, gfx1036 per prepare, a scaled 8 GB-class row) and the x4 / x8 rule; chip-model-v3.md: the mixer row alone as the headline (layer 5 measured, not adopted, with the 5090 and 9070 XT g beside the Mac's), x8 rows at year 0 and year 4 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:02:23 +00:00
igneum-labs
147db8db44 mixer x8 candidate beside x4 (coordinator's rule, 5 October 2026 21:30 UTC): LoadClass::MX8 ("mx8", same stream, keys (r m + j + 1) x 0x9E3779B9), the two candidate packs mx8-genesis and mx8-devnet-epoch0 (generator 2 with the class in the id; the vectors are re-cut through the seam after the x4/x8 choice), tests/mixer.rs fuzz takes IGNEUM_MIXER_CLASS, the PC playbooks carry the x8 packs and the gfx1036 fallback; mixer-x4.md: the Metal fuzz row 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:02:23 +00:00
igneum-labs
86ef4eab1e chip-model-v3.md: the hot table in the added form priced with the Mac's g (0.93 / 0.87 at 32 / 64 MiB, the 5090's g pending the PC rows): 1.98x and 2.12x at the equal integer budget, 1.60x and 1.67x with the SRAM deducted; the margin section says which convention keeps the claim 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:02:23 +00:00
igneum-labs
36ef07fda2 mixer x4: tests/mixer.rs (200-program v3 fuzz with the Metal pack writer, stats beside v2, dataset edges at every multiplier, determinism against the pinned pack); scratch.rs edge literal gains era_bytes; mixer-x4.md: the v3 vector tables, the v2 diff, the Metal and Apple OpenCL bit-exactness rows, the soundness table so far 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:02:23 +00:00
igneum-labs
65600a5caa Counter ASIC 2.0 status 22:01: the regression bisected, the mixer PC job, the PC 2 queue, the ship template 2026-10-05 22:01:10 +00:00
igneum-labs
23ab08202f plan: the 12 GB floor's cause (the shipped sp1-gpu-server refuses cards under 24 GB and allocates every prover at Setup; the prover-floor agent's source read) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 22:00:37 +00:00
igneum-labs
1852593e58 Counter ASIC 2.0: G6 job 2 green; the master merge dry-run; status 22:00 2026-10-05 22:00:30 +00:00
igneum-labs
be67d76914 Counter ASIC 2.0 status 21:59: 0.3.10 shipped and merged, the 0.3.11 base is master 2a9dbd8 2026-10-05 21:59:55 +00:00
igneum-labs
e3b7ac869b counter-asic-2-node.md: the cache merge done and checked, the mixer fix owed (54bbfcc is not it; its merge conflicts in bench-log.md and packbench.swift only) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:59:18 +00:00
igneum-labs
d60caeb608 Counter ASIC 2.0 status 21:58: ca2-v3 def920b with the cache merged 2026-10-05 21:58:53 +00:00
igneum-labs
ae699a4af2 release-0.3.10 plan: the merge to master, the console card's stale commit string, the site build on a conflicted journey.json 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:58:34 +00:00
igneum-labs
4c4a947baa Counter ASIC 2.0: layers 4 and 8 decided IN on the PC rows; status 21:58 2026-10-05 21:58:33 +00:00
igneum-labs
def920b1ed counter-asic-2-node.md: the CPU hash rate across the switch in run 2 (approximate) and the verifier slowdown the era agent measured, to be re-measured after the mixer fix 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:58:22 +00:00
igneum-labs
2a9dbd8176 Merge release-0.3.10: the certificate-driven reorg (C4), EVM transaction relay (protocol 14), the pack loader fix and the rebuilt workers, the six-section miner, GPU hot-plug, elevated-job exit codes, the PC-built Windows node (static libstdc++), node 21d4c73c; shipped 5 October 2026 21:32Z 
# Conflicts:
#	site/index.html
#	site/journey.json
 2026-10-05 21:58:04 +00:00
igneum-labs
e83084a1c1 Counter ASIC 2.0 status 21:58: ca2-cache rebased 39ecd7c 2026-10-05 21:58:03 +00:00
igneum-labs
3a6beaa0b8 Counter ASIC 2.0 status 21:57: the era PC job, the verifier regression gate item, the PC 2 order 2026-10-05 21:57:48 +00:00
igneum-labs
39ecd7c52b hot table (Counter ASIC 2.0 layer 5), measured and not adopted, on the ca2-v3 composed class (squash of tag ca2-cache-history-2026-10-05) 
LoadClass::hot (Option<HotClass { mb, k, added }>) beside mix, slots, scratch, mixer_mult, growth and era; V3_CLASS = { era: None, hot: None, ..LoadClass::MX4 } (hot stays None: the hot code is behind the flag, measured and not adopted). Op::Hot, the hot slots drawn after the scratch slots, no width roll (v2_loads allows the added form's extra slots), the id suffix hot/<S><k>[added], the hot parsing inside parse_loads, the era branch first in name(). HotTable under seed_words("igneum-hot/" || epoch seed) with the cache chain and tag umHT, read at H[mulhi(src, HOT_WORDS)]; DatasetSource::hot attached by new_class_day and from_seed_bytes_class; the acceptance stand-in dataset_elem(idx, S[2], S[3]); the three emitters (hot argument after the init words, ht_segment and igneum_hot_fill beside the layout-aware cores); packfile.h hot fields beside class, era, attempt and mixerMult; OpenCL host, Metal packbench and NVRTC worker fill H on the device and self-test it. Eight packs under proto-cuda/packs-ca2-hot (replaced hot32k4 hot64k4 hot96k4 hot64k2 hot64k8, added hot32k4a hot64k4a hot96k4a) re-exported on the merged crate: vectors unchanged, program.h and program.json carry the mixer fields. docs/plans/hot-table.md (design, spec text, per-tier budget, chip model, Mac and PC measurements, the decision: layer 5 out of v3, the 3.0 note); bench-log entry and addenda with job ids and worker sha256s; the two PC playbooks.

Checks on this commit: cargo test --release 53 + 19 pass (the pinned v2, mx4, era, readwidth and hot packs); the pinned packs under proto-cuda/packs, packs-ca2-mixer, packs-ca2-era and packs-readwidth untouched; Metal packbench and Apple OpenCL --bench-pack on all eight hot packs (run lock, 2^20 at base 0): 96/96 lanes, hot table head, last line and FNV PASS, one fingerprint per pack on both harnesses, equal to the fingerprints before the rebase (hot32k4 679e5e83378d3790, hot64k4 d4c9e456b039fdef, hot96k4 7c98eceffee9fd73, hot64k2 f43b10a95879b8e5, hot64k8 c11309d743be9392, hot32k4a afb700b2d997c847, hot64k4a ba214baa9c1a9e85, hot96k4a 29e1916aed6deff5). No era or mixer behaviour changed: every resolution kept the ca2-v3 side and appended the hot branch.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:57:39 +00:00
igneum-labs
3f81901155 plan: the aggregation-cost agent's card-alone rows (an empty shard 2 s, an aggregation 2 s, 4 proving-only cards for an empty chain) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:57:26 +00:00
igneum-labs
26ebf9cf29 release-0.3.10 plan: the ship (run 37374158235 after six dispatches through GitHub's outage, the fallback rehearsed on PC 1 and stood down), the rollout with per-machine times, the hand nodes and the seed, the digest sweep, the mixed fleet, the next cut and the open items 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:57:21 +00:00
igneum-labs
5fc5e100ad Counter ASIC 2.0: G6 first job failed on the known kaspa-consensus flake, split re-run; the app branch final a223ca9; status 21:56 2026-10-05 21:56:54 +00:00
igneum-labs
c4da08d302 App: the resume path re-arms every stopped card, re-exports its pack and checks 90 s later that every enabled card mines (PC 2 at 21:25:11Z and the Mac that afternoon stayed at 0 MH/s after resume); the PC 2 socket-fix job 
The known-failed case, from PC 2's 0.3.9 log (run win-1ccfe586-20261005-200114): 1791234223 pause -> 'stopping the
miners (paused)' (every slot's restart_at cleared, the 5090 'off'); 1791235511 '[ok] mining resumed'; then
'0.00 MH/s, waiting' at every 30-s status line until the 0.3.10 restart at 21:49:41Z. Cause: Cmd::Resume re-armed
only slots whose watchdog said faulted; the 5090's slot was healthy and stopped, so nothing restarted it. The test
the_pc2_resume_of_21_25_11z_restarts_under_the_new_rule_and_not_the_old encodes that slot (faulted false, live
false): the old rule returns [] (the defect), the new rule [0]. cargo test -p igneum-app resume: 3 passed;
provedefault: 6 passed.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:56:20 +00:00
igneum-labs
1610a0744b Counter ASIC 2.0 status 21:55: both PCs on 0.3.10, the PC 2 prover socket item, ca2-v3 495c552 2026-10-05 21:55:39 +00:00
igneum-labs
495c55280c counter-asic-2-node.md: gate G4 run 2 PASS on the composed class (era in the class on the mixer, 1558971): 181 / 124 blocks, 0 rejected, 0 forks; the PC 2 suite job id; the cache merge owed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:53:37 +00:00
igneum-labs
fc5721a516 Counter ASIC 2.0 status 21:53: the suite job published 2026-10-05 21:53:24 +00:00
igneum-labs
4127c80108 Counter ASIC 2.0: gate G4 green (runs 1 and 2); status 21:52: the suites packing 2026-10-05 21:52:11 +00:00
igneum-labs
110a9b1af1 Counter ASIC 2.0: the resume fix assigned to 0.3.11's app half; status 21:50 2026-10-05 21:50:54 +00:00
igneum-labs
6d4767b2a9 Consequences ledger: sweep 7 notes (hot table out, era draw in, x8 verifier half, the PC 2 resume defect) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:49:39 +00:00
igneum-labs
705e129446 Counter ASIC 2.0 status 21:46: PC 1 on 0.3.10, the era go 2026-10-05 21:46:13 +00:00
igneum-labs
17da4045b5 Counter ASIC 2.0 status 21:45: the PC 2 resume no-op defect, the miners off since 21:25 2026-10-05 21:45:43 +00:00
igneum-labs
30f7c41c29 Consequences ledger: C19 and C14 closed on the mixer verifier measurement (x8 = 2.1x, 7.1 ms margin); D5 carries it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:43:45 +00:00
igneum-labs
978c430a8a Counter ASIC 2.0 status 21:42: the era fast-forward 1558971, the cache rebase, the suites' tip 2026-10-05 21:42:41 +00:00
igneum-labs
5f125f5aee Counter ASIC 2.0 status 21:41: the era draw's Mac spread 0.8%, the final package, the merges 2026-10-05 21:41:42 +00:00
igneum-labs
1558971521 era layout (Counter ASIC 2.0 layers 4 and 8) behind the class flag, on the ca2-v3 seam: the 7-draw era stream from E_n (stride, interleave, width pinned at 4 B), per-site window draws (dataset, half, quarter at a 256 MiB floor), the strided windowed load address in the interpreter, the acceptance mirror and the three emitters, the interleaved dataset layout riding with the program (memhard::Layout, mh_t/mh_j/mh_addr, Epoch::dataset_word), V3_CLASS with the era drawn inside by generate_from_seed_bytes_program_class, --era / --era-widths on the CLI, six class v3 era packs (packs-ca2-era), tests, the design doc, host.cu/host.c deriving host words through the pack's mh_word, emu/test-layout.sh, the PC 1 playbook 
Squashed from six commits (tag ca2-era-pre-squash) for one merge.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:41:33 +00:00
igneum-labs
f394016bc3 Counter ASIC 2.0 status 21:41: the mixer timing session, x8 provisional 2026-10-05 21:41:15 +00:00
igneum-labs
208487c300 Counter ASIC 2.0 status 21:40: x8 built and bit-exact, the mixer PC job 2026-10-05 21:40:50 +00:00
igneum-labs
b3d15a7304 counter-asic-2-node.md: the two owed items (gate run 2 on the composed class, per-day dataset reuse in the CUDA and OpenCL workers) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:39:11 +00:00
igneum-labs
a61bbc4524 Counter ASIC 2.0: gate G4 run 1 PASS recorded; status 21:39 2026-10-05 21:39:01 +00:00
igneum-labs
08db83b2eb counter-asic-2-node.md: gate G4 run 1 PASS on the mixer-x4 class (181 / 124 blocks across the boundary, 0 rejected, 0 forks, 3 switch lines, v2 and v3 program ids), the summary JSON 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:38:37 +00:00
igneum-labs
29e1b28db4 Counter ASIC 2.0 status 21:38: ca2-cache final 2de19e5 2026-10-05 21:38:34 +00:00
igneum-labs
9eb6b5e654 Counter ASIC 2.0: layer 5 decided OUT on the PC rows; status 21:36 2026-10-05 21:36:30 +00:00
igneum-labs
5c0c196331 Consequences ledger: C23 taken by ca2-mixer too 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:36:08 +00:00
igneum-labs
030858063c Counter ASIC 2.0 status 21:34: PC 2 timing, the suites after the restart 2026-10-05 21:34:16 +00:00
igneum-labs
d6a503ca93 Counter ASIC 2.0: the iGPU restart-per-epoch statement, dataset reuse on the next-cut list, the gate's script fix; status 21:32 2026-10-05 21:32:35 +00:00
igneum-labs
54132959be Merge origin/master (the explorer pages, the public API check, the CLAUDE.md note) into release-0.3.10; docs, site, observer and ci.yml only 2026-10-05 21:32:17 +00:00
igneum-labs
2432a01f6c Counter ASIC 2.0 status 21:31: the runner recovered, the 0.3.10 rollout, the restart rule 2026-10-05 21:31:32 +00:00
igneum-labs
1df7ae9b08 Consequences ledger: C25 closed (Ember Tune 5d7ced9) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:31:24 +00:00
igneum-labs
ac55f878e1 Consequences ledger: C23 taken by the coordinator, C24 in work with the no-skip rule 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:31:11 +00:00
igneum-labs
dd37094a5b ember-tune.md: a signed prior is a starting point inside the card's own reported limits, never a memory clock; the tests that prove the clamp (consequences row C25) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:31:06 +00:00
igneum-labs
3791a29ebb Counter ASIC 2.0 status 21:31: C23 and C24 2026-10-05 21:31:06 +00:00
igneum-labs
48c13b5f1e Consequences ledger round 3: C23 the mixer's daily build on the iGPU tier, C24 the bash-body-in-PowerShell class, C25 tuning priors under the signing key; D5 re-cut to the measured chip row 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:30:25 +00:00
igneum-labs
d8e6ad3341 Counter ASIC 2.0: the x8 refinement in the rollout plan; status 21:28: hot-table go, installer attempt 3 failed, PC 1 order 2026-10-05 21:28:07 +00:00
igneum-labs
52e41787ec Counter ASIC 2.0: the x4/x8 decision rule recorded (delegated); status 21:27 2026-10-05 21:27:46 +00:00
igneum-labs
8981d15f59 Counter ASIC 2.0 status 21:27: installer attempt 3, the fast-failure rule 2026-10-05 21:27:00 +00:00
igneum-labs
99f7836a81 bench log: Ember Tune, what PC 1 could measure tonight (elevated=False, the cancelled prompt at 20:09 UTC, the 9070 XT off the bus), the pipeline verified without a card, the tier consequences 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:26:31 +00:00
igneum-labs
e2be67fc3f Counter ASIC 2.0: G6 state and the expected 0.3.11 digest; status 21:25 2026-10-05 21:25:28 +00:00
igneum-labs
7053d206a1 counter-asic-2-node.md: the (program id, era seed) identity, the measured digest flip, the Mac suite results 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:25:09 +00:00
igneum-labs
5c808b89e0 Ember Tune: every card tuned for MH per watt out of the box, the fleet prior per card model in the signed manifest, the console and /miners priors table 
the project lead, 5 October 2026, 22:45 BST: "make sure we have ember tuning every single card for efficiency out of the box, the
more data = the better the tune, make an awesome system." Built on lever 3 (docs/plans/miner-eff.md), lever 2's signed
tuning section (docs/design/miner-tuning.md), the AMD telemetry helper (423936b, its --tune/--set-gmax/--set-plimit/
--reset contract) and the Power control switch (057f0ec). Design, data flow, tiers and the privacy line:
docs/plans/ember-tune.md.

- src/ember.rs (new): two knobs per card (power limit %, core clock cap MHz; memory clock never touched), the full plan
  (power ladder 100..50%, then the clock ladder 90..60% at the chosen power), the confirm plan (the fleet prior and one
  neighbour), the baseline plan (measure only), the marks (faulted, hot, memory_clock_dropped, unapplied, no_readings),
  the choice (best MH/W within 1% of the top rate, then rate, then draw), the fleet record (a hash of the install id,
  no address), the prior lookup and the kill switch (tuning.ember), the state machine on a fake clock. 9 unit tests.
- engine.rs: tick_sweep schedules every NVIDIA, AMD and Apple card (120 s steady, 600 s to the boundary, no job hold,
  no pause, weekly, again after a driver major or program-class change, never under the manifest kill switch); the
  probe (nvidia-smi clocks.max.gr + driver_version and the direct/helper mode; igneum-gpu-telemetry --tune for AMD);
  tune_apply (nvidia-smi -pl / -lgc 0,<MHz> / -rgc directly or through the helper; the AMD helper per request);
  Cmd::TuneProbe, Cmd::TuneSet; faults from rejected and mismatched hashes mark the step; the TUNE lines and the TUNE
  {json} record, uploaded with the log; the Tuned line on the card state. The NVIDIA helper starts only with Power
  control on: the --sweep job never counts as permission (no prompt on a PC with nobody there).
- sweep.rs: the helper protocol gains lgc/rgc (clock cap and reset) and resets the clocks after 20 idle minutes.
- state.rs, config.rs: the tune fields (clock cap, driver, class, source, the Tuned line); the nvidia-smi telemetry
  query carries clocks.gr and clocks.mem; the AMD sample line's plimit_pct and gmax_mhz are parsed.
- ui: "Tuned: X MH/s at Y W (Z MH/W)" with the point, the source and when; measure-only cards say why; the Ember Tune
  switch; tune-line.test.mjs.
- relay/lib/ember.mjs + relay/test/ember.test.mjs: the aggregation per (card model | driver major | program class):
  median point, MH/W, spread, samples, machines; five samples converge, an outlier does not move the median, baselines
  make no prior, de-duplication, the manifest merge keeps lever 2's cards. api/console.mjs fn=tuning and
  tools/console.mjs tuning; tools/tuning.mjs --priors [--write tuning.json] [--site] [--tuning-off].
- site: the fleet priors table on /miners (site/miner-priors.json), the lever text.
- relay/playbooks/ember-tune-pc1.ps1: the PC 1 run (second engine with --sweep from a scratch copy of the install).

Measured tonight: see the bench log entry that follows the PC 1 run. The 9070 XT left PC 1's bus at 20:40 UTC and the
5090 needs the administrator prompt the project lead cannot answer asleep, so tonight's PC 1 run is the baseline plan on the 5090
through the whole pipeline; the two-knob tune on both cards is owed.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:25:09 +00:00
igneum-labs
48baa91575 Counter ASIC 2.0 status 21:25: the mixer x4 bit-exact on the Mac, the chip row 1.84x, the hot table's effect on the row 2026-10-05 21:25:03 +00:00
igneum-labs
c0c44cab39 Counter ASIC 2.0 status 21:24: the third eGPU drop, the miners are mining, the installer build running 2026-10-05 21:24:45 +00:00
igneum-labs
ec0c36f611 Counter ASIC 2.0 status 21:23: the era package, the V3_CLASS composition rule 2026-10-05 21:23:38 +00:00
igneum-labs
123af2d107 Counter ASIC 2.0 status 21:23: the installer build republished, PC 1 order 2026-10-05 21:23:10 +00:00
igneum-labs
877b45a116 Counter ASIC 2.0 status 21:22: the installer build job failed in 2 s, PC 1 decision pending 2026-10-05 21:22:37 +00:00
igneum-labs
ced3b703d4 Counter ASIC 2.0 status 21:22: Ember Tune queued 2026-10-05 21:22:20 +00:00
igneum-labs
e8547b1bcb Counter ASIC 2.0 status 21:21: PC 2 to agg-cost-pc2-2 until 21:45, the PC 1 order 2026-10-05 21:21:27 +00:00
igneum-labs
41afd097cd Counter ASIC 2.0 status 21:20: the added-form hot table on the Mac, the decision rule for layer 5 2026-10-05 21:20:53 +00:00
igneum-labs
8420f074d5 Counter ASIC 2.0 status 21:20: layer 9 complete with the compile-ahead table and the floor 2026-10-05 21:20:25 +00:00
igneum-labs
5a6c30560a Counter ASIC 2.0: the proving v1 app branch final 6dc686a; the 0.3.11 tree composition; status 21:20 2026-10-05 21:20:13 +00:00
igneum-labs
6cb846b84c ca2-epoch: the Mac compile-ahead measurement (10 fresh programs 15.9 / 17.7 / 20.4 ms min / median / max, the devnet pack 79 ms then 1 ms from the shader cache) in docs/bench-log.md and epoch-length.md section 6; the per-card table and the 600-s floor filled 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:19:33 +00:00
igneum-labs
b52c5f4cda Consequences ledger: C19 taken by ca2-mixer, the 8x corrected to under 4x pending the run 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:17:11 +00:00
igneum-labs
37fa956ca5 Consequences ledger: C22 taken in full by the proving agent 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:12:23 +00:00
igneum-labs
2f6c7138b6 evidence and litepaper: the 24 GB tier is measured on the 32 GB card's allocation, not yet on a 24 GB card (consequences C22) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:12:13 +00:00
igneum-labs
451b02ea42 Counter ASIC 2.0 status 21:11: the 9070 XT back on the bus, PC 1 to the 0.3.10 build, the playbook parse-gate rule 2026-10-05 21:11:19 +00:00
igneum-labs
2bc198b89d Consequences ledger: C2 closed on the miner-on curve; C22 the 30 GB CPU prover against the macOS switch; sweep 5 notes; D2 the two drafts and the 24 GB marker 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:09:39 +00:00
igneum-labs
1319adf588 Counter ASIC 2.0 status 21:05: the node merge ba43cf0f, the hot-table package, unproven_daa at fast time 2026-10-05 21:05:20 +00:00
igneum-labs
36c5f13a5f fast-time: the proving v1 fields and pow_genesis_dataset_log2 in both override files (the fork's every-field test), README rows; class-v3.mjs reports the build time per epoch; docs/plans/counter-asic-2-node.md (the node side of Counter ASIC 2.0, gate result pending) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:04:39 +00:00
igneum-labs
006b2fe585 Counter ASIC 2.0: proving v1 handoff recorded in the rollout plan; status 21:04 2026-10-05 21:04:35 +00:00
igneum-labs
594790b354 Merge branch 'amd-prove' into ca2-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-05 21:03:58 +00:00
igneum-labs
5424c30bba Proving v1: the app's default restores Decision and gb (lost in the tier rewrite), the AMD-only and Apple 'mines and does not prove' line with the CPU prover's measured cost, the plan's AMD/Apple row 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:03:42 +00:00
igneum-labs
ffa2633845 docs/analysis/amd-proving.md: no zkVM proves on AMD (SP1, RISC Zero, Jolt, OpenVM, ICICLE cited), the SP1 CPU prover measured on PC 1 beside the miners (282 s a shard at any size, 30 GB RSS: no CPU tier), the tier consequences and the public line; PC 1 job scripts with the bash -n gate; bench-log entry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:02:59 +00:00
igneum-labs
4366c6ad90 Counter ASIC 2.0 status 21:02: the measure lock convoy, found by lsof 2026-10-05 21:02:13 +00:00
igneum-labs
64ab9ce8d0 Counter ASIC 2.0 status 21:01: the 0.3.10 installer build takes PC 1 after the repro run 2026-10-05 21:01:20 +00:00
igneum-labs
b93d1897eb Counter ASIC 2.0 status 21:00: PC 1 to the repro run, PC 2 to agg-cost, the CPU fallback numbers, the S_p shard dropped 2026-10-05 21:00:58 +00:00
igneum-labs
2abdb56194 Counter ASIC 2.0 status 20:58: PC 1 and PC 2 occupancy 2026-10-05 20:58:57 +00:00
igneum-labs
46bad306d8 Proving v1: the harness passes on the final fork tree (N = 8, 21 checks in 244 s) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:57:33 +00:00
igneum-labs
b4e94a482d Counter ASIC 2.0 status 20:57: the mixer construction committed, MX4 is V3_CLASS 2026-10-05 20:57:12 +00:00
igneum-labs
4ddc9fcf4c Proving v1: the miner-on curve's 2^25 rows (the prototype shard 24.7 GB and 38.8 s beside the miner) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:56:32 +00:00
igneum-labs
88740ce75e Counter ASIC 2.0 status 20:56: PC 2 released, the proving fork tip, the S_p curve with the miner on 2026-10-05 20:56:23 +00:00
igneum-labs
1aff0b79d1 Proving v1: the miner-on curve (the adopted shard 22.2 GB and 13.2 s beside the miner; the prototype 30.1 GB): the 24 GB tier measured, the public lines updated 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:55:54 +00:00
igneum-labs
e08909f138 mixer x4 and the cache growth rule (Counter ASIC 2.0, class v3 construction): LoadClass mixer_mult and growth, LoadClass::MX4 (v2 loads, no width roll), memhard::Shape in MixParams, m mixer applications per round with keys round_key(r m + j), Cache::fill_log2, the option C schedule (growth_doublings, cache_log2_words, dataset_log2_words, days_since_genesis) with its test table, day-sized Epoch entries, the three emitters (m loop only for m > 1, v2 text unchanged), program.h and program.json fields, packfile.h mixerMult, packbench and OpenCL host prints, --class mx4 and --days on the CLI; docs/plans/mixer-x4.md design and spec text, docs/analysis/chip-model-v3.md, the 5090 and 9070 XT dataset-build playbooks (measurements and vectors to follow) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:54:10 +00:00
igneum-labs
3e237db050 counter-asic-2.md: layer 9 row and the decisions table of 5 October 2026 (night) 2026-10-05 20:53:45 +00:00
igneum-labs
f2c99cff95 Spec 01 1.4.5 and 1.4.6: generator 3, the class and era seed in the pack and on the job line, the refusal rule 2026-10-05 20:53:26 +00:00
igneum-labs
9eee20f97c Counter ASIC 2.0 status 20:53: spec text applied for layers 6, 7, 9; what still lands from the branches 2026-10-05 20:53:12 +00:00
igneum-labs
ac0d7c1592 Spec 01 and 04: layer 9 epoch_len (1.12, 1.13.1, 4.3), reserve family R1 and the emulation rule (1.13.2), the cache growth rule option C and the step mapping (1.13.3), the mixer_mult row 2026-10-05 20:52:58 +00:00
igneum-labs
cf0839a231 Counter ASIC 2.0 status 20:51: chain_dataset_day wired in the node, evidence row 22 2026-10-05 20:51:52 +00:00
igneum-labs
b8f8105af4 evidence.md: the card-lifetime claim as a designed row under the step schedule 2026-10-05 20:51:38 +00:00
igneum-labs
4a7b72da9b Litepaper hardware line on the step schedule; status 20:51: public copy applied, level 1 and the limits bullet wait for the chip row 2026-10-05 20:51:26 +00:00
igneum-labs
949c4582e1 Counter ASIC 2.0 status: readwidth head hash corrected to 06dcb31 2026-10-05 20:50:30 +00:00
igneum-labs
9fd666f3ff Consequences ledger: the read-width hash is 30ff674 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:50:21 +00:00
igneum-labs
fadc284414 Consequences ledger: C6 closed on pool-v0 (proving flag, no software dev fee in pool mode); D8 carries the fee sentence; the HiveOS README three-branch merge note 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:50:18 +00:00
igneum-labs
4f042f37dc Counter ASIC 2.0 status 20:50: the measure lock holder, the with-lock status defect 2026-10-05 20:50:05 +00:00
igneum-labs
ad2c0b566b Consequences ledger: C12 the Apple footprint arithmetic and the harness fields (read-width 46dcc3e) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:50:05 +00:00
igneum-labs
06dcb310fb read-width: per-watt and per-pound rows (telemetry watts, list prices approximate) and the AMD consequence (C11); packbench prints Metal's currentAllocatedSize and recommendedMaxWorkingSetSize (C12) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:49:45 +00:00
igneum-labs
4a1f872cb6 Counter ASIC 2.0 status 20:49: mixer construction, the lock cleared, PC 2 state, one merged-tree suite job 2026-10-05 20:49:39 +00:00
igneum-labs
1eaeefd770 Proving v1: the S_p curve's re-plan points (28.4 GB at 20 M cycles: the peak is flat from 20 M to 60 M) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:49:26 +00:00
igneum-labs
27471633c7 Counter ASIC 2.0 status: heading times 20:42 to 20:47 corrected to the commit clock 2026-10-05 20:48:20 +00:00
igneum-labs
9343d96a98 Counter ASIC 2.0 status 21:15: the Sonnet box off the link, PC 1 facts corrected, the queue 2026-10-05 20:47:57 +00:00
igneum-labs
ad6c8b4c52 Consequences ledger: C7 and C21 closed on the rig side (217d873), C20 confirmed no rig change 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:47:02 +00:00
igneum-labs
ce7474a74e Consequences ledger: sweep 3 notes (the 9070 XT bus drop stated by the coordinator, the epoch plan's tier table, the drafted litepaper sentences); C7 HiveOS table re-cut (2d056e8) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:46:53 +00:00
igneum-labs
c8f0fe7472 Counter ASIC 2.0: the G1 ruling (gfx1036 as the AMD vendor tonight), hardware events section for the morning 2026-10-05 20:46:20 +00:00
igneum-labs
1887438b36 Consequences decisions: D2 notes the proving agent's drafted sentences on its branch 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:45:56 +00:00
igneum-labs
4c9820c202 Consequences ledger: C15 closed with the S_p curve tiers; D2 recommendation re-cut to the measured tiers 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:45:46 +00:00
igneum-labs
fbeb3bb94d Counter ASIC 2.0 status 21:05: the 9070 XT absent on PC 1, app restart facts, era package ETA 2026-10-05 20:45:35 +00:00
igneum-labs
b1266b7fb7 Consequences ledger: C20 closed with the epoch agent's correction (prepare-ahead, exit 42 on a miss only) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:45:14 +00:00
igneum-labs
894022b926 Proving v1: the tiers from the S_p curve (24 GB proves the adopted shard, 32 GB mines and proves the prototype one, 12 and 16 GB off on this build) in the app's default, the litepaper, evidence rows 15 and 16 and the plan 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:45:01 +00:00
igneum-labs
560b6f78b6 ca2-epoch: docs/plans/epoch-length.md, the epoch length as a signalled era parameter (layer 9): day-anchored ladder 600 to 7,200, signal-only with the draw slot consumed, lead and T_epoch fixed (option A), the difficulty-settle constraint, the FPGA compile-time threat with citations, the per-card compile-ahead table and the 600-s floor (Mac rows pending the measurement), consequences per tier, spec text for 1.12, 1.13.1 and 4.3, owed list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:44:45 +00:00
igneum-labs
878c0581ef Counter ASIC 2.0 status 21:00: the Metal pack path, the --prepare-packs app item, the seam signatures, the build queue 2026-10-05 20:44:16 +00:00
igneum-labs
03313281ba Proving v1: the S_p curve, card alone (13.9 GB floor, 20.4 GB at the v1 shard, 28.3 GB at the prototype shard): the 12 and 16 GB tiers cannot prove on SP1 6.8.1's GPU server, 24 GB proves v1 shards, 32 GB the prototype 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:43:22 +00:00
igneum-labs
bc671326a7 Consequences ledger: C21 the wallet also trusts K1 alone 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:43:21 +00:00
igneum-labs
fe852a4335 AMD telemetry: igneum-gpu-telemetry (ADLX on Windows, amdgpu sysfs on Linux, PDH utilisation fallback) feeds the card row's draw, temperature, fan, memory clock and MH/W; measured on PC 1: 9070 XT 198.9 W, 64 C, 657 rpm, 17.73 MH/s = 0.089 MH/W beside the 5090 at 307.6 W, 122.30 MH/s = 0.398 MH/W 
the project lead watched the 9070 XT at 90% usage with its fans barely turning and the app could not say what it drew: the
draw, temperature and MH per watt line came from nvidia-smi only, and the earlier per-watt figure used the board
rating. proto-opencl/gpu-telemetry.c prints one line per AMD card per sample (bus from SetupAPI by the display
device's name, kind, name, watts, temp_c, fan_rpm, fan_pct, mclk_mhz, gclk_mhz, util_pct, source), built by
build-windows.sh against vendor/adlx (the SDK clone), shipped by make-payload.sh and push-inputs.sh. The engine
runs it with -l 5 beside nvidia-smi (Source::AmdTelemetry, tick_amd_telemetry), parse_amd_telemetry fills
power_w, temp_gpu, fan_pct, fan_rpm, mclk_mhz, util_pct and telemetry_at on the AMD card matched by kind and
ordinal, so eff_mhw and the dashboard's existing line show it; app.js shows fan and memory clock when present.
Tests: three on the parser with lines captured on PC 1 and the Mac fixture; the sysfs path ran on a fixture tree.

Measured over 20:27:45 to 20:29:41 UTC with both cards mining (docs/bench-log.md, under the 9070 XT ceiling table):
9070 XT 198.9 W (193 to 212), 64 C, 657 rpm, 2,505 MHz memory, 3,290 MHz shader, 100% busy, 17.73 MH/s =
0.089 MH/W; RTX 5090 307.6 W, 69 C, 44% fan, 122.30 MH/s = 0.398 MH/W.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:43:21 +00:00
igneum-labs
436d3f70d6 Consequences ledger: C21 the OTA agent's take (7a412bd), the HiveOS README double-edit merge note 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:43:09 +00:00
igneum-labs
fd5384abe6 Consequences ledger: C7 HiveOS words landed (226d3b8), C18 closed, C19 C20 in work 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:42:14 +00:00
igneum-labs
0e337349d0 Counter ASIC 2.0 rollout: the rig miners' exit-42 path on the next-cut list as a layer 9 precondition 2026-10-05 20:42:03 +00:00
igneum-labs
3e3b12b505 Counter ASIC 2.0: C18 per-pound correction struck everywhere, C19 and C20 routed 2026-10-05 20:41:50 +00:00
igneum-labs
3f9bf60576 Counter ASIC 2.0 status 20:45: the node switch written, the Metal worker gate item, PC 1 gaps 2026-10-05 20:41:37 +00:00
igneum-labs
e43db2b6f1 Consequences ledger round 2: C18 per-pound figure, C19 mixer x4 verify cost per tier, C20 layer 9 rig restarts, C21 OTA keys on rigs; C4 C8 C11 C12 states; D4 revised to (b) with the lifetime table 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:41:27 +00:00
igneum-labs
33713368b6 Counter ASIC 2.0 status: heading times corrected to the commit clock (UTC) 2026-10-05 20:41:03 +00:00
igneum-labs
7f3201f533 Counter ASIC 2.0: rig-install follow-ups on the next-cut list, the CPU fixture in the PC 1 gap, no more agents 2026-10-05 20:39:44 +00:00
igneum-labs
05c6feef0d Consequences ledger: C7 the rig gates follow the sweep (70b95d5) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:39:18 +00:00
igneum-labs
9dcb9697cf Counter ASIC 2.0 status 23:20: the PC 1 queue 2026-10-05 20:39:03 +00:00
igneum-labs
3f1d7e31aa Consequences ledger: C7 the rig installer's answer; D8 the miner page's mines-and-proves sentence 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:38:47 +00:00
igneum-labs
4ce31bbbe0 Counter ASIC 2.0 status 23:10: layer 7 PC rows, PC 1 free 2026-10-05 20:38:08 +00:00
igneum-labs
344cba8e8c Proving v1: the memory sweep and the miner-on peaks, the root-socket class fix (cleanup lines, tools/ci/prover-socket-check.sh in CI), the host's --budget re-plan and the S_p curve job, the RAM and aggregation-card gates, N = 8 in the fast-time file and spec 7.4 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:35:13 +00:00
igneum-labs
3f33c6fd00 Counter ASIC 2.0 status 23:00: layer 9 agent, PC queues 2026-10-05 20:32:53 +00:00
igneum-labs
770145f7be Counter ASIC 2.0: card lifetime merged, cache freed after the build, growth mapping (b) recommended, public lines listed 2026-10-05 20:31:48 +00:00
igneum-labs
c9ebe7bd14 Counter ASIC 2.0 layer 7: RTX 5090 and RX 9070 XT dot4 numbers from PC 1 (job run-dot4-20261005): dp4a 7.45 T/s on the 5090 via inline PTX, v_dot4_i32_iu8 0.66 T/s on the 9070 XT via the clang builtin in Adrenalin OpenCL C, signed emulation 7.1x / 1.46x / 4.7x the ALU step on NVIDIA / AMD / Apple; no PC platform lists cl_khr_integer_dot_product 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:31:33 +00:00
igneum-labs
fa5a69148b Merge branch 'card-lifetime' into ca2-coord 2026-10-05 20:31:25 +00:00
igneum-labs
99ab478f1e docs/analysis/card-lifetime-2026-10-05.md: years each card tier keeps mining under the dataset schedule and the working-set rule, against the site and litepaper claims 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:30:46 +00:00
igneum-labs
66c2fea107 Consequences ledger: C16 the 20:01Z quit explained in part; C17 the root-owned SP1 socket class and the unattributed quit 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:30:31 +00:00
igneum-labs
37f6fa5a41 Consequences ledger: C13 closed by the explorer agent (894fe08) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:30:03 +00:00
igneum-labs
efeab4b23d Counter ASIC 2.0 rollout: ota-k2 commit on the next-cut list 2026-10-05 20:29:37 +00:00
igneum-labs
339b6981dd Consequences ledger: the proving agent's takes; C15 the 28.3 GB full shard and the unmeasured v1 shard; C16 the unexplained PC 2 app quit at 20:01Z 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:29:31 +00:00
igneum-labs
35b3e38d2a Counter ASIC 2.0 status 22:40: C1 decision and the 16:00Z check, one packfile.h fix 2026-10-05 20:29:09 +00:00
igneum-labs
e5a184dea2 Consequences ledger: states after the coordinator's and the miner UI's replies; C14 the mixer x4 verify cost for pools and nodes 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:28:17 +00:00
igneum-labs
724c5eee37 Counter ASIC 2.0: layer 9 row, C1 constraint, era mid-way and the attempt-aware packfile bug, C10 and C11 answers 2026-10-05 20:27:58 +00:00
igneum-labs
73358ca92d Proving v1: the 12 GB memory sweep on the 5090 (13.9 GB floor on an empty shard, 28.3 GB on a full one, no knob moves the floor) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:27:45 +00:00
igneum-labs
fff1994c8a Counter ASIC 2.0: layers 1, 2, 3 decided from the readwidth table, layer 5 Mac rows and the added-form redesign, user tiers, public level 2 edit 2026-10-05 20:27:01 +00:00
igneum-labs
6a9b7c1283 Counter ASIC 2.0: the mixer x4 decision into v3, ca2-mixer agent, status 22:00 2026-10-05 20:27:01 +00:00
igneum-labs
f4fc651512 Counter ASIC 2.0: layer 3 decided (scratch share 0, chip 2.4x at every share), the claim qualified, public level 3 headline 2026-10-05 20:27:01 +00:00
igneum-labs
5c3a35c6de Counter ASIC 2.0 status 21:35: the corrected SRAM mirror table 2026-10-05 20:27:01 +00:00
igneum-labs
bcb3f20bd9 Counter ASIC 2.0 status 21:25: proving v1 state, PC 2 queue 2026-10-05 20:27:01 +00:00
igneum-labs
cbbc81f002 Counter ASIC 2.0: the shipped-density correction to the SRAM mirror (130 to 165 mm^2), carried into the rollout and public docs 2026-10-05 20:27:01 +00:00
igneum-labs
b258094890 Counter ASIC 2.0: layer 6 option C and layer 7 R1 decided (delegated), the chip headline rule for the scratch share 2026-10-05 20:27:01 +00:00
igneum-labs
ece48696f3 Counter ASIC 2.0 status 20:55: layers 6 and 7, node agent, 0.3.11 scope with proving v1 2026-10-05 20:27:01 +00:00
igneum-labs
002c455eaa Counter ASIC 2.0 status: the four-level public description deliverable 2026-10-05 20:27:01 +00:00
igneum-labs
7262df1964 Counter ASIC: the public description in four levels (levels 1 and 2 as copy, 3 and 4 with owed markers) 2026-10-05 20:27:01 +00:00
igneum-labs
1509a2c477 Counter ASIC 2.0 status 20:35: readwidth round 2, probe ceilings, width arithmetic 2026-10-05 20:27:01 +00:00
igneum-labs
045e8e5708 Counter ASIC 2.0 status 20:25: 0.3.10 blocked on GitHub, node fork convention, 0.3.11 inputs 2026-10-05 20:27:01 +00:00
igneum-labs
4b11f3a0cb Counter ASIC 2.0 status 20:15: the devnet mandate, gates, node path note 2026-10-05 20:27:01 +00:00
igneum-labs
34ba9cd92e Counter ASIC 2.0 rollout: the project lead's devnet decision rules, the six gates, the 0.3.11 release path 2026-10-05 20:27:01 +00:00
igneum-labs
b3b935f69f Counter ASIC 2.0 status 20:05: readwidth PC jobs, the capped-scratch finding 2026-10-05 20:27:01 +00:00
igneum-labs
8988f9e03c Counter ASIC 2.0: rollout plan draft (program_class_v3 height switch, digest first, decisions table) 2026-10-05 20:27:00 +00:00
igneum-labs
14303e9bf8 Counter ASIC 2.0 status: agents respawned, first readwidth Mac rows 2026-10-05 20:27:00 +00:00
igneum-labs
68e9c9fd29 Counter ASIC 2.0 status: restart after the credit cut-off, the 6 GB working-set budget 2026-10-05 20:27:00 +00:00
igneum-labs
578a903b36 Counter ASIC 2.0: coordinator status file, first entry 2026-10-05 20:27:00 +00:00
igneum-labs
9a4c69960e Consequences ledger (night of 5 October 2026): round 1, thirteen rows (fee switch vs the 0.3.10 export, 16 GB chained peak, 12 GB gate, host RAM, restart in flight, pool accounting, HiveOS prover, card lifetime, index mapping, the 2.4x chip row, AMD per watt, Apple unified memory, explorer supply) and seven decision requests 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:26:32 +00:00
igneum-labs
2d04a1c553 read-width: bench-log entry and docs/plans/read-width.md (three cards, probes, widths, the per-load mix, the scratch at 32 and 128 KiB, chip model, recommendation: keep v2; w16 the only width that passes the rules and closes nothing); test multiply made wrapping (dev-profile overflow check) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:24:40 +00:00
igneum-labs
340d7f4cd7 Proving v1: the decisions (N 8, T 600, a tenth to the aggregator, H = tip + 14,400, no sortition, Apple off) with the other networks' rules read tonight; the profile rows wait for the sweep 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:22:32 +00:00
igneum-labs
3f09a552eb scratch-soundness.md: the five findings, the recompute-versus-store arithmetic at 64, 256 and 2,048 slots, the named on-die-cache chip row per variant (2.4x at every share under the cap) beside the M16 mixer lever, the host tag contract, the vector requirements, the Metal results (228 of 228 pass, 3 of 3 built-in failures caught); bench-log entry with the commands and counts 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:21:49 +00:00
igneum-labs
d4848453ae Proving v1: the chain of 8 on the 5090 measured (N = 2, 4, 8: 32.6, 66.8, 135.6 s; chained aggregation 9.7 s a block on a mining card), the fleet table re-cut on the measured rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:21:14 +00:00
igneum-labs
e9508926dc Proving v1: the chain of 2 on the 5090 (31.8 s, the chained aggregation 9.5 s), the job aborted by the 0.3.10 restart at block 3 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:21:14 +00:00
igneum-labs
251ea75b23 Proving v1: step 1 measured with the fleet mining (the prover costs the 5090 4.0%, GPU peak 15.6 GB with the miner), the fleet coverage window (2.4%, p50 44 s) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:21:14 +00:00
igneum-labs
ae3b681b3d Proving v1: the fleet-size table from the measured inputs, the numbers table in the plan 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:21:14 +00:00
igneum-labs
3fcf4f705c Proving v1: the harness passes (21 checks), the bench-log entry with the step 1 GPU memory, RAM and SM-target numbers, the CPU chain of 2 and verify-segment 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:21:14 +00:00
igneum-labs
55ea10cc26 Proving v1: prover on by default, the aggregated segment record, host modes chain, aggregate and verify-segment, the app's aggregator step, spec 7.8, the fast-time harness and the coverage tool 
Step 1: app/igneum-app/src/provedefault.rs decides once per install (NVIDIA 12 GB or more, WSL2 answering on
Windows, Linux native, Apple silicon off until measured), never switching an explicit on back off; the Settings
switch line and the tile line say why (5 unit tests). tools/proving-v1/pc2-prover-cost.ps1 is the PC 2 job
(5 min mining alone, 5 min with the prover, GPU memory and host RAM peaks, the sp1-gpu-server's SM targets).

Step 2: the host gains --mode chain (consecutive fixtures, each block aggregated with the previous block's
proof by recursion), --mode aggregate (the live aggregator over shard proof files, a run of blocks in one
process) and --mode verify-segment (the node's verifier against the pinned aggregator key); the app's prover
loop gains aggregate_once (spec 7.8). Eight consecutive live fixtures (blocks 81046 to 81053, node 1's export
at tip 81076) under proving/fixtures/chain/. tools/proving-v1/pc2-chain.ps1 is the PC 2 job (held).

Steps 3 and 4: tools/proving-v1/coverage.mjs (the proven-block share and the on-chain latency from one node's
RPC), tools/proving-v1/net.mjs (the fast-time 3-node harness on 29950+ with the known-finished and
known-failed cases of the chain rule and the unproven rule), the four proving_v1 fields in
infra/fast-time/override-60x.json. Spec 7.8, the 7.4 rows, the 5.3 sentence, docs/plans/proving-v1.md.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:21:04 +00:00
igneum-labs
16cfea717a Counter ASIC 2.0 layer 6, revision 2: shipped cache-die density (AMD V-Cache 64 MB on 41 mm^2 at 7 nm, Hot Chips 33) as the headline column beside the bit-cell lower bound; mirror 106 to 164 mm^2 and $30 to $56 per die at 256 MiB; year 0 to 10, hot-table and option tables redone; latency citations section (MEMSYS 2018, Chang 2017, mining-chip memory types) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:20:46 +00:00