igneum-labs
074509e874
Class v6: section 10, the floor (the five floor lanes' terms, what the document already holds measured for each, the default at 19:30 and the row owed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5b7e219da
2026-10-08 12:28:19 +00:00
igneum-labs
7835d342a2
Class v6: the sound per-load form's 5090 rows measured (shl4096x1 at class v4's count: 116 W over class v3 against the whole block's 152 unlocked, 59 against 84 at the knee; shl2304x3 19 W and 6.6 W over the whole block)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a10fa0d5e
2026-10-08 12:28:19 +00:00
igneum-labs
ac94670313
Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 77be72c11
2026-10-08 12:28:19 +00:00
igneum-labs
8fe7a731cd
Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d8b2e2ee6
2026-10-08 12:28:19 +00:00
igneum-labs
321184e321
Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 837576edc
2026-10-08 12:28:19 +00:00
igneum-labs
b9dc2dac42
Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0182c50dc
2026-10-08 12:28:18 +00:00
igneum-labs
f310ac4e86
Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8}
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of be1ff694c
2026-10-08 12:28:18 +00:00
igneum-labs
441a2b89b7
Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a07d69371
2026-10-08 12:28:18 +00:00
igneum-labs
12d36b2208
Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e458519a3
2026-10-08 12:28:18 +00:00
igneum-labs
424596d046
Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2fc3377cd
2026-10-08 12:28:18 +00:00
igneum-labs
070d319ce6
Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 93a5e401b
2026-10-08 12:28:18 +00:00
igneum-labs
f5f34eb36e
Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 963235c7c
2026-10-08 12:28:18 +00:00
igneum-labs
777098f829
Counter ASIC 4.0 research: 15.1a the microbench rows (20 probes on the 5090 at both states) and the correction they force: a tile is 32 MACs per lane, not 1,024, so the int8 MAC costs 1.5 to 4 pJ measured (the 6 October 4090 figure 1.8, not 0.056); the tensor shadow is the worse lever (k 0.03 to 0.3); the shuffle at 55.8 pJ per op is the card's dearest instruction (the re-weight's GPU side against it); an L2 hit at 2.4 nJ kills the hot-table lever; the first sentence and the ranking corrected
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fc16c2ef1
2026-10-08 12:28:17 +00:00
igneum-labs
afca2b06d4
Counter ASIC 4.0 research: 20.3b the SM-sparse reading (a quarter of the SMs holds 98 percent of the rate at the same draw; the draw follows the work, not the SM count): rank 2 dead on measured rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 100d50aab
2026-10-08 12:28:17 +00:00
igneum-labs
7a5e13a4fb
Counter ASIC 4.0 research: 20.4 names the 1,430-tile point as the one the k column was priced at, the Apple side open, nothing served moving
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9422f42a7
2026-10-08 12:28:17 +00:00
igneum-labs
c343a2a6d9
Counter ASIC 4.0 research: 20.3 the card rows of the seven packs (the tile block carries the ALU shadow's premium at the same rate, 14 percent cheaper at the knee; 0.048 to 0.091 pJ per MAC measured on the 5090), 20.4 the chip-model rows, the first sentence on measured rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8522caca0
2026-10-08 12:28:17 +00:00
igneum-labs
19d64f2c86
Counter ASIC 4.0 research: --bench honours --variant through the pinned race (the SM-sparse run of 00:22 to 00:41 UTC served base on all 48 rows); RESULT carries variant, sparse_blocks and block_warps, variant_not_installed is the known-failed line; 20.3a records the run and its knee rows (v4 309.9 W, v3 219.4 W, premium 90.5 W at 1,300 MHz)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0b0151b55
2026-10-08 12:28:17 +00:00
igneum-labs
a3b0f01364
Counter ASIC 4.0 research: 20.2a-close, the per-load 16 x 27 construction dead as a chain class (1.4 percent acceptance, 42 of 64 seeds without a program), the sound form named, rank 4 marked
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 4072cd7f0
2026-10-08 12:28:17 +00:00
igneum-labs
ecbd82956e
Counter ASIC 4.0 research: 20.2a the per-load fault fixed with clock readings, the drawn-era census (0 pairs across 16 eras), the Metal fingerprints (the tile reference bit-exact; the Apple emulation costs 35 and 78 percent of rate at 1,024 and 4,096 tiles per hash); 20.2b the biased-product-bits requirement from adv-cache-2
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d26704367
2026-10-08 12:28:16 +00:00
igneum-labs
5fbc907c87
Counter ASIC 4.0 research: 20.2 the verifier rows (AVX2 tile path 0.047 us per tile per unit, mm1430 10.14 ms loaded; the per-load placement derives 11 percent fewer distinct items per warp: a uniformity fault as drawn, with its fix)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 598fd20f0
2026-10-08 12:28:16 +00:00
igneum-labs
e0dc3bcb79
Counter ASIC 4.0 research: section 20, the two prototypes built (what, where, gates; the verifier and card rows pending)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1a7689e1b
2026-10-08 12:28:16 +00:00
igneum-labs
cc36d4db03
Counter ASIC 4.0 research, second pass: the k-above-1 hunt, the capex lever and the re-ranked list
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Sections 15 to 19: every GPU block gaming and AI paid for, priced against the best public 4 to 5 nm chip figure with its k band, verifier cost and the edge at the measured premium (the one-sentence answer: nothing reads k above 1 with certainty; the int8 tensor tile is the only block near or above 1, so the tensor shadow with a SIMD byte-dot verifier is the new rank 3); the capex column added to the chip model (both sides capex-dominated at 7x to 10x their electricity; the per-unit capex wall unreachable by 3x to 7x; the project wall doubled from USD 100 M to about USD 200 M of break-even cap by the shadow-per-load design, the mission lane's method); the microbench of 20 probes documented as built (section 18); the owed list.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e76770109
2026-10-08 12:28:16 +00:00
igneum-labs
c4de71072e
Counter ASIC 4.0 research: clock stamps in UTC (the box compile at 20:48 UTC, the knee reading at 20:5x UTC)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 30c2d2211
2026-10-08 12:28:16 +00:00
igneum-labs
596f284ddc
Counter ASIC 4.0 research: the identity that forbids a zero-premium chip lever, the ranked designs, and the SM-sparse worker variant
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docs/analysis/counter-asic-4-research.md (excluded from the public export): edge = (E_card + F) / (E_mem + k F); at zero premium the stored-dataset chip keeps E_card / E_mem, 3.6x on a 5090 locked at 1,400 MHz (measured card, modelled chip), about 2x at that card's idle-plus-memory bound, 1.7x on the M5 Max; class v5 at zero shadow leaves it at 5.1x to 9.1x; the shadow buys 2.1x at k = 1 for the measured 88 W (81.8 W at the knee) and turns against us below 1.8 pJ per op; per-card classes, the refresh as a cost, proof of useful work, memory shaping and the tensor block priced out with their arithmetic; ten designs ranked with the chip edge, the 5090 and 4070 premiums, the verifier cost, agent hours and what breaks each; the recommendation in five sentences; consequences per tier.
proto-cuda/nvrtc/worker.cpp: opt-in SM-sparse variants sp<N> and sp<N>-w<W> (a persistent grid of N blocks of W warps over the dispatch's nonces; the bound kernel rewritten at compile time with exact anchors into a unit function plus a wrapper of the kernel's name; made on demand by name, never in the default race; refused on variant-5 packs and with minBlocks). Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra, 22:48 UTC; exe sha256 ee8d0e70dd101f125f42c0c7cf07481a794ee18a1317acf68561b37ea18d72be; unrun on a card (the hash lane's PC 1 job run-ca4-pc1-ca4sparse-5090-20261007 is its first run).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5abb666ae
2026-10-08 12:28:16 +00:00
igneum-labs
17cc15dc5e
Merge ca3-coord-record 68008678 into master (gate: green on 68008678, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:13:44 +00:00
igneum-labs
cd123dbaf1
Merge class-v6-family-gate a39dbeca into master (gate: green on a39dbeca, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:12:39 +00:00
igneum-labs
6800867884
Counter ASIC 3.0 status: Devnet 3 stalled at the class v5 floor at 12:48 BST (the fleet's workers without the kit's generator-5 worker; --exec-rpc) and crossed clean at 12:57:40, the pairing checked three ways, the worker-smoke gate rule; the pin's node sha 5f316c21 (the chain-id answer) every gate green; the research lane's section 10 and the two floor rows; kit b's 5090 rows (the x16 draw free on the GPU, the size term real at the knee); the 9070 XT row served ( 023b9bee); the attack pass's census split; the deploys 773c56f9, 023b9bee
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:06:07 +00:00
igneum-labs
f64d866e1f
Merge master 023b9bee into wallet-bridge (master moved 24 commits during the landing's gate)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:59:16 +00:00
igneum-labs
2c34ca933a
Merge ca3-coord-record 367b7078 into master (gate: green on 367b7078, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:53:54 +00:00
igneum-labs
367b70788e
Standing rule (main's word, 8 October 2026, 12:5x UK): no kill by name on the Mac, pid file only, ad-hoc shell lines included; Counter ASIC 3.0 status: the node lane's named commit 42ce0f07 (four node fixes incl. the proof-map window, the OOM class behind the seed outage), the fleet census (36 on population A, 21 stale re-walking), the research lane's b6799782 (chip-model 5.12, the class v6 document through section 9), lane D's move to build-3 and its lossy-share curve, the F8-256 PASS, the hash lane's v6 packs rows and the byte-seed export lesson, the shipper's 12:33 line, the pkill class
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:46:11 +00:00
igneum-labs
bc7c0d4d20
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 11:46:02 +00:00
igneum-labs
5eeb2299d3
Class v6 invention: the 5090 rows for the two per-load packs (the sound form costs the card 15 to 20 percent more per shadow instruction than the whole block, +19 W unlocked and +6.6 W at the knee at class v4's count; rank 1's GPU column corrected, the verdict restated with the honest sign)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:45:37 +00:00
igneum-labs
1ef5480189
Merge ca3-coord-record 2d3da301 into master (gate: green on 2d3da301, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:45:12 +00:00
igneum-labs
5218ce8f07
Merge class-v6-invention 4ad3e401 into master (gate: green on 4ad3e401, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:44:26 +00:00
igneum-labs
4e815cc8e3
Merge dex-devnet3 dd3a1b3b into master (gate: green on dd3a1b3b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:43:52 +00:00
igneum-labs
967ebc555a
The wallet line's text under master's founder scrub: the name replaced in the README, updater.rs's comment, the three wallet plan documents and the capture script (the files predate the scrub; the facts stay)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:36:47 +00:00
igneum-labs
dd3a1b3b3c
Bridge: one Devnet 3 account balance proven on the Sepolia verifier (547.8077 IGN under the state root of Devnet 3 block 28,462, three-node eth_getProof from the reader node; eth_call true on the live contract, the suite 10 of 10 green on build-3); the vector committed
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:41 +00:00
igneum-labs
a39dbeca29
Class v6 family gate, the 17:00 cut: the harness as a plain diff at 3dc3117c (the founder-strings check refuses the patch form's author lines)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:25 +00:00
igneum-labs
4ad3e4013c
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 11:35:21 +00:00
igneum-labs
053c387132
Class v6 invention: the uniformity read at 2^20 on 64 seeds (the sound per-load forms clean, 0 over 1.2x and 0 sites under 0.995; the raw class v4 shape through the v2/v3 rule 41 of 64 hot at 7x to 36x, AP-F8-1's class as the harness's known-failed firing), the harness crate, the box OOM record, the offered window-bits test
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:11 +00:00
igneum-labs
ba9319f84b
Merge master into wallet-bridge (the wallet's line meets master for the landing of the page bridge)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
# Conflicts:
# packaging/ota/publish-manifest.sh
# site/index.html
# site/wallet.html
2026-10-08 11:33:30 +00:00
igneum-labs
2d3da3010a
Counter ASIC 3.0 status: the 8a217427 deploy read back, the 0.3.25 pre-pin matrix green on four boxes, the 9070 XT grid on the AMD knob (run-ca3-pc1-amd-grid-9070-20261008-b: 149 W at 18.96 MH/s, both floors, the knob a watts lever only, the two 5090 denominators), the Arc default at 12:30 (pairing f2267bb6, kit 65b47211, Intel held out), the explorer deploys 3b21d002, e3efb38b and 4b8712eb, the /build lane's close, lane D's 24,000-era coverage (61 of 5,000 at the lossy corner against 0 of 19,000), the node lane's missed 12:30 clock and the gate-priority lesson, main's census correction
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:30:51 +00:00
igneum-labs
debcb01092
Class v6 family gate, the 17:00 cut: the last-resort rows corrected for class v5's verified scan (the finding at the corner is the correlation of one era's attempts, 1,000x the independent estimate, not an unchecked program); the harness patch series at 236ef3a5 (the lossy-share curve and the scan's verdict column)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:27:11 +00:00
igneum-labs
d4cd6a3ce2
Class v6 family gate, the 17:00 cut: the measured coverage (24,000 drawn eras through the ring-B tests on build-1 and build-3, 54 core-hours), per stratum and per axis, with the bound arithmetic on the counts; four measured rows (the lossy corner of B = 4 exhausts the 256 cap in 1.2 percent of eras, the band capped at the lossy families; the (c''') floor's per-width calibration; the shape axis's draw cost; the era-stride bias at bit R in half the eras of every stratum); the census rows, logs, scripts and the harness patch series under logs/
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:25:26 +00:00
igneum-labs
4b8712ebbd
Merge dex-devnet3 66038966 into master (gate: green on 66038966, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:17:02 +00:00
igneum-labs
660389668b
Bridge: the first Devnet 3 checkpoint (index 2127) verified and recorded on the Sepolia verifier (tx 0x569a62c1, block 11869773); docs/contracts/sepolia.json
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:10:43 +00:00
igneum-labs
3f8c803e7d
Merge dex-devnet3 496db8b9 into master (gate: green on 496db8b9, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:09:11 +00:00
igneum-labs
3b21d002c7
Merge explorer-dn3 ace058e5 into master (gate: green on ace058e5, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:05:43 +00:00
igneum-labs
496db8b9df
Bridge: the verifier live on Sepolia at 0xAf74f3F512081291D663Bb1d6b6d37E99e37D744 with the Devnet 3 voter table (29 keys, 7,164 weight at index 2127; docs/contracts/sepolia.json), the Osaka test EVM, the account vector mode and the Devnet 3 account test (skips until the eth_getProof node serves)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:02:40 +00:00
igneum-labs
ace058e521
Merge remote-tracking branch 'build/master' into explorer-dn3
...
# Conflicts:
# site/build.mjs
2026-10-08 10:58:52 +00:00
