2 commits

Author	SHA1	Message	Date
igneum-labs	5588aa5cc8	Counter ASIC 3.0 items 6 and 7: proposed reserve order and spec text (docs/plans/counter-asic-3-reserve.md), the vendor-share section on the benchmark page, the observer README row	2026-10-06 07:40:41 +00:00
igneum-labs	9e1b44a4e2	docs/benchmarks/repro.md: carried from repro-bench fa00419	2026-10-06 07:34:58 +00:00