igneum-labs
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15128f593a
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 036c1aded (bfccc26ed4) for the box mirror master
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2026-10-08 14:32:45 +00:00 |
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igneum-labs
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35e6a80e73
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shadow-k: the programmable core's synthesis-only row (6.9 pJ per lane-op ASAP7, k 0.56 at the lock at N3), the edge table in the absolute convention, the lease-routed Makefile
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ed7d2626d (bfccc26ed4) for the box mirror master
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2026-10-08 14:32:44 +00:00 |
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igneum-labs
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a60981933b
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 49c49c340 (bfccc26ed4) for the box mirror master
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2026-10-08 14:32:44 +00:00 |
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igneum-labs
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b15ba14323
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chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6fab785c5 (bfccc26ed4) for the box mirror master
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2026-10-08 14:32:43 +00:00 |
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igneum-labs
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23fcb5dc62
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9009ed0f4 (bfccc26ed4) for the box mirror master
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2026-10-08 14:32:43 +00:00 |
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