igneum-labs
c3d26c1712
adv-cache-3 ledger: the sibling-43 kill was adv-cache-2's drain; file superseded, not rerun
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 20:41:54 +00:00
igneum-labs
3df56637d7
adv-cache-3: sibling file 43 run for adv-cache-2 (SIGTERM at 247 s, partial rows recorded)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 20:41:17 +00:00
igneum-labs
c5556005cf
adv-cache-3: the exhaustive image census landed at all 64 depths (random function to six places, the permutation plant fires); sibling file 43 claimed
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 20:36:05 +00:00
igneum-labs
4111419d4a
adv-cache-3: the flip-table ladder at 2^18 lines (rounds 2, 3, 4, 6) landed; single-bit tests stop between one and two double rounds
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 20:15:25 +00:00
igneum-labs
8e7d53fd8a
adv-cache-3 ledger: the box-2 lease taken by error at 20:41 and killed; file 98 queued
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 19:42:18 +00:00
igneum-labs
4fa1b3a4dd
adv-cache-3: report with every row landed (Q1, Q2, Q3, Q4 bounds, the pebbling baseline finding, the image census to depth 8) and the logs
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 19:28:55 +00:00
igneum-labs
9c1ae6177e
adv-cache-3: ledger records the 20:20 BST kill and the lease re-queue
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 19:21:58 +00:00
igneum-labs
e98be85e93
adv-cache-3: report skeleton with the first skip row (internal adversarial pass, not an independent review)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 19:18:07 +00:00
igneum-labs
e746d39fbd
adv-cache-3: attack plan for the chain break or skip (internal adversarial pass, not an independent review)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 18:49:24 +00:00
igneum-labs
63f4437f71
Merge build-server a8587452 into master on the box mirror (GitHub suspended since 18:02 BST; the box gate stamp stands in for CI; main's rule of 18:1x BST)
2026-10-07 18:23:34 +00:00
igneum-labs
a85874524f
Build boxes to near max (the project lead, 7 Oct 2026 19:4x BST): the bounded class is 88 of 96 cores with -j 88 (8 reserved for release builds, the seed and the observers), the jobs rule 88 alone / 44 shared, the spill line 80; checks updated. testnet-go.md: LG-2 waived by the owner, the new gate, the seeds held armed
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 18:23:14 +00:00
igneum-labs
2cd6b2fade
Merge ship-docs-0321 d646849f into master (gate: green on d646849f, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-07 18:21:29 +00:00
igneum-labs
d646849ffd
release 0.3.22 section 7: the project lead moves the apps to Devnet 3 tonight (the clock), the pin 34a2dbaa with no heights and why, the app tree at 19:15 BST, PC 2's evening and the rules it added
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 18:17:15 +00:00
igneum-labs
7fa7d22bb6
Merge build/master into ca3-coord (release-0.3.21.md keeps both sides); Counter ASIC 3.0 status: Devnet 3's proof window, the utilisation table, the bench table, the v5 gap list, the in-house pass, the PC 1 queue
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 18:05:34 +00:00
igneum-labs
4794a8ef82
Counter ASIC 3.0 status: the Devnet 3 epoch-0 pack, the project lead's three orders and the in-house correction (class v5 now, the internal adversarial pass, the PC 1 measurements)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:54:43 +00:00
igneum-labs
c659b2c85c
Site and evidence: the chip model's next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), not external lots; the one outside check staged on its escrow and the publish word (the project lead's correction, 7 October 2026)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:54:43 +00:00
igneum-labs
f078116c3b
release 0.3.22: proving on Devnet 3 opens (first segment submitted 18:45 BST, the sizing), the 0.3.21 warm cases end and why the relay cell reads on Devnet 3
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:52:42 +00:00
igneum-labs
313dc1f16b
release 0.3.21 section 7: the Mac entry LIVE 18:41:50 BST, Windows as its own entry, the parallel installer shapes, the testnet 6ed56f63 line, the 0.3.22 pin candidate 34a2dbaa, the signing bonus paragraph
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:42:54 +00:00
igneum-labs
59284364b5
release 0.3.22 section 6: DN3 GATE PASS, the two clocks, the tree order (a) to (f) with main's floor-file ruling, the project lead's nine-switch ruling and main's height mechanics, the testnet re-arm, the 0.3.21 Windows toolchain finding
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:40:37 +00:00
igneum-labs
a8753a60c0
release plans: 0.3.21 ships as the app tree over c4459193 (section 6, the GitHub exception window from 18:02 BST, the Windows path without windows.yml, the DMG 490919d9); 0.3.22 section 5 the Devnet 3 genesis on 69d1b56e at 18:06:19 BST (gates, pairs, the program id correction, the seed left off the sweep); rule 5 names the seeds in the wave list with a read-back line
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:25:23 +00:00
igneum-labs
0370961489
Counter ASIC 3.0 status: Devnet 3's pair agrees since 17:18Z (702 blocks, 0 rejected; first lock about 19:10Z on the 7,200-DAA window); the no-GitHub rule
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:20:43 +00:00
igneum-labs
e1e5db0f70
Counter ASIC 3.0 status: Devnet 3's epoch-0 program id fce15bf61030be57 (the id follows the seed; the pairing pin unchanged)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:12:25 +00:00
igneum-labs
ff2c7470c1
Counter ASIC 3.0 status: GitHub suspended (the mirror is the record), Devnet 3 mines on 69d1b56e from 17:06:19Z, the Hetzner seed still on the old object
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:09:33 +00:00
igneum-labs
dae386ef46
Counter ASIC 3.0 status: the 0.3.22 kaspa-pow suite green, master green on the pow fix, the chip texts live (incl. /claims), Devnet 3's first go refused on the genesis timestamp (8 Oct 00:00Z)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 17:03:06 +00:00
igneum-labs
e67deba19e
Counter ASIC 3.0 status: the pow stop-the-line executed (ca3-v4-amend on master as 363ec7ad, igneum-pow byte-identical to a5d735b2)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:48:07 +00:00
igneum-labs
363ec7ad8c
Merge ca3-v4-amend c44b4416 into master (gate: green on c44b4416, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-07 16:45:48 +00:00
igneum-labs
39f13fca13
Merge site-ui-5 e5e6b517 into master (gate: green on e5e6b517, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-07 16:45:01 +00:00
igneum-labs
c44b4416d4
Merge origin/master f8344773 into ca3-v4-amend (igneum-pow kept byte-identical to the frozen a5d735b2 per main's stop-the-line ruling; the ledger keeps both sides)
2026-10-07 16:40:29 +00:00
igneum-labs
b94c8e9f76
Counter ASIC 3.0 status: the 0.3.22 re-pin staged (bd710a36, candidate fa7f854f, byte 7 from genesis)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:39:34 +00:00
igneum-labs
0324527e03
Counter ASIC 3.0 status: the stop-the-line on master's pow suite (era-vdf's be4db4f3 against the pins), the hash lane's merge of e9cfe6c1 ordered, the condition verified
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:39:05 +00:00
igneum-labs
b8a56fea1f
Merge remote-tracking branch 'origin/master' into site-ui-5
2026-10-07 16:37:57 +00:00
igneum-labs
157aeeef0e
site-ui-5: the capture set after the padding sweep and the launch-first chip text (every route at 390 and 1440 dark, the three bands, the full wallet page)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:37:57 +00:00
igneum-labs
3f5d6d3f7c
site: the chip claim launch-first in the four public places (Counter ASIC lane, docs/plans/counter-asic-3-public-text-2026-10-07.md sections 1 to 4, on the project lead's "I thought we were making it 2.1 from launch?")
...
Home row 03, the litepaper's chip section at /litepaper#chip-model (paragraph and table; the class v3 row last, "never the launch
state"), the miner page's line and evidence.md row 17 in its eight columns: 2.1x to 3.9x under class v4 from the first block,
class v5 removing the stored-dataset chip as a category, the 5x to 9x only as the class v3 baseline, the devnet's activation
height as a devnet fact. The litepaper's abstract carried the same claim in the old form ("5x to 9x today; class v4, now on
the vote") and now reads launch-first too. tools/ci/ledger-text-check.mjs follows the sentences (X35 on the home page and the
litepaper). No disclosure prize anywhere.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:34:12 +00:00
igneum-labs
b6d99aff16
Counter ASIC 3.0 status: Devnet 3 now (0.3.22, genesis by 17:30Z), the frozen sub-version 3 handoff ( a5d735b2, byte 7, id a785001687d8688a, gates green, open items stated), the chip text rewritten launch-first
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:32:40 +00:00
igneum-labs
0aedcfb52f
The chip claim, public text: rewritten launch-first (2.1x to 3.9x under class v4 from genesis; class v5; the 5x to 9x only as the class v3 baseline; the devnet's height a devnet fact) on the project lead's word
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:25:18 +00:00
igneum-labs
12dfedab35
Counter ASIC 3.0 status: the four-seed tail ruled accepted (AP-F8-1 closes), 0.3.21's first candidate passes the node gates; the lane stops for tonight
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:17:54 +00:00
igneum-labs
6ee5619fd8
Counter ASIC 3.0 status: the 0.3.20 record (publish 14:54:17Z, floor 900,000, digest 4bbbe816, sweep complete 15:39Z, earliest flip about 14 Oct 23:00Z); sub-version 3 at a5d735b2 passes both gates with the named tail, the frozen generator for 0.3.22
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:11:02 +00:00
igneum-labs
e9cfe6c1a6
Counter ASIC 3.0 gates (hash): ledger AP-F8-1, F8's 64-seed gate and exhaustion count on a5d735b2 (60 of 64, the four over = the named tail; 0 exhausted of 24,631), the node's draw-cost line
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:03:13 +00:00
igneum-labs
4e83245506
Counter ASIC 3.0 status: release-0.3.21-node staged at 96161037 (byte 5, no re-pin), the set green, the floor file's digest 4bbbe816
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 16:01:00 +00:00
igneum-labs
f74059e05b
release plans on master: 0.3.20 live and swept (sections 38 and 39), the rules file with 4c and 14, the 0.3.21 plan as staged
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 15:41:42 +00:00
igneum-labs
c84bd7504b
Merge era-vdf be4db4f3 into master (gate: green on be4db4f3, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-07 15:31:24 +00:00
igneum-labs
2a2ffd263b
Counter ASIC 3.0 status: the hash lane's e0c77761 on origin, CI success; nothing in flight on the hash side
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 15:25:27 +00:00
igneum-labs
c88b00f578
Era VDF lane (7 October 2026): spec 04 sections 4.2, 4.4, 4.5 and 4.6 completed for the era path (the scheme byte and the hash-chain fallback, the cut rule under the O-4.3 reading, the day-of-blues input, the delay, the seed, the era constants as measured), spec 01 section 1.13.1 and era-layout.md section 8 updated, open items O-4.8 closed and O-4.10 to O-4.12 added, FUD ledger F11 updated, two decisions for the project lead in ledger-decisions.md, the record docs/analysis/era-vdf-2026-10-07.md (what was built, the parameters and measured rates, the harness gate with both runs, the cut rule for the finality lane, the verify gate, the tiers), the F7 re-roll harness against the real era cut (tools/era-vdf/reroll.mjs: --vdf off fires 6 of 6, --vdf on silent 0 of 6; the adversary evaluates asynchronously with the node's own code and is found by the node's own log line), the fast-time file's era fields
2026-10-07 15:24:22 +00:00
igneum-labs
9983f9cf6d
Merge master-pin-0320 6cb15004 into master (gate: green on 6cb15004, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-07 15:20:54 +00:00
igneum-labs
bf526104e1
Merge ca3-coord f9321c88 into master (gate: green on f9321c88, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-07 15:18:58 +00:00
igneum-labs
05ee47db79
Merge bench-5060ti dfb2e621 into master (gate: green on dfb2e621, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-07 15:17:18 +00:00
igneum-labs
f9321c8895
Counter ASIC 3.0 status: the census at a5d735b2 (0 lossy sites, 0 exhaustions, mean 2.086 attempts), CI success, the class check moving 2.0 percent of attempts
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 15:15:23 +00:00
igneum-labs
6cb1500410
master re-pinned to the published 0.3.20 node (c4459193): packaging/windows/node-source.pin against the live payload-inputs.json, so windows-ci's payload inputs step reads green; release rule 14, master re-pinned at every publish
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-07 15:13:10 +00:00
igneum-labs
e0c77761da
Counter ASIC 3.0 gates (hash): ledger AP-F8-1, the suite (103 of 103), CI and census lines at a5d735b2; the census draws in parallel
...
Suite at a5d735b2a3859c1f
2026-10-07 15:10:13 +00:00
igneum-labs
dfb2e6216f
RTX 5060 Ti (16 GB, Razer Core X V2 Thunderbolt) on PC 2: detection, G1 bit-exact on class v4 sub-version 1 and the v3 control, the 10-minute stock window, the bench-log entry, the card-picker entry and the public table row
...
The first 16 GB card and the first Thunderbolt card. The app's first poll listed it (vendor nvidia, 16,311 MiB,
driver 610.47 shared with the 5090, kind discrete: the app does not know it is an eGPU) and started a miner on
it by itself. Job run-5060ti-bench-20261007-b (tools/bench-5060ti/pc2-5060ti-bench.ps1, the card alone under
the runner's --cards-off, the 5090 mining, no power limit written: 180 W default read back unchanged, PC 2 lost
power twice that day): G1 PASS with 867dbc45cfb36b4d (sub-version 1) and 90f794dd556f7a3b equal to the Mac's;
the window 1,105 dispatches of 2^24 in 602 s at 30.882 MH/s, 114.8 W mean at utilisation 90 percent and over,
0.269 MH/W, PCIe 4.0 x4 through the enclosure (the hash is latency-bound, the link costs nothing measurable).
Owed: the efficient point (the app's Ember Tune; PC 2's Power Helper refuses every request since the restart)
and the prove-beside read (the shipped WSL2 host has no IGNEUM_CUDA_DEVICE selector; the floor server is on
PC 2; the prover-floor host is the cut). The kit (tools/bench-5060ti/make-kit.sh) takes the sub-version 1 packs
from ca3-v4-amend 38ce010d
2026-10-07 15:05:47 +00:00
