diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md
index 736acbbf5..87699838d 100644
--- a/docs/plans/counter-asic-3-status.md
+++ b/docs/plans/counter-asic-3-status.md
@@ -67,7 +67,21 @@ What moves the f = 1 rows (chip-model-v3.md section 5.7): not the dataset size (
 
 ## 6. Decisions for the project lead
 
-1. The public claim. "Under 2x" is true of the recompute chip per chip at the op budget and false of the stored-dataset chip per joule (item 1). Re-word to the measured fact (the honest card runs at 1/128 of its dependent-read ceiling; a chip must out-read it per watt) until the item 8 rows land, or keep the claim with "per chip, against the recompute chip" stated. Nothing changes on the site until the project lead's word.
+1. The public claim. "Under 2x" is true of the recompute chip per chip at the op budget and false of the stored-dataset chip per joule (item 1). Nothing on the site or in the litepaper changes from this run; the two drafts below are for the project lead's decision, with the rows that bound them.
+
+| Row | Per chip (rate) | Per joule | Source |
+|---|---|---|---|
+| On-die recompute chip, class v3 (f = 0) | 0.92x with the 3x factor (0.31x bare) | 1.86x (1.3x to 2.4x over the on-die read energy) | chip-model-v3.md sections 2 and 5.4, model |
+| Stored-dataset memory-controller chip, GDDR7 (f = 1) | 1.22x | 5.1x | chip-model-v3.md 5.4, model |
+| Stored-dataset chip, HBM3 one stack / eight stacks | 0.61x / 4.9x | 7.5x / 9.2x | chip-model-v3.md 5.4, model |
+| Ethash precedent, the same chip class: Linzhi Phoenix 2020, Antminer E9 2022, Jasminer X4 2021 | | 2.1x / 2.9x / 4.8x per joule | asic-resistance-history.md rows 3 and 4 |
+| With the latency shadow filled (item 8, model until measured) | 1.22x | 1.85x at N = 330,000 and a chip core equal to the GPU's ALU; 2.5x at 1.5x worse | chip-model-v3.md 5.7 |
+
+Draft (a), scoped: "The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090. A memory-controller chip that stores the whole dataset reaches 1.2x per chip and, in our model, 5x to 9x per joule; the Ethash chips of this class reached 2.1x to 4.8x. The lever against it, program work in the latency shadow, is being measured (Counter ASIC 3.0 item 8)."
+
+Draft (b), the measured fact only: "An RTX 5090 mines this hash at 136 MH/s and 17.5 billion dependent 4-byte reads a second, 82 percent of its memory's random-read ceiling, with its integer units at 0.15 percent of their budget. A chip beats it only by reading per watt what a 512-bit GDDR7 board reads, and the gap is the card's own idle logic."
+
+Either replaces "under 2x" on the site and in the litepaper once the project lead chooses; until then the claim stays as it is and this file records that it is not safe as worded.
 
 ## 7. Unverified and owed