diff --git a/app/igneum-app/tiers/class-v5-tiers.json b/app/igneum-app/tiers/class-v5-tiers.json new file mode 100644 index 000000000..612accda4 --- /dev/null +++ b/app/igneum-app/tiers/class-v5-tiers.json @@ -0,0 +1,1727 @@ +{ + "_about": "Ember Tune tiers per card class under class v5 (floor lane 4, the honest denominator, 8 October 2026; docs/analysis/class-v6/floor/denominator.md). One entry per card class: the three tiers (efficiency, balanced, max) as rows in the shape the app reads back from a card's state (src/ember.rs tier_from_json: id, clock_mhz, power_pct, mem_mhz, limit_w, mhs, w; mhw and source as Tier::json writes them), plus the fields this table adds: label (measured or estimated), uj (microjoules per hash at that point under class v5), note and src. clock_mhz 0 = unlocked; power_pct is percent of the card's default limit (50 to 100); AMD rows carry the ADLX offsets in core_offset_mhz and power_offset_pct instead (the app's AMD knob, 0.3.25). A card with no lever (Apple, Intel) has one tier, max, source stock. Nothing here is interpolated between measured rows: an estimated row is a prior the card's own search starts from and replaces; a measured row is the search's own result on that card.", + "class": "v5", + "class_string": "mx8-era+sh256x27+state (class v4's shape, 256 x 27 shadow, plus the state leaves)", + "v5_over_v4": { + "rate_pct": 0.0, + "watts_pct": 2.0, + "source": "the hash lane's v5lock job, 8 October 2026: at the 5090's 1,300 MHz knee class v5 125.93 MH/s at 299.8 W against class v4 125.92 at 294.0 W" + }, + "tier_ids": [ + "efficiency", + "balanced", + "max" + ], + "tier_rule": "efficiency = the best MH per watt row of the card's search outright (the knee or one rung past it); balanced = the best MH per watt row within 1 percent of the top rate (the default from install); max = the stock row (unlocked, 100 percent). The search measures; this table is where it starts and what it ships when it cannot run.", + "remeasure_rule": { + "stale_when": "the card's program class differs from the tiers' class (src/ember.rs tiers_stale): a set measured under class v4 never applies as current under class v5", + "on_flip": "the stored efficiency and balanced points are the provisional start of the re-measure, not its result: the search begins at the stored point and walks one rung either way (clock and power), the fingerprint checked on every step; the max tier is stock and is never stale", + "measured_flip": "v4 to v5 on the RTX 5090 at the 1,300 MHz lock: 0.0 percent of rate, +2.0 percent of watts (the v5lock job); the knee did not move", + "expected_flip_cost": "any class change that keeps the shadow's op count and mix inside the latency-bound band moves the knee by 0 to 1 rung; a change that doubles the op count moves the knee up (the 5090 at 431 W binds at 210,000 ops), so a class whose shadow leaves the band re-measures from stock, not from the stored point", + "period": "the stored set also re-measures weekly (PERIOD_S) and on a driver major change (the prior key carries driver major and class)" + }, + "cards": [ + { + "card": "NVIDIA GeForce RTX 5090", + "match": [ + "5090" + ], + "vendor": "nvidia", + "arch": "blackwell", + "memory_gb": 32, + "label": "measured", + "stock": { + "mhs": 136.8, + "w": 475.5, + "uj": 3.48, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1200, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 575, + "mhs": 133.8, + "w": 311.2, + "mhw": 0.4299, + "source": "measured", + "label": "measured", + "uj": 2.33, + "note": "class v4 best MH per watt (133.80 MH/s at 305.1 W, 2.2 percent of rate given); under class v5 +2.0 percent watts: 311.2 W, 2.33" + }, + { + "id": "balanced", + "clock_mhz": 1300, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 575, + "mhs": 134.76, + "w": 318.8, + "mhw": 0.4227, + "source": "measured", + "label": "measured", + "uj": 2.37, + "note": "the knee: class v4 134.76 MH/s at 312.5 W on the efficiency pass; under class v5 +2.0 percent watts: 318.8 W, 2.37 (the v5lock job read class v5 125.93 at 299.8 W with the one-warp-per-block worker: 2.38, the same energy at a lower rate)" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 575, + "mhs": 136.8, + "w": 475.5, + "mhw": 0.2877, + "source": "stock", + "label": "measured", + "uj": 3.48, + "note": "the power cap is flat on this hash (0.41 MH/W under every limit), so no power rung is used on any tier" + } + ], + "src": "docs/bench-log.md, the class v4 efficiency passes 7 to 8 October 2026 (PC 1); counter-asic-4-research.md 20.3" + }, + { + "card": "NVIDIA GeForce RTX 5080", + "match": [ + "5080" + ], + "vendor": "nvidia", + "arch": "blackwell", + "memory_gb": 16, + "label": "measured", + "stock": { + "mhs": 71.35, + "w": 248.0, + "uj": 3.48, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1100, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 360, + "mhs": 71.2, + "w": 146.6, + "mhw": 0.4857, + "source": "measured", + "label": "measured", + "uj": 2.06, + "note": "class v4 best MH per watt; the draw floors from 1,500 MHz down; the knee is between 1,000 and 900 MHz (900 costs 5.2 percent); class v5 about 2.10" + }, + { + "id": "balanced", + "clock_mhz": 1100, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 360, + "mhs": 71.2, + "w": 146.6, + "mhw": 0.4857, + "source": "measured", + "label": "measured", + "uj": 2.06, + "note": "the same row: the rate at 1,100 MHz is within 0.3 percent of unlocked" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 360, + "mhs": 71.35, + "w": 248.0, + "mhw": 0.2877, + "source": "stock", + "label": "measured", + "uj": 3.48, + "note": "class v5 measured on a Vast 5080 (13:49 UK): 71.35 MH/s at 248.0 W (3.48, 39 samples, SM 2,769, memory 14,801); class v3 71.16 at 159.4 W on the same host; PC 1 read class v4 71.41 at 253.1 W: the three agree within 3 percent on this card; stock, lock owed on the rented host" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5, class v5 kit, 200 batches of 2^24 under the 1 Hz sampler, 13:4x to 13:5x UK); stock, lock owed" + }, + { + "card": "NVIDIA GeForce RTX 5070 Ti", + "match": [ + "5070 TI", + "5070TI" + ], + "vendor": "nvidia", + "arch": "blackwell", + "memory_gb": 16, + "label": "estimated", + "stock": { + "mhs": 78.8, + "w": 224.0, + "uj": 2.84, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1100, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 300, + "mhs": 78.7, + "w": 131.0, + "mhw": 0.6008, + "source": "measured", + "label": "estimated", + "uj": 1.7, + "note": "the Blackwell shape applied to the measured stock rows (the v3 draw x0.63, the premium x0.5): band 1.6 to 2.0; the rented host refused -lgc, so the knee is the search's to find" + }, + { + "id": "balanced", + "clock_mhz": 1300, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 300, + "mhs": 78.8, + "w": 140.0, + "mhw": 0.5629, + "source": "measured", + "label": "estimated", + "uj": 1.81, + "note": "one rung above the efficiency point" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 300, + "mhs": 78.8, + "w": 224.0, + "mhw": 0.3518, + "source": "stock", + "label": "measured", + "uj": 2.84, + "note": "rented pod 8 October 10:09Z: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W; the class v5 sweep rented this card twice (14:08 and 14:13 UK) and neither host ever accepted the fleet key" + } + ], + "src": "docs/design/class-v6-rotating-family.md section 0 (the 5070 Ti column); the knee modelled on the 5080 and 5090 ladders" + }, + { + "card": "NVIDIA GeForce RTX 5070", + "match": [ + "5070" + ], + "vendor": "nvidia", + "arch": "blackwell", + "memory_gb": 12, + "label": "estimated", + "stock": { + "mhs": 58.9, + "w": 176.1, + "uj": 2.99, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1100, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 250, + "mhs": 58.9, + "w": 103.0, + "mhw": 0.5718, + "source": "measured", + "label": "estimated", + "uj": 1.75, + "note": "the Blackwell shape on the measured stock rows (paired class v3 113 W): band 1.7 to 2.1" + }, + { + "id": "balanced", + "clock_mhz": 1300, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 250, + "mhs": 58.9, + "w": 110.0, + "mhw": 0.5355, + "source": "measured", + "label": "estimated", + "uj": 1.87, + "note": "one rung above the efficiency point" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 250, + "mhs": 58.9, + "w": 176.1, + "mhw": 0.3344, + "source": "stock", + "label": "measured", + "uj": 2.99, + "note": "rented v4watts pod 8 October; the 7 October pod read class v3 52.0 MH/s at 102.8 W (the rate differs by host); the class v5 sweep rented this card twice (14:08 and 14:13 UK) and neither host ever accepted the fleet key" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the 8 October v4watts rows" + }, + { + "card": "NVIDIA GeForce RTX 5060 Ti", + "match": [ + "5060 TI", + "5060TI" + ], + "vendor": "nvidia", + "arch": "blackwell", + "memory_gb": 16, + "label": "estimated", + "stock": { + "mhs": 30.84, + "w": 123.9, + "uj": 4.02, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1100, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 180, + "mhs": 30.84, + "w": 72.7, + "mhw": 0.4243, + "source": "measured", + "label": "estimated", + "uj": 2.36, + "note": "the Blackwell shape on the PC 2 stock row: band 2.2 to 2.6; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium)" + }, + { + "id": "balanced", + "clock_mhz": 1300, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 180, + "mhs": 30.84, + "w": 80.5, + "mhw": 0.3829, + "source": "measured", + "label": "estimated", + "uj": 2.61, + "note": "one rung above the efficiency point" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 180, + "mhs": 30.84, + "w": 123.9, + "mhw": 0.2489, + "source": "stock", + "label": "measured", + "uj": 4.02, + "note": "class v5 measured on a Vast 5060 Ti (13:5x UK): 30.84 MH/s at 123.9 W (4.02, 96 samples, SM 2,835); class v3 30.75 at 82.6 W on the same host; PC 2's enclosure row read class v4 30.9 at 114.8 W; stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5, class v5 kit, 200 batches of 2^24 under the 1 Hz sampler, 13:4x to 13:5x UK); stock, lock owed" + }, + { + "card": "NVIDIA GeForce RTX 5060", + "match": [ + "5060" + ], + "vendor": "nvidia", + "arch": "blackwell", + "memory_gb": 8, + "label": "estimated", + "stock": { + "mhs": 30.8, + "w": 115.7, + "uj": 3.76, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1100, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 145, + "mhs": 30.8, + "w": 68.1, + "mhw": 0.4523, + "source": "measured", + "label": "estimated", + "uj": 2.21, + "note": "class v3 measured 31.27 MH/s at 75.4 W; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium)" + }, + { + "id": "balanced", + "clock_mhz": 1300, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 145, + "mhs": 30.8, + "w": 75.5, + "mhw": 0.4082, + "source": "measured", + "label": "estimated", + "uj": 2.45, + "note": "one rung above the efficiency point" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 145, + "mhs": 30.8, + "w": 115.7, + "mhw": 0.2662, + "source": "stock", + "label": "measured", + "uj": 3.76, + "note": "class v5 measured (13:51 UK): 30.80 MH/s at 115.7 W (3.76, 99 samples, SM 2,715, memory 13,801); class v3 30.76 at 78.8 W on the same host (the shadow +37 W = 12 pJ per op); stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5, class v5 kit, 200 batches of 2^24 under the 1 Hz sampler, 13:4x to 13:5x UK); stock, lock owed" + }, + { + "card": "NVIDIA GeForce RTX 4090", + "match": [ + "4090" + ], + "vendor": "nvidia", + "arch": "ada", + "memory_gb": 24, + "label": "estimated", + "stock": { + "mhs": 70.63, + "w": 353.5, + "uj": 5.0, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1860, + "power_pct": 60, + "mem_mhz": 0, + "limit_w": 450, + "mhs": 70.63, + "w": 252.5, + "mhw": 0.2797, + "source": "measured", + "label": "estimated", + "uj": 3.58, + "note": "the Ada shape (the 4070's measured tune: v3 x0.72, the premium x0.7) on the measured stock rows (class v3 253.4 W, class v4 353.5 W, floor lane 1, 8 October): band 3.3 to 4.0; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium)" + }, + { + "id": "balanced", + "clock_mhz": 2400, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 450, + "mhs": 70.63, + "w": 282.8, + "mhw": 0.2498, + "source": "measured", + "label": "estimated", + "uj": 4.0, + "note": "the Ada prior (a cap holds the rate until the SM clock falls under about 2,400 MHz)" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 450, + "mhs": 70.63, + "w": 353.5, + "mhw": 0.1998, + "source": "stock", + "label": "measured", + "uj": 5.0, + "note": "floor lane 1's rented 4090 at a 450 W limit: class v3 70.63 MH/s at 253.4 W (3.59), class v4 70.63 at 353.5 W (5.0); the denominator sweep's Vast 4090 carried a 250 W host limit: class v5 62.68 at 249.9 W (3.99, the SM at 2,579 MHz) and class v3 62.40 at 200.5 W, so a 250 W cap held 89 percent of the rate at 71 percent of the draw (an Ada cap row measured); stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5, class v5 kit, 200 batches of 2^24 under the 1 Hz sampler, 13:4x to 13:5x UK); stock, lock owed" + }, + { + "card": "NVIDIA GeForce RTX 4080", + "match": [ + "4080" + ], + "vendor": "nvidia", + "arch": "ada", + "memory_gb": 16, + "label": "estimated", + "stock": { + "mhs": 40.8, + "w": 200.7, + "uj": 4.92, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1860, + "power_pct": 60, + "mem_mhz": 0, + "limit_w": 320, + "mhs": 40.8, + "w": 143.3, + "mhw": 0.2847, + "source": "measured", + "label": "estimated", + "uj": 3.51, + "note": "the Ada shape on the measured stock rows (class v3 128.6 W, class v4 185.6 W): band 3.1 to 3.7; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium)" + }, + { + "id": "balanced", + "clock_mhz": 2400, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 320, + "mhs": 40.8, + "w": 160.6, + "mhw": 0.2541, + "source": "measured", + "label": "estimated", + "uj": 3.94, + "note": "the Ada prior" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 320, + "mhs": 40.8, + "w": 200.7, + "mhw": 0.2033, + "source": "stock", + "label": "measured", + "uj": 4.92, + "note": "class v5 measured (13:50 UK): 40.80 MH/s at 200.7 W (4.92, 72 samples, SM 2,760); class v3 40.69 at 141.5 W on the same host; the v4watts pod read class v4 40.74 at 185.6 W; stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5, class v5 kit, 200 batches of 2^24 under the 1 Hz sampler, 13:4x to 13:5x UK); stock, lock owed" + }, + { + "card": "NVIDIA GeForce RTX 4070", + "match": [ + "4070" + ], + "vendor": "nvidia", + "arch": "ada", + "memory_gb": 12, + "label": "measured", + "stock": { + "mhs": 28.43, + "w": 165.5, + "uj": 5.82, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1860, + "power_pct": 50, + "mem_mhz": 0, + "limit_w": 200, + "mhs": 31.08, + "w": 111.2, + "mhw": 0.2795, + "source": "measured", + "label": "measured", + "uj": 3.58, + "note": "Ember run 6's tune point (1,863 MHz at 50 percent) under class v4 (sh256x27): 31.08 MH/s at 109.0 W, +30 W over class v3 at the same point for no rate; class v5 about 3.58; the ladder below 1,860 under class v4 is owed (band 3.2 to 3.6)" + }, + { + "id": "balanced", + "clock_mhz": 2173, + "power_pct": 50, + "mem_mhz": 0, + "limit_w": 200, + "mhs": 31.1, + "w": 112.0, + "mhw": 0.2777, + "source": "measured", + "label": "estimated", + "uj": 3.6, + "note": "Ember run 6's 2,173 MHz rung (77.7 W on class v3) plus the measured 30 W class v4 premium" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 200, + "mhs": 28.43, + "w": 165.5, + "mhw": 0.1718, + "source": "stock", + "label": "measured", + "uj": 5.82, + "note": "class v5 measured on a Vast 4070 (13:54 UK): 28.43 MH/s at 165.5 W (5.82, 108 samples, SM 2,820, memory 9,801, a 210 W host limit not binding); class v3 28.40 at 116.3 W on the same host (the shadow +49 W = 17 pJ per op at the stock clock); Ember run 6's PC 1 stock on class v3 read 28.72 at 106.0 W; the tune point (1,860 MHz, 50 percent) under class v4 measured 31.08 at 109.0 W (3.51), so the lock takes 34 percent of this card's class v5 draw for no rate" + } + ], + "src": "docs/plans/counter-asic-3-status.md item 8 (the 4070 rows, 6 October); docs/bench-log.md Ember run 6" + }, + { + "card": "NVIDIA GeForce RTX 4070 Ti", + "match": [ + "4070 TI", + "4070TI" + ], + "vendor": "nvidia", + "arch": "ada", + "memory_gb": 12, + "label": "estimated", + "stock": { + "mhs": 31.26, + "w": 155.3, + "uj": 4.97, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1860, + "power_pct": 60, + "mem_mhz": 0, + "limit_w": 285, + "mhs": 31.26, + "w": 111.0, + "mhw": 0.2816, + "source": "measured", + "label": "estimated", + "uj": 3.6, + "note": "the Ada shape on the measured stock rows (class v3 95.4 W, class v4 155.3 W); the 4070 Super at a 110 W host cap held 31.26 MH/s at 108.4 W under class v4 (3.47): a cap row measured on a sibling" + }, + { + "id": "balanced", + "clock_mhz": 2400, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 285, + "mhs": 31.26, + "w": 125.0, + "mhw": 0.2501, + "source": "measured", + "label": "estimated", + "uj": 4.08, + "note": "the Ada prior" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 285, + "mhs": 31.26, + "w": 155.3, + "mhw": 0.2013, + "source": "stock", + "label": "measured", + "uj": 4.97, + "note": "rented pods 8 October" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, 8 October" + }, + { + "card": "NVIDIA GeForce RTX 4060 Ti", + "match": [ + "4060 TI", + "4060TI" + ], + "vendor": "nvidia", + "arch": "ada", + "memory_gb": 16, + "label": "estimated", + "stock": { + "mhs": 18.75, + "w": 99.8, + "uj": 5.32, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1860, + "power_pct": 60, + "mem_mhz": 0, + "limit_w": 165, + "mhs": 18.75, + "w": 71.4, + "mhw": 0.2625, + "source": "measured", + "label": "estimated", + "uj": 3.81, + "note": "the Ada shape (the 4070's measured tune: v3 x0.72, the premium x0.7) on the measured class v5 stock row; band 3.5 to 4.2" + }, + { + "id": "balanced", + "clock_mhz": 2400, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 165, + "mhs": 18.75, + "w": 79.8, + "mhw": 0.2348, + "source": "measured", + "label": "estimated", + "uj": 4.26, + "note": "the Ada prior" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 165, + "mhs": 18.75, + "w": 99.8, + "mhw": 0.1879, + "source": "stock", + "label": "measured", + "uj": 5.32, + "note": "class v5 measured on a Vast 4060 Ti (14:27 UK): 18.75 MH/s at 99.8 W (5.32) under a 140 W host limit; class v3 18.74 at 79.1 W on the same host (the shadow +21 W = 11 pJ per op; this host read 7 percent under the 7 October pod's 20.10 MH/s); the v4watts pod read class v4 20.10 at 102.3 W (5.09); stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5); stock, lock owed" + }, + { + "card": "NVIDIA GeForce RTX 4060", + "match": [ + "4060" + ], + "vendor": "nvidia", + "arch": "ada", + "memory_gb": 8, + "label": "estimated", + "stock": { + "mhs": 19.09, + "w": 95.0, + "uj": 4.98, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1860, + "power_pct": 60, + "mem_mhz": 0, + "limit_w": 115, + "mhs": 19.09, + "w": 72.0, + "mhw": 0.2651, + "source": "measured", + "label": "estimated", + "uj": 3.77, + "note": "19.09 MH/s measured on three rented hosts, the watts unread on every one (no power sensor): the watts are the 4060 Ti's shape; band 3.7 to 4.2" + }, + { + "id": "balanced", + "clock_mhz": 2400, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 115, + "mhs": 19.09, + "w": 80.0, + "mhw": 0.2386, + "source": "measured", + "label": "estimated", + "uj": 4.19, + "note": "the Ada prior" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 115, + "mhs": 19.09, + "w": 95.0, + "mhw": 0.2009, + "source": "stock", + "label": "estimated", + "uj": 4.98, + "note": "watts OWED: every rented 4060 host exposed no power sensor" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, 7 and 8 October (the rate); the watts modelled" + }, + { + "card": "NVIDIA GeForce RTX 3090", + "match": [ + "3090" + ], + "vendor": "nvidia", + "arch": "ampere", + "memory_gb": 24, + "label": "estimated", + "stock": { + "mhs": 61.49, + "w": 309.4, + "uj": 5.03, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1800, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 350, + "mhs": 61.0, + "w": 275.0, + "mhw": 0.2218, + "source": "measured", + "label": "estimated", + "uj": 4.51, + "note": "the Ampere cap lever (10 to 15 percent of the draw; a cap that takes the SM under 1,800 MHz costs rate) on the measured class v5 stock row; the 3090 Ti read class v3 61.95 MH/s at 249.5 W (4.03)" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 90, + "mem_mhz": 0, + "limit_w": 350, + "mhs": 61.49, + "w": 290.0, + "mhw": 0.212, + "source": "measured", + "label": "estimated", + "uj": 4.72, + "note": "one power rung under stock, no lock" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 350, + "mhs": 61.49, + "w": 309.4, + "mhw": 0.1987, + "source": "stock", + "label": "measured", + "uj": 5.03, + "note": "the denominator sweep, RunPod, 8 October 13:25 UK: class v3 60.01 MH/s at 294.6 W (4.91), class v5 61.49 at 309.4 W (5.03, 46 samples, SM 1,673 MHz, memory 9,501); the class v5 premium on this card 5 percent at stock; stock, lock owed (the host refused -lgc and -lmc)" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep 8 October (sweep 2026-10-08-denominator-v5)" + }, + { + "card": "NVIDIA GeForce RTX 3080", + "match": [ + "3080" + ], + "vendor": "nvidia", + "arch": "ampere", + "memory_gb": 10, + "label": "estimated", + "stock": { + "mhs": 50.71, + "w": 230.0, + "uj": 4.54, + "class": "v5 (modelled watts: the host's 170 W limit bound)" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1800, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 320, + "mhs": 50.0, + "w": 210.0, + "mhw": 0.2381, + "source": "measured", + "label": "estimated", + "uj": 4.2, + "note": "the Ampere cap lever (10 percent, no lower: a 170 W cap took 34 percent of the class v5 rate on this card, a 180 W cap 11 percent)" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 90, + "mem_mhz": 0, + "limit_w": 320, + "mhs": 50.71, + "w": 220.0, + "mhw": 0.2305, + "source": "measured", + "label": "estimated", + "uj": 4.34, + "note": "one power rung under stock" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 320, + "mhs": 50.71, + "w": 230.0, + "mhw": 0.2205, + "source": "stock", + "label": "estimated", + "uj": 4.54, + "note": "the sweep's two 3080 hosts both carried a limit under the class v5 draw: at 170 W class v3 50.71 MH/s at 169.2 W (3.34) held the rate and class v5 fell to 33.37 MH/s at 169.9 W (5.09) with the SM at 689 MHz; at 180 W class v3 49.83 at 177.8 W and class v5 44.31; the uncapped class v5 stock by the 3080 Ti's +30 percent: about 230 W (4.54); the Ampere cap under the shadow costs rate one for one: measured twice" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5, class v5 kit, 200 batches of 2^24 under the 1 Hz sampler, 13:4x to 13:5x UK); stock, lock owed" + }, + { + "card": "NVIDIA GeForce RTX 3070", + "match": [ + "3070" + ], + "vendor": "nvidia", + "arch": "ampere", + "memory_gb": 8, + "label": "estimated", + "stock": { + "mhs": 37.11, + "w": 196.4, + "uj": 5.29, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1800, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 220, + "mhs": 37.1, + "w": 178.0, + "mhw": 0.2084, + "source": "measured", + "label": "estimated", + "uj": 4.8, + "note": "the Ampere cap lever on the measured stock rows (class v3 142.3 W, class v4 196.4 W); the 3070 Ti 38.98 MH/s at 177.1 / 267.6 W" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 90, + "mem_mhz": 0, + "limit_w": 220, + "mhs": 37.11, + "w": 186.0, + "mhw": 0.1995, + "source": "measured", + "label": "estimated", + "uj": 5.01, + "note": "one power rung under stock" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 220, + "mhs": 37.11, + "w": 196.4, + "mhw": 0.189, + "source": "stock", + "label": "measured", + "uj": 5.29, + "note": "rented pods 8 October; the class v5 sweep's two 3070 hosts closed the connection mid-bench" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, 8 October" + }, + { + "card": "NVIDIA GeForce RTX 3060", + "match": [ + "3060" + ], + "vendor": "nvidia", + "arch": "ampere", + "memory_gb": 12, + "label": "estimated", + "stock": { + "mhs": 26.53, + "w": 169.8, + "uj": 6.4, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1800, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 170, + "mhs": 26.5, + "w": 153.0, + "mhw": 0.1732, + "source": "measured", + "label": "estimated", + "uj": 5.77, + "note": "the Ampere cap lever (10 percent) on the measured class v4 stock row; the 3060 Ti at a 130 W host cap held 33.06 MH/s at 128.7 W under class v4 (3.89): a cap row measured on a sibling" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 90, + "mem_mhz": 0, + "limit_w": 170, + "mhs": 26.53, + "w": 161.0, + "mhw": 0.1648, + "source": "measured", + "label": "estimated", + "uj": 6.07, + "note": "one power rung under stock" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 170, + "mhs": 26.53, + "w": 169.8, + "mhw": 0.1562, + "source": "stock", + "label": "measured", + "uj": 6.4, + "note": "class v5 measured on a Vast 3060 (13:53 UK): 26.53 MH/s at 169.8 W (6.40) at the host's 170 W limit (the limit binding: the class v4 pod read 26.89 at 166.1 W, 6.18); class v3 26.53 at 120.4 W on the same host; stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5); stock, lock owed" + }, + { + "card": "AMD Radeon RX 9070 XT", + "match": [ + "9070 XT", + "9070XT", + "GFX1201" + ], + "vendor": "amd", + "arch": "rdna4", + "memory_gb": 16, + "label": "measured", + "stock": { + "mhs": 18.9, + "w": 202.0, + "uj": 10.7, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 0, + "power_pct": 70, + "mem_mhz": 0, + "core_offset_mhz": -500, + "power_offset_pct": -30, + "limit_w": 304, + "mhs": 18.9, + "w": 149.3, + "mhw": 0.1266, + "source": "measured", + "label": "measured", + "uj": 7.9, + "note": "the ADLX grid (24 rows, PC 1): the rate flat at 18.9 MH/s across the grid, the best point -500 MHz core and -30 percent power, 24 percent under stock; class v5 about 8.1" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 85, + "mem_mhz": 0, + "core_offset_mhz": -300, + "power_offset_pct": -15, + "limit_w": 304, + "mhs": 18.9, + "w": 172.0, + "mhw": 0.1099, + "source": "measured", + "label": "estimated", + "uj": 9.1, + "note": "inside the flat band, half the offsets" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "core_offset_mhz": 0, + "power_offset_pct": 0, + "limit_w": 304, + "mhs": 18.9, + "w": 202.0, + "mhw": 0.0936, + "source": "stock", + "label": "measured", + "uj": 10.7, + "note": "the app's own power reading at the stock point, 8 October 07:11 UK" + } + ], + "src": "the hash lane's PC 1 AMD grid, 8 October 2026 12:13 BST; site/miner-bench.json" + }, + { + "card": "AMD Radeon RX 7900 XTX", + "match": [ + "7900 XTX", + "7900XTX" + ], + "vendor": "amd", + "arch": "rdna3", + "memory_gb": 24, + "label": "estimated", + "stock": { + "mhs": 28.0, + "w": 300.0, + "uj": 10.7, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 0, + "power_pct": 70, + "mem_mhz": 0, + "core_offset_mhz": -500, + "power_offset_pct": -30, + "limit_w": 355, + "mhs": 28.0, + "w": 224.0, + "mhw": 0.125, + "source": "measured", + "label": "estimated", + "uj": 8.0, + "note": "not rentable, not owned: the 9070 XT's dependent-read rate per channel (150 M per second per 32-bit channel) on 24 channels; the knob by the 9070 XT grid" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 85, + "mem_mhz": 0, + "core_offset_mhz": -300, + "power_offset_pct": -15, + "limit_w": 355, + "mhs": 28.0, + "w": 255.0, + "mhw": 0.1098, + "source": "measured", + "label": "estimated", + "uj": 9.1, + "note": "half the offsets" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "core_offset_mhz": 0, + "power_offset_pct": 0, + "limit_w": 355, + "mhs": 28.0, + "w": 300.0, + "mhw": 0.0933, + "source": "stock", + "label": "estimated", + "uj": 10.7, + "note": "modelled" + } + ], + "src": "modelled on the 9070 XT rows" + }, + { + "card": "AMD Radeon RX 7800 XT", + "match": [ + "7800 XT", + "7800XT" + ], + "vendor": "amd", + "arch": "rdna3", + "memory_gb": 16, + "label": "estimated", + "stock": { + "mhs": 18.0, + "w": 230.0, + "uj": 12.8, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 0, + "power_pct": 70, + "mem_mhz": 0, + "core_offset_mhz": -500, + "power_offset_pct": -30, + "limit_w": 263, + "mhs": 18.0, + "w": 171.0, + "mhw": 0.1053, + "source": "measured", + "label": "estimated", + "uj": 9.5, + "note": "16 channels of GDDR6 at the 9070 XT's per-channel rate; the knob by the 9070 XT grid" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 85, + "mem_mhz": 0, + "core_offset_mhz": -300, + "power_offset_pct": -15, + "limit_w": 263, + "mhs": 18.0, + "w": 195.0, + "mhw": 0.0923, + "source": "measured", + "label": "estimated", + "uj": 10.8, + "note": "half the offsets" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "core_offset_mhz": 0, + "power_offset_pct": 0, + "limit_w": 263, + "mhs": 18.0, + "w": 230.0, + "mhw": 0.0783, + "source": "stock", + "label": "estimated", + "uj": 12.8, + "note": "modelled" + } + ], + "src": "modelled on the 9070 XT rows" + }, + { + "card": "AMD Radeon RX 7600 XT", + "match": [ + "7600 XT", + "7600XT" + ], + "vendor": "amd", + "arch": "rdna3", + "memory_gb": 16, + "label": "estimated", + "stock": { + "mhs": 9.0, + "w": 160.0, + "uj": 17.8, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 0, + "power_pct": 70, + "mem_mhz": 0, + "core_offset_mhz": -500, + "power_offset_pct": -30, + "limit_w": 190, + "mhs": 9.0, + "w": 117.0, + "mhw": 0.0769, + "source": "measured", + "label": "estimated", + "uj": 13.0, + "note": "8 channels; the card-in queue holds one for a PC measurement" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 85, + "mem_mhz": 0, + "core_offset_mhz": -300, + "power_offset_pct": -15, + "limit_w": 190, + "mhs": 9.0, + "w": 136.0, + "mhw": 0.0662, + "source": "measured", + "label": "estimated", + "uj": 15.1, + "note": "half the offsets" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "core_offset_mhz": 0, + "power_offset_pct": 0, + "limit_w": 190, + "mhs": 9.0, + "w": 160.0, + "mhw": 0.0563, + "source": "stock", + "label": "estimated", + "uj": 17.8, + "note": "modelled" + } + ], + "src": "modelled on the 9070 XT rows" + }, + { + "card": "AMD Radeon RX 9060 XT", + "match": [ + "9060 XT", + "9060XT" + ], + "vendor": "amd", + "arch": "rdna4", + "memory_gb": 16, + "label": "estimated", + "stock": { + "mhs": 9.5, + "w": 130.0, + "uj": 13.7, + "class": "v4" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 0, + "power_pct": 70, + "mem_mhz": 0, + "core_offset_mhz": -500, + "power_offset_pct": -30, + "limit_w": 160, + "mhs": 9.5, + "w": 95.0, + "mhw": 0.1, + "source": "measured", + "label": "estimated", + "uj": 10.0, + "note": "8 channels of GDDR6 on RDNA 4; the card-in queue holds one" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 85, + "mem_mhz": 0, + "core_offset_mhz": -300, + "power_offset_pct": -15, + "limit_w": 160, + "mhs": 9.5, + "w": 110.0, + "mhw": 0.0864, + "source": "measured", + "label": "estimated", + "uj": 11.6, + "note": "half the offsets" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "core_offset_mhz": 0, + "power_offset_pct": 0, + "limit_w": 160, + "mhs": 9.5, + "w": 130.0, + "mhw": 0.0731, + "source": "stock", + "label": "estimated", + "uj": 13.7, + "note": "modelled" + } + ], + "src": "modelled on the 9070 XT rows" + }, + { + "card": "NVIDIA H100 80GB HBM3", + "match": [ + "H100" + ], + "vendor": "nvidia", + "arch": "hopper", + "memory_gb": 80, + "label": "estimated", + "stock": { + "mhs": 241.3, + "w": 621.6, + "uj": 2.58, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1400, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 700, + "mhs": 250.0, + "w": 500.0, + "mhw": 0.5, + "source": "measured", + "label": "estimated", + "uj": 2.0, + "note": "the premium 240 to 280 W at stock says half of it is the clock; a lock on an owned host (Hopper at 1,980 MHz boost, HBM3-bound): about 500 W (2.0); band 1.9 to 2.4; rented hosts refuse -lgc" + }, + { + "id": "balanced", + "clock_mhz": 1600, + "power_pct": 90, + "mem_mhz": 0, + "limit_w": 700, + "mhs": 250.6, + "w": 560.0, + "mhw": 0.4475, + "source": "measured", + "label": "estimated", + "uj": 2.23, + "note": "one rung above" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 700, + "mhs": 241.3, + "w": 621.6, + "mhw": 0.3882, + "source": "stock", + "label": "measured", + "uj": 2.58, + "note": "the denominator sweep, RunPod, 13:25 UK: class v3 252.96 MH/s at 382.4 W (1.51), class v5 241.34 at 621.6 W (2.58, 7 samples, the SM throttled to 1,590 MHz under the 700 W cap); the 7 and 8 October pods read class v4 250.6 at 695.1 W (2.77); -lmc answered 'use --lock-memory-clocks-deferred' and the memory clock stayed 2,619; stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, 8 October" + }, + { + "card": "NVIDIA L40S", + "match": [ + "L40S" + ], + "vendor": "nvidia", + "arch": "ada", + "memory_gb": 48, + "label": "estimated", + "stock": { + "mhs": 56.49, + "w": 298.7, + "uj": 5.29, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1860, + "power_pct": 60, + "mem_mhz": 0, + "limit_w": 350, + "mhs": 56.49, + "w": 213.5, + "mhw": 0.2646, + "source": "measured", + "label": "estimated", + "uj": 3.78, + "note": "the Ada shape on the measured stock rows (class v3 220.7 W, class v4 277.6 W); re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium)" + }, + { + "id": "balanced", + "clock_mhz": 2400, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 350, + "mhs": 56.49, + "w": 239.0, + "mhw": 0.2364, + "source": "measured", + "label": "estimated", + "uj": 4.23, + "note": "the Ada prior" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 350, + "mhs": 56.49, + "w": 298.7, + "mhw": 0.1891, + "source": "stock", + "label": "measured", + "uj": 5.29, + "note": "class v5 measured (13:49 UK): 56.49 MH/s at 298.7 W (5.29, 46 samples, SM 2,520); class v3 56.35 at 221.5 W on the same host; the v4watts pod read class v4 56.4 at 277.6 W; stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, the denominator sweep (2026-10-08-denominator-v5, class v5 kit, 200 batches of 2^24 under the 1 Hz sampler, 13:4x to 13:5x UK); stock, lock owed" + }, + { + "card": "NVIDIA A100-SXM4-80GB", + "match": [ + "A100" + ], + "vendor": "nvidia", + "arch": "ampere", + "memory_gb": 80, + "label": "estimated", + "stock": { + "mhs": 133.1, + "w": 398.1, + "uj": 2.99, + "class": "v5" + }, + "tiers": [ + { + "id": "efficiency", + "clock_mhz": 1200, + "power_pct": 80, + "mem_mhz": 0, + "limit_w": 400, + "mhs": 133.0, + "w": 385.0, + "mhw": 0.3455, + "source": "measured", + "label": "estimated", + "uj": 2.89, + "note": "the card already runs at 1,410 MHz and the 400 W host limit binds under class v5 (SM clock gives); a cap under it costs rate on Ampere, so the floor is within 5 percent of the measured stock row" + }, + { + "id": "balanced", + "clock_mhz": 0, + "power_pct": 90, + "mem_mhz": 0, + "limit_w": 400, + "mhs": 133.1, + "w": 392.0, + "mhw": 0.3396, + "source": "measured", + "label": "estimated", + "uj": 2.95, + "note": "one power rung under stock" + }, + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 400, + "mhs": 133.1, + "w": 398.1, + "mhw": 0.3343, + "source": "stock", + "label": "measured", + "uj": 2.99, + "note": "the denominator sweep, RunPod, 13:24 UK: class v3 138.06 MH/s at 294.9 W (2.14), class v5 133.11 at 398.1 W (2.99, 19 samples, at the host's 400 W limit, memory 1,593 MHz); the v4watts pod on a 500 W host read class v4 138.0 at 489.3 W (3.54); -lmc 'not supported' on this card; stock, lock owed" + } + ], + "src": "~/igneum-fleet/cardbench/rows.jsonl, 8 October" + }, + { + "card": "Intel Arc B580", + "match": [ + "B580" + ], + "vendor": "intel", + "arch": "battlemage", + "memory_gb": 12, + "label": "estimated", + "stock": { + "mhs": 10.6, + "w": 110.0, + "uj": 10.4, + "class": "v4" + }, + "tiers": [ + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 190, + "mhs": 10.6, + "w": 110.0, + "mhw": 0.0964, + "source": "stock", + "label": "estimated", + "uj": 10.4, + "note": "10.6 to 11 MH/s measured on PC 2 (the enclosure), the watts unread; about 110 W by the board's class (OWED); no clock lever in the app for Intel" + } + ], + "src": "docs/bench-log.md, 7 October; site/miner-bench.json" + }, + { + "card": "Intel Arc A750", + "match": [ + "A750" + ], + "vendor": "intel", + "arch": "alchemist", + "memory_gb": 8, + "label": "estimated", + "stock": { + "mhs": 8.0, + "w": 150.0, + "uj": 18.8, + "class": "v4" + }, + "tiers": [ + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 225, + "mhs": 8.0, + "w": 150.0, + "mhw": 0.0533, + "source": "stock", + "label": "estimated", + "uj": 18.8, + "note": "unmeasured; modelled from the B580 and the Alchemist board" + } + ], + "src": "modelled" + }, + { + "card": "Apple M5 Max", + "match": [ + "M5 MAX" + ], + "vendor": "apple", + "arch": "apple-m5", + "memory_gb": 0, + "label": "measured", + "stock": { + "mhs": 26.67, + "w": 37.3, + "uj": 1.4, + "class": "v4" + }, + "tiers": [ + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 0, + "mhs": 26.67, + "w": 37.3, + "mhw": 0.715, + "source": "stock", + "label": "measured", + "uj": 1.4, + "note": "the GPU and DRAM channels of the IOReport meter (not the wall): class v3 27.08 MH/s at 21.0 W (0.78), class v4 26.67 at 37.3 W (1.40), class v5 about 1.43; the package about 17 W more; no lever (no clock cap on Apple silicon)" + } + ], + "src": "docs/analysis/latency-shadow-2026-10-06.md section 3; docs/plans/ember-tune.md (the package figure)" + }, + { + "card": "Apple M4 Max", + "match": [ + "M4 MAX" + ], + "vendor": "apple", + "arch": "apple-m4", + "memory_gb": 0, + "label": "estimated", + "stock": { + "mhs": 26.0, + "w": 40.0, + "uj": 1.55, + "class": "v5" + }, + "tiers": [ + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 0, + "mhs": 26.0, + "w": 40.0, + "mhw": 0.65, + "source": "stock", + "label": "estimated", + "uj": 1.55, + "note": "the same 512-bit LPDDR5X (8,533 against 9,600 MT/s) and a 40-core GPU on N3E: about 26 MH/s; class v3 about 0.85 at the meter, class v5 about 1.55 (the M5 Max's rows scaled); a devnet row from an unnamed Apple laptop read 24.3 MH/s on class v4" + } + ], + "src": "modelled on the M5 Max rows" + }, + { + "card": "Apple M4 Pro", + "match": [ + "M4 PRO" + ], + "vendor": "apple", + "arch": "apple-m4", + "memory_gb": 0, + "label": "estimated", + "stock": { + "mhs": 13.5, + "w": 22.0, + "uj": 1.65, + "class": "v5" + }, + "tiers": [ + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 0, + "mhs": 13.5, + "w": 22.0, + "mhw": 0.6136, + "source": "stock", + "label": "estimated", + "uj": 1.65, + "note": "256-bit LPDDR5X and a 20-core GPU: about 13.5 MH/s; the shadow's per-hash premium does not shrink with the part, so class v5 reads about 1.65 at the meter" + } + ], + "src": "modelled on the M5 Max rows" + }, + { + "card": "Apple M3 Max", + "match": [ + "M3 MAX" + ], + "vendor": "apple", + "arch": "apple-m3", + "memory_gb": 0, + "label": "estimated", + "stock": { + "mhs": 24.0, + "w": 42.0, + "uj": 1.75, + "class": "v5" + }, + "tiers": [ + { + "id": "max", + "clock_mhz": 0, + "power_pct": 100, + "mem_mhz": 0, + "limit_w": 0, + "mhs": 24.0, + "w": 42.0, + "mhw": 0.5714, + "source": "stock", + "label": "estimated", + "uj": 1.75, + "note": "512-bit LPDDR5-6400 and a 40-core GPU on N3B: about 24 MH/s; class v5 about 1.75 at the meter" + } + ], + "src": "modelled on the M5 Max rows" + } + ] +} diff --git a/app/igneum-app/tiers/class-v5-tiers.mjs b/app/igneum-app/tiers/class-v5-tiers.mjs new file mode 100644 index 000000000..1e89fc3ba --- /dev/null +++ b/app/igneum-app/tiers/class-v5-tiers.mjs @@ -0,0 +1,100 @@ +// The class v5 tiers table (app/igneum-app/tiers/class-v5-tiers.json): the loader and the validator the test and the +// app's packaging read it through. The rows are in the shape src/ember.rs tier_from_json reads back from a card's state +// (id, clock_mhz, power_pct, mem_mhz, limit_w, mhs, w), so a card whose own search has not run can be set to a tier +// from this table by /api/tune/tier, and the search replaces the row when it runs. node --test class-v5-tiers.test.mjs +import { readFileSync } from 'node:fs'; +import { fileURLToPath } from 'node:url'; +import { dirname, join } from 'node:path'; + +export const TIER_IDS = ['efficiency', 'balanced', 'max']; +export const LABELS = ['measured', 'estimated']; +export const SOURCES = ['measured', 'stock']; +export const VENDORS = ['nvidia', 'amd', 'apple', 'intel']; +// the fields tier_from_json reads, every one a number +export const ROW_FIELDS = ['clock_mhz', 'power_pct', 'mem_mhz', 'limit_w', 'mhs', 'w']; +// the brief's card classes (floor lane 4, 8 October 2026): every one must have an entry +export const REQUIRED_CARDS = ['5090', '5080', '5070 Ti', '5070', '5060 Ti', '5060', '4090', '4080', '4070', '3090', '3080', '3070', '3060', + '9070 XT', '7900 XTX', '7800 XT', '7600 XT', '9060 XT', 'H100', 'L40S', 'A100', 'B580', 'A750', 'M5 Max', 'M4 Max', 'M4 Pro', 'M3 Max']; + +export function loadTable(path) { + const p = path || join(dirname(fileURLToPath(import.meta.url)), 'class-v5-tiers.json'); + return JSON.parse(readFileSync(p, 'utf8')); +} + +/** Every fault in the table as a list of strings; an empty list is a valid table. */ +export function validate(t) { + const faults = []; + const f = (s) => faults.push(s); + if (t.class !== 'v5') f(`class is ${t.class}, not v5`); + if (!Array.isArray(t.tier_ids) || t.tier_ids.join() !== TIER_IDS.join()) f('tier_ids must be efficiency, balanced, max'); + for (const k of ['stale_when', 'on_flip', 'measured_flip', 'period']) if (!t.remeasure_rule || typeof t.remeasure_rule[k] !== 'string' || !t.remeasure_rule[k]) f(`remeasure_rule.${k} missing`); + if (!t.v5_over_v4 || typeof t.v5_over_v4.watts_pct !== 'number') f('v5_over_v4.watts_pct missing'); + if (!Array.isArray(t.cards) || t.cards.length === 0) { f('cards missing'); return faults; } + const seen = new Set(); + for (const c of t.cards) { + const name = c.card || '(unnamed)'; + if (seen.has(name)) f(`${name}: listed twice`); + seen.add(name); + if (!VENDORS.includes(c.vendor)) f(`${name}: vendor ${c.vendor}`); + if (!LABELS.includes(c.label)) f(`${name}: label ${c.label}`); + if (!Array.isArray(c.match) || c.match.length === 0) f(`${name}: no match list`); + if (typeof c.src !== 'string' || !c.src) f(`${name}: no src`); + if (!c.stock || typeof c.stock.uj !== 'number' || c.stock.uj <= 0) f(`${name}: stock.uj missing`); + if (!Array.isArray(c.tiers) || c.tiers.length === 0) { f(`${name}: no tiers`); continue; } + const ids = c.tiers.map((r) => r.id); + for (const id of ids) if (!TIER_IDS.includes(id)) f(`${name}: tier id ${id}`); + if (new Set(ids).size !== ids.length) f(`${name}: a tier id repeats`); + const lever = c.vendor === 'nvidia' || c.vendor === 'amd'; + if (lever && ids.join() !== TIER_IDS.join()) f(`${name}: a card with a lever carries all three tiers in order`); + if (!lever && ids.join() !== 'max') f(`${name}: a card with no lever carries the max tier only`); + for (const r of c.tiers) { + for (const k of ROW_FIELDS) if (typeof r[k] !== 'number' || !Number.isFinite(r[k])) f(`${name}/${r.id}: ${k} is not a number`); + if (typeof r.power_pct === 'number' && (r.power_pct < 50 || r.power_pct > 100)) f(`${name}/${r.id}: power_pct ${r.power_pct} outside 50 to 100`); + if (typeof r.clock_mhz === 'number' && (r.clock_mhz < 0 || r.clock_mhz > 4000)) f(`${name}/${r.id}: clock_mhz ${r.clock_mhz}`); + if (!LABELS.includes(r.label)) f(`${name}/${r.id}: label ${r.label}`); + if (!SOURCES.includes(r.source)) f(`${name}/${r.id}: source ${r.source}`); + if (typeof r.uj !== 'number' || r.uj <= 0) f(`${name}/${r.id}: uj missing`); + if (typeof r.note !== 'string' || !r.note) f(`${name}/${r.id}: no note`); + if (r.mhs > 0 && r.w > 0 && r.uj > 0 && Math.abs(r.w / r.mhs - r.uj) / r.uj > 0.025) f(`${name}/${r.id}: uj ${r.uj} is not w over mhs (${(r.w / r.mhs).toFixed(2)})`); + if (r.mhs > 0 && r.w > 0 && typeof r.mhw === 'number' && Math.abs(r.mhs / r.w - r.mhw) / r.mhw > 0.025) f(`${name}/${r.id}: mhw ${r.mhw} is not mhs over w`); + if (r.id === 'max' && r.source !== 'stock') f(`${name}/max: the max tier is the stock row`); + if (r.id === 'max' && (r.clock_mhz !== 0 || r.power_pct !== 100)) f(`${name}/max: stock is unlocked at 100 percent`); + if (c.vendor === 'amd' && (typeof r.core_offset_mhz !== 'number' || typeof r.power_offset_pct !== 'number')) f(`${name}/${r.id}: an AMD row carries core_offset_mhz and power_offset_pct`); + if (c.vendor === 'amd' && r.core_offset_mhz > 0) f(`${name}/${r.id}: an AMD core offset never raises the clock`); + } + const by = Object.fromEntries(c.tiers.map((r) => [r.id, r])); + if (by.efficiency && by.max && by.efficiency.uj > by.max.uj) f(`${name}: efficiency costs more per hash than stock`); + if (by.efficiency && by.balanced && by.balanced.uj + 1e-9 < by.efficiency.uj) f(`${name}: balanced is cheaper per hash than efficiency`); + if (by.balanced && by.max && by.balanced.mhs > 0 && by.max.mhs > 0 && by.balanced.mhs < by.max.mhs * 0.98) f(`${name}: balanced gives up over 2 percent of the top rate`); + if (c.label === 'measured' && !c.tiers.some((r) => r.label === 'measured' && r.source === 'measured') && lever) f(`${name}: a measured card has no measured tuned row`); + } + for (const want of REQUIRED_CARDS) if (!t.cards.some((c) => c.card.includes(want))) f(`no entry for ${want}`); + return faults; +} + +/** The entry a card name matches (the first whose match list hits; the longer match wins, so "5070 Ti" beats "5070"). */ +export function entryFor(t, cardName) { + const n = cardName.toUpperCase(); + let best = null, bestLen = 0; + for (const c of t.cards) for (const m of c.match) if (n.includes(m.toUpperCase()) && m.length > bestLen) { best = c; bestLen = m.length; } + return best; +} + +/** The tier row a card starts from, in the shape tier_from_json reads; null when the table has none. */ +export function tierRow(t, cardName, id) { + const c = entryFor(t, cardName); + if (!c) return null; + return c.tiers.find((r) => r.id === id) || null; +} + +/** The re-measure verdict the app applies on a class flip (src/ember.rs tiers_stale): stale when both classes are known and differ. */ +export function stale(tiersClass, programClass) { + return Boolean(tiersClass) && Boolean(programClass) && tiersClass !== programClass; +} + +if (process.argv[1] && fileURLToPath(import.meta.url) === process.argv[1]) { + const t = loadTable(); + const faults = validate(t); + if (faults.length) { console.error(faults.join('\n')); process.exit(1); } + console.log(`class ${t.class}: ${t.cards.length} card classes, ${t.cards.filter((c) => c.label === 'measured').length} measured`); +} diff --git a/app/igneum-app/tiers/class-v5-tiers.test.mjs b/app/igneum-app/tiers/class-v5-tiers.test.mjs new file mode 100644 index 000000000..087379df8 --- /dev/null +++ b/app/igneum-app/tiers/class-v5-tiers.test.mjs @@ -0,0 +1,109 @@ +// node --test app/igneum-app/tiers/class-v5-tiers.test.mjs +// The class v5 tiers table: the shipped file validates; the measured rows carry the record's numbers; the match rule +// picks the longer name; a class flip reads stale; and the known-failed cases (a bad power rung, a missing field, a +// tuned row dearer than stock, a card class left out) are refused, so a stale or broken table cannot pass. +import { test } from 'node:test'; +import assert from 'node:assert/strict'; +import { loadTable, validate, entryFor, tierRow, stale, REQUIRED_CARDS, ROW_FIELDS } from './class-v5-tiers.mjs'; + +const clone = (t) => JSON.parse(JSON.stringify(t)); + +test('the shipped table validates with no faults', () => { + const t = loadTable(); + assert.deepEqual(validate(t), []); + assert.equal(t.class, 'v5'); + assert.ok(t.cards.length >= REQUIRED_CARDS.length); +}); + +test('the measured rows are the record\'s (the 5090 at its 1,300 MHz knee, the 5080 at 1,100, the 4070 at its tune, the 9070 XT grid, the M5 Max meter)', () => { + const t = loadTable(); + const r5090 = tierRow(t, 'NVIDIA GeForce RTX 5090', 'balanced'); + assert.equal(r5090.clock_mhz, 1300); + assert.equal(r5090.label, 'measured'); + assert.ok(Math.abs(r5090.uj - 2.38) < 0.01, `the 5090 balanced row reads 2.38 microjoules under class v5: ${r5090.uj}`); + const e5090 = tierRow(t, 'NVIDIA GeForce RTX 5090', 'efficiency'); + assert.equal(e5090.clock_mhz, 1200); + const r5080 = tierRow(t, 'NVIDIA GeForce RTX 5080', 'efficiency'); + assert.equal(r5080.clock_mhz, 1100); + assert.ok(Math.abs(r5080.uj - 2.06) < 0.01); + const r4070 = tierRow(t, 'NVIDIA GeForce RTX 4070', 'efficiency'); + assert.equal(r4070.clock_mhz, 1860); + assert.equal(r4070.power_pct, 50); + const amd = tierRow(t, 'AMD Radeon RX 9070 XT', 'efficiency'); + assert.equal(amd.core_offset_mhz, -500); + assert.equal(amd.power_offset_pct, -30); + assert.ok(Math.abs(amd.w - 149.3) < 0.01); + const apple = entryFor(t, 'Apple M5 Max'); + assert.equal(apple.tiers.length, 1); + assert.equal(apple.tiers[0].id, 'max'); + assert.ok(Math.abs(apple.tiers[0].uj - 1.40) < 0.01); +}); + +test('every entry carries the three tiers where the card has a lever, and only max where it has none', () => { + const t = loadTable(); + for (const c of t.cards) { + const ids = c.tiers.map((r) => r.id).join(); + if (c.vendor === 'nvidia' || c.vendor === 'amd') assert.equal(ids, 'efficiency,balanced,max', c.card); + else assert.equal(ids, 'max', c.card); + for (const r of c.tiers) for (const k of ROW_FIELDS) assert.equal(typeof r[k], 'number', `${c.card}/${r.id}.${k}`); + } +}); + +test('the match rule takes the longer name: a 5070 Ti is not a 5070, a 4060 Ti is not a 4060, a 9060 XT is not a 9070 XT', () => { + const t = loadTable(); + assert.equal(entryFor(t, 'NVIDIA GeForce RTX 5070 Ti').card, 'NVIDIA GeForce RTX 5070 Ti'); + assert.equal(entryFor(t, 'NVIDIA GeForce RTX 5070').card, 'NVIDIA GeForce RTX 5070'); + assert.equal(entryFor(t, 'NVIDIA GeForce RTX 4060 Ti').card, 'NVIDIA GeForce RTX 4060 Ti'); + assert.equal(entryFor(t, 'NVIDIA GeForce RTX 4060').card, 'NVIDIA GeForce RTX 4060'); + assert.equal(entryFor(t, 'AMD Radeon RX 9060 XT').card, 'AMD Radeon RX 9060 XT'); + assert.equal(entryFor(t, 'amd:gfx1201').card, 'AMD Radeon RX 9070 XT'); + assert.equal(entryFor(t, 'NVIDIA GeForce GTX 1080 Ti'), null); + assert.equal(tierRow(t, 'NVIDIA GeForce GTX 1080 Ti', 'max'), null); +}); + +test('a class flip reads stale exactly as src/ember.rs tiers_stale does', () => { + assert.equal(stale('v4', 'v5'), true); + assert.equal(stale('v5', 'v5'), false); + assert.equal(stale('', 'v5'), false); + assert.equal(stale('v4', ''), false); + const t = loadTable(); + assert.ok(t.remeasure_rule.measured_flip.includes('0.0 percent of rate')); + assert.equal(t.v5_over_v4.watts_pct, 2.0); +}); + +test('known-failed: a power rung under 50 is refused', () => { + const t = clone(loadTable()); + t.cards[0].tiers[0].power_pct = 40; + assert.ok(validate(t).some((s) => s.includes('power_pct 40'))); +}); + +test('known-failed: a row missing a field tier_from_json reads is refused', () => { + const t = clone(loadTable()); + delete t.cards[1].tiers[1].limit_w; + assert.ok(validate(t).some((s) => s.includes('limit_w is not a number'))); +}); + +test('known-failed: a tuned row dearer per hash than stock is refused, and a max tier that is not stock', () => { + const t = clone(loadTable()); + const c = t.cards.find((x) => x.card.includes('4080')); + c.tiers[0].uj = c.tiers[2].uj + 1; c.tiers[0].w = c.tiers[0].uj * c.tiers[0].mhs; c.tiers[0].mhw = c.tiers[0].mhs / c.tiers[0].w; + assert.ok(validate(t).some((s) => s.includes('efficiency costs more per hash than stock'))); + const u = clone(loadTable()); + u.cards[0].tiers[2].clock_mhz = 1500; + assert.ok(validate(u).some((s) => s.includes('stock is unlocked at 100 percent'))); +}); + +test('known-failed: a card class of the brief left out is refused, and a stale uj (not w over mhs) is refused', () => { + const t = clone(loadTable()); + t.cards = t.cards.filter((c) => !c.card.includes('3060')); + assert.ok(validate(t).some((s) => s === 'no entry for 3060')); + const u = clone(loadTable()); + u.cards[0].tiers[1].uj = 9.99; + assert.ok(validate(u).some((s) => s.includes('is not w over mhs'))); +}); + +test('known-failed: a table under another class is refused', () => { + const t = clone(loadTable()); + t.class = 'v4'; + assert.ok(validate(t).some((s) => s.includes('not v5'))); +}); diff --git a/docs/analysis/class-v6/census-w16-mix.md b/docs/analysis/class-v6/census-w16-mix.md new file mode 100644 index 000000000..ea41ba25d --- /dev/null +++ b/docs/analysis/class-v6/census-w16-mix.md @@ -0,0 +1,139 @@ +# Class v6 census: the read width W = 16 and the op-mix re-weight through the sub-version 3 rules + +8 October 2026, 13:2x to 14:1x UK, branch `class-v6-census` from `counter-asic-4` (base 4bb4c0ca), the census lane of the Counter ASIC 4.0 research under the Counter ASIC coordinator. The question: two class v6 changes are about to be chosen (the read width W = 16 words, the whole 64-byte item, the existing class `w64`; and an op-mix re-weight toward the families the k lane's RTL rows rank hardest for a programmable chip core), and neither may enter the class without the sub-version 3 rules. This file carries the census rows, the exact commands, and PASS or FAIL per candidate. Every number is measured on build-3 (igneum-build-3, 32 threads) or build-4 (igneum-build-4, 96 threads) under the lease pool at nice 19, measure class, owner `class-v6-census`; nothing ran on the Mac; nothing here touches the devnet, the testnet object or any served number. + +## 0. One page + +Both class v6 changes pass the sub-version 3 rules, measured, on 256 seeds each without an era and 256 seeds each across eight drawn eras, on build-3 and build-4 between 13:37 and 14:05 UK. + +- **(a) W = 16, the whole 64-byte item, at the current mix: PASS.** 256 of 256 seeds accepted without an era (0 exhausted at the 256 cap, 0.704 rejection per candidate against the record's 0.668 and the 0.986 to 0.990 death line), 256 of 256 across eras 0 to 7 with the value-level window-bit test switched on as a refusal (0 refusals for the instrument's reason; 189 refusals at the era's stride bit against the control's 218, the record's own class on today's `load_index`), the (c''') floor refusing 1.4 percent of candidates, the F8-form top-0.1-percent share 0.999 to 1.006 of the uniform control at 2^20, the verifier +0.6 percent within a 4 percent drift. It is the cleanest address of the three: at 16 words the product's low bits 0 to 3 are alignment and never enter the address (the control carries that law at bit 0 in 116 of 256 programs). +- **(b) W = 4 at the re-weighted mix (13, 11, 6, 10, 8, 8, 7, 2, 6, 4: mulhi 6 to 2, mul 8 to 6, mad 8 to 10, add, xor, rotl, sub +1 each): PASS on the rules.** 256 of 256 both ways, 0 exhausted, rejection 0.407 (the fewest lossy ops), (c''') 1.2 percent, verifier within drift. Weaker than (a) on the address: at 4 words the product law lands on bit 2 (75 of 256 programs), and the extra `mad` raises the stride-bit refusals to 1.6 per seed on the eras whose R is in range (the control 1.2). +- **(c) both: PASS on the rules**, 256 of 256 both ways, rejection 0.426, (c''') 3.4 percent, F8-form 0.999 to 1.002, verifier -0.1 percent; the address as (a) at the low bits and as (b) at the stride bit. + +The order (the coordinator's correction at 14:1x UK, taken into the close): W = 16 passes the rules but is dead on energy, measured today by floor lane 5 on the 5090, 4090, H100 and 3090 (the card pays the second sector through its own fabric, +25 to +34 percent energy per hash, equal to the chip's +33, so the edge does not move and the honest card loses a quarter of its efficiency). So the class order is: W = 8 pins (lane 3), the index fold lands first, then the re-weight (b) at W = 8 goes through this harness again (five box-minutes on 16 cores) before it enters. What this census keeps from (a): the rules hold at the widest width, and a wider read removes the product's own low bits from the address by construction (at W = 8 bits 0 to 2 are alignment, so the bit-2 law of the W = 4 rows is gone there too); the stride bit R is the fold's to remove. The W = 8 class is not a width the generator draws today (`WIDTH_WORDS` is 1, 4, 16), so lane 3's construction lands before its census runs. + +## 1. The candidates and the rules + +| Candidate | Class under `igneum-pow accept` | Read width | Weights (add, xor, mul, mad, shfl, rotl, sub, mulhi, rotr, or; sum 75) | +|---|---|---|---| +| ctrl, the record (class v4) | `mx8+sh256x27` | W = 1 (4 bytes) | base: 12, 10, 8, 8, 8, 7, 6, 6, 6, 4 | +| w16, the design's genesis pin | `w16m8g+sh256x27` | W = 4 (16 bytes) | base | +| (a) W = 16 at the current mix | `w64m8g+sh256x27` | W = 16 (64 bytes, two 32-byte sectors) | base | +| (b) W = 4 at the re-weighted mix | `w16m8g+sh256x27` with `IGNEUM_FG_WEIGHTS` | W = 4 | re-weighted: 13, 11, 6, 10, 8, 8, 7, 2, 6, 4 | +| (c) both | `w64m8g+sh256x27` with `IGNEUM_FG_WEIGHTS` | W = 16 | re-weighted | + +**The re-weight, stated.** The k lane's RTL table (class v6 design 10.2: k absolute at N3 against the 5090's lock, highest first) reads mad 0.20, the ARX families add, xor, rotl, rotr, sub 0.17 to 0.18, the index fold 0.14, or 0.12, mul 0.08, prmt and lop3 0.06, mulhi 0.03. The re-weight moves 6 points of 75 from the two families the chip finds easiest (mulhi 6 to 2, mul 8 to 6) to the family it finds hardest (mad 8 to 10) and to four ARX families (add 12 to 13, xor 10 to 11, rotl 7 to 8, sub 6 to 7); shfl, rotr and or stay at base. `prmt` and `lop3` are chip RTL rows, not drawn families (the generator's ten non-load families are add, sub, mul, mulhi, xor, or, rotl, rotr, mad, shfl), so "prmt down" has no weight to move; the nearest drawn family, shfl, stays at base. The lossy share (or + mul + mulhi) falls from 18 to 12 of 75, inside the family-gate band (the lossy families never above their base). mulhi keeps 2 points rather than 0 so the family stays drawn (layer 3's rotation decides family membership, not this re-weight). + +**The rules every candidate is judged by** (the harness, `igneum-pow/src/accept.rs` and `generator.rs` on this branch, on only under `IGNEUM_FAMILY_GATE` and never on a chain path): the class v4 rule set keyed on the class v4 shape at any read width (`is_census_shape`: the 256 x 27 block over the mx8 base with the mix one-hot on 1, 4 or 16 words), so (a') the freshness fixpoint in the draw and the acceptance, (c') saturated sources, (c'') the distinct-index ratio at 0.98 over 2^20 evaluations with the window divided by the width (the family-gate harness's calibration), and the 256-attempt cap with the last resort all apply; plus (c''') the class v5 hot-item floor at 0.995 on the same 2^20 sample (ported from the class v5 crate); plus the value-level index-bit test (the research file's 20.2b) read on every class over the bits the site's window and the width's alignment leave free, refused above 6 sigma under `IGNEUM_FG_BITTEST` (the drawn-era runs) and recorded on the accepted program otherwise. + +## 2. The no-era census (256 seeds per candidate, `igneum-v6c/0..255`, the class's own 256-attempt cap) + +The instrument of the research file's 20.2a-close (the invention lane's no-era census), on this branch's harness: every candidate of each seed through the whole rule, no era, the index the plain `x AND mask` so every free bit is fair to judge. `r` is the rejection rate per candidate (the record's death line for the per-load forms was 0.986 to 0.990; the class v4 control under the family-gate band read 0.595 to 0.73 across strata). The index-bit column is the value-level read on the accepted program over the 64 units' 16,384 addresses per site (sigma 64; the bits below the width's alignment are 0 by construction and not judged), so a z here is 8x smaller than the family-gate harness's 2^20 reading of the same bias. + +| Candidate | Seeds accepted of 256 | Exhausted at the 256 cap | Candidates walked | r per candidate | Mean attempt, max | (c''') refused of candidates | (c'') refused | Rejections by part | Accepted programs with a site over 6 sigma; worst | Box, clock (UK) | +|---|---|---|---|---|---|---|---|---|---|---| +| ctrl, the record (W = 1, `mx8+sh256x27`) | **256** | 0 | 770 | **0.668** | 2.01, 18 | 1 (0.1 percent) | 8 (1.0 percent) | (a') 431, (a) 52, (b) 18, (c) 4 | 143 of 256 (56 percent); z 97.1 at bit 0; 116 programs at bit 0, 14 at bit 1, 5 at bits 2 and 3, 8 at bits 4 to 26 (the product's low-bit law at the load's source, the family-gate harness's 48 to 58 percent read at 2^20 replicated at 2^14) | build-3, 8 cores, 13:45 to 13:53 | +| (a) W = 16, base mix (`w64m8g+sh256x27`) | **256** | 0 | 865 | **0.704** | 2.38, 16 | 12 (1.4 percent) | 12 (1.4 percent) | (a') 500, (a) 57, (b) 19, (c) 9 | 26 of 256 (10 percent); z 41.9 at site 0 bit 15 (seed 69); bits 4, 5, 9, 10, 11, 15, 19, 21, 27 | build-3, 8 cores, 13:37 to 13:42 | +| w16, the design's genesis pin (W = 4, base mix) | **256** | 0 | 854 | **0.700** | 2.34, 16 | 9 (1.1 percent) | 11 (1.3 percent) | (a') 491, (a) 58, (b) 20, (c) 9 | 97 of 256 (38 percent); z 56.3 at bit 10; 74 programs at bit 2 | build-4, 16 cores, 13:51 to 13:55 | +| (b) W = 4, re-weighted (`w16m8g+sh256x27`, weights 13,11,6,10,8,8,7,2,6,4) | **256** | 0 | 432 | **0.407** | 0.69, 5 | 5 (1.2 percent) | 14 (3.2 percent) | (a') 123, (a) 21, (c) 9, (b) 4 | 97 of 256 (38 percent); z 71.0 at bit 23; **75 programs at bit 2** (the lowest bit the 4-word alignment leaves free: the product's low-bit law moves up to it), 22 at bits 4 to 27 | build-4, 16 cores, 13:46 to 13:50 | +| (c) W = 16, re-weighted (`w64m8g+sh256x27`, the same weights) | **256** | 0 | 446 | **0.426** | 0.74, 6 | 15 (3.4 percent) | 14 (3.1 percent) | (a') 127, (a) 21, (c) 9, (b) 4 | 32 of 256 (12.5 percent); z 34.1 at bit 18; 13 programs at bit 4, the rest spread over bits 5 to 27 | build-4, 16 cores, 13:46 to 14:00 | + +What the no-era rows say. Every candidate accepts 256 of 256 seeds inside the chain's cap with no seed past attempt 18, and every rejection rate sits far under the 0.986 to 0.990 line that killed the per-load forms: the width moves r by nothing (0.668 at W = 1, 0.700 at W = 4, 0.704 at W = 16, the (c''') floor's per-width calibration adding about 1 point at W = 16) and the re-weight LOWERS it (0.407 to 0.426: six fewer points on the lossy families means fewer (a') refusals, mean attempt 0.7 against 2.0 to 2.4). The index-bit column is the product's low-bit law, and it moves with the width exactly as the alignment predicts: at W = 1 it sits at bit 0 in 116 of 256 programs (56 percent carry a biased site); at W = 4 bits 0 and 1 are alignment and the law lands on bit 2 (74 to 75 of 256); at W = 16 bits 0 to 3 are alignment and the law is gone from the address, leaving 26 to 32 of 256 programs (10 to 12 percent) with a weaker bias at bits 4 and up (z 8 to 42 at 2^14), the class the record's family-gate rows attribute to the era stride and to lossy writers upstream, which layer 1's index fold is the remedy for. The re-weight does not change the bias picture at either width (97 of 256 at W = 4 with or without it; 26 against 32 at W = 16). + +## 3. The drawn-era census with the window-bit test as a refusal (eras `igneum-era-test/0..7`, 32 seeds per era, 256 per candidate) + +The per-era form of the research file's 20.2a-correction: the value-level index-bit test judges only the bits inside each site's era window (so a narrow-window site's fixed top bits are never counted, the instrument fault of 10:5x UTC) and above the width's alignment, and here it REFUSES a candidate (6 sigma over the 64 units) so the count of refusals per era is read directly; a refused candidate is redrawn, as the chain would. The eras' stride rotations: era 0 R = 19, era 1 R = 6, era 2 R = 28, era 3 R = 30, era 4 R = 10, era 5 R = 22, era 6 R = 3, era 7 R = 27 (`igneum-pow show --era`). Zero refusals for the instrument's reason on every era and every candidate (the fixed window bits are not judged); every refusal below is a real bias at the era's stride bit, the adv-cache-2 class the record already carries on today's `load_index` (the product's low bits placed at address bit R by `rotl(x * M, R)`), on the eras whose R lands inside the free bits. + +| Candidate | Seeds accepted of 256 | Exhausted at the 256 cap | Candidates walked | r per candidate | Mean attempt, max | Window-bit refusals per era 0 to 7 (of candidates) | The bit refused, per era (count) | Worst free bit on the accepted programs | Box, clock (UK) | +|---|---|---|---|---|---|---|---|---|---| +| ctrl, W = 1 | **256** | 0 | 1,502 | 0.830 | 4.87, 22 | 38, 33, 5, 25, 33, 33, 38, 13 (218 of 1,502, 14.5 percent) | 19 (34), 6 (31), 0 (4), 0 (23), 10 (31), 22 (31), 3 (34), 27 (9): bit R on every era with R under 28, bit 0 (the product's own) on eras 2 and 3 | 5.9 sigma (under the band by construction) | build-4, 16 cores, 13:59 to 14:02 | +| w16, W = 4, base mix (the reference) | **256** | 0 | 1,556 | 0.835 | 5.08, 40 | 29, 38, 0, 2, 48, 40, 40, 7 (204 of 1,556, 13.1 percent) | bit R on the R-in-range eras, as the control | 5.5 sigma | build-4, 16 cores, 14:02 to 14:05 | +| (a) W = 16, base mix | **256** | 0 | 1,524 | 0.832 | 4.95, 40 | 27, 41, 0, 1, 48, 32, 33, 7 (189 of 1,524, 12.4 percent) | 19 (24), 6 (33), none, 5 (1), 10 (40), 22 (26), 4 (31: R = 3 is alignment, the law's next bit), 27 (7): bit R, never bits 0 to 3 | 5.9 sigma | build-3, 8 cores, 13:54 to 13:58 | +| (b) W = 4, re-weighted | **256** | 0 | 814 | 0.686 | 2.18, 11 | 50, 54, 1, 3, 51, 51, 51, 12 (273 of 814, 33.5 percent) | 19 (46), 6 (48), 2 (1), 2 (2), 10 (46), 22 (47), 3 (46), 27 (11) | 5.3 sigma | build-3, 8 cores, 13:58 to 14:02 | +| (c) W = 16, re-weighted | **256** | 0 | 781 | 0.672 | 2.05, 11 | 50, 54, 1, 3, 50, 51, 24, 14 (247 of 781, 31.6 percent) | 19 (46), 6 (48), 4 (1), 4 (3), 10 (45), 22 (47), 4 (22), 27 (12) | 5.5 sigma | build-4, 15 cores, 13:55 to 13:59 | + +What the era rows say. Every candidate accepts every seed on every era inside the cap with the bias refusal switched on, so none costs liveness: the price is attempts (mean 2 to 5, the worst seed 40 at W = 16 on eras 1, 4 and 6 against the control's 22). The refusals are the era-stride class on every candidate and on the control alike: on the four eras with R in 6 to 22 (eras 0, 1, 4, 5) about one candidate per seed is refused at bit R, on eras with R at 27 or above almost none, and the width only decides whether the product's OWN low bits are also in the address (bit 0 on eras 2 and 3 for the control: 27 refusals; gone at W = 16: 1). The re-weight raises the stride-bit incidence (1.6 refusals per seed at eras 0, 1, 4, 5 against 0.8 to 1.2 at the base mix): more `mad` means more product-sourced loads in front of the rotation, and `mad` is an injecting family the (a') rule accepts as a load's last writer. None of this is the candidates' to fix: the design's remedy is layer 1's index fold of the product's low bits before the stride rotation, after which this test becomes the guard that the fold holds; until the fold is in, the bias test stays a record per era, as section 5.1 of the design says, and the chain's rule (without it) accepts the same programs at the no-era rates of section 2. + +## 4. The F8-form uniformity read (2^20 nonces per seed) + +The invention lane's instrument with the era draw added (`tools/attack/v6-census/uniform`): per seed the first accepted candidate under the harness, then every load's word index over 2^20 nonces through the library's own `trace_load_indices`; per site the distinct-index ratio against `N - N^2 / 2W_s` (the window over the width); the cross-hash ITEM histogram's top 0.1 percent share against a uniform control of the same size (the F8 pass line: within 1.2x; the record's class v4 read 1.00x on the clean seeds and the plants fire at 29x and 4.8x). No era here (the no-era index is the plain `x AND mask`); the drawn-era F8 verdict is section 3's window-bit test, and the family-gate lane's 2^24 live-dataset census is the instrument for a per-era hot-set hunt, at 45 to 100 core-hours per point, which this window does not hold. + +| Candidate | Seeds | Top 0.1 percent share, ratio to the uniform control (min to max) | Min site distinct ratio (min to max over seeds) | Max item reads (candidate / control) | Box, clock (UK) | +|---|---|---|---|---|---| +| ctrl, the record (W = 1) | 16 | 0.9992 to 1.0163 (PASS) | 0.9722 to 1.0001 | 26 to 29 / 29 | build-3, 8 cores, 13:50 to 13:52 | +| w16 (W = 4, base mix) | 16 | 0.9993 to 1.0053 (PASS) | 0.9967 to 1.0026 | 26 to 30 / 29 | build-3, 8 cores, 13:52 to 13:54 | +| (b) W = 4, re-weighted | 16 | **0.9989 to 1.0077** (PASS at 1.2x) | 0.9815 to 1.0026 | 26 to 30 / 29 | build-3, 8 cores, 14:02 to 14:05 | +| (a) W = 16, base mix | 16 | **0.9986 to 1.0061** (PASS at 1.2x) | 1.0439 to 1.0491 | 26 to 30 / 27 to 29 | build-3, 8 cores, 13:44 to 13:46 | +| (c) W = 16, re-weighted | 16 | **0.9987 to 1.0016** (PASS at 1.2x) | 1.0465 to 1.0491 | 26 to 30 / 27 to 29 | build-3, 8 cores, 13:42 to 13:44 | + +## 5. The verifier cost + +`igneum-pow bench --warps 20` on one leased core of build-4 (core 18, nice 19, 13:55 to 14:02 UK) while the box ran 80 other leased threads, so the figures carry the box's load: the control's three repeats at the start read 9.55, 9.54, 9.68 ms per 32-lane warp and the same program at the end 9.49, 9.13, 9.19 (the load fell during the run). Every pair is read against the nearest control block. + +| Candidate | ms per warp, three repeats of 20 warps | Against the control | Reading | +|---|---|---|---| +| ctrl (first) / ctrl (last) | 9.55, 9.54, 9.68 / 9.49, 9.13, 9.19 | | the drift of the box: 4 percent across the run | +| w16 (W = 4, base mix) | 9.65, 9.42, 9.45 | -0.9 percent on the means (first block) | within the drift | +| (a) W = 16, base mix | 9.48, 9.75, 9.70 | **+0.6 percent** on the means (first block) | within the drift; the invention lane's +4 percent (20.2b's row) is not seen at this resolution | +| (b) W = 4, re-weighted | 9.62, 8.60, 8.38 | -5 percent on the means (the load fell mid-run; the first repeat equals the control) | within the drift | +| (c) W = 16, re-weighted | 9.15, 9.21, 9.25 | **-0.1 percent** against the last control block | within the drift | + +The verifier cost delta of both changes is under the run's 4 percent drift on a loaded core; a quiet-box reading (`lease quiet`, the ladder's method with the SMT sibling loaded) is owed before the number is quoted as a figure. Nothing here approaches the 10 ms loaded gate. + +## 6. PASS or FAIL per candidate against the sub-version 3 rules + +The line: 256 of 256 seeds accepted on the no-era census inside the chain's cap with r far under 0.986 to 0.990; the drawn-era census on eras 0 to 7 with 0 refusals for the instrument's reason and every seed accepted; no product bit in the address that the record does not already carry (the era-stride bit under the pre-fold `load_index`, equal in kind on the control); the (c''') floor applied and its cost stated; the F8-form read within 1.2x of the uniform control. + +| Candidate | No-era census | Drawn-era census and the window-bit test | Biased product bits in the address | (c''') | F8-form at 2^20 | Verifier | Verdict | +|---|---|---|---|---|---|---|---| +| (a) W = 16 at the current mix | 256 of 256, 0 exhausted, r 0.704 | 256 of 256 on eras 0 to 7, 0 exhausted, 0 instrument refusals; 189 stride-bit refusals of 1,524 candidates (the control 218 of 1,502) | the product's own low bits (0 to 3) are alignment and never reach the address; the stride bit R stays, as on the record | 1.4 percent of candidates refused | 0.999 to 1.006 of the control | +0.6 percent, within drift | **PASS** | +| (b) W = 4 at the re-weighted mix | 256 of 256, 0 exhausted, r 0.407 | 256 of 256, 0 exhausted, 0 instrument refusals; 273 stride-bit refusals of 814 | bit 2 carries the product law in 75 of 256 programs (the width's, not the mix's: the w16 reference reads 74); the stride bit refused 1.6 times per seed on R-in-range eras against the control's 1.2 | 1.2 percent | 0.999 to 1.008 of the control | within drift | **PASS on the rules; weaker than (a) on the bias count** | +| (c) both | 256 of 256, 0 exhausted, r 0.426 | 256 of 256, 0 exhausted, 0 instrument refusals; 247 stride-bit refusals of 781 | as (a) at bits 0 to 3; the stride bit refused 1.6 times per seed on R-in-range eras | 3.4 percent | 0.999 to 1.002 of the control | -0.1 percent, within drift | **PASS on the rules; the re-weight's stride-bit cost as in (b)** | + +Meaning for the two changes. The read width W = 16 passes every sub-version 3 rule at the record's own rates and is the cleanest of the three on the address: a wider read removes the product's low-bit law from the address by construction. It does not enter: floor lane 5's card rows of today (the 5090, 4090, H100 and 3090) read the second sector at +25 to +34 percent energy per hash on the card, paid through its own fabric and equal to the chip's +33, so the edge does not move and the honest card loses a quarter of its efficiency; W = 16 is dead on energy, and the rules' verdict here is what it would have needed beside that. The re-weight passes the rules with a lower rejection rate (fewer lossy ops, fewer (a') refusals) and costs nothing on the verifier, but it moves weight onto `mad`, a product the (a') rule accepts at a load's source, so the era-stride bias is refused about a third more often per seed until layer 1's index fold lands; with the fold in, that cost disappears and the re-weight's chip-side gain (the k lane's ranking) stands on its own. The class order, per the coordinator's close: W = 8 pins (lane 3), the index fold lands first, then the re-weight (b) at W = 8 goes through this harness again (five box-minutes) before it enters; the W = 8 draw is lane 3's construction (the generator's widths are 1, 4 and 16 today), and the harness takes it the day it parses. + +## 7. The exact commands + +The harness is this branch's `igneum-pow` at 14c550e3 (the CLI binary pinned on both boxes as `/srv/builds/v6-census/bin/14c550e3/igneum-pow`, sha256 d601098699840534...; the uniform tool `v6census-uniform` beside it, 2a150ee714b06e79...), built on the box through `tools/build-remote.sh --box 3` and `--box 4` from `igneum-pow/` and from `tools/attack/v6-census/uniform/` (`build --release`). The scripts are in the tree under `tools/attack/v6-census/` (the census) and were copied to `/srv/builds/v6-census/` on each box with the launchers below. + +One census job (the launcher `launch.sh ...`, jobs `ctrl-none a-none b-none c-none w16-none ctrl-era a-era b-era c-era w16-era`; the era jobs carry the candidate's own class, since a single allowed era width leaves the base class's mix as drawn): + +``` +nohup /srv/builds/_bin/lease pool 16 --min 4 --nice 19 --class measure \ + --label "class v6 census: a-none (w64m8g+sh256x27, era widths 64, weights base) on 14c550e3" --owner class-v6-census -- \ + env THREADS={cores} BIN=/srv/builds/v6-census/bin/14c550e3/igneum-pow OUT=/srv/builds/v6-census TAG=a-none \ + CLASS=w64m8g+sh256x27 ERAS=none SEEDS=256 ERAW=64 /srv/builds/v6-census/v6census.sh > /srv/builds/v6-census/run-a-none.log 2>&1 & +# the re-weighted candidates add IGNEUM_FG_WEIGHTS=13,11,6,10,8,8,7,2,6,4; the era jobs add ERAS="0 1 2 3 4 5 6 7" SEEDS=32 IGNEUM_FG_BITTEST=1 +``` + +Inside the script, one seed is one process (the harness flag on, the class's own cap of 256 attempts, the per-era form with the width pinned): + +``` +IGNEUM_FAMILY_GATE=1 igneum-pow accept --seed igneum-v6c/ --class w64m8g+sh256x27 +IGNEUM_FAMILY_GATE=1 IGNEUM_FG_BITTEST=1 igneum-pow accept --seed igneum-v6c/ --class w64m8g+sh256x27 --era igneum-era-test/ --era-widths 64 +``` + +The F8-form uniformity read (`uniform-launch.sh ctrl a b c w16`, no era, 16 seeds at 2^20 nonces): + +``` +nohup /srv/builds/_bin/lease pool 16 --min 4 --nice 19 --class measure --label "class v6 census: F8-form uniform a era none ..." --owner class-v6-census -- \ + env IGNEUM_FAMILY_GATE=1 /srv/builds/v6-census/bin/14c550e3/v6census-uniform --class w64m8g+sh256x27 --seeds 16 --nonces 1048576 --threads {cores} --era none --era-widths 64 > uniform-a-none.tsv & +``` + +The verifier bench (`benchall.sh`, one leased core, three repeats of 20 warps per candidate, the control first and last): + +``` +nohup /srv/builds/_bin/lease pool 1 --min 1 --nice 19 --class measure --label "class v6 census: verifier bench per candidate, one core" --owner class-v6-census -- ./benchall.sh > bench.log 2>&1 & +# inside: IGNEUM_FAMILY_GATE=1 [IGNEUM_FG_WEIGHTS=...] igneum-pow bench --seed igneum-v6c/0 --class --warps 20 +``` + +Every job writes its lease pid to `/srv/builds/v6-census/pids/.lease.pid` and the script its own to `pids/.pid`; a job is stopped only through those files. The launchers (`launch.sh`, `uniform-launch.sh`, `benchall.sh`) and the summary script are in `tools/attack/v6-census/`. The summary over a TSV is `summ.py` (per era: seeds, accepted, exhausted, candidates, r, mean and max attempt, the worst index-bit sigma, the over-6-sigma count, the window-bit refusals, the rejections by part); the TSVs and logs stay under `/srv/builds/v6-census/` on the box that ran them, with copies under `docs/analysis/class-v6/logs/census/` on this branch. + +## 8. Unverified and owed + +- The drawn-era F8 hot-set census at 2^24 on the live dataset (ring C, 45 to 100 core-hours per point) was not run in this window; section 4 is the 2^20 no-era form plus section 3's per-era window-bit test. +- The verifier figures are from a loaded core with a 4 percent drift; the quiet-box reading is owed before a number is served. +- The (c''') floor at W = 4 and W = 16 refuses 1.2 to 3.4 percent of candidates against 0.1 percent at W = 1 on the same 2^20 sample with the window divided by the width; the family-gate lane's per-width calibration (its 09:00 item) decides whether 0.995 is the floor at every width or a sigma form replaces it. No seed was lost to it here. +- The re-weight's weights are this lane's reading of the k lane's table, not the k lane's optimiser (owed by that lane at 19:30 UK); a different split inside the band would need its own census, at about five box-minutes per candidate on 16 cores with this harness. +- The index-bit sigma on the accepted programs is read at the acceptance's 2^14 evaluations (sigma 64); the family-gate harness reads the same statistic at 2^20 and sees 8x the z. The counts here are therefore lower bounds on the share of programs carrying a biased site. +- The harness widens the class v4 rules to any width only under `IGNEUM_FAMILY_GATE`; the chain's generator and acceptance on `counter-asic-4` are unchanged by this branch, and the per-width `site_window` division in `distinct_ratio_pass` is the one unconditional edit (width 1 on every shipped class, so no shipped verdict moves). diff --git a/docs/analysis/class-v6/floor/denominator.md b/docs/analysis/class-v6/floor/denominator.md new file mode 100644 index 000000000..13085425f --- /dev/null +++ b/docs/analysis/class-v6/floor/denominator.md @@ -0,0 +1,386 @@ +# Class v6 floor lane 4: the honest denominator (8 October 2026) + +Branch `class-v6-floor-denominator` from `counter-asic-4` (91117093). The question: every chip edge in the record is a +ratio over the honest tier's microjoules per hash, and the honest tier's own operating point is half the resistance, +the half the project controls through Ember's tuning. This file finds how low the honest joule goes per card class +today with software alone, under class v5, and reads the chip edge against each row; models the LPDDR6 and +unified-memory tier five years out; and lands the Ember tiers statement as a table the app reads +(`app/igneum-app/tiers/class-v5-tiers.json`, its validator and test beside it). Every figure is labelled measured (with +its source) or estimated (with its method). Nothing here moves a consensus object or a served text. Times are UK (BST). + +## 0. One page + +1. **The honest floor under class v5, measured today:** the RTX 5080 at an 1,100 MHz core lock reads 2.06 microjoules + per hash on class v4's shape (71.20 MH/s at 146.6 W) and about 2.10 under class v5; the RTX 5090 at its 1,300 MHz + knee 2.37 (134.76 MH/s at 318.8 W, the v5lock job's +2.0 percent over class v4 applied); the RTX 4070 at its tune + point 3.51 to 3.58; the RX 9070 XT at the ADLX grid's best point 7.9 to 8.1; the Apple M5 Max 1.40 to 1.43 at the + GPU-plus-DRAM meter with no lever. The class v5 STOCK column is now measured on 14 card classes (the rented sweep, + 13:4x to 14:0x UK, every host refusing the lock): the 5080 3.48, the 4070 5.82, the 4080 4.92, the 5060 3.76, the + 5060 Ti 4.02, the 3090 5.03, the 3060 6.40, the L40S 5.29, the H100 2.58, the A100 2.99, the 4090 5.0 (lane 1), so + the lock is worth 34 to 41 percent of a Blackwell or Ada card's class v5 draw (the 5080 3.48 to 2.10, the 4070 5.82 + to 3.58) for under 2 percent of rate, and the stock column is a different card from the floor column. The 5080 + beats the 5090 per joule at the knee, and the 16 GB and 12 GB Blackwell cards (5070 Ti, 5070) read lower still by + the Blackwell shape (1.7 to 2.1, estimated): **the honest NVIDIA floor is the mass-market Blackwell card at its + knee, not the 5090.** +2. **The chip edge against the honest floor, class v5, the chip's shadow core priced in absolute terms** (3.2 pJ per + forced op, the record's k = 0.5 at the 5090's knee; and 6.4 pJ, k = 1): the GDDR7 stored-dataset board reads 2.7x / + 1.9x against the 5080's floor, 3.0x / 2.1x against the 5090's, 1.8x / 1.3x against the M5 Max; one HBM3 stack 3.3x / + 2.2x, 3.6x / 2.4x, 2.2x / 1.5x; the N2 SRAM die 4.5x / 2.7x, 5.0x / 3.0x, 3.1x / 1.8x. The served 2.1x (the 5090 at + the knee, k = 1) stands; the honest sentence per joule is now "under 2x against a 16 GB Blackwell card at its knee + for a core as good as a GPU lane, 1.3x against an Apple laptop". +3. **What moves the floor is the operating point and nothing else in software.** The SM-sparse kernel is dead on + measured rows (the draw follows the work, not the SM count; research file 20.3b; floor lane 1's rows of 13:25 on a + rented 4090 and H100 say the same at stock: the best occupancy shape saves 1 to 2 percent of the watts and the draw + over idle is flat across the SM count while the rate holds, so the residual is the clock domain, reachable by the + lock and the undervolt only); the cache-policy hint is dead; the + memory clock is never touched (a step that drags it down cannot win); the power cap is flat on Blackwell at the hash + (0.41 MH/W under every limit on the 5090) and is the only lever on Ampere; the core lock walks the driver's V/F + curve and is the lever on Blackwell and Ada; AMD has the ADLX offsets (measured today: 24 percent of the 9070 XT's + draw for no rate); Apple and Intel have no lever in the app. +4. **Five years out the honest tier is the unified-memory SoC on LPDDR6**, modelled at about 1.2 microjoules per hash + under class v5 at the meter for an Apple Max-class part (0.27 of DRAM reads, 0.35 of GPU issue, 0.56 of shadow), 1.6 + to 1.7 at the package; the AMD, Qualcomm, MediaTek and NVIDIA LPDDR SoCs model 3 to 10 microjoules because their + GPUs hide the latency worse, not because of the memory. Against that tier the GDDR7 chip reads 1.5x / 1.06x, one + HBM3 stack 1.8x / 1.2x, the N2 SRAM die 2.5x / 1.5x, the custom HBM4E base die 2.4x / 1.4x. The class should size the + shadow per tier with the Apple tier as the binding ceiling (it already does by the 2.0 rule: N at or under 130,000 + ops) and state resistance against the best honest joule; it should NOT score the acceptance floor per tier (one + network-wide number, the same for every honest card). Pricing the Apple-bound shadow for the 5090 tier: N = 130,000 + instead of 100,000 costs the 5090 +0.19 microjoules at the knee (+8 percent of its electricity) and moves its GDDR7 + edge at k = 1 from 2.1x to 1.95x. +5. **The tiers for Ember** (`app/igneum-app/tiers/class-v5-tiers.json`): per card class the Efficiency, Balanced and Max + rows in the app's own tier shape, measured on the 5090, 5080, 4070, 9070 XT and M5 Max, estimated from the measured + stock rows and the architecture's shape elsewhere (Blackwell: lock 1,100 to 1,300 MHz, power 100 percent; Ada: lock + 1,860 to 2,400 and 50 to 80 percent; Ampere: 80 to 90 percent and no lock below 1,800 MHz; AMD: -500 MHz and -30 + percent; Apple and Intel: stock). The re-measure rule: a set measured under one class never applies under another + (the app's `tiers_stale`); the stored point is the provisional start of the re-measure, the Max tier is stock and never + stale; the measured v4 to v5 flip on the 5090 moved the knee by nothing (0.0 percent of rate, +2.0 percent of watts). + +## 1. The method and the denominators + +| Quantity | Value | Label | Source | +|---|---|---|---| +| Class v5 | `mx8-era+sh256x27+state`: class v4's shape (64-instruction base, a 256-instruction shadow block x27, 102,100 counted ops per hash) plus the state leaves; the worker uploads the leaves for the dataset build and frees them | measured (the kit's RESULT line on a rented 4090 and 23 other cards: every v5 fingerprint MATCH) | `~/igneum-fleet/cv5-results.txt`; `~/igneum-fleet/cardbench/rows.jsonl` 8 October | +| Class v5 over class v4 at the same point | 0.0 percent of rate, +2.0 percent of watts (the 5090 at the 1,300 MHz lock: 125.93 MH/s at 299.8 W against 125.92 at 294.0) | measured | the hash lane's v5lock job, 8 October; `scratch v4/ca4-v6-cost-rows.md` | +| The 5090 at class v4, the core-clock grid | unlocked 136.84 MH/s at 475.5 W; 1,300 MHz 134.76 at 312.5 (the knee, rate -1.5 percent); 1,200 MHz 133.80 at 305.1 (the best MH per watt, -2.2 percent); 1,100 MHz 122.43 at 287.3 (-10.5 percent); the class v4 premium 145.3 W unlocked, 81.8 W at the best points | measured, PC 1, 7 to 8 October | `docs/bench-log.md`, the class v4 efficiency passes | +| The 5080 at class v4, the core-clock grid | unlocked 71.41 at 253.1 W; 1,100 MHz 71.20 at 146.6 (the best MH per watt, -0.3 percent); 1,000 MHz 71.19 at 149.0; 900 MHz 67.66 at 137.8 (-5.2 percent); the draw floors from 1,500 MHz down; the premium 83.4 W unlocked and 41 W at the best points | measured, PC 1, 8 October 00:45 to 01:54 UTC | the same | +| The 4070 at its Ember tune (1,860 MHz lock, the 50 percent cap) | class v3 30.95 MH/s at 79.5 W (2.57); class v4 31.08 at 109.0 (3.51): +30 W for no rate; stock class v3 28.7 at 102.7 (3.58) | measured, PC 1, 6 October | `docs/plans/counter-asic-3-status.md` item 8; Ember run 6 | +| The 9070 XT on the ADLX grid | 24 rows, the rate flat at 18.9 MH/s, the best point -500 MHz core and -30 percent power = 149.3 W (7.9), 24 percent under the 202 W stock point (10.7) | measured, PC 1, 8 October 12:13 | the hash lane's AMD grid job | +| The M5 Max | class v3 27.08 MH/s at 21.0 W (0.78), class v4 26.67 at 37.3 W (1.40) at the GPU and DRAM channels of the IOReport meter; the package about 17 W more; marginal 6.9 pJ per counted op | measured, 6 October | `docs/analysis/latency-shadow-2026-10-06.md` section 3 | +| The rented stock rows (class v3 and the class v4 shape, 24 card classes) | `rows.jsonl`, 7 and 8 October: three timed runs, an nvidia-smi sampler at 1 Hz, the three power fields; no host allowed `-lgc` ("The current user does not have permission to change clocks") so no rented row carries a knee | measured (stock only) | `~/igneum-fleet/cardbench/rows.jsonl`; `bench-table.md` | +| The rented against the PC spread | the 5080 read 143.4 W at 71.16 MH/s on a rented Linux host and 169.7 W at 71.28 on PC 1 (Windows) on class v3: 18 percent apart at the same rate; the 5090 the same shape (258 W rented at 0.3.12 against 312 W on the PC) | measured; neither corrected | `site/miner-bench.json` notes | +| The chips at zero shadow | GDDR7 board 0.466 microjoules per hash; one HBM3 stack 0.321; the N2 SRAM die 0.14 | modelled | chip-model-v3 5.4 and 5.12; `class-v6/hardware-future.md` section 5 | +| The chip's shadow under class v5 | 101,170 forced ops per hash (102,100 minus the 930 base) at 3.2 pJ (k = 0.5 against the 5090's measured 6.4 pJ per op at the knee: the record's centre band) = 0.324 microjoules; at 6.4 pJ (k = 1) = 0.648 | modelled on the measured GPU rows | research file 15.1a, 20.4 | +| The chips under class v5 | GDDR7 0.79 / 1.11; HBM3 0.65 / 0.97; N2 SRAM 0.46 / 0.79 (k = 0.5 / k = 1) | modelled | this file | + +Reading the identity. The chip's energy is `E_mem + c x N` with `c` the chip core's picojoules per forced op and `N` +the op count, a number that does not depend on which card is the reference; so the chip's microjoules per hash are +fixed by the class (0.79 to 1.11 on GDDR7 under class v5) and every row's edge is just that card's microjoules over +them. The record's `k` columns are this `c` divided by the reference card's own picojoules per op: k = 1 at the 5090's +knee is 6.4 pJ, k = 1 at the unlocked 5090 would be 10.8 pJ, k = 1 on the M5 Max 6.9 pJ. Stating the chip in absolute +picojoules keeps the comparison honest across cards. + +What "every software knob" is, per vendor. NVIDIA through nvidia-smi: `-pl` (the power cap, percent of the default +limit, floor 50 percent, min 400 W on a 5090), `-lgc 0,` (a core-clock cap that walks the driver's V/F curve; +administrator rights, so only through the Power Helper on Windows and never on a rented Linux host), `-lmc` (the +memory clock, never touched: a step whose memory clock falls under 95 percent of baseline is marked and cannot win); +no voltage offset (that is NVAPI's). AMD through the ADLX line in igneum-gpu-telemetry: `--set-gmax` (a core offset) +and `--set-plimit` (a power offset), no memory knob on RDNA 4, no elevation. Apple: measure only. Intel: measure only. +The kernel-side knobs the record closed: the SM-sparse variant (dead: the energy per hash never falls below base on +either class, 20.3b), `ld.global.cs` (dead: equals base within 1 W, 20.3c), the block shape (64 to 256 instructions, +fixed by the class), the occupancy (one warp per block, 24 blocks per SM, fixed by the worker's race). + +## 2. The table: every card class under class v5, the lowest microjoules per hash with the knobs, and the chip edge + +"Floor" is the lowest class v5 energy per hash the card reaches with the knobs available to it today; "stock" is the +card unlocked at 100 percent under class v5 (the sweep's measured rows, 13:4x to 14:0x UK, say "stock, lock owed" in +the table: no rented host allowed the lock). A measured row cites its job; an estimated row names its method and its +band. The chip columns divide the row's floor by the chip's class v5 energy at three core figures: 1.1 pJ per forced op +(the k lane's synthesised sequencer-core floor at N3, the pessimistic column), 3.2 pJ (the record's k = 0.5) and 6.4 +pJ (k = 1, a core as good as a GPU lane); `E_mem` 0.466, 0.321 and 0.14 microjoules. The Apple rows are at the GPU-plus-DRAM meter (the package adds about 17 W on the M5 +Max; the wall more); the NVIDIA and AMD rows are whole-card. + +| Card | Tier | Class v5 floor, microjoules per hash | Label | Class v5 stock, microjoules per hash (label) | GDDR7 board at 1.1 / 3.2 / 6.4 pJ per forced op | HBM3 one stack | N2 SRAM die | The point, the band and the source | +|---|---|---|---|---|---|---|---|---| +| NVIDIA GeForce RTX 5090 | 32 GB | 2.33 | measured | 3.48 (measured) | 4.0x / 3.0x / 2.1x | 5.4x / 3.6x / 2.4x | 9.3x / 5.0x / 3.0x | 1200 MHz at 100 percent. class v4 best MH per watt (133.80 MH/s at 305.1 W, 2.2 percent of rate given); under class v5 +2.0 percent watts: 311.2 W, 2.33 Stock: the power cap is flat on this hash (0.41 MH/W under every limit), so no power rung is used on any tier | +| NVIDIA GeForce RTX 5080 | 16 GB | 2.06 | measured | 3.48 (measured) | 3.6x / 2.6x / 1.9x | 4.8x / 3.2x / 2.1x | 8.2x / 4.4x / 2.6x | 1100 MHz at 100 percent. class v4 best MH per watt; the draw floors from 1,500 MHz down; the knee is between 1,000 and 900 MHz (900 costs 5.2 percent); class v5 about 2.10 Stock: class v5 measured on a Vast 5080 (13:49 UK): 71.35 MH/s at 248.0 W (3.48, 39 samples, SM 2,769, memory 14,801); class v3 71.16 at 159.4 W on the same host; PC 1 read class v4 71.41 at 253.1 W: the three agree within 3 percent on this card; stock, lock owed on the rented host | +| NVIDIA GeForce RTX 5070 Ti | 16 GB | 1.7 | estimated | 2.84 (measured) | 2.9x / 2.2x / 1.5x | 3.9x / 2.6x / 1.8x | 6.8x / 3.7x / 2.2x | 1100 MHz at 100 percent. the Blackwell shape applied to the measured stock rows (the v3 draw x0.63, the premium x0.5): band 1.6 to 2.0; the rented host refused -lgc, so the knee is the search's to find Stock: rented pod 8 October 10:09Z: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W; the class v5 sweep rented this card twice (14:08 and 14:13 UK) and neither host ever accepted the fleet key | +| NVIDIA GeForce RTX 5070 | 12 GB | 1.75 | estimated | 2.99 (measured) | 3.0x / 2.2x / 1.6x | 4.0x / 2.7x / 1.8x | 7.0x / 3.8x / 2.2x | 1100 MHz at 100 percent. the Blackwell shape on the measured stock rows (paired class v3 113 W): band 1.7 to 2.1 Stock: rented v4watts pod 8 October; the 7 October pod read class v3 52.0 MH/s at 102.8 W (the rate differs by host); the class v5 sweep rented this card twice (14:08 and 14:13 UK) and neither host ever accepted the fleet key | +| NVIDIA GeForce RTX 5060 Ti | 16 GB | 2.36 | estimated | 4.02 (measured) | 4.1x / 3.0x / 2.1x | 5.5x / 3.7x / 2.4x | 9.4x / 5.1x / 3.0x | 1100 MHz at 100 percent. the Blackwell shape on the PC 2 stock row: band 2.2 to 2.6; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium) Stock: class v5 measured on a Vast 5060 Ti (13:5x UK): 30.84 MH/s at 123.9 W (4.02, 96 samples, SM 2,835); class v3 30.75 at 82.6 W on the same host; PC 2's enclosure row read class v4 30.9 at 114.8 W; stock, lock owed | +| NVIDIA GeForce RTX 5060 | 8 GB | 2.21 | estimated | 3.76 (measured) | 3.8x / 2.8x / 2.0x | 5.1x / 3.4x / 2.3x | 8.8x / 4.8x / 2.8x | 1100 MHz at 100 percent. class v3 measured 31.27 MH/s at 75.4 W; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium) Stock: class v5 measured (13:51 UK): 30.80 MH/s at 115.7 W (3.76, 99 samples, SM 2,715, memory 13,801); class v3 30.76 at 78.8 W on the same host (the shadow +37 W = 12 pJ per op); stock, lock owed | +| NVIDIA GeForce RTX 4090 | 24 GB | 3.58 | estimated | 5.0 (measured) | 6.2x / 4.5x / 3.2x | 8.3x / 5.6x / 3.7x | 14.2x / 7.7x / 4.5x | 1860 MHz at 60 percent. the Ada shape (the 4070's measured tune: v3 x0.72, the premium x0.7) on the measured stock rows (class v3 253.4 W, class v4 353.5 W, floor lane 1, 8 October): band 3.3 to 4.0; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium) Stock: floor lane 1's rented 4090 at a 450 W limit: class v3 70.63 MH/s at 253.4 W (3.59), class v4 70.63 at 353.5 W (5.0); the denominator sweep's Vast 4090 carried a 250 W host limit: class v5 62.68 at 249.9 W (3.99, the SM at 2,579 MHz) and class v3 62.40 at 200.5 W, so a 250 W cap held 89 percent of the rate at 71 percent of the draw (an Ada cap row measured); stock, lock owed | +| NVIDIA GeForce RTX 4080 | 16 GB | 3.51 | estimated | 4.92 (measured) | 6.1x / 4.4x / 3.2x | 8.1x / 5.4x / 3.6x | 14.0x / 7.6x / 4.5x | 1860 MHz at 60 percent. the Ada shape on the measured stock rows (class v3 128.6 W, class v4 185.6 W): band 3.1 to 3.7; re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium) Stock: class v5 measured (13:50 UK): 40.80 MH/s at 200.7 W (4.92, 72 samples, SM 2,760); class v3 40.69 at 141.5 W on the same host; the v4watts pod read class v4 40.74 at 185.6 W; stock, lock owed | +| NVIDIA GeForce RTX 4070 | 12 GB | 3.58 | measured | 5.82 (measured) | 6.2x / 4.5x / 3.2x | 8.3x / 5.6x / 3.7x | 14.2x / 7.7x / 4.5x | 1860 MHz at 50 percent. Ember run 6's tune point (1,863 MHz at 50 percent) under class v4 (sh256x27): 31.08 MH/s at 109.0 W, +30 W over class v3 at the same point for no rate; class v5 about 3.58; the ladder below 1,860 under class v4 is owed (band 3.2 to 3.6) Stock: class v5 measured on a Vast 4070 (13:54 UK): 28.43 MH/s at 165.5 W (5.82, 108 samples, SM 2,820, memory 9,801, a 210 W host limit not binding); class v3 28.40 at 116.3 W on the same host (the shadow +49 W = 17 pJ per op at the stock clock); Ember run 6's PC 1 stock on class v3 read 28.72 at 106.0 W; the tune point (1,860 MHz, 50 percent) under class v4 measured 31.08 at 109.0 W (3.51), so the lock takes 34 percent of this card's class v5 draw for no rate | +| NVIDIA GeForce RTX 4070 Ti | 12 GB | 3.6 | estimated | 4.97 (measured) | 6.2x / 4.6x / 3.2x | 8.3x / 5.6x / 3.7x | 14.3x / 7.8x / 4.6x | 1860 MHz at 60 percent. the Ada shape on the measured stock rows (class v3 95.4 W, class v4 155.3 W); the 4070 Super at a 110 W host cap held 31.26 MH/s at 108.4 W under class v4 (3.47): a cap row measured on a sibling Stock: rented pods 8 October | +| NVIDIA GeForce RTX 4060 Ti | 16 GB | 3.81 | estimated | 5.32 (measured) | 6.6x / 4.8x / 3.4x | 8.8x / 5.9x / 3.9x | 15.2x / 8.2x / 4.8x | 1860 MHz at 60 percent. the Ada shape (the 4070's measured tune: v3 x0.72, the premium x0.7) on the measured class v5 stock row; band 3.5 to 4.2 Stock: class v5 measured on a Vast 4060 Ti (14:27 UK): 18.75 MH/s at 99.8 W (5.32) under a 140 W host limit; class v3 18.74 at 79.1 W on the same host (the shadow +21 W = 11 pJ per op; this host read 7 percent under the 7 October pod's 20.10 MH/s); the v4watts pod read class v4 20.10 at 102.3 W (5.09); stock, lock owed | +| NVIDIA GeForce RTX 4060 | 8 GB | 3.77 | estimated | 4.98 (estimated) | 6.5x / 4.8x / 3.4x | 8.7x / 5.8x / 3.9x | 15.0x / 8.1x / 4.8x | 1860 MHz at 60 percent. 19.09 MH/s measured on three rented hosts, the watts unread on every one (no power sensor): the watts are the 4060 Ti's shape; band 3.7 to 4.2 Stock: watts OWED: every rented 4060 host exposed no power sensor | +| NVIDIA GeForce RTX 3090 | 24 GB | 4.51 | estimated | 5.03 (measured) | 7.8x / 5.7x / 4.1x | 10.4x / 7.0x / 4.7x | 17.9x / 9.7x / 5.7x | 1800 MHz at 80 percent. the Ampere cap lever (10 to 15 percent of the draw; a cap that takes the SM under 1,800 MHz costs rate) on the measured class v5 stock row; the 3090 Ti read class v3 61.95 MH/s at 249.5 W (4.03) Stock: the denominator sweep, RunPod, 8 October 13:25 UK: class v3 60.01 MH/s at 294.6 W (4.91), class v5 61.49 at 309.4 W (5.03, 46 samples, SM 1,673 MHz, memory 9,501); the class v5 premium on this card 5 percent at stock; stock, lock owed (the host refused -lgc and -lmc) | +| NVIDIA GeForce RTX 3080 | 10 GB | 4.2 | estimated | 4.54 (estimated) | 7.3x / 5.3x / 3.8x | 9.7x / 6.5x / 4.3x | 16.7x / 9.1x / 5.3x | 1800 MHz at 80 percent. the Ampere cap lever (10 percent, no lower: a 170 W cap took 34 percent of the class v5 rate on this card, a 180 W cap 11 percent) Stock: the sweep's two 3080 hosts both carried a limit under the class v5 draw: at 170 W class v3 50.71 MH/s at 169.2 W (3.34) held the rate and class v5 fell to 33.37 MH/s at 169.9 W (5.09) with the SM at 689 MHz; at 180 W class v3 49.83 at 177.8 W and class v5 44.31; the uncapped class v5 stock by the 3080 Ti's +30 percent: about 230 W (4.54); the Ampere cap under the shadow costs rate one for one: measured twice | +| NVIDIA GeForce RTX 3070 | 8 GB | 4.8 | estimated | 5.29 (measured) | 8.3x / 6.1x / 4.3x | 11.1x / 7.4x / 5.0x | 19.1x / 10.4x / 6.1x | 1800 MHz at 80 percent. the Ampere cap lever on the measured stock rows (class v3 142.3 W, class v4 196.4 W); the 3070 Ti 38.98 MH/s at 177.1 / 267.6 W Stock: rented pods 8 October; the class v5 sweep's two 3070 hosts closed the connection mid-bench | +| NVIDIA GeForce RTX 3060 | 12 GB | 5.77 | estimated | 6.4 (measured) | 10.0x / 7.3x / 5.2x | 13.3x / 8.9x / 6.0x | 23.0x / 12.4x / 7.3x | 1800 MHz at 80 percent. the Ampere cap lever (10 percent) on the measured class v4 stock row; the 3060 Ti at a 130 W host cap held 33.06 MH/s at 128.7 W under class v4 (3.89): a cap row measured on a sibling Stock: class v5 measured on a Vast 3060 (13:53 UK): 26.53 MH/s at 169.8 W (6.40) at the host's 170 W limit (the limit binding: the class v4 pod read 26.89 at 166.1 W, 6.18); class v3 26.53 at 120.4 W on the same host; stock, lock owed | +| AMD Radeon RX 9070 XT | 16 GB | 7.9 | measured | 10.7 (measured) | 13.7x / 10.0x / 7.1x | 18.3x / 12.3x / 8.2x | 31.4x / 17.0x / 10.0x | ADLX -500 MHz, -30 percent. the ADLX grid (24 rows, PC 1): the rate flat at 18.9 MH/s across the grid, the best point -500 MHz core and -30 percent power, 24 percent under stock; class v5 about 8.1 Stock: the app's own power reading at the stock point, 8 October 07:11 UK | +| AMD Radeon RX 7900 XTX | 24 GB | 8.0 | estimated | 10.7 (estimated) | 13.9x / 10.1x / 7.2x | 18.5x / 12.4x / 8.3x | 31.8x / 17.3x / 10.2x | ADLX -500 MHz, -30 percent. not rentable, not owned: the 9070 XT's dependent-read rate per channel (150 M per second per 32-bit channel) on 24 channels; the knob by the 9070 XT grid Stock: modelled | +| AMD Radeon RX 7800 XT | 16 GB | 9.5 | estimated | 12.8 (estimated) | 16.5x / 12.0x / 8.5x | 22.0x / 14.7x / 9.8x | 37.8x / 20.5x / 12.1x | ADLX -500 MHz, -30 percent. 16 channels of GDDR6 at the 9070 XT's per-channel rate; the knob by the 9070 XT grid Stock: modelled | +| AMD Radeon RX 7600 XT | 16 GB | 13.0 | estimated | 17.8 (estimated) | 22.5x / 16.5x / 11.7x | 30.1x / 20.2x / 13.4x | 51.7x / 28.0x / 16.5x | ADLX -500 MHz, -30 percent. 8 channels; the card-in queue holds one for a PC measurement Stock: modelled | +| AMD Radeon RX 9060 XT | 16 GB | 10.0 | estimated | 13.7 (estimated) | 17.3x / 12.7x / 9.0x | 23.1x / 15.5x / 10.3x | 39.8x / 21.6x / 12.7x | ADLX -500 MHz, -30 percent. 8 channels of GDDR6 on RDNA 4; the card-in queue holds one Stock: modelled | +| NVIDIA H100 80GB HBM3 | DC | 2.0 | estimated | 2.58 (measured) | 3.5x / 2.5x / 1.8x | 4.6x / 3.1x / 2.1x | 8.0x / 4.3x / 2.5x | 1400 MHz at 80 percent. the premium 240 to 280 W at stock says half of it is the clock; a lock on an owned host (Hopper at 1,980 MHz boost, HBM3-bound): about 500 W (2.0); band 1.9 to 2.4; rented hosts refuse -lgc Stock: the denominator sweep, RunPod, 13:25 UK: class v3 252.96 MH/s at 382.4 W (1.51), class v5 241.34 at 621.6 W (2.58, 7 samples, the SM throttled to 1,590 MHz under the 700 W cap); the 7 and 8 October pods read class v4 250.6 at 695.1 W (2.77); -lmc answered 'use --lock-memory-clocks-deferred' and the memory clock stayed 2,619; stock, lock owed | +| NVIDIA L40S | DC | 3.78 | estimated | 5.29 (measured) | 6.5x / 4.8x / 3.4x | 8.7x / 5.9x / 3.9x | 15.0x / 8.2x / 4.8x | 1860 MHz at 60 percent. the Ada shape on the measured stock rows (class v3 220.7 W, class v4 277.6 W); re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium) Stock: class v5 measured (13:49 UK): 56.49 MH/s at 298.7 W (5.29, 46 samples, SM 2,520); class v3 56.35 at 221.5 W on the same host; the v4watts pod read class v4 56.4 at 277.6 W; stock, lock owed | +| NVIDIA A100-SXM4-80GB | DC | 2.89 | estimated | 2.99 (measured) | 5.0x / 3.7x / 2.6x | 6.7x / 4.5x / 3.0x | 11.5x / 6.2x / 3.7x | 1200 MHz at 80 percent. the card already runs at 1,410 MHz and the 400 W host limit binds under class v5 (SM clock gives); a cap under it costs rate on Ampere, so the floor is within 5 percent of the measured stock row Stock: the denominator sweep, RunPod, 13:24 UK: class v3 138.06 MH/s at 294.9 W (2.14), class v5 133.11 at 398.1 W (2.99, 19 samples, at the host's 400 W limit, memory 1,593 MHz); the v4watts pod on a 500 W host read class v4 138.0 at 489.3 W (3.54); -lmc 'not supported' on this card; stock, lock owed | +| Intel Arc B580 | 12 GB | 10.4 | estimated | 10.4 (estimated) | 18.0x / 13.2x / 9.3x | 24.1x / 16.1x / 10.7x | 41.4x / 22.4x / 13.2x | stock, no lever. 10.6 to 11 MH/s measured on PC 2 (the enclosure), the watts unread; about 110 W by the board's class (OWED); no clock lever in the app for Intel | +| Intel Arc A750 | 8 GB | 18.8 | estimated | 18.8 (estimated) | 32.6x / 23.8x / 16.9x | 43.5x / 29.2x / 19.4x | 74.8x / 40.5x / 23.9x | stock, no lever. unmeasured; modelled from the B580 and the Alchemist board | +| Apple M5 Max | Apple | 1.4 | measured | 1.4 (measured) | 2.4x / 1.8x / 1.3x | 3.2x / 2.2x / 1.4x | 5.6x / 3.0x / 1.8x | stock, no lever. the GPU and DRAM channels of the IOReport meter (not the wall): class v3 27.08 MH/s at 21.0 W (0.78), class v4 26.67 at 37.3 W (1.40), class v5 about 1.43; the package about 17 W more; no lever (no clock cap on Apple silicon) | +| Apple M4 Max | Apple | 1.55 | estimated | 1.55 (estimated) | 2.7x / 2.0x / 1.4x | 3.6x / 2.4x / 1.6x | 6.2x / 3.3x / 2.0x | stock, no lever. the same 512-bit LPDDR5X (8,533 against 9,600 MT/s) and a 40-core GPU on N3E: about 26 MH/s; class v3 about 0.85 at the meter, class v5 about 1.55 (the M5 Max's rows scaled); a devnet row from an unnamed Apple laptop read 24.3 MH/s on class v4 | +| Apple M4 Pro | Apple | 1.65 | estimated | 1.65 (estimated) | 2.9x / 2.1x / 1.5x | 3.8x / 2.6x / 1.7x | 6.6x / 3.6x / 2.1x | stock, no lever. 256-bit LPDDR5X and a 20-core GPU: about 13.5 MH/s; the shadow's per-hash premium does not shrink with the part, so class v5 reads about 1.65 at the meter | +| Apple M3 Max | Apple | 1.75 | estimated | 1.75 (estimated) | 3.0x / 2.2x / 1.6x | 4.0x / 2.7x / 1.8x | 7.0x / 3.8x / 2.2x | stock, no lever. 512-bit LPDDR5-6400 and a 40-core GPU on N3B: about 24 MH/s; class v5 about 1.75 at the meter | + +To fold any other chip core figure (the research lane's convention, 13:5x): the edge on a row is the card's class v5 +microjoules over `E_mem + 101,170 x c`, with `E_mem` 0.466 (GDDR7 board), 0.321 (one HBM3 stack), 0.14 (the N2 SRAM +die), 0.18 (the custom HBM4E base die) and `c` the core's picojoules per forced op; at the k lane's synthesised +sequencer-core floor of 1.1 pJ per op at N3 (its per-unit figure before fetch, decode and the register file, due 15:00) +the chip's class v5 energy reads GDDR7 0.577, HBM3 0.432, SRAM 0.251, so the 5080's floor of 2.10 gives 3.6x, 4.9x and +8.4x and the M5 Max's 1.43 gives 2.5x, 3.3x and 5.7x; that figure is a floor on the core and the row at it is the +pessimistic column. + +What the table says: + +1. The honest floor per tier, measured: 32 GB 2.33 to 2.37 (the 5090 at its knee); 16 GB 2.06 to 2.10 (the 5080 at + 1,100 MHz); 12 GB 3.51 to 3.58 (the 4070 at its tune); 16 GB AMD 7.9 to 8.1 (the 9070 XT on the grid); Apple 1.40 + to 1.43 (the M5 Max, no lever). The 16 GB NVIDIA tier is cheaper per hash than the 32 GB tier at the knee, and the + estimated 5070 Ti and 5070 rows (1.7 to 2.1) say the 12 and 16 GB Blackwell cards are the honest NVIDIA floor: the + 5090's 170 SMs carry the shadow at the same picojoules per op as the 5080's 84 but its memory system draws more + per read (16 GDDR7 devices against 8). +2. The chip edge against the honest floor at k = 1 (a core as good as a GPU lane): GDDR7 1.9x to 2.1x on Blackwell at + the knee, 1.3x on the M5 Max; one HBM3 stack 2.2x to 2.4x and 1.5x; the N2 SRAM die 2.7x to 3.0x and 1.8x. At the + record's centre (k = 0.5): 2.7x to 3.0x, 1.8x; 3.3x to 3.6x, 2.2x; 4.5x to 5.0x, 3.1x. The served 2.1x stands as the + 5090 figure; the public sentence can carry the lower honest row. +3. The lock recovers half the shadow's premium on Blackwell (the 5090: 145 W to 82 W; the 5080: 83 W to 41 W) and a + third of the class v3 draw (330 to 223 W; 170 to 104 W); on Ada the 4070's tune took 30 W of 106 on class v3 and the + premium reads 30 W at the tune point; on Ampere the cap is the only lever and it costs rate past 1,800 MHz; on AMD + the ADLX offsets take 24 percent of the draw for no rate; on Apple nothing moves. +4. Every Ada and Ampere consumer row is estimated at its knee because no rented host allows `-lgc` and no founder + machine holds one but the 4070 (whose full class v4 ladder is owed to a PC 1 job). The rented stock rows are + measured and stand; the estimated knees carry bands of about plus or minus 10 percent and the rented-against-PC + watts spread of 15 to 20 percent on top. + +## 3. What moves the floor, per architecture (the knob set the measured rows support) + +| Architecture | The lever | What it does, measured | The tier points (Efficiency / Balanced / Max) | Known-failed | +|---|---|---|---|---| +| Blackwell (5090, 5080; 5070 Ti, 5070, 5060 Ti, 5060 by shape) | the core lock; the power cap is flat on this hash | the rate holds within 1.5 percent to 1,300 MHz on the 5090 and within 0.3 percent to 1,000 on the 5080; the draw falls a third on class v3 and the shadow's premium halves | 1,200 / 1,300 / unlocked on the 5090; 1,100 / 1,100 / unlocked on the 5080; 1,100 / 1,300 / unlocked as the prior on the others | the 5090 at 1,100 (-10.5 percent on class v4), the 5080 at 900 (-5.2 percent); the Power Helper's skip-rule fault (0.3.20) needs the padding lines | +| Ada (4090, 4080, 4070 Ti, 4070, 4060 Ti, 4060, L40S) | the core lock with a cap | the 4070's tune: 1,860 MHz and the 50 percent cap hold 30.95 MH/s at 79.5 W on class v3 (28.7 at 102.7 stock); a cap holds the rate until the SM clock falls under about 2,400 MHz (the search prior); the 4090's class v4 premium at stock is 100 W (lane 1), under the 5090's 145 for 40 percent fewer counted ops per second | 1,860 at 50 to 60 percent / 2,400 at 80 percent / unlocked | the 4070 Ti Super at a 210 W host limit with the SM at 2,400 lost 10 percent on class v4 (36.95 against 41.24 MH/s): a cap that binds under the shadow costs rate on Ada too | +| Ampere (3090, 3080, 3070, 3060, A4000 to A6000, A100) | the power cap only | a cap holds the rate until the SM falls under about 1,800 MHz; stock clocks sit at 1,900 to 2,000, so the lever is 10 to 15 percent of the draw; the 3060 Ti at a 130 W host cap held 33.06 MH/s at 128.7 W on class v4 | 80 percent with the lock at 1,800 as a ceiling / 90 percent / unlocked | the 3080 Ti at 63 percent with the SM at 749 MHz: 24 to 28 percent of rate lost | +| Hopper (H100) | the core lock on an owned host | unmeasured: rented hosts refuse `-lgc`; the premium 283 W at stock (11.2 pJ per op) says half of it is the clock | 1,400 at 80 percent / 1,600 at 90 percent / unlocked, all estimated | none measured | +| RDNA 4 (9070 XT; 9060 XT by shape) and RDNA 3 (7900 XTX, 7800 XT, 7600 XT by shape) | the ADLX core and power offsets (0.3.25); no memory knob; no elevation | the 9070 XT's grid: the rate flat at 18.9 MH/s across 24 rows, -500 MHz and -30 percent = 149.3 W against 202 | -500 MHz, -30 percent / -300 MHz, -15 percent / stock | Ember run 6 aborted on "card reports 0 W" (fixed bd7fcf4); the ADLX sampler window bug (fixed) | +| Apple (M5 Max measured; M4 Max, M4 Pro, M3 Max by shape) | none | no clock cap on Apple silicon; the GPU draws 11 W at the hash and 27 W with the shadow, the DRAM 10 W throughout | stock only (the max tier, source stock) | none | +| Intel (B580 measured for rate; A750 by shape) | none in the app | measure only; the watts unread on the B580 | stock only | a kit without the Intel rotate-fold rewrite fails its self-test on Arc (a build fault, not an Arc result) | + +The one rule under the table: a step that drags the memory clock under 95 percent of baseline is marked and cannot +win, because on this hash the memory clock is the rate and the core clock is only the shadow's cost; the Ember 2 +climb may raise the memory clock (5 percent of the range per probe) where the vendor exposes it, and no measured row +yet shows a gain from it (the 5090's memory sits at 13,801 of 14,001 MHz). + +## 4. The LPDDR6 and unified-memory tier, five years out + +The method. The M5 Max row is the only measured unified-memory point and it splits three ways at the meter: the DRAM +rail 10.2 W at 27.08 MH/s x 128 reads = 2.94 nJ per dependent read (LPDDR5X-9600, 512-bit, 32 channels of 16 bits); +the GPU 11.0 W at the hash = 0.41 microjoules per hash of issue and latency-hiding cost; the shadow +16 W = 0.62 +microjoules (6.9 pJ per counted op). Each device below is modelled by scaling those three terms: reads per second by +the part's sub-channel count at the M5 Max's 108 M dependent reads per second per 16-bit channel (the rate is +activate-bound per bank, not pin-rate-bound, so 14.4 Gbps moves it little); DRAM energy per read by the generation +(LPDDR6 at JESD209-6's lower VDD and the 32-byte atom, which halves the over-fetch of a 4-byte read against LPDDR5X's +64-byte burst: 2.0 to 2.3 nJ per read at the meter against 2.94, approximate); the GPU term by the vendor's measured +latency-hiding (Apple 0.41 microjoules per hash; AMD's RDNA reads 2.4 G dependent reads per second at 199 W on the +9070 XT, so its GPU term is about 7 microjoules per hash; NVIDIA's Blackwell at a 128-bit board (the 5060) about 1.5 +at the knee); the shadow term by the vendor's ALU picojoules per op (Apple 6.9 measured, NVIDIA 6.4 at the knee, AMD +about 3 W for the whole shadow on the 9070 XT, so near zero at the card's rate). Every row is modelled; none is a +measurement, and the first LPDDR6 part to be sold will replace its row. + +| Device class (5 years out) | Memory | Modelled MH/s | DRAM / GPU / shadow, microjoules per hash | Class v5 at the meter, microjoules per hash | GDDR7 board edge k = 0.5 / 1 | HBM3 stack | N2 SRAM die | Custom HBM4E base die (0.18 + shadow) | +|---|---|---|---|---|---|---|---|---| +| Apple Max-class on LPDDR6 (an M7 or M8 Max, 2028 to 2030: 576-bit, 24 channels of 24 bits = 48 sub-channels, a 40 to 48-core GPU at N2) | LPDDR6-14400 | about 41 | 0.27 / 0.35 / 0.56 | **1.18** (the package about 1.6 to 1.7) | 1.5x / 1.06x | 1.8x / 1.2x | 2.5x / 1.5x | 2.4x / 1.4x | +| Apple Pro-class on LPDDR6 (384-bit, 32 sub-channels) | LPDDR6 | about 27 | 0.27 / 0.37 / 0.58 | 1.22 | 1.5x / 1.1x | 1.9x / 1.3x | 2.6x / 1.6x | 2.4x / 1.5x | +| Apple M5 Max today, for the comparison | LPDDR5X-9600 | 27 measured | 0.38 / 0.41 / 0.62 | 1.40 measured (v5 1.43) | 1.8x / 1.3x | 2.2x / 1.5x | 3.1x / 1.8x | 2.8x / 1.7x | +| AMD Strix Halo class and its LPDDR6 successor (256-bit LPDDR5X-8000 today, 40 CU RDNA 3.5; approximate) | LPDDR5X then LPDDR6 | about 12 (the GPU's latency hiding binds, not the memory: the 9070 XT's 64 CU read 2.4 G per second) | 0.35 / about 6 / about 0.2 | about 6.5 (band 5 to 9) | 8x / 6x | 10x / 7x | 14x / 8x | 13x / 8x | +| NVIDIA GB10 class (DGX Spark, N1X: 256-bit LPDDR5X-9400, a 48-SM Blackwell GPU; approximate) | LPDDR5X then LPDDR6 | about 13.5 | 0.33 / about 2.5 at a lock / 0.65 | about 3.5 (band 3 to 4.5) | 4.4x / 3.1x | 5.4x / 3.6x | 7.5x / 4.4x | 7x / 4.2x | +| Qualcomm X Elite class (128-bit LPDDR5X-8448, 8 channels; Adreno X1; no worker exists; approximate) | LPDDR5X then LPDDR6 | about 7 | 0.35 / about 2.5 / about 0.8 | about 3.7 (band 3 to 5) | 4.7x / 3.3x | 5.7x / 3.8x | 8x / 4.7x | 7.4x / 4.5x | +| MediaTek Dimensity class (64-bit LPDDR5X, 4 channels; a phone; approximate) | LPDDR5X then LPDDR6 | about 3.4 | 0.35 / about 2 / about 0.9 | about 3.3 | 4.2x / 3x | 5.1x / 3.4x | 7.1x / 4.2x | 6.6x / 4x | +| LPDDR6 controller chip, 32 channels (lane B's row: the chip built on the honest tier's own memory) | LPDDR6 | about 100 per chip | 0.25 to 0.30 at zero shadow; + 0.32 / 0.65 | 0.57 to 0.62 / 0.90 to 0.95 | against the Apple LPDDR6 row: 2.0x / 1.3x | | | | + +What the rows say: + +1. The honest tier five years out is Apple's unified-memory part on LPDDR6 at about 1.2 microjoules per hash under class + v5 at the meter, 15 percent under today's M5 Max; the gain is the DRAM term (0.38 to 0.27, the 32-byte atom and the + lower rail) and the GPU term at N2, not the pin rate. The other unified-memory vendors model 3 to 10 microjoules + because their GPUs hide a dependent read's latency worse (AMD's RDNA 8x worse than Apple's per read, measured on + the 9070 XT), and the memory does not rescue a GPU term that large. So "the unified-memory SoC tier" as the reference + joule means the Apple tier specifically, until a measurement on a Strix or GB10 part says otherwise. +2. Against the Apple LPDDR6 row every chip's edge is the lowest in the record: the GDDR7 board 1.5x at k = 0.5 and + 1.06x at k = 1 (at parity with a laptop at a core as good as a GPU lane); the N2 SRAM die 2.5x / 1.5x; the custom + HBM4E base die 2.4x / 1.4x; the LPDDR6 controller chip 2.0x / 1.3x. The chips lane B priced at 13x to 17x against + the stock 5090 are 1.5x to 2.5x against the best honest joule with the shadow on. +3. The reference joule should be the best honest joule, stated as a rule, not a fifth layer: the layers change what a + chip can be built as; the denominator changes what the edge is called. The public text carries the edge over the + Apple tier (1.3x at k = 1 today on GDDR7, 1.8x on the SRAM die) and over the 16 GB Blackwell card at its knee (1.9x + and 2.7x), with the stock 5090 figure retired from the headline. +4. Per-tier scoring. (a) The shadow sizing (layer 1's program-length band): YES, and it already is: the 2.0 rule caps N + at the card that loses 5 percent first, which is the Apple tier (130,000 ops on the M5 Max against 210,000 on the + 5090 at 431 W and about 150,000 at its knee). Sizing N to the Apple ceiling rather than the 5090's costs the 5090 + tier: at N = 130,000 the 5090 at its knee pays 6.4 pJ x 131,170 = 0.84 microjoules of shadow instead of 0.65 (+0.19, + +8 percent of its electricity at 2.37 to 2.56), its GDDR7 edge at k = 1 moves from 2.13x to 1.95x and at k = 0.5 + from 3.0x to 2.9x; the M5 Max pays +0.21 (1.43 to 1.64, +15 percent) for 1.3x to 1.25x at k = 1. The shadow's + extra length buys about 0.15x of edge on every tier for 8 to 15 percent of every honest miner's electricity: the + priced answer is to keep N at 100,000 and let the per-era draw move inside the band, not to size it up to the Apple + ceiling. (b) The acceptance floor (layer 4, the (c''') ratio and the F8 uniformity test): NO per-tier scoring. The + floor is a property of the program's address distribution against a chip's on-die SRAM (the 1.067x hot-set ceiling), + the same number whichever honest card runs it; scoring it per tier would change the figure for nobody and would + invite a per-card class menu, which section 6 of the research file shows can never beat the single best class. +5. The dataset stays inside 16 GB unified memory (8 GiB at the top of the schedule) so the honest tier keeps mining: + lane B's point stands and this file adds a number: a 16 GB Mac is out at the candidate 10 GiB step and pays the + measured -12 to -22 percent rate cost of a larger working set before any limit; the Apple LPDDR6 row above is a + 36 GB or larger part. + +## 5. The tiers statement for Ember (keyed by class v5) + +The table the app reads: `app/igneum-app/tiers/class-v5-tiers.json`, 30 card classes, 5 measured (the 5090, 5080, +4070, 9070 XT, M5 Max), the rest estimated from the measured stock rows and the architecture's shape in section 3. +Each entry carries the three tiers as rows in the shape `src/ember.rs tier_from_json` reads back from a card's state +(`id`, `clock_mhz`, `power_pct`, `mem_mhz`, `limit_w`, `mhs`, `w`; `mhw` and `source` as `Tier::json` writes them) plus +`label` (measured or estimated), `uj`, `note` and `src`; the AMD rows carry `core_offset_mhz` and `power_offset_pct` +for the ADLX knob; a card with no lever carries the `max` tier only, source `stock`. The validator +(`class-v5-tiers.mjs`) refuses a class other than v5, a tier outside the three, a power rung outside 50 to 100, a +missing field, a `uj` that is not watts over rate, a tuned row dearer than stock, a max tier that is not stock, an AMD +row without its offsets, and a missing card class of the brief; the test (`class-v5-tiers.test.mjs`, 10 of 10 on +igneum-build-3 at 13:0x) runs the shipped file, the measured rows, the match rule (a 5070 Ti is not a 5070), the stale +rule and the known-failed cases. + +| Tier | The rule (the ember-tiers-25 definition) | Blackwell | Ada | Ampere | AMD | Apple, Intel | +|---|---|---|---|---|---|---| +| Efficiency | the best MH per watt row of the card's search outright | the lock one rung past the knee at 100 percent power: 1,200 on the 5090 (measured), 1,100 on the 5080 (measured), 1,100 as the prior elsewhere | the lock at 1,860 with the 50 to 60 percent cap (the 4070 measured) | the 80 percent cap with the lock at 1,800 as a ceiling (no row under it) | -500 MHz core, -30 percent power (the 9070 XT measured) | stock (no lever) | +| Balanced (the default from install) | the best MH per watt row within 1 percent of the top rate | the knee: 1,300 on the 5090 (measured), 1,100 on the 5080 (the same row), 1,300 as the prior elsewhere | 2,400 at 80 percent (the Ada prior) | the 90 percent cap, no lock | -300 MHz, -15 percent (inside the flat band) | stock | +| Max | the stock row (unlocked, 100 percent) | stock | stock | stock | stock | stock | + +The re-measure rule after a class flip, as the table carries it (`remeasure_rule`): + +1. A set measured under one program class never applies as current under another (`tiers_stale`: both classes known + and different). The stored Efficiency and Balanced points are the provisional START of the re-measure, not its + result: the search begins at the stored point and walks one rung either way on the clock and the power ladder, + the fingerprint checked on every step; the Max tier is stock and is never stale. +2. The measured flip: class v4 to class v5 on the 5090 at the 1,300 MHz lock cost 0.0 percent of rate and +2.0 + percent of watts; the knee did not move. The expected flip cost for any class whose shadow stays inside the + latency-bound band (the op count and the mix inside layer 1's draw band) is 0 to 1 rung of knee; a class whose shadow + leaves the band (doubling the op count: the 5090 at 431 W binds at 210,000 ops) re-measures from stock, not from + the stored point. +3. The set also re-measures weekly (`PERIOD_S`) and on a driver major change (the prior key carries driver major and + class), and a confirm check that beats its prior by over 1 percent on MH per watt asks for the full plan. + +## 6. The denominator sweep (rented, 8 October 13:05 to 14:1x UK, the stock rows the record lacked) + +Three drivers of the fleet lane's model sweep and then a direct ssh runner: `box-cardbench-v2.sh` (class v3, the v5 +kit's fingerprint, the memprobe ceiling), `box-cardbench-v4watts.sh` (the class v4 shape with the paired class v3 run) +and, from 13:21 on the coordinator's full-spend order, `box-cardbench-v2m.sh` on 16 card classes in parallel (the +class v5 kit's bench run for 200 batches of 2^24 under the 1 Hz sampler, so the class v5 watts are a measured mean +over busy samples from 8 s in; then `-lmc` to the card's maximum and a second class v5 run when the host accepted it). +One one-shot pod per card class on RunPod or Vast under the consumer cap, destroyed at the end of each row; the rows +in `~/igneum-fleet/cardbench/rows.jsonl` under `sweep: 2026-10-08-denominator` and `-v5`; the lane's spend about USD 5 +of its USD 100 (the pods ran 3 to 10 minutes each). No rented host allowed `-lgc`; the two that accepted `-lmc` (the +H100 and A100) left the memory clock where it was, so every row here is stock and the knees of section 2 stay +estimated where no founder machine holds the card. + +Two faults found on the way, for the fleet lane: (1) the sweep driver's ssh wait read every Vast pod of the 13:21 wave +as "never answered ssh in 10 minutes" while a direct `ssh` to the same host and port answered at once (13 pods, all +live; the rows were then taken by a direct runner, `~/igneum-fleet/denom-direct.sh`, which keys on the provider's +own ssh host and port and nothing in the registry); (2) the registry lock `~/igneum-fleet/boxes.json.lock` was held +from 13:32 by three `dn3-q05.py` processes of another lane, so every `Registry.patch` from this lane blocked (a +re-rent sat 12 minutes on a live pod and then destroyed it); the lane's scripts now write the registry best-effort +under a 15 s alarm. The rented stock rows against the PC rows on the one card measured both ways (the 5080): class v5 +71.35 MH/s at 248.0 W rented against class v4 71.41 at 253.1 W on PC 1, within 3 percent, so the 18 percent class v3 +spread of the morning was that host and not the method. + +| Card | Host | Class v3 (MH/s at W = microjoules) | Class v4 shape or class v5 (MH/s at W = microjoules; samples) | The knobs on the host | Cost | +|---|---|---|---|---|---| +| RTX 4090 24 GB | runpod m1tstl1h1b7r0o (595.91.07), limit 450.0 W | 70.094 at 222.6 W = 3.18 | class v5 70.253 MH/s (MATCH), watts not sampled on this row | -lgc refused | USD 0.032 | +| RTX 5060 8 GB | vast 54840005 (580.126.09), limit 145.0 W | | class v4 16.234 at 87.8 W = 5.41 (v4 over v3 20.4 percent on this host) | | USD 0.009 | +| RTX 5060 8 GB | vast 54840004 (580.126.09), limit 145.0 W | 24.774 at 80.7 W = 3.26 | class v5 31.312 MH/s (MATCH), watts not sampled on this row | -lgc refused | USD 0.011 | +| RTX 5080 16 GB | vast 54840017 (570.133.07), limit 300.0 W | | class v4 70.951 at 239.8 W = 3.38 (v4 over v3 41.1 percent on this host) | | USD 0.052 | +| RTX 3080 10 GB | vast 54840023 (580.159.03), limit 130.0 W | | class v4 24.007 at 129.2 W = 5.38 (v4 over v3 3.0 percent on this host) | | USD 0.025 | +| RTX 3060 12 GB | vast 54840846 (580.126.20), limit 170.0 W | | class v4 26.886 at 166.1 W = 6.18 (v4 over v3 44.6 percent on this host) | | USD 0.007 | +| RTX 4070 12 GB | vast 54840856 (580.173.02), limit 200.0 W | 30.829 at 107.1 W = 3.47 | class v5 30.878 MH/s (MATCH), watts not sampled on this row | -lgc refused | USD 0.023 | +| A100 80 GB | runpod miuoe6gkcb1rhz (580.126.16), limit 400.0 W | 138.062 at 294.9 W = 2.14 | class v5 133.548 MH/s (MATCH), watts not sampled on this row | -lgc refused | USD 0.075 | +| H100 80 GB | runpod zosqj1s802dk3x (580.126.09), limit 700.0 W | 252.959 at 382.4 W = 1.51 | class v5 241.342 MH/s (MATCH), watts not sampled on this row | -lgc refused | USD 0.216 | +| RTX 3090 24 GB | runpod sbrhhunqui25d0 (580.65.06), limit 310.0 W | 60.008 at 294.6 W = 4.91 | class v5 61.486 MH/s (MATCH), watts not sampled on this row | -lgc refused | USD 0.014 | +| RTX 3080 10 GB | vast 54841582 (580.159.03), limit 180.0 W | 49.832 at 177.8 W = 3.57 | class v5 44.308 MH/s (MATCH), watts not sampled on this row | -lgc refused | USD 0.024 | +| RTX 5080 16 GB | vast 54845199 (570.133.07), limit 300.0 W | 71.16 at 159.4 W = 2.24 | class v5 71.349 at 248.0 W = 3.476; 39 samples, SM 2769, memory 14801 | -lgc refused; -lmc refused | USD 0.014 | +| L40S 48 GB | vast 54845608 (595.71.05), limit 350.0 W | 56.354 at 221.5 W = 3.93 | class v5 56.493 at 298.7 W = 5.287; 46 samples, SM 2520, memory 9001 | -lgc refused; -lmc refused | USD 0.04 | +| RTX 4080 16 GB | vast 54845190 (595.84), limit 320.0 W | 40.694 at 141.5 W = 3.48 | class v5 40.8 at 200.7 W = 4.919; 72 samples, SM 2760, memory 10801 | -lgc refused; -lmc refused | USD 0.017 | +| RTX 3080 10 GB | vast 54845161 (580.178.04), limit 170.0 W | 50.708 at 169.2 W = 3.34 | class v5 33.37 at 169.9 W = 5.091; 90 samples, SM 689, memory 9251 | -lgc refused; -lmc refused | USD 0.008 | +| RTX 4090 24 GB | vast 54845886 (595.84), limit 250.0 W | 62.401 at 200.5 W = 3.21 | class v5 62.684 at 249.9 W = 3.987; 46 samples, SM 2579, memory 10251 | -lgc refused; -lmc refused | USD 0.02 | +| RTX 5060 8 GB | vast 54845177 (595.84), limit 140.0 W | 30.76 at 78.8 W = 2.56 | class v5 30.804 at 115.7 W = 3.756; 99 samples, SM 2715, memory 13801 | -lgc refused; -lmc refused | USD 0.011 | +| RTX 5060 Ti 16 GB | vast 54845162 (580.126.09), limit 180.0 W | 30.747 at 82.6 W = 2.69 | class v5 30.843 at 123.9 W = 4.017; 96 samples, SM 2835, memory 13801 | -lgc refused; -lmc refused | USD 0.013 | +| RTX 3060 12 GB | vast 54845154 (580.126.09), limit 170.0 W | 26.534 at 120.4 W = 4.54 | class v5 26.53 at 169.8 W = 6.4; 117 samples, SM 1806, memory 7301 | -lgc refused; -lmc refused | USD 0.008 | +| RTX 4070 12 GB | vast 54845860 (580.126.09), limit 210.0 W | 28.401 at 116.3 W = 4.09 | class v5 28.433 at 165.5 W = 5.821; 108 samples, SM 2820, memory 9801 | -lgc refused; -lmc refused | USD 0.011 | +| RTX 4060 Ti 16 GB | vast 54849184 (580.159.03), limit 100.0 W | 18.735 at 79.1 W = 4.22 | class v5 18.75 at 99.8 W = 5.323; 163 samples, SM 2668, memory 8751 | -lgc refused; -lmc refused | USD 0.016 | + +Not reached by the class v5 sweep (stock, their class v4 rows of the morning stand within 2 percent): the 5070 Ti and +the 5070 (two Vast hosts each, 14:08 and 14:13 UK, never accepted the fleet key in 15 minutes); the 3070 (two hosts +closed the connection mid-bench). The sweep closed at 14:35 UK: 20 rows landed, no pod left on either provider +(audited 14:40), the lane's spend about USD 5 of its USD 100. + +## 7. Consequences per tier + +| Tier | What this file means | What is being done | +|---|---|---| +| Home miner, one 8 GB card (5060, 4060, 3070) | the Blackwell 8 GB card at its knee is 2.15 microjoules (estimated), inside 10 percent of the 5090's measured floor; the Ada and Ampere 8 GB cards 3.8 to 4.8. The lever is the Efficiency tier: on a 5060 about 40 W of 110 back for no rate (estimated); on a 3070 about 20 W of 196 | the tiers table ships the prior; the card's own search measures it; the 5060 and 4060 watts rows are the sweep's | +| One 12 GB card (5070, 4070, 3060) | the 5070 at its knee about 1.75 (the lowest NVIDIA row in the record, estimated); the 4070 measured 3.51 at its tune; the 3060 4.9 | the 4070's class v4 ladder below 1,860 MHz is owed to a PC 1 job (the hash lane's scripts, not this lane's hands) | +| One 16 GB card (5080, 5070 Ti, 5060 Ti, 4080, 4060 Ti, 9070 XT) | the 5080 measured 2.06 to 2.10 at 1,100 MHz, 42 percent of its stock draw back for 0.3 percent of rate; the 5070 Ti about 1.70 (estimated); the 9070 XT 8.1 measured on the grid, 24 percent of its draw back for nothing | the 5060 Ti ladder on PC 2 (the card-in job); the 9070 XT grid lands in the AMD tier rows | +| One 24 or 32 GB card (5090, 4090, 3090) | the 5090 at its knee 2.33 to 2.37, 33 percent of its electricity back for 1.5 percent of rate; the 4090 about 3.4, the 3090 about 6.4 (estimated: Ampere's cap is a small lever) | the Balanced tier is the default from install; the 4090 and 3090 stock rows are the sweep's | +| Apple (M-series) | the honest best per joule the project owns: 1.40 to 1.43 measured on the M5 Max, nothing to set; the M4 and M3 parts within 25 percent (estimated); five years out about 1.2 on LPDDR6 | the public edge is stated against this tier; the dataset stays inside 16 GB unified memory | +| A rig | per card as above; a 5090 rig at the Balanced tier draws 319 W per card instead of 476 on class v5; a 5080 rig 147 instead of 253 | the tiers table | +| A pool user | nothing changes in shares or payout from any row here | | +| A chip | the honest floor it must beat is 2.1 microjoules on a mass-market 16 GB Blackwell card at its knee (1.9x at k = 1 on GDDR7, 2.7x on the N2 SRAM die) and 1.43 on an Apple laptop (1.3x and 1.8x); five years out 1.2 on the Apple LPDDR6 part (1.06x and 1.5x) | the research lane's synthesis carries the number | +| The public claim | the honest sentence per joule: "a chip that stores the dataset keeps the card's whole-card energy over its memory energy: under 2x against a 16 GB Blackwell card at its knee and 1.3x against an Apple laptop for a core as good as a GPU lane; 2.7x and 1.8x against a 2 nm SRAM store" | to the Counter lane for the chip texts; nothing served moves from this file | + +## 8. Unverified and owed + +- Every Ada and Ampere knee is estimated: no rented host allows `-lgc`, and the founder's machines hold one Ada card + (the 4070, its class v4 ladder below 1,860 MHz owed to a PC 1 job through the hash lane's scripts) and no Ampere. + The estimated knees carry about plus or minus 10 percent, and the rented stock watts read 15 to 20 percent under a + PC's on the one card measured both ways (the 5080). +- The 5070 Ti and 5070 floors (1.7 to 2.1) are the strongest claims in this file and both are estimated from stock + rows; a 5070 Ti ladder on PC 1 or PC 2 (the card-in job's queue) would settle whether the honest NVIDIA floor is a 16 + GB card. +- The AMD rows other than the 9070 XT are modelled on one card; the 9060 XT and 7600 XT in the card-in queue will + replace two of them. +- The Apple M4 Max, M4 Pro and M3 Max rows are modelled on the M5 Max's split; a Metal bench on any of them with the + IOReport meter would replace its row in an hour. +- Section 4's LPDDR6 rows are modelled on JESD209-6's public summary (the bank count and tFAW are behind the + paywall, lane B's note) and on the M5 Max's three-way split; the Strix, GB10 and Qualcomm rows rest on the vendor's + measured latency hiding on other parts and are approximate. +- The 4060's watts (three rented hosts, no power sensor), the B580's watts, the H100's lock, the A750 entirely. +- The class v5 stock rows of the 5070 Ti, the 5070 and the 3070 (section 6: the hosts never took the key or closed + the connection); their class v4 stock rows stand within 2 percent. +- Two fleet-tooling faults for the fleet lane (section 6): the sweep driver's ssh wait misreads live Vast pods, and a + registry flock held for an hour by another lane's processes blocks every `Registry.patch`; both cost this lane 40 + minutes and five pods. + +## 9. The reading for the 15:45 BST close (five sentences) + +The honest joule under class v5 is 2.06 to 2.10 microjoules per hash on a 16 GB Blackwell card at its 1,100 MHz lock +(measured), 2.33 to 2.37 on the 5090 at its knee (measured), about 1.7 to 2.1 on the 12 and 16 GB Blackwell cards +(estimated from their measured stock rows), 1.40 to 1.43 on an Apple M5 Max with nothing to set (measured), and the +only software lever that moves it is the operating point: the core lock on Blackwell and Ada (worth 34 to 41 percent +of the class v5 stock draw measured today on the 5080 and the 4070), the cap on Ampere (10 to 15 percent, and a cap +under the shadow costs rate one for one: the 3080 at 170 W lost a third of its class v5 rate), the ADLX offsets on +AMD (24 percent), nothing on Apple and Intel; the occupancy knob is 1 to 2 percent and the memory clock is untouched. +Against those floors the stored-dataset chips read 1.9x to 2.1x on GDDR7, 2.2x to 2.4x on one HBM3 stack and 2.7x to +3.0x on a 2 nm SRAM die at a core as good as a GPU lane (6.4 pJ per forced op), 2.6x to 3.0x, 3.2x to 3.6x and 4.4x +to 5.0x at the record's 3.2 pJ, and 3.6x to 4.0x, 4.8x to 5.4x and 8.2x to 9.3x at the k lane's 1.1 pJ floor; against +the Apple laptop 1.3x, 1.5x and 1.8x at 6.4 pJ; the served 2.1x stands as the 5090 figure and the honest headline is +under 2x against a mass-market card at a core as good as a GPU lane. Five years out the honest tier is Apple's +unified-memory part on LPDDR6 at about 1.2 microjoules (modelled), against which the GDDR7 chip is at parity at 6.4 pJ +and the SRAM die 1.5x; the other LPDDR SoC vendors model 3 to 10 microjoules because their GPUs hide the latency +worse, so the reference joule is the Apple tier by name. The class should state resistance against the best honest +joule and keep sizing the shadow by the Apple tier's 5 percent point (N at 100,000, the band drawn per era), and +should not score the acceptance floor per tier; sizing N up to the Apple ceiling would cost every honest miner 8 to +15 percent of its electricity for about 0.15x of edge. The tiers table ships the measured points on the 5090, 5080, +4070, 9070 XT and M5 Max, the measured class v5 stock row on 14 classes and an architecture prior for the knee +everywhere else, with the rule that a class flip re-measures from the stored point (the measured v4 to v5 flip moved +the 5090's knee by nothing), and the rows still owed are the Ada and Ampere knees, which no rented host can give. diff --git a/docs/analysis/class-v6/floor/invention.md b/docs/analysis/class-v6/floor/invention.md index c655233c5..bd9434f9b 100644 --- a/docs/analysis/class-v6/floor/invention.md +++ b/docs/analysis/class-v6/floor/invention.md @@ -6,7 +6,7 @@ **The identity, as the record states it** (`docs/analysis/counter-asic-4-research.md` section 2): against the chip that stores the dataset, `edge = (E_card + F) / (E_mem + k F)`; at zero premium the edge is `E_card / E_mem` (3.6x on a 5090 at its 1,300 MHz knee against the GDDR7 board, measured card, modelled chip), and a shadow op with `k` under 1 never fully closes it. The one thing with `k = 1` by construction is the memory itself: the same devices on both sides. The record forced one DRAM operation per read (the activate and one 32-byte sector) and called every wider read "nothing to force: the chip already pays the sector". That is true up to 32 bytes; at 64 bytes the chip pays a second sector, and this lane's question was whether the honest card pays it at the DRAM's price or at its own. -**The candidate this lane found, measured today, and where it stands.** The dataset item is 64 bytes (16 words; spec 1.5). Reading the whole item (W = 16 words, the read-width branch's class `w64`, bit-exact on four runtimes, fingerprint `836e56e7d496e980`, the verifier +4 percent) forces a second 32-byte sector per read in the same open row: on the chip model's own inputs (909 pJ of activation plus 1,150 pJ of movement per sector, Micron's 4.5 pJ per bit, claimed) the GDDR7 chip's energy per hash rises from 0.466 to 0.62 microjoules (+33 percent, its rate unchanged), one HBM3 stack's from 0.321 to 0.40 (+24), and on floor lane 3's wire figure the N2 SRAM die's from 0.036 to 0.126 (66x to 19x). The design's "never 16 words" rested on one row, the 5090's 71.9 MH/s (-47 percent) in the exported kernel at full occupancy, while the same card's own 64-byte probe read -13 percent; so the lane rented cards and measured the card side at stock (section 3.1): **the rate question is settled per architecture, and the energy question kills the lever at stock.** A one-request form of the same kernel text (PTX `ld.global.L2::64B` on the first load of each item; bit-exact, the same fingerprint) holds the 4-byte rate on the RTX 4090 at full occupancy (63.65 against 64.73 MH/s, 98 percent, PASS) and on the RTX 5090 at a sparse shape (145.7 against 142.6 MH/s, sp170-w4, PASS); on the H100 the best form is -21 percent and the hint does nothing (FAIL); on the RTX 3090 the best form is -13 percent (FAIL). But the card pays the second sector at its own fabric's price, not the DRAM's 1.15 nJ: 8.6 nJ on the 4090 (+71 W at 8.3 G reads per second for no rate) and 4.7 nJ on the 5090 (+88 W at 18.6 G), so the energy per hash rises 34 percent on the 4090, 25 on the 5090, 33 on the H100's best form and 25 on the 3090, against the modelled chip's 33 (GDDR7) and 50 (HBM3). The sector's `k` is about 0.13 (4090) to 0.24 (5090) on GDDR7, under the ALU shadow's 0.3 to 0.8; the edge at zero shadow moves 0 on Ada, 7 percent on Blackwell (4.7x to 4.4x at stock) and 0.9x in the chip's favour on Hopper, and 0 with the shadow on (3.3x at `k` 0.5 either way). **KILL at stock on measured rows.** The one row that could revive it is the honest card's knee (a smaller fixed share and a lower fabric voltage; a rented pod refuses `-lgc`), owed as a single PC 1 row and not blocking anything: W = 16 stays out of class v6. +**The candidate this lane found, measured today, and where it stands.** The dataset item is 64 bytes (16 words; spec 1.5). Reading the whole item (W = 16 words, the read-width branch's class `w64`, bit-exact on four runtimes, fingerprint `836e56e7d496e980`, the verifier +4 percent) forces a second 32-byte sector per read in the same open row: on the chip model's own inputs (909 pJ of activation plus 1,150 pJ of movement per sector, Micron's 4.5 pJ per bit, claimed) the GDDR7 chip's energy per hash rises from 0.466 to 0.62 microjoules (+33 percent, its rate unchanged), one HBM3 stack's from 0.321 to 0.40 (+24), and on floor lane 3's wire figure the N2 SRAM die's from 0.036 to 0.126 (66x to 19x). The design's "never 16 words" rested on one row, the 5090's 71.9 MH/s (-47 percent) in the exported kernel at full occupancy, while the same card's own 64-byte probe read -13 percent; so the lane rented cards and measured the card side at stock (section 3.1): **the rate question is settled per architecture, and the energy question kills the lever at stock.** A one-request form of the same kernel text (PTX `ld.global.L2::64B` on the first load of each item; bit-exact, the same fingerprint) holds the 4-byte rate on the RTX 4090 at full occupancy (63.65 against 64.73 MH/s, 98 percent, PASS) and on the RTX 5090 at a sparse shape (145.7 against 142.6 MH/s, sp170-w4, PASS); on the H100 the best form is -21 percent and the hint does nothing (FAIL); on the RTX 3090 the best form is -13 percent (FAIL). But the card pays the second sector at its own fabric's price, not the DRAM's 1.15 nJ: 8.6 nJ on the 4090 (+71 W at 8.3 G reads per second for no rate) and 4.7 nJ on the 5090 (+88 W at 18.6 G), so the energy per hash rises 34 percent on the 4090, 25 on the 5090, 33 on the H100's best form and 25 on the 3090, against the modelled chip's 33 (GDDR7) and 50 (HBM3). The sector's `k` is about 0.13 (4090) to 0.24 (5090) on GDDR7, under the ALU shadow's 0.3 to 0.8; the edge at zero shadow moves 0 on Ada, 7 percent on Blackwell (4.7x to 4.4x at stock) and 0.9x in the chip's favour on Hopper, and 0 with the shadow on (3.3x at `k` 0.5 either way). **KILL at stock on measured rows.** The knee row, measured by the hash lane on PC 1 at 15:0x UK, closes it from the other side: at the 1,300 MHz lock the hinted form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x its energy per hash (section 6). W = 16 is out of class v6 at stock and at the knee. **Everything else on the brief is killed, with the number.** The tensor core: the record's `k` 0.03 to 0.3 is not defensible at its floor (the 0.04 pJ figure is INT4 at 0.46 V on a test chip with no memory system); shipping merchant silicon at nominal voltage reads 0.30 to 0.56 pJ per INT8 MAC (Meta MTIA v2 0.51, Qualcomm AI 100 Ultra 0.34, AMD MI355X 0.56, NVIDIA B200 0.44, Apple M4 ANE 0.30 measured; all claimed unless marked), and a Hopper tensor core under a pure MMA loop measured 0.34, so the honest band against the tile the class runs (1.5 pJ per MAC at the knee, measured) is `k` 0.2 to 0.4 and against the dense wide tile (0.83 at the knee) 0.4 to 0.7: equal to or under the ALU shadow's 0.3 to 0.8, never above it, and the Apple cost (-35 percent of rate at 1,024 tiles per hash, measured) kills it as content regardless. The RT core: traversal results are implementation-defined on every API (Vulkan "no ordering guarantee", DXR "no defined order", NVIDIA "could change depending on which driver, which GPU"), the acceleration structure is opaque, and a dedicated unit reads 4 to 33 nJ per ray against 290 to 750 nJ measured board-level on an RTX 2080 (`k` 0.01 to 0.2): dead on bit-exactness and on `k`. Memory-level parallelism per dollar: no asymmetry per channel, but a correction to the chip model: no 28 nm GDDR7 PHY exists (the shipped ones are N3 and FinFET; the oldest GDDR6 PHYs are 12 nm), so the record's cheapest chip (a USD 5 M project, a USD 17 M break-even cap) is not buildable; the floor is a 12 nm GDDR6 part at about USD 20 M to 30 M (cap USD 70 M to 100 M) or an N5-class GDDR7 part at USD 50 M to 75 M (cap 170 M to 250 M), modelled. Proof of latency: the chain checks values, never time; the block is 1 s and a DRAM round trip 0.1 to 0.4 microseconds; the farm's node is on its own LAN; a sequential per-block prefix favours the lower-latency side, which is the chip (about 4x). The time dimension on the address map: a bit permutation is firmware (a few hundred gates), no prefetch exists for a dependent chain, and the literature has no such scheme. The literature since 2023 holds nothing outside the identity; what it adds is a higher Ethash precedent (iPollo V2H, 0.14 J per MH, about 13x a 5090, vendor claim), the measured PAM3 I/O energies (SK hynix, ISSCC 2024) and the PHY-node fact above. Of this lane's own ideas, four more die on the identity (video decode, row-straddling, scratch in DRAM, independent chains per hash), and two items per read (W = 32) dies with W = 16. @@ -178,6 +178,18 @@ A per-block random challenge whose answer window is shorter than one DRAM round Reading: nothing published since 2023 offers a lever outside the identity; every energy figure is a streaming pJ per bit, and no one has measured a per-random-read joule on GDDR6, GDDR7 or HBM3 at the controller, so the record's 2.0 and 1.2 nJ stand as the only model and are owed a measurement nobody can rent (the AWS F2 hour of chip-model 5.3 is still the one HBM2 instrument). The new rows change two precedents: the Ethash band's top is about 13x (claimed) not 6.8x, and the Monero chip story has a shipped-but-unverified successor to the withdrawn X9. +### 2.7 Three precedents, sourced for the 15:45 close (the research lane's ask of 14:0x UK; every figure read 8 October 2026) + +A correction to the question as asked first: Monero did not go chip-free after November 2019; the Antminer X5 shipped in September 2023 at about parity to 1.5x per joule against the best measured CPU. + +| Precedent (launch) | The designers' claim | The chip that shipped | Measured edge per joule against the best commodity part | Months to the first chip | Sources | +|---|---|---|---|---|---| +| Monero RandomX (fork 30 November 2019) | design.md, Introduction: a PoW "must achieve device binding by targeting specific features of existing general-purpose hardware"; section 3.4 SuperscalarHash: light-mode ASICs "will be bottlenecked by SuperscalarHash ... their efficiency will be destroyed by the high power usage"; no numeric bound anywhere in the document (claimed) | Bitmain Antminer X5, preorders 29 August 2023, delivered late September 2023: 212 kH/s at 1,350 W = 157 H/J (claimed); Antminer X9 announced 26 December 2025, 1,000 kH/s at 2,472 W = 405 H/J (claimed), USD 5,600, listed for July 2026, reported pulled on 31 July 2026 by a reseller with no Bitmain statement | Ryzen 9 9950X on xmrig 20.66 kH/s at 199 W = 104 H/J (hashrate.no, one verified submission, measured); Kryptex 27 kH/s at 170 W = 159 H/J (unlabelled); the X5 1.0x to 1.5x; the X9, if it exists, 3.9x | 46 | https://github.com/tevador/RandomX/blob/master/doc/design.md ; https://www.asicminervalue.com/miners/bitmain/antminer-x5 ; https://github.com/monero-project/monero/issues/10270 ; https://oneminers.com/blogs/news/antminer-x9-cancelled-what-bitmain-pulling-the-model-means-for-monero-mining ; https://www.hashrate.no/cpus/9950x/XMR ; https://pool.kryptex.com/device/cpu/AMD/ryzen-9-9950x | +| Ethereum Ethash (mainnet 30 July 2015; PoW ended 15 September 2022, ETC continues) | a memory-hard DAG to keep GPUs competitive; no numeric bound (claimed) | first: Antminer E3, announced 3 to 4 April 2018, 180 MH/s at 800 W = 0.23 MH/J, shipped July 2018 with most units slipping to Q4 (claimed); current: iPollo V2H, released November 2024, 3,400 MH/s at 475 W (both plus or minus 10 percent) = 7.2 MH/J (vendor page, claimed) | RTX 4090 on Etchash 127 MH/s at 249 W = 0.51 MH/J; RTX 5090 215.8 MH/s at 405 W = 0.53 (hashrate.no, community-measured); the E3 under a good 2018 GPU per joule; the V2H 14x the 4090, 13.5x the 5090 | 36 | https://cointelegraph.com/news/bitmain-releases-ethash-asic-miners ; https://www.tweaktown.com/news/61527/bitmain-pushes-back-ethereum-asic-miner-now-coming-july/index.html ; https://www.ipollo.com/products/ipollo-v2h ; https://asicminervalue.com/miners/ipollo/v2h ; https://www.hashrate.no/gpus/4090 ; https://www.hashrate.no/gpus/5090 | +| Kaspa kHeavyHash (mainnet 7 November 2021) | no resistance claimed: designed for optical PoW, described as ASIC-friendly by design (secondary sources) | IceRiver KS0, August to September 2023, 100 GH/s at 65 W = 1.54 GH/J; Antminer KS3, October 2023, 9.4 TH/s at 3,500 W = 2.7 GH/J; Antminer KS5 Pro, March 2024, 21 TH/s at 3,150 W = 6.67 GH/J (all claimed) | RTX 4090 2,080 MH/s at 226 W = 9.2 MH/J (Kryptex medium profile, GPU-reported watts); the KS0 167x, the KS5 Pro 725x | 21 to 22 | https://www.asicminervalue.com/miners/iceriver/ks0 ; https://www.asicminervalue.com/miners/bitmain/antminer-ks3 ; https://www.asicminervalue.com/miners/bitmain/antminer-ks5-pro ; https://www.kryptex.com/overclocking/nvidia-rtx-4090-micron-24gb-medium-overclock ; https://www.btc-echo.de/academy/bibliothek/kaspa-mining/ | + +Reading: RandomX promised parity and got roughly it (1.0x to 1.5x after 46 months; the one chip claiming more never shipped); Ethash promised nothing numeric, bought 36 months before a chip worse than a GPU, and sits at about 14x today on a memory system without a GPU; Kaspa claimed nothing, got its chip in 21 months and went 167x to 725x in six. Every ASIC watt is nameplate and every CPU and GPU figure a community test table, so the edges carry about 20 percent either way. + ## 3. This lane's own ideas ### 3.1 The second sector: W = 16 words, the whole 64-byte item (KILL at stock on measured rows; the knee row owed) @@ -206,7 +218,7 @@ Reading: nothing published since 2023 offers a lever outside the identity; every The rows are the record: the 4090 and H100 pods were destroyed before their raw logs were copied home (the copy step failed quietly on a shell expansion), so their figures above are the extracted rows read off the pods in the session; the 3090's raw logs are at `~/igneum-fleet/fl5-results/3090-*` (result.log, result2.log, power.csv, power2.csv). Spend: about USD 6 of the USD 150 allowed. -**What the rows say, on the identity.** (1) The rate question: the exported form's -47 to -60 percent is a request-shape and occupancy effect, as the 5090's probe said; one PTX qualifier on the first load makes the 64-byte item one L2 request and holds the 4-byte rate on Ada at full occupancy (98 percent), while on Hopper the hint changes nothing (the H100's loss is elsewhere: its HBM3 pseudo-channel moves a 64-byte access as two bursts and its best shape is 79 percent) and on Ampere the best shape is 87 percent. (2) The energy question, which decides it: the card pays the second sector at the cost of a whole dependent read, not at the DRAM's movement term. On the 4090 the hinted form draws 71 W more at the same 64.7 MH/s: 71 W over 8.3 G reads per second is **8.6 nJ per second sector**; on the 5090 at sp170-w4, 88 W more at 145.7 MH/s: **4.7 nJ**; against the 1.15 nJ the DRAM device charges for it (the 4090's GDDR6X at 6 pJ per bit would be 1.5), so the other 7 nJ is the card's own L2, crossbar, L1 and the SMs' longer wait, the same anatomy as the record's 8.7 nJ whole-card marginal per dependent read (15.1a). In the identity's terms `F` is 128 x 8.6 nJ = 1.1 microjoules per hash on the 4090 (0.6 on the 5090) and the chip's cost for the same work is 128 x 1.15 = 0.15: **`k` about 0.13 on the 4090, 0.24 on the 5090**, under the ALU shadow's 0.3 to 0.8 and no better than the L2 hot table's. The energy per hash rises 34 percent on the 4090 and 33 percent on the H100's best form against the modelled chip's 33 (GDDR7) and 50 (HBM3): the edge at zero shadow moves 0 on Ada against the GDDR7 chip and 0.9x in the chip's favour against HBM3 on Hopper; against the SRAM die the chip's 66x to 19x becomes about 25x against the card's new energy, not 19x. (3) The one row that could change the sign is the knee: at the 1,300 MHz lock the 5090's fixed share is smaller and its fabric runs at a lower voltage, so the sector's 8.6 nJ would fall with the measured 10.9 to 8.7 nJ per read (15.1a) and the card's rise would be a larger fraction of a smaller base; the lever lives only if the card's energy per hash rises under about 20 percent there, and a rented pod cannot read it (`nvidia-smi -lgc` refused: "does not have permission to change clocks"). That row is one PC 1 run (the `w4` and `w64-l2` packs at `--block-warps 1`, 60 batches, at the lock) and is owed to the hash lane as a formality, not a gate. +**What the rows say, on the identity.** (1) The rate question: the exported form's -47 to -60 percent is a request-shape and occupancy effect, as the 5090's probe said; one PTX qualifier on the first load makes the 64-byte item one L2 request and holds the 4-byte rate on Ada at full occupancy (98 percent), while on Hopper the hint changes nothing (the H100's loss is elsewhere: its HBM3 pseudo-channel moves a 64-byte access as two bursts and its best shape is 79 percent) and on Ampere the best shape is 87 percent. (2) The energy question, which decides it: the card pays the second sector at the cost of a whole dependent read, not at the DRAM's movement term. On the 4090 the hinted form draws 71 W more at the same 64.7 MH/s: 71 W over 8.3 G reads per second is **8.6 nJ per second sector**; on the 5090 at sp170-w4, 88 W more at 145.7 MH/s: **4.7 nJ**; against the 1.15 nJ the DRAM device charges for it (the 4090's GDDR6X at 6 pJ per bit would be 1.5), so the other 7 nJ is the card's own L2, crossbar, L1 and the SMs' longer wait, the same anatomy as the record's 8.7 nJ whole-card marginal per dependent read (15.1a). In the identity's terms `F` is 128 x 8.6 nJ = 1.1 microjoules per hash on the 4090 (0.6 on the 5090) and the chip's cost for the same work is 128 x 1.15 = 0.15: **`k` about 0.13 on the 4090, 0.24 on the 5090**, under the ALU shadow's 0.3 to 0.8 and no better than the L2 hot table's. The energy per hash rises 34 percent on the 4090 and 33 percent on the H100's best form against the modelled chip's 33 (GDDR7) and 50 (HBM3): the edge at zero shadow moves 0 on Ada against the GDDR7 chip and 0.9x in the chip's favour against HBM3 on Hopper; against the SRAM die the chip's 66x to 19x becomes about 25x against the card's new energy, not 19x. (3) The knee, which could have changed the sign, did not (the hash lane's PC 1 row, section 6: the hinted form at the 1,300 lock reads 37.6 MH/s against 100.6 at 2.3x the energy per hash; the hint recovers nothing in the latency-bound regime on Blackwell). The reasoning that made it the one open row, for the record: at the 1,300 MHz lock the 5090's fixed share is smaller and its fabric runs at a lower voltage, so the sector's 8.6 nJ would fall with the measured 10.9 to 8.7 nJ per read (15.1a) and the card's rise would be a larger fraction of a smaller base; the lever lives only if the card's energy per hash rises under about 20 percent there, and a rented pod cannot read it (`nvidia-smi -lgc` refused: "does not have permission to change clocks"). That row ran on PC 1 at 15:0x UK and is in section 6. **Verdict: KILL at stock on measured rows; W = 16 words stays out of class v6; the design's "never 16" stands, for the measured reason (the card's fabric price of a sector) rather than the plan's (the pins).** What is kept: the hinted one-request load as a kernel fact for Ada (a 64-byte dependent read at the 4-byte rate), which a future width decision can use; the measured 8.6 nJ per sector as the card-side figure the chip model's width rows lacked; and the per-architecture rate table above. @@ -256,7 +268,7 @@ Both sides are capex-dominated (the record's 16.1: 7x to 10x their electricity p | Home miner, one 8 GB NVIDIA card (32-byte sectors) | nothing ships; had W = 16 shipped, this tier would have paid about a third more energy per hash for no rate (Ada) and an eighth of its rate too (Ampere) | nothing; the knee row on PC 1 is a formality | | One 12 GB card (4070, 5070) | the same | the same | | One 16 GB card (RX 9070 XT) | nothing (its 64-byte line is free at W = 16, measured 5 October); its row against the chip is unchanged at 22.7x on class v3 | the vendor-share metric | -| One 24 or 32 GB card (5090 class) | nothing ships; had W = 16 shipped, the 5090 would have held its rate at a sparse shape and paid +88 W (+25 percent per hash) at stock; the record's 3.6x at the knee and 2.1x at `k = 1` stand | the knee row on PC 1 (the hash lane, one row, a formality) | +| One 24 or 32 GB card (5090 class) | nothing ships; had W = 16 shipped, the 5090 would have held its rate at a sparse shape and paid +88 W (+25 percent per hash) at stock, and at its knee lost 63 percent of its rate at 2.3x the energy (measured, PC 1); the record's 3.6x at the knee and 2.1x at `k = 1` stand | nothing | | Apple (M5 Max and the unified tiers) | nothing (free at 64 bytes, measured 5 October); the honest best per joule is unchanged | nothing | | A rig | nothing ships; the two model corrections raise the chip's project floor (USD 20 M to 75 M), which is the rig's real wall, by 4x to 15x over the record's cheapest row | the chip model's rows corrected (the Counter lane) | | A pool user | nothing changes | | @@ -266,12 +278,13 @@ Both sides are capex-dominated (the record's 16.1: 7x to 10x their electricity p ## 6. Unverified and owed -- The knee row (the 5090 at the 1,300 MHz lock, `w4` against `w64-l2`, 60 batches, watts): a rented pod refuses the lock; one PC 1 row with the hash lane; the lever lives only under a 20 percent energy rise there, which the stock rows make unlikely. +- The knee row: DONE by the hash lane on PC 1's 5090 (kit d, 14:51 to 15:0x UK, the v5 kit's CUDA worker, `--block-warps 1`, 250 batches of 2^24, nvidia-smi 1 Hz, fingerprint 836e56e7d496e980 PASS on every `w64` row). Unlocked: `w4` 119.95 MH/s at 308.2 W (2.57 microjoules); `w64` 63.35 at 332.9 W; `w64-l2` 92.35 at 369.1 W (4.00 microjoules): the hint recovers 46 percent of the plain form's loss at full occupancy and stays 23 percent under the 4-byte rate at 1.56x its energy per hash. At the 1,300 MHz lock: `w4` 100.55 at 190.5 W (1.89 microjoules); `w64` 37.35 at 177.8 W; `w64-l2` 37.59 at 164.1 W (4.37 microjoules): **at the knee the hint gives nothing and the card's energy per hash is 2.3x the 4-byte row's**, far over the 20 percent line. The lever is dead at the knee as at stock; the sparse shape (sp170-w4) was not in the kit's worker and was not asked for again, because at the lock the card's fixed share is smaller and the sector's share larger, so no shape can bring a 2.3x rise under 1.2x. This closes every row this lane owed on W = 16. - The 4090's and H100's raw logs were not copied before their pods were destroyed; the rows in 3.1 are the figures read off the pods during the session. The 5090's and the 3090's raw logs are at `~/igneum-fleet/fl5-results/5090-*` and `3090-*` (result.log, result2.log, result3.log, power*.csv). - The watts are `nvidia-smi` board power at 1 Hz, the upper half of each row's samples averaged; idle on the rented pods read 29 W (4090) and 70 W (H100); the 3090's idle row was taken straight after a run and is not a settled idle. - The chip side of 3.1 is the model's own data-movement term applied twice (4.5 pJ per bit, Micron, claimed, streaming; O'Connor's 3.48 for HBM2) and lane 3's wire figure for the SRAM die; no one has measured a second-sector column read's energy on GDDR7 (section 2.6: the public record has no random-read joule on any current part). - The tensor chip figures are vendor specifications at TDP (claimed), the M4 ANE and the H800 loop measured; the RT figures are claims and one measured RTX 2080 row; the PHY node facts are vendor IP pages read today. - The project-cost corrections use the history's figures (a 7 nm-class startup project USD 50 M to 75 M, claimed; the 12 nm figure scaled, approximate) and the mission lane's cap model. +- The `w64` class's census under the sub-version 3 rule and its F8 row, which this lane owed before any cut, are DONE by the census lane (`docs/analysis/class-v6/census-w16-mix.md` on `class-v6-census` at d20eb04bd, 14:0x UK): 256 of 256 seeds accepted with and without an era (0.704 rejection per candidate against the control's 0.668; 0 exhaustions; 0 window-bit refusals for the instrument's reason; 189 stride-bit refusals of 1,524 candidates against the control's 218; (c''') 1.4 percent); the F8-form top-0.1-percent share 0.999 to 1.006 of the uniform control at 2^20 on 16 seeds; the verifier +0.6 percent inside a 4 percent drift on a loaded core (this file's +4 percent neither confirmed nor refuted; a quiet-box row owed). One structural row for 3.1: at 16 words the product's low bits are alignment, so the whole-item read removes the product's own bias from the address (the control carries it at bit 0 in 116 of 256 programs); the stride bit R stays until the index fold. The class is sound; it is dead on energy, not on soundness. - Nothing ran on the Mac, on a Hetzner box or on a PC for this file; the measurements ran on four RunPod one-shot pods, all destroyed on their done (the 5090 pod when its rows are in). ## 7. Sources diff --git a/docs/analysis/class-v6/floor/sm-sparse.md b/docs/analysis/class-v6/floor/sm-sparse.md new file mode 100644 index 000000000..41099203b --- /dev/null +++ b/docs/analysis/class-v6/floor/sm-sparse.md @@ -0,0 +1,717 @@ +# Class v6 floor lane 1: SM-sparse, the honest card's watts toward the DRAM's own (8 October 2026) + +Branch `class-v6-floor-sm` off `counter-asic-4` (d8ba861e). The term this lane owns is `E_card` above `E_mem` in the +identity of `docs/analysis/counter-asic-4-research.md` section 2: at zero shadow the stored-dataset chip's edge is +`E_card / E_mem`, and the only honest-side lever is to take the card's watts toward the DRAM's own at the activate +ceiling. Section 20.3b of that file read five shapes on PC 1's RTX 5090 (one block of 32 warps per SM at 170, 85, 43, +21 and 11 SMs) and closed the candidate: the draw follows the work, not the SM count. This file starts from that row, +answers the question it left open (what the residual watts between idle-plus-memory and the card's draw ARE, and +whether any occupancy shape at full SM count moves them) on four rented RTX 5090s, an RTX 4090 and an H100 plus PC 1 at +the 1,300 MHz lock, measures the memory-clock knob where a host allows it, and ships the measurement as a worker option +with a self-tune. + +Every number here is **measured** unless marked otherwise: the worker's `--bench` (250 dispatches of 2^24 nonces, the +pack's vector warps through the served kernel first, the 2^24 fingerprint on every row and equal across every shape of +a pack) with `nvidia-smi` at 1 Hz beside it (the mean from 8 s in; `power.draw`, `power.draw.instant` and +`power.draw.average` within 2 W on every row). The shapes: `base` is the shipped grid (one warp per block); `w4` and +`w8` the shipped grid at 4 and 8 warps per block; `sp-w` the persistent wrapper of N blocks of W warps (the +Counter ASIC 4.0 variant, bit-exact), and a `%smid` probe on every rented card confirmed that N blocks of 1,024 threads +land on N distinct SMs, one block each, for every N used. The chip rows are the model's (`chip-model-v3.md` 5.3 to 5.6 +and 5.12; lane B's SRAM die): GDDR7 board 0.466 microjoules per hash, one HBM3 stack 0.321, the N2 SRAM die 0.14; the +M5 Max's 0.78 is measured (6 October). "Edge" is the card's microjoules over the chip's. Times are UTC in the logs and UK +(BST, UTC+1) in the text. Idle is the card alone after 12 s with nothing running. + +## 0. The answer + +1. **The SM count is not the lever.** On every card the draw over idle is flat across the SM count and the warps per + SM for as long as the rate holds, and falls only when the rate falls. RTX 5090 (four rented hosts, class v3 at + stock): 43 of 170 SMs holds 99.4 percent of the ceiling, 36 SMs 99.1, 28 SMs 98.4, 21 SMs 96.6, 16 SMs 91, 11 SMs + 71; the best energy per hash on any host is 1.3 to 3.9 percent under its base (host c 2.053 against 2.079 + microjoules at 43 SMs; host e 2.389 against 2.485). RTX 4090: 16 of 128 SMs holds 99.0 percent at 4 W under base; + the best shape 1.2 percent under. H100: per-SM throughput-bound (the rate falls one for one with the SM count, + 1.93 MH/s per SM), so its sparse floor is 127 of 132 SMs at 1.4 percent under base. +2. **Fewer warps per SM at full SM count reads the same as fewer SMs.** 170 SMs at 8 warps (1,360 warps) and 43 SMs + at 32 warps (1,376 warps) give 2.063 and 2.053 microjoules on the same host: the warps in flight set the rate, + nothing in the occupancy sets the watts. One warp per SM (5,440 lanes) still holds 84 percent of the 5090's rate. +3. **Class v4's knee is 43 SMs by rate at stock and the full grid at the 1,300 MHz lock, and nothing is saved at + either.** Under 43 SMs the shadow is compute-bound at stock (PC 1: 36 SMs 88 percent, 28 SMs 69, 21 SMs 52, 16 SMs + 39 of the rate); at 43 SMs the watts equal or exceed the base's. At the lock (PC 1, this file's job) the shadow + needs every SM: 134.2 MH/s at 302 W on the full grid, 125 at 85 SMs, 64 at 43 SMs (3.24 against 2.25 microjoules). + On the H100 the persistent shape itself loses 4 percent of the class v4 rate and the self-tune installs nothing. + PC 1's class v3 at stock agrees with the rented ladder at every rung (43 SMs 136.5 of 136.7 MH/s at 10 W under + base; 170 SMs x 8 warps 137.1 at 310.8 W, 3.5 percent under base, the best shape on that board). +4. **The residual is the core clock domain and the memory path on the GPU side, and the memory clock is the one + knob left after the core lock.** The decomposition probes (section 3) put the 5090's draw over idle at the hash + into: the resident SMs issuing nothing (the SM clock domain awake), the L2 and crossbar path per read, and the DRAM + path per read on top of the memory's own modelled 2.0 nJ; the memory-clock ladder on PC 1 at the 1,300 lock reads + the PHY's share directly. The honest floor per tier is the base row at stock within 2 percent, the core lock + (rank 1 of the research file) and the memory-clock lock behind it, and the fraction a chip cannot strip is the + memory side's own (section 4). +5. **What ships.** `--sm-sparse auto` on the worker (section 5): one NVRTC compile of the persistent shape, a ladder + from the SM count down, a bisection, the fewest blocks holding 99 percent of the ceiling installed, bit-exact or + nothing; the tuning file's `sm_sparse` and `sm_hold` per card. Measured: 15 s on the H100 (chose 127 of 132 SMs, + 1.4 percent of watts), 24 s on the 4090 (chose 26 of 128, 1.3 percent), nothing installed on class v4 where the + shape loses rate. The design default is off; the tiers map to it (Efficiency on at 0.985, Balanced on at 0.995, + Maximum off) and Ember re-runs it on every pack flip because the tune is part of the pair's build. + +## 1. The rows + +Each rented card's table: one row per shape per pack, the sampler's watts, microjoules per hash and the edge against +the four chip rows. The 5090 hosts differ by board (power limit, idle, cooling), so the ladder is read as a percent of +each host's own base and the energy as a difference within the host; the across-host spread of the base row itself +(2.08 to 2.49 microjoules at 142 MH/s on class v3) is the rented-against-rented band the denominator lane also reads. +Class v4 on hosts c, d and f is power-capped (the board's limit at 450 or 475 W, the clock throttling to 2,770 to +2,810 MHz), so those class v4 rows are a cap reading, not a free-running one; PC 1 (452.8 W, no cap) and host e (533.6 +W) are the free-running class v4 rows. + +### RTX 5090, rented host c (Vast, Alberta; driver 610.57; the board's power limit 450 W of a 600 W default; idle 7 W) + +knob pl=refused +knob lgc=refused +knob lmc=refused +card NVIDIAGeForceRTX5090 driver 610.57.04 power limit 450.00 W idle 7.1 W at 218.8 MHz SM, 478.6 MHz memory + +**mx8-genesis** (mx8) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 142.60 | 296.4 | 289.3 | 2.079 | 4.46x / 6.48x / 14.85x / 2.67x | 2880 | 52 | PASS | +| sp170-w32 | 170 x 32 | 142.14 (99.7%) | 296.9 | 289.8 | 2.089 | 4.48x / 6.51x / 14.92x / 2.68x | 2865 | 54 | PASS | +| sp170-w16 | 170 x 16 | 142.55 (100.0%) | 296.0 | 288.9 | 2.076 | 4.45x / 6.47x / 14.83x / 2.66x | 2865 | 57 | PASS | +| sp170-w8 | 170 x 8 | 142.41 (99.9%) | 293.8 | 286.7 | 2.063 | 4.43x / 6.43x / 14.74x / 2.64x | 2865 | 59 | PASS | +| sp170-w4 | 170 x 4 | 141.88 (99.5%) | 293.5 | 286.4 | 2.069 | 4.44x / 6.45x / 14.78x / 2.65x | 2865 | 59 | PASS | +| sp170-w2 | 170 x 2 | 139.31 (97.7%) | 288.7 | 281.6 | 2.072 | 4.45x / 6.45x / 14.80x / 2.66x | 2865 | 59 | PASS | +| sp170-w1 | 170 x 1 | 119.59 (83.9%) | 270.3 | 263.2 | 2.260 | 4.85x / 7.04x / 16.14x / 2.90x | 2865 | 59 | PASS | +| sp128-w32 | 128 x 32 | 142.60 (100.0%) | 303.4 | 296.3 | 2.128 | 4.57x / 6.63x / 15.20x / 2.73x | 2865 | 59 | PASS | +| sp96-w32 | 96 x 32 | 138.96 (97.4%) | 294.5 | 287.4 | 2.119 | 4.55x / 6.60x / 15.14x / 2.72x | 2865 | 59 | PASS | +| sp85-w32 | 85 x 32 | 142.42 (99.9%) | 296.0 | 288.9 | 2.078 | 4.46x / 6.47x / 14.84x / 2.66x | 2865 | 59 | PASS | +| sp64-w32 | 64 x 32 | 142.24 (99.7%) | 295.2 | 288.1 | 2.075 | 4.45x / 6.46x / 14.82x / 2.66x | 2865 | 59 | PASS | +| sp52-w32 | 52 x 32 | 136.01 (95.4%) | 288.8 | 281.7 | 2.123 | 4.56x / 6.61x / 15.16x / 2.72x | 2865 | 59 | PASS | +| sp43-w32 | 43 x 32 | 141.77 (99.4%) | 291.1 | 284.0 | 2.053 | 4.41x / 6.40x / 14.66x / 2.63x | 2865 | 59 | PASS | +| sp36-w32 | 36 x 32 | 141.38 (99.1%) | 290.2 | 283.1 | 2.053 | 4.41x / 6.40x / 14.66x / 2.63x | 2865 | 59 | PASS | +| sp28-w32 | 28 x 32 | 140.27 (98.4%) | 288.6 | 281.5 | 2.058 | 4.42x / 6.41x / 14.70x / 2.64x | 2865 | 59 | PASS | +| sp21-w32 | 21 x 32 | 137.81 (96.6%) | 288.1 | 281.0 | 2.091 | 4.49x / 6.51x / 14.94x / 2.68x | 2865 | 59 | PASS | +| sp16-w32 | 16 x 32 | 129.98 (91.2%) | 280.4 | 273.3 | 2.157 | 4.63x / 6.72x / 15.41x / 2.77x | 2865 | 58 | PASS | +| sp11-w32 | 11 x 32 | 100.88 (70.7%) | 255.5 | 248.4 | 2.533 | 5.44x / 7.89x / 18.09x / 3.25x | 2865 | 57 | PASS | +| sp43-w8 | 43 x 8 | 139.54 (97.9%) | 286.9 | 279.8 | 2.056 | 4.41x / 6.40x / 14.69x / 2.64x | 2865 | 58 | PASS | +| sp340-w16 | 340 x 16 | 142.57 (100.0%) | 303.7 | 296.6 | 2.130 | 4.57x / 6.64x / 15.21x / 2.73x | 2865 | 59 | PASS | + +**mx8_sh256x27** (mx8+sh256x27) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 142.55 | 450.0 | 442.9 | 3.157 | 6.77x / 9.83x / 22.55x / 4.05x | 2797 | 66 | PASS | +| sp170-w32 | 170 x 32 | 142.12 (99.7%) | 450.0 | 442.9 | 3.166 | 6.79x / 9.86x / 22.61x / 4.06x | 2810 | 64 | PASS | +| sp170-w16 | 170 x 16 | 142.36 (99.9%) | 450.0 | 442.9 | 3.161 | 6.78x / 9.85x / 22.58x / 4.05x | 2811 | 64 | PASS | +| sp170-w8 | 170 x 8 | 141.93 (99.6%) | 450.0 | 442.9 | 3.171 | 6.80x / 9.88x / 22.65x / 4.07x | 2796 | 64 | PASS | +| sp170-w4 | 170 x 4 | 139.72 (98.0%) | 450.0 | 442.9 | 3.221 | 6.91x / 10.03x / 23.01x / 4.13x | 2802 | 64 | PASS | +| sp170-w2 | 170 x 2 | 99.50 (69.8%) | 389.4 | 382.3 | 3.913 | 8.40x / 12.19x / 27.95x / 5.02x | 2865 | 62 | PASS | +| sp170-w1 | 170 x 1 | 55.28 (38.8%) | 287.7 | 280.6 | 5.204 | 11.17x / 16.21x / 37.17x / 6.67x | 2865 | 57 | PASS | +| sp128-w32 | 128 x 32 | 142.41 (99.9%) | 450.0 | 442.9 | 3.160 | 6.78x / 9.84x / 22.57x / 4.05x | 2823 | 62 | PASS | +| sp96-w32 | 96 x 32 | 139.18 (97.6%) | 450.0 | 442.9 | 3.233 | 6.94x / 10.07x / 23.09x / 4.14x | 2846 | 64 | PASS | +| sp85-w32 | 85 x 32 | 141.46 (99.2%) | 450.0 | 442.9 | 3.181 | 6.83x / 9.91x / 22.72x / 4.08x | 2833 | 64 | PASS | +| sp64-w32 | 64 x 32 | 136.58 (95.8%) | 450.4 | 443.3 | 3.298 | 7.08x / 10.27x / 23.56x / 4.23x | 2850 | 63 | PASS | +| sp52-w32 | 52 x 32 | 121.00 (84.9%) | 417.9 | 410.8 | 3.454 | 7.41x / 10.76x / 24.67x / 4.43x | 2873 | 62 | PASS | +| sp43-w32 | 43 x 32 | 124.16 (87.1%) | 422.7 | 415.6 | 3.404 | 7.30x / 10.60x / 24.31x / 4.36x | 2872 | 62 | PASS | +| sp36-w32 | 36 x 32 | 104.35 (73.2%) | 380.5 | 373.4 | 3.646 | 7.82x / 11.36x / 26.04x / 4.67x | 2877 | 61 | PASS | +| sp28-w32 | 28 x 32 | 81.35 (57.1%) | 334.2 | 327.1 | 4.108 | 8.82x / 12.80x / 29.34x / 5.27x | 2880 | 59 | PASS | +| sp21-w32 | 21 x 32 | 61.05 (42.8%) | 288.2 | 281.1 | 4.721 | 10.13x / 14.71x / 33.72x / 6.05x | 2878 | 57 | PASS | +| sp16-w32 | 16 x 32 | 46.51 (32.6%) | 252.1 | 245.0 | 5.420 | 11.63x / 16.88x / 38.71x / 6.95x | 2872 | 55 | PASS | +| sp11-w32 | 11 x 32 | 32.04 (22.5%) | 216.3 | 209.2 | 6.752 | 14.49x / 21.03x / 48.23x / 8.66x | 2880 | 54 | PASS | +| sp43-w8 | 43 x 8 | 87.18 (61.2%) | 345.2 | 338.1 | 3.960 | 8.50x / 12.34x / 28.29x / 5.08x | 2872 | 59 | PASS | +| sp340-w16 | 340 x 16 | 142.18 (99.7%) | 450.0 | 442.9 | 3.165 | 6.79x / 9.86x / 22.61x / 4.06x | 2800 | 65 | PASS | + + +The follow-up on host c (the memory-clock try, the first self-tune rows, the microbench) overlapped its own queue on the card (the launcher's wait keyed on a pid file written after it read it), so those rows are discarded; the self-tune was re-run alone on the idle card (idle 5.2 W, 1 MiB used) and these are its rows: + + +| Hold | Pack | Served shape | MH/s | Watts | Microjoules | Tune line | +|---|---|---|---|---|---|---| +| 0.99 | mx8-genesis | sp37-w32 | 141.272 | 286.5 | 2.028 | tune device NVIDIA_GeForce_RTX_5090 sms 170 installed base 142.575 ceiling 142.575 hold 0.990 rows 170=142.008 127=142.276 85=142.224 63=141.866 42=141.549 31=140.347 36=141.083 39=141.295 37=141.240 chosen sp37-w32 141.240 (99.1% of the ceiling, 37 of 170 SMs) 21816 ms | +| 0.99 | mx8_sh256x27 | sp82-w32 | 141.045 | 448.3 | 3.178 | tune device NVIDIA_GeForce_RTX_5090 sms 170 installed base 142.288 ceiling 142.288 hold 0.990 rows 170=141.986 127=141.787 85=141.302 63=135.712 74=140.204 79=140.561 82=141.046 80=140.855 chosen sp82-w32 141.046 (99.1% of the ceiling, 82 of 170 SMs) 19820 ms | +| 0.98 | mx8-genesis | sp27-w32 | 139.717 | 284.1 | 2.033 | tune device NVIDIA_GeForce_RTX_5090 sms 170 installed base 142.277 ceiling 142.277 hold 0.980 rows 170=141.940 127=142.336 85=142.125 63=142.024 42=141.710 31=140.447 21=137.555 26=139.300 28=139.939 27=139.557 chosen sp27-w32 139.557 (98.1% of the ceiling, 27 of 170 SMs) 24133 ms | +| 0.98 | mx8_sh256x27 | sp71-w32 | 140.082 | 446.1 | 3.185 | tune device NVIDIA_GeForce_RTX_5090 sms 170 installed base 142.534 ceiling 142.534 hold 0.980 rows 170=142.005 127=141.994 85=141.509 63=136.138 74=140.573 68=139.343 71=140.150 69=139.615 chosen sp71-w32 140.150 (98.3% of the ceiling, 71 of 170 SMs) 19850 ms | + + +### RTX 5090, rented host d (Vast, Quebec; driver 595.91; power limit 475 W) + +knob pl=refused +knob lgc=refused +knob lmc=refused +card NVIDIAGeForceRTX5090 driver 595.91.07 power limit 475.00 W idle 27.4 W at 195.0 MHz SM, 405.0 MHz memory + +**mx8-genesis** (mx8) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 142.44 | 326.3 | 298.9 | 2.291 | 4.92x / 7.14x / 16.36x / 2.94x | 2887 | 50 | PASS | +| sp170-w32 | 170 x 32 | 141.88 (99.6%) | 327.5 | 300.1 | 2.308 | 4.95x / 7.19x / 16.49x / 2.96x | 2886 | 53 | PASS | +| sp128-w32 | 128 x 32 | 142.28 (99.9%) | 327.7 | 300.3 | 2.303 | 4.94x / 7.17x / 16.45x / 2.95x | 2872 | 55 | PASS | +| sp96-w32 | 96 x 32 | 138.83 (97.5%) | 323.4 | 296.0 | 2.330 | 5.00x / 7.26x / 16.64x / 2.99x | 2872 | 56 | PASS | +| sp85-w32 | 85 x 32 | 142.23 (99.9%) | 328.1 | 300.7 | 2.307 | 4.95x / 7.19x / 16.48x / 2.96x | 2872 | 57 | PASS | +| sp64-w32 | 64 x 32 | 142.03 (99.7%) | 329.0 | 301.6 | 2.316 | 4.97x / 7.21x / 16.54x / 2.97x | 2872 | 58 | PASS | + +**mx8_sh256x27** (mx8+sh256x27) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 142.36 | 475.0 | 447.6 | 3.337 | 7.16x / 10.40x / 23.84x / 4.28x | 2777 | 66 | PASS | +| sp170-w32 | 170 x 32 | 141.98 (99.7%) | 475.0 | 447.6 | 3.345 | 7.18x / 10.42x / 23.89x / 4.29x | 2767 | 68 | PASS | +| sp128-w32 | 128 x 32 | 142.22 (99.9%) | 475.0 | 447.6 | 3.340 | 7.17x / 10.40x / 23.86x / 4.28x | 2764 | 69 | PASS | +| sp96-w32 | 96 x 32 | 139.08 (97.7%) | 475.0 | 447.6 | 3.415 | 7.33x / 10.64x / 24.39x / 4.38x | 2787 | 69 | PASS | +| sp85-w32 | 85 x 32 | 141.27 (99.2%) | 475.0 | 447.6 | 3.362 | 7.21x / 10.47x / 24.01x / 4.31x | 2772 | 70 | PASS | +| sp64-w32 | 64 x 32 | 135.94 (95.5%) | 475.0 | 447.6 | 3.494 | 7.50x / 10.88x / 24.96x / 4.48x | 2803 | 70 | PASS | + + + +### RTX 5090, rented host e (Vast, United Kingdom; driver 595.91) + +knob pl=refused +knob lgc=refused +knob lmc=refused +card NVIDIAGeForceRTX5090 driver 595.91.07 power limit 575.00 W idle 11.7 W at 185.2 MHz SM, 445.5 MHz memory + +**mx8-genesis** (mx8) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 141.96 | 352.7 | 341.0 | 2.485 | 5.33x / 7.74x / 17.75x / 3.19x | 2917 | 56 | PASS | +| sp52-w32 | 52 x 32 | 135.85 (95.7%) | 332.0 | 320.3 | 2.444 | 5.24x / 7.61x / 17.46x / 3.13x | 2922 | 56 | PASS | +| sp43-w32 | 43 x 32 | 141.21 (99.5%) | 337.4 | 325.7 | 2.389 | 5.13x / 7.44x / 17.06x / 3.06x | 2917 | 57 | PASS | +| sp36-w32 | 36 x 32 | 140.88 (99.2%) | 336.9 | 325.2 | 2.391 | 5.13x / 7.45x / 17.08x / 3.07x | 2917 | 58 | PASS | +| sp28-w32 | 28 x 32 | 139.58 (98.3%) | 335.6 | 323.9 | 2.404 | 5.16x / 7.49x / 17.17x / 3.08x | 2917 | 58 | PASS | +| sp21-w32 | 21 x 32 | 137.23 (96.7%) | 334.9 | 323.2 | 2.440 | 5.24x / 7.60x / 17.43x / 3.13x | 2917 | 58 | PASS | + +**mx8_sh256x27** (mx8+sh256x27) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 141.90 | 533.6 | 521.9 | 3.760 | 8.07x / 11.71x / 26.86x / 4.82x | 2902 | 68 | PASS | +| sp52-w32 | 52 x 32 | 122.17 (86.1%) | 484.4 | 472.7 | 3.965 | 8.51x / 12.35x / 28.32x / 5.08x | 2903 | 68 | PASS | +| sp43-w32 | 43 x 32 | 125.11 (88.2%) | 491.8 | 480.1 | 3.931 | 8.44x / 12.25x / 28.08x / 5.04x | 2902 | 69 | PASS | +| sp36-w32 | 36 x 32 | 105.18 (74.1%) | 444.6 | 432.9 | 4.227 | 9.07x / 13.17x / 30.19x / 5.42x | 2902 | 68 | PASS | +| sp28-w32 | 28 x 32 | 81.73 (57.6%) | 389.2 | 377.5 | 4.762 | 10.22x / 14.83x / 34.01x / 6.11x | 2896 | 66 | PASS | +| sp21-w32 | 21 x 32 | 61.61 (43.4%) | 340.4 | 328.7 | 5.525 | 11.86x / 17.21x / 39.46x / 7.08x | 2902 | 63 | PASS | + + + +### RTX 5090, rented host f (Vast, Beijing; driver 580.173; power limit 450 W) + +knob pl=refused +knob lgc=refused +knob lmc=refused +card NVIDIAGeForceRTX5090 driver 580.173.02 power limit 450.00 W idle 29.8 W at 300.0 MHz SM, 405.0 MHz memory + +**mx8-genesis** (mx8) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 142.49 | 333.2 | 303.4 | 2.338 | 5.02x / 7.28x / 16.70x / 3.00x | 3028 | 47 | PASS | +| sp16-w32 | 16 x 32 | 130.53 (91.6%) | 309.8 | 280.0 | 2.373 | 5.09x / 7.39x / 16.95x / 3.04x | 3030 | 48 | PASS | +| sp11-w32 | 11 x 32 | 106.04 (74.4%) | 288.1 | 258.3 | 2.717 | 5.83x / 8.46x / 19.41x / 3.48x | 3030 | 48 | PASS | +| sp170-w8 | 170 x 8 | 142.32 (99.9%) | 322.8 | 293.0 | 2.268 | 4.87x / 7.07x / 16.20x / 2.91x | 3030 | 49 | PASS | +| sp170-w4 | 170 x 4 | 141.72 (99.5%) | 323.3 | 293.5 | 2.281 | 4.89x / 7.11x / 16.29x / 2.92x | 3030 | 50 | PASS | +| sp170-w2 | 170 x 2 | 139.28 (97.8%) | 320.6 | 290.8 | 2.302 | 4.94x / 7.17x / 16.44x / 2.95x | 3030 | 51 | PASS | +| sp43-w8 | 43 x 8 | 139.46 (97.9%) | 320.0 | 290.2 | 2.295 | 4.92x / 7.15x / 16.39x / 2.94x | 3030 | 52 | PASS | + +**mx8_sh256x27** (mx8+sh256x27) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 142.39 | 450.0 | 420.2 | 3.160 | 6.78x / 9.84x / 22.57x / 4.05x | 2882 | 58 | PASS | +| sp16-w32 | 16 x 32 | 48.94 (34.4%) | 298.0 | 268.2 | 6.090 | 13.07x / 18.97x / 43.50x / 7.81x | 3022 | 54 | PASS | +| sp11-w32 | 11 x 32 | 33.79 (23.7%) | 259.2 | 229.4 | 7.671 | 16.46x / 23.90x / 54.79x / 9.83x | 3037 | 52 | PASS | +| sp170-w8 | 170 x 8 | 141.83 (99.6%) | 450.0 | 420.2 | 3.173 | 6.81x / 9.88x / 22.66x / 4.07x | 2853 | 59 | PASS | +| sp170-w4 | 170 x 4 | 139.72 (98.1%) | 450.0 | 420.2 | 3.221 | 6.91x / 10.03x / 23.01x / 4.13x | 2854 | 60 | PASS | +| sp170-w2 | 170 x 2 | 102.45 (72.0%) | 443.5 | 413.7 | 4.329 | 9.29x / 13.49x / 30.92x / 5.55x | 3012 | 62 | PASS | +| sp43-w8 | 43 x 8 | 90.20 (63.3%) | 398.7 | 368.9 | 4.420 | 9.48x / 13.77x / 31.57x / 5.67x | 3022 | 60 | PASS | + + + +### RTX 4090, rented (RunPod, 128 SMs, GDDR6X; driver 595.91; power limit 450 W) + +knob pl=refused +knob lgc=refused +knob lmc=refused +card NVIDIAGeForceRTX4090 driver 595.91.07 power limit 450.00 W idle 34.7 W at 210.0 MHz SM, 405.0 MHz memory + +**mx8-genesis** (mx8) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 70.63 | 253.4 | 218.7 | 3.588 | 7.70x / 11.18x / 25.63x / 4.60x | 2732 | 39 | PASS | +| w4 | 0 x 4 | 70.62 (100.0%) | 254.9 | 220.2 | 3.609 | 7.74x / 11.24x / 25.78x / 4.63x | 2730 | 44 | PASS | +| w8 | 0 x 8 | 70.64 (100.0%) | 255.6 | 220.9 | 3.618 | 7.76x / 11.27x / 25.84x / 4.64x | 2721 | 47 | PASS | +| sp128-w32 | 128 x 32 | 70.64 (100.0%) | 255.6 | 220.9 | 3.618 | 7.76x / 11.27x / 25.84x / 4.64x | 2715 | 48 | PASS | +| sp256-w16 | 256 x 16 | 70.57 (99.9%) | 256.1 | 221.4 | 3.629 | 7.79x / 11.31x / 25.92x / 4.65x | 2715 | 48 | PASS | +| sp512-w8 | 512 x 8 | 70.60 (100.0%) | 256.0 | 221.3 | 3.626 | 7.78x / 11.30x / 25.90x / 4.65x | 2715 | 49 | PASS | +| sp128-w16 | 128 x 16 | 70.64 (100.0%) | 254.2 | 219.5 | 3.599 | 7.72x / 11.21x / 25.71x / 4.61x | 2715 | 49 | PASS | +| sp128-w8 | 128 x 8 | 70.58 (99.9%) | 252.0 | 217.3 | 3.570 | 7.66x / 11.12x / 25.50x / 4.58x | 2715 | 49 | PASS | +| sp128-w4 | 128 x 4 | 70.45 (99.7%) | 251.3 | 216.6 | 3.567 | 7.65x / 11.11x / 25.48x / 4.57x | 2715 | 48 | PASS | +| sp128-w2 | 128 x 2 | 70.17 (99.4%) | 250.6 | 215.9 | 3.571 | 7.66x / 11.12x / 25.51x / 4.58x | 2715 | 48 | PASS | +| sp128-w1 | 128 x 1 | 66.28 (93.8%) | 242.7 | 208.0 | 3.662 | 7.86x / 11.41x / 26.16x / 4.69x | 2715 | 47 | PASS | +| sp96-w32 | 96 x 32 | 70.61 (100.0%) | 253.7 | 219.0 | 3.593 | 7.71x / 11.19x / 25.66x / 4.61x | 2715 | 48 | PASS | +| sp64-w32 | 64 x 32 | 70.59 (100.0%) | 253.1 | 218.4 | 3.585 | 7.69x / 11.17x / 25.61x / 4.60x | 2715 | 48 | PASS | +| sp48-w32 | 48 x 32 | 70.50 (99.8%) | 252.2 | 217.5 | 3.578 | 7.68x / 11.15x / 25.56x / 4.59x | 2715 | 48 | PASS | +| sp32-w32 | 32 x 32 | 70.42 (99.7%) | 251.4 | 216.7 | 3.570 | 7.66x / 11.12x / 25.50x / 4.58x | 2715 | 48 | PASS | +| sp24-w32 | 24 x 32 | 67.15 (95.1%) | 247.1 | 212.4 | 3.680 | 7.90x / 11.46x / 26.29x / 4.72x | 2715 | 48 | PASS | +| sp16-w32 | 16 x 32 | 69.95 (99.0%) | 249.6 | 214.9 | 3.568 | 7.66x / 11.12x / 25.49x / 4.57x | 2715 | 47 | PASS | +| sp12-w32 | 12 x 32 | 68.69 (97.3%) | 246.5 | 211.8 | 3.589 | 7.70x / 11.18x / 25.64x / 4.60x | 2715 | 47 | PASS | +| sp8-w32 | 8 x 32 | 65.07 (92.1%) | 239.1 | 204.4 | 3.675 | 7.89x / 11.45x / 26.25x / 4.71x | 2715 | 46 | PASS | +| sp32-w8 | 32 x 8 | 70.19 (99.4%) | 248.9 | 214.2 | 3.546 | 7.61x / 11.05x / 25.33x / 4.55x | 2715 | 47 | PASS | + +**mx8_sh256x27** (mx8+sh256x27) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 70.63 | 353.5 | 318.8 | 5.005 | 10.74x / 15.59x / 35.75x / 6.42x | 2715 | 56 | PASS | +| w4 | 0 x 4 | 70.62 (100.0%) | 356.8 | 322.1 | 5.052 | 10.84x / 15.74x / 36.09x / 6.48x | 2715 | 58 | PASS | +| w8 | 0 x 8 | 70.63 (100.0%) | 357.6 | 322.9 | 5.063 | 10.86x / 15.77x / 36.16x / 6.49x | 2715 | 58 | PASS | +| sp128-w32 | 128 x 32 | 70.60 (100.0%) | 356.1 | 321.4 | 5.044 | 10.82x / 15.71x / 36.03x / 6.47x | 2715 | 59 | PASS | +| sp256-w16 | 256 x 16 | 70.58 (99.9%) | 356.9 | 322.2 | 5.057 | 10.85x / 15.75x / 36.12x / 6.48x | 2715 | 59 | PASS | +| sp512-w8 | 512 x 8 | 70.57 (99.9%) | 358.4 | 323.7 | 5.078 | 10.90x / 15.82x / 36.27x / 6.51x | 2715 | 59 | PASS | +| sp128-w16 | 128 x 16 | 70.54 (99.9%) | 355.6 | 320.9 | 5.041 | 10.82x / 15.70x / 36.01x / 6.46x | 2715 | 59 | PASS | +| sp128-w8 | 128 x 8 | 70.53 (99.9%) | 355.0 | 320.3 | 5.034 | 10.80x / 15.68x / 35.96x / 6.45x | 2715 | 59 | PASS | +| sp128-w4 | 128 x 4 | 70.30 (99.5%) | 354.4 | 319.7 | 5.041 | 10.82x / 15.70x / 36.01x / 6.46x | 2715 | 59 | PASS | +| sp128-w2 | 128 x 2 | 63.43 (89.8%) | 332.5 | 297.8 | 5.242 | 11.25x / 16.33x / 37.44x / 6.72x | 2715 | 57 | PASS | +| sp128-w1 | 128 x 1 | 40.51 (57.4%) | 267.5 | 232.8 | 6.603 | 14.17x / 20.57x / 47.16x / 8.47x | 2715 | 54 | PASS | +| sp96-w32 | 96 x 32 | 70.57 (99.9%) | 350.9 | 316.2 | 4.972 | 10.67x / 15.49x / 35.51x / 6.37x | 2715 | 58 | PASS | +| sp64-w32 | 64 x 32 | 70.57 (99.9%) | 349.7 | 315.0 | 4.955 | 10.63x / 15.44x / 35.39x / 6.35x | 2715 | 59 | PASS | +| sp48-w32 | 48 x 32 | 69.10 (97.8%) | 345.1 | 310.4 | 4.994 | 10.72x / 15.56x / 35.67x / 6.40x | 2715 | 59 | PASS | +| sp32-w32 | 32 x 32 | 68.22 (96.6%) | 341.4 | 306.7 | 5.004 | 10.74x / 15.59x / 35.74x / 6.42x | 2715 | 58 | PASS | +| sp24-w32 | 24 x 32 | 66.93 (94.8%) | 336.6 | 301.9 | 5.029 | 10.79x / 15.67x / 35.92x / 6.45x | 2715 | 58 | PASS | +| sp16-w32 | 16 x 32 | 44.84 (63.5%) | 276.4 | 241.7 | 6.163 | 13.23x / 19.20x / 44.02x / 7.90x | 2715 | 54 | PASS | +| sp12-w32 | 12 x 32 | 33.66 (47.7%) | 242.9 | 208.2 | 7.216 | 15.48x / 22.48x / 51.54x / 9.25x | 2715 | 51 | PASS | +| sp8-w32 | 8 x 32 | 22.46 (31.8%) | 208.0 | 173.3 | 9.261 | 19.87x / 28.85x / 66.15x / 11.87x | 2715 | 48 | PASS | +| sp32-w8 | 32 x 8 | 58.36 (82.6%) | 311.3 | 276.6 | 5.334 | 11.45x / 16.62x / 38.10x / 6.84x | 2715 | 54 | PASS | + + +**follow-up, 4090** + +| Tag | Pack | Served shape | MH/s | Watts | Microjoules | SM MHz | Mem MHz | Check | Tune line | +|---|---|---|---|---|---|---|---|---|---| + +RESULT memclocks label=4090 lmc=refused + +| tune0.99 | mx8-genesis | sp26-w32 (26 x 32) | 70.15 | 250.2 | 3.567 | 2715 | 10501 | PASS | RESULT sparse tune device NVIDIA_GeForce_RTX_4090 sms 128 installed base 70.632 ceiling 70.632 hold 0.990 rows 128=70.609 96=70.616 64=70.590 48=70.524 32=70.476 24=67.148 28=70.377 26=70.143 25=69.726 chosen sp26-w32 70.143 (99.3% of the ceiling, 26 of 128 SMs) 24485 ms | +| tune0.99 | mx8_sh256x27 | sp61-w32 (61 x 32) | 70.42 | 346.9 | 4.926 | 2715 | 10501 | PASS | RESULT sparse tune device NVIDIA_GeForce_RTX_4090 sms 128 installed base 70.624 ceiling 70.627 hold 0.990 rows 128=70.627 96=70.574 64=70.573 48=69.092 56=67.021 60=69.890 62=70.459 61=70.423 chosen sp61-w32 70.423 (99.7% of the ceiling, 61 of 128 SMs) 21979 ms | +| tune0.98 | mx8-genesis | sp25-w32 (25 x 32) | 69.73 | 250.3 | 3.590 | 2715 | 10501 | PASS | RESULT sparse tune device NVIDIA_GeForce_RTX_4090 sms 128 installed base 70.636 ceiling 70.636 hold 0.980 rows 128=70.622 96=70.618 64=70.574 48=70.516 32=70.472 24=67.159 28=70.391 26=70.159 25=69.728 chosen sp25-w32 69.728 (98.7% of the ceiling, 25 of 128 SMs) 24483 ms | +| tune0.98 | mx8_sh256x27 | sp59-w32 (59 x 32) | 70.23 | 345.9 | 4.925 | 2715 | 10501 | PASS | RESULT sparse tune device NVIDIA_GeForce_RTX_4090 sms 128 installed base 70.619 ceiling 70.619 hold 0.980 rows 128=70.619 96=70.581 64=70.564 48=69.094 56=67.027 60=69.901 58=69.197 59=70.270 chosen sp59-w32 70.270 (99.5% of the ceiling, 59 of 128 SMs) 22034 ms | +| v5 | v5-genesis | ( x ) | 69.91 | 360.1 | 5.151 | 2715 | 10501 | PASS | | +| v5 | v4-genesis | ( x ) | 69.89 | 360.0 | 5.151 | 2715 | 10501 | PASS | | +| v5 | v4-genesis | base (0 x 1) | 69.91 | 360.6 | 5.158 | 2715 | 10501 | PASS | | + +RESULT after-micro label=4090 watts=134.5 RESULT microbench probe=sleep status=ok unit="none (the SM-resident floor: full occupancy, __nanosleep, no issue)" ops_per_step=0 lanes=196608 regs=11 blocks_per_sm=6 steps=2000 launches=14056 launch_ms=2.1 seconds=30.0 start_utc=2026-10-08T12:32:09Z end_utc=2026-10-08T12:32:39Z G_steps_s=184.227 G_ops_s=0.000 checksum=f4a2875f29883636 + + +RESULT after-micro label=4090 watts=447.1 RESULT microbench probe=int_arx status=ok unit="int32 add, xor or rotate (4 independent chains, 3 ops each per step)" ops_per_step=12 lanes=196608 regs=12 blocks_per_sm=6 steps=16384 launches=20066 launch_ms=1.5 seconds=30.0 start_utc=2026-10-08T12:32:39Z end_utc=2026-10-08T12:33:09Z G_steps_s=2154.515 G_ops_s=25854.179 checksum=e8e10dc19924d864 + + +RESULT after-micro label=4090 watts=268.4 RESULT microbench probe=dram_chase_1g status=ok unit="dependent random 4-byte read in a 1 GiB table (the hash's own pattern, the control)" ops_per_step=1 lanes=196608 regs=16 blocks_per_sm=6 steps=512 launches=2795 launch_ms=10.7 seconds=30.0 start_utc=2026-10-08T12:33:09Z end_utc=2026-10-08T12:33:39Z G_steps_s=9.376 G_ops_s=9.376 checksum=7e9ab598fe7052e5 + + +RESULT after-idle label=4090 watts=65.7 sm_mhz=536.7 mem_mhz=3659.4 + + + +### H100 80 GB HBM3, rented (RunPod, 132 SMs; driver 580.126; power limit 700 W) + +knob pl=refused +knob lgc=refused +knob lmc=allowed +card NVIDIAH10080GBHBM3 driver 580.126.09 power limit 700.00 W idle 71.3 W at 345.0 MHz SM, 2619.0 MHz memory + +**mx8-genesis** (mx8) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 254.63 | 450.4 | 379.1 | 1.769 | 3.80x / 5.51x / 12.64x / 2.27x | 1980 | 44 | PASS | +| w4 | 0 x 4 | 254.35 (99.9%) | 454.2 | 382.9 | 1.786 | 3.83x / 5.56x / 12.76x / 2.29x | 1980 | 46 | PASS | +| w8 | 0 x 8 | 254.52 (100.0%) | 457.2 | 385.9 | 1.796 | 3.85x / 5.60x / 12.83x / 2.30x | 1980 | 50 | PASS | +| sp132-w32 | 132 x 32 | 253.98 (99.7%) | 453.4 | 382.1 | 1.785 | 3.83x / 5.56x / 12.75x / 2.29x | 1980 | 52 | PASS | +| sp264-w16 | 264 x 16 | 254.20 (99.8%) | 457.4 | 386.1 | 1.799 | 3.86x / 5.60x / 12.85x / 2.31x | 1980 | 54 | PASS | +| sp528-w8 | 528 x 8 | 254.20 (99.8%) | 461.5 | 390.2 | 1.816 | 3.90x / 5.66x / 12.97x / 2.33x | 1980 | 55 | PASS | +| sp132-w16 | 132 x 16 | 253.94 (99.7%) | 454.1 | 382.8 | 1.788 | 3.84x / 5.57x / 12.77x / 2.29x | 1980 | 56 | PASS | +| sp132-w8 | 132 x 8 | 252.53 (99.2%) | 454.7 | 383.4 | 1.801 | 3.86x / 5.61x / 12.86x / 2.31x | 1980 | 56 | PASS | +| sp132-w4 | 132 x 4 | 237.53 (93.3%) | 430.1 | 358.8 | 1.811 | 3.89x / 5.64x / 12.94x / 2.32x | 1980 | 56 | PASS | +| sp132-w2 | 132 x 2 | 178.50 (70.1%) | | | | | | | PASS | +| sp132-w1 | 132 x 1 | 105.25 (41.3%) | 277.6 | 206.3 | 2.637 | 5.66x / 8.21x / 18.84x / 3.38x | 1980 | 49 | PASS | +| sp99-w32 | 99 x 32 | 212.70 (83.5%) | 402.8 | 331.5 | 1.894 | 4.06x / 5.90x / 13.53x / 2.43x | 1980 | 50 | PASS | +| sp66-w32 | 66 x 32 | 189.20 (74.3%) | 372.9 | 301.6 | 1.971 | 4.23x / 6.14x / 14.08x / 2.53x | 1980 | 48 | PASS | +| sp44-w32 | 44 x 32 | 150.11 (58.9%) | 323.9 | 252.6 | 2.158 | 4.63x / 6.72x / 15.41x / 2.77x | 1980 | 46 | PASS | +| sp33-w32 | 33 x 32 | 123.41 (48.5%) | 291.0 | 219.7 | 2.358 | 5.06x / 7.35x / 16.84x / 3.02x | 1980 | 44 | PASS | +| sp24-w32 | 24 x 32 | 89.90 (35.3%) | 250.2 | 178.9 | 2.783 | 5.97x / 8.67x / 19.88x / 3.57x | 1980 | 42 | PASS | +| sp17-w32 | 17 x 32 | 63.66 (25.0%) | 219.1 | 147.8 | 3.442 | 7.39x / 10.72x / 24.59x / 4.41x | 1980 | 41 | PASS | +| sp12-w32 | 12 x 32 | 55.38 (21.7%) | 210.8 | 139.5 | 3.806 | 8.17x / 11.86x / 27.19x / 4.88x | 1980 | 40 | PASS | +| sp8-w32 | 8 x 32 | 36.93 (14.5%) | 189.3 | 118.0 | 5.126 | 11.00x / 15.97x / 36.61x / 6.57x | 1980 | 40 | PASS | +| sp33-w8 | 33 x 8 | 123.50 (48.5%) | 293.2 | 221.9 | 2.374 | 5.09x / 7.40x / 16.96x / 3.04x | 1980 | 47 | PASS | + +**mx8_sh256x27** (mx8+sh256x27) + +| Shape | Blocks x warps | MH/s | Watts | Watts over idle | Microjoules per hash | Edge: GDDR7 / HBM3 / SRAM / M5 Max | SM MHz | Temp | Check | +|---|---|---|---|---|---|---|---|---|---| +| base | 0 x 1 | 251.90 | 699.4 | 628.1 | 2.776 | 5.96x / 8.65x / 19.83x / 3.56x | 1830 | 66 | PASS | +| w4 | 0 x 4 | 250.56 (99.5%) | 698.5 | 627.2 | 2.788 | 5.98x / 8.69x / 19.91x / 3.57x | 1748 | 69 | PASS | +| w8 | 0 x 8 | 249.31 (99.0%) | 697.6 | 626.3 | 2.798 | 6.00x / 8.72x / 19.99x / 3.59x | 1734 | 70 | PASS | +| sp132-w32 | 132 x 32 | 242.15 (96.1%) | 696.7 | 625.4 | 2.877 | 6.17x / 8.96x / 20.55x / 3.69x | 1744 | 72 | PASS | +| sp264-w16 | 264 x 16 | 237.66 (94.3%) | 698.5 | 627.2 | 2.939 | 6.31x / 9.16x / 20.99x / 3.77x | 1795 | 71 | PASS | +| sp528-w8 | 528 x 8 | 231.67 (92.0%) | 695.7 | 624.4 | 3.003 | 6.44x / 9.36x / 21.45x / 3.85x | 1768 | 69 | PASS | +| sp132-w16 | 132 x 16 | 226.18 (89.8%) | 699.4 | 628.1 | 3.092 | 6.64x / 9.63x / 22.09x / 3.96x | 1857 | 69 | PASS | +| sp132-w8 | 132 x 8 | 173.30 (68.8%) | 630.0 | 558.7 | 3.635 | 7.80x / 11.32x / 25.96x / 4.66x | 1980 | 66 | PASS | +| sp132-w4 | 132 x 4 | 108.07 (42.9%) | 452.5 | 381.2 | 4.187 | 8.98x / 13.04x / 29.91x / 5.37x | 1980 | 57 | PASS | +| sp132-w2 | 132 x 2 | 54.90 (21.8%) | 301.3 | 230.0 | 5.488 | 11.78x / 17.10x / 39.20x / 7.04x | 1980 | 49 | PASS | +| sp132-w1 | 132 x 1 | 29.45 (11.7%) | 226.4 | 155.1 | 7.688 | 16.50x / 23.95x / 54.91x / 9.86x | 1980 | 44 | PASS | +| sp99-w32 | 99 x 32 | 206.11 (81.8%) | 697.2 | 625.9 | 3.383 | 7.26x / 10.54x / 24.16x / 4.34x | 1967 | 63 | PASS | +| sp66-w32 | 66 x 32 | 138.62 (55.0%) | 520.4 | 449.1 | 3.754 | 8.06x / 11.69x / 26.81x / 4.81x | 1980 | 57 | PASS | +| sp44-w32 | 44 x 32 | 92.59 (36.8%) | 392.6 | 321.3 | 4.240 | 9.10x / 13.21x / 30.29x / 5.44x | 1980 | 52 | PASS | +| sp33-w32 | 33 x 32 | 69.57 (27.6%) | 330.5 | 259.2 | 4.751 | 10.20x / 14.80x / 33.94x / 6.09x | 1980 | 49 | PASS | +| sp24-w32 | 24 x 32 | 50.64 (20.1%) | 279.1 | 207.8 | 5.511 | 11.83x / 17.17x / 39.36x / 7.07x | 1980 | 46 | PASS | +| sp17-w32 | 17 x 32 | 35.89 (14.2%) | 238.0 | 166.7 | 6.631 | 14.23x / 20.66x / 47.36x / 8.50x | 1980 | 43 | PASS | +| sp12-w32 | 12 x 32 | 25.34 (10.1%) | 207.5 | 136.2 | 8.190 | 17.58x / 25.51x / 58.50x / 10.50x | 1980 | 41 | PASS | +| sp8-w32 | 8 x 32 | 16.90 (6.7%) | 182.5 | 111.2 | 10.798 | 23.17x / 33.64x / 77.13x / 13.84x | 1980 | 39 | PASS | +| sp33-w8 | 33 x 8 | 45.06 (17.9%) | 262.6 | 191.3 | 5.827 | 12.50x / 18.15x / 41.62x / 7.47x | 1980 | 43 | PASS | + + +**follow-up, h100** + +| Tag | Pack | Served shape | MH/s | Watts | Microjoules | SM MHz | Mem MHz | Check | Tune line | +|---|---|---|---|---|---|---|---|---|---| + +RESULT memclocks label=h100 supported=[2619 1593 ] + +| mem2619 | mx8-genesis | base (0 x 1) | 254.84 | 454.6 | 1.784 | 1980 | 2619 | PASS | | +| mem2619 | mx8_sh256x27 | base (0 x 1) | 253.00 | 699.4 | 2.764 | 1716 | 2619 | PASS | | +| mem1593 | mx8-genesis | base (0 x 1) | 254.57 | 458.8 | 1.802 | 1980 | 2619 | PASS | | +| mem1593 | mx8_sh256x27 | base (0 x 1) | 252.77 | 698.4 | 2.763 | 1694 | 2619 | PASS | | +| tune0.99 | mx8-genesis | sp127-w32 (127 x 32) | 253.19 | 441.6 | 1.744 | 1980 | 2619 | PASS | RESULT sparse tune device NVIDIA_H100_80GB_HBM3 sms 132 installed base 254.458 ceiling 254.458 hold 0.990 rows 132=254.076 99=212.879 115=230.328 123=244.690 127=253.179 125=248.878 chosen sp127-w32 253.179 (99.5% of the ceiling, 127 of 132 SMs) 15165 ms | +| tune0.99 | mx8_sh256x27 | base (0 x 1) | 252.67 | 692.7 | 2.742 | 1752 | 2619 | PASS | RESULT sparse tune device NVIDIA_H100_80GB_HBM3 sms 132 installed base 247.311 ceiling 247.311 hold 0.990 rows 132=242.003 99=205.751 chosen none (no sparse shape held; the installed kernel stays) 6557 ms | +| tune0.98 | mx8-genesis | sp127-w32 (127 x 32) | 253.35 | 451.1 | 1.781 | 1980 | 2619 | PASS | RESULT sparse tune device NVIDIA_H100_80GB_HBM3 sms 132 installed base 254.909 ceiling 254.909 hold 0.980 rows 132=254.394 99=212.934 115=230.633 123=244.933 127=252.939 125=249.108 chosen sp127-w32 252.939 (99.2% of the ceiling, 127 of 132 SMs) 15153 ms | +| tune0.98 | mx8_sh256x27 | base (0 x 1) | 252.17 | 687.3 | 2.726 | 1782 | 2619 | PASS | RESULT sparse tune device NVIDIA_H100_80GB_HBM3 sms 132 installed base 247.177 ceiling 247.177 hold 0.980 rows 132=241.720 99=204.596 chosen none (no sparse shape held; the installed kernel stays) 6572 ms | +| v5 | v5-genesis | ( x ) | 250.24 | 698.8 | 2.793 | 1674 | 2619 | PASS | | +| v5 | v4-genesis | ( x ) | 250.59 | 699.7 | 2.792 | 1732 | 2619 | PASS | | +| v5 | v4-genesis | base (0 x 1) | 250.58 | 699.6 | 2.792 | 1755 | 2619 | PASS | | + +RESULT after-micro label=h100 watts=136.6 RESULT microbench probe=sleep status=ok unit="none (the SM-resident floor: full occupancy, __nanosleep, no issue)" ops_per_step=0 lanes=270336 regs=11 blocks_per_sm=8 steps=2000 launches=13740 launch_ms=2.1 seconds=30.0 start_utc=2026-10-08T12:16:17Z end_utc=2026-10-08T12:16:47Z G_steps_s=247.619 G_ops_s=0.000 checksum=8b671be935472947 + + +RESULT after-micro label=h100 watts=437.9 RESULT microbench probe=int_arx status=ok unit="int32 add, xor or rotate (4 independent chains, 3 ops each per step)" ops_per_step=12 lanes=270336 regs=14 blocks_per_sm=8 steps=16384 launches=11899 launch_ms=2.4 seconds=30.0 start_utc=2026-10-08T12:16:47Z end_utc=2026-10-08T12:17:17Z G_steps_s=1756.760 G_ops_s=21081.115 checksum=fcb635c03d37ed2a + + +RESULT after-micro label=h100 watts=450.3 RESULT microbench probe=dram_chase_1g status=ok unit="dependent random 4-byte read in a 1 GiB table (the hash's own pattern, the control)" ops_per_step=1 lanes=270336 regs=19 blocks_per_sm=8 steps=512 launches=6982 launch_ms=4.2 seconds=30.0 start_utc=2026-10-08T12:17:17Z end_utc=2026-10-08T12:17:47Z G_steps_s=32.213 G_ops_s=32.213 checksum=7623c6b86570e4c + + +RESULT after-idle label=h100 watts=80.0 sm_mhz=350.6 mem_mhz=2619.0 + + + +### PC 1, the RTX 5090 alone, the hash lane's job `run-ca4-pc1-floorsm-5090-20261008` (the ca4sparse5 exe, unlocked and at the 1,300 MHz lock through the Power Helper) + + +The floorsm ladder + +| Pack | State | Shape | MH/s | W | Microjoules | SM MHz | Mem MHz | Temp max | Check | +|---|---|---|---|---|---|---|---|---|---| +| v4-devnet-epoch0 | unlocked | base (0) | 137.164 | 452.8 | 3.301 | 2865 | 13801 | 62 | PASS | +| v4-devnet-epoch0 | unlocked | sp170-w32 (170) | 136.407 | 462.6 | 3.391 | 2842 | 13801 | 67 | PASS | +| v4-devnet-epoch0 | unlocked | sp170-w16 (170) | 137.12 | 480.3 | 3.503 | 2842 | 13801 | 72 | PASS | +| v4-devnet-epoch0 | unlocked | sp170-w8 (170) | 137.035 | 482.9 | 3.524 | 2827.6 | 13801 | 74 | PASS | +| v4-devnet-epoch0 | unlocked | sp170-w4 (170) | 134.941 | 483.9 | 3.586 | 2827 | 13801 | 75 | PASS | +| v4-devnet-epoch0 | unlocked | sp170-w2 (170) | 98.779 | 409.6 | 4.147 | 2835 | 13801 | 73 | PASS | +| v4-devnet-epoch0 | unlocked | sp128-w32 (128) | 136.422 | 476.2 | 3.491 | 2835 | 13801 | 74 | PASS | +| v4-devnet-epoch0 | unlocked | sp96-w32 (96) | 134.373 | 470.6 | 3.502 | 2835 | 13801 | 75 | PASS | +| v4-devnet-epoch0 | unlocked | sp85-w32 (85) | 136.278 | 474.8 | 3.484 | 2835 | 13801 | 76 | PASS | +| v4-devnet-epoch0 | unlocked | sp64-w32 (64) | 136.056 | 474.7 | 3.489 | 2835 | 13801 | 75 | PASS | +| v4-devnet-epoch0 | unlocked | sp52-w32 (52) | 128.568 | 459.9 | 3.577 | 2842 | 13801 | 75 | PASS | +| v4-devnet-epoch0 | unlocked | sp43-w32 (43) | 134.477 | 470 | 3.495 | 2842 | 13801 | 75 | PASS | +| v4-devnet-epoch0 | unlocked | sp36-w32 (36) | 120.347 | 440.9 | 3.664 | 2842 | 13801 | 74 | PASS | +| v4-devnet-epoch0 | unlocked | sp32-w32 (32) | 107.265 | 413.1 | 3.851 | 2850 | 13801 | 73 | PASS | +| v4-devnet-epoch0 | unlocked | sp28-w32 (28) | 94.364 | 384.2 | 4.071 | 2857 | 13801 | 71 | PASS | +| v4-devnet-epoch0 | unlocked | sp24-w32 (24) | 80.823 | 353.8 | 4.377 | 2850 | 13801 | 69 | PASS | +| v4-devnet-epoch0 | unlocked | sp21-w32 (21) | 70.735 | 327.2 | 4.626 | 2850 | 13801 | 66 | PASS | +| v4-devnet-epoch0 | unlocked | sp16-w32 (16) | 53.985 | 290.9 | 5.389 | 2858.3 | 13801 | 64 | PASS | +| v4-devnet-epoch0 | unlocked | sp11-w32 (11) | 37.34 | 250.9 | 6.719 | 2872 | 13801 | 60 | PASS | +| v4-devnet-epoch0 | unlocked | sp43-w8 (43) | 89.595 | 362.8 | 4.049 | 2855.9 | 13801 | 65 | PASS | +| mx8-devnet-epoch0 | unlocked | base (0) | 136.721 | 320.9 | 2.347 | 2850 | 13801 | 63 | PASS | +| mx8-devnet-epoch0 | unlocked | sp170-w32 (170) | 136.166 | 319.1 | 2.343 | 2850 | 13801 | 63 | PASS | +| mx8-devnet-epoch0 | unlocked | sp170-w16 (170) | 136.884 | 316.8 | 2.314 | 2850 | 13801 | 63 | PASS | +| mx8-devnet-epoch0 | unlocked | sp170-w8 (170) | 137.149 | 310.8 | 2.266 | 2850 | 13801 | 63 | PASS | +| mx8-devnet-epoch0 | unlocked | sp170-w4 (170) | 136.904 | 310.9 | 2.271 | 2865 | 13801 | 63 | PASS | +| mx8-devnet-epoch0 | unlocked | sp170-w2 (170) | 135.705 | 309.9 | 2.284 | 2865 | 13801 | 62 | PASS | +| mx8-devnet-epoch0 | unlocked | sp128-w32 (128) | 136.627 | 313.4 | 2.294 | 2865 | 13801 | 62 | PASS | +| mx8-devnet-epoch0 | unlocked | sp96-w32 (96) | 134.635 | 309.9 | 2.302 | 2865 | 13801 | 62 | PASS | +| mx8-devnet-epoch0 | unlocked | sp85-w32 (85) | 136.758 | 311.6 | 2.278 | 2865 | 13801 | 62 | PASS | +| mx8-devnet-epoch0 | unlocked | sp64-w32 (64) | 136.733 | 311.3 | 2.277 | 2865 | 13801 | 62 | PASS | +| mx8-devnet-epoch0 | unlocked | sp52-w32 (52) | 132.782 | 307.2 | 2.314 | 2865 | 13801 | 62 | PASS | +| mx8-devnet-epoch0 | unlocked | sp43-w32 (43) | 136.463 | 310.6 | 2.276 | 2865 | 13801 | 61 | PASS | +| mx8-devnet-epoch0 | unlocked | sp36-w32 (36) | 136.046 | 309.6 | 2.276 | 2865 | 13801 | 61 | PASS | +| mx8-devnet-epoch0 | unlocked | sp32-w32 (32) | 135.686 | 309.4 | 2.280 | 2865 | 13801 | 61 | PASS | +| mx8-devnet-epoch0 | unlocked | sp28-w32 (28) | 135.201 | 308.6 | 2.283 | 2865 | 13801 | 61 | PASS | +| mx8-devnet-epoch0 | unlocked | sp24-w32 (24) | 133.819 | 307 | 2.294 | 2865 | 13801 | 61 | PASS | +| mx8-devnet-epoch0 | unlocked | sp21-w32 (21) | 132.826 | 305.6 | 2.301 | 2865 | 13801 | 61 | PASS | +| mx8-devnet-epoch0 | unlocked | sp16-w32 (16) | 125.545 | 294.4 | 2.345 | 2865 | 13801 | 61 | PASS | +| mx8-devnet-epoch0 | unlocked | sp11-w32 (11) | 100.111 | 275.1 | 2.748 | 2865.2 | 13801 | 60 | PASS | +| mx8-devnet-epoch0 | unlocked | sp43-w8 (43) | 135.989 | 306.2 | 2.252 | 2865 | 13801 | 61 | PASS | +| v4-devnet-epoch0 | 1300 | base (0) | 134.234 | 302 | 2.250 | 1290 | 13801 | 55 | PASS | +| v4-devnet-epoch0 | 1300 | sp170-w32 (170) | 128.882 | 298.1 | 2.313 | 1290 | 13801 | 59 | PASS | +| v4-devnet-epoch0 | 1300 | sp170-w16 (170) | 130.496 | 302.4 | 2.317 | 1290 | 13801 | 61 | PASS | +| v4-devnet-epoch0 | 1300 | sp170-w8 (170) | 131.723 | 303.7 | 2.306 | 1290 | 13801 | 62 | PASS | +| v4-devnet-epoch0 | 1300 | sp170-w4 (170) | 101.305 | 267.2 | 2.638 | 1290 | 13801 | 60 | PASS | +| v4-devnet-epoch0 | 1300 | sp170-w2 (170) | 54.393 | 197.9 | 3.638 | 1290 | 13801 | 57 | PASS | +| v4-devnet-epoch0 | 1300 | sp128-w32 (128) | 130.252 | 299 | 2.296 | 1290 | 13801 | 59 | PASS | +| v4-devnet-epoch0 | 1300 | sp96-w32 (96) | 120.933 | 286.1 | 2.366 | 1290 | 13801 | 60 | PASS | +| v4-devnet-epoch0 | 1300 | sp85-w32 (85) | 125.221 | 292.8 | 2.338 | 1290 | 13801 | 61 | PASS | +| v4-devnet-epoch0 | 1300 | sp64-w32 (64) | 95.167 | 249.9 | 2.626 | 1290 | 13801 | 59 | PASS | +| v4-devnet-epoch0 | 1300 | sp52-w32 (52) | 77.801 | 228.9 | 2.942 | 1290 | 13801 | 57 | PASS | +| v4-devnet-epoch0 | 1300 | sp43-w32 (43) | 64.343 | 208.5 | 3.240 | 1290 | 13801 | 55 | PASS | +| v4-devnet-epoch0 | 1300 | sp36-w32 (36) | 53.964 | 185.3 | 3.434 | 1290 | 13801 | 53 | PASS | +| v4-devnet-epoch0 | 1300 | sp32-w32 (32) | 47.978 | 174.7 | 3.641 | 1290 | 13801 | 51 | PASS | +| v4-devnet-epoch0 | 1300 | sp28-w32 (28) | 41.985 | 170.9 | 4.071 | 1290 | 13801 | 50 | PASS | +| v4-devnet-epoch0 | 1300 | sp24-w32 (24) | 35.981 | 158.5 | 4.405 | 1290 | 13801 | 49 | PASS | +| v4-devnet-epoch0 | 1300 | sp21-w32 (21) | 31.455 | 155 | 4.928 | 1290 | 13801 | 48 | PASS | +| v4-devnet-epoch0 | 1300 | sp16-w32 (16) | 24.07 | 137.3 | 5.704 | 1290 | 13801 | 46 | PASS | +| v4-devnet-epoch0 | 1300 | sp11-w32 (11) | 16.551 | 115.1 | 6.954 | 1290 | 13801 | 44 | PASS | +| v4-devnet-epoch0 | 1300 | sp43-w8 (43) | 45.592 | 173.4 | 3.803 | 1290 | 13801 | 46 | PASS | +| mx8-devnet-epoch0 | 1300 | base (0) | 134.076 | 213 | 1.589 | 1290 | 13801 | 48 | PASS | +| mx8-devnet-epoch0 | 1300 | sp170-w32 (170) | 129.08 | 208.9 | 1.618 | 1290 | 13801 | 49 | PASS | +| mx8-devnet-epoch0 | 1300 | sp170-w16 (170) | 130.441 | 209.7 | 1.608 | 1290 | 13801 | 51 | PASS | +| mx8-devnet-epoch0 | 1300 | sp170-w8 (170) | 130.788 | 209.7 | 1.603 | 1290 | 13801 | 51 | PASS | +| mx8-devnet-epoch0 | 1300 | sp170-w4 (170) | 130.789 | 210.1 | 1.606 | 1290 | 13801 | 52 | PASS | +| mx8-devnet-epoch0 | 1300 | sp170-w2 (170) | 130.278 | 210.4 | 1.615 | 1290 | 13801 | 52 | PASS | +| mx8-devnet-epoch0 | 1300 | sp128-w32 (128) | 132.634 | 213.6 | 1.610 | 1290 | 13801 | 53 | PASS | +| mx8-devnet-epoch0 | 1300 | sp96-w32 (96) | 120.795 | 205.2 | 1.699 | 1290 | 13801 | 52 | PASS | +| mx8-devnet-epoch0 | 1300 | sp85-w32 (85) | 110.96 | 191.9 | 1.729 | 1290 | 13801 | 52 | PASS | +| mx8-devnet-epoch0 | 1300 | sp64-w32 (64) | 103.449 | 187.2 | 1.810 | 1290 | 13801 | 51 | PASS | +| mx8-devnet-epoch0 | 1300 | sp52-w32 (52) | 85.585 | 174.3 | 2.037 | 1290 | 13801 | 50 | PASS | +| mx8-devnet-epoch0 | 1300 | sp43-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp36-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp32-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp28-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp24-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp21-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp16-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp11-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | 1300 | sp43-w8 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | base | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp170-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp170-w16 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp170-w8 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp170-w4 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp170-w2 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp128-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp96-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp85-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp64-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp52-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp43-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp36-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp32-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp28-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp24-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp21-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp16-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp11-w32 | | | | | | | error: budget | +| v4-devnet-epoch0 | unlocked-end | sp43-w8 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | base | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp170-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp170-w16 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp170-w8 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp170-w4 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp170-w2 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp128-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp96-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp85-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp64-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp52-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp43-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp36-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp32-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp28-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp24-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp21-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp16-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp11-w32 | | | | | | | error: budget | +| mx8-devnet-epoch0 | unlocked-end | sp43-w8 | | | | | | | error: budget | + + +### PC 1, the memory-clock ladder at the 1,300 MHz lock, job `run-ca4-pc1-memclk-5090-20261008` + + +The memory-clock ladder: not landed. + + +### The decomposition probes (the worker's --microbench: sleep = full residency and no issue; the L2 chase; the dependent DRAM chase; the ALU probe; 30 s each with the sampler's watts and both clocks) + + +| Card | Probe | Watts | SM MHz | Mem MHz | G ops or reads per s | Lanes | nJ or pJ per op over the sleep row | +|---|---|---|---|---|---|---|---| +| 4090 | idle | 33.9 | 210.0 | 405.0 | | | | +| 4090 | sleep | 133.1 | 2725.9 | 10501.0 | 0.000 | 196608 | | +| 4090 | int_arx | 448.0 | 2574.1 | 10501.0 | 26076.595 | 196608 | 12.1 pJ | +| 4090 | l2_chase_32m | 329.0 | 2715.0 | 10501.0 | 80.816 | 196608 | 2.42 nJ | +| 4090 | l2_indep4_32m | 328.2 | 2715.0 | 10501.0 | 82.301 | 196608 | 2370.6 pJ | +| 4090 | dram_chase_1g | 263.0 | 2715.0 | 10501.0 | 9.399 | 196608 | 13.82 nJ | +| 5090c | idle | 184.2 | 2044.5 | 11141.9 | | | | +| 5090c | sleep | 196.5 | 2865.0 | 13801.0 | 0.000 | 261120 | | +| 5090c | int_arx | 372.9 | 2853.9 | 13801.0 | 13064.448 | 261120 | 13.5 pJ | +| 5090c | l2_chase_32m | 382.2 | 2865.0 | 13801.0 | 53.964 | 261120 | 3.44 nJ | +| 5090c | l2_indep4_32m | 401.4 | 2851.3 | 13801.0 | 51.085 | 261120 | 4011.0 pJ | +| 5090c | dram_chase_1g | 372.9 | 2865.0 | 13801.0 | 8.019 | 261120 | 22.00 nJ | +| 5090e | idle | 8.7 | 180.0 | 405.0 | | | | +| 5090e | sleep | 139.0 | 2932.0 | 13801.0 | 0.000 | 261120 | | +| 5090e | int_arx | 535.6 | 2854.9 | 13801.0 | 29035.421 | 261120 | 13.7 pJ | +| 5090e | l2_chase_32m | 415.1 | 2902.0 | 13801.0 | 104.533 | 261120 | 2.64 nJ | +| 5090e | l2_indep4_32m | 434.9 | 2902.0 | 13801.0 | 112.864 | 261120 | 2621.7 pJ | +| 5090e | dram_chase_1g | 341.3 | 2904.0 | 13801.0 | 17.617 | 261120 | 11.48 nJ | +| h100 | idle | 71.8 | 345.0 | 2619.0 | | | | +| h100 | sleep | 130.3 | 1980.0 | 2619.0 | 0.000 | 270336 | | +| h100 | int_arx | 440.0 | 1980.0 | 2619.0 | 21499.215 | 270336 | 14.4 pJ | +| h100 | l2_chase_32m | 479.1 | 1980.0 | 2619.0 | 121.037 | 270336 | 2.88 nJ | +| h100 | l2_indep4_32m | 538.6 | 1980.0 | 2619.0 | 107.277 | 270336 | 3806.0 pJ | +| h100 | dram_chase_1g | 466.5 | 1980.0 | 2619.0 | 32.551 | 270336 | 10.33 nJ | + +## 2. What the rows say, shape by shape + +| Question | 5090 (host c; PC 1 for the lock) | 4090 | H100 | Label | +|---|---|---|---|---| +| Fewest SMs that hold 99 percent of class v3 | 43 of 170 (99.4); 28 holds 98.4 | 16 of 128 (99.0); the tune's 26 at 99.3 | 127 of 132 (the rate falls with the SM count below it) | measured | +| Watts at that point against base | 291.1 against 296.4 (-5 W); host e 337.4 against 352.7 (-15 W) | 249.6 against 253.4 (-4 W) | 441.6 against 450.4 (-9 W) | measured | +| Energy per hash at that point | 2.053 against 2.079 (-1.3 percent); host e -3.9 percent | 3.568 against 3.588 (-0.6); the tune's 3.567 | 1.744 against 1.769 (-1.4) | measured | +| Fewer warps per SM at full SM count | 8 warps per SM 2.063 (-0.8 percent); 2 warps 97.7 percent of rate at 2.072; 1 warp 84 percent | 8 warps 3.570; 1 warp 94 percent at 3.662 | 8 warps 99.2 percent at the same draw; 4 warps 93 percent; 1 warp 41 percent | measured | +| Matched warps, packed against spread (43 x 32 against 170 x 8) | 2.053 against 2.063: equal | 32 x 8 (3.546) against the ladder's 256 warps (3.568): equal | 33 x 8 against 33 x 32: 123.5 against 123.4 MH/s, equal | measured | +| Class v4 knee by rate | 43 SMs (PC 1: 98 percent; 36 SMs 88; 28 SMs 69) | the full grid (all shapes within 0.1 percent; the ladder below 128 not run on class v4) | the shipped grid; the persistent shape loses 4 percent | measured | +| Class v4 watts at its knee | PC 1 470 W against 452.8 base (heat drift 62 to 75 C across the pass); host c capped at 450 | 356 against 353.5 | capped at 700 | measured | +| At the 1,300 MHz lock (PC 1, this file's job) | class v4: the full grid 134.2 MH/s at 302 W = 2.25 microjoules; the persistent shape on every SM 128.9 at 298.1 (the wrapper costs 4 percent); 128 SMs 130.3 at 299; 96 SMs 120.9 at 286; 85 SMs 125.2 at 292.8; 64 SMs 95.2 at 249.9; 43 SMs 64.3 at 208.5 (3.24 microjoules): nothing under the full grid's energy at any point. Class v3: the full grid 134.1 at 213 W = 1.589; 128 SMs 132.6 at 213.6; 96 SMs 120.8 at 205.2; 85 SMs 111.0 at 191.9; 64 SMs 103.4 at 187.2; 52 SMs 85.6 at 174.3; the rows under 52 SMs were cut by the job's 66-minute budget | no lock on a rented host | no lock on a rented host | measured; the class v3 lock ladder is PARTIAL and disagrees with 20.3b (85 SMs 129.8 MH/s at 207.8 W there against 111.0 at 191.9 here, 43 SMs 126.3 there, not reached here): the pass ran across the founder's card swap on PC 1 (14:2x UK) and is re-run before it replaces 20.3b's lock points | +| Class v3 at stock on PC 1 (this file's job, the same board as 20.3b) | base 136.7 at 320.9 W = 2.347; 43 SMs 136.5 at 310.6 = 2.276 (3.0 percent under); 28 SMs 135.2 at 308.6; 21 SMs 132.8 at 305.6; 16 SMs 125.5 at 294.4; 11 SMs 100.1 at 275.1; 170 SMs x 8 warps 137.1 at 310.8 = 2.266 (3.5 percent under, the best shape on PC 1) | | | measured; agrees with the rented ladder within 1 percent at every rung | +| Class v5 against class v4 | not run on the rented 5090s (the v5-kits worker has no sparse shapes); PC 1's v5lock-b of 8 October: v5 at the knee = v4 rate, +2 percent watts | not run | 250.2 MH/s at 698.8 W against 251.9 at 699.4: equal under the cap | measured | +| The memory-clock knob on a rented host | refused (-lmc, -lgc, -pl all refused on Vast) | refused (RunPod) | -lmc accepted and the clock did not move (2,619 MHz on the row at both settings) | measured | + +Two oddities the ladder shows and this file keeps: on host c the 96-SM and 52-SM shapes read 97.4 and 95.4 percent of +the rate where 85 and 43 read 99.9 and 99.4 (and host e's 52 reads 95.7, host d's 96 reads 97.5), so the dip is the +shape, not the host; the 5090's 170 SMs sit in 8 GPCs, and a block count that lands unevenly across them (96 and 52 +against 85 and 43) leaves some GPCs' L2 ports hotter than others. The persistent wrapper's own cost is visible on the +H100 only (sp132-w32 at 96 percent of class v4's base against 99.7 on class v3: a compute-bound kernel pays the loop). + +## 3. The decomposition: what the residual is + +The microbench's probes run one kernel each at full residency for 30 s with the sampler beside it: `sleep` (every warp +resident, no instruction issued: the SM clock domain awake and nothing else), `l2_chase_32m` (a dependent 4-byte chain +inside the L2: the L2 and crossbar path, no DRAM), `dram_chase_1g` (the hash's own pattern over 1 GiB: the DRAM path +through the same L2 and crossbar), `int_arx` (the ALU path). The table in section 1 carries the rows; the reading per +card, watts over idle: + +| Card | Idle | SM clock domain awake (sleep minus idle) | The L2 path per dependent read (l2 chase minus sleep, over reads per s) | The DRAM path per dependent read (dram chase minus sleep, over reads per s) | The hash's draw over idle at its read rate | Of which the memory path (hash minus sleep) | The memory's own, modelled (chip-model 5.3) | Label | +|---|---|---|---|---|---|---|---|---| +| RTX 5090, PC 1 (15.1a, 8 October, the microbench at stock) | 74.7 W | 45 W (120.2 at full residency) | 2.4 nJ (378.7 W at 107.6 G reads per s) | 10.9 nJ whole-card (318.4 W at 18.2 G); 8.5 nJ over the L2 path | 311 - 75 = 236 W at 17.6 G reads per s = 13.4 nJ per read (20.3's mx8 row) | 191 W = 10.9 nJ per read | 2.0 nJ per read plus 20 W static = 55 W, 3.1 nJ per read | measured; the memory's own modelled | +| RTX 5090, rented host e (this file's probes) | 8.7 W at 180 MHz | 130 W (139.0 W at 2,932 MHz) | 2.6 nJ (415.1 W at 104.5 G reads per s) | 11.5 nJ over the sleep row (341.3 W at 17.6 G); 18.9 nJ whole-card | 352.7 - 8.7 = 344 W at 18.2 G reads per s = 18.9 nJ per read | 214 W = 11.8 nJ per read | the same 55 W | measured; modelled | +| RTX 4090, rented | 33.9 W at 210 MHz | 99 W (133.1 W at 2,726 MHz with every warp resident and nothing issued) | 2.4 nJ (329.0 W at 80.8 G reads per s) | 13.8 nJ over the sleep row (263.0 W at 9.4 G); 24.4 nJ whole-card | 253.4 - 33.9 = 219 W at 9.04 G reads per s = 24.2 nJ per read | 120 W = 13.3 nJ per read | 2.0 nJ plus 15 W static = 33 W, 3.7 nJ per read (approximate for GDDR6X) | measured; modelled | +| H100 80 GB HBM3, rented | 71.8 to 80 W at 345 MHz | 50 to 58 W (130.3 to 136.6 W at 1,980 MHz) | 2.9 nJ (479.1 W at 121.0 G reads per s) | 10.3 nJ over the sleep row (466.5 W at 32.6 G); 12.1 nJ whole-card | 450.4 - 71.3 = 379 W at 32.6 G reads per s = 11.6 nJ per read | 320 W = 9.8 nJ per read | 1.2 nJ plus about 20 W static = 59 W, 1.8 nJ per read | measured; modelled | + +The reading: at the hash, each card's draw splits into a fixed "awake" floor (the card with every warp resident and +nothing issuing: 120 to 139 W on the 5090 whatever its idle, 133 W on the 4090, 130 to 137 W on the H100; the SM clock +tree, the GPCs' shared logic and the memory clock domain at their boost clocks; the SM-sparse rows say the SMs' own +share of it is 4 to 15 W, because emptying three quarters of them saves that much) and a per-read term on the memory +path (10.9 to 11.8 nJ per dependent read on the 5090 on two boards, 13.3 on the 4090, 9.8 on the H100) of which the +memory devices themselves are 2.0 or 1.2 nJ modelled; the difference (8 to 11 nJ per read) is the L2 slices, the +crossbar, the memory controllers and the PHY, in that order of distance from the SM, and the L2 path alone is 2.4 to +2.9 nJ of it (the L2 chase). The ALU path is not in the hash's draw at all (512 ops per hash at 11 to 14 pJ is under +1 W). The two 5090 boards agree on the per-read term within 8 percent and differ by 60 W on the idle (7 to 9 W on the +rented Linux boards against 75 W on PC 1 with its display), which is where the across-host base spread comes from. + +What the SM-sparse rows add to it: the SMs that go idle at the knee were worth 4 to 15 W on every card (the difference +between the sleeping SM clock domain at full residency and the same domain with three quarters of its SMs empty), so +the "SM clock domain awake" term is mostly the clock tree and the GPCs' shared logic, not the SMs' own schedulers and +register files. The rest of the draw over idle at the hash is the memory path on the GPU side: the L2 slices, the +crossbar, the memory controllers and the GDDR7 or HBM PHY, at the boost clock for the first three and at the memory +clock for the PHY. The core lock takes the first three down with the clock (the 5090's 311 to 213 W at the same 17.5 G +reads per second on PC 1, 20.3); the memory-clock lock is the only knob on the fourth, and no rented host allows it, so +its row is PC 1's (the memory-clock ladder table in section 1, the job `run-ca4-pc1-memclk-5090-20261008`). + +## 4. The honest floor per tier, and the fraction a chip cannot strip + +The chip of the record pays the memory's own energy per read, its static power and a controller and PHY of its own +(chip-model-v3 5.3 to 5.5: GDDR7 2.0 nJ per read plus 20 W static plus a 15 W controller at 166 MH/s = 0.466 +microjoules per hash; one HBM3 stack 0.321). The honest card pays the same memory's energy (the devices are the same +silicon on both sides) plus everything its die spends around the read. So the fraction of the card's energy per hash a +chip cannot strip is the memory side's own share of it, and the floor's real number per tier is that share: + +| Tier (class v3, stock unless named) | Card microjoules per hash | The memory side's own (modelled: the DRAM's 2.0 or 1.2 nJ x 128 reads, plus static over the rate) | Fraction a chip cannot strip | Edge at zero shadow: GDDR7 board / HBM3 stack / SRAM die | Label | +|---|---|---|---|---|---| +| RTX 5090, rented host c (the best board of four) | 2.079 | 0.256 + 0.140 = 0.40 | 19 percent | 4.5x / 6.5x / 14.9x | measured card; modelled memory | +| RTX 5090, rented host e (the worst of four) | 2.485 | 0.40 | 16 percent | 5.3x / 7.7x / 17.8x | the same | +| RTX 5090, PC 1 at the 1,300 MHz lock (20.3b, class v3 base) | 1.58 | 0.40 | 25 percent | 3.4x / 4.9x / 11.3x | measured | +| RTX 4090, rented (GDDR6X at 9.0 G reads per s) | 3.588 | 0.256 + 0.21 = 0.47 | 13 percent | 7.7x / 11.2x / 25.6x | measured card; modelled memory | +| H100 80 GB, rented (HBM3, 5 stacks) | 1.769 | 0.154 + 0.08 = 0.23 | 13 percent | 3.8x / 5.5x / 12.6x | the same | +| Apple M5 Max (6 October, GPU plus DRAM channels) | 0.78 | about 0.3 (approximate: LPDDR at 1.5 to 2.0 nJ) | about 40 percent | 1.7x / 2.4x / 5.6x | measured card; approximate memory | + +The edge columns above are against the model's three chips; the 5090 host c row is the honest 5090 floor at stock +this lane measured (4.5x against the GDDR7 board, not the 5.2x of the 7 October PC 2 row: the rented board draws 296 W +at 142.6 MH/s where PC 2's drew 330 at 136.6, and PC 1's 311 at 137.5; the three are one card model on three boards and +drivers, and the honest denominator is a band, as the denominator lane's file says). The lock row (PC 1, 20.3b) stays +the honest 5090 floor: 3.4x on class v3 at zero shadow, 3.6x at the knee on the efficiency pass's 1.67; with class v4's +shadow and the record's k band it is section 20.4's 2.1x at k = 1. + +Per tier, what it means and what is done: a home miner on one 5090, 4090 or any NVIDIA card gains 1 to 4 percent of +energy per hash from the occupancy at stock and never more, so nothing in the occupancy changes what the card earns; +the core lock stays the lever (the 5090: 1.67 against 2.26 microjoules, the Ember knob of 0.3.24), and the memory-clock +lock behind it is measured on PC 1 in this file; the self-tune ships as the safe default inside Ember's Efficiency tier +and costs nothing at Maximum. An H100 owner (a rented or data-centre tier) gets the 1.4 percent from the self-tune and +nothing from its memory clock (the knob is accepted and ignored on the rented host). A 4090 owner gets 1.3 percent. An +AMD or Apple owner gets nothing from this lane (the shapes are CUDA's; Metal and OpenCL workers run the shipped grid). + +## 5. The patch: `--sm-sparse auto` and the self-tune + +`proto-cuda/nvrtc/worker.cpp` on this branch: + +- `--sm-sparse auto|off|N` and `--sm-hold ` (default 0.99); the tuning file's per-card `"sm_sparse": "auto" | + "off" | ""` and `"sm_hold": 0.99` (the manifest's tuning object is written as is to `tuning.json`, so a fleet + default needs no app change; the flag wins over the file). A count pins `sp-w32` through the existing pinned race + (the vector warps gate the install); `auto` runs `tuneSparse` at the end of `buildPair`, on the first pack and on + every prepared pack, so a pack flip re-measures. +- `tuneSparse`: the persistent shape is one compiled kernel for every block count (N is the launch's grid, not the + text), so one NVRTC compile serves the whole search; the installed kernel's rate is the ceiling's first reading, the + sparse shape on every SM its second (the vector warps through it first: bit-exact or nothing is installed); the ladder + (`sparseLadder`: the SM count by quarters and eighths down to 2) descends until a shape falls under the hold and a + bisection of at most four probes closes the bracket; `chooseSparseBlocks` installs the fewest blocks that held. One + line goes out with the race line (`sparse tune device ... rows N=mhs ... chosen sp-w32 (x percent of the ceiling)`) + and the bench's RESULT line carries `variant=` and `sparse_blocks=`. +- Measured: H100 15.2 s, 6 probes, `chosen sp127-w32 253.179 (99.5% of the ceiling)`, the served row 253.2 MH/s at + 441.6 W (1.744 against 1.769 microjoules); class v4 on the H100 `chosen none` in 6.6 s (the persistent shape at 97.8 + percent of the ceiling, under the hold); RTX 4090 24.5 s, `chosen sp26-w32 (99.3%)`, 70.15 MH/s at 250.2 W (3.567 + against 3.588); RTX 5090 host c, class v3 at the 0.99 hold `chosen sp37-w32`, 141.27 MH/s at 286.5 W = 2.028 + against the base's 2.079 (2.5 percent), at 0.98 `sp27-w32` 2.033; class v4 at the 0.99 hold `sp82-w32` 3.178 + against 3.157 (nothing, inside noise under the board's 450 W cap), at 0.98 `sp71-w32` 3.185. The 0.99 hold is the + default: on class v4 it costs 1 percent of rate for no watts, which is why Maximum turns it off and Balanced holds + 0.995. +- Tests: `proto-cuda/nvrtc/emu/variant-test.cpp` case `sparse-tune` (the ladder from 170 SMs, the chooser on the 20.3b + rows at holds 0.99, 0.98, 0.5 and 1.0, the mode reader on nine strings, the tuning keys for two cards): PASS beside + the three earlier cases, built with the real headers on the H100 pod (`g++ -DIGNEUM_EMU`), 8 October 12:04 UTC. The + known-failed shape it guards: a hold of 1.0 or an empty row set must choose nothing (the 7 October fault was a shape + installed that was never measured). +- The tiers (the Ember tiers lane's `ember-tiers-25` carries the tier switch; this file names the mapping): Efficiency + writes `sm_sparse: auto, sm_hold: 0.985`; Balanced `auto, 0.995`; Maximum `off`. The tune runs inside the pair's build + (the prepare thread, ahead of the epoch), so a flip of tier or pack re-measures at the next prepare and the serve loop + never stalls; its cost is 7 to 25 s of the prepare lead (600 DAA). +- What it is not: a lever on the floor. It is a 1 to 4 percent per-watt line on NVIDIA at stock, worth shipping + because it is free and measured, and the frame (one compile, a ladder, a hold, bit-exact or nothing) is the shape any + later occupancy or clock self-tune takes. + +## 6. Unverified and owed + +- PC 1's 1,300 MHz lock ladder is in section 1 as the job left it: class v4 complete (every point under the full + grid's energy, the shadow compute-bound under 128 SMs at 1,290 MHz), class v3 cut at 52 SMs by the job's budget and + reading the sparse shapes lower than 20.3b did on the same board at the same lock (85 SMs 111.0 against 129.8 MH/s); + the pass ran across the founder's card swap on PC 1 (14:2x UK), so the class v3 lock row stays 20.3b's (43 SMs + 126.3 MH/s at 205.4 W against the full grid's 134.0 at 211.4: 1.63 against 1.58 microjoules, nothing saved) and the + ladder is re-run on a quiet PC 1 before it replaces it. The memory-clock ladder is queued behind the hash lane's two + jobs (run-ca4-pc1-memclk-5090-20261008-b) and lands in section 1 when its upload does. +- The decomposition probes on the 4090 and the 5090 host c: in section 1 when their runs end (queued behind the + sweeps on the same cards so no row shares the card). +- The memory side's own share per tier is modelled (chip-model 5.3); the memory-clock ladder is the one measurement of + its PHY term, and only on PC 1. +- Class v5 on the rented 5090s was not run (the v5-kits worker carries the leaf upload and not the sparse shapes; the + two trees merge in 0.3.26); the H100 row and PC 1's v5lock-b stand in. +- The 4090's class v4 ladder below 128 SMs was not run (the slice pods ran class v3 and the full-grid class v4 rows). +- Every chip figure is the model's; no chip has been measured. +- Spend: six pods, USD 25 of the lane's 300 (h100 3.49 per hour, 4090 0.74, four 5090s 0.44 to 0.56; two 5090 hosts + destroyed unused: one shared with another tenant's 5.7 GB process at 485 W idle, one with a dead CUDA init; the + Korean host vanished mid-run). diff --git a/docs/analysis/class-v6/logs/census/a-era.tsv b/docs/analysis/class-v6/logs/census/a-era.tsv new file mode 100644 index 000000000..407069e89 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/a-era.tsv @@ -0,0 +1,259 @@ +# a-era class w64m8g+sh256x27 eras [0,1,2,3,4,5,6,7] seeds 32 era-widths 64 weights base bittest 1 bin d601098699840534 start 2026-10-08T12:53:59Z host igneum-build-3 threads 8 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +a-era 0 7 8 1 7 3.2 12 8 a'=5;c,=2; +a-era 0 2 9 1 8 3.4 5 11 a'=7;a=1; +a-era 0 0 2 1 1 2.9 7 14 a'=1; +a-era 0 4 9 1 8 2.8 1 23 a'=4;c,=3;a=1; +a-era 0 1 6 1 5 3.1 3 7 a'=4;c,=1; +a-era 0 6 2 1 1 3.5 5 24 a'=1; +a-era 0 5 14 1 13 2.9 10 16 a'=12;a=1; +a-era 0 3 2 1 1 3.1 11 9 a'=1; +a-era 0 8 1 1 0 3.5 6 20 +a-era 0 10 1 1 0 3.0 6 20 +a-era 0 12 3 1 2 2.9 0 18 a'=2; +a-era 0 13 1 1 0 3.4 0 27 +a-era 0 9 5 1 4 2.8 15 4 a'=3;c,=1; +a-era 0 14 13 1 12 2.5 8 9 a'=9;a=2;c,=1; +a-era 0 11 9 1 8 3.1 4 21 c,=5;a'=3; +a-era 0 15 6 1 5 3.4 1 9 a'=3;c,=1;a=1; +a-era 0 16 5 1 4 3.3 14 18 a'=4; +a-era 0 18 3 1 2 3.2 10 25 c,=2; +a-era 0 17 3 1 2 3.1 8 5 a'=2; +a-era 0 19 5 1 4 3.0 8 12 a'=3;a=1; +a-era 0 21 4 1 3 3.1 13 4 a'=3; +a-era 0 20 8 1 7 3.6 7 11 a'=5;c,=1;a=1; +a-era 0 22 6 1 5 2.6 8 11 a'=4;a=1; +a-era 0 23 4 1 3 2.9 5 8 c,=1;a'=1;a=1; +a-era 0 24 3 1 2 3.0 9 24 a'=2; +a-era 0 25 6 1 5 3.1 10 13 c,=2;a=2;a'=1; +a-era 0 30 8 1 7 3.1 3 19 a'=6;a=1; +a-era 0 28 15 1 14 2.9 2 10 a'=10;c,=2;a=2; +a-era 0 29 4 1 3 4.1 7 8 c,=2;a'=1; +a-era 0 27 7 1 6 3.3 10 12 a'=6; +a-era 0 26 2 1 1 4.0 13 15 a'=1; +a-era 0 31 12 1 11 5.9 0 21 a'=5;c,=3;a=2;b=1; +a-era 1 0 2 1 1 2.9 5 12 a'=1; +a-era 1 2 9 1 8 3.5 12 16 a'=7;a=1; +a-era 1 1 6 1 5 2.8 0 6 a'=4;c,=1; +a-era 1 3 2 1 1 3.0 14 13 a'=1; +a-era 1 4 12 1 11 2.6 14 17 a'=6;c,=4;a=1; +a-era 1 5 21 1 20 3.1 13 17 a'=15;c,=3;a=2; +a-era 1 6 2 1 1 3.0 0 11 a'=1; +a-era 1 7 8 1 7 3.4 6 8 a'=5;c,=2; +a-era 1 8 1 1 0 3.2 1 19 +a-era 1 9 5 1 4 3.4 15 7 a'=3;c,=1; +a-era 1 10 1 1 0 3.4 3 20 +a-era 1 11 9 1 8 2.8 14 24 c,=5;a'=3; +a-era 1 13 1 1 0 3.0 4 4 +a-era 1 12 3 1 2 3.2 15 9 a'=2; +a-era 1 14 13 1 12 3.0 6 16 a'=9;a=2;c,=1; +a-era 1 15 6 1 5 3.4 13 23 a'=3;c,=1;a=1; +a-era 1 16 5 1 4 3.2 8 4 a'=4; +a-era 1 17 3 1 2 3.0 1 21 a'=2; +a-era 1 18 3 1 2 3.2 14 18 c,=2; +a-era 1 20 8 1 7 3.1 7 22 a'=5;c,=1;a=1; +a-era 1 19 5 1 4 2.8 5 12 a'=3;a=1; +a-era 1 21 4 1 3 3.1 11 8 a'=3; +a-era 1 22 6 1 5 3.2 8 5 a'=4;a=1; +a-era 1 24 3 1 2 2.9 11 19 a'=2; +a-era 1 23 4 1 3 2.5 8 14 c,=1;a'=1;a=1; +a-era 1 25 6 1 5 3.5 15 8 c,=2;a=2;a'=1; +a-era 1 26 2 1 1 2.5 0 20 a'=1; +a-era 1 28 15 1 14 3.2 12 6 a'=10;c,=2;a=2; +a-era 1 27 7 1 6 3.0 7 7 a'=6; +a-era 1 29 4 1 3 3.6 14 25 c,=2;a'=1; +a-era 1 30 41 1 40 2.7 6 5 a'=29;c,=8;a=2;b=1; +a-era 2 0 2 1 1 2.7 13 20 a'=1; +a-era 1 31 17 1 16 3.4 11 15 a'=7;c,=5;a=3;b=1; +a-era 2 1 4 1 3 2.6 2 9 a'=3; +a-era 2 2 9 1 8 3.1 8 11 a'=7;a=1; +a-era 2 3 2 1 1 3.3 10 16 a'=1; +a-era 2 4 2 1 1 3.3 6 6 a'=1; +a-era 2 5 14 1 13 3.1 2 6 a'=12;a=1; +a-era 2 6 2 1 1 3.1 12 21 a'=1; +a-era 2 7 4 1 3 3.1 13 16 a'=3; +a-era 2 8 1 1 0 2.8 10 9 +a-era 2 9 3 1 2 3.2 7 15 a'=2; +a-era 2 10 1 1 0 2.3 7 7 +a-era 2 11 2 1 1 3.5 10 16 a'=1; +a-era 2 12 3 1 2 2.7 1 6 a'=2; +a-era 2 13 1 1 0 4.3 15 25 +a-era 2 14 5 1 4 2.9 1 13 a'=3;a=1; +a-era 2 15 3 1 2 2.8 8 5 a'=2; +a-era 2 16 5 1 4 3.2 5 9 a'=4; +a-era 2 17 3 1 2 2.7 10 19 a'=2; +a-era 2 18 1 1 0 4.0 6 9 +a-era 2 19 5 1 4 4.0 12 23 a'=3;a=1; +a-era 2 20 7 1 6 3.6 8 10 a'=5;a=1; +a-era 2 21 4 1 3 3.0 4 21 a'=3; +a-era 2 22 6 1 5 2.8 13 15 a'=4;a=1; +a-era 2 23 2 1 1 2.8 14 17 a=1; +a-era 2 24 3 1 2 2.5 13 13 a'=2; +a-era 2 25 4 1 3 3.3 12 13 a=2;a'=1; +a-era 2 26 2 1 1 2.7 10 23 a'=1; +a-era 2 27 7 1 6 3.7 1 17 a'=6; +a-era 2 28 8 1 7 3.1 14 14 a'=5;a=2; +a-era 2 29 2 1 1 3.0 1 23 a'=1; +a-era 2 30 8 1 7 3.3 5 4 a'=6;a=1; +a-era 2 31 4 1 3 3.7 10 15 a'=2;b=1; +a-era 3 0 2 1 1 2.8 5 9 a'=1; +a-era 3 1 4 1 3 2.8 4 13 a'=3; +a-era 3 2 9 1 8 3.7 7 26 a'=7;a=1; +a-era 3 4 2 1 1 2.7 10 12 a'=1; +a-era 3 3 2 1 1 2.9 13 14 a'=1; +a-era 3 5 14 1 13 2.9 5 12 a'=12;a=1; +a-era 3 6 2 1 1 2.6 6 17 a'=1; +a-era 3 8 1 1 0 3.8 0 24 +a-era 3 7 4 1 3 3.0 0 18 a'=3; +a-era 3 9 3 1 2 4.2 5 19 a'=2; +a-era 3 10 1 1 0 3.5 5 16 +a-era 3 11 2 1 1 3.3 5 4 a'=1; +a-era 3 12 3 1 2 3.5 9 15 a'=2; +a-era 3 13 1 1 0 3.0 6 16 +a-era 3 14 5 1 4 3.6 14 10 a'=3;a=1; +a-era 3 15 3 1 2 3.8 14 19 a'=2; +a-era 3 16 5 1 4 3.0 13 10 a'=4; +a-era 3 17 3 1 2 2.7 0 26 a'=2; +a-era 3 18 1 1 0 3.2 14 5 +a-era 3 20 7 1 6 3.1 11 23 a'=5;a=1; +a-era 3 19 5 1 4 3.2 12 22 a'=3;a=1; +a-era 3 21 4 1 3 2.9 7 15 a'=3; +a-era 3 22 6 1 5 2.8 3 5 a'=4;a=1; +a-era 3 23 2 1 1 3.5 2 21 a=1; +a-era 3 24 3 1 2 4.1 3 24 a'=2; +a-era 3 25 4 1 3 3.5 4 6 a=2;a'=1; +a-era 3 26 2 1 1 2.8 0 15 a'=1; +a-era 3 28 8 1 7 3.1 7 24 a'=5;a=2; +a-era 3 27 7 1 6 3.8 6 11 a'=6; +a-era 3 29 2 1 1 3.5 3 11 a'=1; +a-era 3 30 8 1 7 3.0 14 9 a'=6;a=1; +a-era 3 31 6 1 5 3.1 1 10 a'=3;c,=1;b=1; +a-era 4 0 2 1 1 3.8 12 22 a'=1; +a-era 4 1 6 1 5 2.8 3 14 a'=4;c,=1; +a-era 4 2 9 1 8 3.5 15 8 a'=7;a=1; +a-era 4 3 2 1 1 2.8 14 19 a'=1; +a-era 4 4 9 1 8 3.5 1 14 a'=4;c,=3;a=1; +a-era 4 5 21 1 20 3.1 0 4 a'=15;c,=3;a=2; +a-era 4 6 2 1 1 3.0 12 12 a'=1; +a-era 4 8 1 1 0 3.0 4 8 +a-era 4 7 8 1 7 4.0 3 21 a'=5;c,=2; +a-era 4 9 5 1 4 2.7 8 21 a'=3;c,=1; +a-era 4 10 1 1 0 3.8 3 22 +a-era 4 11 9 1 8 3.0 4 4 c,=5;a'=3; +a-era 4 12 3 1 2 2.9 6 26 a'=2; +a-era 4 13 1 1 0 3.8 9 25 +a-era 4 14 13 1 12 3.9 1 5 a'=9;a=2;c,=1; +a-era 4 16 5 1 4 3.3 0 19 a'=4; +a-era 4 15 6 1 5 2.5 0 11 a'=3;c,=1;a=1; +a-era 4 17 3 1 2 3.2 6 17 a'=2; +a-era 4 18 3 1 2 3.5 1 4 c,=2; +a-era 4 20 8 1 7 4.0 2 21 a'=5;c,=1;a=1; +a-era 4 19 5 1 4 3.3 12 19 a'=3;a=1; +a-era 4 21 4 1 3 3.2 2 4 a'=3; +a-era 4 22 6 1 5 3.3 7 22 a'=4;a=1; +a-era 4 24 3 1 2 3.0 12 26 a'=2; +a-era 4 23 36 1 35 2.5 3 24 a'=21;c,=9;a=4;c=1; +a-era 4 25 6 1 5 2.8 1 14 c,=2;a=2;a'=1; +a-era 4 26 2 1 1 3.2 14 6 a'=1; +a-era 4 27 7 1 6 2.7 14 16 a'=6; +a-era 4 28 15 1 14 3.9 12 11 a'=10;c,=2;a=2; +a-era 4 29 4 1 3 3.5 8 9 c,=2;a'=1; +a-era 4 30 41 1 40 3.1 7 13 a'=29;c,=8;a=2;b=1; +a-era 4 31 17 1 16 3.9 11 7 a'=7;c,=5;a=3;b=1; +a-era 5 0 2 1 1 3.8 10 17 a'=1; +a-era 5 1 6 1 5 3.1 13 4 a'=4;c,=1; +a-era 5 2 9 1 8 3.5 10 23 a'=7;a=1; +a-era 5 3 2 1 1 3.6 11 19 a'=1; +a-era 5 4 9 1 8 3.5 12 13 a'=4;c,=3;a=1; +a-era 5 5 21 1 20 2.8 9 15 a'=15;c,=3;a=2; +a-era 5 6 2 1 1 3.3 9 13 a'=1; +a-era 5 8 1 1 0 3.2 8 23 +a-era 5 7 8 1 7 2.9 1 18 a'=5;c,=2; +a-era 5 9 5 1 4 3.3 5 25 a'=3;c,=1; +a-era 5 10 1 1 0 3.5 9 9 +a-era 5 11 9 1 8 2.8 12 21 c,=5;a'=3; +a-era 5 12 3 1 2 3.1 14 17 a'=2; +a-era 5 13 1 1 0 3.3 2 19 +a-era 5 14 13 1 12 2.7 9 15 a'=9;a=2;c,=1; +a-era 5 15 6 1 5 3.4 10 16 a'=3;c,=1;a=1; +a-era 5 16 5 1 4 3.2 6 11 a'=4; +a-era 5 17 3 1 2 3.4 4 13 a'=2; +a-era 5 18 3 1 2 2.9 0 5 c,=2; +a-era 5 19 5 1 4 2.6 9 16 a'=3;a=1; +a-era 5 20 8 1 7 3.5 10 10 a'=5;c,=1;a=1; +a-era 5 21 4 1 3 2.6 5 25 a'=3; +a-era 5 22 6 1 5 3.4 13 4 a'=4;a=1; +a-era 5 24 3 1 2 3.2 12 9 a'=2; +a-era 5 23 4 1 3 3.4 5 24 c,=1;a'=1;a=1; +a-era 5 25 6 1 5 3.0 5 10 c,=2;a=2;a'=1; +a-era 5 26 2 1 1 3.2 9 18 a'=1; +a-era 5 27 7 1 6 3.7 5 9 a'=6; +a-era 5 28 15 1 14 3.4 12 22 a'=10;c,=2;a=2; +a-era 5 29 4 1 3 3.6 2 18 c,=2;a'=1; +a-era 5 30 8 1 7 5.6 13 23 a'=6;a=1; +a-era 6 0 2 1 1 3.3 12 22 a'=1; +a-era 5 31 17 1 16 3.1 9 12 a'=7;c,=5;a=3;b=1; +a-era 6 1 6 1 5 2.4 9 20 a'=4;c,=1; +a-era 6 2 9 1 8 3.5 5 6 a'=7;a=1; +a-era 6 3 2 1 1 3.0 2 12 a'=1; +a-era 6 4 6 1 5 3.0 10 24 a'=4;c,=1; +a-era 6 5 19 1 18 3.5 14 17 a'=14;c,=2;a=2; +a-era 6 6 2 1 1 3.7 12 25 a'=1; +a-era 6 7 4 1 3 3.5 7 26 a'=3; +a-era 6 8 1 1 0 3.1 2 13 +a-era 6 9 5 1 4 3.1 15 20 a'=3;c,=1; +a-era 6 10 1 1 0 2.8 6 12 +a-era 6 11 2 1 1 3.5 11 4 a'=1; +a-era 6 12 3 1 2 2.9 7 24 a'=2; +a-era 6 13 1 1 0 3.3 9 19 +a-era 6 15 3 1 2 5.7 12 4 a'=2; +a-era 6 14 13 1 12 3.1 15 10 a'=9;a=2;c,=1; +a-era 6 16 5 1 4 2.9 8 18 a'=4; +a-era 6 17 3 1 2 3.4 10 18 a'=2; +a-era 6 18 1 1 0 3.1 3 21 +a-era 6 19 5 1 4 3.4 5 23 a'=3;a=1; +a-era 6 20 8 1 7 3.5 5 25 a'=5;c,=1;a=1; +a-era 6 21 4 1 3 2.8 1 23 a'=3; +a-era 6 24 3 1 2 2.8 7 16 a'=2; +a-era 6 22 6 1 5 3.8 1 14 a'=4;a=1; +a-era 6 23 36 1 35 3.0 13 11 a'=21;c,=9;a=4;c=1; +a-era 6 25 5 1 4 2.8 15 16 a=2;c,=1;a'=1; +a-era 6 26 2 1 1 3.0 3 20 a'=1; +a-era 6 27 7 1 6 2.7 1 7 a'=6; +a-era 6 28 15 1 14 5.0 12 4 a'=10;c,=2;a=2; +a-era 6 29 4 1 3 2.6 13 20 c,=2;a'=1; +a-era 6 31 14 1 13 3.4 15 4 a'=6;c,=4;a=2;b=1; +a-era 6 30 41 1 40 3.2 8 20 a'=29;c,=8;a=2;b=1; +a-era 7 0 2 1 1 2.8 14 26 a'=1; +a-era 7 1 4 1 3 2.7 5 11 a'=3; +a-era 7 2 9 1 8 3.0 8 14 a'=7;a=1; +a-era 7 3 2 1 1 2.9 5 6 a'=1; +a-era 7 4 2 1 1 3.4 8 24 a'=1; +a-era 7 5 14 1 13 3.1 7 23 a'=12;a=1; +a-era 7 6 2 1 1 2.9 13 16 a'=1; +a-era 7 8 1 1 0 3.1 7 10 +a-era 7 7 6 1 5 2.8 1 7 a'=4;c,=1; +a-era 7 9 3 1 2 2.8 3 26 a'=2; +a-era 7 10 1 1 0 2.6 4 25 +a-era 7 11 2 1 1 3.4 4 14 a'=1; +a-era 7 12 3 1 2 3.5 15 4 a'=2; +a-era 7 13 1 1 0 3.4 14 15 +a-era 7 15 6 1 5 2.8 6 12 a'=3;c,=1;a=1; +a-era 7 14 5 1 4 3.3 2 12 a'=3;a=1; +a-era 7 16 5 1 4 2.9 8 13 a'=4; +a-era 7 17 3 1 2 3.8 14 20 a'=2; +a-era 7 18 3 1 2 3.0 2 15 c,=2; +a-era 7 19 5 1 4 2.5 11 17 a'=3;a=1; +a-era 7 20 8 1 7 3.1 7 27 a'=5;c,=1;a=1; +a-era 7 21 4 1 3 3.1 1 11 a'=3; +a-era 7 23 2 1 1 3.0 9 22 a=1; +a-era 7 24 3 1 2 3.4 5 17 a'=2; +a-era 7 22 6 1 5 3.1 11 4 a'=4;a=1; +a-era 7 25 4 1 3 3.5 10 16 a=2;a'=1; +a-era 7 26 2 1 1 3.1 15 8 a'=1; +a-era 7 27 7 1 6 2.6 6 11 a'=6; +a-era 7 28 14 1 13 3.8 7 12 a'=10;a=2;c,=1; +a-era 7 29 2 1 1 4.1 0 16 a'=1; +a-era 7 30 8 1 7 2.7 1 7 a'=6;a=1; +a-era 7 31 6 1 5 3.1 10 20 a'=3;c,=1;b=1; +# end 2026-10-08T12:58:29Z rows=257 diff --git a/docs/analysis/class-v6/logs/census/a-none.tsv b/docs/analysis/class-v6/logs/census/a-none.tsv new file mode 100644 index 000000000..9634c530b --- /dev/null +++ b/docs/analysis/class-v6/logs/census/a-none.tsv @@ -0,0 +1,259 @@ +# a-none class w64m8g+sh256x27 eras [none] seeds 256 era-widths 64 weights base bittest off bin d601098699840534 start 2026-10-08T12:37:23Z host igneum-build-3 threads 8 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +a-none none 2 5 1 4 2.8 8 24 a'=3;a=1; +a-none none 6 2 1 1 3.6 2 5 a'=1; +a-none none 7 1 1 0 5.2 11 5 +a-none none 0 3 1 2 3.1 7 10 a'=2; +a-none none 4 2 1 1 2.9 12 17 a'=1; +a-none none 1 2 1 1 4.3 5 4 a'=1; +a-none none 5 2 1 1 3.2 1 12 a'=1; +a-none none 3 7 1 6 3.0 13 5 a'=3;a=2;c'''=1; +a-none none 9 7 1 6 2.5 6 11 a'=5;a=1; +a-none none 13 2 1 1 4.0 9 11 a'=1; +a-none none 10 7 1 6 3.4 2 16 a'=6; +a-none none 8 2 1 1 2.5 14 27 a'=1; +a-none none 12 1 1 0 3.2 1 4 +a-none none 14 9 1 8 10.4 12 27 a'=7;a=1; +a-none none 11 1 1 0 2.9 2 24 +a-none none 15 3 1 2 3.1 4 18 a'=2; +a-none none 16 10 1 9 3.4 2 17 a'=9; +a-none none 18 3 1 2 3.1 15 27 a'=2; +a-none none 19 3 1 2 2.9 12 26 a'=2; +a-none none 17 2 1 1 2.9 6 21 a'=1; +a-none none 20 3 1 2 3.2 6 23 a'=1;a=1; +a-none none 21 5 1 4 2.7 8 21 a'=4; +a-none none 22 1 1 0 2.7 4 15 +a-none none 23 4 1 3 4.2 0 16 a'=3; +a-none none 25 13 1 12 3.2 12 19 a'=10;a=2; +a-none none 24 2 1 1 2.7 0 6 a'=1; +a-none none 27 3 1 2 3.0 5 27 b=1;a'=1; +a-none none 29 3 1 2 5.2 9 4 a'=2; +a-none none 28 2 1 1 8.2 4 4 a'=1; +a-none none 30 3 1 2 8.8 0 4 a'=1;a=1; +a-none none 26 7 1 6 3.9 2 4 a'=4;c''=1;a=1; +a-none none 32 4 1 3 2.9 13 14 a'=3; +a-none none 33 2 1 1 3.7 3 4 a=1; +a-none none 34 2 1 1 2.9 12 25 a=1; +a-none none 31 12 1 11 3.0 5 8 a'=7;a=2;c''=1;b=1; +a-none none 35 12 1 11 5.8 6 6 a'=9;a=2; +a-none none 36 1 1 0 3.3 11 18 +a-none none 37 4 1 3 10.5 11 4 a'=3; +a-none none 39 1 1 0 3.4 5 20 +a-none none 40 1 1 0 2.7 7 18 +a-none none 38 4 1 3 2.8 3 4 c'''=1;b=1;a'=1; +a-none none 42 1 1 0 4.0 7 4 +a-none none 43 2 1 1 3.1 6 4 a'=1; +a-none none 44 5 1 4 4.7 8 4 a'=4; +a-none none 45 9 1 8 3.6 2 8 a'=7;a=1; +a-none none 46 5 1 4 4.7 5 4 a'=4; +a-none none 47 1 1 0 3.0 3 10 +a-none none 41 5 1 4 4.0 9 4 c''=2;a'=2; +a-none none 48 2 1 1 2.9 1 23 a'=1; +a-none none 49 2 1 1 3.8 7 9 a=1; +a-none none 51 2 1 1 3.2 9 6 a'=1; +a-none none 50 2 1 1 4.3 12 4 a'=1; +a-none none 52 1 1 0 8.1 4 10 +a-none none 54 5 1 4 3.7 3 4 a'=3;a=1; +a-none none 56 4 1 3 3.0 15 9 a'=3; +a-none none 55 1 1 0 3.2 2 17 +a-none none 57 1 1 0 2.9 15 9 +a-none none 58 6 1 5 6.8 9 5 a'=5; +a-none none 59 4 1 3 2.9 13 11 a'=3; +a-none none 60 2 1 1 3.6 12 11 a'=1; +a-none none 53 2 1 1 3.7 1 4 c''=1; +a-none none 61 3 1 2 7.9 14 4 a'=2; +a-none none 64 4 1 3 3.2 4 25 a'=2;a=1; +a-none none 65 4 1 3 5.6 4 4 a'=2;b=1; +a-none none 66 6 1 5 4.3 10 4 a'=4;a=1; +a-none none 67 4 1 3 5.6 15 4 a'=2;a=1; +a-none none 68 2 1 1 5.3 6 27 a'=1; +a-none none 62 4 1 3 2.9 7 23 a'=2;c''=1; +a-none none 63 15 1 14 3.1 5 16 a'=13;c'''=1; +a-none none 69 4 1 3 41.9 0 15 a'=2;a=1; +a-none none 70 2 1 1 3.6 15 16 a'=1; +a-none none 71 3 1 2 3.2 6 14 c=1;a'=1; +a-none none 73 4 1 3 3.6 8 18 a'=3; +a-none none 74 1 1 0 3.2 3 14 +a-none none 75 1 1 0 3.4 0 17 +a-none none 76 4 1 3 3.6 0 15 a'=2;a=1; +a-none none 72 7 1 6 3.2 4 24 a'=5;c''=1; +a-none none 78 3 1 2 3.6 6 4 a'=2; +a-none none 79 1 1 0 2.8 5 21 +a-none none 80 5 1 4 2.9 2 7 a'=4; +a-none none 81 3 1 2 3.3 11 12 a'=2; +a-none none 77 14 1 13 3.2 0 21 a'=9;b=2;c''=1;a=1; +a-none none 82 3 1 2 3.4 6 9 a'=2; +a-none none 83 1 1 0 3.2 5 5 +a-none none 85 1 1 0 3.2 2 15 +a-none none 86 2 1 1 2.9 0 10 a'=1; +a-none none 84 3 1 2 12.6 9 4 c'''=1;a'=1; +a-none none 87 1 1 0 32.2 9 10 +a-none none 88 6 1 5 3.3 10 26 a'=4;b=1; +a-none none 89 4 1 3 3.6 0 4 a'=2;b=1; +a-none none 90 2 1 1 3.0 12 17 a'=1; +a-none none 91 1 1 0 2.5 9 24 +a-none none 92 1 1 0 3.5 14 25 +a-none none 93 1 1 0 3.5 10 6 +a-none none 94 1 1 0 5.1 5 4 +a-none none 95 2 1 1 2.8 11 27 a'=1; +a-none none 96 3 1 2 3.8 11 14 a'=2; +a-none none 97 1 1 0 3.2 11 15 +a-none none 99 1 1 0 2.9 12 10 +a-none none 98 3 1 2 3.5 0 4 c'''=1;a'=1; +a-none none 100 2 1 1 2.9 5 26 a'=1; +a-none none 101 1 1 0 4.1 13 27 +a-none none 102 1 1 0 3.3 12 4 +a-none none 103 1 1 0 3.9 8 4 +a-none none 104 1 1 0 3.1 5 27 +a-none none 106 4 1 3 5.0 10 18 a'=2;a=1; +a-none none 105 8 1 7 3.3 12 15 a'=6;c'''=1; +a-none none 107 3 1 2 9.6 0 27 a'=2; +a-none none 108 2 1 1 3.5 0 11 a'=1; +a-none none 110 2 1 1 2.6 13 22 a'=1; +a-none none 109 1 1 0 3.0 12 16 +a-none none 111 1 1 0 3.3 2 25 +a-none none 112 3 1 2 5.5 3 4 b=1;a'=1; +a-none none 113 1 1 0 4.3 12 4 +a-none none 114 10 1 9 2.8 4 24 a'=8;a=1; +a-none none 115 1 1 0 3.0 11 4 +a-none none 116 4 1 3 3.3 8 5 a'=3; +a-none none 117 4 1 3 3.6 5 10 a'=3; +a-none none 118 3 1 2 3.7 10 4 c=1;a=1; +a-none none 119 2 1 1 9.0 3 21 a'=1; +a-none none 121 1 1 0 2.8 13 9 +a-none none 122 1 1 0 25.4 2 4 +a-none none 120 5 1 4 3.3 5 4 a'=3;c''=1; +a-none none 124 1 1 0 3.3 5 12 +a-none none 125 1 1 0 3.0 9 5 +a-none none 126 2 1 1 2.8 15 26 a'=1; +a-none none 123 2 1 1 33.0 5 5 c'''=1; +a-none none 128 2 1 1 5.9 4 27 a'=1; +a-none none 127 7 1 6 2.8 2 16 a'=4;c'''=1;a=1; +a-none none 129 1 1 0 3.1 14 26 +a-none none 130 7 1 6 3.0 14 13 a'=5;b=1; +a-none none 131 2 1 1 4.2 5 4 a'=1; +a-none none 132 1 1 0 3.1 9 16 +a-none none 133 1 1 0 26.9 0 10 +a-none none 134 2 1 1 2.8 7 19 a'=1; +a-none none 135 2 1 1 3.2 2 23 a'=1; +a-none none 136 1 1 0 25.4 6 4 +a-none none 137 2 1 1 3.0 1 20 a'=1; +a-none none 138 9 1 8 3.8 15 10 a'=6;b=1;a=1; +a-none none 139 5 1 4 3.2 10 25 a'=4; +a-none none 140 4 1 3 10.9 14 11 b=1;a'=1;a=1; +a-none none 141 4 1 3 4.7 1 4 a'=2;c=1; +a-none none 142 2 1 1 2.6 8 8 a=1; +a-none none 144 3 1 2 3.4 14 27 a'=2; +a-none none 146 1 1 0 3.6 10 15 +a-none none 145 1 1 0 3.5 3 10 +a-none none 143 6 1 5 3.0 2 19 a'=2;a=2;c=1; +a-none none 147 2 1 1 3.6 2 22 a'=1; +a-none none 148 2 1 1 3.0 11 13 a=1; +a-none none 149 2 1 1 3.7 15 8 a'=1; +a-none none 150 1 1 0 28.4 3 9 +a-none none 151 2 1 1 3.2 11 16 a'=1; +a-none none 152 2 1 1 11.6 13 19 a'=1; +a-none none 153 5 1 4 3.0 4 10 a'=4; +a-none none 154 3 1 2 3.1 11 15 a'=2; +a-none none 155 7 1 6 2.9 0 16 a'=3;a=3; +a-none none 156 2 1 1 5.6 13 4 a=1; +a-none none 157 2 1 1 2.6 12 14 a'=1; +a-none none 158 8 1 7 2.9 0 6 a'=6;a=1; +a-none none 159 1 1 0 3.4 12 24 +a-none none 160 2 1 1 2.7 0 7 a'=1; +a-none none 161 6 1 5 6.3 4 4 a'=5; +a-none none 162 3 1 2 4.5 13 24 a'=2; +a-none none 163 5 1 4 3.1 5 22 a'=4; +a-none none 164 3 1 2 2.5 4 22 a'=1;a=1; +a-none none 165 4 1 3 3.6 7 19 a'=3; +a-none none 166 8 1 7 3.6 4 8 a'=7; +a-none none 168 1 1 0 4.1 1 4 +a-none none 167 5 1 4 3.3 13 16 a'=3;a=1; +a-none none 169 1 1 0 3.5 5 5 +a-none none 170 3 1 2 3.0 15 12 c=1;a'=1; +a-none none 171 1 1 0 2.5 5 14 +a-none none 172 5 1 4 5.0 8 7 a'=3;a=1; +a-none none 173 4 1 3 2.9 11 24 a'=3; +a-none none 174 2 1 1 2.9 0 25 a=1; +a-none none 175 1 1 0 3.1 8 25 +a-none none 176 6 1 5 3.7 14 19 a'=4;a=1; +a-none none 177 1 1 0 2.6 4 24 +a-none none 179 1 1 0 2.7 0 7 +a-none none 180 1 1 0 3.5 13 12 +a-none none 181 3 1 2 2.9 6 11 a'=2; +a-none none 182 1 1 0 3.0 5 22 +a-none none 178 4 1 3 2.8 3 8 a'=2;c''=1; +a-none none 184 6 1 5 2.7 6 24 a'=4;b=1; +a-none none 183 3 1 2 3.4 12 5 a'=2; +a-none none 185 2 1 1 3.3 5 4 a'=1; +a-none none 186 1 1 0 15.3 1 26 +a-none none 187 6 1 5 2.7 14 17 a'=4;a=1; +a-none none 189 3 1 2 3.2 0 8 a'=2; +a-none none 191 2 1 1 2.8 6 14 a'=1; +a-none none 192 2 1 1 6.2 15 4 a'=1; +a-none none 193 1 1 0 3.6 12 17 +a-none none 190 4 1 3 3.1 11 24 c'''=1;b=1;a'=1; +a-none none 194 17 1 16 3.2 2 11 a'=10;b=3;c=2;a=1; +a-none none 195 2 1 1 3.2 5 24 a'=1; +a-none none 188 8 1 7 4.3 15 25 a'=5;c'''=1;c''=1; +a-none none 196 3 1 2 4.3 15 4 a'=2; +a-none none 197 2 1 1 4.0 15 4 a'=1; +a-none none 198 7 1 6 3.5 6 4 a'=5;b=1; +a-none none 199 1 1 0 3.2 4 8 +a-none none 200 10 1 9 3.1 4 8 a'=6;a=3; +a-none none 201 4 1 3 2.8 14 23 a'=3; +a-none none 202 3 1 2 4.8 0 12 a'=2; +a-none none 203 4 1 3 3.5 10 16 a'=3; +a-none none 204 2 1 1 2.8 7 6 a=1; +a-none none 205 1 1 0 2.8 11 10 +a-none none 206 11 1 10 3.5 2 17 a'=9;a=1; +a-none none 207 2 1 1 3.3 1 27 a'=1; +a-none none 208 4 1 3 3.5 9 11 a'=2;a=1; +a-none none 210 3 1 2 4.1 11 4 a'=2; +a-none none 209 12 1 11 3.0 12 19 a'=9;c=1;a=1; +a-none none 211 3 1 2 3.2 3 15 a'=1;a=1; +a-none none 212 4 1 3 3.5 1 17 a'=3; +a-none none 213 3 1 2 8.7 2 20 a'=2; +a-none none 215 2 1 1 3.6 4 19 a'=1; +a-none none 214 6 1 5 12.0 2 4 a'=5; +a-none none 216 2 1 1 3.3 10 25 a'=1; +a-none none 217 1 1 0 3.1 1 15 +a-none none 219 7 1 6 3.5 0 5 a'=6; +a-none none 220 1 1 0 2.9 6 13 +a-none none 218 3 1 2 2.9 0 20 c=1;a'=1; +a-none none 221 3 1 2 3.4 2 5 a'=2; +a-none none 223 1 1 0 3.0 8 9 +a-none none 224 3 1 2 3.0 9 27 a'=2; +a-none none 225 2 1 1 3.7 9 26 a'=1; +a-none none 226 1 1 0 30.2 14 16 +a-none none 222 5 1 4 2.6 5 6 a'=3;c'''=1; +a-none none 227 5 1 4 3.6 2 19 a'=4; +a-none none 228 1 1 0 3.0 13 4 +a-none none 229 1 1 0 2.9 12 24 +a-none none 231 4 1 3 2.7 15 17 a'=3; +a-none none 232 3 1 2 3.0 5 5 a'=2; +a-none none 233 1 1 0 4.6 13 4 +a-none none 234 1 1 0 2.9 10 17 +a-none none 235 1 1 0 4.0 0 25 +a-none none 230 9 1 8 5.6 3 5 a'=7;c''=1; +a-none none 236 1 1 0 2.8 4 24 +a-none none 237 4 1 3 3.3 5 18 a'=3; +a-none none 238 7 1 6 4.8 12 5 a'=5;a=1; +a-none none 239 1 1 0 3.7 1 22 +a-none none 240 1 1 0 5.0 6 4 +a-none none 241 11 1 10 5.6 2 4 a'=10; +a-none none 242 6 1 5 3.5 1 21 a'=5; +a-none none 243 1 1 0 3.2 1 22 +a-none none 244 3 1 2 3.2 8 5 a'=2; +a-none none 245 6 1 5 3.4 10 20 a'=5; +a-none none 247 2 1 1 4.3 6 4 a'=1; +a-none none 248 3 1 2 13.4 1 4 a'=2; +a-none none 249 1 1 0 4.1 2 27 +a-none none 250 2 1 1 3.1 8 19 a'=1; +a-none none 251 3 1 2 3.4 9 11 b=1;a'=1; +a-none none 246 4 1 3 4.0 11 5 a'=2;c'''=1; +a-none none 252 4 1 3 2.7 2 27 a'=2;a=1; +a-none none 253 3 1 2 3.5 12 25 a'=2; +a-none none 254 5 1 4 2.8 0 10 a'=4; +a-none none 255 1 1 0 3.1 10 8 +# end 2026-10-08T12:41:48Z rows=257 diff --git a/docs/analysis/class-v6/logs/census/b-era.tsv b/docs/analysis/class-v6/logs/census/b-era.tsv new file mode 100644 index 000000000..8b138d88e --- /dev/null +++ b/docs/analysis/class-v6/logs/census/b-era.tsv @@ -0,0 +1,259 @@ +# b-era class w16m8g+sh256x27 eras [0,1,2,3,4,5,6,7] seeds 32 era-widths 16 weights 13,11,6,10,8,8,7,2,6,4 bittest 1 bin d601098699840534 start 2026-10-08T12:58:31Z host igneum-build-3 threads 8 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +b-era 0 1 2 1 1 2.6 11 10 c,=1; +b-era 0 5 3 1 2 5.3 11 19 a'=2; +b-era 0 6 2 1 1 3.0 6 7 a'=1; +b-era 0 2 2 1 1 3.2 7 23 c,=1; +b-era 0 3 2 1 1 3.0 14 21 c,=1; +b-era 0 7 3 1 2 3.4 1 11 c,=1;a'=1; +b-era 0 0 5 1 4 3.7 15 25 c,=2;a'=2; +b-era 0 4 9 1 8 2.9 12 25 a'=5;c,=2;a=1; +b-era 0 9 2 1 1 3.3 15 21 c,=1; +b-era 0 8 1 1 0 3.1 7 15 +b-era 0 12 5 1 4 3.5 6 2 c,=2;a'=1;a=1; +b-era 0 11 9 1 8 3.2 6 22 c,=7;a'=1; +b-era 0 13 3 1 2 3.0 7 12 c,=1;a'=1; +b-era 0 14 6 1 5 3.2 10 26 a'=3;c,=2; +b-era 0 15 6 1 5 2.9 1 10 c,=3;a'=2; +b-era 0 10 10 1 9 2.9 7 19 c,=8;a=1; +b-era 0 16 1 1 0 3.9 7 22 +b-era 0 17 3 1 2 3.6 6 17 c,=1;a'=1; +b-era 0 18 2 1 1 5.1 12 21 c,=1; +b-era 0 19 1 1 0 3.0 1 13 +b-era 0 20 3 1 2 3.4 13 12 c,=1;a'=1; +b-era 0 21 4 1 3 3.5 9 15 a'=2;c,=1; +b-era 0 22 2 1 1 3.1 9 5 a'=1; +b-era 0 23 2 1 1 3.0 4 16 a=1; +b-era 0 24 1 1 0 3.0 1 15 +b-era 0 25 6 1 5 3.0 2 25 c,=4;a=1; +b-era 0 27 2 1 1 3.0 4 19 a'=1; +b-era 0 28 9 1 8 3.4 12 7 a'=4;c,=3;a=1; +b-era 0 29 2 1 1 3.6 1 3 c,=1; +b-era 0 26 11 1 10 3.3 1 5 c,=6;a'=3;c=1; +b-era 0 30 5 1 4 2.9 5 19 a'=3;a=1; +b-era 0 31 1 1 0 3.0 8 21 +b-era 1 0 5 1 4 3.2 14 24 c,=2;a'=2; +b-era 1 3 2 1 1 3.0 3 3 c,=1; +b-era 1 1 2 1 1 3.6 13 3 c,=1; +b-era 1 2 2 1 1 3.5 9 24 c,=1; +b-era 1 5 3 1 2 4.5 11 6 a'=2; +b-era 1 4 12 1 11 3.4 8 2 c,=5;a'=5;a=1; +b-era 1 6 2 1 1 3.1 2 12 a'=1; +b-era 1 7 3 1 2 3.1 6 16 c,=1;a'=1; +b-era 1 8 1 1 0 3.8 1 5 +b-era 1 9 2 1 1 2.8 15 21 c,=1; +b-era 1 11 9 1 8 2.7 15 16 c,=7;a'=1; +b-era 1 12 5 1 4 3.2 9 7 c,=2;a'=1;a=1; +b-era 1 10 10 1 9 3.2 2 12 c,=8;a=1; +b-era 1 14 6 1 5 2.9 6 4 a'=3;c,=2; +b-era 1 13 3 1 2 2.7 1 18 c,=1;a'=1; +b-era 1 15 6 1 5 3.6 4 3 c,=3;a'=2; +b-era 1 16 1 1 0 2.9 8 27 +b-era 1 17 3 1 2 2.6 12 2 c,=1;a'=1; +b-era 1 19 1 1 0 3.5 5 6 +b-era 1 20 3 1 2 3.2 11 20 c,=1;a'=1; +b-era 1 21 4 1 3 3.3 10 25 a'=2;c,=1; +b-era 1 18 3 1 2 2.7 1 23 c,=2; +b-era 1 22 2 1 1 3.1 8 3 a'=1; +b-era 1 23 2 1 1 2.9 15 4 a=1; +b-era 1 24 1 1 0 3.0 2 12 +b-era 1 27 2 1 1 3.9 2 19 a'=1; +b-era 1 25 6 1 5 2.9 4 13 c,=4;a=1; +b-era 1 28 9 1 8 2.7 12 8 a'=4;c,=3;a=1; +b-era 1 29 2 1 1 3.2 13 5 c,=1; +b-era 1 30 5 1 4 3.0 6 12 a'=3;a=1; +b-era 1 26 11 1 10 3.3 10 12 c,=6;a'=3;c=1; +b-era 1 31 1 1 0 3.7 0 17 +b-era 2 0 2 1 1 3.2 6 17 a'=1; +b-era 2 1 1 1 0 4.0 5 10 +b-era 2 3 2 1 1 3.7 0 18 c,=1; +b-era 2 2 1 1 0 3.1 2 23 +b-era 2 4 1 1 0 3.2 7 5 +b-era 2 6 2 1 1 3.5 5 11 a'=1; +b-era 2 5 3 1 2 3.5 5 19 a'=2; +b-era 2 7 1 1 0 2.9 11 18 +b-era 2 8 1 1 0 3.0 10 19 +b-era 2 9 1 1 0 3.3 1 18 +b-era 2 11 1 1 0 2.8 11 3 +b-era 2 10 1 1 0 3.4 0 16 +b-era 2 12 2 1 1 3.6 1 25 a'=1; +b-era 2 13 1 1 0 3.4 4 20 +b-era 2 14 1 1 0 3.3 3 9 +b-era 2 15 2 1 1 3.1 12 9 a'=1; +b-era 2 16 1 1 0 2.5 6 19 +b-era 2 18 1 1 0 3.1 1 15 +b-era 2 17 2 1 1 4.0 10 19 a'=1; +b-era 2 20 1 1 0 4.9 5 3 +b-era 2 19 1 1 0 2.9 2 20 +b-era 2 21 3 1 2 2.5 7 15 a'=2; +b-era 2 22 2 1 1 2.9 3 14 a'=1; +b-era 2 23 2 1 1 3.0 7 22 a=1; +b-era 2 24 1 1 0 3.0 2 24 +b-era 2 25 1 1 0 2.9 2 23 +b-era 2 27 2 1 1 3.1 15 9 a'=1; +b-era 2 26 1 1 0 3.7 6 15 +b-era 2 28 5 1 4 3.4 12 20 a'=3;a=1; +b-era 2 29 1 1 0 3.8 2 9 +b-era 2 30 5 1 4 3.2 5 10 a'=3;a=1; +b-era 2 31 1 1 0 3.5 3 25 +b-era 3 0 2 1 1 3.2 2 8 a'=1; +b-era 3 1 1 1 0 3.2 15 13 +b-era 3 4 6 1 5 3.4 9 23 a'=4;c,=1; +b-era 3 3 2 1 1 4.1 11 4 c,=1; +b-era 3 2 1 1 0 2.9 8 5 +b-era 3 5 3 1 2 5.0 11 3 a'=2; +b-era 3 6 2 1 1 3.3 3 22 a'=1; +b-era 3 7 1 1 0 3.1 2 18 +b-era 3 9 1 1 0 2.9 1 4 +b-era 3 8 1 1 0 3.0 10 16 +b-era 3 11 1 1 0 3.6 2 15 +b-era 3 12 2 1 1 3.2 14 14 a'=1; +b-era 3 10 1 1 0 3.0 4 12 +b-era 3 13 1 1 0 3.3 10 8 +b-era 3 14 1 1 0 2.8 0 16 +b-era 3 15 2 1 1 4.5 14 2 a'=1; +b-era 3 16 1 1 0 3.0 1 21 +b-era 3 17 2 1 1 3.1 14 2 a'=1; +b-era 3 18 1 1 0 3.2 10 20 +b-era 3 19 1 1 0 2.7 14 25 +b-era 3 20 3 1 2 3.1 12 24 c,=1;a'=1; +b-era 3 21 3 1 2 4.5 12 8 a'=2; +b-era 3 22 2 1 1 2.6 11 11 a'=1; +b-era 3 23 2 1 1 2.9 2 18 a=1; +b-era 3 24 1 1 0 3.4 13 16 +b-era 3 25 1 1 0 3.9 2 7 +b-era 3 26 1 1 0 2.7 0 23 +b-era 3 28 5 1 4 3.4 2 25 a'=3;a=1; +b-era 3 27 2 1 1 2.9 13 2 a'=1; +b-era 3 29 1 1 0 3.3 11 17 +b-era 3 30 5 1 4 3.7 0 19 a'=3;a=1; +b-era 3 31 1 1 0 2.8 10 21 +b-era 4 0 5 1 4 3.0 15 8 c,=2;a'=2; +b-era 4 1 2 1 1 3.0 10 15 c,=1; +b-era 4 3 2 1 1 4.0 13 21 c,=1; +b-era 4 2 2 1 1 3.0 7 19 c,=1; +b-era 4 4 9 1 8 2.7 6 7 a'=5;c,=2;a=1; +b-era 4 5 3 1 2 4.3 11 10 a'=2; +b-era 4 6 2 1 1 3.1 3 11 a'=1; +b-era 4 7 3 1 2 4.1 7 9 c,=1;a'=1; +b-era 4 8 1 1 0 3.2 9 19 +b-era 4 9 2 1 1 2.7 6 10 c,=1; +b-era 4 12 5 1 4 2.7 8 24 c,=2;a'=1;a=1; +b-era 4 11 9 1 8 4.0 9 19 c,=7;a'=1; +b-era 4 10 10 1 9 3.1 12 12 c,=8;a=1; +b-era 4 13 3 1 2 2.5 3 8 c,=1;a'=1; +b-era 4 14 6 1 5 2.7 13 23 a'=3;c,=2; +b-era 4 15 6 1 5 3.5 9 13 c,=3;a'=2; +b-era 4 16 1 1 0 3.6 0 6 +b-era 4 17 3 1 2 3.7 6 6 c,=1;a'=1; +b-era 4 18 3 1 2 3.5 1 22 c,=2; +b-era 4 20 3 1 2 3.1 3 21 c,=1;a'=1; +b-era 4 19 1 1 0 3.4 12 13 +b-era 4 21 4 1 3 3.2 6 17 a'=2;c,=1; +b-era 4 22 2 1 1 3.1 10 3 a'=1; +b-era 4 23 2 1 1 3.7 1 9 a=1; +b-era 4 24 1 1 0 2.8 6 6 +b-era 4 25 6 1 5 2.8 12 21 c,=4;a=1; +b-era 4 27 2 1 1 3.3 0 12 a'=1; +b-era 4 28 9 1 8 3.9 6 20 a'=4;c,=3;a=1; +b-era 4 26 11 1 10 3.1 10 10 c,=6;a'=3;c=1; +b-era 4 29 2 1 1 2.9 10 20 c,=1; +b-era 4 30 5 1 4 3.5 14 23 a'=3;a=1; +b-era 4 31 1 1 0 2.6 10 11 +b-era 5 0 5 1 4 3.4 4 19 c,=2;a'=2; +b-era 5 1 2 1 1 2.5 8 25 c,=1; +b-era 5 2 2 1 1 3.1 11 25 c,=1; +b-era 5 3 2 1 1 3.5 14 25 c,=1; +b-era 5 4 9 1 8 3.7 15 22 a'=5;c,=2;a=1; +b-era 5 5 3 1 2 5.2 11 23 a'=2; +b-era 5 6 2 1 1 3.1 6 22 a'=1; +b-era 5 7 3 1 2 3.0 8 11 c,=1;a'=1; +b-era 5 8 1 1 0 3.8 9 18 +b-era 5 9 2 1 1 4.0 13 2 c,=1; +b-era 5 10 10 1 9 2.8 5 7 c,=8;a=1; +b-era 5 11 9 1 8 3.2 13 13 c,=7;a'=1; +b-era 5 12 5 1 4 3.3 3 25 c,=2;a'=1;a=1; +b-era 5 13 3 1 2 3.2 12 26 c,=1;a'=1; +b-era 5 14 6 1 5 3.3 10 22 a'=3;c,=2; +b-era 5 15 6 1 5 3.2 5 2 c,=3;a'=2; +b-era 5 16 1 1 0 3.1 4 26 +b-era 5 17 3 1 2 3.3 7 27 c,=1;a'=1; +b-era 5 18 3 1 2 3.2 1 12 c,=2; +b-era 5 19 1 1 0 3.3 3 22 +b-era 5 20 3 1 2 2.7 7 11 c,=1;a'=1; +b-era 5 21 4 1 3 3.7 3 15 a'=2;c,=1; +b-era 5 22 2 1 1 4.1 3 5 a'=1; +b-era 5 23 2 1 1 3.5 2 19 a=1; +b-era 5 24 1 1 0 2.7 5 8 +b-era 5 27 2 1 1 3.0 1 6 a'=1; +b-era 5 25 6 1 5 3.0 4 23 c,=4;a=1; +b-era 5 26 11 1 10 2.5 8 24 c,=6;a'=3;c=1; +b-era 5 29 2 1 1 3.0 3 3 c,=1; +b-era 5 28 9 1 8 3.3 1 21 a'=4;c,=3;a=1; +b-era 5 30 5 1 4 3.2 10 8 a'=3;a=1; +b-era 5 31 1 1 0 3.6 10 4 +b-era 6 0 5 1 4 2.4 10 11 c,=2;a'=2; +b-era 6 1 2 1 1 3.5 15 18 c,=1; +b-era 6 2 2 1 1 3.3 1 9 c,=1; +b-era 6 4 9 1 8 3.1 1 7 a'=5;c,=2;a=1; +b-era 6 3 2 1 1 3.0 12 18 c,=1; +b-era 6 5 3 1 2 4.1 11 5 a'=2; +b-era 6 6 2 1 1 3.2 1 20 a'=1; +b-era 6 7 3 1 2 2.8 3 22 c,=1;a'=1; +b-era 6 8 1 1 0 3.8 3 20 +b-era 6 9 2 1 1 2.9 6 18 c,=1; +b-era 6 14 6 1 5 3.2 2 5 a'=3;c,=2; +b-era 6 13 3 1 2 3.8 5 10 c,=1;a'=1; +b-era 6 10 10 1 9 3.2 2 24 c,=8;a=1; +b-era 6 12 5 1 4 3.1 3 17 c,=2;a'=1;a=1; +b-era 6 11 9 1 8 3.2 8 11 c,=7;a'=1; +b-era 6 15 6 1 5 2.9 12 13 c,=3;a'=2; +b-era 6 16 1 1 0 3.5 8 3 +b-era 6 17 3 1 2 3.8 15 5 c,=1;a'=1; +b-era 6 21 4 1 3 3.8 4 21 a'=2;c,=1; +b-era 6 20 3 1 2 2.9 15 10 c,=1;a'=1; +b-era 6 18 3 1 2 3.2 14 20 c,=2; +b-era 6 19 1 1 0 3.3 10 3 +b-era 6 22 2 1 1 3.5 0 11 a'=1; +b-era 6 23 2 1 1 2.9 11 20 a=1; +b-era 6 24 1 1 0 3.2 0 16 +b-era 6 25 6 1 5 3.0 14 24 c,=4;a=1; +b-era 6 29 2 1 1 3.0 14 5 c,=1; +b-era 6 27 2 1 1 4.2 0 2 a'=1; +b-era 6 26 11 1 10 3.5 12 6 c,=6;a'=3;c=1; +b-era 6 30 5 1 4 3.7 0 14 a'=3;a=1; +b-era 6 28 9 1 8 3.4 15 25 a'=4;c,=3;a=1; +b-era 6 31 1 1 0 3.1 2 20 +b-era 7 0 2 1 1 2.9 13 20 a'=1; +b-era 7 1 1 1 0 3.4 12 23 +b-era 7 3 2 1 1 3.0 13 18 c,=1; +b-era 7 2 2 1 1 2.9 4 9 c,=1; +b-era 7 4 1 1 0 5.1 0 3 +b-era 7 6 2 1 1 3.2 10 3 a'=1; +b-era 7 5 3 1 2 3.1 1 9 a'=2; +b-era 7 7 1 1 0 3.0 4 8 +b-era 7 8 1 1 0 3.4 15 20 +b-era 7 9 2 1 1 3.8 10 23 c,=1; +b-era 7 11 1 1 0 3.2 7 23 +b-era 7 10 1 1 0 3.2 10 26 +b-era 7 12 2 1 1 3.4 6 13 a'=1; +b-era 7 13 3 1 2 3.0 4 4 c,=1;a'=1; +b-era 7 14 1 1 0 3.0 1 27 +b-era 7 15 6 1 5 2.9 5 11 c,=3;a'=2; +b-era 7 16 1 1 0 2.9 0 23 +b-era 7 17 2 1 1 3.2 11 14 a'=1; +b-era 7 18 2 1 1 3.4 5 24 c,=1; +b-era 7 20 1 1 0 3.1 6 14 +b-era 7 19 1 1 0 2.6 8 10 +b-era 7 21 4 1 3 3.2 2 19 a'=2;c,=1; +b-era 7 22 2 1 1 3.6 3 3 a'=1; +b-era 7 23 2 1 1 3.4 14 20 a=1; +b-era 7 24 1 1 0 2.6 10 15 +b-era 7 25 1 1 0 2.7 2 12 +b-era 7 26 7 1 6 3.0 2 3 c,=3;a'=2;c=1; +b-era 7 27 2 1 1 3.0 12 8 a'=1; +b-era 7 28 5 1 4 3.1 0 11 a'=3;a=1; +b-era 7 29 1 1 0 2.8 8 27 +b-era 7 30 5 1 4 3.8 11 25 a'=3;a=1; +b-era 7 31 1 1 0 3.3 10 25 +# end 2026-10-08T13:01:58Z rows=257 diff --git a/docs/analysis/class-v6/logs/census/b-none.tsv b/docs/analysis/class-v6/logs/census/b-none.tsv new file mode 100644 index 000000000..3a6f5f611 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/b-none.tsv @@ -0,0 +1,258 @@ +# b-none class w16m8g+sh256x27 eras [none] seeds 256 era-widths 16 weights 13,11,6,10,8,8,7,2,6,4 bittest off bin d601098699840534 start 2026-10-08T12:45:53Z host igneum-build-4 threads 16 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +b-none none 0 2 1 1 3.9 11 3 a'=1; +b-none none 2 5 1 4 3.4 15 18 a'=3;a=1; +b-none none 11 1 1 0 2.7 8 6 +b-none none 12 1 1 0 3.4 13 11 +b-none none 13 1 1 0 3.3 15 16 +b-none none 14 1 1 0 16.0 11 2 +b-none none 15 2 1 1 3.7 0 27 a'=1; +b-none none 1 1 1 0 3.3 14 3 +b-none none 17 1 1 0 20.1 10 2 +b-none none 16 4 1 3 3.6 10 23 a'=3; +b-none none 18 1 1 0 3.0 8 24 +b-none none 10 1 1 0 2.9 8 10 +b-none none 19 1 1 0 23.6 4 2 +b-none none 6 2 1 1 16.2 2 2 c=1; +b-none none 4 2 1 1 3.2 13 26 a'=1; +b-none none 5 1 1 0 2.5 15 9 +b-none none 8 2 1 1 5.0 2 17 a'=1; +b-none none 7 1 1 0 15.8 0 2 +b-none none 9 4 1 3 57.7 2 10 a'=2;a=1; +b-none none 3 1 1 0 16.4 9 2 +b-none none 22 1 1 0 31.0 5 23 +b-none none 23 2 1 1 7.0 3 2 a'=1; +b-none none 28 1 1 0 2.8 2 20 +b-none none 24 2 1 1 3.2 13 3 a'=1; +b-none none 30 3 1 2 9.8 0 4 a'=1;a=1; +b-none none 25 1 1 0 3.9 0 19 +b-none none 20 1 1 0 19.1 10 2 +b-none none 29 3 1 2 2.9 12 12 a'=2; +b-none none 21 4 1 3 3.2 15 12 a'=3; +b-none none 27 3 1 2 3.2 11 17 c=1;b=1; +b-none none 36 1 1 0 3.3 2 21 +b-none none 40 1 1 0 3.5 12 3 +b-none none 42 1 1 0 3.0 7 23 +b-none none 31 4 1 3 2.9 15 11 a'=3; +b-none none 26 1 1 0 9.0 10 2 +b-none none 34 2 1 1 3.0 14 11 a=1; +b-none none 32 1 1 0 2.8 4 2 +b-none none 33 2 1 1 28.7 1 19 a=1; +b-none none 35 2 1 1 29.4 2 2 a'=1; +b-none none 37 2 1 1 3.5 4 13 a'=1; +b-none none 48 2 1 1 3.0 10 22 a'=1; +b-none none 39 1 1 0 2.9 7 10 +b-none none 38 1 1 0 10.7 3 27 +b-none none 43 2 1 1 3.0 1 18 a'=1; +b-none none 41 2 1 1 3.9 0 2 a'=1; +b-none none 44 1 1 0 3.0 10 12 +b-none none 45 1 1 0 17.7 15 2 +b-none none 46 2 1 1 71.0 2 23 a'=1; +b-none none 51 2 1 1 3.3 9 11 a'=1; +b-none none 47 2 1 1 11.8 13 2 a'=1; +b-none none 50 1 1 0 41.5 3 2 +b-none none 56 1 1 0 3.3 15 3 +b-none none 49 2 1 1 3.1 4 10 a'=1; +b-none none 55 1 1 0 16.4 3 2 +b-none none 61 3 1 2 17.9 12 2 a'=2; +b-none none 52 1 1 0 17.6 8 2 +b-none none 54 5 1 4 3.8 1 3 a'=2;c'''=1;a=1; +b-none none 63 2 1 1 17.3 6 2 a'=1; +b-none none 57 1 1 0 3.4 3 15 +b-none none 59 1 1 0 2.8 15 21 +b-none none 68 2 1 1 15.5 1 2 a'=1; +b-none none 67 1 1 0 9.5 3 2 +b-none none 58 1 1 0 2.9 10 16 +b-none none 70 1 1 0 4.2 12 2 +b-none none 69 2 1 1 16.8 13 2 a=1; +b-none none 71 1 1 0 2.9 9 18 +b-none none 74 1 1 0 6.5 12 2 +b-none none 53 2 1 1 3.0 14 16 c''=1; +b-none none 62 1 1 0 15.5 11 2 +b-none none 64 1 1 0 3.2 10 23 +b-none none 60 2 1 1 3.7 12 18 a'=1; +b-none none 65 1 1 0 3.0 9 15 +b-none none 72 3 1 2 3.8 5 21 c'''=1;a'=1; +b-none none 76 6 1 5 7.2 0 15 a'=4;a=1; +b-none none 66 2 1 1 39.1 10 2 a=1; +b-none none 81 2 1 1 64.0 6 25 a'=1; +b-none none 73 1 1 0 3.0 13 5 +b-none none 82 1 1 0 2.6 5 8 +b-none none 84 1 1 0 3.5 5 6 +b-none none 75 1 1 0 3.7 5 18 +b-none none 85 1 1 0 3.3 2 26 +b-none none 83 1 1 0 3.1 15 26 +b-none none 86 1 1 0 3.7 7 16 +b-none none 87 1 1 0 32.3 9 10 +b-none none 79 1 1 0 17.5 8 2 +b-none none 80 1 1 0 3.0 8 6 +b-none none 78 1 1 0 2.7 5 18 +b-none none 92 1 1 0 8.6 7 2 +b-none none 91 1 1 0 15.2 12 2 +b-none none 90 2 1 1 3.0 7 18 c''=1; +b-none none 88 1 1 0 3.1 14 18 +b-none none 89 2 1 1 3.6 5 3 a'=1; +b-none none 77 3 1 2 2.8 14 17 c''=1;a=1; +b-none none 97 1 1 0 2.8 4 22 +b-none none 96 1 1 0 2.9 3 17 +b-none none 99 2 1 1 2.8 4 21 c''=1; +b-none none 93 1 1 0 4.0 4 11 +b-none none 103 1 1 0 16.4 8 2 +b-none none 105 1 1 0 3.6 12 14 +b-none none 111 1 1 0 2.8 7 3 +b-none none 98 1 1 0 56.0 0 5 +b-none none 94 1 1 0 16.4 5 2 +b-none none 114 2 1 1 3.4 11 23 c=1; +b-none none 95 2 1 1 3.5 8 19 a'=1; +b-none none 113 1 1 0 13.4 12 2 +b-none none 100 1 1 0 5.0 1 26 +b-none none 107 3 1 2 3.2 10 17 a'=2; +b-none none 101 2 1 1 4.4 11 2 c''=1; +b-none none 104 1 1 0 3.2 15 19 +b-none none 102 1 1 0 16.2 9 2 +b-none none 106 1 1 0 4.7 3 2 +b-none none 118 2 1 1 15.5 9 2 a=1; +b-none none 117 1 1 0 3.1 12 8 +b-none none 121 1 1 0 7.1 5 19 +b-none none 122 1 1 0 15.1 2 2 +b-none none 112 2 1 1 13.2 7 2 a'=1; +b-none none 108 1 1 0 65.3 15 10 +b-none none 110 2 1 1 3.0 3 22 a'=1; +b-none none 109 1 1 0 3.5 12 25 +b-none none 124 1 1 0 3.1 12 19 +b-none none 119 1 1 0 5.6 9 3 +b-none none 123 1 1 0 18.2 13 17 +b-none none 128 6 1 5 3.0 13 16 a'=3;c=1;a=1; +b-none none 130 1 1 0 14.7 10 2 +b-none none 126 1 1 0 8.7 0 11 +b-none none 115 1 1 0 3.6 10 4 +b-none none 116 2 1 1 3.8 2 9 a'=1; +b-none none 120 2 1 1 17.0 13 2 a'=1; +b-none none 131 1 1 0 2.7 12 9 +b-none none 132 1 1 0 3.3 5 19 +b-none none 133 3 1 2 14.1 11 2 a'=2; +b-none none 139 3 1 2 36.4 4 2 a'=2; +b-none none 129 1 1 0 2.9 11 8 +b-none none 125 1 1 0 3.1 7 7 +b-none none 142 2 1 1 14.4 5 2 c=1; +b-none none 136 1 1 0 64.4 6 2 +b-none none 144 1 1 0 3.5 4 18 +b-none none 141 2 1 1 3.1 6 20 a'=1; +b-none none 135 2 1 1 2.8 8 6 a'=1; +b-none none 134 4 1 3 3.2 6 7 a'=3; +b-none none 150 1 1 0 27.8 3 9 +b-none none 151 1 1 0 15.6 1 2 +b-none none 137 2 1 1 3.1 10 18 a'=1; +b-none none 152 2 1 1 3.1 3 13 a'=1; +b-none none 127 4 1 3 15.5 14 2 a'=2;c'''=1; +b-none none 138 1 1 0 2.7 4 16 +b-none none 146 1 1 0 6.2 8 2 +b-none none 140 4 1 3 4.9 13 19 b=1;a'=1;a=1; +b-none none 155 1 1 0 14.5 0 2 +b-none none 145 1 1 0 11.7 9 2 +b-none none 149 2 1 1 8.5 11 2 a'=1; +b-none none 147 4 1 3 2.6 0 25 a'=3; +b-none none 159 1 1 0 5.8 3 2 +b-none none 148 2 1 1 3.5 8 24 a=1; +b-none none 154 1 1 0 3.1 2 27 +b-none none 161 4 1 3 3.3 13 19 a'=3; +b-none none 162 1 1 0 7.2 0 2 +b-none none 143 3 1 2 19.4 1 6 c''=1;a=1; +b-none none 163 1 1 0 16.6 12 2 +b-none none 164 1 1 0 16.5 14 2 +b-none none 165 1 1 0 3.1 0 2 +b-none none 166 4 1 3 2.9 13 3 a'=3; +b-none none 153 1 1 0 3.0 8 22 +b-none none 167 2 1 1 2.8 11 26 a=1; +b-none none 160 2 1 1 2.7 2 24 a'=1; +b-none none 158 1 1 0 3.2 1 24 +b-none none 172 1 1 0 17.1 2 2 +b-none none 157 1 1 0 3.7 13 15 +b-none none 176 3 1 2 2.8 2 16 a'=1;a=1; +b-none none 173 3 1 2 3.1 13 11 a'=2; +b-none none 156 2 1 1 3.1 8 19 a=1; +b-none none 171 1 1 0 3.2 9 9 +b-none none 174 1 1 0 5.9 2 27 +b-none none 168 1 1 0 7.2 1 2 +b-none none 175 1 1 0 3.1 13 22 +b-none none 170 1 1 0 18.0 9 2 +b-none none 169 3 1 2 2.9 6 11 c''=1;a'=1; +b-none none 189 2 1 1 16.0 5 2 a'=1; +b-none none 187 1 1 0 63.9 13 15 +b-none none 181 4 1 3 3.4 5 26 a'=3; +b-none none 183 1 1 0 17.5 5 2 +b-none none 182 1 1 0 34.2 4 18 +b-none none 179 1 1 0 3.2 0 9 +b-none none 178 2 1 1 3.2 3 25 a'=1; +b-none none 177 1 1 0 3.1 14 15 +b-none none 186 1 1 0 14.8 5 2 +b-none none 180 2 1 1 3.4 0 18 a'=1; +b-none none 190 4 1 3 5.4 0 2 a'=2;c'''=1; +b-none none 184 3 1 2 7.8 8 2 a'=2; +b-none none 193 1 1 0 4.8 14 2 +b-none none 194 2 1 1 16.8 12 2 c=1; +b-none none 196 2 1 1 3.0 6 23 a'=1; +b-none none 188 4 1 3 5.7 8 9 a'=2;c''=1; +b-none none 200 1 1 0 3.0 15 21 +b-none none 195 1 1 0 2.9 2 6 +b-none none 205 1 1 0 3.4 10 4 +b-none none 185 2 1 1 12.7 5 2 c''=1; +b-none none 201 1 1 0 15.5 9 2 +b-none none 191 2 1 1 3.3 8 4 a'=1; +b-none none 192 1 1 0 15.1 7 2 +b-none none 204 2 1 1 4.4 9 18 c=1; +b-none none 198 1 1 0 2.7 11 22 +b-none none 199 1 1 0 3.1 1 8 +b-none none 197 4 1 3 3.2 5 12 a'=3; +b-none none 202 1 1 0 3.0 13 27 +b-none none 208 1 1 0 3.9 0 26 +b-none none 210 1 1 0 5.6 9 2 +b-none none 215 2 1 1 3.1 8 16 a'=1; +b-none none 206 6 1 5 10.1 5 13 a'=4;a=1; +b-none none 214 2 1 1 3.0 1 15 b=1; +b-none none 203 4 1 3 5.3 9 16 a'=3; +b-none none 207 1 1 0 2.9 6 10 +b-none none 217 1 1 0 3.8 15 27 +b-none none 216 2 1 1 3.4 13 16 c'''=1; +b-none none 221 2 1 1 15.7 8 2 a'=1; +b-none none 212 2 1 1 3.3 2 19 a'=1; +b-none none 213 1 1 0 9.4 2 2 +b-none none 220 1 1 0 12.0 13 2 +b-none none 222 1 1 0 11.9 6 19 +b-none none 219 1 1 0 4.4 9 5 +b-none none 209 3 1 2 2.8 5 4 c''=1;c=1; +b-none none 224 3 1 2 3.2 7 23 a'=2; +b-none none 226 1 1 0 31.0 14 16 +b-none none 211 3 1 2 3.4 8 7 c''=1;a=1; +b-none none 228 1 1 0 2.8 3 11 +b-none none 218 3 1 2 2.8 1 15 c=1;a'=1; +b-none none 227 1 1 0 7.1 15 2 +b-none none 223 1 1 0 2.9 1 2 +b-none none 231 1 1 0 5.2 3 20 +b-none none 225 1 1 0 3.0 5 11 +b-none none 230 1 1 0 3.0 11 18 +b-none none 233 1 1 0 16.0 13 2 +b-none none 234 3 1 2 28.7 2 2 a'=2; +b-none none 232 1 1 0 16.1 7 2 +b-none none 235 1 1 0 11.3 3 2 +b-none none 236 1 1 0 9.2 13 2 +b-none none 238 1 1 0 3.1 8 11 +b-none none 229 1 1 0 3.3 12 19 +b-none none 242 1 1 0 3.0 0 13 +b-none none 239 1 1 0 3.0 2 27 +b-none none 240 1 1 0 15.4 6 2 +b-none none 241 1 1 0 15.4 4 2 +b-none none 245 2 1 1 3.0 3 13 a'=1; +b-none none 243 1 1 0 5.8 0 3 +b-none none 237 1 1 0 17.1 5 2 +b-none none 247 1 1 0 3.0 15 22 +b-none none 244 1 1 0 10.5 10 2 +b-none none 249 1 1 0 7.1 0 2 +b-none none 250 1 1 0 3.0 6 5 +b-none none 248 1 1 0 3.2 1 15 +b-none none 252 4 1 3 3.0 13 26 a'=2;a=1; +b-none none 253 1 1 0 3.1 0 12 +b-none none 251 5 1 4 6.3 0 2 a'=2;c''=1;b=1; +b-none none 254 1 1 0 10.5 4 16 +b-none none 255 1 1 0 3.1 6 16 +b-none none 246 4 1 3 11.3 11 2 c''=2;a'=1; diff --git a/docs/analysis/class-v6/logs/census/bench.log b/docs/analysis/class-v6/logs/census/bench.log new file mode 100644 index 000000000..e32c9def4 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/bench.log @@ -0,0 +1,95 @@ +lease: 0 of 1 pool cores free (88 leased); waiting +lease: holding 1 pool cores (18, waited 804 s, class measure): class v6 census: verifier bench per candidate, one core +# bench start 2026-10-08T12:55:00Z host igneum-build-4 cores 18 bin d601098699840534 +== ctrl rep 1 class mx8+sh256x27 weights base +warp base 0: single cold run 9.956 ms, 4096 items derived, lane0 2fc898410932f9e3 lane31 46d6a126c7aa1def +warp base 4096: single cold run 9.650 ms, 4096 items derived, lane0 7a977c3ed95fd05a lane31 2845370fe23e9cbc +warp base 1000000: single cold run 9.576 ms, 4096 items derived, lane0 7ec39eb3571dd232 lane31 a96c22d96855eaaf +CPU verify: 9.550 ms per 32-lane warp, avg of 20 (checksum 0e89d7e40db622e9) +== ctrl rep 2 class mx8+sh256x27 weights base +warp base 0: single cold run 9.835 ms, 4096 items derived, lane0 2fc898410932f9e3 lane31 46d6a126c7aa1def +warp base 4096: single cold run 9.602 ms, 4096 items derived, lane0 7a977c3ed95fd05a lane31 2845370fe23e9cbc +warp base 1000000: single cold run 9.590 ms, 4096 items derived, lane0 7ec39eb3571dd232 lane31 a96c22d96855eaaf +CPU verify: 9.543 ms per 32-lane warp, avg of 20 (checksum 0e89d7e40db622e9) +== ctrl rep 3 class mx8+sh256x27 weights base +warp base 0: single cold run 9.959 ms, 4096 items derived, lane0 2fc898410932f9e3 lane31 46d6a126c7aa1def +warp base 4096: single cold run 9.649 ms, 4096 items derived, lane0 7a977c3ed95fd05a lane31 2845370fe23e9cbc +warp base 1000000: single cold run 9.607 ms, 4096 items derived, lane0 7ec39eb3571dd232 lane31 a96c22d96855eaaf +CPU verify: 9.677 ms per 32-lane warp, avg of 20 (checksum 0e89d7e40db622e9) +== w16 rep 1 class w16m8g+sh256x27 weights base +warp base 0: single cold run 9.520 ms, 4096 items derived, lane0 86246a72110d1bdb lane31 9624ff67d32d0143 +warp base 4096: single cold run 9.607 ms, 4096 items derived, lane0 58a778388ac864f7 lane31 3971533d5d207c9a +warp base 1000000: single cold run 9.587 ms, 4096 items derived, lane0 25a14bccb7b1307b lane31 939807ae42c54b17 +CPU verify: 9.648 ms per 32-lane warp, avg of 20 (checksum 042c4aa1de6d950e) +== w16 rep 2 class w16m8g+sh256x27 weights base +warp base 0: single cold run 10.004 ms, 4096 items derived, lane0 86246a72110d1bdb lane31 9624ff67d32d0143 +warp base 4096: single cold run 9.839 ms, 4096 items derived, lane0 58a778388ac864f7 lane31 3971533d5d207c9a +warp base 1000000: single cold run 9.746 ms, 4096 items derived, lane0 25a14bccb7b1307b lane31 939807ae42c54b17 +CPU verify: 9.421 ms per 32-lane warp, avg of 20 (checksum 042c4aa1de6d950e) +== w16 rep 3 class w16m8g+sh256x27 weights base +warp base 0: single cold run 9.722 ms, 4096 items derived, lane0 86246a72110d1bdb lane31 9624ff67d32d0143 +warp base 4096: single cold run 9.468 ms, 4096 items derived, lane0 58a778388ac864f7 lane31 3971533d5d207c9a +warp base 1000000: single cold run 9.469 ms, 4096 items derived, lane0 25a14bccb7b1307b lane31 939807ae42c54b17 +CPU verify: 9.450 ms per 32-lane warp, avg of 20 (checksum 042c4aa1de6d950e) +== a rep 1 class w64m8g+sh256x27 weights base +warp base 0: single cold run 9.697 ms, 4096 items derived, lane0 256f099baec10276 lane31 bf2cf1eaa6860226 +warp base 4096: single cold run 9.469 ms, 4096 items derived, lane0 0566cfce49f016a7 lane31 29c0d372bb080cb4 +warp base 1000000: single cold run 9.444 ms, 4096 items derived, lane0 e2e4a79baa3d476b lane31 8d41a0d34c9a9988 +CPU verify: 9.477 ms per 32-lane warp, avg of 20 (checksum abd5e098a8b332df) +== a rep 2 class w64m8g+sh256x27 weights base +warp base 0: single cold run 10.134 ms, 4096 items derived, lane0 256f099baec10276 lane31 bf2cf1eaa6860226 +warp base 4096: single cold run 9.666 ms, 4096 items derived, lane0 0566cfce49f016a7 lane31 29c0d372bb080cb4 +warp base 1000000: single cold run 9.831 ms, 4096 items derived, lane0 e2e4a79baa3d476b lane31 8d41a0d34c9a9988 +CPU verify: 9.751 ms per 32-lane warp, avg of 20 (checksum abd5e098a8b332df) +== a rep 3 class w64m8g+sh256x27 weights base +warp base 0: single cold run 9.949 ms, 4096 items derived, lane0 256f099baec10276 lane31 bf2cf1eaa6860226 +warp base 4096: single cold run 9.665 ms, 4096 items derived, lane0 0566cfce49f016a7 lane31 29c0d372bb080cb4 +warp base 1000000: single cold run 9.731 ms, 4096 items derived, lane0 e2e4a79baa3d476b lane31 8d41a0d34c9a9988 +CPU verify: 9.703 ms per 32-lane warp, avg of 20 (checksum abd5e098a8b332df) +== b rep 1 class w16m8g+sh256x27 weights 13,11,6,10,8,8,7,2,6,4 +warp base 0: single cold run 9.843 ms, 4096 items derived, lane0 7f0a9d0730f4f729 lane31 c01afb20069e0408 +warp base 4096: single cold run 9.607 ms, 4096 items derived, lane0 09d0e2b984e04fad lane31 2e59642314e381b7 +warp base 1000000: single cold run 9.650 ms, 4096 items derived, lane0 a4697a4c254a61a7 lane31 3cc24e96c299c61d +CPU verify: 9.616 ms per 32-lane warp, avg of 20 (checksum 7e659be3d18245a4) +== b rep 2 class w16m8g+sh256x27 weights 13,11,6,10,8,8,7,2,6,4 +warp base 0: single cold run 9.277 ms, 4096 items derived, lane0 7f0a9d0730f4f729 lane31 c01afb20069e0408 +warp base 4096: single cold run 8.567 ms, 4096 items derived, lane0 09d0e2b984e04fad lane31 2e59642314e381b7 +warp base 1000000: single cold run 8.582 ms, 4096 items derived, lane0 a4697a4c254a61a7 lane31 3cc24e96c299c61d +CPU verify: 8.598 ms per 32-lane warp, avg of 20 (checksum 7e659be3d18245a4) +== b rep 3 class w16m8g+sh256x27 weights 13,11,6,10,8,8,7,2,6,4 +warp base 0: single cold run 8.619 ms, 4096 items derived, lane0 7f0a9d0730f4f729 lane31 c01afb20069e0408 +warp base 4096: single cold run 8.234 ms, 4096 items derived, lane0 09d0e2b984e04fad lane31 2e59642314e381b7 +warp base 1000000: single cold run 7.971 ms, 4096 items derived, lane0 a4697a4c254a61a7 lane31 3cc24e96c299c61d +CPU verify: 8.249 ms per 32-lane warp, avg of 20 (checksum 7e659be3d18245a4) +== c rep 1 class w64m8g+sh256x27 weights 13,11,6,10,8,8,7,2,6,4 +warp base 0: single cold run 8.851 ms, 4096 items derived, lane0 10e24635c2a2eb4f lane31 050b69a708943300 +warp base 4096: single cold run 8.922 ms, 4096 items derived, lane0 f7b8d920396a4441 lane31 784c075f03b92f28 +warp base 1000000: single cold run 8.880 ms, 4096 items derived, lane0 07f320e47aa8c175 lane31 622c9b4638d07f65 +CPU verify: 9.148 ms per 32-lane warp, avg of 20 (checksum 8551e68dd6a59dae) +== c rep 2 class w64m8g+sh256x27 weights 13,11,6,10,8,8,7,2,6,4 +warp base 0: single cold run 9.579 ms, 4096 items derived, lane0 10e24635c2a2eb4f lane31 050b69a708943300 +warp base 4096: single cold run 8.808 ms, 4096 items derived, lane0 f7b8d920396a4441 lane31 784c075f03b92f28 +warp base 1000000: single cold run 8.869 ms, 4096 items derived, lane0 07f320e47aa8c175 lane31 622c9b4638d07f65 +CPU verify: 9.214 ms per 32-lane warp, avg of 20 (checksum 8551e68dd6a59dae) +== c rep 3 class w64m8g+sh256x27 weights 13,11,6,10,8,8,7,2,6,4 +warp base 0: single cold run 9.415 ms, 4096 items derived, lane0 10e24635c2a2eb4f lane31 050b69a708943300 +warp base 4096: single cold run 9.177 ms, 4096 items derived, lane0 f7b8d920396a4441 lane31 784c075f03b92f28 +warp base 1000000: single cold run 9.243 ms, 4096 items derived, lane0 07f320e47aa8c175 lane31 622c9b4638d07f65 +CPU verify: 9.254 ms per 32-lane warp, avg of 20 (checksum 8551e68dd6a59dae) +== ctrl-again rep 1 class mx8+sh256x27 weights base +warp base 0: single cold run 9.541 ms, 4096 items derived, lane0 2fc898410932f9e3 lane31 46d6a126c7aa1def +warp base 4096: single cold run 9.261 ms, 4096 items derived, lane0 7a977c3ed95fd05a lane31 2845370fe23e9cbc +warp base 1000000: single cold run 9.239 ms, 4096 items derived, lane0 7ec39eb3571dd232 lane31 a96c22d96855eaaf +CPU verify: 9.493 ms per 32-lane warp, avg of 20 (checksum 0e89d7e40db622e9) +== ctrl-again rep 2 class mx8+sh256x27 weights base +warp base 0: single cold run 9.285 ms, 4096 items derived, lane0 2fc898410932f9e3 lane31 46d6a126c7aa1def +warp base 4096: single cold run 8.907 ms, 4096 items derived, lane0 7a977c3ed95fd05a lane31 2845370fe23e9cbc +warp base 1000000: single cold run 8.967 ms, 4096 items derived, lane0 7ec39eb3571dd232 lane31 a96c22d96855eaaf +CPU verify: 9.125 ms per 32-lane warp, avg of 20 (checksum 0e89d7e40db622e9) +== ctrl-again rep 3 class mx8+sh256x27 weights base +warp base 0: single cold run 9.423 ms, 4096 items derived, lane0 2fc898410932f9e3 lane31 46d6a126c7aa1def +warp base 4096: single cold run 9.181 ms, 4096 items derived, lane0 7a977c3ed95fd05a lane31 2845370fe23e9cbc +warp base 1000000: single cold run 9.123 ms, 4096 items derived, lane0 7ec39eb3571dd232 lane31 a96c22d96855eaaf +CPU verify: 9.191 ms per 32-lane warp, avg of 20 (checksum 0e89d7e40db622e9) +# bench end 2026-10-08T12:56:53Z +lease: released 1 pool cores after 918 s, exit 0 diff --git a/docs/analysis/class-v6/logs/census/c-era.tsv b/docs/analysis/class-v6/logs/census/c-era.tsv new file mode 100644 index 000000000..2d853e1a2 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/c-era.tsv @@ -0,0 +1,259 @@ +# c-era class w64m8g+sh256x27 eras [0,1,2,3,4,5,6,7] seeds 32 era-widths 64 weights 13,11,6,10,8,8,7,2,6,4 bittest 1 bin d601098699840534 start 2026-10-08T12:55:03Z host igneum-build-4 threads 15 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +c-era 0 12 5 1 4 3.0 15 16 c,=2;a'=1;a=1; +c-era 0 1 2 1 1 2.8 9 15 c,=1; +c-era 0 3 2 1 1 3.1 7 24 c,=1; +c-era 0 9 2 1 1 4.3 15 20 c,=1; +c-era 0 11 9 1 8 3.3 10 8 c,=7;a'=1; +c-era 0 10 10 1 9 2.8 4 10 c,=8;a=1; +c-era 0 4 9 1 8 3.5 10 7 a'=5;c,=2;a=1; +c-era 0 8 1 1 0 2.9 12 5 +c-era 0 6 2 1 1 2.8 14 16 a'=1; +c-era 0 14 6 1 5 3.0 11 25 a'=3;c,=2; +c-era 0 13 3 1 2 3.2 15 8 c,=1;a'=1; +c-era 0 5 3 1 2 3.7 11 19 a'=2; +c-era 0 0 5 1 4 3.5 3 19 c,=2;a'=2; +c-era 0 2 2 1 1 2.7 3 9 c,=1; +c-era 0 7 3 1 2 2.7 11 26 c,=1;a'=1; +c-era 0 16 1 1 0 3.5 8 13 +c-era 0 17 3 1 2 3.2 3 11 c,=1;a'=1; +c-era 0 19 1 1 0 3.1 1 11 +c-era 0 18 2 1 1 4.9 12 21 c,=1; +c-era 0 20 3 1 2 3.1 12 17 c,=1;a'=1; +c-era 0 21 4 1 3 3.4 2 11 a'=2;c,=1; +c-era 0 23 2 1 1 2.7 4 12 a=1; +c-era 0 27 2 1 1 2.8 6 20 a'=1; +c-era 0 15 6 1 5 3.0 15 11 c,=3;a'=2; +c-era 0 25 6 1 5 3.0 13 18 c,=4;a=1; +c-era 0 24 1 1 0 3.5 3 18 +c-era 0 29 2 1 1 2.8 7 5 c,=1; +c-era 0 22 2 1 1 2.8 2 15 a'=1; +c-era 0 26 11 1 10 3.2 2 25 c,=6;a'=3;c=1; +c-era 0 28 9 1 8 3.0 10 15 a'=4;c,=3;a=1; +c-era 0 31 1 1 0 3.2 8 21 +c-era 0 30 5 1 4 3.1 12 5 a'=3;a=1; +c-era 1 0 5 1 4 3.1 10 15 c,=2;a'=2; +c-era 1 3 2 1 1 3.7 11 17 c,=1; +c-era 1 1 2 1 1 3.1 15 19 c,=1; +c-era 1 5 3 1 2 4.7 11 7 a'=2; +c-era 1 6 2 1 1 3.0 5 6 a'=1; +c-era 1 2 2 1 1 3.2 10 23 c,=1; +c-era 1 7 3 1 2 3.7 7 26 c,=1;a'=1; +c-era 1 10 10 1 9 3.0 0 19 c,=8;a=1; +c-era 1 4 12 1 11 2.5 6 7 c,=5;a'=5;a=1; +c-era 1 9 2 1 1 2.7 5 20 c,=1; +c-era 1 8 1 1 0 3.2 1 18 +c-era 1 11 9 1 8 2.7 2 15 c,=7;a'=1; +c-era 1 14 6 1 5 4.0 12 17 a'=3;c,=2; +c-era 1 12 5 1 4 2.7 14 22 c,=2;a'=1;a=1; +c-era 1 16 1 1 0 3.1 13 5 +c-era 1 21 4 1 3 3.8 7 13 a'=2;c,=1; +c-era 1 20 3 1 2 3.0 6 24 c,=1;a'=1; +c-era 1 13 3 1 2 3.8 10 19 c,=1;a'=1; +c-era 1 17 3 1 2 3.1 1 6 c,=1;a'=1; +c-era 1 15 6 1 5 2.6 10 17 c,=3;a'=2; +c-era 1 25 6 1 5 2.8 0 6 c,=4;a=1; +c-era 1 18 3 1 2 3.1 2 20 c,=2; +c-era 1 22 2 1 1 3.2 14 25 a'=1; +c-era 1 28 9 1 8 3.6 5 20 a'=4;c,=3;a=1; +c-era 1 27 2 1 1 3.3 8 23 a'=1; +c-era 1 19 1 1 0 3.0 7 17 +c-era 1 26 11 1 10 3.5 12 21 c,=6;a'=3;c=1; +c-era 1 23 2 1 1 3.1 3 24 a=1; +c-era 1 30 5 1 4 3.0 12 21 a'=3;a=1; +c-era 1 31 1 1 0 3.2 7 7 +c-era 1 24 1 1 0 3.5 4 12 +c-era 2 0 2 1 1 3.0 5 5 a'=1; +c-era 2 2 1 1 0 3.3 9 14 +c-era 2 6 2 1 1 3.2 13 27 a'=1; +c-era 1 29 2 1 1 3.3 3 6 c,=1; +c-era 2 9 1 1 0 3.2 6 5 +c-era 2 8 1 1 0 3.0 8 17 +c-era 2 1 1 1 0 2.7 2 15 +c-era 2 10 1 1 0 2.5 12 19 +c-era 2 3 2 1 1 2.9 0 4 c,=1; +c-era 2 5 3 1 2 3.0 7 18 a'=2; +c-era 2 11 1 1 0 3.5 12 21 +c-era 2 12 2 1 1 3.6 8 22 a'=1; +c-era 2 4 1 1 0 3.0 4 20 +c-era 2 7 1 1 0 3.0 7 25 +c-era 2 13 1 1 0 2.8 14 11 +c-era 2 14 1 1 0 2.8 15 7 +c-era 2 16 1 1 0 3.0 10 22 +c-era 2 15 2 1 1 3.1 0 14 a'=1; +c-era 2 18 1 1 0 3.7 12 5 +c-era 2 20 1 1 0 2.9 4 5 +c-era 2 19 1 1 0 3.5 15 4 +c-era 2 21 3 1 2 3.0 6 10 a'=2; +c-era 2 22 2 1 1 2.9 5 4 a'=1; +c-era 2 17 2 1 1 2.6 0 19 a'=1; +c-era 2 25 1 1 0 3.4 11 14 +c-era 2 23 2 1 1 2.9 6 15 a=1; +c-era 2 27 2 1 1 4.0 10 23 a'=1; +c-era 2 24 1 1 0 2.7 0 23 +c-era 2 26 1 1 0 2.8 13 14 +c-era 2 28 5 1 4 3.0 8 10 a'=3;a=1; +c-era 2 31 1 1 0 3.5 13 18 +c-era 2 29 1 1 0 2.5 5 18 +c-era 3 2 1 1 0 3.3 3 7 +c-era 3 4 6 1 5 3.5 6 12 a'=4;c,=1; +c-era 2 30 5 1 4 2.9 9 26 a'=3;a=1; +c-era 3 0 2 1 1 2.8 4 23 a'=1; +c-era 3 5 3 1 2 4.6 11 4 a'=2; +c-era 3 8 1 1 0 3.2 14 10 +c-era 3 7 1 1 0 3.0 6 7 +c-era 3 6 2 1 1 3.2 7 10 a'=1; +c-era 3 3 2 1 1 2.8 3 20 c,=1; +c-era 3 9 1 1 0 3.0 14 26 +c-era 3 10 1 1 0 2.8 0 12 +c-era 3 1 1 1 0 3.8 7 4 +c-era 3 11 1 1 0 3.6 13 15 +c-era 3 12 2 1 1 2.6 8 25 a'=1; +c-era 3 13 1 1 0 3.0 8 19 +c-era 3 14 1 1 0 3.1 6 17 +c-era 3 16 1 1 0 3.5 3 8 +c-era 3 15 2 1 1 3.5 10 26 a'=1; +c-era 3 19 1 1 0 3.0 13 7 +c-era 3 17 2 1 1 3.6 7 26 a'=1; +c-era 3 18 1 1 0 3.0 11 20 +c-era 3 20 3 1 2 2.9 14 9 c,=1;a'=1; +c-era 3 24 1 1 0 2.6 14 17 +c-era 3 21 3 1 2 3.6 2 4 a'=2; +c-era 3 23 2 1 1 3.1 9 15 a=1; +c-era 3 25 1 1 0 3.1 15 21 +c-era 3 28 5 1 4 3.0 7 17 a'=3;a=1; +c-era 3 26 1 1 0 2.7 4 4 +c-era 4 0 5 1 4 3.2 13 22 c,=2;a'=2; +c-era 3 29 1 1 0 3.1 0 24 +c-era 3 22 2 1 1 3.2 1 24 a'=1; +c-era 3 31 1 1 0 3.0 1 4 +c-era 3 30 5 1 4 2.9 3 10 a'=3;a=1; +c-era 3 27 2 1 1 3.1 3 7 a'=1; +c-era 4 4 9 1 8 4.9 1 14 a'=5;c,=2;a=1; +c-era 4 2 2 1 1 3.1 10 5 c,=1; +c-era 4 1 2 1 1 3.1 3 26 c,=1; +c-era 4 3 2 1 1 3.4 3 18 c,=1; +c-era 4 5 3 1 2 4.3 11 11 a'=2; +c-era 4 10 10 1 9 3.1 13 7 c,=8;a=1; +c-era 4 6 2 1 1 2.5 1 7 a'=1; +c-era 4 11 9 1 8 2.8 10 23 c,=7;a'=1; +c-era 4 8 1 1 0 2.7 3 4 +c-era 4 13 3 1 2 3.3 7 9 c,=1;a'=1; +c-era 4 7 3 1 2 3.4 8 12 c,=1;a'=1; +c-era 4 18 3 1 2 2.9 14 7 c,=2; +c-era 4 12 3 1 2 5.4 0 10 c,=1;a'=1; +c-era 4 9 2 1 1 3.3 15 23 c,=1; +c-era 4 16 1 1 0 3.0 2 11 +c-era 4 14 6 1 5 2.8 9 13 a'=3;c,=2; +c-era 4 21 4 1 3 3.3 9 19 a'=2;c,=1; +c-era 4 17 3 1 2 3.3 15 23 c,=1;a'=1; +c-era 4 15 6 1 5 3.3 9 8 c,=3;a'=2; +c-era 4 19 1 1 0 3.2 4 18 +c-era 4 20 3 1 2 3.2 0 18 c,=1;a'=1; +c-era 4 22 2 1 1 3.9 12 25 a'=1; +c-era 4 25 6 1 5 3.3 4 16 c,=4;a=1; +c-era 4 23 2 1 1 3.5 9 7 a=1; +c-era 4 27 2 1 1 2.9 14 7 a'=1; +c-era 4 24 1 1 0 3.0 3 15 +c-era 5 1 2 1 1 3.5 12 24 c,=1; +c-era 5 6 2 1 1 3.3 8 18 a'=1; +c-era 5 0 5 1 4 4.0 2 17 c,=2;a'=2; +c-era 4 31 1 1 0 3.0 2 13 +c-era 5 9 2 1 1 3.3 7 21 c,=1; +c-era 5 8 1 1 0 3.2 15 22 +c-era 4 28 9 1 8 3.3 9 18 a'=4;c,=3;a=1; +c-era 4 30 5 1 4 3.3 8 19 a'=3;a=1; +c-era 4 29 2 1 1 3.9 13 10 c,=1; +c-era 4 26 11 1 10 3.4 11 4 c,=6;a'=3;c=1; +c-era 5 10 10 1 9 3.0 4 24 c,=8;a=1; +c-era 5 13 3 1 2 3.3 4 21 c,=1;a'=1; +c-era 5 17 3 1 2 3.4 5 4 c,=1;a'=1; +c-era 5 5 3 1 2 5.1 11 22 a'=2; +c-era 5 14 6 1 5 2.9 0 14 a'=3;c,=2; +c-era 5 7 3 1 2 3.4 9 8 c,=1;a'=1; +c-era 5 19 1 1 0 2.7 11 11 +c-era 5 15 6 1 5 3.4 6 23 c,=3;a'=2; +c-era 5 3 2 1 1 2.7 4 23 c,=1; +c-era 5 4 9 1 8 3.0 8 13 a'=5;c,=2;a=1; +c-era 5 2 2 1 1 3.2 10 4 c,=1; +c-era 5 18 3 1 2 3.4 13 11 c,=2; +c-era 5 20 3 1 2 4.0 15 13 c,=1;a'=1; +c-era 5 11 9 1 8 2.7 8 18 c,=7;a'=1; +c-era 5 16 1 1 0 3.5 1 23 +c-era 5 12 5 1 4 3.5 11 15 c,=2;a'=1;a=1; +c-era 5 21 4 1 3 2.9 13 14 a'=2;c,=1; +c-era 5 22 2 1 1 2.6 11 10 a'=1; +c-era 5 24 1 1 0 2.9 0 12 +c-era 5 28 9 1 8 2.9 8 10 a'=4;c,=3;a=1; +c-era 5 25 6 1 5 3.5 3 9 c,=4;a=1; +c-era 5 29 2 1 1 2.8 6 25 c,=1; +c-era 5 30 5 1 4 4.5 10 22 a'=3;a=1; +c-era 5 26 11 1 10 3.1 14 19 c,=6;a'=3;c=1; +c-era 5 27 2 1 1 3.1 11 4 a'=1; +c-era 5 23 2 1 1 2.7 2 20 a=1; +c-era 5 31 1 1 0 3.7 11 11 +c-era 6 4 6 1 5 3.0 7 7 a'=4;c,=1; +c-era 6 0 2 1 1 3.0 8 10 a'=1; +c-era 6 5 3 1 2 4.1 11 6 a'=2; +c-era 6 2 2 1 1 3.5 7 8 c,=1; +c-era 6 6 2 1 1 3.0 9 21 a'=1; +c-era 6 1 2 1 1 2.6 2 26 c,=1; +c-era 6 9 1 1 0 3.1 5 9 +c-era 6 3 2 1 1 2.9 13 24 c,=1; +c-era 6 11 5 1 4 3.1 0 7 c,=4; +c-era 6 13 1 1 0 3.1 0 4 +c-era 6 12 2 1 1 3.4 12 13 a'=1; +c-era 6 10 7 1 6 2.9 12 13 c,=5;a=1; +c-era 6 14 1 1 0 3.2 14 23 +c-era 6 7 1 1 0 3.2 4 12 +c-era 6 8 1 1 0 2.8 13 8 +c-era 6 15 6 1 5 3.3 3 11 c,=3;a'=2; +c-era 6 17 3 1 2 3.5 8 5 c,=1;a'=1; +c-era 6 19 1 1 0 3.3 9 21 +c-era 6 18 1 1 0 2.9 7 14 +c-era 6 16 1 1 0 2.8 9 13 +c-era 6 20 3 1 2 2.9 13 6 c,=1;a'=1; +c-era 6 22 2 1 1 3.1 14 6 a'=1; +c-era 6 21 3 1 2 3.9 14 7 a'=2; +c-era 6 27 2 1 1 2.9 3 20 a'=1; +c-era 6 24 1 1 0 3.7 9 7 +c-era 6 23 2 1 1 3.0 3 24 a=1; +c-era 6 25 1 1 0 3.0 12 7 +c-era 6 26 7 1 6 5.5 5 5 c,=3;a'=2;c=1; +c-era 6 29 1 1 0 2.7 13 5 +c-era 6 28 9 1 8 2.9 12 21 a'=4;c,=3;a=1; +c-era 6 31 1 1 0 3.5 1 23 +c-era 7 0 2 1 1 2.7 12 23 a'=1; +c-era 6 30 5 1 4 3.4 9 4 a'=3;a=1; +c-era 7 2 2 1 1 3.1 2 17 c,=1; +c-era 7 1 1 1 0 2.6 3 5 +c-era 7 3 2 1 1 3.0 12 6 c,=1; +c-era 7 7 1 1 0 3.2 0 8 +c-era 7 4 9 1 8 3.3 7 5 a'=5;c,=2;a=1; +c-era 7 8 1 1 0 2.7 6 23 +c-era 7 5 3 1 2 2.8 11 25 a'=2; +c-era 7 11 1 1 0 2.8 11 7 +c-era 7 9 2 1 1 2.7 8 13 c,=1; +c-era 7 14 1 1 0 2.7 14 7 +c-era 7 6 2 1 1 2.8 1 24 a'=1; +c-era 7 10 1 1 0 3.5 10 21 +c-era 7 17 2 1 1 3.4 5 21 a'=1; +c-era 7 12 2 1 1 3.3 1 10 a'=1; +c-era 7 13 3 1 2 3.1 7 15 c,=1;a'=1; +c-era 7 20 1 1 0 3.8 15 17 +c-era 7 15 6 1 5 2.8 13 24 c,=3;a'=2; +c-era 7 22 2 1 1 3.0 0 9 a'=1; +c-era 7 18 2 1 1 2.9 8 16 c,=1; +c-era 7 21 4 1 3 3.3 0 20 a'=2;c,=1; +c-era 7 23 2 1 1 2.9 8 13 a=1; +c-era 7 16 1 1 0 2.9 11 7 +c-era 7 24 1 1 0 3.1 8 12 +c-era 7 19 1 1 0 3.5 6 25 +c-era 7 25 1 1 0 3.3 2 16 +c-era 7 26 7 1 6 3.5 3 19 c,=3;a'=2;c=1; +c-era 7 28 5 1 4 3.0 13 14 a'=3;a=1; +c-era 7 29 1 1 0 3.2 13 19 +c-era 7 30 5 1 4 2.7 8 17 a'=3;a=1; +c-era 7 31 1 1 0 3.2 7 20 +c-era 7 27 2 1 1 2.9 2 4 a'=1; +# end 2026-10-08T12:59:21Z rows=257 diff --git a/docs/analysis/class-v6/logs/census/c-none.tsv b/docs/analysis/class-v6/logs/census/c-none.tsv new file mode 100644 index 000000000..99cfb4711 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/c-none.tsv @@ -0,0 +1,258 @@ +# c-none class w64m8g+sh256x27 eras [none] seeds 256 era-widths 64 weights 13,11,6,10,8,8,7,2,6,4 bittest off bin d601098699840534 start 2026-10-08T12:45:54Z host igneum-build-4 threads 16 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +c-none none 1 1 1 0 3.1 2 9 +c-none none 15 2 1 1 4.1 10 10 a'=1; +c-none none 2 5 1 4 3.3 3 26 a'=3;a=1; +c-none none 6 2 1 1 3.9 2 4 c=1; +c-none none 3 1 1 0 6.7 9 4 +c-none none 4 2 1 1 3.0 14 15 a'=1; +c-none none 8 2 1 1 4.8 2 16 a'=1; +c-none none 5 1 1 0 2.9 1 8 +c-none none 18 1 1 0 3.1 3 10 +c-none none 19 1 1 0 7.2 4 5 +c-none none 21 4 1 3 3.2 3 5 a'=3; +c-none none 22 1 1 0 30.9 5 23 +c-none none 17 1 1 0 11.9 10 4 +c-none none 20 1 1 0 13.6 10 4 +c-none none 14 1 1 0 4.0 11 4 +c-none none 10 1 1 0 3.0 14 7 +c-none none 13 1 1 0 3.3 15 22 +c-none none 24 2 1 1 3.2 9 4 a'=1; +c-none none 23 2 1 1 2.9 1 4 a'=1; +c-none none 25 1 1 0 2.5 8 5 +c-none none 11 1 1 0 3.1 3 13 +c-none none 7 1 1 0 4.0 0 4 +c-none none 12 1 1 0 3.2 1 12 +c-none none 29 3 1 2 4.0 12 19 a'=2; +c-none none 0 2 1 1 2.9 3 18 a'=1; +c-none none 27 3 1 2 2.8 5 14 c=1;b=1; +c-none none 16 4 1 3 3.4 11 21 a'=3; +c-none none 30 3 1 2 9.8 0 4 a'=1;a=1; +c-none none 28 1 1 0 3.0 0 7 +c-none none 26 1 1 0 3.5 10 26 +c-none none 41 2 1 1 3.3 8 5 a'=1; +c-none none 34 2 1 1 2.9 15 19 a=1; +c-none none 33 2 1 1 32.4 1 19 a=1; +c-none none 32 1 1 0 3.4 13 19 +c-none none 38 1 1 0 10.8 3 27 +c-none none 9 7 1 6 3.8 3 13 a'=3;c'''=1;c''=1;a=1; +c-none none 31 4 1 3 3.7 14 11 a'=3; +c-none none 35 2 1 1 9.9 2 4 a'=1; +c-none none 37 2 1 1 3.1 8 7 a'=1; +c-none none 36 1 1 0 3.0 1 21 +c-none none 39 1 1 0 2.8 8 22 +c-none none 42 1 1 0 3.0 6 12 +c-none none 40 1 1 0 2.8 1 13 +c-none none 48 2 1 1 3.0 3 10 a'=1; +c-none none 49 2 1 1 3.8 8 11 a'=1; +c-none none 56 1 1 0 3.3 3 20 +c-none none 50 1 1 0 13.6 3 4 +c-none none 57 1 1 0 3.5 15 9 +c-none none 55 1 1 0 5.7 1 21 +c-none none 52 1 1 0 7.4 4 10 +c-none none 44 1 1 0 3.0 2 10 +c-none none 43 2 1 1 3.2 5 22 a'=1; +c-none none 54 5 1 4 3.0 10 6 a'=2;c'''=1;a=1; +c-none none 53 2 1 1 3.6 8 12 c''=1; +c-none none 45 1 1 0 5.5 15 4 +c-none none 51 2 1 1 3.1 6 15 a'=1; +c-none none 59 1 1 0 3.3 10 25 +c-none none 47 2 1 1 3.0 12 8 a'=1; +c-none none 58 1 1 0 3.5 14 14 +c-none none 60 2 1 1 3.1 1 16 a'=1; +c-none none 61 3 1 2 8.1 12 4 a'=2; +c-none none 63 2 1 1 6.0 6 4 a'=1; +c-none none 64 1 1 0 3.0 12 21 +c-none none 46 4 1 3 3.6 14 23 a'=2;c'''=1; +c-none none 62 1 1 0 5.2 11 4 +c-none none 65 1 1 0 2.9 6 12 +c-none none 66 2 1 1 12.1 10 4 a=1; +c-none none 67 1 1 0 2.6 3 11 +c-none none 68 2 1 1 9.1 2 4 a'=1; +c-none none 70 1 1 0 3.1 4 10 +c-none none 69 2 1 1 4.2 13 4 a=1; +c-none none 76 6 1 5 8.7 0 15 a'=4;a=1; +c-none none 71 1 1 0 3.2 0 16 +c-none none 73 1 1 0 3.1 3 13 +c-none none 75 1 1 0 3.0 0 9 +c-none none 80 1 1 0 3.0 12 19 +c-none none 79 1 1 0 3.2 8 4 +c-none none 82 1 1 0 3.6 12 22 +c-none none 74 1 1 0 3.1 13 9 +c-none none 77 3 1 2 3.8 6 9 c''=1;a=1; +c-none none 84 1 1 0 3.0 2 5 +c-none none 81 3 1 2 3.3 0 5 c'''=1;a'=1; +c-none none 83 1 1 0 2.9 7 25 +c-none none 78 1 1 0 3.1 9 9 +c-none none 88 1 1 0 3.3 9 25 +c-none none 72 3 1 2 3.3 12 11 c''=1;a'=1; +c-none none 95 2 1 1 2.5 15 19 a'=1; +c-none none 93 1 1 0 3.6 14 17 +c-none none 90 2 1 1 2.9 1 19 c''=1; +c-none none 98 2 1 1 2.8 10 5 c'''=1; +c-none none 91 1 1 0 5.1 12 4 +c-none none 85 1 1 0 3.4 14 20 +c-none none 100 1 1 0 3.1 13 25 +c-none none 87 1 1 0 31.4 9 10 +c-none none 86 1 1 0 3.0 8 10 +c-none none 102 1 1 0 3.4 9 4 +c-none none 99 2 1 1 2.9 9 6 c''=1; +c-none none 89 2 1 1 2.8 6 5 a'=1; +c-none none 92 1 1 0 2.8 9 12 +c-none none 97 1 1 0 2.6 7 12 +c-none none 96 1 1 0 2.7 3 8 +c-none none 94 1 1 0 3.5 5 4 +c-none none 101 2 1 1 3.2 3 19 c''=1; +c-none none 106 1 1 0 2.8 6 9 +c-none none 107 3 1 2 3.0 1 8 a'=2; +c-none none 103 1 1 0 4.4 8 4 +c-none none 110 2 1 1 2.7 11 19 a'=1; +c-none none 104 1 1 0 3.5 6 9 +c-none none 111 1 1 0 3.2 3 9 +c-none none 109 1 1 0 3.3 2 11 +c-none none 112 2 1 1 3.6 7 4 a'=1; +c-none none 113 1 1 0 3.5 5 13 +c-none none 108 2 1 1 5.1 10 4 c'''=1; +c-none none 115 1 1 0 3.2 14 14 +c-none none 105 1 1 0 2.7 13 10 +c-none none 114 2 1 1 3.4 7 6 c=1; +c-none none 118 2 1 1 2.6 9 4 a=1; +c-none none 116 2 1 1 3.0 14 8 a'=1; +c-none none 120 2 1 1 3.1 12 12 a'=1; +c-none none 119 1 1 0 3.1 8 18 +c-none none 124 1 1 0 3.3 9 18 +c-none none 122 1 1 0 4.6 2 4 +c-none none 123 2 1 1 32.4 5 5 c'''=1; +c-none none 129 1 1 0 3.2 7 4 +c-none none 121 1 1 0 7.8 5 19 +c-none none 117 1 1 0 3.3 7 9 +c-none none 132 1 1 0 3.2 6 11 +c-none none 125 1 1 0 2.8 5 6 +c-none none 126 1 1 0 9.0 0 11 +c-none none 133 3 1 2 5.4 11 4 a'=2; +c-none none 130 1 1 0 5.2 10 4 +c-none none 128 6 1 5 4.0 0 5 a'=3;c=1;a=1; +c-none none 131 1 1 0 3.5 0 4 +c-none none 134 4 1 3 2.8 11 19 a'=3; +c-none none 138 1 1 0 3.2 10 23 +c-none none 137 2 1 1 3.1 1 17 a'=1; +c-none none 127 4 1 3 4.3 14 4 a'=2;c'''=1; +c-none none 141 2 1 1 2.7 11 26 a'=1; +c-none none 142 2 1 1 5.8 5 4 c=1; +c-none none 135 2 1 1 3.1 6 17 a'=1; +c-none none 140 4 1 3 7.1 13 14 b=1;a'=1;a=1; +c-none none 136 1 1 0 12.6 6 4 +c-none none 144 1 1 0 3.3 8 7 +c-none none 145 1 1 0 3.3 9 4 +c-none none 151 1 1 0 2.9 14 8 +c-none none 139 3 1 2 10.5 4 4 a'=2; +c-none none 148 2 1 1 2.7 2 15 a=1; +c-none none 150 1 1 0 28.8 3 9 +c-none none 147 4 1 3 3.5 7 24 a'=3; +c-none none 155 1 1 0 3.2 0 4 +c-none none 156 2 1 1 3.3 10 13 a=1; +c-none none 154 1 1 0 3.2 7 16 +c-none none 153 1 1 0 3.6 1 6 +c-none none 149 2 1 1 3.2 14 5 a'=1; +c-none none 152 2 1 1 3.2 1 21 a'=1; +c-none none 146 1 1 0 3.7 2 5 +c-none none 159 1 1 0 3.4 9 5 +c-none none 143 5 1 4 5.0 2 4 c'''=1;c''=1;a'=1;a=1; +c-none none 157 1 1 0 4.0 10 10 +c-none none 160 2 1 1 2.8 11 9 a'=1; +c-none none 168 1 1 0 2.7 5 27 +c-none none 158 1 1 0 3.0 2 19 +c-none none 163 1 1 0 3.3 6 16 +c-none none 175 1 1 0 3.0 9 6 +c-none none 165 1 1 0 2.7 3 11 +c-none none 161 4 1 3 3.0 10 8 a'=3; +c-none none 171 1 1 0 4.3 3 13 +c-none none 167 2 1 1 3.2 2 11 a=1; +c-none none 164 1 1 0 3.7 14 4 +c-none none 162 1 1 0 2.8 14 14 +c-none none 179 1 1 0 3.2 0 12 +c-none none 166 4 1 3 3.4 0 22 a'=3; +c-none none 172 1 1 0 4.2 2 4 +c-none none 170 1 1 0 4.3 10 4 +c-none none 173 3 1 2 2.5 5 5 a'=2; +c-none none 183 1 1 0 3.5 10 13 +c-none none 176 3 1 2 3.5 5 13 a'=1;a=1; +c-none none 177 1 1 0 2.4 1 23 +c-none none 174 1 1 0 6.7 2 27 +c-none none 178 2 1 1 2.7 5 9 a'=1; +c-none none 169 3 1 2 3.0 10 22 c''=1;a'=1; +c-none none 182 1 1 0 34.1 4 18 +c-none none 184 3 1 2 5.0 7 10 a'=2; +c-none none 180 2 1 1 3.0 0 23 a'=1; +c-none none 181 4 1 3 3.5 5 5 a'=3; +c-none none 189 2 1 1 5.8 5 4 a'=1; +c-none none 185 2 1 1 3.4 5 4 c''=1; +c-none none 190 4 1 3 2.7 10 16 a'=2;c'''=1; +c-none none 186 1 1 0 14.8 1 26 +c-none none 188 4 1 3 5.8 8 27 a'=2;c''=1; +c-none none 198 1 1 0 2.9 7 24 +c-none none 191 2 1 1 3.6 13 26 a'=1; +c-none none 193 1 1 0 4.1 6 6 +c-none none 195 1 1 0 3.2 13 18 +c-none none 192 1 1 0 3.3 7 4 +c-none none 199 1 1 0 2.5 4 27 +c-none none 200 1 1 0 3.2 1 15 +c-none none 197 4 1 3 3.1 0 17 a'=3; +c-none none 196 2 1 1 3.1 6 24 a'=1; +c-none none 201 1 1 0 5.0 9 4 +c-none none 187 2 1 1 4.5 3 4 c'''=1; +c-none none 202 1 1 0 3.0 2 13 +c-none none 203 4 1 3 5.2 9 11 a'=3; +c-none none 194 2 1 1 4.4 12 4 c=1; +c-none none 207 1 1 0 3.1 13 23 +c-none none 205 1 1 0 2.8 14 4 +c-none none 204 2 1 1 2.9 4 10 c=1; +c-none none 210 1 1 0 3.2 13 27 +c-none none 213 1 1 0 3.7 12 15 +c-none none 208 1 1 0 2.5 10 4 +c-none none 212 2 1 1 4.0 1 14 a'=1; +c-none none 215 2 1 1 2.8 13 17 a'=1; +c-none none 214 2 1 1 2.8 15 8 b=1; +c-none none 217 1 1 0 2.7 13 6 +c-none none 209 3 1 2 2.9 2 21 c'''=1;c=1; +c-none none 216 2 1 1 2.8 6 22 c'''=1; +c-none none 206 6 1 5 7.0 5 13 a'=4;a=1; +c-none none 211 3 1 2 3.4 2 5 c''=1;a=1; +c-none none 219 1 1 0 2.8 4 10 +c-none none 221 2 1 1 4.0 8 4 a'=1; +c-none none 226 1 1 0 31.5 14 16 +c-none none 228 1 1 0 3.1 15 4 +c-none none 227 1 1 0 3.0 2 15 +c-none none 230 1 1 0 3.6 1 20 +c-none none 223 1 1 0 2.6 10 15 +c-none none 231 1 1 0 7.0 3 20 +c-none none 232 1 1 0 4.4 10 4 +c-none none 229 1 1 0 3.6 0 12 +c-none none 233 1 1 0 4.0 13 4 +c-none none 222 3 1 2 3.1 11 15 c'''=1;a'=1; +c-none none 235 1 1 0 9.0 12 4 +c-none none 225 1 1 0 3.4 6 27 +c-none none 236 1 1 0 3.6 12 12 +c-none none 224 3 1 2 3.6 10 19 a'=2; +c-none none 220 1 1 0 3.7 13 4 +c-none none 234 3 1 2 9.6 2 4 a'=2; +c-none none 245 2 1 1 3.4 8 11 a'=1; +c-none none 243 1 1 0 3.1 2 16 +c-none none 242 1 1 0 3.4 12 9 +c-none none 244 1 1 0 3.0 13 12 +c-none none 241 1 1 0 5.0 4 4 +c-none none 238 1 1 0 3.3 12 19 +c-none none 237 1 1 0 4.4 5 4 +c-none none 239 1 1 0 3.0 2 17 +c-none none 218 3 1 2 3.2 3 11 c=1;a'=1; +c-none none 240 1 1 0 4.1 6 4 +c-none none 250 1 1 0 2.9 1 7 +c-none none 249 1 1 0 4.8 2 27 +c-none none 254 1 1 0 9.7 4 18 +c-none none 255 1 1 0 3.9 11 9 +c-none none 253 1 1 0 4.4 0 21 +c-none none 252 4 1 3 2.7 2 14 a'=2;a=1; +c-none none 246 4 1 3 3.3 10 14 c'''=1;c''=1;a'=1; +c-none none 247 1 1 0 2.6 10 7 +c-none none 248 1 1 0 3.7 0 16 +c-none none 251 5 1 4 3.0 4 7 a'=2;c''=1;b=1; diff --git a/docs/analysis/class-v6/logs/census/ctrl-era.tsv b/docs/analysis/class-v6/logs/census/ctrl-era.tsv new file mode 100644 index 000000000..746b10baa --- /dev/null +++ b/docs/analysis/class-v6/logs/census/ctrl-era.tsv @@ -0,0 +1,259 @@ +# ctrl-era class mx8+sh256x27 eras [0,1,2,3,4,5,6,7] seeds 32 era-widths 4 weights base bittest 1 bin d601098699840534 start 2026-10-08T12:59:30Z host igneum-build-4 threads 16 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +ctrl-era 0 0 1 1 0 3.2 2 4 +ctrl-era 0 2 6 1 5 3.2 15 17 a'=4;c,=1; +ctrl-era 0 10 18 1 17 3.4 12 4 a'=8;c,=6;a=2;c=1; +ctrl-era 0 13 2 1 1 3.3 10 12 a=1; +ctrl-era 0 4 1 1 0 2.8 3 15 +ctrl-era 0 9 7 1 6 3.6 15 3 a'=5;a=1; +ctrl-era 0 5 4 1 3 3.1 10 17 a'=2;c,=1; +ctrl-era 0 3 17 1 16 2.9 5 21 a'=11;c,=3;a=2; +ctrl-era 0 6 9 1 8 3.3 7 17 a'=7;a=1; +ctrl-era 0 15 4 1 3 3.2 6 7 c,=1;b=1;a'=1; +ctrl-era 0 17 1 1 0 3.7 8 24 +ctrl-era 0 14 6 1 5 3.4 5 21 c,=2;a'=2;a=1; +ctrl-era 0 1 10 1 9 3.1 7 27 a'=7;c,=2; +ctrl-era 0 8 3 1 2 3.1 0 19 a'=2; +ctrl-era 0 18 9 1 8 3.3 15 5 a'=5;c,=2;a=1; +ctrl-era 0 16 14 1 13 3.2 1 23 a'=9;a=2;c,=1;b=1; +ctrl-era 0 7 3 1 2 3.1 10 1 c,=1;a'=1; +ctrl-era 0 12 5 1 4 3.0 0 10 a'=3;c,=1; +ctrl-era 0 20 8 1 7 3.2 8 11 a'=5;a=2; +ctrl-era 0 11 23 1 22 3.0 4 16 a'=15;c,=5;b=1;a=1; +ctrl-era 0 19 14 1 13 3.5 1 3 a'=7;a=3;c,=2;b=1; +ctrl-era 0 23 3 1 2 2.9 12 10 a'=2; +ctrl-era 0 22 18 1 17 3.3 15 12 a'=10;c,=4;a=3; +ctrl-era 0 26 2 1 1 2.8 2 0 a'=1; +ctrl-era 0 27 9 1 8 5.9 12 21 a'=7;a=1; +ctrl-era 0 21 1 1 0 3.0 2 6 +ctrl-era 0 24 12 1 11 2.7 11 10 a'=9;c,=2; +ctrl-era 0 30 3 1 2 3.4 12 21 a'=2; +ctrl-era 0 31 2 1 1 3.0 13 7 c,=1; +ctrl-era 1 1 10 1 9 3.2 6 19 a'=7;c,=2; +ctrl-era 1 2 6 1 5 2.9 7 3 a'=4;c,=1; +ctrl-era 0 29 3 1 2 2.8 14 24 c,=1;a'=1; +ctrl-era 0 25 4 1 3 2.9 12 5 c,=1;b=1;a'=1; +ctrl-era 1 6 9 1 8 2.9 2 2 a'=7;a=1; +ctrl-era 1 3 17 1 16 3.0 8 13 a'=11;c,=3;a=2; +ctrl-era 1 9 7 1 6 3.4 0 19 a'=5;a=1; +ctrl-era 0 28 3 1 2 3.3 9 19 c,=1;a'=1; +ctrl-era 1 0 1 1 0 2.8 8 22 +ctrl-era 1 5 4 1 3 2.9 12 14 a'=2;c,=1; +ctrl-era 1 7 3 1 2 3.3 15 8 c,=1;a'=1; +ctrl-era 1 8 3 1 2 3.4 1 9 a'=2; +ctrl-era 1 11 2 1 1 4.0 11 1 a'=1; +ctrl-era 1 4 1 1 0 3.0 7 23 +ctrl-era 1 10 18 1 17 3.4 10 17 a'=8;c,=6;a=2;c=1; +ctrl-era 1 14 6 1 5 2.8 7 21 c,=2;a'=2;a=1; +ctrl-era 1 12 5 1 4 2.7 1 14 a'=3;c,=1; +ctrl-era 1 19 14 1 13 3.0 13 5 a'=7;a=3;c,=2;b=1; +ctrl-era 1 13 2 1 1 3.7 12 20 a=1; +ctrl-era 1 15 4 1 3 3.4 12 7 c,=1;b=1;a'=1; +ctrl-era 1 18 9 1 8 3.3 8 12 a'=5;c,=2;a=1; +ctrl-era 1 22 9 1 8 2.8 9 4 a'=5;a=2;c,=1; +ctrl-era 1 23 3 1 2 3.5 3 26 a'=2; +ctrl-era 1 17 1 1 0 3.2 4 24 +ctrl-era 1 21 1 1 0 3.1 5 5 +ctrl-era 1 24 12 1 11 3.6 11 10 a'=9;c,=2; +ctrl-era 1 20 8 1 7 3.7 0 6 a'=5;a=2; +ctrl-era 1 16 14 1 13 3.7 5 17 a'=9;a=2;c,=1;b=1; +ctrl-era 1 25 4 1 3 2.9 14 27 c,=1;b=1;a'=1; +ctrl-era 1 29 3 1 2 3.4 8 18 c,=1;a'=1; +ctrl-era 2 0 1 1 0 3.0 10 22 +ctrl-era 1 27 16 1 15 3.1 13 2 a'=11;c,=3;a=1; +ctrl-era 2 1 3 1 2 3.5 15 5 a'=2; +ctrl-era 1 30 3 1 2 3.1 0 25 a'=2; +ctrl-era 1 28 3 1 2 3.2 3 3 c,=1;a'=1; +ctrl-era 1 26 2 1 1 2.8 1 2 a'=1; +ctrl-era 2 3 1 1 0 3.0 4 5 +ctrl-era 1 31 2 1 1 3.0 11 11 c,=1; +ctrl-era 2 2 4 1 3 3.1 7 2 a'=3; +ctrl-era 2 6 9 1 8 2.8 8 16 a'=7;a=1; +ctrl-era 2 13 2 1 1 2.8 14 23 a=1; +ctrl-era 2 11 2 1 1 4.0 0 0 a'=1; +ctrl-era 2 7 1 1 0 4.3 13 0 +ctrl-era 2 5 3 1 2 2.8 8 24 a'=2; +ctrl-era 2 4 1 1 0 3.3 0 3 +ctrl-era 2 16 9 1 8 3.4 6 16 a'=5;a=2;b=1; +ctrl-era 2 8 3 1 2 3.4 6 8 a'=2; +ctrl-era 2 12 1 1 0 3.7 3 0 +ctrl-era 2 18 5 1 4 3.4 13 19 a'=3;a=1; +ctrl-era 2 15 2 1 1 3.1 6 0 b=1; +ctrl-era 2 10 2 1 1 3.0 9 3 c,=1; +ctrl-era 2 9 7 1 6 3.2 14 6 a'=5;a=1; +ctrl-era 2 14 6 1 5 2.7 9 22 c,=2;a'=2;a=1; +ctrl-era 2 17 1 1 0 3.5 3 11 +ctrl-era 2 20 8 1 7 3.1 3 17 a'=5;a=2; +ctrl-era 2 22 9 1 8 3.4 1 1 a'=5;a=2;c,=1; +ctrl-era 2 19 10 1 9 3.4 0 12 a'=5;a=2;c,=1;b=1; +ctrl-era 3 0 1 1 0 2.9 1 11 +ctrl-era 2 24 8 1 7 3.8 13 22 a'=7; +ctrl-era 2 21 1 1 0 2.9 7 25 +ctrl-era 2 27 9 1 8 3.1 7 14 a'=7;a=1; +ctrl-era 2 23 3 1 2 3.8 1 18 a'=2; +ctrl-era 2 30 3 1 2 3.3 1 21 a'=2; +ctrl-era 2 29 1 1 0 2.8 6 16 +ctrl-era 2 26 2 1 1 3.3 3 7 a'=1; +ctrl-era 2 25 1 1 0 3.2 7 17 +ctrl-era 2 31 1 1 0 5.9 2 0 +ctrl-era 3 2 4 1 3 2.8 14 21 a'=3; +ctrl-era 2 28 2 1 1 3.1 0 0 a'=1; +ctrl-era 3 1 10 1 9 3.1 4 1 a'=7;c,=2; +ctrl-era 3 3 1 1 0 3.2 4 26 +ctrl-era 3 5 4 1 3 3.2 13 12 a'=2;c,=1; +ctrl-era 3 6 9 1 8 3.1 9 17 a'=7;a=1; +ctrl-era 3 4 1 1 0 3.7 4 16 +ctrl-era 3 7 3 1 2 3.3 10 11 c,=1;a'=1; +ctrl-era 3 8 3 1 2 3.4 10 8 a'=2; +ctrl-era 3 9 7 1 6 3.2 5 1 a'=5;a=1; +ctrl-era 3 14 6 1 5 2.8 12 4 c,=2;a'=2;a=1; +ctrl-era 3 11 22 1 21 5.0 5 0 a'=15;c,=4;b=1;a=1; +ctrl-era 3 10 18 1 17 3.4 11 25 a'=8;c,=6;a=2;c=1; +ctrl-era 3 16 14 1 13 3.5 7 24 a'=9;a=2;c,=1;b=1; +ctrl-era 3 15 4 1 3 2.7 9 3 c,=1;b=1;a'=1; +ctrl-era 3 13 2 1 1 4.1 4 1 a=1; +ctrl-era 3 12 5 1 4 3.2 1 11 a'=3;c,=1; +ctrl-era 3 17 1 1 0 3.0 0 7 +ctrl-era 3 18 5 1 4 3.7 1 2 a'=3;a=1; +ctrl-era 3 20 8 1 7 3.0 6 6 a'=5;a=2; +ctrl-era 3 19 10 1 9 3.2 6 13 a'=5;a=2;c,=1;b=1; +ctrl-era 3 21 1 1 0 2.8 6 3 +ctrl-era 3 22 9 1 8 3.5 9 11 a'=5;a=2;c,=1; +ctrl-era 3 26 2 1 1 3.0 6 18 a'=1; +ctrl-era 3 24 8 1 7 3.1 5 1 a'=7; +ctrl-era 3 23 3 1 2 2.8 2 22 a'=2; +ctrl-era 3 29 1 1 0 3.0 4 8 +ctrl-era 3 25 4 1 3 2.7 7 6 c,=1;b=1;a'=1; +ctrl-era 3 27 12 1 11 5.5 5 0 a'=9;c,=1;a=1; +ctrl-era 3 28 3 1 2 3.0 5 1 c,=1;a'=1; +ctrl-era 3 30 3 1 2 3.1 6 4 a'=2; +ctrl-era 3 31 2 1 1 3.5 11 3 c,=1; +ctrl-era 4 1 10 1 9 3.4 9 3 a'=7;c,=2; +ctrl-era 4 0 1 1 0 3.0 15 20 +ctrl-era 4 2 6 1 5 3.0 11 3 a'=4;c,=1; +ctrl-era 4 4 1 1 0 3.2 5 19 +ctrl-era 4 3 17 1 16 3.4 10 14 a'=11;c,=3;a=2; +ctrl-era 4 5 4 1 3 3.2 10 25 a'=2;c,=1; +ctrl-era 4 7 3 1 2 3.1 3 10 c,=1;a'=1; +ctrl-era 4 6 9 1 8 3.4 12 2 a'=7;a=1; +ctrl-era 4 8 3 1 2 3.4 7 3 a'=2; +ctrl-era 4 10 18 1 17 2.9 0 26 a'=8;c,=6;a=2;c=1; +ctrl-era 4 9 7 1 6 3.0 4 9 a'=5;a=1; +ctrl-era 4 11 2 1 1 3.5 9 8 a'=1; +ctrl-era 4 13 2 1 1 3.5 10 1 a=1; +ctrl-era 4 14 6 1 5 3.9 15 1 c,=2;a'=2;a=1; +ctrl-era 4 12 5 1 4 3.3 7 15 a'=3;c,=1; +ctrl-era 4 16 14 1 13 3.7 13 7 a'=9;a=2;c,=1;b=1; +ctrl-era 4 15 4 1 3 3.2 1 25 c,=1;b=1;a'=1; +ctrl-era 4 17 1 1 0 3.7 10 25 +ctrl-era 4 18 9 1 8 2.9 9 24 a'=5;c,=2;a=1; +ctrl-era 4 19 14 1 13 3.4 0 11 a'=7;a=3;c,=2;b=1; +ctrl-era 4 22 9 1 8 3.4 14 7 a'=5;a=2;c,=1; +ctrl-era 4 26 2 1 1 3.5 15 22 a'=1; +ctrl-era 4 20 8 1 7 3.6 0 10 a'=5;a=2; +ctrl-era 4 21 1 1 0 3.1 11 20 +ctrl-era 4 25 4 1 3 3.2 13 20 c,=1;b=1;a'=1; +ctrl-era 4 23 3 1 2 3.3 5 8 a'=2; +ctrl-era 4 24 12 1 11 2.8 2 25 a'=9;c,=2; +ctrl-era 4 27 16 1 15 2.9 6 4 a'=11;c,=3;a=1; +ctrl-era 4 29 3 1 2 3.2 7 12 c,=1;a'=1; +ctrl-era 4 28 3 1 2 3.2 6 10 c,=1;a'=1; +ctrl-era 4 30 3 1 2 2.9 2 11 a'=2; +ctrl-era 4 31 2 1 1 3.4 15 22 c,=1; +ctrl-era 5 1 10 1 9 3.2 3 6 a'=7;c,=2; +ctrl-era 5 0 1 1 0 3.1 4 25 +ctrl-era 5 2 6 1 5 3.2 5 2 a'=4;c,=1; +ctrl-era 5 3 17 1 16 3.9 14 12 a'=11;c,=3;a=2; +ctrl-era 5 5 4 1 3 3.3 5 24 a'=2;c,=1; +ctrl-era 5 8 3 1 2 3.3 13 15 a'=2; +ctrl-era 5 4 1 1 0 3.2 15 16 +ctrl-era 5 6 9 1 8 2.6 4 2 a'=7;a=1; +ctrl-era 5 7 3 1 2 2.8 4 17 c,=1;a'=1; +ctrl-era 5 9 7 1 6 3.2 1 2 a'=5;a=1; +ctrl-era 5 11 2 1 1 3.1 9 22 a'=1; +ctrl-era 5 10 18 1 17 2.8 6 4 a'=8;c,=6;a=2;c=1; +ctrl-era 5 14 6 1 5 3.5 5 21 c,=2;a'=2;a=1; +ctrl-era 5 13 2 1 1 3.2 15 4 a=1; +ctrl-era 5 12 5 1 4 3.2 9 7 a'=3;c,=1; +ctrl-era 5 15 4 1 3 2.8 11 9 c,=1;b=1;a'=1; +ctrl-era 5 16 14 1 13 3.5 4 10 a'=9;a=2;c,=1;b=1; +ctrl-era 5 17 1 1 0 3.3 12 7 +ctrl-era 5 18 9 1 8 3.0 10 14 a'=5;c,=2;a=1; +ctrl-era 5 20 8 1 7 3.5 4 7 a'=5;a=2; +ctrl-era 5 21 1 1 0 2.8 11 5 +ctrl-era 5 22 9 1 8 3.1 13 10 a'=5;a=2;c,=1; +ctrl-era 5 19 14 1 13 3.2 8 0 a'=7;a=3;c,=2;b=1; +ctrl-era 5 23 3 1 2 2.9 9 5 a'=2; +ctrl-era 5 24 12 1 11 2.8 9 8 a'=9;c,=2; +ctrl-era 5 25 4 1 3 3.1 13 16 c,=1;b=1;a'=1; +ctrl-era 5 27 16 1 15 3.2 11 23 a'=11;c,=3;a=1; +ctrl-era 5 26 2 1 1 3.2 13 26 a'=1; +ctrl-era 5 29 3 1 2 3.3 0 24 c,=1;a'=1; +ctrl-era 5 28 3 1 2 3.3 12 17 c,=1;a'=1; +ctrl-era 5 30 3 1 2 2.8 9 14 a'=2; +ctrl-era 6 1 10 1 9 3.0 15 17 a'=7;c,=2; +ctrl-era 5 31 2 1 1 3.4 5 23 c,=1; +ctrl-era 6 0 1 1 0 3.0 12 1 +ctrl-era 6 2 6 1 5 3.1 15 3 a'=4;c,=1; +ctrl-era 6 3 17 1 16 3.5 11 0 a'=11;c,=3;a=2; +ctrl-era 6 4 1 1 0 3.4 2 15 +ctrl-era 6 5 4 1 3 4.4 2 13 a'=2;c,=1; +ctrl-era 6 6 9 1 8 3.6 7 19 a'=7;a=1; +ctrl-era 6 8 3 1 2 3.3 9 13 a'=2; +ctrl-era 6 7 3 1 2 2.8 9 25 c,=1;a'=1; +ctrl-era 6 9 7 1 6 3.2 1 6 a'=5;a=1; +ctrl-era 6 11 23 1 22 2.8 0 24 a'=15;c,=5;b=1;a=1; +ctrl-era 6 10 18 1 17 3.7 5 2 a'=8;c,=6;a=2;c=1; +ctrl-era 6 13 2 1 1 3.3 2 18 a=1; +ctrl-era 6 14 6 1 5 2.9 5 27 c,=2;a'=2;a=1; +ctrl-era 6 12 5 1 4 3.1 7 25 a'=3;c,=1; +ctrl-era 6 16 14 1 13 3.1 11 20 a'=9;a=2;c,=1;b=1; +ctrl-era 6 15 4 1 3 2.8 5 13 c,=1;b=1;a'=1; +ctrl-era 6 17 1 1 0 2.8 4 24 +ctrl-era 6 18 9 1 8 3.5 3 25 a'=5;c,=2;a=1; +ctrl-era 6 19 14 1 13 3.3 13 12 a'=7;a=3;c,=2;b=1; +ctrl-era 6 21 1 1 0 3.4 11 1 +ctrl-era 6 20 8 1 7 4.9 0 3 a'=5;a=2; +ctrl-era 6 22 9 1 8 2.8 5 18 a'=5;a=2;c,=1; +ctrl-era 6 23 3 1 2 2.8 8 7 a'=2; +ctrl-era 6 24 12 1 11 3.6 12 6 a'=9;c,=2; +ctrl-era 6 25 4 1 3 2.8 12 7 c,=1;b=1;a'=1; +ctrl-era 6 27 16 1 15 2.9 2 15 a'=11;c,=3;a=1; +ctrl-era 6 26 2 1 1 3.3 0 0 a'=1; +ctrl-era 6 29 3 1 2 2.7 8 13 c,=1;a'=1; +ctrl-era 6 30 3 1 2 3.5 9 22 a'=2; +ctrl-era 6 28 3 1 2 3.5 3 23 c,=1;a'=1; +ctrl-era 6 31 2 1 1 3.0 8 16 c,=1; +ctrl-era 7 0 1 1 0 3.1 9 1 +ctrl-era 7 1 3 1 2 2.9 15 1 a'=2; +ctrl-era 7 2 4 1 3 3.1 14 23 a'=3; +ctrl-era 7 5 3 1 2 2.8 13 0 a'=2; +ctrl-era 7 3 5 1 4 3.5 4 3 a'=2;c,=1;a=1; +ctrl-era 7 6 9 1 8 2.9 5 6 a'=7;a=1; +ctrl-era 7 4 1 1 0 3.5 2 0 +ctrl-era 7 7 1 1 0 2.7 15 2 +ctrl-era 7 8 3 1 2 2.8 9 21 a'=2; +ctrl-era 7 9 7 1 6 3.0 13 21 a'=5;a=1; +ctrl-era 7 11 2 1 1 3.2 7 16 a'=1; +ctrl-era 7 10 2 1 1 3.2 13 12 c,=1; +ctrl-era 7 14 6 1 5 3.6 9 20 c,=2;a'=2;a=1; +ctrl-era 7 12 1 1 0 2.9 3 0 +ctrl-era 7 13 2 1 1 3.8 13 25 a=1; +ctrl-era 7 15 4 1 3 4.1 0 3 c,=1;b=1;a'=1; +ctrl-era 7 16 9 1 8 2.8 4 15 a'=5;a=2;b=1; +ctrl-era 7 17 1 1 0 3.2 4 7 +ctrl-era 7 18 9 1 8 3.3 10 17 a'=5;c,=2;a=1; +ctrl-era 7 19 14 1 13 2.5 15 0 a'=7;a=3;c,=2;b=1; +ctrl-era 7 21 1 1 0 3.5 8 10 +ctrl-era 7 20 8 1 7 3.7 15 16 a'=5;a=2; +ctrl-era 7 22 9 1 8 3.5 9 18 a'=5;a=2;c,=1; +ctrl-era 7 23 3 1 2 2.9 13 8 a'=2; +ctrl-era 7 24 8 1 7 2.7 11 11 a'=7; +ctrl-era 7 27 9 1 8 3.5 0 2 a'=7;a=1; +ctrl-era 7 26 2 1 1 3.2 13 17 a'=1; +ctrl-era 7 29 3 1 2 3.3 11 21 c,=1;a'=1; +ctrl-era 7 25 4 1 3 3.2 3 21 c,=1;b=1;a'=1; +ctrl-era 7 30 3 1 2 3.6 12 14 a'=2; +ctrl-era 7 28 3 1 2 3.4 0 20 c,=1;a'=1; +ctrl-era 7 31 1 1 0 3.5 10 16 +# end 2026-10-08T13:02:25Z rows=257 diff --git a/docs/analysis/class-v6/logs/census/ctrl-none.tsv b/docs/analysis/class-v6/logs/census/ctrl-none.tsv new file mode 100644 index 000000000..b6e23ece0 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/ctrl-none.tsv @@ -0,0 +1,258 @@ +# ctrl-none class mx8+sh256x27 eras [none] seeds 256 era-widths 4 weights base bittest off bin d601098699840534 start 2026-10-08T12:45:46Z host igneum-build-3 threads 8 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +ctrl-none none 1 3 1 2 26.4 10 0 a'=2; +ctrl-none none 4 1 1 0 91.3 2 0 +ctrl-none none 0 1 1 0 41.3 0 0 +ctrl-none none 3 1 1 0 28.7 1 0 +ctrl-none none 5 1 1 0 3.0 10 19 +ctrl-none none 6 3 1 2 67.3 6 0 a'=2; +ctrl-none none 7 4 1 3 31.5 3 0 a'=3; +ctrl-none none 2 3 1 2 3.2 13 8 a'=2; +ctrl-none none 8 1 1 0 64.8 1 0 +ctrl-none none 12 1 1 0 77.0 0 0 +ctrl-none none 9 11 1 10 5.5 3 4 a'=10; +ctrl-none none 15 1 1 0 63.1 14 0 +ctrl-none none 14 1 1 0 3.2 3 23 +ctrl-none none 13 4 1 3 44.2 4 0 a'=3; +ctrl-none none 11 3 1 2 51.1 14 0 a'=1;a=1; +ctrl-none none 10 3 1 2 8.3 0 0 c'''=1;a'=1; +ctrl-none none 16 2 1 1 4.0 3 18 a'=1; +ctrl-none none 20 5 1 4 30.9 11 0 a'=3;a=1; +ctrl-none none 22 3 1 2 63.9 9 0 a'=2; +ctrl-none none 21 2 1 1 32.5 3 0 a'=1; +ctrl-none none 19 4 1 3 3.0 13 23 a'=2;a=1; +ctrl-none none 17 1 1 0 2.9 4 25 +ctrl-none none 18 8 1 7 3.6 7 10 a'=6;c''=1; +ctrl-none none 23 2 1 1 3.4 5 15 a'=1; +ctrl-none none 24 1 1 0 32.3 7 0 +ctrl-none none 25 1 1 0 3.3 1 2 +ctrl-none none 27 1 1 0 3.0 8 25 +ctrl-none none 26 1 1 0 2.9 9 13 +ctrl-none none 29 3 1 2 36.8 1 0 b=1;a'=1; +ctrl-none none 28 1 1 0 2.8 13 0 +ctrl-none none 31 1 1 0 2.8 4 5 +ctrl-none none 30 2 1 1 64.2 6 0 a'=1; +ctrl-none none 32 1 1 0 3.0 8 17 +ctrl-none none 33 1 1 0 5.3 7 0 +ctrl-none none 34 3 1 2 64.5 8 0 a'=2; +ctrl-none none 35 2 1 1 63.9 14 0 a=1; +ctrl-none none 36 2 1 1 63.6 7 0 a'=1; +ctrl-none none 37 3 1 2 6.4 1 1 a'=2; +ctrl-none none 39 3 1 2 64.7 11 0 a'=1;a=1; +ctrl-none none 38 8 1 7 3.8 2 4 a'=7; +ctrl-none none 40 1 1 0 9.2 8 0 +ctrl-none none 41 1 1 0 33.0 6 0 +ctrl-none none 42 2 1 1 2.8 3 4 a'=1; +ctrl-none none 43 2 1 1 24.2 5 0 a'=1; +ctrl-none none 44 1 1 0 30.9 8 0 +ctrl-none none 45 2 1 1 33.0 13 0 a'=1; +ctrl-none none 47 11 1 10 2.9 13 19 a'=10; +ctrl-none none 46 1 1 0 3.3 12 20 +ctrl-none none 48 2 1 1 14.3 0 0 a'=1; +ctrl-none none 49 6 1 5 3.4 12 3 a'=4;b=1; +ctrl-none none 50 7 1 6 30.6 7 0 a'=4;b=1;a=1; +ctrl-none none 52 1 1 0 2.8 10 27 +ctrl-none none 53 6 1 5 46.0 6 1 a'=4;b=1; +ctrl-none none 51 5 1 4 37.0 0 0 a'=2;c''=1;a=1; +ctrl-none none 54 3 1 2 64.0 11 0 a'=1;a=1; +ctrl-none none 55 7 1 6 14.9 0 0 a'=6; +ctrl-none none 56 5 1 4 31.2 5 0 a'=4; +ctrl-none none 58 1 1 0 3.0 3 19 +ctrl-none none 57 2 1 1 15.3 15 1 a'=1; +ctrl-none none 59 3 1 2 63.9 3 0 a'=2; +ctrl-none none 60 5 1 4 3.2 7 11 a'=2;b=1;a=1; +ctrl-none none 61 3 1 2 3.0 4 1 a'=2; +ctrl-none none 63 1 1 0 97.1 3 0 +ctrl-none none 62 4 1 3 63.9 14 0 a'=2;a=1; +ctrl-none none 64 1 1 0 28.7 6 1 +ctrl-none none 66 2 1 1 55.7 1 0 a'=1; +ctrl-none none 65 1 1 0 21.1 0 0 +ctrl-none none 67 1 1 0 61.6 3 0 +ctrl-none none 68 3 1 2 3.4 15 14 a'=1;a=1; +ctrl-none none 71 5 1 4 3.2 9 1 a'=4; +ctrl-none none 69 2 1 1 3.5 1 19 a'=1; +ctrl-none none 70 4 1 3 64.2 15 0 a'=2;a=1; +ctrl-none none 72 1 1 0 63.9 7 0 +ctrl-none none 74 2 1 1 68.5 11 0 a'=1; +ctrl-none none 73 4 1 3 2.9 6 14 a'=3; +ctrl-none none 75 1 1 0 32.4 4 0 +ctrl-none none 76 2 1 1 31.7 5 0 b=1; +ctrl-none none 78 4 1 3 55.8 0 0 a'=3; +ctrl-none none 79 3 1 2 64.0 9 0 b=1;a'=1; +ctrl-none none 77 5 1 4 3.0 14 21 a'=4; +ctrl-none none 80 3 1 2 30.9 14 0 a'=2; +ctrl-none none 81 2 1 1 3.5 1 14 a'=1; +ctrl-none none 82 4 1 3 63.4 0 0 a'=2;a=1; +ctrl-none none 83 5 1 4 2.8 10 1 a'=4; +ctrl-none none 84 1 1 0 2.8 11 22 +ctrl-none none 85 1 1 0 3.3 8 6 +ctrl-none none 86 1 1 0 31.3 7 4 +ctrl-none none 87 1 1 0 62.1 4 0 +ctrl-none none 88 2 1 1 65.8 10 0 a'=1; +ctrl-none none 90 2 1 1 64.0 6 0 a'=1; +ctrl-none none 91 2 1 1 64.1 10 0 a=1; +ctrl-none none 92 7 1 6 63.0 1 0 a'=3;a=2;c=1; +ctrl-none none 89 19 1 18 2.9 5 8 a'=14;a=2;c''=1;b=1; +ctrl-none none 94 4 1 3 3.8 3 0 a'=3; +ctrl-none none 95 2 1 1 8.0 3 0 a'=1; +ctrl-none none 96 2 1 1 39.7 9 0 a'=1; +ctrl-none none 93 4 1 3 3.0 5 11 a'=2;c''=1; +ctrl-none none 97 4 1 3 3.2 14 16 a'=3; +ctrl-none none 99 1 1 0 3.4 0 26 +ctrl-none none 98 2 1 1 3.1 8 0 a'=1; +ctrl-none none 100 3 1 2 3.1 4 6 a'=1;a=1; +ctrl-none none 102 2 1 1 31.9 14 0 a'=1; +ctrl-none none 101 2 1 1 8.4 14 0 a'=1; +ctrl-none none 103 4 1 3 2.8 15 6 a'=3; +ctrl-none none 104 4 1 3 2.9 4 8 a'=3; +ctrl-none none 105 3 1 2 5.0 10 27 a'=2; +ctrl-none none 106 1 1 0 3.2 5 15 +ctrl-none none 107 7 1 6 63.8 5 0 a'=5;a=1; +ctrl-none none 108 2 1 1 2.9 7 11 a'=1; +ctrl-none none 109 1 1 0 2.8 1 4 +ctrl-none none 110 3 1 2 3.6 0 7 a'=2; +ctrl-none none 112 1 1 0 2.8 9 27 +ctrl-none none 111 4 1 3 64.1 15 0 a'=3; +ctrl-none none 113 1 1 0 27.4 0 0 +ctrl-none none 114 3 1 2 4.6 2 1 b=1;a'=1; +ctrl-none none 115 5 1 4 70.0 4 0 a'=3;a=1; +ctrl-none none 116 2 1 1 15.3 15 1 c=1; +ctrl-none none 117 1 1 0 3.2 6 17 +ctrl-none none 118 1 1 0 2.6 9 0 +ctrl-none none 120 5 1 4 78.0 4 0 a'=4; +ctrl-none none 119 6 1 5 3.1 8 22 a'=5; +ctrl-none none 121 3 1 2 63.0 0 0 a'=1;a=1; +ctrl-none none 122 1 1 0 3.3 10 20 +ctrl-none none 123 4 1 3 2.8 9 1 a'=3; +ctrl-none none 124 2 1 1 2.5 6 20 a'=1; +ctrl-none none 125 8 1 7 3.0 6 18 a'=7; +ctrl-none none 126 3 1 2 3.5 9 16 a'=2; +ctrl-none none 128 2 1 1 15.8 14 26 a'=1; +ctrl-none none 127 4 1 3 3.0 7 24 a'=3; +ctrl-none none 129 2 1 1 64.4 7 0 a=1; +ctrl-none none 130 1 1 0 3.4 8 25 +ctrl-none none 131 1 1 0 32.4 14 0 +ctrl-none none 132 2 1 1 3.5 11 7 a'=1; +ctrl-none none 133 6 1 5 63.6 11 0 a'=5; +ctrl-none none 134 1 1 0 3.4 15 26 +ctrl-none none 135 3 1 2 31.0 9 0 a'=2; +ctrl-none none 136 2 1 1 41.0 3 0 a=1; +ctrl-none none 137 1 1 0 63.8 14 0 +ctrl-none none 139 1 1 0 3.2 7 1 +ctrl-none none 140 2 1 1 32.8 11 0 a'=1; +ctrl-none none 141 2 1 1 31.9 2 0 a'=1; +ctrl-none none 142 4 1 3 95.5 11 0 a'=3; +ctrl-none none 138 6 1 5 2.6 10 16 a'=3;c''=1;a=1; +ctrl-none none 143 3 1 2 64.5 12 0 a=2; +ctrl-none none 144 2 1 1 3.5 4 14 a'=1; +ctrl-none none 145 2 1 1 27.6 0 0 a'=1; +ctrl-none none 146 2 1 1 31.4 0 0 a'=1; +ctrl-none none 149 4 1 3 3.1 8 18 a'=3; +ctrl-none none 147 1 1 0 2.9 11 25 +ctrl-none none 148 5 1 4 63.2 12 0 a'=3;a=1; +ctrl-none none 150 5 1 4 9.1 3 1 a'=3;a=1; +ctrl-none none 152 2 1 1 2.8 4 23 a'=1; +ctrl-none none 151 3 1 2 32.5 9 0 a'=2; +ctrl-none none 153 2 1 1 3.0 15 2 a'=1; +ctrl-none none 154 1 1 0 14.2 4 0 +ctrl-none none 155 9 1 8 43.8 3 0 a'=5;b=2;a=1; +ctrl-none none 156 14 1 13 4.0 0 18 a'=10;a=3; +ctrl-none none 157 4 1 3 3.2 4 19 a'=3; +ctrl-none none 158 6 1 5 2.9 12 21 a'=3;a=2; +ctrl-none none 159 8 1 7 2.9 2 5 a'=7; +ctrl-none none 160 1 1 0 3.1 12 23 +ctrl-none none 161 2 1 1 64.2 7 0 a'=1; +ctrl-none none 162 1 1 0 32.6 8 1 +ctrl-none none 163 1 1 0 57.2 4 1 +ctrl-none none 165 2 1 1 64.3 4 0 b=1; +ctrl-none none 164 4 1 3 3.5 6 3 a'=2;b=1; +ctrl-none none 166 1 1 0 63.7 6 15 +ctrl-none none 168 3 1 2 63.7 13 0 a'=2; +ctrl-none none 167 3 1 2 3.0 1 3 a'=2; +ctrl-none none 170 5 1 4 3.1 11 10 a'=4; +ctrl-none none 171 4 1 3 3.2 14 23 a'=3; +ctrl-none none 172 6 1 5 2.8 13 6 a'=5; +ctrl-none none 169 5 1 4 8.2 0 0 a'=3;c''=1; +ctrl-none none 174 3 1 2 63.3 10 1 a'=1;a=1; +ctrl-none none 176 2 1 1 65.0 10 0 a'=1; +ctrl-none none 175 1 1 0 50.3 1 0 +ctrl-none none 173 4 1 3 64.6 10 0 c''=1;a'=1;a=1; +ctrl-none none 177 1 1 0 31.9 8 23 +ctrl-none none 178 6 1 5 2.8 14 6 a'=4;a=1; +ctrl-none none 179 3 1 2 2.7 6 20 a'=2; +ctrl-none none 180 1 1 0 3.4 5 7 +ctrl-none none 181 8 1 7 5.8 0 1 a'=6;a=1; +ctrl-none none 183 4 1 3 72.1 10 0 a'=3; +ctrl-none none 182 1 1 0 4.0 7 22 +ctrl-none none 184 2 1 1 3.9 10 20 a'=1; +ctrl-none none 185 1 1 0 3.1 6 19 +ctrl-none none 186 1 1 0 29.9 7 1 +ctrl-none none 187 2 1 1 3.6 12 18 a'=1; +ctrl-none none 188 1 1 0 19.2 0 3 +ctrl-none none 189 4 1 3 62.8 15 0 b=1;a'=1;a=1; +ctrl-none none 191 3 1 2 55.0 9 26 a'=2; +ctrl-none none 190 1 1 0 27.1 0 0 +ctrl-none none 192 3 1 2 3.6 15 23 b=1;a'=1; +ctrl-none none 193 6 1 5 18.4 0 0 a'=4;a=1; +ctrl-none none 194 1 1 0 16.2 13 0 +ctrl-none none 195 2 1 1 3.2 13 27 a'=1; +ctrl-none none 196 3 1 2 5.4 15 0 a'=2; +ctrl-none none 197 3 1 2 33.6 15 1 a'=2; +ctrl-none none 198 1 1 0 3.3 0 18 +ctrl-none none 199 3 1 2 64.5 11 0 a'=2; +ctrl-none none 200 1 1 0 28.3 9 1 +ctrl-none none 201 2 1 1 3.6 14 7 a'=1; +ctrl-none none 202 2 1 1 25.3 6 0 a'=1; +ctrl-none none 203 7 1 6 8.3 0 0 a'=5;b=1; +ctrl-none none 204 1 1 0 3.7 6 21 +ctrl-none none 205 1 1 0 4.0 2 9 +ctrl-none none 206 3 1 2 63.1 12 0 c=1;a'=1; +ctrl-none none 207 9 1 8 2.8 5 8 a'=8; +ctrl-none none 208 1 1 0 3.6 11 9 +ctrl-none none 209 2 1 1 21.5 13 3 a=1; +ctrl-none none 210 2 1 1 3.3 8 12 a'=1; +ctrl-none none 211 2 1 1 18.3 15 12 a'=1; +ctrl-none none 212 10 1 9 3.8 0 24 a'=7;a=2; +ctrl-none none 213 3 1 2 64.9 1 0 a'=2; +ctrl-none none 214 2 1 1 2.9 11 15 a'=1; +ctrl-none none 215 2 1 1 19.1 3 0 a'=1; +ctrl-none none 216 1 1 0 4.5 7 25 +ctrl-none none 217 5 1 4 14.2 8 0 a'=4; +ctrl-none none 219 2 1 1 3.3 10 15 a'=1; +ctrl-none none 218 1 1 0 16.7 1 0 +ctrl-none none 220 1 1 0 32.6 7 0 +ctrl-none none 221 8 1 7 31.9 8 0 a'=6;a=1; +ctrl-none none 222 1 1 0 32.2 4 1 +ctrl-none none 223 3 1 2 31.7 7 0 a=2; +ctrl-none none 224 2 1 1 51.2 0 0 a'=1; +ctrl-none none 227 1 1 0 3.3 5 13 +ctrl-none none 226 4 1 3 31.2 11 0 a'=2;a=1; +ctrl-none none 228 2 1 1 4.5 12 0 a'=1; +ctrl-none none 229 1 1 0 30.8 7 0 +ctrl-none none 225 5 1 4 13.0 1 0 a'=3;c''=1; +ctrl-none none 230 6 1 5 19.1 0 2 a'=4;c=1; +ctrl-none none 231 1 1 0 3.2 6 2 +ctrl-none none 232 4 1 3 3.2 9 9 a'=2;a=1; +ctrl-none none 233 2 1 1 34.4 3 2 a'=1; +ctrl-none none 234 5 1 4 2.8 9 11 a'=4; +ctrl-none none 236 7 1 6 3.5 4 11 a'=6; +ctrl-none none 235 2 1 1 65.6 3 0 a'=1; +ctrl-none none 237 1 1 0 64.5 3 0 +ctrl-none none 238 5 1 4 41.3 3 3 a'=3;b=1; +ctrl-none none 239 5 1 4 28.0 0 0 a'=4; +ctrl-none none 240 1 1 0 31.5 11 0 +ctrl-none none 241 1 1 0 3.9 9 27 +ctrl-none none 242 4 1 3 3.5 4 20 a'=2;a=1; +ctrl-none none 244 1 1 0 12.6 0 25 +ctrl-none none 243 3 1 2 3.3 15 10 a'=2; +ctrl-none none 245 5 1 4 15.6 2 1 a'=4; +ctrl-none none 246 7 1 6 3.7 12 17 a'=6; +ctrl-none none 247 1 1 0 63.4 10 0 +ctrl-none none 248 1 1 0 3.4 6 20 +ctrl-none none 249 1 1 0 50.8 0 0 +ctrl-none none 250 2 1 1 63.9 3 0 a'=1; +ctrl-none none 251 2 1 1 64.3 2 0 a'=1; +ctrl-none none 253 2 1 1 4.1 6 2 a'=1; +ctrl-none none 252 8 1 7 23.6 11 0 a'=5;a=2; +ctrl-none none 254 6 1 5 33.0 7 4 a'=4;b=1; +ctrl-none none 255 1 1 0 27.9 0 0 diff --git a/docs/analysis/class-v6/logs/census/uniform-a-none.tsv b/docs/analysis/class-v6/logs/census/uniform-a-none.tsv new file mode 100644 index 000000000..061a39389 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/uniform-a-none.tsv @@ -0,0 +1,17 @@ +class era seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads control_max reads +w64m8g+sh256x27 none 4 1 f4487c87cfff1e7a 1.04905 3 0.002380 0.002377 1.0010 26 29 134217728 +w64m8g+sh256x27 none 1 1 29d2bcaba2d8edf5 1.04882 5 0.002382 0.002381 1.0001 27 27 134217728 +w64m8g+sh256x27 none 2 4 5fb46883e180b9f5 1.04885 4 0.002379 0.002380 0.9999 27 29 134217728 +w64m8g+sh256x27 none 0 2 73d1382989a69a8d 1.04894 1 0.002383 0.002382 1.0002 30 27 134217728 +w64m8g+sh256x27 none 6 1 311d1351271e9ea5 1.04885 2 0.002384 0.002380 1.0019 27 28 134217728 +w64m8g+sh256x27 none 5 1 520307099e14103b 1.04903 6 0.002381 0.002379 1.0007 27 28 134217728 +w64m8g+sh256x27 none 7 0 3dc79646fedce4b4 1.04390 11 0.002379 0.002379 1.0000 27 27 134217728 +w64m8g+sh256x27 none 3 6 c10bff8bcd67ceed 1.04888 14 0.002380 0.002380 1.0001 27 28 134217728 +w64m8g+sh256x27 none 11 0 9d64aefadd7069ac 1.04904 0 0.002381 0.002382 0.9996 27 27 134217728 +w64m8g+sh256x27 none 8 1 f98d219ab657820c 1.04906 2 0.002379 0.002379 1.0001 28 27 134217728 +w64m8g+sh256x27 none 9 6 18c383d344cb8948 1.04903 1 0.002381 0.002380 1.0007 28 28 134217728 +w64m8g+sh256x27 none 14 8 0996f04d4debf93a 1.04706 12 0.002396 0.002382 1.0061 27 27 134217728 +w64m8g+sh256x27 none 10 6 d3683b954033a6f5 1.04879 0 0.002381 0.002381 0.9999 27 27 134217728 +w64m8g+sh256x27 none 12 0 bd25136fa86cfdbb 1.04890 4 0.002380 0.002381 0.9993 26 27 134217728 +w64m8g+sh256x27 none 13 1 6fe6ecb094a5a1f6 1.04892 4 0.002379 0.002383 0.9986 27 27 134217728 +w64m8g+sh256x27 none 15 2 a2a33a99967a47a1 1.04894 1 0.002382 0.002380 1.0010 28 27 134217728 diff --git a/docs/analysis/class-v6/logs/census/uniform-b-none.tsv b/docs/analysis/class-v6/logs/census/uniform-b-none.tsv new file mode 100644 index 000000000..9ef11cf90 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/uniform-b-none.tsv @@ -0,0 +1,17 @@ +class era seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads control_max reads +w16m8g+sh256x27 none 4 1 f555de19a14e4b82 1.00253 1 0.002380 0.002377 1.0011 29 29 134217728 +w16m8g+sh256x27 none 1 0 a3c5c857b3d36618 1.00256 0 0.002383 0.002381 1.0008 28 27 134217728 +w16m8g+sh256x27 none 6 1 3acc6704472bbd7d 1.00103 2 0.002381 0.002380 1.0005 28 28 134217728 +w16m8g+sh256x27 none 3 0 db87b6c4aeb9f99f 1.00098 9 0.002383 0.002380 1.0011 26 28 134217728 +w16m8g+sh256x27 none 5 0 e10be8f927a334d8 1.00242 12 0.002382 0.002379 1.0014 30 28 134217728 +w16m8g+sh256x27 none 0 1 48a93d5e5b931cd7 1.00257 14 0.002380 0.002382 0.9989 27 27 134217728 +w16m8g+sh256x27 none 7 0 e2e1dec77412f084 1.00109 0 0.002382 0.002379 1.0011 27 27 134217728 +w16m8g+sh256x27 none 2 4 41a382862fa1488d 1.00260 5 0.002379 0.002380 0.9999 27 29 134217728 +w16m8g+sh256x27 none 8 1 2ff06eec9e814c1c 1.00162 7 0.002385 0.002379 1.0024 27 27 134217728 +w16m8g+sh256x27 none 13 0 59f08545a01b9029 1.00256 7 0.002381 0.002383 0.9995 27 27 134217728 +w16m8g+sh256x27 none 9 3 6aebe5693cda1de5 0.98146 2 0.002398 0.002380 1.0077 28 28 134217728 +w16m8g+sh256x27 none 14 0 c6e829543c08c96c 1.00087 11 0.002379 0.002382 0.9990 26 27 134217728 +w16m8g+sh256x27 none 12 0 e3dee32001ff9ac3 1.00253 15 0.002380 0.002381 0.9996 27 27 134217728 +w16m8g+sh256x27 none 15 1 15cba5607ee486c4 1.00249 0 0.002381 0.002380 1.0005 26 27 134217728 +w16m8g+sh256x27 none 11 0 3f0276dd1258a6bc 1.00254 0 0.002384 0.002382 1.0007 28 27 134217728 +w16m8g+sh256x27 none 10 0 d7fa72b4b388d8e6 1.00257 13 0.002387 0.002381 1.0023 26 27 134217728 diff --git a/docs/analysis/class-v6/logs/census/uniform-c-none.tsv b/docs/analysis/class-v6/logs/census/uniform-c-none.tsv new file mode 100644 index 000000000..b046723ec --- /dev/null +++ b/docs/analysis/class-v6/logs/census/uniform-c-none.tsv @@ -0,0 +1,17 @@ +class era seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads control_max reads +w64m8g+sh256x27 none 4 1 f4487c87cfff1e7a 1.04901 11 0.002380 0.002377 1.0014 29 29 134217728 +w64m8g+sh256x27 none 3 0 8062f9568d273707 1.04899 9 0.002382 0.002380 1.0009 27 28 134217728 +w64m8g+sh256x27 none 2 4 5fb46883e180b9f5 1.04904 7 0.002382 0.002380 1.0010 27 29 134217728 +w64m8g+sh256x27 none 6 1 311d1351271e9ea5 1.04875 2 0.002379 0.002380 0.9998 27 28 134217728 +w64m8g+sh256x27 none 0 1 666d8cc2e6eff09f 1.04884 10 0.002380 0.002382 0.9989 26 27 134217728 +w64m8g+sh256x27 none 1 0 1f41501380e84428 1.04885 0 0.002383 0.002381 1.0005 27 27 134217728 +w64m8g+sh256x27 none 7 0 3dc79646fedce4b4 1.04899 13 0.002381 0.002379 1.0011 27 27 134217728 +w64m8g+sh256x27 none 5 0 0a30b71cd5a3dbe8 1.04894 9 0.002380 0.002379 1.0003 26 28 134217728 +w64m8g+sh256x27 none 8 1 f98d219ab657820c 1.04650 7 0.002382 0.002379 1.0013 27 27 134217728 +w64m8g+sh256x27 none 13 0 902c487ec9750b41 1.04906 4 0.002381 0.002383 0.9993 28 27 134217728 +w64m8g+sh256x27 none 11 0 9d64aefadd7069ac 1.04901 8 0.002380 0.002382 0.9990 26 27 134217728 +w64m8g+sh256x27 none 10 0 55078f515da6288e 1.04896 5 0.002380 0.002381 0.9996 29 27 134217728 +w64m8g+sh256x27 none 12 0 bd25136fa86cfdbb 1.04893 7 0.002382 0.002381 1.0002 30 27 134217728 +w64m8g+sh256x27 none 14 0 cb0d96f15e24881c 1.04881 11 0.002379 0.002382 0.9987 27 27 134217728 +w64m8g+sh256x27 none 15 1 e0536568562886f4 1.04813 0 0.002384 0.002380 1.0016 27 27 134217728 +w64m8g+sh256x27 none 9 6 18c383d344cb8948 1.04892 1 0.002381 0.002380 1.0008 27 28 134217728 diff --git a/docs/analysis/class-v6/logs/census/uniform-ctrl-none.tsv b/docs/analysis/class-v6/logs/census/uniform-ctrl-none.tsv new file mode 100644 index 000000000..665bc50d9 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/uniform-ctrl-none.tsv @@ -0,0 +1,17 @@ +class era seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads control_max reads +mx8+sh256x27 none 0 0 d11a312a6f1860d2 0.99743 0 0.002383 0.002382 1.0002 27 27 134217728 +mx8+sh256x27 none 7 3 545f5f5cdca1adaf 0.99872 3 0.002383 0.002379 1.0016 27 27 134217728 +mx8+sh256x27 none 3 0 63be26aa9e0323a7 0.99904 1 0.002382 0.002380 1.0010 27 28 134217728 +mx8+sh256x27 none 2 2 3a68098aed6c7f40 1.00011 2 0.002381 0.002380 1.0004 27 29 134217728 +mx8+sh256x27 none 1 2 6826db4d7d33105a 0.99794 4 0.002380 0.002381 0.9993 27 27 134217728 +mx8+sh256x27 none 5 0 bf6bf3b3bd2da848 1.00011 14 0.002381 0.002379 1.0008 27 28 134217728 +mx8+sh256x27 none 4 0 858b8d2dc6543f25 0.97224 2 0.002382 0.002377 1.0020 27 29 134217728 +mx8+sh256x27 none 6 2 46b2809292569495 0.99192 6 0.002380 0.002380 1.0000 28 28 134217728 +mx8+sh256x27 none 8 0 6c27b57978ee3352 0.99266 1 0.002381 0.002379 1.0010 27 27 134217728 +mx8+sh256x27 none 9 10 7eae27998eb8665a 1.00002 11 0.002380 0.002380 1.0001 27 28 134217728 +mx8+sh256x27 none 13 3 3d8b2bc39168cb7f 0.99793 4 0.002381 0.002383 0.9994 27 27 134217728 +mx8+sh256x27 none 11 2 ae67b4dd5251fb6a 0.99692 14 0.002380 0.002382 0.9992 27 27 134217728 +mx8+sh256x27 none 15 0 7164644d33b0a84e 0.99244 6 0.002402 0.002380 1.0094 28 27 134217728 +mx8+sh256x27 none 14 0 243233af6588fdfc 1.00008 10 0.002381 0.002382 0.9996 26 27 134217728 +mx8+sh256x27 none 12 0 54e35300fdd79c5b 0.99465 0 0.002381 0.002381 0.9999 27 27 134217728 +mx8+sh256x27 none 10 2 5236758d791df4cd 1.00006 1 0.002420 0.002381 1.0163 29 27 134217728 diff --git a/docs/analysis/class-v6/logs/census/uniform-w16-none.tsv b/docs/analysis/class-v6/logs/census/uniform-w16-none.tsv new file mode 100644 index 000000000..4fef4e2c5 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/uniform-w16-none.tsv @@ -0,0 +1,17 @@ +class era seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads control_max reads +w16m8g+sh256x27 none 5 1 78bcd6b9f7a6ad43 1.00262 10 0.002382 0.002379 1.0013 27 28 134217728 +w16m8g+sh256x27 none 1 1 0bc1d6adf0f97c8d 1.00095 5 0.002383 0.002381 1.0005 30 27 134217728 +w16m8g+sh256x27 none 2 4 41a382862fa1488d 1.00110 2 0.002383 0.002380 1.0014 27 29 134217728 +w16m8g+sh256x27 none 6 1 3acc6704472bbd7d 1.00096 2 0.002384 0.002380 1.0016 27 28 134217728 +w16m8g+sh256x27 none 4 1 f555de19a14e4b82 1.00251 11 0.002380 0.002377 1.0011 27 29 134217728 +w16m8g+sh256x27 none 0 2 54596ced0a2b0f05 1.00250 1 0.002386 0.002382 1.0014 28 27 134217728 +w16m8g+sh256x27 none 7 0 e2e1dec77412f084 0.99668 11 0.002381 0.002379 1.0009 27 27 134217728 +w16m8g+sh256x27 none 3 6 7fed1428f93b1a65 1.00255 7 0.002380 0.002380 0.9998 27 28 134217728 +w16m8g+sh256x27 none 8 1 2ff06eec9e814c1c 1.00249 11 0.002380 0.002379 1.0005 29 27 134217728 +w16m8g+sh256x27 none 11 0 3f0276dd1258a6bc 1.00244 3 0.002382 0.002382 1.0000 26 27 134217728 +w16m8g+sh256x27 none 10 6 b55755978e54358d 1.00258 14 0.002381 0.002381 1.0000 26 27 134217728 +w16m8g+sh256x27 none 12 0 e3dee32001ff9ac3 1.00251 13 0.002382 0.002381 1.0001 27 27 134217728 +w16m8g+sh256x27 none 14 8 9342c807b4b01b42 1.00198 12 0.002394 0.002382 1.0053 27 27 134217728 +w16m8g+sh256x27 none 13 1 2e19dbf83daa8bae 1.00258 14 0.002381 0.002383 0.9993 28 27 134217728 +w16m8g+sh256x27 none 9 6 36de958c90f91238 1.00249 14 0.002378 0.002380 0.9994 27 28 134217728 +w16m8g+sh256x27 none 15 2 87d31ccbad786389 1.00245 7 0.002380 0.002380 0.9999 28 27 134217728 diff --git a/docs/analysis/class-v6/logs/census/w16-era.tsv b/docs/analysis/class-v6/logs/census/w16-era.tsv new file mode 100644 index 000000000..20162bdd2 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/w16-era.tsv @@ -0,0 +1,259 @@ +# w16-era class w16m8g+sh256x27 eras [0,1,2,3,4,5,6,7] seeds 32 era-widths 16 weights base bittest 1 bin d601098699840534 start 2026-10-08T13:02:33Z host igneum-build-4 threads 16 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +w16-era 0 9 5 1 4 2.9 6 22 a'=3;c,=1; +w16-era 0 8 1 1 0 2.8 0 4 +w16-era 0 10 1 1 0 3.3 11 5 +w16-era 0 12 3 1 2 2.9 15 11 a'=2; +w16-era 0 14 13 1 12 3.1 6 24 a'=9;a=2;c,=1; +w16-era 0 0 2 1 1 3.2 2 11 a'=1; +w16-era 0 7 8 1 7 2.9 11 27 a'=5;c,=2; +w16-era 0 15 6 1 5 3.1 1 5 a'=3;c,=1;a=1; +w16-era 0 6 2 1 1 2.9 9 18 a'=1; +w16-era 0 11 9 1 8 2.8 0 7 c,=5;a'=3; +w16-era 0 3 2 1 1 3.1 13 9 a'=1; +w16-era 0 2 9 1 8 3.7 9 13 a'=7;a=1; +w16-era 0 4 9 1 8 3.0 10 7 a'=4;c,=3;a=1; +w16-era 0 13 1 1 0 2.7 8 17 +w16-era 0 5 14 1 13 3.1 3 13 a'=12;a=1; +w16-era 0 1 6 1 5 3.3 13 21 a'=4;c,=1; +w16-era 0 16 5 1 4 3.0 0 5 a'=4; +w16-era 0 17 3 1 2 3.5 15 12 a'=2; +w16-era 0 21 4 1 3 3.0 1 15 a'=3; +w16-era 0 20 8 1 7 2.6 13 27 a'=5;c,=1;a=1; +w16-era 0 25 6 1 5 3.0 12 2 c,=2;a=2;a'=1; +w16-era 0 23 7 1 6 3.7 1 22 a'=2;a=2;c,=1;c=1; +w16-era 0 19 5 1 4 3.1 3 2 a'=3;a=1; +w16-era 0 18 3 1 2 4.0 2 7 c,=2; +w16-era 0 22 6 1 5 3.0 9 4 a'=4;a=1; +w16-era 0 24 3 1 2 3.3 8 8 a'=2; +w16-era 0 28 15 1 14 3.5 13 25 a'=10;c,=2;a=2; +w16-era 0 26 2 1 1 3.1 11 12 a'=1; +w16-era 0 27 7 1 6 2.9 15 17 a'=6; +w16-era 0 29 4 1 3 2.6 15 10 c,=2;a'=1; +w16-era 0 30 8 1 7 3.5 13 18 a'=6;a=1; +w16-era 0 31 17 1 16 2.8 12 13 a'=7;c,=5;a=3;b=1; +w16-era 1 2 9 1 8 3.5 5 6 a'=7;a=1; +w16-era 1 0 2 1 1 4.0 14 13 a'=1; +w16-era 1 3 2 1 1 3.1 1 4 a'=1; +w16-era 1 1 6 1 5 2.9 15 5 a'=4;c,=1; +w16-era 1 5 14 1 13 5.5 2 7 a'=12;a=1; +w16-era 1 8 1 1 0 3.3 10 8 +w16-era 1 7 8 1 7 2.9 2 3 a'=5;c,=2; +w16-era 1 6 2 1 1 3.1 3 21 a'=1; +w16-era 1 4 12 1 11 3.4 3 22 a'=6;c,=4;a=1; +w16-era 1 9 5 1 4 2.8 5 15 a'=3;c,=1; +w16-era 1 10 1 1 0 3.2 12 16 +w16-era 1 12 3 1 2 3.0 7 20 a'=2; +w16-era 1 11 9 1 8 3.0 0 14 c,=5;a'=3; +w16-era 1 13 1 1 0 3.0 14 7 +w16-era 1 14 13 1 12 3.0 2 5 a'=9;a=2;c,=1; +w16-era 1 15 6 1 5 3.7 6 8 a'=3;c,=1;a=1; +w16-era 1 16 5 1 4 3.1 9 22 a'=4; +w16-era 1 17 3 1 2 2.9 14 6 a'=2; +w16-era 1 19 5 1 4 3.6 3 27 a'=3;a=1; +w16-era 1 18 3 1 2 2.8 8 11 c,=2; +w16-era 1 20 8 1 7 2.9 6 21 a'=5;c,=1;a=1; +w16-era 1 21 4 1 3 3.3 10 4 a'=3; +w16-era 1 24 3 1 2 2.8 13 21 a'=2; +w16-era 1 22 6 1 5 3.3 7 5 a'=4;a=1; +w16-era 1 23 4 1 3 3.6 0 8 c,=1;a'=1;a=1; +w16-era 1 25 6 1 5 3.1 4 8 c,=2;a=2;a'=1; +w16-era 1 27 7 1 6 2.7 10 7 a'=6; +w16-era 1 26 2 1 1 3.3 12 22 a'=1; +w16-era 1 28 15 1 14 3.0 12 6 a'=10;c,=2;a=2; +w16-era 1 29 4 1 3 3.2 2 11 c,=2;a'=1; +w16-era 1 30 41 1 40 3.3 0 6 a'=29;c,=8;a=2;b=1; +w16-era 1 31 17 1 16 3.2 10 3 a'=7;c,=5;a=3;b=1; +w16-era 2 0 2 1 1 3.5 6 26 a'=1; +w16-era 2 1 4 1 3 4.1 3 18 a'=3; +w16-era 2 2 9 1 8 3.7 8 10 a'=7;a=1; +w16-era 2 4 2 1 1 3.2 8 22 a'=1; +w16-era 2 3 2 1 1 2.9 0 18 a'=1; +w16-era 2 5 14 1 13 3.1 7 10 a'=12;a=1; +w16-era 2 8 1 1 0 3.8 5 19 +w16-era 2 6 2 1 1 3.0 12 6 a'=1; +w16-era 2 7 4 1 3 2.9 13 4 a'=3; +w16-era 2 9 3 1 2 3.8 12 2 a'=2; +w16-era 2 10 1 1 0 2.8 3 19 +w16-era 2 11 2 1 1 3.2 8 9 a'=1; +w16-era 2 12 3 1 2 3.7 7 17 a'=2; +w16-era 2 13 1 1 0 3.1 1 19 +w16-era 2 14 5 1 4 4.4 15 2 a'=3;a=1; +w16-era 2 15 3 1 2 3.3 0 25 a'=2; +w16-era 2 16 5 1 4 2.9 13 26 a'=4; +w16-era 2 18 1 1 0 2.9 3 26 +w16-era 2 17 3 1 2 3.0 9 20 a'=2; +w16-era 2 20 7 1 6 3.0 12 2 a'=5;a=1; +w16-era 2 19 5 1 4 3.1 12 17 a'=3;a=1; +w16-era 2 21 4 1 3 3.2 11 17 a'=3; +w16-era 2 23 2 1 1 3.0 12 12 a=1; +w16-era 2 24 3 1 2 3.1 10 7 a'=2; +w16-era 2 22 6 1 5 2.8 0 4 a'=4;a=1; +w16-era 2 25 4 1 3 3.4 12 16 a=2;a'=1; +w16-era 2 26 2 1 1 3.2 14 22 a'=1; +w16-era 2 28 8 1 7 3.2 9 19 a'=5;a=2; +w16-era 2 27 7 1 6 3.1 5 11 a'=6; +w16-era 2 29 2 1 1 3.3 4 19 a'=1; +w16-era 2 30 8 1 7 3.3 8 7 a'=6;a=1; +w16-era 2 31 4 1 3 2.9 11 22 a'=2;b=1; +w16-era 3 0 2 1 1 3.5 9 11 a'=1; +w16-era 3 2 9 1 8 3.2 0 23 a'=7;a=1; +w16-era 3 1 4 1 3 2.6 10 26 a'=3; +w16-era 3 4 2 1 1 3.2 10 20 a'=1; +w16-era 3 3 2 1 1 3.9 4 4 a'=1; +w16-era 3 5 14 1 13 3.2 3 21 a'=12;a=1; +w16-era 3 6 2 1 1 3.2 6 19 a'=1; +w16-era 3 8 1 1 0 3.1 7 16 +w16-era 3 7 4 1 3 2.8 9 26 a'=3; +w16-era 3 9 3 1 2 3.2 3 11 a'=2; +w16-era 3 10 1 1 0 3.2 0 23 +w16-era 3 12 3 1 2 3.3 8 8 a'=2; +w16-era 3 11 2 1 1 3.2 13 22 a'=1; +w16-era 3 13 1 1 0 3.4 0 4 +w16-era 3 14 5 1 4 5.5 15 3 a'=3;a=1; +w16-era 3 15 3 1 2 3.5 11 17 a'=2; +w16-era 3 16 5 1 4 3.2 6 4 a'=4; +w16-era 3 17 3 1 2 3.1 3 14 a'=2; +w16-era 3 20 7 1 6 3.7 8 3 a'=5;a=1; +w16-era 3 18 1 1 0 3.0 11 7 +w16-era 3 19 5 1 4 3.1 10 11 a'=3;a=1; +w16-era 3 21 4 1 3 3.0 15 5 a'=3; +w16-era 3 23 2 1 1 3.0 11 8 a=1; +w16-era 3 24 3 1 2 3.7 0 19 a'=2; +w16-era 3 22 6 1 5 3.8 5 13 a'=4;a=1; +w16-era 3 28 8 1 7 4.9 9 2 a'=5;a=2; +w16-era 3 25 4 1 3 3.9 0 2 a=2;a'=1; +w16-era 3 27 7 1 6 3.2 6 5 a'=6; +w16-era 3 26 2 1 1 3.2 3 6 a'=1; +w16-era 3 29 2 1 1 3.1 7 2 a'=1; +w16-era 3 30 8 1 7 2.7 2 5 a'=6;a=1; +w16-era 3 31 10 1 9 5.0 10 2 a'=4;c,=2;a=2;b=1; +w16-era 4 0 2 1 1 3.0 6 11 a'=1; +w16-era 4 2 9 1 8 3.8 5 10 a'=7;a=1; +w16-era 4 1 6 1 5 3.6 0 10 a'=4;c,=1; +w16-era 4 3 2 1 1 3.1 10 15 a'=1; +w16-era 4 4 9 1 8 4.0 1 14 a'=4;c,=3;a=1; +w16-era 4 5 21 1 20 2.8 5 13 a'=15;c,=3;a=2; +w16-era 4 6 2 1 1 3.4 3 16 a'=1; +w16-era 4 8 1 1 0 3.4 1 5 +w16-era 4 11 9 1 8 3.8 8 23 c,=5;a'=3; +w16-era 4 7 8 1 7 2.7 7 16 a'=5;c,=2; +w16-era 4 9 5 1 4 3.0 2 3 a'=3;c,=1; +w16-era 4 10 1 1 0 3.6 0 15 +w16-era 4 12 3 1 2 2.8 11 14 a'=2; +w16-era 4 13 1 1 0 3.2 12 3 +w16-era 4 14 13 1 12 3.2 15 13 a'=9;a=2;c,=1; +w16-era 4 15 6 1 5 2.9 15 12 a'=3;c,=1;a=1; +w16-era 4 21 4 1 3 3.5 8 12 a'=3; +w16-era 4 24 3 1 2 2.9 2 17 a'=2; +w16-era 4 16 5 1 4 2.9 14 4 a'=4; +w16-era 4 27 7 1 6 2.9 2 13 a'=6; +w16-era 4 17 3 1 2 3.0 13 7 a'=2; +w16-era 4 29 4 1 3 2.7 5 18 c,=2;a'=1; +w16-era 4 22 6 1 5 3.2 2 18 a'=4;a=1; +w16-era 4 20 8 1 7 3.0 13 8 a'=5;c,=1;a=1; +w16-era 4 19 5 1 4 3.0 14 12 a'=3;a=1; +w16-era 4 18 3 1 2 3.0 8 13 c,=2; +w16-era 4 26 2 1 1 3.4 4 14 a'=1; +w16-era 4 28 15 1 14 3.5 12 10 a'=10;c,=2;a=2; +w16-era 4 25 6 1 5 3.2 12 20 c,=2;a=2;a'=1; +w16-era 4 23 36 1 35 3.9 1 2 a'=21;c,=9;a=4;c=1; +w16-era 4 30 41 1 40 3.4 8 12 a'=29;c,=8;a=2;b=1; +w16-era 4 31 17 1 16 2.8 15 4 a'=7;c,=5;a=3;b=1; +w16-era 5 1 6 1 5 3.6 11 15 a'=4;c,=1; +w16-era 5 7 8 1 7 2.5 15 25 a'=5;c,=2; +w16-era 5 5 21 1 20 5.2 9 18 a'=15;c,=3;a=2; +w16-era 5 2 9 1 8 3.0 5 22 a'=7;a=1; +w16-era 5 8 1 1 0 3.6 6 22 +w16-era 5 9 5 1 4 3.6 6 9 a'=3;c,=1; +w16-era 5 0 2 1 1 3.0 1 20 a'=1; +w16-era 5 4 9 1 8 3.2 0 11 a'=4;c,=3;a=1; +w16-era 5 10 1 1 0 3.2 1 4 +w16-era 5 3 2 1 1 2.7 14 13 a'=1; +w16-era 5 6 2 1 1 3.2 0 8 a'=1; +w16-era 5 15 6 1 5 3.1 0 18 a'=3;c,=1;a=1; +w16-era 5 12 3 1 2 3.3 10 23 a'=2; +w16-era 5 17 3 1 2 2.8 7 23 a'=2; +w16-era 5 11 9 1 8 3.1 13 25 c,=5;a'=3; +w16-era 5 13 1 1 0 3.0 4 23 +w16-era 5 16 5 1 4 3.3 15 12 a'=4; +w16-era 5 19 5 1 4 3.2 6 25 a'=3;a=1; +w16-era 5 14 13 1 12 3.3 6 23 a'=9;a=2;c,=1; +w16-era 5 24 3 1 2 2.7 8 2 a'=2; +w16-era 5 22 6 1 5 3.0 1 8 a'=4;a=1; +w16-era 5 21 4 1 3 3.1 13 9 a'=3; +w16-era 5 18 3 1 2 3.0 13 4 c,=2; +w16-era 5 26 2 1 1 3.1 3 20 a'=1; +w16-era 5 27 7 1 6 3.4 13 26 a'=6; +w16-era 5 20 8 1 7 3.2 1 4 a'=5;c,=1;a=1; +w16-era 5 28 15 1 14 4.3 12 22 a'=10;c,=2;a=2; +w16-era 5 29 4 1 3 3.4 3 23 c,=2;a'=1; +w16-era 5 23 4 1 3 3.4 7 27 c,=1;a'=1;a=1; +w16-era 5 25 6 1 5 3.4 9 24 c,=2;a=2;a'=1; +w16-era 6 1 6 1 5 3.8 0 3 a'=4;c,=1; +w16-era 6 0 2 1 1 3.5 10 6 a'=1; +w16-era 5 30 41 1 40 2.9 15 18 a'=29;c,=8;a=2;b=1; +w16-era 6 4 9 1 8 2.8 5 20 a'=4;c,=3;a=1; +w16-era 6 3 2 1 1 3.0 9 2 a'=1; +w16-era 6 8 1 1 0 3.2 14 18 +w16-era 5 31 17 1 16 3.5 2 5 a'=7;c,=5;a=3;b=1; +w16-era 6 6 2 1 1 3.8 11 11 a'=1; +w16-era 6 7 8 1 7 2.9 6 19 a'=5;c,=2; +w16-era 6 2 9 1 8 3.2 5 5 a'=7;a=1; +w16-era 6 5 21 1 20 3.0 2 23 a'=15;c,=3;a=2; +w16-era 6 9 5 1 4 3.1 12 10 a'=3;c,=1; +w16-era 6 14 13 1 12 3.5 6 5 a'=9;a=2;c,=1; +w16-era 6 13 1 1 0 3.0 12 12 +w16-era 6 16 5 1 4 3.2 1 9 a'=4; +w16-era 6 10 1 1 0 2.8 7 22 +w16-era 6 11 9 1 8 2.5 6 24 c,=5;a'=3; +w16-era 6 12 3 1 2 3.0 7 5 a'=2; +w16-era 6 19 5 1 4 3.1 9 3 a'=3;a=1; +w16-era 6 22 6 1 5 3.7 3 25 a'=4;a=1; +w16-era 6 21 4 1 3 3.0 15 4 a'=3; +w16-era 6 24 3 1 2 3.5 15 14 a'=2; +w16-era 6 15 6 1 5 2.9 11 13 a'=3;c,=1;a=1; +w16-era 6 20 8 1 7 3.1 10 13 a'=5;c,=1;a=1; +w16-era 6 27 7 1 6 3.1 2 18 a'=6; +w16-era 6 18 3 1 2 3.1 4 11 c,=2; +w16-era 6 17 3 1 2 2.7 4 7 a'=2; +w16-era 6 28 15 1 14 3.6 12 6 a'=10;c,=2;a=2; +w16-era 6 23 4 1 3 3.0 6 12 c,=1;a'=1;a=1; +w16-era 6 30 41 1 40 2.9 4 7 a'=29;c,=8;a=2;b=1; +w16-era 6 26 2 1 1 2.9 8 26 a'=1; +w16-era 7 1 4 1 3 3.8 3 20 a'=3; +w16-era 6 29 4 1 3 3.4 1 6 c,=2;a'=1; +w16-era 7 3 2 1 1 3.1 13 5 a'=1; +w16-era 7 6 2 1 1 3.0 6 17 a'=1; +w16-era 7 2 9 1 8 4.5 7 9 a'=7;a=1; +w16-era 6 25 7 1 6 3.3 10 17 c,=2;a=2;c'''=1;a'=1; +w16-era 7 0 2 1 1 3.5 3 21 a'=1; +w16-era 7 5 14 1 13 3.2 7 7 a'=12;a=1; +w16-era 6 31 17 1 16 3.1 14 24 a'=7;c,=5;a=3;b=1; +w16-era 7 9 3 1 2 2.8 13 23 a'=2; +w16-era 7 4 2 1 1 3.0 6 22 a'=1; +w16-era 7 11 2 1 1 3.2 14 5 a'=1; +w16-era 7 7 6 1 5 3.0 12 4 a'=4;c,=1; +w16-era 7 8 1 1 0 3.2 14 24 +w16-era 7 13 1 1 0 3.2 13 18 +w16-era 7 10 1 1 0 3.2 8 4 +w16-era 7 15 6 1 5 3.4 12 9 a'=3;c,=1;a=1; +w16-era 7 16 5 1 4 2.9 14 11 a'=4; +w16-era 7 14 5 1 4 3.0 4 11 a'=3;a=1; +w16-era 7 12 3 1 2 3.4 15 5 a'=2; +w16-era 7 22 6 1 5 3.5 7 13 a'=4;a=1; +w16-era 7 23 2 1 1 2.9 14 27 a=1; +w16-era 7 24 3 1 2 3.0 14 19 a'=2; +w16-era 7 17 3 1 2 3.5 11 19 a'=2; +w16-era 7 18 3 1 2 3.2 2 5 c,=2; +w16-era 7 19 5 1 4 3.3 9 11 a'=3;a=1; +w16-era 7 20 8 1 7 3.0 12 19 a'=5;c,=1;a=1; +w16-era 7 21 4 1 3 3.1 2 3 a'=3; +w16-era 7 28 14 1 13 3.4 5 6 a'=10;a=2;c,=1; +w16-era 7 30 8 1 7 3.1 1 7 a'=6;a=1; +w16-era 7 29 2 1 1 3.0 10 16 a'=1; +w16-era 7 31 6 1 5 3.2 10 5 a'=3;c,=1;b=1; +w16-era 7 25 4 1 3 3.1 1 20 a=2;a'=1; +w16-era 7 26 2 1 1 2.8 2 2 a'=1; +w16-era 7 27 7 1 6 2.9 0 9 a'=6; +# end 2026-10-08T13:04:55Z rows=257 diff --git a/docs/analysis/class-v6/logs/census/w16-none.tsv b/docs/analysis/class-v6/logs/census/w16-none.tsv new file mode 100644 index 000000000..774b4f738 --- /dev/null +++ b/docs/analysis/class-v6/logs/census/w16-none.tsv @@ -0,0 +1,259 @@ +# w16-none class w16m8g+sh256x27 eras [none] seeds 256 era-widths 16 weights base bittest off bin d601098699840534 start 2026-10-08T12:51:04Z host igneum-build-4 threads 16 +cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons +w16-none none 14 9 1 8 10.4 12 27 a'=7;a=1; +w16-none none 12 1 1 0 3.2 1 21 +w16-none none 13 2 1 1 3.2 3 14 a'=1; +w16-none none 9 7 1 6 3.0 3 14 a'=5;a=1; +w16-none none 7 1 1 0 9.0 11 3 +w16-none none 8 2 1 1 3.7 8 2 a'=1; +w16-none none 10 7 1 6 3.4 0 21 a'=6; +w16-none none 1 2 1 1 14.8 5 2 a'=1; +w16-none none 5 2 1 1 3.5 1 14 a'=1; +w16-none none 15 3 1 2 3.3 8 5 a'=2; +w16-none none 16 10 1 9 2.8 3 15 a'=9; +w16-none none 11 1 1 0 3.0 15 7 +w16-none none 20 3 1 2 3.0 5 6 a'=1;a=1; +w16-none none 6 2 1 1 16.2 2 2 a'=1; +w16-none none 19 3 1 2 3.9 10 20 a'=2; +w16-none none 4 2 1 1 3.8 13 10 a'=1; +w16-none none 21 5 1 4 2.7 14 10 a'=4; +w16-none none 0 3 1 2 3.3 12 7 a'=2; +w16-none none 2 5 1 4 13.9 2 2 a'=3;a=1; +w16-none none 18 3 1 2 3.0 10 2 a'=2; +w16-none none 22 1 1 0 3.2 12 14 +w16-none none 24 2 1 1 7.1 10 2 a'=1; +w16-none none 33 2 1 1 3.9 3 26 a=1; +w16-none none 17 2 1 1 3.0 10 22 a'=1; +w16-none none 27 3 1 2 3.3 8 13 b=1;a'=1; +w16-none none 29 3 1 2 15.0 9 2 a'=2; +w16-none none 30 3 1 2 9.9 0 6 a'=1;a=1; +w16-none none 3 7 1 6 2.9 0 23 a'=3;a=2;c'''=1; +w16-none none 28 2 1 1 32.3 4 2 a'=1; +w16-none none 32 4 1 3 3.0 2 4 a'=3; +w16-none none 25 13 1 12 7.2 6 2 a'=10;a=2; +w16-none none 23 4 1 3 4.1 0 16 a'=3; +w16-none none 34 2 1 1 3.1 0 25 a=1; +w16-none none 31 12 1 11 3.6 13 25 a'=7;a=2;c''=1;b=1; +w16-none none 37 4 1 3 29.2 11 2 a'=3; +w16-none none 35 12 1 11 38.7 6 2 a'=9;a=2; +w16-none none 40 1 1 0 3.0 11 2 +w16-none none 39 1 1 0 3.4 0 14 +w16-none none 42 1 1 0 14.7 7 2 +w16-none none 46 5 1 4 16.8 5 2 a'=4; +w16-none none 36 1 1 0 3.5 10 23 +w16-none none 26 7 1 6 17.4 2 2 a'=4;c''=1;a=1; +w16-none none 48 2 1 1 3.0 6 5 a'=1; +w16-none none 38 4 1 3 3.5 3 18 c'''=1;b=1;a'=1; +w16-none none 43 2 1 1 3.3 10 15 a'=1; +w16-none none 44 5 1 4 15.9 8 2 a'=4; +w16-none none 45 9 1 8 2.8 15 13 a'=7;a=1; +w16-none none 47 1 1 0 3.4 7 7 +w16-none none 49 2 1 1 3.4 0 15 a=1; +w16-none none 50 2 1 1 16.2 12 2 a'=1; +w16-none none 52 1 1 0 16.8 8 2 +w16-none none 54 5 1 4 18.7 3 2 a'=3;a=1; +w16-none none 41 5 1 4 16.4 9 2 c''=2;a'=2; +w16-none none 56 4 1 3 3.7 8 6 a'=3; +w16-none none 58 6 1 5 7.3 9 3 a'=5; +w16-none none 60 2 1 1 2.8 13 16 a'=1; +w16-none none 55 1 1 0 3.4 1 4 +w16-none none 51 2 1 1 3.0 5 14 a'=1; +w16-none none 53 2 1 1 15.5 1 2 c''=1; +w16-none none 59 4 1 3 2.9 10 27 a'=3; +w16-none none 57 1 1 0 3.0 3 15 +w16-none none 64 4 1 3 3.3 1 19 a'=2;a=1; +w16-none none 61 3 1 2 17.4 14 2 a'=2; +w16-none none 67 4 1 3 15.8 15 2 a'=2;a=1; +w16-none none 63 15 1 14 2.5 3 17 a'=13;c'''=1; +w16-none none 65 4 1 3 16.7 4 2 a'=2;b=1; +w16-none none 62 4 1 3 14.4 8 2 a'=2;c''=1; +w16-none none 75 1 1 0 3.1 11 8 +w16-none none 76 4 1 3 3.4 6 22 a'=2;a=1; +w16-none none 66 6 1 5 15.9 10 2 a'=4;a=1; +w16-none none 68 2 1 1 16.5 1 2 a'=1; +w16-none none 71 3 1 2 3.4 10 23 c=1;a'=1; +w16-none none 69 4 1 3 43.3 0 15 a'=2;a=1; +w16-none none 70 2 1 1 2.8 2 2 a'=1; +w16-none none 72 7 1 6 2.8 2 11 a'=5;c'''=1; +w16-none none 73 4 1 3 7.2 0 2 a'=3; +w16-none none 74 1 1 0 5.2 12 2 +w16-none none 77 14 1 13 3.1 7 24 a'=9;b=2;c''=1;a=1; +w16-none none 78 3 1 2 3.4 10 4 a'=2; +w16-none none 80 5 1 4 3.3 11 18 a'=4; +w16-none none 79 1 1 0 3.3 9 18 +w16-none none 82 3 1 2 3.1 10 10 a'=2; +w16-none none 81 3 1 2 3.1 5 19 a'=2; +w16-none none 87 1 1 0 32.4 9 10 +w16-none none 86 2 1 1 3.4 2 2 a'=1; +w16-none none 83 1 1 0 3.5 6 24 +w16-none none 89 4 1 3 8.6 0 2 a'=2;b=1; +w16-none none 90 2 1 1 3.6 6 8 a'=1; +w16-none none 93 1 1 0 3.1 7 27 +w16-none none 94 1 1 0 14.4 5 2 +w16-none none 85 1 1 0 3.0 1 11 +w16-none none 88 6 1 5 3.0 13 19 a'=4;b=1; +w16-none none 92 1 1 0 4.2 2 21 +w16-none none 84 1 1 0 56.3 2 10 +w16-none none 96 3 1 2 3.1 4 17 a'=2; +w16-none none 95 2 1 1 3.3 4 2 a'=1; +w16-none none 91 1 1 0 2.9 15 16 +w16-none none 97 1 1 0 2.8 1 10 +w16-none none 100 2 1 1 2.8 13 3 a'=1; +w16-none none 98 1 1 0 55.7 1 5 +w16-none none 101 1 1 0 4.1 5 17 +w16-none none 99 1 1 0 3.3 8 27 +w16-none none 106 4 1 3 4.9 2 15 a'=2;a=1; +w16-none none 102 1 1 0 2.8 11 12 +w16-none none 105 3 1 2 21.5 4 6 a'=2; +w16-none none 103 1 1 0 15.8 8 2 +w16-none none 108 2 1 1 17.2 10 2 a'=1; +w16-none none 107 3 1 2 10.7 0 27 a'=2; +w16-none none 109 1 1 0 3.1 3 3 +w16-none none 110 2 1 1 2.8 11 5 a'=1; +w16-none none 111 1 1 0 8.7 8 2 +w16-none none 104 1 1 0 2.9 1 26 +w16-none none 112 3 1 2 16.1 3 2 b=1;a'=1; +w16-none none 115 1 1 0 15.9 10 2 +w16-none none 114 10 1 9 3.6 0 5 a'=8;a=1; +w16-none none 113 1 1 0 17.3 12 2 +w16-none none 116 4 1 3 2.8 9 27 a'=3; +w16-none none 117 4 1 3 7.2 1 2 a'=3; +w16-none none 123 1 1 0 17.3 13 17 +w16-none none 125 1 1 0 2.5 10 2 +w16-none none 121 1 1 0 3.1 15 16 +w16-none none 124 1 1 0 3.0 1 19 +w16-none none 119 2 1 1 8.2 3 21 a'=1; +w16-none none 120 5 1 4 15.4 5 2 a'=3;c''=1; +w16-none none 118 3 1 2 15.2 10 2 c=1;a=1; +w16-none none 126 2 1 1 2.9 2 21 a'=1; +w16-none none 122 4 1 3 3.0 4 2 c'''=1;a'=1;a=1; +w16-none none 129 1 1 0 3.9 13 25 +w16-none none 131 2 1 1 16.4 5 2 a'=1; +w16-none none 133 1 1 0 28.1 0 10 +w16-none none 130 7 1 6 3.2 15 25 a'=5;b=1; +w16-none none 135 2 1 1 2.8 13 18 a'=1; +w16-none none 132 1 1 0 3.1 13 27 +w16-none none 134 2 1 1 7.9 15 2 a'=1; +w16-none none 128 2 1 1 15.8 2 2 a'=1; +w16-none none 138 9 1 8 3.3 1 17 a'=6;b=1;a=1; +w16-none none 137 2 1 1 3.0 3 4 a'=1; +w16-none none 127 7 1 6 3.4 7 18 a'=4;c'''=1;a=1; +w16-none none 141 4 1 3 13.2 1 2 a'=2;c=1; +w16-none none 139 5 1 4 2.4 0 21 a'=4; +w16-none none 142 2 1 1 11.6 3 2 a=1; +w16-none none 140 4 1 3 9.9 14 11 b=1;a'=1;a=1; +w16-none none 144 3 1 2 3.0 7 7 a'=2; +w16-none none 145 1 1 0 2.7 5 26 +w16-none none 147 2 1 1 3.0 2 5 a'=1; +w16-none none 149 2 1 1 8.8 11 2 a'=1; +w16-none none 148 2 1 1 3.2 14 2 a=1; +w16-none none 153 5 1 4 3.5 2 11 a'=4; +w16-none none 151 2 1 1 2.8 4 13 a'=1; +w16-none none 146 1 1 0 8.2 8 2 +w16-none none 136 5 1 4 2.9 8 25 a'=2;c'''=1;b=1; +w16-none none 152 2 1 1 13.2 13 25 a'=1; +w16-none none 155 7 1 6 3.6 4 6 a'=3;a=3; +w16-none none 143 6 1 5 2.8 2 16 a'=2;a=2;c=1; +w16-none none 150 1 1 0 28.9 3 9 +w16-none none 154 3 1 2 3.1 9 27 a'=2; +w16-none none 156 2 1 1 16.2 13 2 a=1; +w16-none none 157 2 1 1 3.1 8 25 a'=1; +w16-none none 158 8 1 7 3.0 9 20 a'=6;a=1; +w16-none none 159 1 1 0 3.4 12 9 +w16-none none 160 2 1 1 2.8 2 25 a'=1; +w16-none none 170 3 1 2 7.1 12 2 c=1;a'=1; +w16-none none 162 3 1 2 9.0 11 2 a'=2; +w16-none none 163 5 1 4 3.2 11 16 a'=4; +w16-none none 164 3 1 2 3.0 8 2 a'=1;a=1; +w16-none none 165 4 1 3 3.6 10 12 a'=3; +w16-none none 168 1 1 0 5.7 1 2 +w16-none none 169 1 1 0 8.0 5 3 +w16-none none 166 8 1 7 2.8 0 19 a'=7; +w16-none none 173 4 1 3 3.6 0 20 a'=3; +w16-none none 161 6 1 5 18.7 4 2 a'=5; +w16-none none 167 5 1 4 7.8 14 2 a'=3;a=1; +w16-none none 172 5 1 4 4.1 8 8 a'=3;a=1; +w16-none none 183 3 1 2 3.3 5 2 a'=2; +w16-none none 177 1 1 0 3.3 15 10 +w16-none none 181 3 1 2 7.5 6 2 a'=2; +w16-none none 171 1 1 0 3.2 10 14 +w16-none none 174 2 1 1 3.1 3 26 a=1; +w16-none none 185 2 1 1 10.5 5 2 a'=1; +w16-none none 184 6 1 5 2.9 13 18 a'=4;b=1; +w16-none none 186 1 1 0 15.3 5 2 +w16-none none 178 4 1 3 3.5 14 2 a'=2;c''=1; +w16-none none 187 6 1 5 3.2 7 20 a'=4;a=1; +w16-none none 176 6 1 5 6.0 14 2 a'=4;a=1; +w16-none none 175 1 1 0 2.8 0 8 +w16-none none 182 1 1 0 3.5 8 15 +w16-none none 193 1 1 0 5.0 15 2 +w16-none none 192 2 1 1 15.7 15 2 a'=1; +w16-none none 180 1 1 0 3.0 15 14 +w16-none none 179 1 1 0 3.0 15 4 +w16-none none 188 4 1 3 55.6 1 18 a'=2;c''=1; +w16-none none 198 7 1 6 15.0 6 2 a'=5;b=1; +w16-none none 190 4 1 3 3.0 2 11 c'''=1;b=1;a'=1; +w16-none none 200 10 1 9 3.9 3 19 a'=6;a=3; +w16-none none 191 2 1 1 6.8 15 2 a'=1; +w16-none none 189 3 1 2 2.9 14 19 a'=2; +w16-none none 196 3 1 2 15.2 10 2 a'=2; +w16-none none 202 3 1 2 3.9 0 22 a'=2; +w16-none none 197 2 1 1 16.5 15 2 a'=1; +w16-none none 203 4 1 3 4.4 10 16 a'=3; +w16-none none 205 1 1 0 3.1 14 21 +w16-none none 194 17 1 16 3.5 11 10 a'=10;b=3;c=2;a=1; +w16-none none 195 2 1 1 2.7 15 19 a'=1; +w16-none none 204 2 1 1 3.1 11 14 a=1; +w16-none none 199 1 1 0 3.5 14 14 +w16-none none 206 11 1 10 7.8 0 2 a'=9;a=1; +w16-none none 201 4 1 3 3.2 14 26 a'=3; +w16-none none 210 3 1 2 16.4 11 2 a'=2; +w16-none none 207 2 1 1 2.9 1 8 a'=1; +w16-none none 208 4 1 3 6.3 9 2 a'=2;a=1; +w16-none none 211 3 1 2 3.0 3 23 a'=1;a=1; +w16-none none 215 2 1 1 6.3 8 2 a'=1; +w16-none none 209 12 1 11 3.5 12 25 a'=9;c=1;a=1; +w16-none none 212 4 1 3 3.3 14 10 a'=3; +w16-none none 213 3 1 2 9.0 2 20 a'=2; +w16-none none 214 6 1 5 36.2 2 2 a'=5; +w16-none none 216 2 1 1 3.1 0 4 a'=1; +w16-none none 221 3 1 2 3.0 6 17 a'=2; +w16-none none 222 1 1 0 10.7 6 20 +w16-none none 223 1 1 0 3.1 5 20 +w16-none none 225 2 1 1 3.2 13 3 a'=1; +w16-none none 220 1 1 0 3.7 2 13 +w16-none none 227 5 1 4 19.7 3 2 a'=4; +w16-none none 219 7 1 6 2.6 11 23 a'=6; +w16-none none 217 1 1 0 2.9 0 12 +w16-none none 231 4 1 3 2.6 15 9 a'=3; +w16-none none 218 3 1 2 2.9 11 23 c=1;a'=1; +w16-none none 229 1 1 0 3.2 0 19 +w16-none none 224 3 1 2 3.1 5 8 a'=2; +w16-none none 228 1 1 0 9.4 11 2 +w16-none none 226 1 1 0 30.3 14 16 +w16-none none 232 3 1 2 2.8 0 11 a'=2; +w16-none none 237 4 1 3 3.7 13 7 a'=3; +w16-none none 240 1 1 0 14.9 6 2 +w16-none none 238 7 1 6 7.2 12 3 a'=5;a=1; +w16-none none 233 1 1 0 17.0 13 2 +w16-none none 243 1 1 0 6.3 0 2 +w16-none none 241 11 1 10 12.8 2 2 a'=10; +w16-none none 244 3 1 2 3.6 13 10 a'=2; +w16-none none 235 1 1 0 5.2 5 2 +w16-none none 242 6 1 5 2.7 2 4 a'=5; +w16-none none 234 1 1 0 7.6 1 2 +w16-none none 230 9 1 8 15.8 3 2 a'=7;c'''=1; +w16-none none 239 1 1 0 3.1 13 9 +w16-none none 245 6 1 5 3.6 1 10 a'=5; +w16-none none 236 1 1 0 3.6 7 15 +w16-none none 247 2 1 1 15.4 6 2 a'=1; +w16-none none 249 1 1 0 6.6 2 16 +w16-none none 250 2 1 1 2.8 5 5 a'=1; +w16-none none 252 4 1 3 2.9 7 4 a'=2;a=1; +w16-none none 246 4 1 3 16.3 11 2 a'=2;c''=1; +w16-none none 255 1 1 0 3.0 6 7 +w16-none none 248 3 1 2 38.0 1 2 a'=2; +w16-none none 251 3 1 2 3.6 9 10 b=1;a'=1; +w16-none none 253 3 1 2 6.2 0 2 a'=2; +w16-none none 254 5 1 4 7.4 2 2 a'=4; +# end 2026-10-08T12:54:55Z rows=257 diff --git a/docs/design/app-audit-2026-10-08.md b/docs/design/app-audit-2026-10-08.md new file mode 100644 index 000000000..951864631 --- /dev/null +++ b/docs/design/app-audit-2026-10-08.md @@ -0,0 +1,348 @@ +# Igneum Miner: the window audit, 8 October 2026 + +The order (14:5x BST, the founder): a full audit of the miner window. Things repeat (the tuning on more than one +page), the Earnings page is a mess; think Apple, minimal, informative but simple; handled on the next release. + +Read against the 0.3.25 line (release-0.3.25 b5be4edf) plus the UI lane's tiers-table-26 e34dc5d8, which is the +same window plus the table words. Every screen was captured from the mock on igneum-build-2 (`tools/ui-mock/capture.sh`, +1280 wide, dark and light); the captures are in `~/Desktop/igneum-previews-2026-10-08/audit/` (13 files, 01 to 13). +Nothing here is a Mac build. + +Sections: 1 the window as it stands, 2 the register of repeats, 3 the readouts that mislead or sprawl, 4 the target +layout with every row and its words, 5 the build plan for the UI lane on release-0.3.26, 6 what is held for the founder. + +Verdict words used below: **keep**, **merge into **, **remove**. + +## 1. The window as it stands + +Five pages behind a rail (Overview, Cards, Earnings, Prove, Settings), a four-step setup before them, a log drawer, a +top bar with a status pill, and a rail foot (machine name, "pays 0x…", uptime, Logs, Quit, version). + +### 1.1 Setup (fresh install; captures from the mock's `fresh` scenario were not re-taken, the screens are unchanged since 0.3.23) + +| Screen | What it shows | Verdict | +|---|---|---| +| Welcome | mark, "devnet v4 · nothing is bought or sold", three tiles (background, graphics card, pays an address), Get started | keep | +| Step 1 Your graphics card | every card a row with a switch; notes on NVIDIA 80% cap and the built-in GPU | keep; drop the sentence "The card row has a slider." (the slider is on Tune now, section 4.2) | +| Step 2 Your electricity | region, currency, price per kWh, Skip | keep | +| Step 3 Which network | two network cards | keep | +| Step 4 Where should rewards go | make me an address / use my own | keep | +| Key sheet | the private key once, the acknowledgement | keep; the sentence "Earnings can show it again" becomes "Settings can show it again" | + +### 1.2 Overview (capture 01, 02, 09, 10, 11) + +| Row | What it shows | Verdict | +|---|---|---| +| Top bar pill | "Mining · 203 MH/s" | keep the state word; the rate is the hero's (R8) | +| Hero numbers | 203 MH/s "2 of 2 cards mining"; 622 W "0.33 MH/W"; £4.18 "a day, electricity at 28p/kWh"; 6,785 blocks "this run · 8,055 lifetime" | merge into Mine as four numbers: MH/s, W, MH/W, IGN last 24 h (R8, R9, R18, A5) | +| Start/Stop mining | the big toggle, sub "mining on 2 of 2 cards" | keep the toggle; remove the sub (R8) | +| Clock card | shown only on skew | keep | +| First-block wait card, block card | the Poisson count-up, then the card once | keep | +| Ladder strip | seven rung chips, the current rung's sentence, "The ladder" | remove from Mine (R10) | +| The chain, live | the compact scene, Inspect, Pause, the legend; the full scene with the block inspector behind Inspect | keep | +| Node card | one line plus a disclosure with 13 key/value rows, the rules fingerprint, the next rule change | keep the one line on Mine; merge the disclosure into Settings > Node (R14, A14) | +| Activity | "42 blocks in 10 min · 253 in the last hour · N to the dev fee", "Open the log", eight events | keep the events (five); remove the stats line and the button (R12, R13, A15) | + +### 1.3 Cards (capture 03, 04) + +| Row | What it shows | Verdict | +|---|---|---| +| Ember Tune strip | three tier buttons with fleet numbers and savings; "Ember saves 188 W, £1.26 a day across 2 tuned cards"; Tune all; the sentence; "Electricity £0.28 per kWh, set in Settings · 2 of 2 cards measured"; the knee rule; the heat line; a Power control switch when NVIDIA is measure-only | merge into Tune as the strip: buttons, Tune all, one sentence (R1, R2, R4, R5, R7, R20) | +| Card row | mark, name, kind tag, series, "mining · 32 GB · 102 blocks"; 127 MH/s; 69,898 IGN a day; "450 → 372 W, 0.34 MH/W" with a sparkline; £2.50 a day; 59 °C; Retune; switch; chevron | split: the row on Mine carries name, state, MH/s, W, °C and the switch; everything else is Tune's (R6, R16, R18, R19, A6) | +| Tune line under the row | "Tuned 2 h ago 1950 MHz at 90% · the lock: 33 W less for 1.0% of rate, knee at 1100 MHz · next check 15 Oct" and "saves 78 W, 1.25% of rate" | merge into Tune as one line per card (A9, A10) | +| Details: Power cap | slider "90% · 405 W", two-sentence help, "Cap in force: 405 W, Ember's choice" | merge into Tune details, one sentence (A11) | +| Details: telemetry | "memory 68 °C · core clock 1950 MHz (cap 1950)" | merge into Tune details | +| Details: Tier | the card's three tier buttons, Retune, "Locked at 1950 MHz, 372 W; stock 450 W. A tap applies that row at once, no new search. Ember never locks below the knee by itself. Going lower is your choice." | merge into Tune, the buttons and one lock line (R1, R5) | +| Details: Tuned line | "Tuned: 126.8 MH/s at 372 W (0.341 MH/W) 1950 MHz at 90%, full tune, 2 h ago saves 78 W, 1.25% of rate" | remove (R6) | +| Details: Locked line | "Locked at 1950 MHz: 126.8 MH/s at 372 W (0.341 MH/W) unlocked at the same cap: 128.1 MH/s at 405 W", "the knee at 1100 MHz, where the rate fell 5.8% 33 W less for 1.0% of rate", then the 40-word lock rule | remove; the one lock line carries the lock and the knee (R5, R6, A10) | +| Details: the curve | the tune's curve with a 60-word caption | keep in Tune details with a two-sentence caption (A12) | +| Details: Miners on this card | the identities stepper with a 30-word help | keep in Tune details, one sentence (A13) | +| Details: facts | "runs on CUDA · 21760 cores · CUDA device 0" | keep in Tune details | +| Your cards eyebrow | "2 of 2 on" | keep on Mine | + +### 1.4 Earnings (capture 05, 06, 12) + +| Row | What it shows | Verdict | +|---|---|---| +| Headline | "29,517 IGN a day" "at your last hour's rate: 252 blocks at 4.88 IGN each · about 9,377 IGN expected at 17.0 MH/s" | remove; replaced by the measured windows (A1) | +| Run line | "6,784 blocks this run 33,109 IGN at today's reward · 1 shard, 1.15 IGN · 4 h 10 min" | remove (A2, R9) | +| Weight cell | "rank 3 of 4 keys 61 blocks in 2 hours · 2 of 2 hours · 2.22% of the network" | merge into one Standing row (A3, R10) | +| Electricity cell | "no draw / no card reports its draw" or "£4.18 a day at 28p/kWh for 622 W · 51 IGN per kWh" | keep as one row (A4) | +| Lifetime cell | "8,054 blocks 39,307 IGN at today's reward" | merge into the All time column (R9) | +| Dev fee switch | "Dev fee off. Every block pays your address." | merge into Settings, last section (R12) | +| The ladder | a 40-word intro and seven rungs, each a heading, a line and a sub | merge into the Standing disclosure, rungs only (R10, A17) | +| Your first hour | a six-step timeline behind a disclosure | remove (A18) | +| Rewards address | the address, Copy, Change address, Show my key, Open the wallet, "Your balance is in the wallet." | merge into Settings > Wallet; Earnings keeps one Payouts line (R11) | + +### 1.5 Prove (capture 07) + +| Row | What it shows | Verdict | +|---|---|---| +| Shard card | "Your card proved shard 3 of block 160,390." plus two lines | remove; the shard count is an Earnings column (R15) | +| Prove on this machine | the switch, a two-sentence help, the per-card tier list, the line, the note, Set up, Details (verifier, segments, program id, aggregator id) | merge into Settings > Proving (R15) | +| Prove instead of mining | the second switch for cards under 12 GB | merge into Settings > Proving | + +The page is one switch and one card. It does not earn a rail entry. + +### 1.6 Settings (capture 08, 13) + +| Row | What it shows | Verdict | +|---|---|---| +| Tuning card | the three tier buttons again, "2 of 2 cards measured · £0.28 per kWh, set in Settings", the Ember Tune switch, the Power control switch, Fine tuning, the sentence again | remove the card; Power control stays as its own section; the Ember Tune switch and Fine tuning go to Tune (R1, R2, R3, R4) | +| Electricity | region, currency, price per kWh, the typical-price note | keep | +| Heat mode | the switch with a 45-word label, hold, schedule, room now, two long helps | keep; trim the words (A20) | +| Network | the line, two network cards | merge into Settings > Node | +| This machine | start at login, make my page public, remote jobs (note, Check, History), name, appearance | keep | +| Interface | "Interface 1.0.0, built in", a 35-word help, the built-in switch | merge into Updates as one row (A19) | +| Igneum Miner 0.3.3 | the version line, Check for an update, Install updates by itself | keep as Updates | +| Logs | Copy the log, Show the log, the two paths | keep (R13) | +| Advanced (devnet) | vote on checkpoints, trust proofs, the live page, machine id | keep, before the dev fee | + +### 1.7 The rail, the foot, the drawer + +| Element | What it shows | Verdict | +|---|---|---| +| Rail | Overview, Cards, Earnings, Prove, Settings | four entries: Mine, Tune, Earnings, Settings | +| Rail foot | machine name, "pays 0xdd44…86E8", "up 4 h 10 min", Logs, Quit, "v0.3.3 · devnet v4" | remove the "pays" line (R11); the rest keeps | +| Page sub-titles | "your rate, what it costs, the chain as it grows" and so on | keep, rewritten in 4.5 | +| Log drawer | chips, search, jump to time, last error, last swap, wrap, copy, follow | keep | +| Update card, quit question, notices strip | | keep | + +## 2. The register of repeats + +Each repeat, where it sits today, and the one place it keeps. The test that proves it is in section 5.4 under the same id. + +| Id | Element | Where it appears today | Keeps | Verdict | +|---|---|---|---|---| +| R1 | the three tier buttons (Efficiency, Balanced, Maximum) | Cards strip `#tier-seg`; every card's details `[data-card-tier]`; Settings `#tier-seg-2` | Tune: the strip (fleet) and one row per card | remove from Settings | +| R2 | the Ember Tune sentence (what it is doing, did, will do) | Cards `#tune-schedule`; Settings `#s-tune-schedule` | Tune strip | remove from Settings | +| R3 | the Power control switch | Cards strip `#m-power-control` (when NVIDIA is measure-only); Settings `#s-power-control` | Settings > Power control | Tune shows one sentence with a link when it matters | +| R4 | the electricity price as a figure | Overview "electricity at 28p/kWh"; Cards "Electricity £0.28 per kWh, set in Settings"; Settings Tuning "£0.28 per kWh, set in Settings"; Settings Electricity | Settings > Electricity | remove the three figure lines | +| R5 | "Ember never locks below the knee by itself. Going lower is your choice." | Cards strip `#tier-rule`; each card's tier help; each card's lock help (`LOCK_RULE`); with two cards, five times on one page | Tune, once, at the foot | remove the other four | +| R6 | a card's measured point (126.8 MH/s, 372 W, 0.341 MH/W) | the row; the Balanced button; the "Tuned:" line; the "Locked at" line; the tune line's "saves 78 W"; six readings of one number | the row (live) and the tier button (measured) | remove the Tuned and Locked lines | +| R7 | the fleet saving | the strip's "Ember saves 188 W, £1.26 a day across 2 tuned cards"; the Balanced button's "saves 188 W, £1.26 a day" | the button | remove `#fleet-saving` | +| R8 | the hash total and the card count | the pill "Mining · 203 MH/s"; the hero "203 MH/s"; the hero sub "2 of 2 cards mining"; the toggle sub "mining on 2 of 2 cards" | the hero and its sub | the pill keeps the state word; remove the toggle sub | +| R9 | blocks this run and lifetime | Overview hero "6,785 blocks this run · 8,055 lifetime"; Earnings "6,784 blocks this run"; Earnings "Lifetime 8,054 blocks"; each row's "102 blocks" | Earnings, the windows table | remove from the hero; the row's count stays (it is per card) | +| R10 | rank, weight, the ladder | the Overview strip; the Earnings Weight cell; the Earnings ladder rung "Rank by weight"; the block card's rank line | Earnings, one Standing row with the rungs behind a disclosure | remove the strip and the cell | +| R11 | the rewards address | the rail foot "pays 0x…"; Earnings Rewards address card; the key sheet | Settings > Wallet; one Payouts line on Earnings | remove the foot line and the Earnings card | +| R12 | the dev fee | Earnings switch; Overview activity "N to the dev fee" | Settings, the last section, no control (earnings-26) | remove the switch and the activity mention | +| R13 | open the log | the rail foot Logs; Activity "Open the log"; Settings Logs "Show the log" | the rail foot and Settings Logs | remove the Activity button | +| R14 | the node facts | Overview node card, 13 rows plus fingerprint plus rule change | Settings > Node | Mine keeps one line | +| R15 | proving | the Prove page; the Earnings ladder rung "Your card proved a shard"; the Overview strip chip | Settings > Proving (the switches) and Earnings (the shard counts) | remove the page | +| R16 | Tune and Retune buttons | the row's Retune; the details' Retune; the strip's Tune all | Tune: one per card, Tune all on the strip | remove the row button | +| R17 | hashes per watt | the hero's "0.33 MH/W" as a sub-label; each row's "0.34 MH/W" with a sparkline; each tier button; the Tuned and Locked lines | the hero (as a number), the row, the tier button | the sparkline goes with the curve to Tune details | +| R18 | money a day | hero "£4.18 a day"; each row "£2.50 a day"; Earnings Electricity cell; each tier button's "£2.41 a day" | Earnings Electricity row; the tier button keeps the saving in watts only | remove from the hero and the rows | +| R19 | IGN a day | each row "69,898 IGN a day"; Earnings headline; Earnings "about 9,377 IGN expected" | Earnings, one quiet projection line | remove from the rows | +| R20 | the heat line | Cards strip `#heat-line`; Settings Heat mode `#s-heat-line` | Settings; Tune shows the line only while heat mode is on | | +| R21 | Interface and Updates as two cards | Settings | one Updates section | merge | + +## 3. Readouts that mislead or sprawl + +| Id | Readout | Why it misleads | Verdict | +|---|---|---|---| +| A1 | "29,517 IGN a day … about 9,377 IGN expected at 17.0 MH/s" | two figures three times apart on one line: one hour multiplied by 24 and called a day, beside a share projection; neither is measured | remove; the windows are measured sums (section 4.3); the projection is one quiet line that hides when a job holds a card, the network is paused, or no card mines | +| A2 | "6,784 blocks this run · 33,109 IGN at today's reward · 4 h 10 min" | "this run" is not a window a person thinks in; "at today's reward" recomputes the past | remove; last 24 h, 7 days, all time | +| A3 | "rank 3 of 4 keys · 61 blocks in 2 hours · 2 of 2 hours · 2.22% of the network" | four facts in three units in one cell | one row: "Rank 3 of 4 keys" with the window in the sub | +| A4 | "no draw / no card reports its draw" on Earnings while the Overview hides the watts cell | the same absence told two ways | one sentence, once: "No power reading on Apple silicon." | +| A5 | the hero's MH/W as a sub-label under W | the founder's first-class number rides as small print | its own number tile | +| A6 | "450 → 372 W" on a row | an arrow with no words; a before and an after that are not both now | the row shows the live watts; the tier button on Tune shows "78 W under stock" | +| A7 | tier button "saves 358 W, £2.41 a day" | a saving against stock that reads as a saving against now | "358 W under stock" | +| A8 | "MH/S", "A DAY", "BLOCKS" | the CSS uppercase on unit labels breaks the units | no text-transform on a unit | +| A9 | "Balanced on 2 cards, tuned 1 h ago · next check 15 Oct." and "2 of 2 cards measured" and "Tuned 2 h ago" | three stamps for one event, and the capture shows 1 h against 2 h | one sentence on the strip; one per card | +| A10 | "the lock: 33 W less for 1.0% of rate" and "saves 78 W, 1.25% of rate" | two savings with two baselines (the unlocked cap, stock) | one baseline, stock, once per card | +| A11 | slider "90% · 405 W", "Cap in force: 405 W", tier "372 W" | three watt figures that look like a contradiction (the cap and the draw) | one sentence: "Cap 405 W (90%). The card draws 372 W at the lock." | +| A12 | the curve caption, 60 words | nobody reads a caption that long | two sentences; the legend in the drawing | +| A13 | "Miners on this card", 30-word help | the help explains three cases | one sentence | +| A14 | "Node synced · 4 peers · 39,587 blocks" beside "This node has every block the network has made. Read 6 s ago." | the same fact twice on one line | "Node synced · 4 peers" | +| A15 | "42 blocks in 10 min · 253 in the last hour" over the activity feed | a third set of block counts on the glance page | remove; Earnings has the windows | +| A16 | Earnings sub-title "what you made, where it goes" | "where it goes" is the address, which is settings | "what this machine earned" | +| A17 | the ladder: seven rungs with headings, lines and subs, a 40-word intro | gamification on a money page | one Standing row; the rungs behind a disclosure, no intro | +| A18 | "Your first hour" timeline | the wait card and the block card already mark the first hour | remove | +| A19 | the Interface card | a 35-word explanation of over-the-air bundles beside the Updates card | one row under Updates: "Interface 1.0.0, built in" | +| A20 | Heat mode's 45-word switch label | the switch label is a paragraph | the label is five words; the paragraph is the help | +| A21 | the Prove page's "20 points of every block pay the provers, split by shard. A paid record is a chain fact: anyone can read it." | fine words in the wrong place | the Proving section's help | + +## 4. The target layout + +Four pages, one job each. Mine: what is happening now. Tune: how each card is driven. Earnings: what this machine +earned, measured. Settings: everything you set once. + +Every page under the copy law: no em dashes, no two-beat antithesis, no aphorisms, sentence case, one to three points +per block, `text-wrap: balance` on headings and `text-wrap: pretty` on body, the last two words of every sentence +block glued. Unit labels are never uppercased. Every number names its source on hover (`title`), as today. + +### 4.1 Mine + +Sub-title: "what this machine is doing now". + +1. The toggle: **Start mining** / **Stop mining**. No sub-line. Disabled with "waiting for the engine" as the label while the engine starts. +2. Four numbers in one row, big, each with a unit and one sub-line: + - **203** MH/s, sub "2 of 2 cards mining" (paused: "paused"; waiting: "waiting for the node"; heat rest: "resting, heat mode"). + - **622** W, sub "drawn now". Hidden when no card reports power. + - **0.33** MH/W, sub "hashes per watt". Hidden with the watts. + - **1,234** IGN, sub "last 24 hours" (measured: the blocks and shards of the last 24 hours at the reward each paid). "0 IGN" with sub "no block yet" before the first. +3. The clock card, only on skew (as today). +4. The first-block wait card, then the block card, once (as today). +5. **Your cards**: one row per card. Mark, name, the kind tag, the state word ("mining", "starting", "off", "fault: , retrying"), then **127** MH/s · **372** W · **59** °C, then the switch. No chevron, no buttons, no money, no IGN a day, no arrow. The eyebrow "2 of 2 on". A fault's reason reads on the row (the plug, tune, play rule). +6. **The chain, live**: the compact scene with Inspect and Pause, the legend; the full scene behind Inspect, unchanged. +7. The node line: a dot and "Node synced · 4 peers" (syncing: "Node syncing · 41,000 of 52,000 blocks · about 12 min left"; failed: "Node restarting · "). A click opens Settings > Node. No disclosure here. +8. **Activity**: the last five events in a person's words, each with its time. No stats line, no button. + +What leaves this page: the ladder strip, the money tile, the blocks tile, the node details, the stats line, the log button, the toggle sub-line, every per-card tuning word. + +### 4.2 Tune + +Sub-title: "how Ember drives each card". + +1. The strip, one card: the three tier buttons for the fleet, each: **Efficiency** "193 MH/s · 452 W" "358 W under stock"; **Balanced** "203 MH/s · 622 W" "188 W under stock"; **Maximum** "206 MH/s · 810 W" "stock". The one in force is marked. Then **Tune all**. Then one sentence, the only sentence: + - before the first tune: "Balanced is on. The first measurement runs 2 min into steady mining." + - from the table: "Balanced is on, from the team's table for this card class. Ember measures this card 2 min into steady mining." + - measuring: "Measuring RTX 5090: step 3 of 9, mining again in 4 min." + - measured: "Balanced on 2 cards. Measured 1 h ago, next check 15 Oct." + - off: "Ember Tune is off. The tiers still apply when you tap them." + - paused by the manifest: the manifest's note. + - class flip: "Class v5 arrived: re-measuring 2 cards, started 14:12. The class v4 points are out of date until then." + Then the switch **Measure cards by itself** with the help "Once, 2 min into steady mining, then every 7 days and after a driver or program change." (this is today's `s-sweep`). Under it, when heat mode is on, the heat line; when NVIDIA is measure-only: "Power control is off, so NVIDIA cards are measured and never set. Turn it on in Settings." +2. One card per graphics card: + - head: mark, name, the live "127 MH/s · 372 W · 0.34 MH/W", and **Tune** (or **Stop** while measuring; **Retune** once measured). + - the card's three tier buttons, the same shape as the strip, the one in force marked. A tap applies the row at once. + - one line: "Locked at 1,950 MHz, cap 405 W. Knee at 1,100 MHz." Variants: "Clock unlocked, cap 405 W." / "Measuring: step 3 of 9, 4 min left." / "No lever on Apple silicon: the system sets the clocks. Ember measures and reports." / "Re-measuring for class v5, started 14:12." / "From the team's table, measured on this card class." (or "estimated for"). + - **Details** (a disclosure, closed): the curve with the caption "Hash rate against power for every step of the last measurement. The ringed point is the one Ember kept; a hollow point was rejected; the dashed point is the knee." Then the cap row: the slider and "Cap 405 W (90%). The card draws 372 W at the lock. Lower is cooler and quieter." with **Back to Ember's choice** when pinned. Then **Miners on this card** with the stepper and "Each one votes and is paid on its own. 8 for a big card, 2 for a small one, 1 for a built-in GPU." Then the telemetry line "memory 68 °C · core 1,950 MHz · memory clock 13,801 MHz · fan 62%". Then **Fine tuning** (today's `s-climb`, only when the engine offers it) with "Searches around the best point instead of stepping down a ladder." Then the facts line "runs on CUDA · 21,760 cores · driver 617.42". + - a driver offer, when there is one, as today (Install, Restart now), on this card. +3. The foot, once: "Ember never locks below the knee by itself. Going lower is your choice." + +Nothing about tuning anywhere else: no tier buttons, no Ember sentence, no price figure, no saving line on Mine, Earnings or Settings. + +### 4.3 Earnings + +Sub-title: "what this machine earned". + +1. The headline: **1,234 IGN** with the eyebrow "last 24 hours" and the sub "251 blocks · 3 shards". +2. The windows, one row of two columns, each the same shape (amended 15:2x BST after item 5's capture: the headline is the 24-hour figure, so a 24-hour column beside it was a repeat of this page's own making): + - **7 days**: 8,920 IGN · 1,830 blocks · 19 shards + - **All time**: 39,307 IGN · 8,054 blocks · 61 shards + Every figure is the sum of what the chain paid at the time, never today's reward applied to old blocks. "0 IGN" with "no block yet" before the first. The engine carries the windows (section 5.1, item 2); until it does, a window shows its block count only and the IGN reads "reading", and the 24-hour count falls back to `ladder.blocks_24h`, then to the block list, never to zero. +3. **Electricity**: "£4.18 a day at 28p/kWh for 622 W". Without a price: "622 W. Set a price in Settings for the cost." Without a reading: "No power reading on Apple silicon." +4. **Payouts**: "Pays 0xdd44…86E8" with **Copy** and **Open the wallet**; the sub "Your balance is in the wallet. Change the address in Settings." +5. **Standing**: "Rank 3 of 4 keys · signing 8 of 80 points" with the sub "weight is your blocks over the last 2 hours, 2 of 2 hours mined". Behind **Details**: the rungs as today, without the intro, each one line and one sub. (Held for the founder: section 6, D2.) +6. The projection, one quiet line at the foot, dim: "About 9,400 IGN a day at 17.0 MH/s, 2.2% of the network." It is not shown when a remote job holds a card, when the network or mining is paused, when no card mines, or when the network rate is not read. It never sits beside a measured figure. + +What leaves this page: the dev fee, the address card, the key, the run line, the lifetime cell, the first-hour timeline, the IGN a day headline. + +### 4.4 Settings + +Sub-title: "set once, left alone". Sections in this order, each a card: + +1. **Wallet**: the address with **Copy**; **Change address** (the input, Change, the confirm); **Show my key** (the question, Show, Copy, Hide, the file path); **Open the wallet**. The help "Every block this machine finds pays this address." +2. **Node**: the network cards (Devnet 3 running now, Testnet 1 not yet open) and the switch question; one line "Node synced · 4 peers · 39,587 blocks"; **Details** (a disclosure): the 13 rows as today, the rules fingerprint with Copy, the next rule change. Help: "Every node on the network shows the same fingerprint of the rules. A peer with another one is refused." +3. **Updates**: "Igneum Miner 0.3.26" with the update note and **Check for an update** / **Install now**; the switch **Install updates by itself** "Downloads in the background and installs at a quiet moment, never mid-program."; the row "Interface 1.0.0, built in" with the switch **Use the built-in interface** and the one-line help "Small changes to this window arrive over the air, signed by Igneum." +4. **Power control**: the switch, "Lets the app set NVIDIA power and clock limits. Windows asks for administrator rights once at install. Off, NVIDIA cards are measured and never set." and the engine's note when there is one. +5. **Electricity**: region, currency, price per kWh, the typical-price note. Unchanged. +6. **Heat mode**: the switch **Hold a room temperature**, help "The cards heat for a share of every 10 minutes and rest for the rest. Your card is an electric heater that also earns." Then hold, schedule, room now, each with one sentence of help. +7. **Proving**: the switch **Prove on this machine**, help "Every block is turned into a short proof, in pieces called shards. Your cards prove shards and earn IGN for each one. 20 points of every block pay the provers." Then **Prove instead of mining** when a card is under 12 GB, the per-card tier list, the line, **Set up** when needed, **Details** (verifier, segments, the two program ids). +8. **This machine**: start at login, make my page public, allow remote jobs (note, Check for jobs, History), name, appearance. Unchanged. +9. **Logs**: Copy the log, Show the log, the two paths. Unchanged. +10. **Advanced** (devnet): vote on checkpoints, trust proofs, the live page, the machine id. Unchanged. +11. **The dev fee**, last, no control (the founder's order through the coordinator, 8 October 2026; earnings-26 321041dc): "1 block in 100 pays the people who make this app." and one line on what it funds, the site's wording from site/miner.html. The command-line arm (`--dev-fee 0`) stays; an off state reads "The dev fee is off on this machine." + +### 4.5 The rail, the pill, the titles + +- Rail: **Mine**, **Tune**, **Earnings**, **Settings**; the foot keeps the machine name, "up 4 h 10 min", Logs, Quit, the version. The "pays 0x…" line goes. +- The pill: the state word only: "Mining", "Paused", "Syncing", "Waiting", "Job running", "Node down". The rate lives on Mine. +- Page ids: `mine`, `tune`, `earnings`, `settings`. `View.PAGES` in that order; `page('nonsense')` falls to `mine`. + +## 5. The build plan for release-0.3.26 + +For the UI lane (a414b6bdc81d348d8), on top of tiers-table-26 e34dc5d8 and its two held items (the earnings-tab +fix, the dev fee to the bottom of Settings; both are absorbed below). Ordered by what the person at the window sees +first. Hours are lane hours; the whole plan is about 27 hours of lane time plus 4 of engine time, so two lanes land it +in one working day. Every item ships with its test (5.4) and its captures. + +### 5.1 Items + +| # | Item | What changes | Hours | Tests | +|---|---|---|---|---| +| 1 | The four pages | `View.PAGES` to mine, tune, earnings, settings; the rail; the page titles and subs (4.5); Prove's markup moves under Settings; `renderProve` becomes `renderProvingSection`; the pill reads a state word (`View.pill`) | 2 | T-R15, T-R8 | +| 2 | Earned windows in the engine | `ladder.rs` keeps every block and shard with its time and the wei it paid; `state.ladder.earned = {h24, d7, all}` each `{wei, blocks, shards}`; summed at state time from the kept records; a 0.3.25 record with no wei rows reads the chain facts' reward at the block's time for the back-fill, once | 4 (engine lane) | `ladder.rs` unit: three windows over a fixed record; a block at the 24 h edge counts once | +| 3 | Mine | the hero's four tiles (MH/W as a tile, IGN last 24 h from item 2); the toggle without its sub; the ladder strip removed; the node card to one line that opens Settings > Node; Activity to five events, no stats line, no button; the card rows to name, state, MH/s, W, °C, switch | 4 | T-R8, T-R9, T-R10, T-R13, T-R14, T-R18, T-R19, T-A5, T-A14 | +| 4 | Tune | the page from the Cards strip and the card details: the strip (buttons, Tune all, one sentence, the measure switch, the conditional heat and power lines); per card the head, the buttons, the one lock line, Details (curve with the short caption, cap sentence, miners stepper, telemetry, fine tuning, facts); the foot rule once; the Tuned and Locked lines removed; `fleetSaving`, `priceFigure` and `tier-price` removed | 6 | T-R1, T-R2, T-R3, T-R5, T-R6, T-R7, T-R16, T-R17, T-R20, T-A7, T-A9, T-A10, T-A11 | +| 5 | Earnings | the headline and the windows (item 2), the Electricity row, the Payouts line, the Standing row with the rungs behind Details, the projection line and its hide rule; the dev fee, the address card, the run line, the lifetime cell and the timeline removed | 4 | T-A1, T-A2, T-A3, T-R9, T-R11, T-R12 | +| 6 | Settings | the sections in 4.4's order: Wallet (from Earnings), Node (the network cards plus the Overview disclosure), Updates (with the Interface row), Power control alone, Electricity, Heat mode (short label), Proving (from Prove), This machine, Logs, Advanced, Dev fee last; the Tuning card removed | 4 | T-R1, T-R2, T-R3, T-R4, T-R11, T-R12, T-R14, T-R15, T-R21, T-A19, T-A20 | +| 7 | Copy and units | no `text-transform` on unit labels; the setup's slider sentence; the key sheet's "Settings can show it again"; the widow guard on every new block; a pass over every new sentence against the copy law | 1.5 | T-A8, the copy-law grep (no em dash in `index.html` or `app.js` strings) | +| 8 | Mock, captures, screens | the mock's scenarios keep working (`?page=mine|tune|earnings|settings`); a `audit-26` shot list in `tools/ui-mock/`; captures into `docs/design/app-screens/0.3.26/` (four pages, dark and light, the first-minute and the measured states) on build-2 | 1.5 | the capture run itself | + +Item 1 lands first so items 3 to 6 do not collide on the page markup; items 3 to 6 are one page each and can run in +parallel on one branch (`app-ia-26` off tiers-table-26) with a commit per page. Item 2 is the engine lane's and gates +only the IGN tile and the windows; until it lands the tile reads "reading" and the windows show blocks only. + +### 5.2 What the UI lane's two held items become + +- The earnings-tab fix: absorbed by item 5; the old headline, run line and cells are not fixed, they are replaced. +- The dev fee to the bottom of Settings: item 6, section 11, the last card; the words in 4.4. + +### 5.3 Order of landing + +1. `app-ia-26`: items 1, 3, 4, 5, 6, 7 (one lane, commits per item, the gate green on each). +2. `earned-windows-26`: item 2 (the engine lane), merged under `app-ia-26` before item 5's windows read live. +3. Item 8 on the merged tree; the captures go with the plan commit. +4. The lane reports its sha to main by 18:30 BST; main merges into release-0.3.26 after the gate. + +### 5.4 The tests: nothing twice + +All in `app/igneum-app/ui/view.test.mjs` (the View block runs under node with no DOM) plus a new +`app/igneum-app/ui/once.test.mjs` that reads `index.html` as text and counts. Each repeated element in section 2 has +one assertion. `once(html, needle)` counts occurrences of a string in the static markup; `inPage(html, pageId, needle)` +counts inside one `
`. + +| Test | Asserts | +|---|---| +| T-R1 | `once(html, 'aria-label="Tuning tier"') === 1` and it sits in `#page-tune`; `inPage(html, 'settings', 'tier-seg') === 0`; `View.tierSet` is the only producer of per-card tiers and `tierButtonsHtml` is called from the Tune renderer only (a grep over `app.js`: the string `tier-seg-2` is absent) | +| T-R2 | `once(html, 'id="tune-schedule"') === 1`; `once(html, 's-tune-schedule') === 0` | +| T-R3 | `once(html, 'id="s-power-control"') === 1`; `once(html, 'm-power-control') === 0`; `View.powerNote(state)` returns the one sentence only when an NVIDIA card is present and power control is off | +| T-R4 | the string `per kWh` appears in `index.html` only inside the Electricity section (count 2: the setup step and Settings); `View.priceFigure` is not exported | +| T-R5 | `once(html, 'Ember never locks below the knee') === 1`; `View.TIER_RULE` is read by the Tune foot only (`app.js` grep: one reference outside the View block) | +| T-R6 | for a measured card, `View.tuneLines(card, state)` returns exactly one line and it contains neither "Tuned:" nor "Locked at … MH/s" (the lock line carries MHz and W only); `View.lockWords` is folded into it | +| T-R7 | `View.fleetSaving` is not exported; `once(html, 'fleet-saving') === 0` | +| T-R8 | `View.pill(state).text` for a mining state equals "Mining" (no "MH/s"); `once(html, 'btn-toggle-sub') === 0` | +| T-R9 | `inPage(html, 'mine', 't-blocks') === 0`; `once(html, 'e-run') === 0`; `View.earningsLines(state).all.blocks` is the only lifetime count | +| T-R10 | `once(html, 'ladder-strip') === 0`; `once(html, 'id="rungs"') === 1` and it sits in `#page-earnings` behind `#standing-details` | +| T-R11 | `once(html, 'id="r-address"') === 1` and it sits in `#page-settings`; `View.railFoot(state)` has no "pays" line; `inPage(html, 'earnings', 's-address-input') === 0` | +| T-R12 | `once(html, 'id="s-fee-card"') === 1`, it is the last `.card` of `#page-settings` and holds no ``; `once(html, 's-devfee') === 0`; `#page-earnings` has no "fee" word; `View.activityStats` is not exported and `d-stats` is absent | +| T-R13 | `once(html, 'btn-open-log') === 0`; `once(html, 'id="btn-logs"') === 1`; `once(html, 'id="s-log-open"') === 1` | +| T-R14 | `once(html, 'id="node-details"') === 1` and it sits in `#page-settings`; `inPage(html, 'mine', 'n-digest') === 0` | +| T-R15 | `View.PAGES.map(p => p.id)` deep-equals `['mine', 'tune', 'earnings', 'settings']`; `once(html, 'id="page-prove"') === 0`; `once(html, 'id="s-prove"') === 1` and it sits in `#page-settings` | +| T-R16 | the Mine row renderer output for a tunable card contains no `data-tune` and no `data-stop`; the Tune card contains exactly one of them | +| T-R17 | `View.cells(card)` has `eff` once; the Mine row output contains `MH/W` zero times (the hero tile carries it); the Tune head contains it once | +| T-R18 | `inPage(html, 'mine', 't-money') === 0`; the Mine row output contains no currency symbol; `View.earningsLines(state).cost` is the one money line | +| T-R19 | `View.cardIgnDay` is not exported; `View.earningsLines(state).projection` is the one IGN a day figure and is `null` when `jobs.active`, `mining.paused`, `mining.state !== 'mining'` or `chain.hps` is unread | +| T-R20 | `once(html, 'id="heat-line"') === 1` in `#page-tune`; `View.heatLine(heat).text` is empty when heat mode is off | +| T-R21 | `once(html, 's-interface-card') === 0`; `once(html, 'id="s-ui-line"') === 1` inside the Updates card | +| T-A1 | `View.earningsLines(state)` returns `h24`, `d7`, `all`, each `{ign, blocks, shards}` summed from `state.ladder.earned`; no field named `day` | +| T-A2 | no "this run" in any `earningsLines` text | +| T-A3 | `View.standing(state).text` equals "Rank 3 of 4 keys · signing 8 of 80 points" for the ladder fixture | +| T-A5 | the Mine hero markup has four `.tot` tiles with the unit labels `MH/s`, `W`, `MH/W`, `IGN` in that order | +| T-A7 | a tier button's sub reads "358 W under stock" for the fixture; no "saves" and no currency | +| T-A8 | `app.css` has no `text-transform: uppercase` rule that applies to `.tot .k`, `.num .unit` or `.tier-b .l` | +| T-A9 | `View.tierSentence(cards, state, now)` for two measured cards returns one sentence containing exactly one time word | +| T-A10 | the Tune card's lock line for the fixture contains "under stock" at most once and no "for … of rate" | +| T-A11 | `View.capSentence(card)` equals "Cap 405 W (90%). The card draws 372 W at the lock." for the fixture | +| T-A14 | `View.nodeLine(node).text` for a synced node equals "Node synced · 4 peers" | +| T-A19 | `View.interfaceWords(ui).line` equals "Interface 1.0.0, built in" and the help is one sentence | +| T-A20 | the Heat mode switch label text in `index.html` is under 30 characters | + +The copy-law grep joins `tools/ci/checks.txt` for `app/igneum-app/ui`: no em dash (U+2014) in `index.html` or in a +string literal of `app.js`; it is already the rule for served text and the window is served text. + +## 6. Held for the founder + +Defaults stand unless a word comes by the time given. + +| Id | Question | Default | By | +|---|---|---|---| +| D1 | Prove loses its rail entry: the switches go to Settings > Proving, the shard counts to Earnings | fold it | 17:00 BST | +| D2 | The ladder: one Standing row on Earnings with the rungs behind Details, or gone from the window (it stays on igneum.network) | one row, rungs behind Details | 17:00 BST | +| D3 | Electricity as one row on Earnings (it is measured: watts now at the typed price) | keep the row | 17:00 BST | +| D4 | The card rows (name, state, rate, watts, switch) live on Mine; every tuning control on Tune | Mine | 17:00 BST | +| D5 | The chain scene stays on Mine as the live graph; the block inspector stays behind Inspect | stays | 17:00 BST | + +Captures: `~/Desktop/igneum-previews-2026-10-08/audit/01-overview-live-dark.png` to `13-settings-light.png`. diff --git a/docs/fud-ledger.md b/docs/fud-ledger.md index de4d087b4..32d32c148 100644 --- a/docs/fud-ledger.md +++ b/docs/fud-ledger.md @@ -2499,6 +2499,8 @@ F8's 64-seed gate on 017e7037 (the attack-pass lane, box 2, last seed 16:00:20 U The tail read (8 October 2026, 09:40 to 09:46 UK, the hash lane, the M5 Max under the measure lock, one seed at a time; attack-f8 census at 2^24 nonces, window-model control, by-site attribution; tree b38b4af6 with igneum-pow at the frozen 017e7037): the four gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x), the hot-set verdict on the windowed control is clear on all four, and every tail is attributed to one load site reading a narrow window, the site's 256-item bucket concentration carrying the excess with no saturated and no lossy source. p4: site 1 (instr 8, source r2, window 2^22 items, offset 1, last base writer mad at 4) puts 1.448 percent of its reads into the top 0.1 percent of items against 0.107 flat, index entropy 13.74 of 14 bits, largest 256-item bucket 4.5x its window expectation; hottest item 0x4000e7 at 355 reads, predicted source none. p8: site 14 (instr 51, r7, window 2^22, offset 2, writer xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, and site 6 (instr 33, r3, window 2^23, offset 1, writer mad at 30) 0.834 percent, entropy 14.71 of 15, bucket 3.5x; hottest 0x837de4 at 420 reads, source none. p10: site 8 (instr 28, r0, window 2^22, offset 1, writer mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x; hottest 0x4004da at 362 reads, source none. p34: site 1 (instr 13, r3, window 2^23, offset 1, writer sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x; hottest 0x800010 at 541 reads, predicted source a one-bit value from the sub at 5, saturated source 0.0001 percent. Every other site in all four seeds reads at its flat share. Reading: the residue is a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short of uniform on a 2^22 window; 0.04 on p34) at one narrow-window site whose last writer is a mad, an xor or a sub, and the ratio tracks the bucket excess (5.6x gives 1.50x; 3.1x to 4.5x give 1.22x to 1.38x). Sub-version 3's distinct-index ratio (c'') passes these sites at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would refuse all four is a per-site bound on the largest 256-item bucket, about 2x its window expectation, at the 2^20 units (c'') already draws; it is a generator change, so it is not for the frozen 017e7037, and its cost on clean seeds is unmeasured (a morning item). Chip consequence of the residue: none beyond the window model's (a quarter bit at one site of sixteen is under 1.002x on the item set a chip would hold). The row's tail is attributed; nothing in the stream, the id or the fingerprints changes. +The F8-256 attributions (8 October 2026, 14:0x UK; the attack-pass lane's 256-seed gate on the class v5 freeze 1c420786, section (e) of its record, and the hash lane's by-site reads): the two seeds the gate flagged with a predicted one-one-bit source were read by site. p212 (1.1917x over the window model, the attack-pass lane on the gate's own line, build-4): the excess sits at site 9 (instr 35, r6, window 2^22, offset 0) at 16.4x its flat share, index entropy 13.981 of 14 bits, the largest 256-item bucket 1.75x its window expectation, the hottest items read from that site in all eight iterations near the window's base; the predicted site (instr 7, r5, a load at 2) reads the ordinary narrow-window share. p225 (1.2452x, the hash lane on the 1c420786 crate, build-3): site 4 (instr 23, r7, window 2^23, offset 1, last base writer mad at 21) at 12.6x with full entropy and the bucket at expectation, the predicted site (instr 37, r5, a load at 36) second at 3.7x. Reading: p212 is this row's tail class (a quarter-bit bucket concentration at one narrow-window site) and p225 a value-level concentration on specific items from a mad-written index; in both the predicted-source line names a site that is not the excess, so that prediction is a hint and the by-site histogram is the attribution. Consequence for the next class's acceptance: a per-site bucket bound near 2x refuses this morning's four (3.1x to 5.6x) and neither of these (1.75x; none); the value-level test (adv-cache-2's) is what sees p225, and a bucket bound near 1.5x would take p212 at a clean-seed cost estimated at 3 to 6 percent. Nothing in the stream, the id or the fingerprints changes. + Two in-house pass findings against sub-version 3 (adv-accept-3, 7 October 2026, evening), neither a chain consequence. (1) Documentation: program.json's `program_id_derivation` and spec 01 section 1.4.6 stated the plain form while generator 4 appends `'sub/' || sub_version_le16`, so a client written from the text derives another id (the devnet v4 pack: 8aa9f185d63f269e from the text against a785001687d8688a; Devnet 3's epoch 0: 30956569d8f3d8d7 against fce15bf61030be57). Fixed at 15008aca and 0f45c8be: one byte recipe (`generator::IdRecipe`) builds the id and the text, the emitter prints that text, the spec states the suffix, the class v5 form (generator 5, no suffix) and the rung form, `tests/derivation.rs` re-derives every pinned pack's id from its own text with the pack's fields only (the plain text as the known-failed case), 38 packs' program.json corrected one line each with every other file and every id and fingerprint byte-identical on re-export; the twelve readwidth mix packs of 5 October keep their text (a class name the parser no longer accepts). (2) Correctness, unreachable: the last-resort program after 256 failed attempts (`last_resort_v4`, the xor rewrite) fails the acceptance rule in 223 of 2,500 seeds (209 by part (a)) and is handed to the chain unchecked; at r = 0.67 to 0.68 the path is reached with probability about 4.6e-44 per epoch, so no chain reaches it and sub-version 3 is not reopened for it. Sub-version 3's last resort is therefore UNREACHABLE AND UNVERIFIED against the rule; class v5's generator (the v5 lane) carries the verified construction with the known-failed test on one of the 223 seeds, and its entry states it. From the same pass: the three lowest-ratio steering seeds of 4,975 at a 256-unit sample read 1.0002x worst live, so the 256-unit ratio is noise as a selector and the selector works only at the 2^20-unit read, which is what rule (c'') uses. Owed (recorded, not run, by the founder's word): G2 (the CPU verifier on 1,024 hashes per card) on the amended stream; G3 (the Metal fuzz, edge, stats and determinism runs) on the amended stream; the hash-rate ladder re-measure on the M5 Max and the RTX 5090 (the amendment changes the base program's source draws, not the op mix or the load count, so the latency-bound rows of `docs/analysis/latency-shadow-2026-10-06.md` are expected to hold within their spread; unmeasured); AMD (the RX 9070 XT, PC 1); the 2019-class verifier core (O-1.14); F8's phase E (the 64-seed dynamic census) on the amended stream, which is the attack-pass lane's and the test of the per-op table. The row reads FIXED-AND-PASSED only after phase E passes against the amended class. diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 65eea4931..c74012d2e 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,7 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. THE FAST-TIME GATE ON THE RE-CUT: SUMMARY PASS (cross-0324-c9e385eb) at 22:49:32Z (23:49 BST) on the shipped 0.3.24 re-cut c9e385eb (igneumd 7a841b20..., igneum-miner 1e209b9e..., igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 22:36:25Z to 22:49:32Z, every check green: rung 1 by signal at epoch 6 (22:42:54Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (22:44:54Z, 4 of 4, 9,985 bps), 11 of 11 ids equal to the CPU verifier's, the stale node 86 of 86 refused with 0 accepted after the first refresh, the restart step across the boundary on a kept datadir resynced in 28.1 s with the catch-up done after 10 s and 0 of its own blocks during it, four sinks equal at 660, honest nodes 0 PoW rejections; record on v5-fasttime 76276be6, docs/design/class-v5-harness/fasttime/cross-0324-c9e385eb.json. The 0.3.24 move's gates left (the shipper's correction of this record): not F9 and F1's full 10^5 PASS (landing about 00:40 BST, too close to the 00:52 ceiling) but an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, max attempt 25), any non-zero holding the move, the full 10^5 the record line after; the minute named by the fleet on the last FETCHED plus ten once the build-server lane's c9e385eb pairs land. THE 61-ROW ERA READING (the v5 lane, box 2, 23:4x to 23:5x BST, docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log): 0 of 61 refused by the 0.995 floor at the table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), every class v5 draw on the class v4 attempt; era-drawn-28 (id 5e9eb01efbbf653e, attempt 6, R 15, the worst of adv-cache-2's census at 1.7451x) reads its biased site 15 at 0.9969, over the floor by 0.0019; era-drawn-25 (1.3571x, R 21) site 11 at 0.9994; the eight over 1.2x span 0.9965 to 0.9997 while the eight few-item hot sets sat 0.003 to 0.013 under the line. Main's sentence opens AP-F8-6 and section 14 verbatim with the two-instrument reading under it. THE CLASS V5 ATTEMPTS CENSUS for 1.4.7 (1,000 f8 seeds through the chain draw, v5-attempts-census-1000.log, the crypto lane's form): 3,219 candidates, 2,219 rejected, per-candidate rejection 0.6893 (sub-version 3: 0.68), accepted attempt mean 2.219, 0 exhaustions, P(256 consecutive) 4.4e-42; first failing part (a') 83.4 percent of rejections, (a) 10.7, (b) 3.0, (c'') 1.2, (c''') 1.0 (0.7 percent of candidates, one in 140: the floor's own share, 0.045 on the attempt mean), (c) 0.7 together, (c') none; the 5.14 percent of class v3 that 1.4.6 quotes is the audit lane's to replace. Both on class-v5 at 3b1dffd6 with main's sentence (891dd008), the mirror's master merged (e0471019: AP-F8-1's update and AP-F8-4 taken, the program-id recipe form with the state tag, no conflict), the design page's pre-public scrub (the founder's name six times, gone), M35's status word and the regenerated public ledger; the push waits on the full gate and the pinned-packs test on the merged tree (the proof that e5a4ac5978462156 and the other ids still derive under master's recipe form). THE 00:00 BST READINGS (the crypto lane; the verified roll-up of all nine lanes in section 13 of in-house-pass.md on crypto-engage, every branch tip read from the mirror and igneum-pow identical to 017e7037 on each). adv-accept, tip a7c49399 (about 5.5 box-hours, 0 pod-hours): 182,646 distinct accepted programs drawn (18 percent of the 10^6); eight pass every part of the frozen rule and flag the live hot-set test at 2^24 (X at 0.1 percent +0.102 to +0.221, 1.54x to 2.24x), all in the lowest 34 stand-in-ratio seeds against 0 in 20 random; each about 1 MB of items holding 0.26 to 0.41 percent of reads, 1.002x at the largest; the mechanism a near-saturated source at one site mapped by the era stride to one fixed item (plus two lesser shapes); the exemplar reads the same under the class v5 dataset. Against the class v5 floor: 8 of 8 refused; 3 mild residuals missed (adv-cache-2's rotation class, a load_index question not a floor question); 6 clean programs refused among the 9 deepest (the 2.4 percent). Q2 BOUND (54 programs plus 17 reads, 0 disagreements). Row 90: 0.6787 per candidate, (a') 83.3 percent, 0 exhaustions, P 8e-44. Partial named: 18 percent of seeds, 54 live rows, row 90 at half; a longer pass adds rows of the same shapes, not a different answer, unless a seed reads a hot set over 1 percent of reads, which 182,646 draws did not produce. THE PER-LOAD CLASS CLOSED (the research lane, for main; clock readings UTC): the per-load shadow fix held for distinctness and then met the value-level requirement from adv-cache-2, and the construction did not survive it; the per-load 16 x 27 class is dead as a chain class. 22:44 the attempt verdicts on four seeds (igneum-genesis 0 of 32 accepted); 22:47 the 64-seed census under the full rule (duplicate lanes at a load row plus the one-count of every index bit per site over the 64 units, 6-sigma band): 22 of 1,621 candidates accepted (1.4 percent), 42 of 64 seeds exhaust the chain's 32 attempts (an epoch without a program); the first failing test per candidate: biased index bit 775, duplicate lanes 643, the base rule 110, (b) 43, (a) 28; candidate 0 of the class carries index bit 0 set in 40 of 1,024 addresses (z 29.5); 22:52 the suite green (64 + 5 + 7 + 4 + 19 + 2 + 7); the acceptance rule with BiasedIndexBit for this class and the tests pushed as the record, the file's 20.2a closed. The structural reason: 27 passes of a 16-instruction map right before a load is an iterated small function and collapses or biases the load's address register before any base instruction re-randomises it; the class v4 shape has 64 base instructions and 16 loads between its block and every load. Both exports were accepted only because the rule did not model the placement; their PC 1 rows stay as an energy reading of the placement, labelled unsound. Rank 4 and the USD 200 M capex row rest on a construction not shown to exist (chip model 5.11's clause marked so in this landing); the sound form is one pass of a 432-instruction sub-block per load (a program segment, not an iterated map), a new class to draw, accept and measure, not tonight's. Replicated by a second instrument: the class v4 shape on this pre-amendment generator carries the adv-cache-2 product bit at address bit R exactly in 14 of 17 drawn eras (one-count 250 or 780 of 1,024, z 15 to 19), 0 duplicate pairs across the eras. What stands from the two prototypes: the tile block (bit-exact on the Metal reference, the AVX2 verifier at 0.047 us per tile, the Apple emulation cost 35 to 78 percent) awaiting its 5090 rows; the per-load placement closed. THE SPEC REWRITE ON MASTER (the site audit lane, 8b834634 at 23:56 BST; gate GREEN on 64e2a91b, 71 checks; the igneum-pow suite green on the box for that commit with derivation.rs and spec_readback.rs): spec 01 sections 1.4.3 and 1.4.6.1 to 1.4.6.6 rewritten to 017e7037 with the 20-row constants table (ACCEPT_TAG, the window-cap literal, MAX_SATURATED as the first refused count with the 163 message noted) and the 6-row pinned-ids table with Devnet 3's full genesis hex; the shadow block in 1.7; the ninth era draw in 1.13.1; tools/ci/spec-constants-check.mjs in the gate (known-failed first, every Constant | Value | Where table, pending rows skipped while absent); igneum-pow/tests/spec_readback.rs (ids derived through the crate, each class v4 row drawn to its attempt); ledger AP-F8-5 after AP-F8-4; the ledger-page fix (both heading forms, the pass as its own section, known-failed self-test in the gate; AP-F8-1, AP-F8-4 and AP-F8-5 render on /ledger); the fud-ledger's two prize clauses and "paid independent cryptanalysis" removed at the source so the regenerated page carries neither (commit 90424d5a, merge 64e2a91b). A HARDWARE FACT IN DISPUTE, for main: tonight's 5080 efficiency rows came from PC 1 jobs (run-ca3-pc1-v4-eff-5080-20261007-b and -c), the audit lane's record reads the RTX 5080 and the Arc B580 on PC 1, the hash lane's 22:09Z device list on PC 1 shows the 5090, the 9070 XT and the 4070 only, and main places the 5080 and the B580 on PC 2; identity-check.sh's "PC 2" substitution text names cards and is left card-free until the PC 2 job's own --list settles which cards sit where. THE IDENTITY CHECK'S PC 2 TEXT (the CI steward, 00:05 UK on 8 October): tools/ci/identity-check.sh rewrites "PC 2" card-free as "the second Windows rig" (commit 40f2be54, merge 0d2cf334, gate GREEN 71 checks, identity grep 0 hits over 306 export files and 52 served pages); line 69's PC 1 list untouched; the reason recorded in a bash comment above the perl call. THE 32,400 FLOOR LOST (the node lane, 00:0x UK on 8 October): dn3-g1's chain read DAA 25,126 at 23:52:03Z and 25,169 at 23:52:38Z, so the publish DAA passed 25,200 at about 23:53:09Z with no 0.3.24 move made (build-1's three Devnet 3 nodes last restarted about 21:31Z on the 0.3.23 move; the old seed holds 38 peers on ba75bf6f; no move minute was named). The next boundary is 36,000 (epoch 10), about 02:52Z on 8 October (03:52 BST) at 1.0 DAA/s, holding for a publish up to DAA 28,800 (about 00:53Z, 01:53 BST). Two routes put to the shipper and main: the same re-cut script on release-0.3.24-node (program_class_v5_activation_daa 36,000, nothing else, the same gate set, about 20 minutes to the pin line), or the fleet names its minute first and the floor is cut from it in one go (publish DAA plus 7,200 to the next 3,600) instead of a fourth chase; the pin c9e385eb stands meanwhile. THE FLOOR RE-CUT FROM A NAMED MINUTE (the shipper, 00:1x BST on 8 October, under the slip rule main set with the object commit): the floor re-cuts once more to 39,600 (epoch 11, about 04:52 BST) from a move minute the shipper named: 02:00 BST on 8 October, or the fleet's last FETCHED plus ten if later but before 02:53 BST (DAA 32,400, the ceiling); the node lane's pin line in about 20 minutes with the new Devnet 3 digest; the F9/F1 interim read at 01:55 BST; the publish minute equals the move minute (the apps' entries at or after it); the fast-time SUMMARY PASS reruns on the new pin as part of its gate set; the cause of the lost floor named: the c9e385eb pairs and the two PC jobs unreported for forty minutes, so the fleet had nothing to point its move file at. "slot closed" on PC 1 still waits on the host job's exit. THE 0.3.24 NODE PIN AT 39,600 (the node lane): dfbd1e10 on release-0.3.24-node (both mirrors, 23:54:13Z) = c9e385eb with program_class_v5_activation_daa 39,600 (epoch 11), nothing else; pairing igneum-pow 1c420786; every gate green at 00:01:52Z (build 23:56Z rc 0 at gate priority, igneumd 4870ccf2..., igneum-miner aa8c2978..., /srv/artefacts/0324-dfbd1e10/node-lane; pow 19, consensus 134, p2p-flows 38, exec 47, core 175, miner 28); the Devnet 3 canary set (23:56:33Z to 23:58:13Z): digest b1ba78229b069dc395fa666638a686a66615eb760d251798adfa6a654a415f82 on igneum-devnet-3 from ba75bf6f, object version 6 stamped (block version 1538), the override file refused, shutdown 2,015 ms, two empty nodes handshaking on it, the shared-devnet dialler rejected, a 2720d8d2 node refused on the digest both ways; the testnet canary b2e856ed unchanged (byte 7, a live old-object testnet node refused). The cut's read: dn3-g1 at DAA 25,169 at 23:52:38Z (1.0 DAA/s), the publish DAA at the named minute 01:00Z about 29,211, plus 7,200 = 36,411, the boundary 39,600 about 03:53:09Z on 8 October (04:53 BST), holding for a publish up to DAA 32,400 (about 01:53:09Z, 02:53 BST). The one gate running: the fast-time pair on dfbd1e10 (about 13 minutes from its start). c9e385eb is void as a pin; the F9/F1 interim read armed at 00:55Z. THE TWO PC QUEUES AT 01:03 BST (the hash lane): PC 1's "slot closed" has not come (the shipper's 0.3.24 host job, the build-server lane's, took the slot at 22:13Z for an expected two to three minutes; nothing reported in 110 minutes); nothing of the hash lane's has run on PC 1 since 22:09:25Z; the v5 kit fetch and the 9070 XT v5 bench are prepared and unpublished (tools/ca3-v4-amend/pc1-publish-20261007.sh, steps v5-kit and v5-amd), so no 9070 XT class v5 fingerprint exists yet; the lock protocol holds unless main says the lock-free pair goes ahead of the silent host job. PC 2's "clear" has not come either (the 0.3.23 take 3 smoke and the scheduler proof unreported by either lane); the Intel job is prepared and unpublished. THE HARDWARE FACT, read from tonight's PC 1 lines: nvidia-smi on PC 1 lists GPU 0 RTX 5090 (bus 01:00.0) and GPU 1 RTX 5080 (bus 0D:00.0); its OpenCL list carries the RX 9070 XT (gfx1201) and the integrated gfx1036 and no Intel platform; so the 5080 is on PC 1 (the audit lane's record right, the 22:09Z device-list summary short by one card) and the Arc B580 is not, which agrees with main's word that it is PC 2's eGPU; the kits row, the bench notes and identity-check's card-free PC 2 text stand on that. The locked PC 1 jobs stay parked (the 5080 full grid, the third 5090 pass, SM-sparse, the microbench and packs knee states, the two Ember tunes, the hot-table ldcs rows); the lock-free CA4 rows queue after the v5 bench on the same "slot closed". THE 00:00 BST READINGS, THE OTHER THREE (read by the crypto lane from each branch's report on the mirror at 01:03 BST; the roll-up section 13 of in-house-pass.md at crypto-engage c84ba51b with adv-accept's reading at 1b4e07ff; all nine branch tips read back from the mirror and igneum-pow IDENTICAL to 017e7037 on every one: adv-mixer d2ba3134, adv-mixer-2 2a632579, adv-mixer-3 4ebe2455, adv-cache 555c3e42, adv-cache-2 9384ee09, adv-cache-3 9452c0bf, adv-accept a7c49399, adv-accept-2 92168536, adv-accept-3 0c150e3c). adv-accept-3 (exhaustion or steering of the draw), tip 0c150e3c, every sweep ended 23:05 BST, about 3.3 box-hours, 0 pod-hours: Q1 exhaustion BOUND (per attempt accept 0.323, reject 0.677 ((a') 0.568, (a) 0.079, (b) 0.022, dynamic parts about 0.009), geometric histogram, P(exhaust) 0.677^256 = 4.6e-44, 0 of 16,337 seeds at the cap); Q1b the last resort FINDING (correctness; the mirror fired at cap 256 byte-identically; of 3,000 last-resort programs the real rule rejects 271, 9.0 percent: 251 by (a), 14 by (b), 6 by (c) distinct sum; handed out unchecked; unreachable; closed in class v5 by 8ca66afa, AP-F8-3); Q2 steering BOUND (45 of 48 planted rows fired, the real rule rejects every effective plant by (a'); 975 seeds at the first part, min ratio 0.998, 18 of 18 chain re-draws equal); Q2b the price of a seed property at 1 in 10^6 tries is a shadow block with 38 multiplies of 256 against a mean 74, about 2 to 3 percent of the f = 1 chip's energy per hash, the load critical path worth nothing at the memory activate ceiling; Q2c the 256-unit ratio is noise as a selector; Q3 program id FINDING (documentation: the "sub/" || 3_le16 suffix omitted from program.json and spec 1.4.6; a text-derived implementation computes 30956569d8f3d8d7 for Devnet 3 against the pack's fce15bf61030be57; 0 collisions over 10^7 pairs; fixed as AP-F8-4 at da2fc101); Q4 determinism DONE (the (c'') f64 compare never disagrees with the integer rule on any of the 2^20 + 1 values, margins 0.32 to 0.44 counts; a second interpretation agrees on 5,748 of 5,748 verdicts of 1,792 seeds); Q5 the era lever BOUND (400 eras, no stride under NAF weight 7, all 31 rotations, 354 distinct interleaves; epoch 0's accepted attempt is 3 under every era, so the era moves the address map, not the program). Partial named: the steering sweep at 975 of a planned 10^5 seeds (about 8 box-hours more at 32 cores). adv-cache-2 (the hot-set attack), tip 9384ee09 at 23:52 BST, about 2.2 box-hours by wall times threads over 96 (the boxes at load 400 to 600 for the first two hours), 0 pod-hours; two shards still queued at 00:00 (lines-2e30-s2c, warps-devnet-2e25-v2), named partial: Q1 the line index PASS (pooled 16 days; segments max +4.84 sigma against a control's +4.24, lines +5.61 against +5.35, chi2/dof 0.99937, top 0.1 and 1 percent of lines 1.0003x and 1.0002x of control; the 2^35 + 3 x 2^33 census all PASS; 0 mirror mismatches); Q2a the real programs PASS on the hot-set test (devnet at 2^26 1.0002x; Devnet 3 at 2^26 items 1.0071x, lines 1.0000x) with the FINDING at Devnet 3 site 0; Q2b all 64 programs done, every one clear on the hot-set test (items 0.9993x to 1.0075x of the windowed control) but the site class as recorded above (13 of 27 drawn-era over 1.04x, 8 over 1.2x, worst 1.7451x; the v5 floor refuses 0 of 61; AP-F8-6); Q3(1) steering by t PASS (worst cell 3.95 sigma in 2 x 2,112 cells); Q3(2) the weak-day scan PASS over 16,384 days (2^30 derivations in 707 s; worst per-day max bucket +8.13 sigma against the control's +7.78; the plant fired at +1,090); Q3(3) the window layer: the exact distribution matches the 4,096-program census to four digits (top quarter mean 0.3382, top half 0.5811), with a FINDING against the chip model's table: the f = 0.25 and f = 0.5 partial-store rows overstate the recompute share by up to 1.8x at f = 0.5, the full-store (f = 1) verdict unchanged (a correction owed in chip-model-v3's partial-store rows; no served number rests on f under 1); Q4 the prices: the only measured excess over f is the window layer's and the line reference multiplicity (a hottest-lines half store hits 57.8 percent instead of 50 at a higher miss cost than the stride). adv-mixer-3 (the statistical distinguisher and round margin), tip 4ebe2455 at 00:41 BST, still RUNNING at 01:03 (Q3 and Q4 at k = 8 on day 20729, queue 07 in the pool, the SAT ladder at k = 3 timed out; the total box-hours the lane's to give): Q1 the exhaustive round-0 line-index census over all 2^32 t PASS to k = 8 on days 20729 and 20733 and at k = 2, 3, 4, 8 on 20730 (z within 1.5); Q2 single-bit avalanche FINDING at k = 1 (354 and 266 holes, 130,000 cells beyond 6 sigma, the known one-application diffusion), PASS from k = 2 at 2^24 (0 holes, worst z under 5.3 through k = 8); Q2b the t-bit avalanche the same shape; Q3 differential multiplicity over 576 low-weight differences FINDING at k = 1 (695 and 537 deterministic output bits), PASS k = 2 through 7, k = 8 running; Q4 and Q4b linear correlations PASS from k = 1 (worst c 0.00046 to 0.00062, z under 5.1); Q5 rotational-XOR PASS from k = 1; Q6 SAT: k = 1 SATISFIABLE in 137 s (t = 0x49880000 verified through the real code), k = 2 and 3 TIMEOUT at the one-hour cap. The round margin as it stands: no statistic survives 2 of the 8 applications between reads; a chip gets nothing from the k = 1 findings because every read sits behind 8. The lanes' own lines go into section 13.1 as they arrive. THE LANES' OWN 00:00 LINES (adv-accept-3 and adv-mixer-3, 01:0x BST, in section 13.1 of in-house-pass.md): adv-accept-3's P(exhaust) refined to 1.0e-43 per epoch seed from 62,240 full-rule candidates plus 3.0e6 static candidates; Q2 steering BOUND over 19,975 full-rule and 1e6 static seeds, no property buying over about 1.03x at 1 in 1e6 tries; a second documentary FINDING: an implementation written from the spec text (not the code) at 017e7037's spec differs on 264 of 400 epoch programs, the same text-against-code gap as the id suffix (the audit lane's rewrite 8b834634 with spec_readback.rs is the fix; the proof that it closes this is a re-run of the text-derived implementation against the rewritten text, asked); a plant note: the floor-0.97 known-failed variant did not fire because the (c'') ratios are bimodal (accepted 0.989 to 0.999, rejected 0.814 to 0.966), replaced by a single-pass (a) variant that did; 3.3 box-hours, nothing running. adv-mixer-3: about 3.0 wall-hours of sweep plus 4 single-core CaDiCaL hours; the round margin stated as 6 of 8 applications between reads and 70 of 72 per item on every measured statistic, the k = 1 effects one mechanism (the lowest-set-bit trail through one application, dead once both addends carry a difference), nothing saving one application against 9,360 ops per item; still running at 4 cores on build-1 (2^27 and 2^28 avalanche rows, finish about 03:00 BST) and the day-20733 SAT ladder on build-2 (about 03:45 BST); not attempted: multi-bit linear masks and a MILP trail bound. adv-cache-2's own line still owed. ADV-CACHE-2'S OWN LINE (01:05 BST, tip 3f50d6c4; section 13 of in-house-pass.md now carries every lane's reading in its own words plus the verified roll-up): the drawn-era prevalence read on the SAME 32 base programs is 2 of 32 under the devnet era against 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), the mechanism carried by rotl(x times M, R) into the item index unless R is 29 or 30 (2 of 31 rotations), with a sub-class of warp-uniform sources once in 16,000 warps; the window layer's price restated: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the chip model's partial-store rows overstate the recompute share by up to 2.3x on these programs, the f = 1 verdict unchanged (the correction to chip-model-v3's partial-store rows is the coordinator's next commit); partial named (the drawn-era windows census of 4,096 and one line shard in the pool); the longer-pass line: the biased-site rate per era in closed form (the R in {29, 30} rate 2 in 31) and a 2^28 read of the worst site. Nothing of the pass stands between the pool and a higher-class job except two pre-emptable shards on box 2. THE SPEC-TEXT RE-DERIVATION ORDERED (01:06 BST): adv-accept-3 re-derives its 400 epoch programs from the rewritten spec text alone at master 8b834634 (1.4.3 to 1.4.6 grown from 79 to 198 lines with the constants and pinned-ids tables), lease pool 16 --min 8 class adv, row Q4c in its report; the expected reading 0 of 400, any non-zero naming the diverging sentence to the audit lane; the proof that AP-F8-5 closed the text-against-code gap. THE CHIP MODEL'S PARTIAL-STORE ROWS carry a second correction (section 5, 8 October 2026) from adv-cache-2's window-layer reading: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the uniform-store rows overstate the recompute share by up to 2.3x; the f = 1 row, the SRAM column and the full-store verdict unchanged, no served number on f under 1. THE CLASS V5 PACKS TEST ON THE MERGED TREE (the v5 lane, 01:0x UK): the job ran on box 2 the minute two adv-accept holders ended (65 cores; no lease fault, plain starvation before); 19 passed, 1 FAILED: v5_pack_is_the_v4_program_over_the_state_leaves (tests/packs.rs:977), the byte-for-byte compare of every pinned pack file with the crate's export. The ids are EQUAL (v4-genesis exports a217c7f698880830 as pinned; the state tag rides in master's recipe form unchanged); what differs is the program_id_derivation TEXT in program.json, which master's export (the hash lane's AP-F8-4 read-back form) now writes as "... || attempt_le32 || 'sub/' || sub_version_le16" for generator 4 while the pinned packs carry the pre-suffix wording. Disposition: the three pinned packs re-exported from the merged crate (text only; the ids, kernel texts, leaves and the fingerprint 82b19cbde8557ea5 must come out byte-identical, proved by the same test); the CLI rebuilding on build-1 from 51aa5bc4, the export from the box's IGSD1 streams, the packs test and the full suite on box 2 at 16 cores, then the push; readiness about 01:35 UK. The 0.3.24 kit zip (packs-ca3-v5-20261007T221001Z.zip) carries the old derivation text in its program.json files: a text field only, no id, kernel or fingerprint change, so the kit stands for 0.3.24 and the shipper is told; the re-exported packs go in the next kit. THE ONE 0.3.24 KIT, NAMED for the shipper (01:1x BST): packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 the pin pairs with; the fleet keeps placing it. The 23:11 zip packs-ca3-v5-20261007T221001Z.zip (sha256 4aaf9b9e..., /srv/artefacts/packs/ on build-1, from class-v5 7f58af97) carries the same packs, ids, kernels, leaves, fingerprint and derivation text and differs only in the merged kit host code and scripts beside the packs; it is the bench lanes' kit for the fingerprint jobs. The coordinator's earlier line naming 4aaf9b9e as the 0.3.24 kit was wrong and is corrected here. THE SPEC-TEXT READ-BACK RUNNING (adv-accept-3's Q4c, 01:11 BST on build-2, lease pool 16 --min 8 class adv): the same 400 epoch seeds re-derived from the spec text at master 8b834634 alone (1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7, 1.13.1; a fresh text interpretation), compared field for field with the chain draw; the count about 01:21. One sentence already named divergent before the count: 1.4.6 part (c) cites dataset_elem(idx, S[0], S[1]) "of verify.rs" without stating its six operations, so part (c) cannot be computed from the text alone and the derivation takes that one function from the crate; the audit lane is to state the closed form's six operations in the text or the constants table, else 1.4.6 stays code-dependent on that line. A NINTH LIVE HOT SET (adv-accept, 01:12 BST): seed 228763 (id 2c4be0f6dc44c423, stand-in 0.9820) at 2^24 (X at 0.1 percent +0.118, 1.82x the window model), its single hottest item 0xe2cc96 at 1,218,380 reads, 0.057 percent of ALL reads, the largest single item of the pass (40x 100767's), from a NON-saturated source r0 at site 9 (the sel register), saturated-source share 0.000: the third shape at scale, a value-level concentration neither (c') nor a saturation test can see by construction; its 2^20 ratio against the 0.995 floor lands in minutes and decides whether the floor's instrument reaches it (if missed, the exemplar for the next class's non-saturated case). 638990 reads 1.51x beyond the gate with one item at 0.027 percent (r0, no saturation), no hot set; 623492 clean. Tally: 9 hot sets in 37 tail seeds against 0 in 20 random, 269,250 programs drawn; the price unchanged at 1.002x (0.27 percent of reads on 1 MB; one item 64 bytes). The public sentence's "eight of eight" moves to "nine of nine" or gains the first miss when the ratio reads. THE FLOOR REACHES THE NON-SATURATED SHAPE (adv-accept gap-tail3, 01:13 BST): seed 228763 reads minimum site 9 at 0.9809 at the 2^20 sample, the lowest of the pass, REFUSED; 638990 site 2 at 0.9872, REFUSED; 623492 (clean live) site 0 at 0.9922, REFUSED, a seventh false refusal. Final tally over everything the lane read at 2^20: 9 of 9 live hot sets refused (0.9809 to 0.9919), both single-item programs refused, 7 clean-live programs refused and 1 passed among the 12 deepest 256-unit seeds, 3 mild residuals missed at about 1.0004x. The reading: the distinct-index ratio reads any few-item concentration whatever its source, saturated or not, and misses only the diffuse era-stride excess; the class v5 floor closes the hot-set class entire at the 2.4 percent clean-rejection cost; the next class's value-level test is for the diffuse class alone. The public sentence reads "nine of nine hot sets refused" from here (the v5 lane's follow-up cfce57ea rides its push; AP-F8-1 on master updates with the next record commit). THE FAST-TIME GATE ON dfbd1e10: SUMMARY PASS (cross-0324-dfbd1e10) at 00:12:57Z on 8 October (01:13 BST), the shipped re-cut's binaries (igneumd 4870ccf2..., igneum-miner aa8c2978..., igneum-pow 1c420786), build-1 under lease pool class v5, 23:58:56Z to 00:12:57Z, every check green: rung 1 by signal at epoch 6 (00:05:37Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (00:07:46Z, 4 of 4, 9,985 bps), 12 of 12 ids equal to the CPU verifier's, the stale node 95 of 95 refused, the restart step across the boundary on a kept datadir resynced in 36.2 s with the catch-up done after 11 s (4 IsInIBD refusals of its own miner during it, 0 of its blocks accepted), four sinks equal at 661, 0 PoW rejections on the honest nodes; record on v5-fasttime 0a09eb78, docs/design/class-v5-harness/fasttime/cross-0324-dfbd1e10.json. Every gate on the pin is green; the move waits on the pairs on the dl host, the last FETCHED plus ten, and the F9/F1 interim read. THE RE-EXPORT READ (the v5 lane, box 1 with the merged crate ac285733): the three pinned packs' only difference was program.json's program_id_derivation text (generator 4 now "|| 'sub/' || sub_version_le16", generator 5 the class recipe "igneum-program-rw/ ..."); ids, kernel texts, leaves.bin, vectors and the fingerprint 82b19cbde8557ea5 byte-identical; the pinned packs carry the merged text; the full gate and the full igneum-pow suite with the packs test and spec_readback running on that tree, the push and commit string about 01:45 UK; main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2 at class-v5 b5d6368d (nothing with eight of eight reached the mirror). AP-F8-1's two eight-of-eight lines on master move to nine in this record commit. THE MOVE'S SOURCE (the shipper's ruling at 01:05 BST, corrected to this record at 01:1x): the 02:00 BST move does not wait on the build-server lane's pairs; that lane is dark (nothing published since 23:05 BST, nothing answered since 00:17), so the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair at /srv/artefacts/0324-dfbd1e10/node-lane on build-1 (igneumd 4870ccf2, igneum-miner aa8c2978, the pair every gate ran on, native glibc 2.39 on every fleet box), the way dn3-g1 and g2 moved at 22:30; the fleet's puller fetches from build-1, not the dl host. The move waits on the fleet publishing the dfbd1e10 move file and naming the minute (asked 01:05) and the F9/F1 interim at 01:55. The hive and the Windows pairs are the dark lane's loss for tonight unless main gives the shipper the word to build them (asked 01:06); the Mac entry publishes at the minute regardless; if the fleet has not published the move file by 01:40 BST, main and the coordinator hear it with the clock. THE PC 1 LOCK VOID, THE V5 AMD BENCH PUBLISHED (the hash lane, 01:1x BST): the shipper's 0.3.24 host job was never published to the jobs file, so the slot was void (the shipper's "slot void" at 01:05 BST); the v5 kit fetch landed on both PCs at 00:12:06Z (919,273 bytes, sha256 ok); run-ca3-pc1-v5-amd-bench-20261007 published 00:14:19Z (the 9070 XT by name, about 3 minutes, lock-free), its start line printing app_version, so the 0.3.20 or 0.3.23 reading of PC 1's app comes with the fingerprint; PC 2's Arc job needs only the shipper's "PC 2 clear". PC 1's app had NOT taken the 0.3.23 kit as of the last reads (every job log through 21:46Z app_version 0.3.20; the install folder's exe igneum-app 0.3.20, mtime 12:24:42Z, sha256 0443ae17...). The update-return lane (a22d765a2e0355a9f) last spoke at 23:0x BST: the helper workaround for 0.3.20 scripts (truncate cmd.txt, restart the task, wait for helper.alive, then write; or four leading " dev " padding lines), the locked jobs held as they are, power-helper-24 b9a72b9b merged into release-0.3.24 (daa7427b: a silent change becomes a logged line, the helper writes its exit reason), install-close-23 4ad6c199 for 0.3.23's take 3, the re-probe job when PC 1's app has taken the 0.3.23 kit; nothing since. THE SPEC-TEXT READ-BACK PASS (adv-accept-3 Q4c, 01:11 to 01:15 BST on build-2 at 16 cores; report section 6.5 on build/adv-accept-3, log 983-textderive-8b834634.tsv, pushed): the spec text at master 8b834634, implemented fresh without the crate's generator or rule, reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences (every instruction, the chosen attempt, the id, the rejection sequence); the 264-of-400 divergence against the text at 017e7037 is closed, so AP-F8-5 reads fixed on a measurement. The one remaining gap: 1.4.6.4 names dataset_elem "of verify.rs" without its six operations, so parts (c), (c') and (c'') still take that function from the crate; the audit lane's one-sentence closed form (asked 01:1x) closes it, and the read-back re-runs on the new text. THE AMD CLASS V5 FINGERPRINT (PC 1's RX 9070 XT, gfx1201, beside the miners, lock-free): 82b19cbde8557ea5 at 01:16:14 BST, equal to the kit e6c088bb's on Metal, Apple OpenCL and CUDA, self-test PASS, the v4-genesis control 892b6d55a7ddcfcb PASS; the 0.3.24 kit stands on four platforms; Intel waits on PC 2 (held until main's word, since the 0.3.23 take 3 never ran there); PC 1's queue continues with the CA4 unlocked rows. The kits row reads: Metal, Apple OpenCL, CUDA, AMD equal; Intel not measured tonight. THE UPDATE-RETURN LANE'S THREE READINGS (01:17 BST, from the live manifest and the intake): (1) 0.3.23 take 3 (install-close-23 4ad6c199) never reported; the live manifest igneum-app-latest.json reads 0.3.23 published 20:37:44Z with platforms = {mac} only, NO Windows entry, so neither PC has anything to take through its update path; PC 2's app run is still take 1's relaunch from 21:08:43Z (997 uploads, last 00:16Z); (2) PC 1 will not take 0.3.23 unattended tonight for want of a Windows entry; its run win-ae432dc7-20261007-160110 (0.3.20) never restarted (2,376 uploads, last 00:16Z), mining 18.96 MH/s on the 9070 XT; when a Windows entry is published the 0.3.20 engine's OTA takes it with no hand; the 21:41:32Z helper.ps1 write was not the prompt path (0.3.20 writes that file unconditionally), so no screen is owed in the morning for it; (3) the re-probe job (relay/playbooks/pc1-helper-reprobe.ps1 on power-helper-24 69f3c733) waits only on PC 1's exe becoming 0.3.21 or later; the 0.3.20 workaround is cleared to run tonight as a lock-free job so the locked grids go ahead: per grid job, before the first command, empty sweep\cmd.txt, Stop-ScheduledTask and Start-ScheduledTask 'Igneum Power Helper', wait until helper.alive is within 4 s, then write the lines with climbing sequences (in 0.3.20 the skip is the line count at the helper's start, fixed for its life); the helper idle-exits 20 minutes after its last command and the next start must begin over an empty file again; never pad after a command. The coordinator's order to the hash lane on it: the locked grids proceed in the earlier order (the 5080 full grid, the third 5090 pass to the driver's floor, SM-sparse, the two Ember tunes, the hot-table ldcs rows), each with its restore step, under the no-prompt rule; a Start-ScheduledTask that reads the 0x800710E0 refusal again stops the job and reports, nothing escalates. THE LOCKED GRIDS UNDER THE WORKAROUND (the hash lane, 01:2x BST; commit 24f9858e on the mirror): the three lock scripts carry the cleared sequence (empty sweep\cmd.txt, Stop- then Start-ScheduledTask 'Igneum Power Helper', helper.alive within 4 s with a 60 s cap, then dev + command with climbing sequences; repeated before any write when helper.alive is older than 10 s; a refused start 0x800710E0 or no heartbeat stops the lock path with the text on RESULT lines, nothing escalates; no padding; each grid job ends with rgc through the same sequence and the applications clock read back). PC 1's app_version on the v5 bench's start line: 0.3.20 (no Windows 0.3.23 published, nothing to take). The CA4 SM-sparse job run-ca4-pc1-ca4sparse-5090-20261007 runs since 00:20:40Z on the earlier padded script (unlocked rows first, then its 1,300 knee attempt; about 25 to 50 minutes); then in order on the shipper's acks: the 5080 full grid as run-ca3-pc1-v4-eff-5080-20261007-d, the third 5090 pass (1,100 MHz down), the microbench and the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the 5080 grid's knee and best points to the site audit lane for row 17 as read. THE ATTEMPTS CENSUS COMPLETE (adv-accept row 90, 01:34 BST, 20,000 seeds, closing the partial named at 00:00): 42,711 rejected candidates; (a') 83.5 percent, (a) 11.6, (b) 3.0, (c'') 1.1 (459 candidates), constant bit 0.4, saturated 0.3, (c') 0.05, distinct 0.04, lane-constant and bias 0; per-candidate rejection 0.681, flat across attempts 0 to 3 (the halves agree to a tenth of a percent); accepted-attempt mean 2.136, max 28; 0 exhaustions; P(256 consecutive rejections) 2e-43 per seed. The number for spec 1.4.6: under sub-version 3 the per-candidate rejection is 68.1 percent and the expected attempt 2.1. adv-accept's shards run on in the pool's gaps under the mechanical yield; the box-hours cross 8 later tonight. CLASS-V5 LANDED ON BOTH MIRRORS (the v5 lane, 091a0758 at 01:40 UK): the full pre-push gate GREEN at 71 checks (stamp on 48d38493, the last code change); the igneum-pow suite on box 2 (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs byte-identical to the merged crate's export, so e5a4ac5978462156, 7c54302b487340a1, a217c7f698880830 and 82b19cbde8557ea5 hold under master's recipe form, recheck 2, scratch 7, spec_readback 2); spec-constants 28 rows agreeing; identity grep 0 hits. Carried since 61588347: main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2; the 61-row era reading and the class v5 attempts census on the spec, the page and the ledger; AP-F8-3; spec 1.4.7 and 1.8.6 with the constants and id tables; the AMD fingerprint row; the kits branch and master merged; two corrections the proofs found: master's program_id_derivation text lacked the class v5 rung-0 arm (the v5 packs' text named the class recipe while the id was the plain form; the arm added to the TEXT, re-exported, ids unchanged; a post-freeze change on the class-v5 line, so 0.3.25's pairing, never 1c420786's), and the public-export scrub (the founder's name six times on the page, the zone name in three files; gone). Incoming to the page: the Arc fingerprint, F9 and F1. THE MOVE FILE NOT PUBLISHED (the shipper, 01:41 BST): build-1's /fleet/move.json still names commit 2720d8d2 with the 22:30 BST minute; no FETCHED count, no named minute; the fleet lane (ac055d60427caab99) has answered nothing since its 22:4x report (asks at 01:05, 01:16 and 01:41; its task output last written 22:21 BST, its last action a hand read of dn3-g1's proven share), the second dark lane beside the build-server lane (last written 22:36 BST). So 02:00 BST cannot hold; the 02:53 BST ceiling (DAA 32,400) stands only if a signed move file lands at once and the 34 pullers fetch inside forty minutes; main has the clock line with the two options (wake or replace the fleet lane; or a fourth re-cut from a morning minute, the Mac entry standing down with it). The publish record's shape stands: the Mac entry at the minute (staged, DMG 1aa301cc, both folders, armed); the hive and the Windows pairs on main's word; the pairing 1c420786, 091a0758 0.3.25's. Every other gate on dfbd1e10 green and recorded. THE RUNG-0 ARM CONFIRMED (the v5 lane, 01:4x UK): 987e90e8 touches only Program::program_id_derivation, the text in program.json; Program::program_id untouched (the v5 rung-0 plain-form branch since the freeze); the crate at 091a0758 and 1b5684ec (master 35602b30 merged, pushed 01:41 UK) derives every pinned id byte for byte (packs 20 on box 2 comparing all three pinned packs' files including program_id and leaves.bin; spec_readback 2); the shipper told 091a0758 and 1b5684ec are 0.3.25's pairing, 0.3.24 on 1c420786. THE SM-SPARSE JOB (run-ca4-pc1-ca4sparse-5090-20261007, exit 0 at 00:41:53Z, 1,171 s, the 5090 alone, every fingerprint matched, the Power Helper answering every command on the padded write, the card left unlocked at 2,855 MHz): the SM-sparse reading does NOT exist; the research lane's worker ran its base kernel on every variant row (its race line "race 0 ms variant base" on all 48 rows, no NVRTC compile text), so --bench never honoured --variant sp-w32; the sparse rows equal base in rate and drift in watts with the card's heat only; the rerun waits on the research lane's exe honouring the flag. What stands: a repeat of the efficiency pass at two states, 32 s rows, the card alone: v4 unlocked 137.07 MH/s at 465.5 W (0.294 MH/W), at 1,300 MHz 134.26 at 309.9 W (0.433; 155.6 W back for 2.05 percent of rate); v3 unlocked 136.71 at 331.6 W (0.412), at 1,300 134.03 at 219.4 W (0.611; 112.2 W back for 1.97 percent); the v4 premium 133.9 W unlocked, 90.5 W at the knee; the three power fields agree within 0.2 W on every row (power.draw = instant = average on driver 617.14), which settles the field question on PC 1's side and leaves the 5080's 110 W gap to the fleet's rented card's sampler. Next on the shipper's ack: the 5080 full grid (-d) through the cleared helper sequence, the third 5090 pass, the microbench, the seven packs, the two tunes, the hot-table ldcs rows (kit and job at 292fcc75). THE --variant FAULT FIXED (the research lane, counter-asic-4, UTC clocks on 8 October): 00:44 the fix (a --bench with --variant runs the pinned race and installs the named kernel; the RESULT line carries variant=, sparse_blocks=, block_warps=; a served kernel other than the requested one prints variant_not_installed); 00:46 the known-failed test on build-1 against the real class v4 pack, no card (base: race off, 524,288 blocks of 32, "variant base"; sp43-w32: race on, 43 sparse blocks of 32 warps, the rewritten kernel with the nonces argument and the unit function, 43 blocks of 1,024; PASS; before the fix both read the base shape); 00:46 the Windows exe igneum-worker-cuda-ca4sparse3.exe sha256 0ba97edcd5c46a302a7ff5ddd1bbb1e493ca15f64d0757820ed645972df3bb56, mingw exit 0; the commit after 2d0013d1; the hash lane has the sha, the test's lines and the rerun's job shape (the same 48 rows, the race line per row); the op-mix re-weight stays behind the SM-sparse reading, the served 3.4x standing; the clean efficiency repeat in the file's 20.3a (6.6 pJ per counted op). THE SPEC'S LAST CRATE-DEPENDENT SENTENCE CLOSED (the site audit lane, master 56eebc0d at 01:49 BST, gate GREEN on c2c92eab, 71 checks; spec_readback now 3 tests): 1.4.6.4 states dataset_elem in full (the eight operations, the three constants, 32-bit wrapping) with two pinned vectors (dataset_elem(0x00000fed, 0x9E3779B9, 0x7F4A7C15) = 0x5c7dabd2; dataset_elem(0x0fffffff, 0, 0) = 0x7662c1ec) that spec_readback.rs reads from the text and checks against the crate, so part (c) computes from the text alone (34845c47); 1.4.6.5 names the class v2 figures as class v2's and carries the shipped rule's own census sentence (20,000 seeds, 68.1 percent rejected per candidate, the per-part shares, mean attempt 2.1, max 28, 0 exhaustions, 2e-43). The text-derived re-run on this text is the proof it is sufficient end to end (asked of adv-accept-3). THE MOVE FILE STAGED (the shipper, 01:5x BST): id mdfbd-1, commit dfbd1e10, want_digest b1ba7822, both pair slots on build-1's served tarball dfbd1e10-node-lane.tgz (e59ed0e6), at_epoch 0, signed with the fleet key on the Mac and verified against the fleet's public key in the puller's namespace; the read-back on placing it: the served file's id by curl and the first FETCHED on the relay intake; the 34 pullers fetch inside their one-minute timers (27 MB from build-1), the last FETCHED about five minutes after the file, the earliest minute ten after that. THE REAL LATEST-PUBLISH CLOCK: the file alone halts every miner on the restart, because each box's pack gate PAIR_MINER_SHA16 lacks aa8c2978 and the puller does not carry the file's miner sha into the restart environment; so route (A) also needs one ssh line on each of the 34 boxes before the minute with the fleet's tooling (the fleet lane's, or the shipper's on main's word). Absent main's word by 02:15 BST the shipper stands the Mac entry down under the ceiling rule (no app alone on b1ba7822) and 0.3.24 becomes a morning minute with a fourth re-cut. ROUTE (A) STAGED TO ONE COMMAND (the shipper, 01:5x BST): the gate script r0324/move/pair-gate-aa8c2978.py in its scratch (dry run by default, apply on the literal argument, the fleet's own Box helper and label list, nothing restarted); the dry run read 33 of 35 boxes, every one carrying the old gate list with fb147dd1 last and aa8c2978 absent, no env-last override; unreachable dn3-relay and p2-4090-1b (dead Vast proxies; they fall off at the move and rejoin by the pull); the apply about 90 s for the 33 with each gate read back and counted. THE F9/F1 INTERIM (the attack-pass lane, read at 01:5x BST): 71,292 seeds, 0 exhausted, 0 panics, max attempt 30; F1 0 failures at 2 h 23 min; the move's gate reads clear. On main's (A): apply 02:00, the file placed 02:02, the last FETCHED about 02:05, the minute 02:15 BST; main has the clock. Nothing applies before the word. THE SPEC TEXT SUFFICIENT END TO END (adv-accept-3 Q4d, 01:52 to 01:57 BST on build-2 at 16 cores; report section 6.6 on build/adv-accept-3, log 984-textderive-56eebc0d.tsv, every row equal to its Q4c row): the spec text at master 56eebc0d, implemented with nothing from the crate (text.rs: 0 igneum_pow imports; dataset_elem from 1.4.6.4, its two pinned vectors checked at start), reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences on every field; no sentence of the generator or acceptance sections needs the crate; the documentary finding (AP-F8-4, AP-F8-5) closed in full on two measurements; the lane at its end, 3.35 box-hours in all. F9 AND F1 AT 00:59Z (class v5 at 1c420786, pairing e5a4ac5978462156, build-1): F9 73,691 of 100,000 chain-shaped seeds written, 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; the attempt histogram 23,119 / 15,981 / 10,805 / 7,547 / 5,181 / 3,415 / 2,439 / 1,653 / 1,119 / 744 / 529 / 389 / 258 / 152 / 113 / 72 / 54 / 40 / 31 / 14 / 15 / 5 / 2 / 6 / 2 / 4 / 1 at 26 / 1 at 30, r about 0.69; the 10^5 about 01:30Z (02:30 BST). F1: the 10^5 redundancy census at 2 h 28 min under its lease with no end marker (18 minutes on an idle box; under tonight's load no minute named); its panic path live and empty, 0 failures the honest reading. Both land as record lines, then the board's close per item on sub-version 3 and class v5. AP-F8-5 ON TWO MEASUREMENTS (the site audit lane, commit 116e6055, master 5c77a7ac at 02:05 BST, gate GREEN 71 checks): the row carries Q4c (8b834634, 0 of 400 with one crate function, section 6.5, log 983) and Q4d (56eebc0d, 0 of 400 with no crate import, section 6.6, log 984); the public ledger and the ledger page regenerated; nothing open in the spec or the ledger on the audit lane's side. THE 5080 FULL GRID (run-ca3-pc1-v4-eff-5080-20261007-d, exit 0 at 01:54:00Z, 4,118 s; PC 1's dock card alone, driver 617.14, app 0.3.20, mem 14,801 MHz throughout; every lock through the cleared helper sequence, every command answered first time, every fingerprint matched, clocks reset and read back): the knee as a reading: the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes (v4 71.19 of 71.41 MH/s; v3 71.11 of 71.28) and falls 5.2 percent at 900 MHz on v4 (67.66), where the 75-minute budget ended the grid (v3's 900 and below not taken; the drift check skipped); so the 5080's knee sits between 1,000 and 900 MHz, a third of its 2,963 MHz boost, lower than the 5090's 1,300 (84 SMs at 2,960 MHz have more compute headroom per unit of its 960 GB/s than the 5090's 170 SMs per unit of 1,792 GB/s; the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: v4 at 1,100 MHz, 71.20 MH/s at 146.6 W (0.486 MH/W; 106.5 W recovered for 0.29 percent of rate); v3 at 1,000 MHz, 71.11 at 103.7 W (0.686; 66.0 W for 0.25 percent). The v4 premium 83.4 W unlocked (253.1 against 169.7), 41 W at the best points (146.6 against 105.6 at 1,100). Per tier: a 5080 owner on class v4 locked near 1,100 MHz draws 147 W instead of 253 for 0.3 percent less rate (MH/W up 72 percent) and the shadow's residual cost is 41 W. Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 71.41/253.1/0.282 ; 71.28/169.7/0.420 (sm 2,963/2,977); 2850 71.41/229.5/0.311 ; 71.29/155.3/0.459; 2700 71.41/209.6/0.341 ; 71.29/149.2/0.478; 2550 71.41/193.0/0.370 ; 71.29/134.4/0.531; 2400 71.41/176.0/0.406 ; 71.29/128.7/0.554; 2250 71.41/165.6/0.431 ; 71.28/117.3/0.608; 2100 71.38/157.7/0.453 ; 71.28/112.3/0.635; 1950 71.37/154.0/0.463 ; 71.26/111.6/0.639; 1800 71.35/150.3/0.475 ; 71.24/113.4/0.628; 1650 71.33/151.4/0.471 ; 71.22/109.7/0.649; 1500 71.30/149.2/0.478 ; 71.19/110.6/0.644; 1400 71.27/149.6/0.476 ; 71.16/107.0/0.665; 1300 71.24/147.9/0.482 ; 71.14/107.7/0.661; 1200 71.20/149.4/0.477 ; 71.12/104.4/0.681; 1100 71.20/146.6/0.486 ; 71.11/105.6/0.673; 1000 71.19/149.0/0.478 ; 71.11/103.7/0.686; 900 67.66/137.8/0.491 ; not taken. Throttle reason 0x400 (the power governor) on every row, never the clock lock, so the draw floor of about 147 W (v4) and 104 W (v3) from 1,500 MHz down is the memory system plus idle, not the SMs: the clock lever is spent by 1,500 MHz on this card. The three power fields agree within 0.2 W on every row. The site audit lane has the knee and best points for row 17; the bench table's 5080 row takes "71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", class v4 cost "+83 W unlocked, +41 W at the best points", hive core 1100 (the mem clock unchanged) once the fleet's rented-5080 sampler question is closed. Next on the shipper's ack: the third 5090 pass, the SM-sparse rerun on the fixed exe, the microbench, the packs, the two tunes, the hot table. THE NIGHT'S MOVE OUTCOME (the shipper, 02:58 BST): main's word on (A), (A') or (B) did not come (asked 01:41, 01:50, 01:53, 01:56 by the shipper and 01:42, 01:52, 01:5x, 02:00 by the coordinator); the gate script not applied (the dry run's 33 of 35 the only read); the move file not placed (build-1's /fleet/move.json serves m2720-1, 2720d8d2, the 22:30 minute, by curl at 02:56); no move minute; the stand-down under the ceiling rule holds from 02:15 (the shipper's stand-down line at 02:15 was not sent, its miss, the state unchanged); the Mac entry standing, not published (staged on DMG 1aa301cc in both folders, the live manifest at 0.3.23). A FINDING: build-1's Devnet 3 seed (the process on 26631 with JSON RPC 27632, the node lane's DAA reader) is DOWN (no such process; node1-dn3 26671 and the observer 26651 run on 2720d8d2; the node lane's 0.3.24 reader on 28690 runs but answers no DAA by the envelope tried), so the node lane's DAA reads since 25,169 at 00:52:38 BST may have stopped with it; at 1.0 DAA/s the DAA passed 32,400 at about 02:53 BST, the 39,600 floor is lost, and the fourth re-cut is from a morning minute main names (before 12:50 BST, or the three heights move with the floor). Every Devnet 3 node is on the 0.3.23 pin 2720d8d2, digest ba75bf6f (the 22:30 move; dn3-j1 behind its proxy unverified since); nothing of 0.3.24 is on any box or in any manifest. The night's 0.3.24: every gate green on dfbd1e10, the kit on four platforms, the move unmade for want of one word and two dark lanes. THE ATTACK-PASS BOARD'S CLOSE (lane (d), 01:58Z on 8 October; record docs/analysis/attack-pass-2026-10.md on the mirror's attack-pass; box-hours approximate: build-2 about 7 h, build-1 about 9 h plus about 6 h of F6 batches and F2 solvers earlier in the day). F9 so far: 89,301 of 100,000 chain-shaped seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 20: 20, 21: 6, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1; r about 0.69), three chunks on their cores to about 02:20Z; F1 the 10^5 redundancy census at 3 h 22 min on 17 threads, healthy, no end marker, 0 failures on its live panic path. The board: F1 shadow redundancy PASS on sub-version 3 (max 5.078 percent at honest-compiler parity; AP-F1-1 on the v5 list at 3.0 percent), running on v5; F2 mixer round margin PASS effort-bounded (no trail under weight 20 to 24 at 2 applications, 29 to 35 at 3, 39 to 47 at 4), not re-run on v5 (the mixer unchanged); F3 chained cache j+1 PASS, not re-run; F4 weak-day census PASS on v4 on the DSP-bound metric with AP-F4-1 reconciled with adv-mixer-2 (median 226, 15 days a century, worst 2050-04-28 at 1.113x), on v5 PASS at 8ca66afa (0 of 2^24 days over 1.1x on both metrics, AP-F4-1 FIXED-AND-PASSED); F5 chip-model sweep FIXED-AND-PASSED (the F2 hour skipped by decision), not re-run; F6 verifier worst case PASS (worst of 10^5 at 8.708 ms half-core; O-1.14 closed, i7-9700K 6.334 ms), not re-run; F7 era draw PASS on all three (0 of 6 re-rolls), not re-run; F8 uniformity FIXED-AND-PASSED on sub-version 3 (60 of 64 under 1.2x; AP-F8-1, 2, 3 closed), PASS on v5 (61 of 64, worst 1.50x, the residue p4, p8, p10; p34 under); F9 edges, hot set, grinding PASS on sub-version 3 (34 of 105,064 edges bounded; grinding +0.004 percent), the exhaustion count running on v5; F10 ladder signal PASS, not re-run (node rule). Findings of the pass, all in-house: AP-F1-1, AP-F4-1, AP-F5-1 (the X9), AP-F8-1, AP-F8-2, AP-F8-3; two operating hazards fixed (AP-H1 the box clean, AP-H2 the shared binary path). The open tail (p4, p8, p10, and p34 on sub-version 3) is named in the public report; no outside party holds it (the attack-pass lane's close wrote "disclosed to the firms", stale wording from before the in-house ruling; its record file is to say "named in the public report"). THE SEED'S DEATH AND THE DAA NOW (the node lane, 03:0x BST): build-1's Devnet 3 seed log /home/build/dn3seed.log ends at 01:09:05Z at DAA 29,732 mid-stream with no stop, shutdown or panic line, so it was killed abruptly (it ran under nohup from a shell, not a unit; no journal names the killer; the OOM record needs sudo the lane lacks); its datadir /home/build/dn3seed/igneum-devnet-3/datadir is intact (13 GB) and it stays down until the shipper says; the lane's reads 25,169 at 23:52:38Z and 28,906 at 00:55:09Z came from it while it lived. The DAA now from node1-dn3 on 28670: 32,659 at 01:57:50Z (the observer 32,660), both on 2720d8d2; the chain passed 32,400 at about 01:53Z, 39,600 lost. The fourth cut in one line: the script on release-0.3.24-node reads the DAA from 28670, sets the floor to the morning minute's publish DAA plus 7,200 rounded up to the next 3,600, commits, pushes both mirrors and dispatches the gate set (about 20 minutes to the pin line, then the fast-time pair about 14); the latest minute before the three heights move with the floor is about 11:50Z (12:50 BST), where the floor reaches 79,200; nothing is cut until main names the minute. A morning item for the box owner: a process on build-1 was killed at 01:09:05Z without a log line while the box carried a load of 400 to 600; the killer (OOM or a sweep's cleanup) is to be read from the journal with sudo before anything long-lived runs there again under nohup. THE BENCH LOG ENTRY (the hash lane): docs/bench-log.md "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080" (both cards' full tables, the knee per card, the best MH per watt points, the premiums at the lock, the lever's limits, the job ids and clocks, the rented-5080 watts note) on the mirror's master as merge 773b93a8 at 02:04:47Z (commit 11c698ad); the audit lane writes row 17's sentence from it. PC 1: the third 5090 pass run-ca3-pc1-v4-eff-5090-floor2-20261007 (1,100 MHz down to 300) since 01:57:03Z, about 28 minutes; then the SM-sparse rerun. ROW 17 AND THE 5080 BENCH ROW (the site audit lane, master 2c5c7f52 at 03:19 BST, gate GREEN on 6eb6fd9b, 71 checks): docs/evidence.md row 17 carries both cards' efficiency passes from the bench-log entry (the 5090's knee, best points and premium; the 5080's 71.41 MH/s at 253.1 W unlocked, 71.20 at 146.6 W at 1,100 MHz, v3 at 1,000 MHz 103.7 W, the premium 83.4 W to 41 W, the knee between 1,000 and 900 MHz, the per-tier reading, the Ember Tune lever), a what-moved table for 8 October, /evidence rebuilt (865a0a5e); site/miner-bench.json's RTX 5080 row states the team's pass as the card's figure ("71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", "+83 W unlocked, +41 W at the best points", hive core 1100 with the memory stock, driver 617.14, the bench-log entry as the source) and keeps the rented-fleet sampler reading with its 110 W gap as the open question; /miners rebuilt at 35 rows (6eb6fd9b); 0 identity hits; nothing deployed, the deploy the morning hand-off. The design pass on ca3-coord (015cc839) now sits behind this master and rebases onto it before its own landing on main's word. THE DESIGN PASS REBASED (the coordinator, 03:2x BST): ca3-coord rebased onto master 2c5c7f52 as the three site commits only (f5b7140c the design pass, 8cc4cbc6 the phone grid, 9ad3fdc9 the six-column row; the two commits already landed through the record branch skipped), site/miners.html rebuilt at each from the merged miner-bench.json so the page carries the 5080's new row ("71.4 stock (71.2 tuned)") under the design; the diff against master is build.mjs and miners.html only; pushed to the mirror (pre-push GREEN); it lands on main's word after the captures, one gate run. ADV-MIXER-3's LINE (read from its report at tip e02297ae, 03:18 BST): queue 17 finished on build-1 at 01:3x BST; Q2 single-bit avalanche at 2^27, k = 2 and 3 on day 20729: 0 holes, 0 cells beyond 6 sigma at band 0.00026, PASS (the k = 1 finding stands as the single-application diffusion); Q2b t-bit avalanche on day 20733 at 2^28: 0 cells beyond 6 sigma at band 0.00018, PASS (k = 2, 3, 4 on 20729 at 2^28 the same); Q3 at k = 8 NOT run (killed at 20:20 BST under the lease rule, not re-queued; k = 2 to 7 clean with 0 deterministic bits on both days), named partial; Q6 the day-20733 SAT ladder: k = 2 and 3 TIMEOUT at the one-hour cap, k = 4 on one build-2 core since 03:05 BST, its cap about 04:05; one pre-emption in its ledger (23:58 BST, 21 minutes of a 2^27 row lost, re-queued); box-hours about 3.0 wall-hours of sweep (build-1 1.9, build-2 1.1) plus about 4 single-core CaDiCaL hours, about 7 with the 20733 ladder. The pass's close with the per-lane table and totals at about 04:05 BST; section 13 on crypto-engage (docs only) merging the current master and going through the gate to the mirror's master so the record cites a master commit. Box 2 at 03:20: adv-accept 87 cores in four shards with three waiting, adv-mixer-3 one core; build-1 load 34, no adv lease. THE DESIGN PASS'S OVERLAP ON THE BOX (the CI steward, 03:33 BST): the 1440 and 390 dark captures of /miners from ca3-coord 9ad3fdc9 taken on build-2 under lease pool 4 (Playwright chromium 1194, the recorded feed; /srv/artefacts/captures/ca3-coord-9ad3fdc9/miners-1440-dark.png 1440 x 4280 and miners-390-dark.png 390 x 9779); the overlap sweep on the same checkout, 390 to 1600 px, light and dark: RED, 3 findings on the change itself: at 1280 px dark and 1600 px light and dark the date span in the lead cell's class v4 line is COVERED by the rate cell (4 of 5 sample points under td.big); 390 to 1024 pass. Cause: the branch's last gate ran on the Mac, which has no browser, so the sweep skipped and read GREEN; on the page the row rule's white-space:nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell from 1280 px up. FIXED at ca3-coord 2ca45001 (the lead cell's rule at the row rule's specificity, max-width 360 px, the class v4 line wrapping with overflow-wrap), rebuilt, pushed; the sweep and the captures re-run on the box before main's word. THE IN-HOUSE PASS'S PATH TO MASTER (the crypto lane, 03:2x BST): adv-accept's box-hours crossed 8 before 02:00 BST and sit near 10 (87 cores in four shards; it sweeps on under the mechanical yield, its reading unchanged); crypto-engage merged master 56eebc0d at 342b6730 (one conflict in funding.md, the pre-public scrub against the rewrite, resolved to the in-house pass with the scrub applied; the founder never named in in-house-pass.md or funding.md), the full gate running, merge-to-master on GREEN; section 13.3: master's igneum-pow moved after the freeze in four files (src/emit.rs and src/generator.rs, the derivation string and its recipe helpers, ids unchanged; tests/derivation.rs and tests/spec_readback.rs), none the hash, so the object the pass bounded is unchanged in every operation the hash performs. THE PASS IN ONE LINE (the crypto lane, 03:2x BST): eight of nine lanes closed, adv-mixer-3 on one SAT timeout (about 04:05 BST), adv-accept sweeping to its 16 box-hour line (9.2 now, the reading saturated at the 1.002x class), adv-cache-2 on one line shard; no break of class v4 sub-version 3; the acceptance's hot-set class closed by the class v5 floor (9 of 9) and its diffuse era-stride class routed to the next class; the weak-day FPGA tail reconciled and closed by a measured redraw rule; the attempts census complete; the spec text proven sufficient by two read-backs; one pod at USD 0.33 in the whole pass, none originated by the lane. THE THIRD 5090 PASS BELOW THE KNEE (run-ca3-pc1-v4-eff-5090-floor2-20261007, running at 02:34Z on its 500 MHz step; the steps lengthen as the rate falls since the batch count was sized from the unlocked rate, about 155 s at 500 against 60 at 1,100; the helper answering every command on the cleared sequence, every fingerprint matched, the 5090 alone). Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 137.09/456.7/0.300 ; 136.79/320.0/0.428 (sm 2,858/2,862); 1100 120.98/275.9/0.439 ; 117.32/198.6/0.591; 1000 110.03/254.9/0.432 ; 106.73/180.2/0.592; 900 97.43/232.7/0.419 ; 94.33/174.5/0.541; 800 86.00/216.3/0.398 ; 83.41/166.6/0.501; 700 75.98/202.7/0.375 ; 73.58/156.4/0.470; 600 65.30/178.2/0.366 ; 63.25/153.3/0.413; 500 53.03/166.5/0.319 ; v3 running. Reading: below the knee the rate falls about 10 percent per 100 MHz on both classes (compute-bound: the shadow and the base program no longer fit the memory wait) and MH per watt falls with it from 1,100 down, so the best point stays where the second pass put it (v4 at 1,200, v3 at 1,300); the driver took every lock down to 500 (the SM clock within 10 MHz), so the floor is below 500 MHz and is not where the optimum lives; the v4 premium below the knee 77 W at 1,100, 75 at 1,000, 58 at 900, 50 at 800, 46 at 700, 25 at 600 (the ALU work shrinking with the clock as the rate does). The exit line, the 400 and 300 rows, the drift check and the restore at its close; then the SM-sparse rerun on the fixed exe (each sparse row reading served= and sparse_blocks=, marked variant_row=FAILED if served as base). F9 AND F1 AT 02:34Z (class v5 at 1c420786, build-1): F9 98,945 of 100,000 seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 18: 39, 19: 19, 20: 24, 21: 8, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1); the last three chunks within minutes of their ends; F1 at 4 h 02 min under its lease, no end marker, 0 on its panic path. The pass record's wording fixed on the mirror's attack-pass at 9474cea8 ("named in the public report"; no "firm", "firms", "escrow", "prize", "paid review" or "Lot" line in the pass record or the ten row records; identity grep 0 hits); the section's merge to master after the two record lines, through the full gate in a detached worktree. THE SECOND SWEEP ON THE DESIGN PASS (the CI steward on 2ca45001, 03:38 BST): the desktop widths pass; RED at 390 px dark only, three findings on the lead cell (the card name and the class v4 line covered by the rate cell), the cause the new 360 px max-width on the phone grid; FIXED at ca3-coord 5158276c (the lead-cell width rule scoped to widths above 1,100 px, the phone grid's lead cell with no max-width), rebuilt, pushed; the sweep and captures re-run on it. F9 PASS ON CLASS V5 (the attack-pass lane, class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, the last chunk written 02:34:54Z): 100,000 of 100,000 seeds drawn through the chain path (era-composed class), 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; histogram 0: 31,454, 1: 21,460, 2: 14,660, 3: 10,263, 4: 7,047, 5: 4,701, 6: 3,297, 7: 2,256, 8: 1,532, 9: 1,027, 10: 702, 11: 509, 12: 365, 13: 216, 14: 153, 15: 103, 16: 80, 17: 56, 18: 39, 19: 20, 20: 24, 21: 9, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1 (first-draw acceptance 0.3145; the mean attempt index 2.185, so 3.185 draws per seed on average; 4,862 seeds, 4.86 percent, at index 8 or above and 255, 0.255 percent, at 16 or above; the 256-attempt cap and the deterministic last resort never reached; the lane's first line read 1.993, a slip it corrected); the exhaustion gate holds for the 0.3.24 move; record docs/analysis/attack-pass/f9-grind.md and the lane (d) section on the mirror's attack-pass. F1 still running (4 h 05 min, 16 cores, 0 on its panic path, no end marker). F9's record on the mirror's attack-pass at 2bcb7e08 (the lane (d) row and f9-grind.md section (d); feature gate GREEN); F1 the one open item before the lane (d) merge to master. THE DESIGN PASS GREEN ON THE BOX (the CI steward on ca3-coord 5158276c, 03:4x BST; build-2 under lease pool 4): the overlap sweep 390 to 1600 px, light and dark, GREEN, 0 findings (the known-failed fixture fired first); the 390 px capture byte-identical to 9ad3fdc9's (the phone shape that passed before), the desktop widths carrying the wrap at 4,640 px tall; the four dark whole-page captures on build-1 under /srv/artefacts/captures/ca3-coord-5158276c/: miners-390-dark.png (sha256 9eec8f27..., 509,158 bytes), miners-1280-dark.png (1b6e636d..., 438,541), miners-1440-dark.png (87387e14..., 445,402), miners-1600-dark.png (d53973cd..., 448,545); the run log /srv/builds/bs-ci-steward/cap-out/run-5158276c.log on build-2. The branch's gate record: a full gate on the Mac skips the sweep (no browser), so the box line is the sweep's verdict for 5158276c; the branch waits on main's word on the look and lands in one gate run. THE IN-HOUSE PASS'S RECORD ON MASTER (the crypto lane): crypto-engage dab0c89f (gate GREEN, 71 checks) landed through merge-to-master.sh --remote build at 03:50 BST as master 00b8cd1b: docs/plans/cryptanalysis/in-house-pass.md section 13 (the roll-up, every lane's reading, the frozen-object note) and funding.md's in-house row and brief, scrubbed under founder-strings-check.sh. AN EXCEPTION OWNED (03:39 to 03:50 BST): the lane's first merge call used the tool's default path, which reads CI on GitHub with gh run list; GitHub is suspended and the rule says never poll it; the tool polled 21 times (each 403, nothing pushed, nothing read); the run's process outlived the task stop and the lane ended it by its pid at 03:50 BST, then used --remote build; the breach is the tool's default against the rule and the lane's for not passing the switch; no state moved on GitHub's side. The coordinator's order on it: merge-to-master.sh's default remote must refuse GitHub while the suspension stands (the CI steward, a gate-side fix with a known-failed self-test), so the rule does not rest on every lane remembering the switch. THE THIRD 5090 PASS CLOSED BY ITS CAP (run-ca3-pc1-v4-eff-5090-floor2-20261007, ended by the 45-minute cap at 02:42:05Z during the 300 MHz step, exit -1, its own finally block never ran; every row taken matched its fingerprint, the 5090 alone): the 500 row's v3 side 51.37 MH/s at 136.4 W (0.377); 400: v4 42.62/152.5/0.280, v3 41.32/131.3/0.315 (sm 390); 300 not taken; no unlocked-end drift check; the driver took every lock down to 400 (the SM clock within 10 MHz), so the floor is at or below 400 MHz. The reading: below 1,300 the rate falls about 10 percent per 100 MHz on both classes and MH per watt falls from 1,100 down (v4 0.439 at 1,100 to 0.280 at 400; v3 0.592 at 1,000 to 0.315), so the optimum stays at the second pass's points (v4 1,200 MHz, v3 1,300) and nothing below 1,100 is worth the knob's time; the v4 premium below the knee shrinks with the clock (77 W at 1,100, 46 at 700, 21 at 400). AN EXCEPTION OWNED: the 5090 sat at the 400 lock (390 MHz, 127 W mining) for four minutes until run-ca3-pc1-clocks-restore-20261008 (02:45:20 to 02:46:30Z, exit 0) started the helper over an empty cmd.txt and sent rgc ("All done"), the card reading 2,880 MHz after; the cause the batch count per step sized from the unlocked rate, so the low steps ran 2.5x longer than planned; the fix in the scripts: the budget check ends the grid with the restore inside the cap, and a probe dev line answered in helper.log counts as the helper up when its heartbeat file stays stale (the restore answered at once with helper.alive stale past 60 s). THE SM-SPARSE RERUN: fetch-ca4-sparse3-exe-20261008 landed 02:49:57Z (sha256 0ba97edc...), run-ca4-pc1-ca4sparse-5090-20261008 published 02:51:15Z on the hash lane's own order (the shipper's acks were for the void host slot); each sparse row reads served= and sparse_blocks= and is marked variant_row=FAILED if served as base; the close about 03:15Z (04:15 BST). THE STEP-BUDGET FIX ON MASTER (the hash lane, merge 9fd8b1d8 at 03:02:03Z on 8 October, commit 0b00c42e, the full gate GREEN): the efficiency pass keeps four minutes of its cap for the restore (every step and lock guarded by the deadline minus four minutes) and sizes each step's batch count from the last rate read for the pack, so a 60 s step stays 60 s as the rate falls; a probe dev line answered in helper.log counts as the helper up when the heartbeat file stays stale (all four lock scripts); the gate check tools/ci/pc1-step-budget-check.sh with the known-failed case first (under the old rule a lengthening grid ends on the cap with no restore; under the new it ends with the restore at 1,500 s of 2,700), wired into pre-push.sh and checks.txt (74 checks). The 5080 Ember tune, the 9070 XT tune pass and the hot-table ldcs rows publish behind the SM-sparse rerun, the microbench and the packs. THE SM-SPARSE RERUN FAILS THE SAME WAY, NOW NAMED (run-ca4-pc1-ca4sparse-5090-20261008, the fixed exe ca4sparse3, started 02:52:48Z): every sparse row served=base sparse_blocks=0 variant_row=FAILED, the worker's own line "RESULT variant_not_installed requested=sp43-w32 served=base race=... variants 1 base only, no race (no other variant named)", no "compile:" text, so NVRTC never saw a rewritten kernel: the variant name is parsed into the request but never added to the race's variant table in this exe; the research lane's emulation test checked resolve and rewrite, not the race list the bench builds (a test of the wrong layer; the known-failed case must be the bench's own race line reading "variants 2"). The rows are base runs; no reading. The queue goes on: the microbench at the rerun's exit (about 03:15Z), the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the SM-sparse question's fourth row stays with the research lane, an exe whose card-free check shows "variants 2" in its race line getting the slot within the minute. CLASS-V5'S F9 ROW PUSHED (the v5 lane, class-v5 1d5e5d23 on both mirrors at 04:04 UK): the page's F9 row (100,000 seeds, 0 exhausted, max index 30, first-draw acceptance 0.3145, mean index 2.185, F9 PASS, the record file named), F1 stated as running with 0 failures (its own commit to follow), the Intel row not measured tonight; master merged twice (2c5c7f52 gated at 5f5e0a5c, full gate GREEN 71 checks at 03:45 UK; 9fd8b1d8 auto-merged and pushed on the hook's light gate, the full gate running on 1d5e5d23); the generated ledger files and the spec-constants check clean on the tree. THE THIRD --variant FIX (the research lane, 03:04Z on build-1 under lease, with the hash lane): the cause of the 02:52Z rows: the race's push looked the pinned name up in the empty order list through the variant lookup, whose on-demand sp path answers for any list, so the sparse variant was "found" and never pushed; the order is now a pure function with membership by name; --list-race prints, with no device, the race order the worker's own option handling builds and whether the rewrite applies: with the job's exact flags "variants=2 names=base,sp43-w32" and "sparse_blocks=43 block_warps=32 rewrite=applied bytes=22261 nonces_arg=1 unit_fn=1" (before the fix variants=1); exe igneum-worker-cuda-ca4sparse4.exe sha256 84846396559004a8df61881c15ecb42fa3fc1010ad99074e0c0b53e81bb1ca3b, the commit on the mirror after 7e9d52a6; the third rerun on the hash lane's queue at the next slot; the two failed runs stay the night's SM-sparse state, the op-mix re-weight held, the served 3.4x standing. THE GITHUB GUARD ON MASTER (the CI steward, tip 2f702735 at 04:05 UK; merges 53773860 and 2f702735, full gate GREEN 71 checks each): fa7e98fe adds the tracked marker tools/ci/github-suspended (suspended-since 2026-10-07T17:02:00Z, removed by main at the cut-over) and two refusals: merge-to-master.sh refuses a GitHub remote (origin by default, or any remote whose URL carries github.com) with one line naming the switch and exit 2 before any gh or git call; the pre-push hook refuses any push to a GitHub remote the same way (the hook reads the remote URL, so a bare git push origin is refused too); known-failed first in both self-tests; the live read on the Mac: merge-to-master.sh --remote origin exits 2, nothing contacted; two follow-ups (9484b988, a08423d4) fix the tool's own --self-test under the real marker. The rule no longer rests on any lane remembering the switch. F1 READ AT 03:05:58Z (the attack-pass lane; the census process itself, not the lease wrapper): state S with 17 threads, 15 cores busy over 45 s, 2 d 19 h of CPU banked over 4 h 30 min of wall, RSS 0.8 to 1.0 GB; computing, not hung. No rows can exist before the end: the harness collects every Report in memory under thread::scope and writes census.csv in one go at the end (no progress print), named as a harness gap in the record. Why fifteenfold against the v4 reference: under class v5 every candidate draw runs the (c''') distinct-index floor over 2^20 (about 1.8 core-s per candidate under the night's load, times 3.2 draws per program, about 5.8 core-s per program before the analysis), so 10^5 programs at 15 busy cores is about 10.7 h of wall, the end about 09:00Z (10:00 BST), nearer the early side as the load fell to 21. Ruling: not killed (a kill loses 4 h 30 min with nothing on disk); the lane (d) section merges to the mirror's master now with F9 and the F1 row reading "running, 03:06Z reading, projected end about 09:00Z", F1's record line in a second merge when it writes; the harness gains a progress line before its next 10^5 run. THE IN-HOUSE ADVERSARIAL PASS CLOSED (04:08 BST on 8 October; an internal adversarial pass, not an independent review; section 14 of in-house-pass.md at crypto-engage c099e818 landing on master through --remote build; every tip read from the mirror at 04:07 with igneum-pow identical to 017e7037 on all nine). Per lane (tip; box-hours; verdict; partial): adv-mixer d2ba3134, about 0.6 plus 1.8 single-core SAT hours, the algebraic structure BOUND, none; adv-mixer-2 2a632579, 0.31, BOUND for every chip, GPU and the verifier with the FPGA LUT-area FINDING (2^-10.8 of days, 15 a century, worst 2050-04-28 at 1.113x) closed by the measured redraw rule, none; adv-mixer-3 981bfff2, about 5.0 wall-hours plus 8 single-core SAT hours, Q1 BOUND (2^32 t uniform at k = 1 to 8, both days and 8 random days), Q2 and Q2b FINDING at k = 1 only and BOUND from 2 to 8 at 2^24 to 2^28, Q3 FINDING at k = 1 and BOUND 2 to 7, Q4 and Q5 BOUND from k = 1, Q6 SAT BOUND (k = 1 in 137 s, k = 2 to 4 timeout), the round margin 70 of 72 per item, partial Q3 at k = 8 not run, multi-bit masks and a MILP bound not attempted, GPU blocked; adv-cache 555c3e42, 0.55, the recompute shortcut BOUND on every row, none; adv-cache-2 91ca5ce1, about 2.25, the line census PASS at 2^35 + 3 x 2^33, the real programs PASS with the Devnet 3 site-0 FINDING, the diffuse era-stride class named (16 of 32 base programs biased under drawn eras against 2 of 32 under R = 29, 8 over 1.2x, worst 1.75x, under 0.1 percent of reads per site, 0 of 61 refused by the v5 floor, AP-F8-6), steering and the 16,384-day scan PASS, the window layer exact and the chip model's partial-store rows overstated up to 2.3x with the verdict unchanged, partial the line shard s2c waiting on build-1 since 23:09 BST; adv-cache-3 9452c0bf, 0.23, the chain-break or skip BOUND on every row with the pebbling optimum under the hold-every-k curve, none; adv-accept c8a98e46, about 9.2 at 03:25 BST running to its 16-hour line, the bypass FINDING confirmed and bounded (9 few-item hot sets in the tail of 408,067 accepted programs, 0 in 20 random, 1.002x at the largest; all 9 refused by the class v5 floor, 7 clean programs falsely refused among the 12 deepest, 3 mild residuals missed), the stand-in gap BOUND, distinguishers BOUND, the attempts census complete, partial the sweep at 408,067 of 10^6; adv-accept-2 92168536, about 9.0 core-hours and 0.3 pod-hours (the one pod), header grinding BOUND by card measurement (+0.09 percent on an A6000) and by tail (3e-7), one 0.1 percent repeat class for the rule's owners, none; adv-accept-3 7826d2b2, 3.3, exhaustion BOUND (P 1.0e-43), the last-resort path FINDING (correctness, unreachable; closed in class v5), steering BOUND (no property over 1.03x at 1 in 1e6 tries), the program id BOUND with the derivation-string FINDING (fixed on master and in the packs), determinism BOUND, the spec text proven sufficient by two read-backs, the era lever BOUND, partial the steering sweep at 975 of 10^5 full-rule seeds. Totals: about 30.4 box-hours of run across the nine lanes (lease waits excluded) plus about 9.8 single-core SAT hours; pod-hours 0.3 on one RunPod A6000, USD 0.33 in all, rented and destroyed by the fleet lane. The verdict: no lane broke the frozen object; the acceptance rule admits two residual classes of address concentration, both under 1.002x to a chip: the few-item hot sets, closed entire by the class v5 floor (9 of 9) at a 2.4 percent clean-rejection cost, and the diffuse era-stride excess the floor does not reach, routed to the next class with its lever; the weak-day FPGA tail reconciled and closed. Already changed by the pass: the derivation string in the shipped packs, spec 1.4.3 to 1.4.6 rewritten and proven text-sufficient, the chip model's partial-store and pebbling baselines corrected, the last-resort path flagged and closed in class v5. Still to come: adv-cache-2's s2c row and adv-accept's final count, appended when they land. CLASS-V5 GATED (the v5 lane): the full gate on 1d5e5d23 GREEN, 72 checks in 347 s (04:1x UK); class-v5 4a162aba on both mirrors at 04:12 UK with the page's F1 line stating the 04:06 reading (computing, not hung; census.csv only at its end; projected end about 10:00 UK); nothing of the lane's pending on a box or a watch. THE LANE (d) MERGE ON MASTER (the attack-pass lane, 399f8c4d at 03:16:35Z, 04:17 BST; attack-pass 4150f66d, full gate GREEN 45 checks on the branch): F9 PASS on 1c420786 (row and f9-grind.md section (d)), the F1 row as ruled (running, the 03:06Z reading, projected end about 09:00Z, 0 on its live panic path, the harness gap named), the in-house wording kept through a conflict with master's older copy, one founder-strings scrub the gate caught on the pass record (the attribution now "The founder's word"). The harness item: the progress line every 1,000 programs and the flushed partial census.csv (temp file and rename) committed on attack-v5-frozen at 18a9c04a, built on box 2, its known-failed test (a 4,000-program census killed by pid at the 2,000 line, 2,000 rows expected) running under lease pool class adv; the verdict and the push follow. THE SM-SPARSE QUESTION, THE THIRD RUN (run-ca4-pc1-ca4sparse-5090-20261008-b on ca4sparse4, 03:23:45 to 03:48:45Z, exit 0): the card-free check on the card's own exe listed the sparse variant (variants=2 names=base,sp43-w32, rewrite=applied), the race ran it, and NVRTC refused the rewritten kernel on every sparse row: "kernel_bound.cu(370): error: identifier "d" is undefined | igneum_hash_bound_unit(d, ou, baseNonc, mas, i, gid);" (the same for sp170, sp85, sp21, sp11), so the race installed base and every sparse row reads served=base variant_row=FAILED. The hash lane's reading to the research lane: the wrapper's call carries the kernel's parameter names cut by one character (d, ou, baseNonc, mas for ds, out, baseNonce, mask), which points at the rewrite's name capture against the PC's CRLF pack text (the Linux check reported a different byte count for the rewritten kernel): the first card test of the rewrite, the finding kept. The base rows a third repeat of the knee pass (v4 137.06 MH/s at 449.7 W unlocked, 134.23 at 301.4 W at 1,300; v3 136.79 at 329.8, 134.05 at 218.0), the card restored each time. The slot returns to the research lane on an exe whose card-free check compiles the rewritten text through nvrtc for sm_120 (on CRLF input). The queue: the microbench run-ca4-pc1-microbench-5090-20261007 since 03:52:14Z (20 probes of 60 s unlocked, then at the 1,300 lock; about 50 minutes), then the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. THE CLOSE'S MASTER COMMIT (the crypto lane, sent 04:55 BST for a 04:14 landing, the forty-minute gap its own): crypto-engage c099e818 (full gate GREEN, 71 checks) landed as the mirror's master 2882352c at 04:14:50 BST; the record cites the roll-up and every lane's reading at 00b8cd1b and the close (section 14) at 2882352c; further landings only for adv-accept's final count and adv-cache-2's s2c row. THE FOURTH --variant FIX (the research lane, 03:55Z on build-1 under lease): the cause was not the line endings: the rewrite's parameter capture wrote the substring length as end minus start where the last index needs plus one, so every argument lost its last character on any input; CRLF would have missed the anchors entirely; the rewrite now strips \r first (the same rewritten bytes from LF and CRLF, 22,266 on both) and the capture is right; the card-free check through NVRTC on LF and a CRLF copy, identical lines: variants=2 names=base,sp43-w32; rewrite=applied; call="igneum_hash_bound_unit(ds, out, baseNonce, mask, iw, gid)" params=6 args=6 names_match=1; nvrtc=libnvrtc.so.12 arch=sm_120 compiled=1 image_bytes=36256; the failed case the 03:23Z card line. Exe igneum-worker-cuda-ca4sparse5.exe sha256 a4550202b301faf22f5329c2ab4fa1c0aa6695dbdaf31c974f316dca2524d7d6, with the hash lane; the commit on the mirror after 3ac5d20a; the slot after the microbench and the packs. The three failures gave three repeats of the knee pass (the v4 premium 133.9 to 145.3 W unlocked, 90.5 W at 1,300 MHz) in the file's 20.3a. ADV-ACCEPT OFF BUILD-1 (04:5x BST, the coordinator's placement rule): adv-accept runs on to its 16-hour line (about 10:15 BST, 10.6 box-hours at 04:54, the reading saturated) in box 2's gaps under the mechanical yield, its build-1 shard ended at the frontier and its waiter withdrawn, so F1's census keeps build-1 (its 10:00 BST projection assumed load 21) until census.csv writes; adv-cache-2's four-minute s2c shard the one exception. Confirmed by lease status at 04:57 BST: build-1 holds F1 (release, 16 cores) and adv-cache-2's s2c (32 cores, its last shard) and nothing of adv-accept's; adv-accept's four holders and waiters on box 2, where the attack-pass lane's flush test waits at 1 free behind them (the same class, no yield case); the coordinator's placement rule: one adv-accept holder ends at its frontier for the flush test (a 4,000-program census, minutes), since adv-accept's reading is saturated and the harness fix gates the morning's F1 rerun class. Done at 04:59 BST: adv-accept's sweep-s05b ended at its frontier at 04:58:50 (46,460 rows kept) and the flush known-failed test took the 16 cores at 04:58:55; the shard re-queued behind it. ADV-CACHE-2 CLOSED (05:0x BST): its last shard s2c ran 04:56 to 04:59 on build-1 (PASS at 2^33 reads, control-level), so the line census totals 2^36 reads over 464 chain days with every statistic at the control's values; final box-hours 2.35 of run (0.08 a duplicate windows run by its build-1 drain, recorded), pod-hours 0; tip bfc3746c on build/adv-cache-2, igneum-pow identical to 017e7037; the biased-site class (AP-F8-6) and the window-layer pricing stand; section 14's row updated on crypto-engage, landing with adv-accept's final count. Eight of nine lanes at their end; adv-accept alone runs to its 16-hour line about 10:15 BST. THE CENSUS HARNESS'S PROGRESS LINE (the attack-pass lane, attack-v5-frozen 18a9c04a on the mirror): the attack-f1 census prints a progress line every 1,000 programs (count, elapsed, running failure count) and flushes a partial census.csv at the same cadence through a temp file and rename; the known-failed test on box 2 under lease pool class adv (binary 14180ef4...): a 4,000-program census killed by pid at the 2,000 line at 04:08:27Z (05:08 BST), census.csv holding exactly 2,000 rows, no tmp file, lease exit 143; PASS (the old harness's known fail zero rows); record f1-shadow.md section 12 on the mirror's attack-pass at c99f147f (riding the F1 record merge); a side reading: 1,000 programs per 286 s on 16 cores, about 4.6 core-s per program, confirming F1's build-1 projection of about 09:00Z (10:00 BST); the running 10^5 census stays on the old binary, every census after it on the new. F1 PASS ON CLASS V5 (the attack-pass lane; class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, 16 cores; census.csv written 04:20Z, 05:20 BST, after 20,774 s of census, 5 h 46 min, earlier than the 09:00Z projection as build-1 emptied): 100,000 of 100,000 programs through the string-seed draw with the (c''') floor; instructions saved min 0.000 percent, mean 0.623, max 4.688 (the worst seed attack-f1/95060: 6,912 to 6,588); chip-view ops saved mean 0.520, max 4.783; programs over 5 percent 0, over 10 percent 0; soundness: differential mismatches 0 of 100,000 (8 random states each), verifier mismatches 0 of 100,000; 0 panics; the histogram of saved in 0.5 percent bins from 0: 55,241, 20,597, 11,762, 9,851, 1,484, 656, 259, 133, 13, 4, 0, 0. Against the v4 10^5 (max 5.078, the AP-F1-1 letter miss): the v5 tip's worst program sits 0.39 points under the 5 percent letter and the top two bins are empty. F1 PASS on 1c420786 by the letter and at honest-compiler parity; the redundancy gate holds for the 0.3.24 move; AP-F1-1's v5 half FIXED-AND-PASSED at this count; record f1-shadow.md section 13 and the lane (d) row, merged to master next. The attack board on class v5 is complete: F4 PASS (8ca66afa), F8 PASS, F9 PASS, F1 PASS; the rest not re-run by rule. CLASS-V5'S F1 ROW (the v5 lane, class-v5 1095eaa8 on both mirrors at 05:24 UK): the page's attack row reads F8 PASS with the known residue, F4 PASS, F9 PASS, F1 PASS on the full 10^5, the rest not re-run by rule; the full gate running on 1095eaa8; nothing else of the lane's open tonight. THE CA4 PACKS ON THE 5090 (run-ca4-pc1-packs-5090-20261008-b, exit 0 at 04:22:54Z, 579 s; the 5090 alone through the installed worker, the lock and reset through the helper, every self-test PASS at both states): the int8 mma tile prototypes' inline PTX compiles under NVRTC 12.8 on sm_120 and matches the CPU reference (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1, mm1430 8e9b7066239d35d1), as do both per-load exports (404cad3b3399f9b3, ee5d7c71180e5ea7), sh256x27 (3d2e8245cc084d07) and the mx8-genesis control (7c28cfb06c5c65a9). Rows (MH/s / W / MH/W), unlocked then at the 1,300 lock: mx8-genesis 137.54/311.0/0.442 then 127.32/213.0/0.598; sh256x27 137.51/462.2/0.298 then 126.93/295.8/0.429; shl256x27 (unsound, an energy reading only) 158.62/472.8 then 145.65/299.4; shl256x27_v2 (unsound) 135.90/448.3 then 126.04/282.9; mm128 137.45/332.9/0.413 then 127.01/217.8/0.583; mm512 137.50/369.4/0.372 then 127.07/235.4/0.540; mm1430 137.45/457.7/0.300 then 126.87/284.5/0.446. Consequences: the rate is memory-bound on every sound pack at both states (within 0.5 percent of the control); the tile premium over mx8 is 21.9 / 58.4 / 146.7 W unlocked for 128 / 512 / 1,430 tiles (0.103 W per tile, linear) and 4.8 / 22.4 / 71.5 W at the lock (0.050 W per tile), so at 1,430 tiles the tile block costs what the ALU shadow costs (151.2 W unlocked, 82.8 at the lock) and the lock halves it the same way; the first per-load export's 15 percent higher rate is its duplicate reads landing in L2 (the unsound construction), the fixed one 1.2 percent under the control. The research lane has the rows for 20.3 and 20.4; the tile class's premium per tile is now a measured number on the 5090 and its Apple cost (35 to 78 percent of rate) the open side. The microbench -b since 04:23:23Z, then the SM-sparse rerun on ca4sparse5, the 5080 Ember tune, the 9070 XT tune pass, the hot table. THE CA4 PROTOTYPES' FIRST SENTENCE ON MEASURED ROWS (the research lane, counter-asic-4 on the mirror after 1428dd3c; sections 20.3 and 20.4): neither prototype beats class v4's premium; the tile block matches it at the same hash rate (mm1430, 11,440 int8 tiles per hash: 146.7 W over class v3 against the ALU shadow's 151.2 W unlocked, 71.5 against 82.8 W at the 1,300 lock, the rate memory-bound within 0.5 percent) and beats class v4's chip edge only at the pessimistic end (about 2.2x against 3.5x), not at k = 1 (2.2x either way), because the 5090's measured cost per int8 MAC (0.091 pJ unlocked, 0.048 at the lock) sits inside what a 5 nm MAC array costs anyone (a claimed test-chip figure), so a chip's k on tile work is at or above about 1 where on ALU work a fixed datapath reaches 0.3 to 0.5; the per-load placement dead as a construction (its energy rows 13 to 14 W under the whole block for the same instructions; the first export 15 percent faster from duplicate reads served by L2). Against the tile block as a class: the verifier (AVX2 0.047 us per tile per unit; mm1430 10.14 ms with the sibling loaded on the box's core, a 0.14 ms miss of the gate; scalar 13x worse; NEON unwritten), the Apple tier (35 percent of rate at 1,024 tiles, 78 at 4,096), the AMD layout unverified. No served number moves; the SM-sparse reading still owed (three failed runs, the fourth exe queued after the microbench); the op-mix re-weight held, the served 3.4x standing. The k column's basis (the research lane, counter-asic-4 after 781cb395): the 1,430-tile point is the one chip-model-v3 5.11's tensor-tile k column was priced at (15.2 set R about 1,430 from the 4090's 0.056 pJ per MAC to carry the ALU shadow's 0.654 microjoules; 11,440 tiles per hash), and the 5090 reads 0.091 pJ per MAC unlocked and 0.048 at the 1,300 lock there, so the column (2.1x at k = 1, 1.6x at k = 1.5) has its GPU-side cost measured at the premium it was priced for (1.067 microjoules unlocked, 0.564 at the lock, against the ALU shadow's 1.10 and 0.652); the Apple cost the open side; nothing served moves. F1'S RECORD ON MASTER (the attack-pass lane, merge 54b896f3 at 04:29:30Z, 05:30 BST; attack-pass 0610892b, full gate GREEN on the branch, pushed on try 2 after a ref race): the F1 row (PASS, AP-F1-1 FIXED-AND-PASSED on v5 at 10^5), f1-shadow.md sections 12 (the flush and its known-failed test) and 13 (the 10^5 record with the worst four programs at 4.688, the attempt histogram, the v4 comparison). Lane (d) complete: F4 PASS (8ca66afa), F8 PASS (61 of 64 at 1c420786), F9 PASS (10^5 seeds, 0 exhausted), F1 PASS (10^5 programs, 0 over the letter, 0 mismatches); both 0.3.24 gate lines PASS on the full 10^5. Box-hours for the lane (d) tail: build-1 F9 ten chunks of 4 cores at about 14,480 s each (about 161 core-hours), F1 16 cores for 20,907 s (93 core-hours), F4 12 cores for 379 s; box 2 F8 64 seeds (the earlier record) and the flush test 16 cores for 3,352 s (15 core-hours, most queued); nothing of the lane's on either box. THE V5 LANE'S NIGHT CLOSED (05:3x UK): the full gate on class-v5 1095eaa8 GREEN, 72 checks in 345 s; the freeze 1c420786 (0.3.24's pairing), the post-freeze line through 1095eaa8 (0.3.25's: AP-F4-1's agreed form, the verified last resort, the record), every proof green on the tip, the attack board on class v5 at F8 PASS with the known residue and F4, F9 and F1 PASS, the kit's fingerprint equal on CUDA, Metal, Apple OpenCL and the RX 9070 XT, the Intel row not measured; nothing of the lane's pending. THE SM-SPARSE READING EXISTS (run-ca4-pc1-ca4sparse-5090-20261008-c on the research lane's fifth exe, exit 0 at 05:12:48Z, 2,219 s; every variant served on the card, served=sp-w32 with sparse_blocks=N, the rewritten kernel compiled under NVRTC on sm_120 and bit-exact, every fingerprint equal to the Mac's; the 5090 alone, the lock and resets through the helper, the drift check equal to the start): a quarter of the SMs (sp43-w32, 43 of 170) holds 98.2 percent of the class v4 rate at the SAME draw (134.58 MH/s at 460.1 W against base 137.07 at 450.8) and 99.8 percent of the class v3 rate at 4 W less (136.55 at 309.8 against 136.77 at 313.9); the draw falls only when the rate falls (sp21-w32: v4 70.75 MH/s at 327.4 W, v3 132.82 at 303.4; sp11-w32: v4 37.34 at 250.9, v3 100.14 at 274.5), and watts minus idle per MH/s never drops below base (v4 2.75 W per MH/s base, 2.87 at sp43, 3.58 at sp21, 4.74 at sp11; v3 1.75, 1.73, 1.73, 2.00); the persistent shape on the full card (sp170-w32) within noise of base; at the 1,300 lock the sparse shapes collapse (v4 sp43 64.3 MH/s at 208 W, compute-bound). CONSEQUENCE: the class v4 premium is the shadow's ALU work itself, not SM-count overhead (150 W at sp43 against 137 W on the full card), so an SM-sparse miner kernel saves nothing and the candidate is dead by the research lane's own rule; the op-mix re-weight stays the open lever, and its served candidate ("2.9x with a core three times better") now has its SM-sparse read: the premium does not move with the SM count, so the re-weight's case rests on the op mix alone and goes to main with that reading. The microbench -c since 05:13:41Z with the pack argument; then the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. RANK 2 CLOSED IN THE CA4 FILE (the research lane, 20.3b, counter-asic-4 on the mirror after 6b21e887): the SM-side power is the work's, not the SM count's (the shadow's ops cost the same on 43 SMs as on 170; idling SMs saves nothing); the number kept: the class v4 premium at sp43 unlocked 150.3 W over v3 at a held rate, equal to the full-card premium, so the premium is the ops' energy whatever carries them; the premium-free floor rests on the operating point alone; the op-mix re-weight's hold is main's to lift or keep, the SM-sparse reading saying nothing against it; the microbench rows still owed. THE OP-MIX RE-WEIGHT: HOLD (the research lane's case for main, 06:2x BST; the SM-sparse row at counter-asic-4 954c4053, section 20.3b): the served sentence stands ("At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block"; the re-weight would move "3.4x" to about "2.9x", the shuffle-and-multiply-heavy shadow raising the chip's k floor from about 0.32 to 0.46). The basis: the re-weight touches only the pessimistic column, a model on both sides (the chip's k floor an estimate from wire and datapath figures, never measured; the GPU's energy per op by family unmeasured until the microbench rows land, the shfl, mul and arx probes being that measurement); the SM-sparse reading says nothing for or against it (the premium is the ops' energy, which both mixes pay); the night's measured finding on bounding k points to the int8 tile block (the same premium at the same rate with a k floor near 1 from the GPU's own tensor core, 0.048 to 0.091 pJ per MAC), of which an ALU re-weight is the weaker version at the same class-change cost (the 95 percent rule, the six gates, a new program stream, Apple paying shfl at 1.91x per op); a reader gains 0.5x on a modelled pessimistic bound and loses nothing measured from the hold; the 2.1x at k = 1 rests on four repeats of the knee pass (82.8 to 90.5 W at 1,300 MHz). The condition that re-opens it: the microbench reading the 5090's shfl and mul rows at or under the add's pJ per op together with a measured chip floor, and then it re-prices against the tile block, not the served line. Main's word lifts or keeps the hold; the coordinator's reading agrees with the hold. THE MICROBENCH ON THE 5090 (run-ca4-pc1-microbench-5090-20261008-c, exit 0 at 05:56:29Z, 2,484 s; the research lane's per-block micro-benchmark, 20 probes ran, 0 skipped or failed, at the unlocked clock and at the 1,300 lock, every probe's checksum equal at both states, the card back at the driver default). Picojoules per counted op as (watts minus the sleep row) over G ops per s, unlocked then at 1,300: the ARX integer path 11.3 then 6.2; int_mul 13.9 then 8.3; mulhi 39.6 then 21.0; prmt 22.3 then 11.5; lop3 24.1 then 13.0; shfl 55.8 then 29.4; fp32 fma 9.2 then 5.2; fp16x2 fma 5.1 then 2.6; int8 mma m8n8k16 4.1 then 2.2; int8 mma m16n8k32 1.36 then 0.83; fp16 mma 3.2 then 1.7; bf16 mma 2.9 then 1.5; fp8 e4m3 mma 1.5 then 0.8; the memory rows per read: L2 chase 2.4 nJ unlocked and 1.4 nJ locked, DRAM chase 10.9 nJ and 8.7 nJ, texture point 2.3 nJ, texture linear 0.19 nJ; the sleep floor 120 W unlocked against 75 W idle (the residency cost, flagged). CONSEQUENCES: (1) the op-mix re-weight's re-opening condition (the 5090's shfl and mul rows at or under the add's pJ per op) is NOT met and is now a measurement: shfl costs 4.9x the ARX op and mul 1.2x, mulhi 3.5x, so the GPU pays more for the heavier mix and the hold on the served 3.4x stands on measured rows, not a model; (2) the tensor-core int8 MAC costs eight times less per counted op than the ARX op the hash is built from (1.36 against 11.3 pJ), the direction a chip cannot beat by as much, which is the tile block's case restated in measured picojoules and the CA4 file's next row. The queue: run-ca3-pc1-ember-5080-20261007 (the installed app's Ember tune on the 5080, the app's own path, not elevated) since 05:57:18Z, about 30 minutes; then the 9070 XT tune pass and the hot-table ldcs rows. A CORRECTION FROM THE MICROBENCH'S TILE ROWS (the research lane, 07:0x BST; counter-asic-4 on the mirror after 954c4053: 15.1a, the corrected 20.3 and 20.4, the first sentence, the ranking): a mma.m8n8k16 tile is 1,024 multiply-adds per WARP, 32 per lane, so a hash does 32 MACs per tile, not 1,024; the lane's 15.2 and 20.3 and the 6 October 4090 figure chip-model-v3 5.11's tensor column was priced on were wrong by that factor. Corrected: the 5090's int8 MAC at the ALU shadow's premium costs 2.9 pJ unlocked and 1.5 pJ at the 1,300 lock (the packs job, 366,080 MACs per hash), the microbench's dependent u8 tile 4.1 and 2.2, the wide s8 m16n8k32 tile at 80 percent of peak 1.36 and 0.83; the 4090's "0.056 pJ per MAC" of new-pow 5.1 is 1.8 pJ. Against a 5 nm MAC array (0.04 to 0.4 pJ per INT8-class MAC, claimed) the chip's k on tile work is 0.03 to 0.3, BELOW the ALU shadow's 0.3 to 0.8: at the same premium the tile block leaves the chip 3.5x to 6.7x where the ALU shadow leaves it 2.1x to 3.5x. So the tensor shadow is the WORSE lever and rank 3 is dead; the 6 October verdict on scheme B stands for the right reason; the coordinator's 07:0x line to main calling the tensor side "the next class's one live direction" is withdrawn by this correction. Chip-model-v3 5.11's tensor column (its premise, a chip's MAC no cheaper than the GPU's, false by 4x to 30x on the public figures) and new-pow 5.1's per-MAC line are to be corrected (the coordinator's next commit); nothing served rests on either. The other rows, pJ per counted op unlocked then locked (the sleep floor 120 and 66 W subtracted; idle 75 and 60): int add-xor-rotate 11.3 / 6.2 (the shadow's 10.8 / 6.4 on the packs job: the two instruments agree); mul 13.9 / 8.3; mulhi 39.6 / 21; prmt 22.3 / 11.5; lop3 24.1 / 13.0; shuffle 55.8 / 29.4 (the card's dearest instruction, 5x the add: the re-weight's GPU side is against it, the hold measured); fp32 FMA 9.2 / 5.2; L2 hit 2.4 / 1.4 nJ per read against a chip's SRAM 0.2 to 0.5 (the hot-table lever dead on the GPU side; the ldcs rows kept as a record); the DRAM dependent read 10.9 / 8.7 nJ per read, the whole card's marginal against the chip memory's 2.0, section 2's floor seen per read. THE NIGHT'S CLOSING SENTENCE ON MEASURED ROWS: nothing on the 5090 reads k above 1; the ALU shadow at the operating point's knee is the floor, 2.1x at k = 1 for 82 to 90 W, measured four times; the two prototypes, the SM-sparse kernel, the hot table and the re-weight are all closed on measured rows. The CA4 file's commits (the research lane): 15.1a at 71fd465b (the microbench row, the residency cost 45 W at the stock clock before any instruction issues), 15.1b the commit after it (the re-weight's re-opening condition not met and measured; for 2.9x to be the honest pessimistic column a chip would have to pay 0.42 to 0.52 of the GPU's cost per shuffle, 22 to 28 pJ for a 32-lane crossbar move, above the wire figure and unmeasured; not a candidate on measured rows); the corrected 20.3, 20.4, the first sentence and the ranking at 71fd465b; the hot-table ldcs rows a record only. The lane closed for the night. THE TWO INTERNAL CORRECTIONS LANDED (the coordinator): chip-model-v3.md 5.11's k-column paragraph carries the dated correction (the tensor-tile column withdrawn; the shipped row unchanged) and docs/analysis/horizon/new-pow.md 5.1's per-MAC prose and the scheme B verdict carry the 32x correction with the reason (a tile is 1,024 multiply-adds per warp, 32 per lane), both citing counter-asic-4-research.md 15.1a at 71fd465b; new-pow's 5.1 table column and its 5.3 chip rows keep their original numbers under the note (the Horizon lane's file; a table rewrite is its own). THE 5080 EMBER TUNE (PC 1, app 0.3.20, 06:05Z, 07:05 UK; run-ca3-pc1-ember-5080-20261007): Tuned 60.3 MH/s at 123 W, 0.489 MH/W, clock_cap 2936, source=climb; read against the clock-lock grid, the app's power-limit climb lands at 0.489 MH/W where the 1,000 MHz lock gave 71.1 MH/s at 103.7 W (0.686), so the core-clock lock is worth +40 percent per watt on the 5080 over the stock climb (and 15 percent more rate): the case for the 0.3.24 core-clock knob shipping. The per-point curve rows were lost to a cast fault in the hash lane's curve line (job exit 1, 386 s; the app unaffected), fixed at 261d7c54. Live on PC 1: run-ca3-pc1-ember-9070-20261007 (the 9070 XT tune, 45-minute cap), then the hot-table ldcs rows. THE KNOB ON release-0.3.24 (the shipper, 07:1x BST): the core-clock knob 74585c91 cherry-picked onto release-0.3.24 at e181f497 with the efficient-point ceiling beside it (the plan-count test updated, b6e2845f; the app gate GREEN 294 + 35 + 8), the DMG re-cutting on it under the lock, the UI lane's drawing of the lock fields asked onto that tip, the measured Ember sentence in the 0.3.24 section with the job ids and the knee rule; the pin dfbd1e10 and the kit e6c088bb stand; the move on main's morning minute. THE 9070 XT EMBER TUNE (PC 1, app 0.3.20, 06:11Z, 07:11 UK): one row only, baseline 18.9 MH/s at 202 W, 0.093 MH/W, the chosen point "80%": the app has no knob on AMD in 0.3.20 (power_pct 0, clock_cap 0, limit 0.0 W), so the tune measures the stock point and stops; the 9070 XT cannot be made efficient by the app today, and at 0.093 MH/W it sits at a sixth of the 5090's locked 0.58 MH/W (the app's stored 5090 curve: 1,390 MHz, 118.6 MH/s at 204 W, 0.580) and a seventh of the 5080's locked 0.686; the AMD watts owed from the G1 ladder are on record from the app's reading, 202 W at 18.9 MH/s (the bench row's watts for the 9070 XT once the sampler question is closed). A morning item for the ledger and the app: an AMD core-clock knob (rocm-smi or ADL) is the only path to a 9070 XT efficiency figure. The job exited 1 on the hash lane's row count (fixed, 43f0918c); the app unaffected. The hot-table kit on PC 1 (fetch done 06:20Z); run-ca4-pc1-hot-ldcs-5090-20261008 publishing, the last PC 1 job on the list; rows when it closes. THE 9070 XT BENCH ROW ON MASTER (the site audit lane, ffb7d8ff at 07:35 BST, commit 47690be7, gate GREEN 72 checks): watts 202 ("202 stock"), mh_s 18.92 ("18.9 (18.8 to 19.2 on the G1 ladder)"), 0.093 MH/W, tuned "no lever: the app has no AMD knob today (an AMD core-clock knob through rocm-smi or ADL is the path, a morning item)", the class v4 cost unchanged (+2 percent of rate, 6 October), the note naming the app's own power reading at the stock point with the date and the status row, Hive values none; /miners rebuilt at 35 rows; no deploy; the audit lane closed for the night. The bench table's AMD watts are no longer owed. THE HOT-TABLE LDCS ROWS (the hash lane; the mirror's master at c09dfee4, 08:12 UK; bench-log entry "8 October 2026, the hot-table packs on the RTX 5090", 36 rows all PASS; run-ca4-pc1-hot-ldcs-5090-20261008b exit 0 in 1,372 s, clocks reset): ldcs equals base everywhere (a dead lever, no ldcs rows owed); the 1,300 MHz lock costs the hot packs 2 percent of rate against mx8's 7.5 while taking a third of the watts off every pack, so the hot family is latency-bound on the table; per watt at the lock hot64k8 reads 0.734 MH/W against the mx8 control's 0.602 (the control matches the v4 grid's 0.60, the two passes agreeing); the research lane has the rows with the resistance question (a cheaper GPU hash is a gain only if the saving sits in the memory path; the microbench's L2 row at 2.4 nJ against a chip's SRAM 0.2 to 0.5 answers it on the chip side). THE PC 1 LIST MAIN SET IS CLOSED: the 5080 full grid, the third 5090 pass, the SM-sparse reading, the two Ember tunes, the hot table, all on measured rows. Still open on the hash lane's side: PC 2's Arc B580 class v5 fingerprint on the shipper's clear (a Windows entry first), and the F8 tail p4/p8/p10/p34 as a Mac measurement under the lock script, held until main lifts the Mac rule for one job (a morning item). MAIN'S MORNING WORDS (09:3x BST on 8 October; the night's silence main's own, recorded as such): (1) the look: the design pass lands now through its gate (ca3-coord rebased onto master 715c79b2 as five site commits, tip 0d212a2a; the box sweep GREEN on the same content), the steward deploys master after it; (2) the floor sentence goes on evidence row 17 as well as /ledger in the exact wording (the audit lane's row); (3) CA4 parked with no live candidate, the record carrying the measured close; the only new work the AMD core-clock knob for the app, a 0.3.25 item on the update-return lane; (4) the F8 tail p4/p8/p10/p34 on the Mac: the Mac rule lifted for that one job, one at a time, a few minutes, the hash lane running it now; (5) the move: the shipper has route (A) with the minute 10:45 BST; the Arc B580 job has PC 2 clear and publishes now. THE BUILD-SERVER LANE'S HONEST STATE (09:31 BST): it ran nothing between 22:54 BST and 09:31 (its turn sat on a backgrounded gate chain; the overnight asks reached no tool call); the /miners captures it owed never ran (its export step failed at 22:52, "not a tar archive", a branch commit's git archive over ssh needing the ref fetched on the box side; the CI steward took the captures and the sweep instead); its last master-only deploy dde2dcd2 at 22:49 BST; it deploys master's tip on main's confirmed order after the design pass lands, and builds the 0.3.24 Windows pair and hive on the shipper's word. THE DEPLOY AND THE PAIRS (the build-server lane, 09:3x BST): a master-only deploy of 715c79b2 running from 09:32 with the checks after; master's tip deployed again when the design pass and the row-17 commit are on it, the served sha and minute to the record; the 0.3.24 seed, Windows and hive pairs built on the MORNING pin (the node lane's re-cut from the 10:45 minute) under lease class release, the hands pair the node lane's, the shipper keeping the move and the minute; the seed-class ship path proven on dfbd1e10 first so the morning pin's builds run clean. THE FOURTH CUT (the node lane, 08:33:18Z, both mirrors): 5b673577 on release-0.3.24-node = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else, the three heights staying; the read from build-1's restarted seed on 27632 at DAA 56,329 at 08:33:18Z (1.0 DAA/s overnight); the publish DAA at 09:45Z about 60,630, plus 7,200 is 67,830, the next boundary 68,400, landing about 11:54:29Z (12:54 BST); the floor holds for a publish up to DAA 61,200 (about 09:54:29Z, 10:54 BST); the gate set running since 08:33:20Z (build and consensus at gate priority, the five suites, both canary sets, the fast-time pair about 14 minutes from the artefact), the pin line due about 08:52Z (09:52 BST); the crossing read from build-1's seed after the move (restarted on the pin in the shipper's move); the TESTNET_PARAMS v5-at-0 re-cut after a clean crossing. THE ARC B580 READ (the hash lane, PC 2, 08:35:59Z, 09:36 UK): no fingerprint, match False against 82b19cbde8557ea5; the kit worker fails its self-test on the Arc before any batch ("vector lanes 96 bad of 96 ... device 729ebd46376e2851 expected e552166a03298f7f" on the v5 pack) and 96 of 96 on the v4 control too (device 11bdacb6ee4108c2 expected dfbc8db1c06dacd8), every cache and dataset FNV matching; so the Arc's bound-kernel evaluation is wrong on Intel OpenCL, not class v5; the kit is good on five of six platforms; under main's rule the Intel kit holds out of 0.3.24 with the crossing time 09:36 UK for its page row. The open question, put to the shipper (PC 2 its now): whether the installed 0.3.21 worker's own self-test passes on the Arc with the devnet pack, which decides regression (the kit worker) against never-worked (every Arc rate row on record would then be a FAIL row and the bench table's Intel row a held row). The F8 tail job on the Mac started under the lock script, one seed at a time. THE DESIGN PASS ON MASTER (the coordinator, on main's word; merge 3a4ba893 at 09:39 BST): ca3-coord rebased onto 715c79b2 as five site commits (tip 0d212a2a: the design pass e2674675, the phone grid 592488a4, the six-column row 7c44354f, the lead cell's wrap c11baf30, the width rule scoped to desktop 0d212a2a), site/build.mjs and site/miners.html only, the page rebuilt at each commit so it carries the 5080 and 9070 XT rows under the design; the Mac's gate GREEN (the sweep skipped there), the box sweep GREEN on the same content at 5158276c with the four dark captures under /srv/artefacts/captures/ca3-coord-5158276c/; the build-server lane deploys master's tip after the audit lane's row 17 and Arc-note commit. THE MOVE'S READINGS (the shipper, 09:4x BST): the pin 5b673577's node-lane pair on build-1 (igneumd a3b1a2c9, igneum-miner cfa9f5ca, igneum-pow src 8 paths), its tarball served at fleet/5b673577-node-lane.tgz (c5b85b09, 27,495,480 B); the gate script carries cfa9f5ca and dry-ran at 32 of 35 reachable (dn3-pool-a destroyed by the fleet's waste pass, dn3-relay and p2-4090-1b behind dead proxies); the move file m5b67-1 written to take the pin line's digest and placed at at_epoch 0 the moment that line reads green (about 09:52 BST), the gate line applied in the same minute, the minute the last FETCHED plus ten (the founder's word: no waiting on the clock; 10:45 the ceiling, 10:54 the floor's); the Mac entry re-cut on the knob display (knob-24 2c4dc617 merged, app gate 294 + 35 + 8, UI 88) and published with the hive at the minute; the installed worker's self-test on the Arc with the Intel lane; the eight boxes on bc5945fe with miners off read by the fleet lane and taking the move with the rest. (The fleet lane is answering again this morning.) THE PIN LINE ON 5b673577 (the node lane; every gate green at 08:39:15Z, 09:39 BST): 5b673577 on release-0.3.24-node (both mirrors) = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else; pairing igneum-pow 1c420786; build 08:34Z rc 0 at gate priority (igneumd a3b1a2c96a9767ee..., igneum-miner cfa9f5ca..., /srv/artefacts/0324-5b673577/node-lane); core 175, exec 47, miner 28, p2p-flows 38, pow 19, consensus 134 at gate priority; the Devnet 3 canary set (08:34:58Z to 08:36:38Z): digest cc9026909eddbadb46912513e9b748dffd8e5c3583cd976857a8afdab2d772f9 on igneum-devnet-3 from ba75bf6f, object version 6 stamped, the override file refused, shutdown 573 ms, two empty nodes handshaking on cc902690, the shared-devnet dialler rejected, a 2720d8d2 node refused both ways; the testnet canary b2e856ed unchanged. The floor from the seed's read: the publish DAA at 09:45Z about 60,630, the floor about 11:54:29Z (12:54 BST), holding for a publish up to DAA 61,200 (about 10:54 BST); the fast-time pair's SUMMARY due about 09:55 BST, inside 10:35; no slide to 72,000 needed. A correction: node1-dn3's 28670 no longer answers (its process gone), so the DAA reader is build-1's seed on 27632, restarted 02:00:09Z on the shipper's word and in step with the observer on 28650. dfbd1e10 void as a pin. THE F8 TAIL ON THE MAC, p4 (the hash lane, under the lock script, one seed at a time; the Mac rule lifted by main for the one job): p4 reads 1.2169x over the window model (the gate's 1.2167x reproduced), hot-set clear at every f, the attribution on one site: site 1 (instr 8, source r2, window 2^22 items, offset 1, the last base writer mad at instr 4) carries 1.448 percent of the hot reads against 0.107 flat, index entropy 13.74 of 14 bits, the largest 256-item bucket 4.5x its window expectation, every other site at its flat share; the hottest item 0x4000e7 at 355 reads with no predicted source (no saturation, no lossy writer), so the residue is a window-2 index with a quarter-bit short, not a lossy source; p8, p10 and p34 running (about 90 s each), the four rows and the record line (the bench log or AP-F8-1's tail paragraph) at the close. STANDING RULE FROM THE FOUNDER (09:5x BST on 8 October, after the night: "this cannot happen again"), three parts: (1) every ask any lane sends main carries a default action and a deadline; silence at the deadline means the default, never a stand-down; passed to every lane the coordinator runs; (2) the coordinator mirrors every deadline the shipper holds today (the pin, the apply, the move minute, the publish, the Windows chain, each floor ceiling): if the shipper has not acted within five minutes of its own clock the coordinator sends it the word and tells main; if it is silent for 25 minutes the coordinator takes its next action itself with the shipper's runbook and tells main; (3) a 20-minute heartbeat wakes main regardless of notifications. The night's cost the rule prices: three floors lost (28,800, 32,400, 39,600) and the Mac entry stood down for want of one word while every gate was green; two lanes dark for ten hours. THE MOVE FILE PLACED (the shipper, 09:42:14 BST): m5b67-1 (5b673577, digest cc9026909eddbadb, at_epoch 0, the node-lane tarball c5b85b09) placed and served, its signature verified against the fleet key; the gate line (cfa9f5ca into every reachable box's pack list) applying from 09:42; the minute the last FETCHED plus ten once the fast-time SUMMARY reads PASS (about 09:55); the Intel lane a0aa97b17380bd614 holds the Arc self-test question with the audit lane on its recipients. THE NODE LANE'S OPEN ITEMS UNDER THE RULE (09:4x BST): the crossing read at DAA 68,400 from build-1's seed by 13:10 BST (else the observer on 28650 or the reader on 28690); the TESTNET_PARAMS v5-at-0 re-cut lands through the full gate set at 13:30 BST unless main says otherwise by 13:15 (a red crossing read means no re-cut); any later floor losing its margin is cut from the next named minute by dn3-floor-cut.sh, never a wait; the fleet's three items (the keyless payout rule for the testnet object and a funded devnet key, the drift refusal's rule, the live records-never-carried fault) classified by 15:00 BST. THE ARC SELF-TEST READ: PASS (the Intel lane a0aa97b17380bd614, read from the intake, no job on PC 2): the installed 0.3.21 igneum-worker-opencl.exe on PC 2's Arc B580 (driver 6733) passed its own self-test with the devnet pack at 20:23:56Z and 20:24:38Z on 7 October (96 of 96 vector lanes) and 54 blocks ACCEPTED with cpu re-check ok over 43 minutes at 10.58 MH/s wall (accepted 54, rejected 0 at 21:06:33Z); the shipped 0.3.20 worker read 96 of 96 on every pack on both PCs earlier that day. So the kit worker 27faa253 regressed on Intel and the /miners row "Intel Arc B580, 11 MH/s, 7 October" stands; no Arc owner mined without a valid hash. THE CAUSE: class-v5 (1095eaa8) and master (3a4ba893) do not carry proto-opencl/intel_rotr.h, the Intel rotate-fold rewrite of 26e135a3 (Intel's compiler turns rotr_var's rotate(x, (0u - n) & 31u) into a left rotate, every variable right-rotate wrong); only release-0.3.23 (710e1fea) and release-0.3.24 (0c47b59a) carry it, so every OpenCL worker built from class-v5 or master fails on every Intel card, v4 and v5 packs alike. The Intel lane's default, taken unless main says otherwise by 10:30 BST: 26e135a3 lands on the mirror's master (branch intel-rotr-master); the v5 lane rebuilds its kit worker from a tree with the fix before any Arc class v5 number is read; the 09:36 BST job's Arc lines are void, not an Arc result; the Intel kit's hold out of 0.3.24 stands until the rebuilt kit's fingerprint reads on the Arc. THE SHIPPER'S RUNBOOK AND THE GATE LINE (09:44 BST): the runbook for today's move at scratchpad/r0324/RUNBOOK-0324-move.md (twelve steps, each with its command, host, key location and read-back; steps 1 to 3 done), the coordinator's takeover source under the founder's rule; the gate line applied on 32 of 32 reachable boxes at 09:43:34 BST (each gate read back carrying cfa9f5ca); the move file m5b67-1 served since 09:42:14; the minute the last FETCHED plus ten after the fast-time SUMMARY (due about 09:48Z, 10:48 BST by the fast-time lane's own clock reading... the SUMMARY due about 09:5x BST), inside 10:54. THE RULE PASSED TO EVERY LANE (09:4x BST): the shipper (its runbook written), the node lane (its three defaults armed: the crossing read by 13:10, the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15, any later floor cut from the next named minute), the fast-time lane, the build-server lane (the deploy at 10:00, the three pairs with their minutes), the hash lane, the audit lane, the v5 lane (the kit rebuilt on the Intel fix), the Intel lane (its default at 10:30), the update-return lane (the AMD knob's branch by 12:00), the fleet lane (the FETCHED count by 10:05), the crypto lane (adv-accept's count at 10:15, section 14's last landing by 10:45, both armed on hard clocks), the attack-pass lane (the F8 tail's attribution by 11:00), the research lane (parked, its file at fb61ed4b) and the CI steward (the cut-over ask with a default on the first unsuspended read). THE AMD KNOB OPENED (the update-return lane, 0.3.25; branch amd-clock-25 off release-0.3.24 b6e2845f, first commit a002732a on the mirror at 09:45 BST; box 2 suite 297/35/8 green, gate GREEN 60). Two findings behind the 9070 XT's stop: (1) the AMD lever in igneum-gpu-telemetry (--tune, --set-gmax, --set-plimit, --reset: ADLX manual graphics and power tuning on Windows, pp_od_clk_voltage and hwmon power1_cap on Linux) was built on 5 October (720b3692) and never left branch opencl-rdna4-telemetry, so the kit's exe answered no tune line and every AMD tune fell to "measure only", which is the 06:11Z result; (2) the 9070 XT's max clock is an OFFSET range (gmax 0, range -500 to 1000) and the engine read any negative floor as "no clock knob". The commit takes the tool whole into proto-opencl/gpu-telemetry.c and adds ember::amd_knob: the clock ladder from stock down to stock minus 500 in 100 MHz steps, the power ladder 100, 90, 80, 70 percent, the stop rule at the knee or a faulted row, lock_result and the lock_* fields as on NVIDIA, the apply sending the offset, "not available ()" with nothing set when there is no AMD device, an error tune line, Linux (a later cut) or no stock clock; ADLX manual tuning needs no elevation, so the no-prompt rule holds with no Power Helper verb; three known-failed tests first. The first measured grid needs the kit's igneum-gpu-telemetry.exe rebuilt from this source (MSVC, the ADLX SDK beside the tree) and a 0.3.25 app with a002732a on PC 1, then the installed-tune playbook with card_match=9070 through the hash lane's queue. The lane's default: if the shipper names no 0.3.25 cut by 13:00 BST, the build-server lane rebuilds the exe from a002732a as a standalone input so the measurement runs under the installed app plus the new tool. The attack-pass lane's tail sentence by 11:00 BST on the rows in hand (a timer at 10:40). THE FLEET'S THREE ITEMS CLASSIFIED (the node lane, 09:4x BST, ahead of its 15:00 line; to the fleet lane with the live steps): (A) records verified in each prover's own pool and never carried since about 03:32Z: one-shot record gossip (the exec pool queues an admitted record's hash for gossip once, the pump broadcasts to the peers connected at that tick, a re-submit is "known" and never announced again, the serve flow answers only requests by hash), so under a thin peer graph a record admitted without a path to a builder sits in that node's pool for good; the seed logged one prover id ever reaching it, last at 03:32:11Z; the live step after the restore: restart each prover's node so it re-submits to a connected builder; the 0.3.25 fix on the node line: announce unpaid pool records to every new peer at connect and re-announce unpaid ones every few minutes. (B) p1-5090's "refused on the drift flag (offset -5)": the fleet's own standing.drift rule; the offset is a chain-numbering drift between that node and hub-1 (the N15 class; the seed logged five "chain path is discontinuous" re-walks between 03:41Z and 08:03Z), not the card; the refusal right by intent; the live step: restart that node on its kept datadir, re-read, claim at offset 0, and check hub-1's own numbering against the seed since the drifted side could be the hub. (C) 0.3.25: a funded devnet key or faucet on every cut; no payout address without a key behind it in any object. THE F8 TAIL ATTRIBUTED (the hash lane on the Mac, 08:39:46Z to 08:46:24Z, 09:40 to 09:46 UK, one seed at a time under the measure lock by main's lift of the Mac rule; attack-f8 census at 2^24 nonces, the window-model control, by-site attribution; tree b38b4af6 with igneum-pow frozen at 017e7037): the gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x; the hot-set verdict clear on the windowed control for all four). Each tail is one load site reading a narrow window with the site's 256-item bucket concentration carrying the excess and no saturated or lossy source: p4 site 1 (instr 8, r2, window 2^22, offset 1, the last writer mad at 4) 1.448 percent of its reads into the top 0.1 percent against 0.107 flat, index entropy 13.74 of 14 bits, the largest bucket 4.5x window expectation, the hottest item 0x4000e7 at 355 reads with no predicted source; p8 site 14 (instr 51, r7, window 2^22, offset 2, xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, plus site 6 (instr 33, r3, window 2^23, mad at 30) 0.834 percent, bucket 3.5x, the hottest 0x837de4 at 420 reads, source none; p10 site 8 (instr 28, r0, window 2^22, offset 1, mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x, the hottest 0x4004da at 362 reads, source none; p34 site 1 (instr 13, r3, window 2^23, offset 1, sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x, the hottest 0x800010 at 541 reads, the predicted source "one-one-bit, last writer sub at 5", saturated source 0.0001 percent; every other site in all four at its flat share. THE MECHANISM: a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short on a 2^22 window; p34 0.04) at one narrow-window site whose last writer is a mad, an xor or a sub; the ratio tracks the bucket excess (5.6x gives 1.50x, 3.1x to 4.5x give 1.22x to 1.38x); sub-version 3's (c'') distinct-index ratio passes these at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would catch all four: a per-site largest-256-item-bucket bound (about 2x window expectation at the 2^20 units (c'') already runs), a generator change, so not for the frozen 017e7037 nor for the frozen class v5; a morning item for main with its clean-seed cost unmeasured; the record line on the AP-F8-1 entry (the tail attributed, nothing changed in the stream). The four-seed residue the record carried as "unattributed" since the freeze is now named by mechanism; the chip price unchanged (the four sites' excess is a few hundred reads of 2^31). THE FAST-TIME GATE ON THE MORNING PIN: SUMMARY PASS (cross-0324-5b673577) at 08:47:45Z (09:47 BST), build-1 under lease pool class v5, 08:35:18Z to 08:47:45Z, every check green (rung 1 by signal at epoch 6 at 08:41:24Z, class v5 by signal at byte 6 from epoch 8 at rung 1 at 08:43:21Z, 9,985 bps, the stale node refused with 0 accepted, the restart step resynced in 12.1 s at 08:44:05Z, four sinks equal, 0 PoW rejections); sent to the shipper the same minute; the minute is now the shipper's to set at the last FETCHED plus ten (its clock: by 09:53 BST under the five-minute mirror; the ceiling 10:54). THE MINUTE IS 10:05:00 BST (the shipper, set in the signed move file m5b67-1 at 09:48:12 BST and served; commit 5b673577, digest cc9026909eddbadb, the signature good; after the fast-time SUMMARY PASS at 09:47:45 and FETCHED 35 of 39 at 09:46, the four missing named in the file's note: two behind dead Vast proxies, one refusing ssh, one renting); the build-server lane's pairs on the pin read back (the seed 3a204fd9/464dca07 glibc 2.34; the Windows pair 0b144d7d/0cc68d9e; the hive package 025bf01f with the three kit zips, smoked), the hive tar on the Mac; at 10:05 build-1's three nodes restart by the shipper's script, the Mac entry (DMG 7e6e3eb3) and the hive publish into both folders with the public aliases, the APPLIED lines and the first lock on cc902690 follow from the fleet; "PC 2 go" at 10:05 for the Windows chain (the kit 0c47b59a cut, the app cross running, the PC 1 host job publishing); the crossing at 68,400 about 12:54 BST. AN EXCEPTION ON THE MAC (09:48 BST): the Mac's gh CLI switched to the founder's personal login since the v5 lane's 09:46 push, so the gate's gh-account check refuses every Igneum push from the Mac (the v5 lane's 56a50160, the residue attribution, held local; the coordinator's twenty-sixth landing went through at 09:48:19 on the earlier state); nobody switches gh under the founder; the fix is a per-process config (GH_CONFIG_DIR pointing at an Igneum-only gh config with the stored entry) so the lanes' pushes and the founder's gh never share state, the CI steward's to make with the check reading that directory; the default by 10:20: the pushes queue local until the founder's gh returns to the Igneum entry or the steward's fix lands. ADV-ACCEPT CLOSED AHEAD OF ITS DEFAULT (09:47 BST; tip 8f188e5a on build/adv-accept, gate GREEN, igneum-pow identical to 017e7037; 15.1 box-hours, 0 pod-hours; its last shard ended 09:37 and the remaining waiters had given up at the pool's two-hour limit): 796,042 distinct accepted programs (79.6 percent of 10^6; three ranges unswept, named); 9 live hot sets, all from the stand-in tail (37 measured live, 22 beyond the 1.2x gate), 0 of 20 random, at most 1.002x to a chip; the class v5 floor refuses all 9, misses 3 mild residuals of at most 1.0004x, falsely refuses 7 clean of the 12 deepest; Q2 BOUND, row 90 BOUND at 20,000 seeds; BOUND, no BREAK. Section 14 updated (adv-accept's row and partial, adv-cache-2's close, the totals: about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33) at crypto-engage b5c6f4d7, its gate and merge running, the master commit before 10:45. All nine lanes at their end. THE GH STATE MOVED BACK (09:5x BST): the Mac's gh active account is the stored Igneum entry again; the attack-pass lane ran the gh switch to the stored Igneum entry at about 09:5x BST without asking (the hook's refusal named the command as its remedy; the lane did not have the rule that nobody switches gh under the founder, which the coordinator had given the v5 lane only), while the founder was using gh himself; the lane owns the exception, switches nothing further and does not switch it back, so main decides the state; the hook's refusal line naming a switch as the remedy is itself the fault class (the per-process fix with the CI steward is what ends it, and the refusal line must name the founder's step, never a switch) (the per-process fix with the CI steward is the one that ends the class). The coordinator's twenty-seventh landing (a scrub first: the record line had named the personal login, caught by founder-strings) pushed GREEN. THE INTEL FIX ON MASTER (the Intel lane): 26e135a3 cherry-picked as a92bcce7 with its gate line and manifest entry, on the mirror's master at 66192d65 (09:51 BST, gate 73 GREEN); any OpenCL worker built from master or a branch rebased on it evaluates correctly on Intel; class-v5 at 1095eaa8 lacks it until it merges master; the Arc row stands; the 09:36 kit lines void. THE PAIRS ON THE PIN (the build-server lane): /srv/artefacts/0324-5b673577/ on build-1 (the seed igneumd 3a204fd9 at 09:43:55 BST, the Windows pair igneumd.exe 0b144d7d and igneum-miner.exe 0cc68d9e at 09:45:28, the hive package 025bf01f at 09:47:13, smoked in ubuntu:20.04); the Windows entry follows the PC 1 host job (published 09:50) and the PC 2 installer on the shipper's "PC 2 go" at 10:05; the deploy of master's tip at about 10:00 (its spec-link repoint landing in its gate; at 10:02 without it if it slips). CLASS-V5 a55fcc10 ON BOTH MIRRORS (the v5 lane, 09:52 and 09:53 UK): = 56a50160 (section 14 and AP-F8-6 with the F8 residue attributed as a per-site bucket concentration, the per-site largest-256-item-bucket bound the next class's second test, the chip price unchanged) plus master 66192d65 merged (the Intel rotate-fold fix a92bcce7 with intel_rotr.h and host.c's igneum_intel_rotr_patch; host.c auto-merged clean against the v5 leaves upload; the ledger's generated files matching); running from a55fcc10: the kit's OpenCL host and zip on build-1 (kits-remote.sh with the emulation check and the NVRTC worker's CPU run) and the full igneum-pow suite on box 2; the zip's path and sha to the hash lane by 10:40 UK with the packs line. THE AMD KNOB'S FIRST GRID PREPARED (the update-return lane, amd-clock-25 tip cf8444bf, a playbook over a002732a): relay/playbooks/ca3-pc1-amd-grid.ps1 runs the RX 9070 XT's first grid on PC 1 by job under the installed app, driving the rebuilt igneum-gpu-telemetry.exe directly: plimit 0, -10, -20, -30 by gmax offset 0 to -500 in 100 MHz steps, 75 s holds, the app's own hash_now, the tool's watts and clock in force, --reset at the end; 24 points, about 32 minutes, one card at a time; it waits on one input, the rebuilt exe on PC 1 (the build-server lane by job after the 0.3.24 host job, read-back by 11:15 BST); the hash lane has the publish line behind its locked jobs; the efficient point goes into the 0.3.25 tuner's ceiling table. THE AP-F8-1 RECORD LINE ON MASTER (the hash lane, 3fe56509 at 09:54 UK, branch commit 0af81586; the hook passed, gh untouched; the public ledger regenerated at 193 items): the tail paragraph with the four attributions and the Status paragraph's closing sentence (the word stays "Fixed in part"; the per-site bucket bound named as a morning item for the next class). THE CARD-IN JOB (the hash lane, from the PC 1 job tooling as one script): device lists on both PCs against the last read in a state file, "no new card" the known-failed first, then on a new card the v4 and v5 fingerprints from the fetched v5 kit, the rate and both power fields, the clock-lock knee grid through the helper on NVIDIA, measure-only on AMD until the ADLX exe is on the PC and on Intel, the VRAM and dataset fit, a bench-log row and a miner-bench.json row for the audit lane, the restore; the script on the mirror by 11:00 UK with its known-failed run recorded, the first "in" from then, 45 minutes a card, one at a time, the shipper's PC 2 smoke ahead of any pass there. Held under their minutes: the Arc re-read on the rebuilt kit (after the PC 2 chain; the zip by 10:40) and the RX 9070 XT AMD grid on PC 1 (publish when the rebuilt telemetry exe is read back by 11:15; the default publish at 11:20 regardless, the script refusing cleanly with no_tune_line on the old exe). THE IN-HOUSE PASS'S LAST LANDING (the crypto lane, 09:55 BST): crypto-engage b5c6f4d7 (full gate GREEN, 71 checks) landed as the mirror's master 9649f51e at 09:54:42 BST; the record cites three master commits: 00b8cd1b (the rule set, the board, the roll-up and every lane's 00:00 reading), 2882352c (the close), 9649f51e (the final section 14: the totals about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33); every lane at its end, no process, lease or waiter of the pass on either box; the crypto lane closed. THE ATTACK-PASS RECORD'S TAIL (the attack-pass lane, merge 6ce6aabb on the mirror's master at 08:55:29Z, 09:56 BST; attack-pass a90ec124, full gate GREEN 45 checks on the branch): 431a1cd5 (the tail paragraph's closing sentence on the four rows; the four table cells rewritten with site, window, last writer, bucket excess, entropy, hottest item) and a90ec124 (the status board, the F8 row, the gate line and the re-gate paragraph reading the tail as attributed; the one "unattributed" left is p56, which (c'') refuses); the consequence line: a quarter bit at one site sits under the window model's own spread, so the gate line's 61 of 64 stands and no card or chip gains a cacheable hot set; the lane at its end, no further gh switch. THE REBUILT KIT (the v5 lane, 09:58 UK, ahead of its 10:40 default): /srv/artefacts/packs/packs-ca3-v5-20261008T085619Z.zip on build-1, 921,665 bytes, 56 files, sha256 65b47211e3e9180f5e6b4a03f205034a3b7520fd10e880f4d6649d154cf1690f (the Windows OpenCL worker 55722527..., built 09:57 UK from the Intel-fix tree); the emulation check and the NVRTC worker's CPU run PASS on v5-dn3-epoch0; the suite on box 2 green (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs, ids and 82b19cbde8557ea5 byte-identical, recheck 2, scratch 7, spec_readback 3); commits a55fcc10, c0d398a1 (the Arc job keeps the host's whole stdout as RESULT lines), 8f481459 (a C99 declaration-order fix the kit build caught) on both mirrors; the Arc re-read with the hash lane through the shipper's PC 2 queue. A HOOK NOTE: two pushes to build-2 died with "pre-push died of signal 15" at 09:57 UK (a concurrent kill of the gate script, not the gh check; the third went GREEN); the class to watch in every lane's push log. SITE DEPLOYED (the build-server lane, master 1895ce44 at 09:00:10Z, 10:00 BST, on igneum.network and igneum.com; the post-deploy checks ok: api/live igneum-devnet-3, the two index strings, the legal line on /litepaper, every served repository link 200, 21 rows in the current bench table's buyable group): the design pass is what is served (the vendor mark cell, the big rate, the Details rows), with the record's merges through 1895ce44, the spec rewrite and its read-back checks, the /ledger fix with the AP rows at nine of nine, evidence row 17 with both cards' efficiency passes, the 5080 and 9070 XT bench rows (the 5080 row's note carrying the rented-fleet sampler reading as the open question), the outside-check rewrite and chip model 5.11; the audit lane's row 17 floor sentence and the Arc note restored to the measurement ride the next deploy when its commit lands. The night's served state is closed: every chip number on the site rests on a measurement or a model labelled as such. ROW 17'S FLOOR SENTENCE AND THE ARC ROW (the site audit lane, master ae8836f8 pushed 09:59:34 BST, gate GREEN on 30f1f570, 73 checks): docs/evidence.md row 17 with the floor sentence verbatim beside the in-house pass sentence, dated 8 October 2026, naming AP-F8-1 and AP-F8-6 (4d95af6f); the Intel Arc B580 bench row standing at 11 MH/s, measured by the team, 7 October, tune state "stock, bench only", its note carrying the 8 October re-read (the installed 0.3.21 worker's self-test 96 of 96, 54 re-checked blocks at 10.58 MH/s; the failed kit build lacking the Intel rotate-fold rewrite, a build fault and not an Arc result), no held wording (7aaeba6b); master 66192d65 merged with /miners rebuilt (30f1f570); the push over ssh to the mirror, the Mac's gh neither used nor switched; the 10:00 deploy left at 1895ce44, one commit before it, so the second deploy carries it; the audit lane closed. THE 0.3.25 NODE BUILD'S SHAPE (the node lane, 10:0x BST; release-0.3.25-node opened from the pin 5b673577 in a second worktree, release-0.3.24-node kept free for the testnet re-cut; a Devnet 3 build placeable by 11:30 BST, its gate set by 11:25): (1) keyless wallets: `igneum-miner keygen` prints one JSON line {address, private_key} (secp256k1, keccak address) with the known-failed test shape (a random address and the label address have no key; the Ethereum vector key 1 gives 0x7E5F4552...; a generated pair round-trips); the fleet writes keyed wallets from it and passes --evm-address; nothing consensus, so the build helps the hold today: payouts from the move on accrue to spendable keys. (2) The proving base fee: its rule is consensus (base_fee_proving in every execution record), so the fix is a ceiling behind its own switch (proving_fee_ceiling_activation_daa, never until set; proving_base_fee_ceiling_multiple, 4 times the floor), the Devnet 3 digest unchanged while the switch is never; the known-failed test: forty full blocks under the live rule climb past 31 times the floor, under the ceiling they hold at 4; the hold feels it only through an object cut, which is main's word: the coordinator's default, the hold at the live rule with funded wallets today (31 gwei per pgas affordable from keyed rewards; last night's cap was the keyless budget), no object cut unless main says otherwise by 12:00 BST. (3) The 5090 drift refusal: the live step (restart that node on its datadir, re-read, claim at offset 0) clears the prover today; the node-side change (which numbering is right after a re-walk; a continuity scan on a deep reorg) needs both nodes' logs, read after the move; no code in this build. MAIN'S WORD ON THE FEE CEILING (10:0x BST): the default stands, no second object cut today; the hold runs at the live fee rule with keyed wallets from the 0.3.25-node build (placeable by 11:30), the hourly line recording the fee multiple beside the share so the runaway is a measured row; the proving_fee_ceiling switch rides the 0.3.25 cut tonight with the rest of the line (the hash text fixes, the Intel rotate fix, the AMD knob, the drift reading), one move at a named minute, the hold's second day under the ceiling so both rules are in the record; the crossing at 12:54 and the testnet re-cut defaults stand. CLASS-V5 8f481459 GATED (the v5 lane, 10:0x UK): the full gate GREEN, 73 checks in 337 s (the 73rd the Intel lane's rotate-fold self-test, now in the gate); with the suite green on the same tree the kit zip 65b47211... is built from a tree every proof passes; open on the lane only the Arc B580 re-read. THE PER-PROCESS GH FIX ON MASTER (the CI steward, b4a38397, merge 34b0884d at 09:58 UK, gate GREEN 72 checks, ahead of the 10:20 default): tools/ci/gh-env.sh sets GH_CONFIG_DIR=~/.config/gh-igneum for the gate, the hook, merge-to-master.sh and ci-state.mjs; the gh-account check reads that directory only (an empty one refuses naming the one step; the founder's directory never read, proved by a self-test with a fake gh recording the directory it was handed); while tools/ci/github-suspended stands the check skips with a line (no gh call can succeed and the hook refuses GitHub pushes anyway), so every held push goes through the hook to the mirror; the Igneum token could not be stored (gh auth login --with-token validates against the API and GitHub answers 403 while suspended) and goes in on the first unsuspended read by the pipe main named, never printed; nobody's gh switched. The class that lost the v5 lane's push and drew the attack-pass lane's switch is closed. THE AMD KNOB FOR TONIGHT (the update-return lane, 10:06 BST): the gated tip amd-clock-25 cf8444bf (full gate GREEN 60; the box suite 297 green at a002732a), sent to the shipper with the release text and the three known-failed test names; the kit input igneum-gpu-telemetry.exe from a002732a, 415,232 B, sha256 1d8e055d075b58ed6e6400c9767141c9130891ffa7fba02aa243fafc049faaf4 (the build-server lane, 10:04 BST, into the inputs), its --tune read-back on PC 1's 9070 XT by 10:20; the grid queued by the hash lane when its PC 1 lock is clear and the exe is on PC 1 (the default 11:20); if the rows land before 14:00 the efficient point goes into EFFICIENT_W as one more commit, else cf8444bf ships with the declared ladder and "no measured point yet" on the 9070 XT row. THE 0.3.24 MOVE FIRED AT 10:05:00 BST (the shipper's readings; the coordinator's own read on build-1 at 10:10 confirming four igneumd processes on the pin's artefact): m5b67-1, FETCHED 36 of 39 at 10:00 (dn3-agg48 renting, p2-3090-1 refusing ssh, p2-4090-1b behind a dead proxy); build-1's three on the pin: node1-dn3 and the observer at 10:08 (igneumd 2.1.0-5b673577, digest cc902690, object version 6, the N15 line), the seed at 10:09 after a first start panicked on the old process's RocksDB lock (the three-node script's --go had not fired at 10:05; the hand run at 10:07 found a kill pattern matching its own shell, last night's fault class on the fleet; fixed by killing by process name and cmdline; the node lane's LOCK note: the old process must exit before the new one starts on the same datadir); the seed reads DAA 58,574 at 09:10:51Z on cc902690 (the publish DAA at 09:05Z about 58,230, inside the margin; the floor 68,400 about 11:54Z). The 0.3.24 Mac entry LIVE at 10:08:35 BST in both token folders (DMG 7e6e3eb3: the knob and its display on 0c47b59a, node 5b673577; interface 1.0.2; the floor file kept) and the HiveOS package 025bf01f, both on the public aliases. Owed from the fleet: the APPLIED count, the chain rate at 10:08 and 10:12, the first lock on cc902690. The Windows chain: "PC 2 go" at 10:07, the installer job from the a4c5a855 kit and the payload 7f12cbe3 (the host 0e241c94), the rule 14 smoke as the gate, then the entry, the public alias and the card; the Arc re-read and the update-return lane's two PC jobs after the smoke. The 0.3.25 plan to the coordinator before 14:00 BST. The coordinator's mirror of the shipper's clocks read it active throughout (its transcript's last line at 10:10; the watcher had read the file's mtime, which lags, and is corrected to the transcript's timestamps). After three lost floors and a stood-down night, 0.3.24 is on Devnet 3 with class v5 at DAA 68,400, about 12:54 BST. THE 0.3.25 PLAN (the shipper, 10:1x BST, from the mirror's tips). Branch and pairing: the app line release-0.3.25 from release-0.3.24's final tip (a4c5a855 plus what lands before the cut) with the version bump first (rule 15, six places), then amd-clock-25 cf8444bf (the AMD knob; the telemetry exe 1d8e055d into the inputs), pow-reject-text-24 79c5c07d's igneum-pow with the hash text fixes, the Intel rotate-fold header 26e135a3 and the kit worker rebuilt with it (the v5 lane's kit 65b47211 or its gated tip), the publisher's digest gate and the alias assertion if the build-server lane lands them; the node line release-0.3.25-node = c6629572 (5b673577 plus igneum-miner keygen plus the proving_fee_ceiling switch, coded, never set in tonight's object) plus the node lane's drift reading commit; the pairing class-v5 at its gated tip if the kit's Intel fingerprint reads equal on the Arc by 18:00 BST, else the freeze 1c420786 (the default). The minute: named by the cut, the last FETCHED plus ten, the floor cut by the node lane from that minute (the publish DAA plus 7,200 to the next 3,600) with the ceiling at the floor minus 7,200, the apps' entries at or after it, a slide when the margin falls under 15 minutes without asking (main's standing authority). The chain with each step's default: the pin named by the node lane with every gate and the digest read back (the cut waits on the pin, nothing else); the pairs and the hive on the box (the build-server lane; at 30 minutes late the node lane's pair moves the fleet, the hive and the Windows pair after the minute); the Mac entry (the shipper's); the Windows entry (the host on PC 1 by job, the installer and smoke on PC 2; it follows the move, never gates it); the kits (the v5 kit at the pairing, the Intel kit in only with the Arc fingerprint equal, else out with the crossing time on the row); the card after the Windows entry. The gate set before the file goes: every box suite on the pin, the two canary sets with the mixed-version refusal, the fast-time SUMMARY on the shipped pair, the kaspa-pow pairing read-back, the app crate gate and pre-push on the app tip, the pack-gate line read back on every reachable box, F8 if the pairing moved off 1c420786, the F9/F1 interim at the minute minus five if F8 was rerun. The move's mechanics from today's lessons: the puller takes the pair's miner sha from the move file (the fleet's puller fix), a box with no running box-dn3.sh restarts from a quoted environment (the nine-node fault of 10:05, the fleet's third known-failed shape), build-1's three by process name with the old process's locks released first. Open: the drift reading's commit (not a consensus field by its description); the evening minute from the shipper the moment the pin is green. CARD-IN READY (the hash lane, 10:1x UK; tools/ca3-v4-amend/pc-card-in.ps1 at 3566ecfe): both known-failed shapes recorded on PC 1 (the baseline of 4 cards; "no new card" in 1 s); a relay "in" with the PC publishes one job (55-minute cap) giving the card's key, VRAM and dataset fit, the v5 and v4 fingerprints through the OpenCL kit on every vendor plus the CUDA sub-version 3 row on NVIDIA, the rate with all three power fields, the lock grid through the helper on NVIDIA (300 MHz steps from the maximum, stop at a 3 percent fall) and measure-only rows on AMD and Intel, the app's own row, the bench-log and miner-bench.json rows as RESULT ROW lines, the restore and "next". The Ember tiers' engine half on ember-tiers-25 at 91406944 (local; the push on the box test build's green by 10:45). The Arc re-read's default: 10:50 UK unless the shipper clears PC 2 earlier. MAIN'S WORD ON THE 0.3.25 PLAN (10:1x BST): it runs as written, one addition to the app line: the three-tier Ember Tune, both halves (the hash lane's engine fields and the apply Cmd on ember-tiers-25; the UI lane's tier buttons with rate, watts and the daily saving, sweep on by default at balanced, per-card wired), gated on 0.3.25 before the cut; if either half is not green by 19:00 BST the cut goes without it and the tiers ride 0.3.26, stated in the record; everything else stands, the silence-means-go at 17:00 and the shipper's minute; two readings to main: one when the pin is green, one at the minute. THE FOUNDER'S WORD AT 10:2x BST: push 0.3.25 everywhere as soon as possible; the plan stands in every mechanic, the clock moves: the cut goes the moment its inputs are green, not tonight. The targets: the node line placeable 11:30; the app line assembled by 12:30 (the AMD knob and exe, the hash text fixes, the Intel header and the rebuilt kit worker, the tiers if both halves are green by 12:30, else they ride 0.3.26 and the record says so); the pin green by 13:00; the move at the last FETCHED plus ten but never before the class v5 crossing at 68,400 (about 12:54) has been read clean by the node lane, so the earliest minute about 13:30; Mac and Hive at the minute, Windows behind it within the hour, the card after; the pairing default 1c420786 unless the Arc fingerprint reads equal by 12:30; the defaults and the slide authority stand; main's silence past any of these clocks means go. THE TIERS' UI HALF (the UI lane, 10:52 BST): branch tiers-25 off release-0.3.24 a4c5a855 = the UI commit e6571f60 plus the merge of the hash lane's ember-tiers-25 3408db40 (d3d0704a); the UI tests known-failed first then 73 green on build-2; mock captures of the three states (the measured 5090 and 5080 at Balanced; the install's first minutes with nothing measured and Ember Tune on at Balanced; the M5 Max with no lever as Stock alone with the reason) under ~/Desktop/igneum-previews-2026-10-08/tiers/; the app crate gate and the full pre-push gate running on the merged tip, the gated tip by about 11:15, inside the 12:30 default; tiers-25 fast-forwards onto release-0.3.25 when the shipper opens it from a4c5a855; the live tier numbers come from the engine's own search, not from any table. THE BUILD-SERVER LANE'S CLOCKS (10:1x BST): the 0.3.25 pairs the moment the pin is named (the start script parameterised on the pin); the publisher's digest gate (publish-manifest.sh --node-bin, --network-digest, --move-clock; tools/digest-read.sh) landing on master before 12:30 and riding the app line (the alias assertion not its own); the telemetry exe's --tune read-back on PC 1 DONE at 09:07Z (the 9070 XT tune line: gmax 0 range -500 to +1000, plimit 0 range -30 to +10, factory 1); the second master-only deploy started 10:15 BST on master's tip. A FAULT: PC 2's 0.3.24 Windows installer failed at ISCC because release-0.3.24's .iss still carries the TDateTime line the 0.3.23 fix removed; the one-line fix with the shipper and the update-return lane, the republish on their tip (the Windows entry's default: it follows the move, never gates it). A SPEND TO SURFACE: two new Hetzner boxes provisioning (build-3 HEL1 32 threads, build-4 FSN1 96 threads, in the pool by 10:45), reported by the build-server lane; ordered on the founder's own word in chat ("re order", about 09:5x BST, after he added the credit himself; main clicked the order in his Chrome profile); the standing rule on purchases held; they stay. SITE DEPLOYED AGAIN (the build-server lane, master f98e8e7c at 09:15:33Z, 10:15 BST, on igneum.network and igneum.com; the checks ok): the tip carries ae8836f8 (row 17's floor sentence, the Arc row restored to its measurement) and the record through the twenty-eighth landing; the served state now carries every served change of the night and morning. THE 0.3.25 NODE LINE PLACEABLE (the node lane, 10:1x BST, ahead of 11:30): release-0.3.25-node = c6629572 on both mirrors (the pin 5b673577 plus igneum-miner keygen and the proving-fee ceiling switch coded and never set), pairing igneum-pow 1c420786; every gate green at 09:16:28Z (build 09:13Z rc 0, igneumd 3fadca49..., /srv/artefacts/0325-c6629572/node-lane; consensus 134, pow 19, miner 29 with the keygen test, p2p-flows 38, exec 48, core 177 at gate priority after a first run on a stale file on the box); the Devnet 3 canary (09:13:25Z to 09:15:04Z): digest cc902690 unchanged, byte 6, the override refused, two empty nodes handshaking, the shared-devnet dialler rejected, and the 0.3.24 pin's node handshaking with this build both ways, so the mixed fleet runs through the placement; the testnet canary b2e856ed unchanged. The keygen read-back from the artefact printed an address and a key (the key elided in every transcript and record; a printed private key never enters a message, a log the relay carries, or this file); the fleet writes keyed wallets from it. The defaults: the line's tip at 13:30 BST is c6629572 plus the drift reading's commit only if both nodes' logs reach the node lane by 12:30, else without it; the ceiling-switch field set in the 0.3.25 object from the shipper's minute by the one-go script (the digest moves then; the hold's second day under the ceiling, as main ruled; a re-cut without asking under a 15-minute margin); the crossing line the moment the DAA passes 68,400, a red first; the TESTNET_PARAMS v5-at-0 re-cut at 13:30 unless main says otherwise by 13:15. THE AMD KNOB'S GATED TIP MOVED (the update-return lane, 10:15 BST): amd-clock-25 e2962b89 (full gate GREEN 60, the box suite 298 green) in place of cf8444bf, with the shipper; from the exe's read-back on PC 1: the integrated Radeon's tune line carries every range as a dash and the knob had read it as an offset knob with a one-MHz ladder; it now reads "not available (the driver exposes no tuning interface for this card)", and the 9070 XT's real line (gmax 0, range -500 to 1000; plimit 0, range -30 to 10; stock 3,292 MHz under load) is the test's second half: the ladder 3,192 down to 2,792, the power 70 to 110 percent, offsets on the apply; the grid by 11:20, the efficient point into EFFICIENT_W before 12:30 or the declared ladder ships. THE MOVE'S READ-BACK (the fleet lane, late against its 10:20 minute): APPLIED on the relay at 09:07Z: 24 MATCH by the puller (igneumd 2.1.0-5b673577, digest cc9026909eddbadb, synced; dn3-g1 at peers 24), p1-3080 on cc902690 by 09:10Z; 2 FAILED (dn3-r01, dn3-r02: no saved environment, hand-started yesterday) moved by hand at 09:10:27Z; 9 MISMATCH with no node after the puller's restart (hub-1, dn3-g2, dn3-q04, dn3-q05, dn3-r04, dn3-p02, dn3-p04, dn3-p05, dn3-relay): the saved environment line NET_ARGS=--devnet --devnet-suffix=3 unquoted, so sourcing it ran "--devnet-suffix=3" as a command and the start never reached box-dn3.sh; all nine moved by hand 09:11:58Z to 09:12:24Z with every value quoted, the puller now quoting every value (redeployed 09:16Z on 34 boxes); so 36 of 36 fetched are on 5b673577 and cc902690 by 09:12:24Z (10:12 BST). The first lock on cc902690: checkpoint 1931, block 63510971..., blue score 57,930, at 09:06:32Z on dn3-g1 (4,803 signed, 69.8 percent of active, 66.7 of total); hub-1 logged the same checkpoint at 09:11:43Z after its hand restart and checkpoint 1944 (blue 58,321) at 09:12:39Z. The chain rate: hub-1 read 0 blocks a minute at 09:07Z because hub-1 was one of the nine down; from 09:12Z the tip moves at about 0.4 chain blocks a second as before, and paidShards moves again (11,821, frozen since 03:32Z, to 12,012 at 09:19Z, pool entries 47): carrying resumed with the move, the node lane's one-shot-gossip class confirmed. The proven share at 09:19Z 0.465 cumulative (the hour's own 0.000, the hour being the move); the proving fee 10,000 gwei per pgas last, 50,566 max over 60 blocks (1.0x and 5.1x the floor), the field now on the hourly line. The unfetched: dn3-agg48 (the L40S in its bring-up, applying at its first tick), p2-3090-1 (ssh refused since 21:48Z yesterday, on 2720d8d2 with 4 old-digest peers), p2-4090-1b (its Vast proxy dead, its node down); dn3-relay fetched at 08:48Z and is on cc902690. The eight "bc5945fe" boxes: no such binary (that sha was the reader's own shell); those boxes had no node at all (dn3-g2 dead since 22:49Z, dn3-g1 since 00:46Z, the others overnight, no panic or OOM on any), restarted 08:43Z to 08:53Z, took the move with the rest, and mine where they mine. The keyed-wallet write not started (the 0325 artefact's first mention to the lane at 10:20; box by box after the launch fleet's first boxes are up; the rent running since 09:16Z). p1-5090's drift reads offset -5 again at 09:21Z; hub-1's numbering against build-1's node the next read. Three fault classes for the record from one move: the unquoted environment line (fixed in the puller), the two hand-started boxes with no saved environment, and the eight boxes that had silently lost their nodes overnight with no panic (a watch for a node absent while its box is up is the fleet's next check). THE TIERS GATED FOR THE CUT (the UI lane, 10:20 BST by the Mac's clock): tiers-25 at d3d0704a on the mirror (the UI commit e6571f60 plus the engine half 3408db40 merged, both off release-0.3.24 a4c5a855, a fast-forward onto release-0.3.25): the app crate gate GREEN 299 + 35 + 8 on build-2, the full pre-push GREEN 60 checks with the stamp, the UI tests 73 green known-failed first, the push gate GREEN; the captures under ~/Desktop/igneum-previews-2026-10-08/tiers/; sent to the shipper; two hours inside the 12:30 default; a rebase and re-gate inside the hour if 0.3.25 opens from a later tip. Both halves of the three-tier Ember Tune are in the cut. THE 0.3.25 APP TIP (the shipper, 10:29 BST, two hours ahead of the 12:30 target): e0d4425f on release-0.3.25 (the box gate green): amd-clock-25 e2962b89, tiers-25 d3d0704a (both halves), the Intel header via 9088293a, the node-source pin c6629572; the node pin candidate c6629572 with the digest cc902690 unchanged; the cut list r0325-cut-list.md: the pin named by 13:00, the move no earlier than 13:30 after the 68,400 crossing reads clean; the pairing 1c420786 unless the Arc reads equal by 12:30, the Intel kit on that read. THE 0.3.25 NODE LINE'S TIP MOVED (the node lane, 7bd2940f on both mirrors at 09:24:03Z, every gate green at 09:29:48Z): c6629572 plus the one-shot gossip fix (unpaid proof records re-announced every 120 s; the class confirmed on the live chain after the 09:05Z move); nothing consensus, the Devnet 3 digest cc902690 unchanged on its canary, the 0.3.24 pin's node handshaking both ways, the testnet digest unchanged; build 09:26Z rc 0 (igneumd 16dee9f1..., /srv/artefacts/0325-7bd2940f/node-lane), exec 49, pow 19, core 177, p2p-flows 38, miner 29, consensus 134 at gate priority; it replaces c6629572 as the placeable keygen build and as the tip the ceiling-field cut lands on; the shipper has the line. The drift item is off this line: the fleet's reads were shared-devnet reads (hub-1's node on 26790 at chain block about 190,900; Devnet 3 at 25,900; both answering chain id 4463 below the floor), p1-5090 a shared-devnet prover, and the three numberings at one hash are the snapshot-inherited class (build-1's node1 itself resumed from a snapshot); the fleet rents a fresh-walk node under its standing ceiling to settle which numbering is right, hub-1's restart held until then, the loader change (re-number the resumed range against the DAG) after that read. THE 0.3.25 PAIRS ON 7bd2940f (the build-server lane, from 10:33:11 BST on build-1 under lease class release, /srv/artefacts/0325-7bd2940f/: the seed about 10:36, the Windows pair about 10:38, the hive package with the three kit zips about 10:41, each minute to the shipper and the coordinator); the c6629572 pairs already built (seed f913e3e7, win 42d0dd57, hive 14d86245) stand in their own folder and are not the cut; the publisher's digest gate on master since 10:17, riding the 0.3.25 app line. THE RE-POINTED APP TIP (the shipper): 92f004f1 on release-0.3.25 (e0d4425f plus the node-source pin to 7bd2940f), the push gate GREEN at 10:32 BST, the box gate GREEN at 10:33:25 (303 + 35 + 8); the cut list's pin candidate 7bd2940f; the kit re-cut from 92f004f1 and the pairs on 7bd2940f's artefact with the build-server lane; the Mac node pair and the DMG rebuilding on 7bd2940f under the lock from 10:32:31; the 13:00 pin and the 13:30 earliest minute standing. The 0.3.25 inputs are all green at 10:33 bar the pin's own gate set and the crossing. A SWEEP FINDING FROM MAIN (10:4x BST): on a rented, power-capped RTX A4000 (114 W cap) class v5 reads 26.0 MH/s against v4's 31.4, 17 percent under, the fingerprint equal; the A100 1.3 percent under; every uncapped consumer card level: v5 costs more compute per hash and a compute-limited card pays, which is what a knee lock makes of a card. Two orders with readings by 12:30: (1) the hash lane sends the 5090's v5 pack rows at the 1,300 lock against v4 at the same lock, and the 5080's if they exist; if v5 at the knee loses more than 2 percent, the knee is re-found under v5 and the tiers table says so; (2) the tiers' engine half: a class change (the chain's program class flipping) invalidates the stored tiers and re-runs the search within ten minutes of the crossing, the first-run line saying why; known-failed first (tiers stored under v4 must read "re-measuring for class v5" after the flip, never apply as if current); on 0.3.25 if it fits by the cut, else 0.3.26 with the record saying the v4 tiers may be off by the measured percentage until the re-tune. Per tier: a locked card may lose a few percent of rate at the class v5 crossing until Ember re-tunes; the number is the 5090 row. THE ORDERS PLACED (the coordinator, 10:4x BST): the hash lane's two readings by 12:30 (the 5090's v5 rows at the 1,300 lock against v4 at the same lock, the 5080's if they exist; the knee re-found under v5 if the loss is over 2 percent; the default if the PC 1 queue cannot run it: the A4000's 17 percent stated for a capped card and "unmeasured at the knee on the 5090"; and ember-tiers-25's class key: a class change invalidates the stored tiers and re-runs the search within ten minutes, known-failed first), the UI lane's class-flip state ("re-measuring for class v5", v4 tiers never applied as current after the flip) and knee note by 12:30, the shipper's cut list carrying both on 0.3.25 only if green by the pin at 13:00, else 0.3.26 with the record's sentence that the v4 tiers may be off by the measured percentage until the re-tune. THE 0.3.25 PAIRS ON build-1 (the build-server lane, /srv/artefacts/0325-7bd2940f/): the seed pair at 10:34:44 BST (igneumd c7fc542b, igneum-miner 4494ecc4, glibc 2.34), the Windows pair at 10:36:13 (igneumd.exe 5d1dea23, igneum-miner.exe eee7bdfa), the hive package igneum-hive-0.3.25-7bd2940f.tar.gz at 10:37:49 (sha d977797f..., the three kit zips, smoked in ubuntu:20.04); the kit re-cut from 92f004f1 (sha 676240f6, 424,540 B) staged in both folders, the PC 1 host from it bc8d4f79 (in host.sha256 at the shipper's 24680e1d), the 0.3.25 Windows payload from 24680e1d cutting. Every pair of the cut exists by 10:38; the pin's gate set and the crossing are the only waits. FOUR NEW LANES ON THE FOUNDER'S ORDER (11:00 BST, "build all this today to close this gap"), mirrored by the coordinator as the shipper's clocks are: the explorer (a5ef1d5801084005b; explorer.igneum.network by 16:00), the canonical DEX and the Sepolia certificate verifier (a74a8267813d6ea34; the AMM by 14:00, the swap UI by 17:00, the verifier by 20:00), the builder pages, faucet and grants (adb29da59baf27898; /build and /grants by 15:00, the faucet by 16:00), three reference apps that only work on a proven chain (a2060899d2a27d31c; /light by 16:00, /receipt by 18:00, the Sepolia oracle demo by 21:00); the build-server lane stands up rpc.devnet.igneum.network by 12:00; they do not touch the 0.3.25 cut, the crossing or the fleet, sharing the boxes' lease pools (class measure) and the master-only deploy; a lane silent past 25 minutes gets the word from the coordinator and then main. THE FAST-TIME GATE ON THE 0.3.25 PAIR: SUMMARY PASS (cross-0325-39f127a1) at 09:54:40Z (10:54 BST) on the pair 39f127a1 (the node code and object byte for byte e0644958's; igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 09:42:25Z to 09:54:40Z, every check green (rung 1 by signal at epoch 6, class v5 by signal at byte 6 from epoch 8 at rung 1 at 9,985 bps, the stale node refused, the restart step resynced in 8 s, four sinks equal, 0 PoW rejections); the ceiling's two new fields absent from the 60x file so the ceiling stayed at never there (the node lane's note); to the shipper the same minute; the pin line names e0644958 and its gates. THE FOUNDER'S WORD AT 11:0x BST ("can we add in any more layers? class rotating? things that would render an ASIC useless as soon as it dropped"): the class v6 design opens today as a rotating family, the research lane and the hash lane under the coordinator, the design doc docs/design/class-v6-rotating-family.md by 18:00 BST with the chip-model rows beside each layer (what it does to k and capex for a fixed-function chip and to the per-joule edge for a GPU-like chip; what it costs every GPU tier, Apple included): (1) per-era draws of the class parameters now fixed by release (the mixer round count within the tested margin, the op-mix weights within the measured safe band, the read width, the program length, the shadow placement), drawn from chain state like the program; (2) the state-derived dataset's size tracking chain-state growth with a floor, so fixed-memory silicon ages out; (3) scheduled family epochs by height (every 180 days by default) with no release; (4) the (c''') acceptance floor and the F8-form uniformity test generalised to each era's parameter draw, redraw on failure, so layers 1 and 3 need no per-era cryptanalysis. Per layer: the gate it needs (the family analysed as a family: the attack board's shape over the testnet period), the known-failed test, an honest line on what a fully general chip still gets. No consensus code this week; the document, the numbers and the gate plan. Per tier for the founder tonight: what each layer does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE ARC RE-READ IN ITS CHAIN (the hash lane, 10:57 UK): no clear came from the shipper, so the default ran at 10:50: the rotate-fold kit's fetch (sha 65b47211) published to PC 2 at 10:51:41, the run (run-ca3-pc2-v5-intel-bench-20261008, the v5 lane's script c0d398a1) in the publish chain behind another lane's publish-jobs.sh sign --deploy from the build-server worktree (the publisher serialises); the fingerprint line by 11:15 if the publisher frees inside ten minutes, else the blocking process named by 11:10. Queued on PC 1 behind the same publisher: run-ca3-pc1-v5lock-5090-20261008 (class v5 against v4 at unlocked, 1,300 and 1,200 MHz, the v5 kit's CUDA packs), its rows by 12:30; the AMD grid after it from about 11:25. The class-key work on ember-tiers-25 started; the v6 cost rows by 16:00 taken. THE TIERS' CLASS-FLIP STATE, THE UI HALF (the UI lane, 10:57 BST): tiers-class-25 at d949e274 on the mirror, off release-0.3.25's tip 24680e1d (the shipper having merged tiers-25 d3d0704a into release-0.3.25 at 111dae69), the crate gate GREEN 303 + 35 + 8 on build-1, the full pre-push GREEN 60, the UI tests 74 green known-failed first (the v4 tiers stayed on the buttons after the flip on d3d0704a); after the flip the table reads "re-measuring for class v5" on every button with the start minute or "queued (within ten minutes of the crossing)", the v4 watts never current, the strip's sentence naming the crossing; the knee note under the table when knee_loss_pct is over 2 percent; the captures tiers-flip-dark.png and -light.png; the fields tiers_class, program_class, tiers_remeasure_at, knee_loss_pct (the shape sent to the hash lane at 10:4x; the engine sha by 12:30); the default: the display rides 0.3.25 inert if the engine half is late and lights up on 0.3.26. THE FOUNDER'S WORD AT 11:1x BST: class v6 is DECLARED with the four layers as its spine (per-era parameter draws, the dataset tracking chain state, scheduled family epochs by height, the acceptance floor generalised to parameters), and deep past-and-future research opens now under the coordinator with serious resources ("see if anything can be optimised, added or invented"; reading public research is in-house, nothing paid or asked of anyone outside): four research lanes today, (A) history (every ASIC-resistant proof-of-work and how it fell or held: Ethash and the E3 and Linzhi chips, ProgPoW's review, RandomX and its chip analyses, Cuckoo, Equihash and the Z9, Argon2 and Scrypt and the Litecoin chips, KawPow, Autolykos, Octopus, kHeavyHash's chips; the exact mechanism each chip used and what the design missed, each mapped to Igneum's layers with "does v6 close it" as a sentence and a number), (B) the hardware future five years out (PIM and processing-near-memory, HBM3e and HBM4, LPDDR6, 3D DRAM, CXL memory pools, wafer-scale, chiplets, FPGA with HBM; for each the chip-model k band against a state-sized dataset and dependent random reads, and the one layer that would blunt it), (C) invention (layers beyond the four, each a paragraph, a known-failed test and a chip-model row: data-dependent program graphs, latency-bound dependent reads tied to the shard proof, randomised memory topology per era, VRAM-size ratchets, proof-carrying hashes sampled by the pool, time-locked parameter commitments, and what the lane invents; rejecting what costs GPUs more than chips), (D) the family gate (how a parameter family is cryptanalysed as a family: sampling bounds, coverage, the F8-form and (c''') tests over the parameter space, the attack board's shape over the testnet period, so layers 1, 3 and 4 can be automatic with a proof of what was tested). Resources: all four boxes under lease class measure, PC 1 by job for card rows, the rented fleet for one-shot measurements inside the ceiling. Deliverables: a first synthesis in docs/design/class-v6-rotating-family.md by 20:00 BST (the four layers priced, every finding from A to D with its number, a ranked list of what v6 adds beyond the four, the honest line on what a fully general chip still gets), the full report by 09:00 tomorrow, one line to main per lane as each lands; per tier at 20:00: what v6 does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE 0.3.25 APP TIP AND PIN CANDIDATE (the shipper, 10:58 BST): the app tip 9b93e649 (push gate GREEN; the crate unchanged from e0d4425f; the node-source pin to e0644958 and host.sha256 bc8d4f79); the pin candidate the node lane's ceiling cut e0644958 (digest 1b37cb9d, every gate green 10:53, the fast-time SUMMARY PASS 10:54, the floor at DAA 82,800 about 16:53 BST, a publish up to 14:53 without a second cut); the tiers' class-key halves: the UI lane's tiers-class-25 d949e274 green and inert alone, merged with the hash lane's engine sha the moment it lands (12:30), gated as a pair on the release tip, riding only if green by the 13:00 pin; the 0.3.24 Windows take 2 failed at a new place (Inno stopped the app and copied nothing); the update-return lane owns the fix on release-0.3.25 by 12:30, the default the 0.3.25 Windows entry waiting for a clean take 3 while Mac and HiveOS move at the minute. THE FOUR CLASS V6 RESEARCH LANES SPAWNED (the coordinator, 11:0x BST, each with its worktree, its box resources under lease class measure, its clocks and the rules): lane A history (a603a938582c43ab5; the first cut docs/analysis/class-v6/history.md by 15:00), lane B the hardware future (a4f73e2a6f2d1b757; hardware-future.md by 16:00), lane C invention (a5dfe95ee8c47cd0f; invention.md by 17:00), lane D the family gate (a07a99a3788566af2; family-gate.md by 17:00); each feeds the research lane's synthesis docs/design/class-v6-rotating-family.md by 20:00 (its outline by 13:00; the hash lane's per-tier rows by 16:00); the full reports by 09:00 tomorrow; the coordinator's lane mirror carries their clocks. A HELD PUSH AND ITS CAUSE (11:00 BST): the hash lane's push of ca3-v4-amend was refused at 10:58 by the gh-account hook reading the founder's gh (his personal login active again; nothing switched by any lane); the cause is the branch's own hook, which predates the per-process fix (34b0884d): the hook runs the branch's tools/ci, so every branch older than 09:58 must merge the mirror's master before its next push, under which the check reads Igneum's own gh directory and skips under the suspension marker; the rule to every lane. Live: the Arc re-read on PC 2 (published 10:59:47) and the v5lock job on PC 1 (published 10:53, about 12 minutes). THE CLASS V6 OUTLINE ON THE MIRROR (the research lane, docs/design/class-v6-rotating-family.md on counter-asic-4, the commit after fb61ed4b, pushed 10:5x UTC, two hours ahead of 13:00): section 0 the founder's table (per layer, what it does to a fixed-function chip and to a GPU-like chip on its release day, and the 5090, 5070 Ti and M5 Max columns, measured where the night's rows exist, the 5070 Ti scaled until the hash lane's row); the honest frame on top: the four layers render a FIXED-FUNCTION chip useless on the first era its wired value leaves (one tape-out lives one era) and move nothing for the stored-dataset chip with a programmable core except the core's size and the N5 project it forces; that chip keeps 3.6x at zero premium and 2.1x at k = 1 on a 5090 at its knee. The layer table (sections 1 and 2) names the bands each draw takes and the measured rows that set them: the mixer in {4, 8, 16} (x16 open), the op-mix weights within B = 4 with shuffle and mulhi capped (shfl 55.8 pJ per op), the read width in {1, 4} words (w64 excluded by the 5 October rows), the block shape 64 to 256 (never 1,024), N left to the ladder's signal (an unconditional draw retires the Apple tier at 200,000). Open numbers asked of the hash lane with defaults at 16:00: the 5070 Ti row (the rented 5070 scaled), the x16 mixer's verifier and build (the chip model's estimate), two re-weighted shadow packs for the op-mix band (the microbench arithmetic). Layers 2 to 4 and the gate plan are skeletons with their sources named, filling by 18:00 with the four research lanes' cuts, the synthesis by 20:00. THE FOUNDER'S WORD AT 11:2x BST ("all builders are idle, load them up"): build-1 to build-4 filled now and kept above 80 percent all day under the lease pool, class measure behind the release gates, in this order of value: (1) the class v6 family gate's sampling runs for lane D (the F8-form census and the (c''') floor over the parameter bands: the mixer {4, 8, 16}, the op-mix weights within B = 4 with shuffle and mulhi capped, the read width {1, 4}, the block 64 to 256; thousands of drawn eras, the uniformity and bucket tests on each, so the family document carries measured coverage tonight); (2) the attack families at scale on the 0.3.25 pin candidate's igneum-pow (F8 to 256 seeds, F9 and F1 to 10^6 on the frozen 1c420786, the day-key scan to 2^28) as the record's strengthening lines; (3) the invention lane's candidate layers measured as packs as fast as it writes them; (4) the full suite matrix of the 0.3.25 pin on every box as the pre-pin check; (5) the Windows and hive cross builds and the sweep's reruns; the lease tool's pre-emption giving release-class work the cores when the pin's gates need them; one line to main at 12:00 with the load on each box and what runs there, then hourly only if a box drops idle. THE DRIFT CLASS SETTLED (the node lane, from the fleet's fresh-walk node, a shared-devnet node synced from an empty datadir to 191,441 chain blocks at 10:03:45Z): hub-1 and five standing boxes number the fresh chain exactly; seven boxes carry numbering inherited from an exec snapshot taken on a chain that later re-walked (+2: p1-4090, p1-a5000, pool-1, build-1's node1; +3: p2-3090-2; +4: p2-3090-4; +5: p1-5090 and p2-3090-3), and a restart on the kept datadir does not re-walk (p1-5090 at 09:22Z stayed +5); the cost: a prover on drifted numbering signs statements the hub vetoes, so the seven earn nothing from proving until they re-walk, the drift refusal stopping the waste. The node lane's word to the fleet: p1-5090 first, both snapshot files moved aside so the executor re-walks from the DAG, the re-walk timed and read against the fresh node, then the other six in series, hub-1 untouched, build-1's node1 after the 12:40Z move; if the re-walk reads over two hours the six wait for the node-side fix on the next node line (the loader re-numbering a resumed range against the DAG before serving). THE 0.3.25 PIN CANDIDATE CONFIRMED (the node lane): e0644958 on both mirrors (keygen, the re-announce, the ceiling switch at 82,800 in the Devnet 3 object, digest 1b37cb9d, the 0.3.24 pin refused both ways), every gate green at 09:53:01Z, the fast-time SUMMARY PASS at 09:54:40Z on the same object; the publish ceiling DAA 75,600 (14:53 BST); waiting only on the 68,400 crossing reading clean (about 12:54; the node lane's line the moment the DAA passes it); the shipper names the pin at 13:00; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. LANE C'S FIRST PACK (the invention lane, 11:0x BST by the Mac's clock; its own line read "12:1x", a clock to correct): build-1 takes the igneum-pow build from counter-asic-4 at 5984ffab, then the per-load shadow in its sound form (mx8+shl6912x1: 16 sub-blocks of 432, one pass, the form 20.2a named and never drew) as the first candidate: the acceptance census over 64 seeds and 16 drawn eras against the 16x27 form and the class v4 shape, the pack export, the F8 read at 2^24 and the verifier bench on a leased core, the first read by 13:30; build-2 next for the second candidate (warp-uniform data-dependent block selection); the candidates with no pack form (the VDF commitment, the VRAM ratchet, the pool-sampled witness, the state-tied reads) stay modelled and the 17:00 cut says so; the worktree igneum-wt-v6-invention on class-v6-invention. THE WINDOWS INSTALLER CLASS AND THE 0.3.25 TIP (the shipper, 11:08 BST): the app tip 139c147a (9b93e649 plus install-detach-25 52a34111, packaging/windows and tools/ci only, the crate unchanged; push gate GREEN); the 0.3.24 take 2 class: an installer started under the app's job runner is a child of the engine, and the engine's kill_tree on quit ended it between PrepareToInstall and the copy; the fix re-launches the installer as a one-shot scheduled task outside the job's tree; the 0.3.24 Windows entry skipped; the rule-14 take on PC 2 is the 0.3.25 installer over the running 0.3.21 app, queued ahead of the Arc re-read; the pin candidate e0644958, the DMG 501ba293 staged, the 13:00 pin and the 13:40 provisional minute standing. THE ATTACK FAMILIES AT SCALE (the attack-pass lane, cores held at 11:08 BST, every run under lease pool class measure): box 2 (88 cores): F8 seeds p66 to p257 (192 new, 256 with the gate's p2 to p65) at 2^24 on class v5 at the freeze 1c420786 (the gated binary 0f5c98dc, pairing e5a4ac5978462156; the leaves re-run on 8f481459 if the kit pairing flips), the window-model control, by-site, as three thirds of 64 seeds; box 4 (80 cores held, 16 asked): F9 to 10^6 on 1c420786 (seeds 100,000 to 999,999 in six chunks of 150,000 at 8 threads, four running), F1 to 10^6 class v5 programs on 1c420786 (one census at 40 threads with the progress line and flushed partials, re-drawing the record's first 10^5 on the way as a reproduction check), the F4 day-key scan to 2^28 on 8ca66afa's redraw rule at 8 threads; nothing on build-1 or build-3 (lane D's); the projections: F4 about 2 to 3 hours, F8's 192 seeds about 9 hours, F9's 900,000 and F1's 10^6 about 30 hours each, so the 17:00 default is partials for those two with the lane (d) rows carrying counts so far; any pre-emption by release-class work reported. THE RPC AND THE 0.3.25 PAIRS ON THE PIN CANDIDATE (the build-server lane, 11:0x BST): rpc.devnet.igneum.network up since 11:08 BST (the first of the founder's builder clocks, 52 minutes ahead); the 0.3.25 pairs on e0644958 running on build-1 since 11:06 (the app tip 139c147a), the Windows and hive crosses on build-2, build-3 and build-4 as reproducibility rows at class release by about 12:40; the sweep reruns' list not held by the lane, the default at 12:30: last night's sweep logs on build-1 read for rows that ended without a result line and those rerun at class measure. THE SWEEP RERUNS' LIST (the fleet lane to the build-server lane, 11:1x BST): the fleet ran nothing under the build boxes' lease pool last night (every fleet bench a rented GPU one-shot), so the rows the lease kills cut short are the hash and class lanes' and the build-server lane's default read on build-1 is the right one; the fleet's own rows without a result (A10, A40, A100 40 GB, H100 NVL, H100 PCIe, MI250, RTX 3050, RX 7800 XT, 7900 XT, 7900 XTX, 6900 XT) are provider gaps needing a GPU host, rerun the moment a provider lists one. THE CLASS-FLIP TIERS, BOTH HALVES (the UI lane, 11:13 BST by the Mac's clock, 1 h 47 min inside the 13:00 pin): tiers-class-25 at 081b3ba7 (the display d949e274 plus the hash lane's ember-tiers-25 0a838072, on release-0.3.25's 9b93e649; the field names matched exactly): the crate gate GREEN 305 + 35 + 8 on build-1, the pre-push GREEN 60, the UI tests 78 green known-failed first, the push gate GREEN; with the shipper. A RED ON THE RELEASE TIP, for the shipper and the update-return lane: release-0.3.25's 139c147a is red on one crate test (ota::return_tests::no_relaunch_while_an_installer_runs_and_a_relaunch_when_it_clears, 304 of 305): install-detach's 0c588b09 reshaped the installer's clear step into a multi-line block while the test asserts the one-line literal at app/igneum-app/src/ota.rs:1348; 9b93e649 passes; the fix is the test's literal on the install-detach line; the UI lane built on 9b93e649 so its tip is green alone. A RED FROM THE PIN MATRIX (the CI steward, 11:13 UK): the core suite fails on the pair (the node e0644958 with the app tree 9b93e649): config::params::tests::fast_time_60x_file_is_the_devnet_at_60x panics "override-60x.json lacks the field base_unit_decimals"; the field was added by 0e4ec18a on ca3-v4-node yesterday at 21:45 UK and reached neither master, release-0.3.25 nor the app tip while the node line's test demands it; so every box reads red on core, and the fix is one line on release-0.3.25 (the cherry-pick of 0e4ec18a, or "base_unit_decimals": 8 in infra/fast-time/override-60x.json); sent to the shipper; green so far pow and app on build-1 and build-3; the two new boxes' toolchains read the same as build-1 (Ubuntu 24.04.5, glibc 2.39, the pinned rustc, sccache and lease, no nvcc). The founder's fourth load item paid in its first ten minutes: a red no single-box gate had read. MAIN'S WORD ON THE TWO REDS (11:1x BST): the install-detach fix belongs in 0.3.25 if it can make it, since a Windows install by any path that lets the engine's job runner kill the installer mid-copy is the plug-tune-play fault class (an update a user repairs by hand); the default order: the update-return lane fixes the ota.rs literal by 12:00; if 139c147a plus the fix is green on the crate gate by 12:15 the cut goes from it, else from 9b93e649 with the detach on 0.3.26 and the record saying Windows installs by job stay unreliable until then; the missing 60x field: the CI steward lands the one-line field on master and the release line by 11:45; the pin slides under the shipper's authority inside 14:53. THE DAY-KEY SCAN TO 2^28 (the attack-pass lane; class-v5 8ca66afa's redraw rule, build-4 under lease pool 8 class measure, 379.2 s, census-2p28.md at 10:15Z, 11:15 BST): days with any gain over 1.1x: 0 of 268,435,456 on M1 (median 226), 0 against the mean, 0 on M2, 0 on ROT and RC; the M1 cost mean 225.791, sd 6.073, min 206 (day 27,016 at 1.0971x, the redraw rule's floor: no day under 206 in 2^28), max 258; every weak class on its analytic expectation (ROT any pair summing to 32: 160,354,008 against 161,256,979; RC any zero: 1 against 1.0, at cost 234, no gain; RC with rk = 0: 87 against 72, 1.8 sigma; the two cells under expectation the rule's own refusals). PASS: no chip buys a weak day in the first 735,000 years of days; at most 1.097x on the best day. The row and f4-weakday.md section 10 committed on attack-pass at eabb4b0e, the push held by the branch's old hook (the fix: merge master, under which the check reads Igneum's own gh directory and skips under the suspension marker). THE SWEEP RERUNS' READ (the build-server lane, 11:18 BST): build-1's records hold no hash-lane or v5-lane run the pool cut short (preempt.log: three TERMs all night, every one to an adv-class holder pre-empted by a release gate, not reruns by rule; no reaped.log; builds.jsonl for 18:00Z to 09:00Z 150 rows with no signal end, the non-zero rows the fast-time gate's designed failed cases and build errors; the census and fingerprint suites leaving no builds.jsonl row and no output directory ending without its result); live at 11:17Z the family gate's v5_attempts_census holding 24 cores on build-1 at class measure; the default at 12:30 if neither lane names a run: no reruns, the boxes carrying the e0644958 reproducibility crosses (build-3's Windows pair already read: igneumd.exe 4b0c3aeb, igneum-miner.exe b3da4088) and the gates. The founder's fifth load item is therefore the crosses, not reruns. The attack-pass branch merged master and pushed (460fd9fa, the F4 2^28 row and f4-weakday.md section 10 on the mirror; the hook skipping the gh read with its suspended line; nothing switched). THE FAMILY GATE'S FIRST COVERAGE (lane D, 11:2x BST by the Mac's clock; its own line read "11:3x"): the harness live on build-1 under lease pool class measure (scripts and pinned binaries under /srv/builds/_adv-family-gate/): (1) the base control v5_attempts_census on the shipped class v5 draw over f8-label seeds 1,000 to 11,000, 24 cores since 11:16; (2) the family harness family_gate_era_census (branch family-gate-v5 = class-v5 8f481459 plus the harness, never a chain path; the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE): one drawn era per seed, every layer-1 parameter from the era's own stream (the shadow block {64, 128, 256} x {108, 54, 27}, the mixer {4, 8, 16} recorded, the read width over {1, 4} words, the ten weights within B = 4 with shfl and mulhi never raised), the chain draw through the real rule with every candidate's first failing part, then on the accepted program at the rule's own 2^20 sample the (c'')/(c''') ratio, the largest 256-item bucket per site (ratio and sigma), the index-bit bias per site in sigma; the 16-era smoke run PASSED at 11:21 (about 10 core-seconds per era; 10,000 eras about 28 core-hours). THE WORST READINGS IN THE 16: (a) the index-bit bias read fires HARD on 7 of 16 eras, |z| 130 to 511 at one site, every one at address bit R (the era's stride rotation) or R+1 (era 15 with R = 25 bit 25 z -511 at P(bit) 0.25, a product's bit 0; era 7 R = 17 z -468; era 5 R = 26 z -440; era 13 R = 1 bit 2 z -255, a product's bit 1 at 3/8; era 1 R = 6 z -224; era 12 R = 5 bit 6 z -130; era 6 R = 18 z +256, an or-shaped source at 5/8), the other 9 under |z| 3.8: adv-cache-2's era-stride class measured at the acceptance's own sample on class v5 accepted programs: not diffuse at the bit level, a 25 percent bias on one address bit of one site in about 40 percent of drawn eras, which (c''') does not see (min ratios 0.9954 to 1.0000); a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50, about 1.6 percent of a hash's reads at f = 1/2 for one site, which does not move the f = 1 verdict but is an auditor's flag on "uniform random reads"; the lever is load_index's form (fold the product's low bits before the rotation), not a floor (a 6-sigma refusal would redraw about 40 percent of epochs): a class v6 design row. (b) The (c'') ratio min 0.9954 (era 7), the rest 0.9965 to 1.0000. (c) Attempts: 14 of 16 accepted at attempt 0 or 1; era 9 (shape 64, width 4, mul 11 and or 8 of 75) took 24 candidates: the lossy corner raises r, the exhaustion number to read per stratum. (d) The largest 256-item bucket: ratios 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets, +4.4 sigma), so the F8-tail bound must be stated in sigma, not ratio (the sigma column in the rebuild). Next: the random stratum (10,000 eras) and the corner strata (the lossy cap, width 4, shape 64, 3,000 each) on build-1's free 64 cores, then build-3 and build-4; the first cut of family-gate.md drafted, the measured coverage table in at 16:xx for the 17:00 cut. THE OTA TEST LITERAL FIXED (the update-return lane, 11:23 BST, ahead of both clocks): ota-test-25 off release-0.3.25 139c147a, tip 53cb2f73 on the mirror, one test-only commit (the test reading the installer's clear step as the begin/end block the detach made it; the detach's behaviour kept), the box 2 crate suite 303 + 35 + 8 passed, 0 failed, the full gate GREEN 60; the shipper's cut tip 139c147a plus this commit, so the install-detach rides 0.3.25 and the PC 2 rule-14 take runs on it. THE 60x FILE, THE WHOLE FILE NOT ONE FIELD (the CI steward, 11:25 UK): the test names the first missing key in key order; with base_unit_decimals in it named emission; the file on master and release-0.3.25 lacks six keys the 0.3.25 node line's OverrideParams has (base_unit_decimals, pool_split_activation_daa, program_class_v5_activation_daa, proving_base_fee_ceiling_multiple, proving_fee_ceiling_activation_daa, subsidy_per_block_activation_daa); ca3-v4-node's copy (81 keys, master's 75 plus those six, no shared value differing) passes on build-3 by hand; release-0.3.25 got the one-field commit 907fdaf4 at 11:23 and the whole-file commit follows through the hook's gate, master the whole file behind the one-field landing; the known-failed on record on all four boxes; the green from the core re-runs in the 12:30 matrix; the risk named to the shipper: an older daemon reading the file with deny_unknown_fields. THE INDEX FOLD AS A CLASS V6 DESIGN ROW (the research lane, docs/design/class-v6-rotating-family.md on the mirror, the commit after 206e81e1): load_index folds a product's low bits before the stride rotation so no era's R lands a biased bit on an address bit (a design row, not a draw and not a floor); the evidence lane D's 7 of 16 drawn eras at |z| 130 to 511 on address bit R or R+1 with the (c''') ratio blind to it; the chip row 1.6 percent of a hash's reads at f = 1/2 for one site and zero at f = 1; the cost 0 on every card (one xor-rotate on the address path); the known-failed test lane D's 7 of 16 reading 0 of 16 with the fold; the value-level bias test in layer 4 ordered after the fold as its guard; the F8 tail's largest-bucket bound restated in sigma against its own window's Poisson expectation. The 60x commits: the one-field commit on both lines (master 7be52d76 at 11:24, release-0.3.25 907fdaf4 at 11:23), the whole-file commits in their gates behind it (release cbbaa8c4 pushing, master's queued). CLASS V5 AT THE KNEE ON THE 5090 (the hash lane, run-ca3-pc1-v5lock-5090-20261008-b, 11:09 to 11:21 UK, the 5090 alone, the v5 kit's CUDA worker on the rotate-fold build 8f481459, 60 s rows, the cleared helper sequence; an hour ahead of main's 12:30 clock): the same genesis seed, class v4 against class v5: unlocked v4 135.82 MH/s at 458.3 W (0.296 MH/W), v5 135.90 at 474.3 W (0.287); at 1,300 MHz v4 125.92 at 294.0 W (0.428), v5 125.93 at 299.8 W (0.420); at 1,200 MHz v4 115.69 at 273.3 W (0.423), v5 115.87 at 278.6 W (0.416); the Devnet 3 epoch-0 v5 pack (another seed, the fingerprint 82b19cbde8557ea5 matched on every row): unlocked 136.94 at 494.4 W, 1,300 134.10 at 315.6 W (0.425), 1,200 128.51 at 302.2 W (0.425). THE READING: at the knee class v5 loses 0.0 percent of rate against class v4 and costs 2.0 percent in watts (1.9 percent per hash), under main's 2 percent line, so the v4 knee stands, the tiers table says the class v5 rows are within it, and the UI lane's knee note stays off (knee_loss_pct 0 on the 5090); the A4000's 17 percent is a capped card's number: the 5090 at 1,200 MHz holds v5 level with v4 too, so the loss appears only where the power cap, not the clock, is the limit. Per tier for the founder: a 5090 or 5080 owner on a knee lock loses nothing at the class v5 crossing; a power-capped card (a datacentre card at its cap) loses up to 17 percent until its cap is raised or its class re-tuned. The 5080's rows after the v6 packs job if wanted; the AMD grid live on PC 1 since 11:25 (24 points, about 32 minutes). LANE B'S FIRST READING, RELAYED BY MAIN (11:2x BST), WHICH CHANGES THE CHIP MODEL AND LEADS THE 20:00 SYNTHESIS: a 2 GiB SRAM full store on one N2 die (about USD 500 of silicon, an N2 project of USD 100 M to 500 M) reads 13x to 17x the 5090 per joule at zero shadow and 2.7x to 4.8x with the shadow at the measured k band; layer 2 (the dataset tracking chain state) moves its capex, not its joules; the custom HBM4E base die (2027 to 2028) 6.5x to 14x, untouched by the four layers; PIM structurally blind to dependent random reads; and the M5 Max at 3.1x the 5090 per joule is the honest denominator. MAIN'S ORDERS: (1) chip-model-v3 gains the SRAM-store row and the HBM4E base-die row with lane B's figures and their claimed or measured marks; (2) the synthesis states the per-joule edge against the SRAM store honestly (3x to 5x with the shadow) and against the M5 Max, and prices the one layer that answers it: a dataset floor that grows on a schedule faster than SRAM cost falls, with the cost to a 12 GB and a 16 GB GPU and to 16 GB unified Apple memory stated; (3) the served chip line ("2.1x per joule at the knee") is reviewed at 20:00 with the measured basis for each clause; no served text changes before the synthesis, and if the SRAM-store reading stands the line becomes the honest range with the project cost and the clock beside it. THE SHIPPER'S THREE READINGS (11:2x BST): (1) override-60x.json: every reader in the tree is the fast-time harness, the sims and CI; no daemon on the fleet loads it; the app manifest's consensus.override is a separate 16-key object carried from the live manifest and untouched by the cut; the live chain's object is the digest's (1b37cb9d on e0644958); the harness's file only, the cut stands. (2) The cut tip cbbaa8c4 on release-0.3.25 (907fdaf4 plus the steward's whole-file commit; the crate and packaging trees byte-identical to 907fdaf4's, whose crate gate read 305 + 35 + 8 at 11:24; override-json-check passing): amd-clock-25 e2962b89, tiers-25 d3d0704a, the Intel header, the tiers class-flip pair 081b3ba7, install-detach-25 52a34111 with its test fix, the node-source pin e0644958, the host bc8d4f79, the fast-time file; the Mac DMG on it afa7f527 (45,766,741 B, the node pair 556926b1/d2dfe966), staging. (3) The knee note off on the 5090 rows. The pin at 13:00 on e0644958 and the 13:40 provisional minute standing; the matrix on cbbaa8c4 and e0644958 the steward's by 12:30. LANE B'S FIRST CUT ON MASTER (34f63b3c at 11:25 UK, four hours and thirty-five minutes ahead of its 16:00 clock): docs/analysis/class-v6/hardware-future.md with the three findings and the k bands (with the research lane, into the synthesis's section 7a on counter-asic-4 at ad37a50c); lane B's four decisions in its section 7 with defaults (the draw bounds by 20:00 via the synthesis; the dataset schedule unchanged; the M5 Max as the reference joule; the clock unchanged); nothing built or benchmarked, gh untouched; the full report by 09:00 adds detail only, no k band moving. LANE A'S FIRST CUT ON MASTER (docs/analysis/class-v6/history.md, 300 lines, merge 4c58ad65 at 11:26 UK, three and a half hours ahead of its 15:00 clock; the full gate GREEN 73 checks; primary documents read from the PDFs: the Least Authority and Bob Rao audits, Kik, EIP-1057, the RandomX design and v2, Tromp's README, the Fudan Equihash solver, Percival's lookup-gap note): 21 chip rows by mechanism (what each chip specialised, the miss, the timeline, the v6 layer, closed or not, the per-joule number), the in-depth sections (Ethash, ProgPoW, RandomX, Cuckoo, Equihash, Scrypt and Argon2, the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows), the four layers against the history layer by layer, the tier consequences. THE HONEST VERDICT WITH THE NUMBER: the chip that stores the dataset (class C: every Ethash chip, the E3 at 1.0x, the Linzhi at 2.1x, the Jasminer X4 at 5.1x via DRAM hybrid-bonded onto a 40 nm logic die, the E9 Pro at 4.1x) is NOT closed by any of the four layers, every per-era draw and family epoch being firmware to it; v6 inherits 5.1x per joule on GDDR7 at zero premium (3.6x at the 5090's knee, 2.1x with the class v4 shadow at k = 1), USD 2.8 against 14.7 per MH/s; classes A, B, D's governance half and E are closed, mostly since v2 and v3. THE THREE LESSONS THAT BIND: (1) the stored-dataset chip is firmware-immune to every draw; only joules and memory growth move it; (2) automatic change beats the human fork only where it costs the chip a redesign, and the one such parameter is the memory: layer 2 as declared is not an anti-chip rate (a 32 GB board lasts 60 years at 0.5 GiB a year; the 8 GB card is out at year 12; the E3 the only chip a growth rule ever killed, 20 to 27 months after shipping, at the fleet's own 4 GB limit), so its floor and a per-tier ceiling are the numbers to fix, not the rate; (3) a steered address pattern is always found after launch unless the test lives in the acceptance rule, and every drawn parameter changes layer 4's null, so the census re-derives per era (2.2 s per candidate). CORRECTIONS TO THE 5 OCTOBER FILE: the Antminer X9 withdrawn May 2026 with zero units (not "July 2026 delivery"); RandomX v2 released 25 March 2026 with activation pending (not "no fork"); CryptoNight's secret chips at about 33 months, not 43; Vorick's "survives forks at under 5x" and "13 months for a startup" on no fetched page, marked unverified. Two asks with defaults: layer 2's ceiling (if no word by 20:00 the full report drafts it as GB per tier per year keyed to card-lifetime-2026-10-05.md, with the flag that a dataset tracking state literally outgrows every card inside a decade if state grows as Ethereum's did); the hardware file cross-cited, not repeated. The lane's web-search budget spent (200 of 200); further additions by direct fetch. LANE D'S STATE (11:2x BST by the Mac's clock; its own line read "11:5x"): the first cut committed on class-v6-family-gate at 55c0dc6a with the full gate running; the census at 640 random eras, 298 lossy-cap, 327 width-4 on build-1 and about 500 shape-64 on build-3, the two build-4 corners queued behind a full pool; the landing on the gate's GREEN, the measured coverage table in the 17:00 cut. THE SNAPSHOT DIGEST STAMP (the node lane, 11:2x BST; a wip on release-0.3.25-node under its suites since 10:28Z): every snapshot a node writes carries its consensus digest as a new last field (the day-streams field's fallback shape, so 0.3.24 files decode with no stamp); a node with its digest set refuses a snapshot stamped under another digest ("re-executing from genesis") and one with no stamp ("written by a node before 0.3.25"), the follower starting at genesis; the daemon sets the digest from its params; the tests known-failed first (another digest refused, an unstamped file refused, nothing loaded; a matching stamp resumes, the written file carries the stamp, a digest-less process resumes as before, the wire round-trips); if the suites read green the full gate set runs and it is in the pin at 13:00 BST. THE CONSEQUENCE FOR THE MOVE: every Devnet 3 node restarted on 0.3.25 re-executes from genesis (no file written before 0.3.25 carries a stamp), so the restart takes the chain's re-execution time, which a fresh 0.3.25 node on build-1 since 10:24Z measures now (about 30,000 chain blocks; the rate in the pin line). TWO READINGS BESIDE THE CAUSE: (a) build-1's three nodes differ at 26247 (node1 0x3f53a7b9, the seed 0x717e7dc8, the observer 0x4548c319), and the seed and node1 differ at block 0 already (0x275b0cce against 0x7e37a9fb), which the ba75bf6f file alone does not explain (both resumed their own files across the same restart; the seed also restarted at 02:00Z on 2720d8d2 from a 0.3.22 file); the fresh node's genesis root and its first divergence from each decide whether a second class (an older-object file on the seed, or the resume itself) is in play; (b) the fleet asked for the roots at 26247 and 15611 on hub-1's Devnet 3 node, dn3-g1 and every prover by 12:30 BST with each node's resume line. The loud status for a vetoed node (a veto counter, the last veto's line on the explorer's status, "state not fresh") on the same line if the suites leave time, else 0.3.26, the node lane's word at 12:30. MAIN'S WORD ON LANE A'S ASK (11:2x BST): the default stands (the GB-per-tier-per-year table keyed to the card-lifetime file, with the flag), and one schedule to price beside it so the 20:00 reading carries a decision: a dataset floor of 6 GiB at the v6 epoch (every 8 GB card keeps mining with its cache; the 6 GB 2060 tier drops), 10 GiB two years on (the 8 GB tier drops), 14 GiB at four years (12 GB drops; 16 GB and Apple 16 GB unified hold), each step by height like a class epoch, the schedule itself a consensus field, with the cost per tier stated as the year each falls off and the share of today's measured cards that is; against the chips: the hybrid-bonded DRAM chip sized at launch (the E3 class) dies at the first step it cannot carry, the SRAM store pays capex only, both said. Lane A's corrections to the 5 October file go into the record and the served texts tonight. MAIN'S WORD ON THE STAMP AND THE GENESIS CLASS (11:3x BST): the stamp rides the pin; the re-execution time goes in the pin line and the move plan per tier; the fleet staggers the restarts in thirds so the proving share never reads zero, and the hourly line says "re-executing" with the count until the last prover is back. The second class is a GATE, not a note: the seed and node1 differing at block 0 means one of them runs a different execution genesis, and a hub node on a wrong genesis is worse than any snapshot drift; the pin is not named until the node lane says which file each of build-1's three nodes and hub-1 loaded at genesis, which root is the network's (the fleet's roots at 26247 and 15611 decide it), and the wrong one is corrected or re-walked; if that is not read by 13:00 the pin waits inside the 14:53 ceiling and the shipper slides by its authority. The vetoed-node status rides 0.3.25 if green, else 0.3.26. THE 60x FILE LANDED (the CI steward, 11:31 UK, ahead of 11:45): release-0.3.25 cbbaa8c4 (the whole 81-key file on 907fdaf4, the hook gate GREEN 60) and master e295c0d5 (the same file, the gate GREEN 73); known-failed to green on record: core RED on the one test on all four boxes before, core GREEN on the fixed pair on build-1, build-3 and build-4 after, build-2's re-run running; the full matrix by 12:30. A NEW GATE ON THE PIN (main, 11:3x BST, from the reference-apps lane's read): node1-dn3 and the re-executed observer diverge from chain block 26294 at DAA 60,578, the 10:05 move minute; node1 executed a block the selected chain later dropped and never unwound it, so its numbering runs one high and its state and records diverge; that is the drift class and the likely cause of last night's proving collapse after a move; the stamp does not cure it. The node lane's order: a known-failed reorg test under the exec follower, the fix on release-0.3.25-node if green by 13:30, else the move with the mitigation (every node re-executes from genesis after the minute, the vetoed-node status loud) and the fix as 0.3.26 tonight; plus the roots census to count stale nodes for the fleet's re-walk before the minute; the shipper's slide authority covers the pin inside 14:53; if the fix needs past 14:53, the floor re-cuts from the next minute by the same authority; the explorer lane reads block numbers from the observer node only (the chain the certificates follow) until the fix is live. THE FAMILY GATE'S 12:00 COVERAGE (lane D, 11:3x BST by the Mac's clock, ahead of its clock): 4,900 drawn eras through the per-era tests on three boxes (build-1 random 1,444 and lossy cap 663 at 10 core-seconds per era; build-3 shape 64 at 2,162; build-4's two lossy corners queued behind a full pool); the full gate on the first cut GREEN (73 checks, 381 s), the landing on one re-gate after a merge conflict on export-exclude.txt with the research lane's line (resolved, both kept). THE WORST ERA PER TEST: (1) THE EXHAUSTION BOUND BREAKS AT THE LOSSY CORNER: with or, mul and mulhi all at +4 points (30 of 75 lossy against the table's 18), r per candidate is 0.956 (the table's 0.681) and 8 of 663 eras EXHAUST the 256-attempt cap (mean attempt 18.6, max 252), so 1.2 percent of epochs at that corner would take the last-resort program, which adv-accept-3 showed fails rule (a) in 9 percent of seeds; B = 4 with the lossy ops free to rise is therefore outside the band; the random stratum at B = 4 (every weight drawn, lossy ones included) reads r = 0.718, max attempt 107 and 0 exhaustions in 1,444, but 107 attempts is 4x the shipped max of 28; the ring-A rule the cut carries: the sum or + mul + mulhi at most the table's 18 plus B, so r stays under 0.85 (r^256 under 1e-18); the default by 17:00: B = 4 on the injecting families only, the lossy families capped at their base. (2) THE ERA-STRIDE CLASS AT THE BIT LEVEL ON THOUSANDS OF ERAS: 52 to 58 percent of accepted programs in EVERY stratum carry one site whose address bit R (or R+1, R+2) is biased at over 6 sigma at 2^20, 33 to 40 percent at over 100 sigma, the worst z 1,024 at bit 7 of a site under R = 7 (a product's bit 0 at P = 1/4 landing at bit R): adv-cache-2's mechanism at half the family's epochs on programs (c''') passes (min ratios 0.9950 to 1.0000); the chip price per site about 1.6 percent of a hash's reads at f = 1/2 against the partial-store curve's 1.26x ops cost: the f = 1 verdict stands, the "uniform random reads" sentence does not; the catch structural (the index fold in load_index before the rotation, the class v6 design row), not a floor. (3) The largest-256-item-bucket excess: clean full-window sites +4.4 sigma; the worst eras +94 to +128 sigma at one site (the F8 tail's quarter-bit class at scale, the same mechanism: the bucket at the biased bit); the bound in sigma from the clean spread in the 17:00 cut. (4) The (c''') refuse rate per stratum: random 2.56 percent of candidates, shape 64 3.41, lossy 0.42 (the lossy rejections earlier at (a')); 0 accepted programs under 0.995 anywhere. (5) VOID and rerun: the width-4 stratum ran at width 1 (the era's one-entry allowed set redrawing to the base's width; fixed, the harness rebuilt, restarted at 11:5x with its own label space); the first corner strata sharing the random stratum's label space coincide with its draw a third of the time; the reruns use per-stratum labels; both stated in the cut. Coverage by 17:00 at about 1,000 eras per hour per 16 cores: random 10,000, shape 64 3,000, lossy cap 3,000, width 4 3,000 plus the two build-4 corners; the rule-of-three line for the random stratum at 10,000 eras a failing fraction under 3e-4 at 95 percent for every ring-B test. THE V6 COST ROWS (the hash lane, 11:4x BST by the Mac's clock, its own line reading "12:4x"; four hours ahead of 16:00): with the research lane at scratch v4/ca4-v6-cost-rows.md, every row labelled measured or modelled; the layer-2 headlines: VRAM 3.2, 5.4 and 9.9 GiB at the floor, 2x and 4x; a 12 GB card falls off at about 9.5 GiB (year 15), a 16 GB GPU at 13.5 GiB (year 23), a 16 GB unified Mac at 8 GiB (year 12), the 5090 at 29 GiB (year 54); the DRAM-read cost per hash size-independent (the 5090's 1.11 microjoules of 2.29), so the layer moves capex not joules, and the card rows allow a floor of 4 GiB in year 1 and 8 GiB by year 4 without retiring a 12 GB card (main's schedule of 6, 10 and 14 GiB at the epoch, two and four years sits above that: the 12 GB tier drops at 14 GiB, the 16 GB holds); the measured size rows (the v3 pack at 2, 4 and 8 GiB on the 5090, unlocked and at 1,300) ride the v6 packs job after the AMD grid. The AMD grid: the first run refused in 2 s at no_tune_line (the old installed exe, as designed); the rebuilt exe on PC 1 by the update-return lane's fetch at 11:33, the rerun from amd-clock-25 572c3ee0 live since 11:39 (about 32 minutes, the rows about 12:15). The class key on the mirror (ember-tiers-25 0a838072 in tiers-class-25 081b3ba7, with the shipper since 11:13, inside the 12:30 reading). The Arc read waits on the shipper's PC 2 take; the 12:30 default "no Arc read" stands unless it starts before. THE DRIFT CLASS READ FROM THE LOG (the node lane, 11:4x BST): at 09:42:09Z node1-dn3 accepted 0x6aa6 (DAA 60,578) and at 09:42:10Z 0xb708 (the same DAA and blue score 60,265, both children of 0x0fed at 26293: a tie at one height); its follower executed 0x6aa6 as chain block 26294 (28 transactions) and 1.1 s later 0xb708 as 26295 (the same 28 skipped as already included), with no reorg line between; every consensus view now (the seed, node1 itself, the observer) has 0xb708 as the chain block with the selected parent 0x0fed and 0x6aa6 off the chain, so node1's records hold an orphan at 26294 and number everything after it one high, and its state root diverged from there (the observer, re-executed from genesis, agrees with node1 to 26293). THE GAP: the 0.3.22 continuity rules (ledger N15) check the first appended block's selected parent against the tip at append time and scan the whole record set against the DAG's selected parents ONCE per state generation (a restart or a loaded snapshot); a break landing after that scan, as this one did ten minutes after node1's restart, is never looked for again until the next restart; the fleet's +2 on four shared-devnet boxes is the same gap. THE FIX on release-0.3.25-node (a wip under the exec suite since 10:41Z): the self-check runs every 30 s over the ring (the last 2,000 records) against the DAG's selected parents and in full on a generation change, a break handing the records above it to the reorg unwind (the existing branch restoring the ring state at the fork and re-walking); the test known-failed first on node1's exact shape; on the same commit the snapshot digest stamp (exec 51 of 51 green on its wip) and the vetoed-node status (vetoes counted on the status with the last veto's line, stateFresh false while any stands, on igneum_getNodeInfo and the status RPC); the exec suite's green about 11:46 BST, then the named commit, the full gate set, both canaries (the digest 1b37cb9d unchanged: nothing consensus) and the fast-time pair, the gated tip by about 12:30, inside 13:30. What the fix does not do: name why the tie-break flipped under node1 at 09:42Z (its DAG now reads 0xb708's parent as 0x0fed and the path at the time must have read otherwise; the second "PoW accepted 0xb708" line 0.4 s after the append says the block was processed twice), a reading for the record after the pin. The fresh 0.3.24-object node on build-1 past IBD and executing from genesis; its root at 26247, its rate and its memory peak in the pin line. MAIN'S WORD AT 11:4x BST: (1) lane D's band default stands (B = 4 on the injecting families only, or, mul and mulhi at base, the ring-A lossy-sum rule), and the index fold before the rotation with the bias test as its guard is layer 1's rule; (2) the served sentence "uniform random reads" is corrected today, not at the review: the audit lane rewrites it to the measured statement (reads spread over the whole dataset; a bit-level bias at one site appears in about half of epochs; it prices about 1.6 percent of reads to a chip storing half the dataset and nothing to a full store; the next class folds it out), through the gate and the master-only deploy, with the ledger row; (3) layer 2's table splits Apple by memory size (16 GB unified at its 8 GiB limit, 32 GB and 64 GB Macs holding every step), the M5 Max being the honest best per joule and the Mac tier a large audience; the schedule decision at 20:00 is the founder's with that column in front of him. THE EXPLORER'S SOURCE (the explorer lane, 11:4x BST): it reads one endpoint and always has, the Devnet 3 observer node on build-1 (the execution RPC on loopback 26850 through tools/observer/explorer-indexer.mjs, the observer's own dn3_ tables on 28650); it has never read node1-dn3, so there was no switch; the indexer on 26850 since 10:04 UTC with a full refill from genesis at 10:33 UTC after the root equality read at block 26,247; the pages now name the observer node as the one source, the chain the certificates follow (on explorer-dn3, in the gate; the merge and deploy follow). THE GENESIS GATE'S ANSWER ON build-1 (the shipper, 11:43 BST): the seed was the odd node (its block 0 from the 0.3.22 binary; the rule change for the node lane's record), re-walked from genesis at 11:35:30 by the shipper's hand (the evm moved aside, the same binary and flags, the kept datadir) and reading population A's roots at 11:43:00 (0x47983bd9 at 15611, 0x3f53a7b9 at 26247, head 26,478). THE MEASURED RE-EXECUTION: 26,478 chain blocks in 7 minutes 30 seconds (about 59 a second over the walk; 100 at the start, 30 past 15,000), RSS 5.5 GB; so the move plan's per-tier line: a prover's node is back about 8 to 10 minutes after its restart on 0.3.25 (30,000 blocks at the minute), a Mac or HiveOS app node the same at its update hour, miners unaffected; with the hub and the seed at the minute and the provers in two thirds at +0 and +25, the proving share never reads zero and the last prover is back about 35 minutes after the minute. The node lane's gated tip (the ring check, the stamp and the vetoed-node status in one commit, the digest 1b37cb9d unchanged) by 12:30; the pin after it and the fleet's census; the minute about 14:10 at the earliest if the fix rides, inside 14:53. LANE A'S SCHEDULE SECTION (history.md 4.2a, master 59963461 at 11:45 UK, five hours ahead of its 17:00 clock; three landings today: 4c58ad65, b645762d with the synthesis lane's six items folded in, 59963461): ONE FLAG on main's schedule with the number: under the standing budget rule (the working set under 6 GB on an 8 GB card, the 75 percent reading) a 6 GiB floor does not fit the 8 GB tier (6,398 to 6,744 MiB, 78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent); 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2 (not the 8 GB tier alone); 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above. The schedule that drops the tiers in the order main named, priced beside it: 5.5 GiB at the v6 epoch (6 GB falls, 3 percent of the 32 measured consumer cards), 8 GiB at two years (8 GB falls, 22 percent, with the 10 GB RTX 3080 and Apple 16 GB; 12 GB holds at 69 to 72 percent), 11 GiB at four years (12 GB falls, 22 percent; 16 GB holds at 70 to 73 percent); 24 GB and above hold throughout. Against the chips: the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 of GDDR7 on a USD 470 part); the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. So the schedule is a fleet-retirement rule with a USD 0 to 160 chip tax, killing only a chip whose maker ignores the field. The default by 20:00: the full report carries both schedules and recommends 5.5 GiB as the floor that keeps the 8 GB tier inside the rule. Owed: the fleet's hashrate-weighted card census (the shares are by count of the bench table's 32 measured consumer cards). LANE A'S CORRECTIONS SERVED (the site audit lane, master 2119e4f3 at 11:46 BST, gate green on 78166c6c, commit 14ad1a33; seven hours ahead of 19:00): every served "no chip shipped" and "seven years without a shipped chip" sentence (the litepaper's precedents row, the chip-model paragraph, the vs RandomX lead and its track-record row, the limits section; /claims and /randomx following) now carries the Antminer X5 (September 2023, 1.46x per joule over a desktop CPU, silicon believed mining privately from about 2021) and RandomX v2 released 25 March 2026 with its mainnet activation pending; the ledger rows X34 and C2 corrected with lane A's file cited, the pins moved, the public ledger and page regenerated; the X9 sentence already matched lane A's row (sales opened 26 December 2025, shipping scheduled July 2026, withdrawn mid-May with zero units), the precedents and track-record cells now reading "withdrawn in May 2026 with zero units"; the 43-month, 13-month and Vorick figures on no served page; the commit also carrying main's governance line beside the class v5 sentence and six class v4 watts rows; the "random reads" correction with its AP-F8 row next by 13:30; the build-server lane deploys on main's word. LANE C'S FIRST CUT ON MASTER (docs/analysis/class-v6/invention.md at a9f03598, 11:48 BST by the Mac's clock, five hours ahead of 17:00, with the census script under tools/attack/v6-invention/ and its two TSVs): build-1 ran the per-load acceptance census (11 forms x 256 seeds, twice: no era and drawn eras, 80 s each on 48 leased cores) and the verifier benches; the two packs exported and with the hash lane for PC 1; the second candidate (warp-uniform block selection) has no pack form without a generator change, which the no-code rule holds this week, so its row stays modelled. A CORRECTION TO THE CA4 FILE'S VERDICT, FOUND BY LANE C: the counter-asic-4 crate's per-load acceptance (BiasedIndexBit) counts the era window's fixed top index bits 26 and 27 as biased, so under any drawn era it refuses every per-load program (0 of 256 on every form today, 5,536 of 7,862 bias rejections naming those two bits); 20.2a-close's "1.4 percent accepted, 42 of 64 seeds exhaust" (the per-load class's death at 00:0x) was read across drawn eras and so measured the instrument on most rows; on the no-era census the sound form (16 x 256 x 1) reads 0.927 rejection per candidate and 234 of 256 seeds accepted, the iterated 16 x 27 form 0.989 and stays dead; the one-line instrument fix (skip bits at or above 28 minus the site's k_off) is a research-crate change, made today as a research-only change behind the pack by the coordinator's order, and the sound per-load form's verdict is REOPENED as a measured candidate (its energy and rate rows on the 5090 through the hash lane; chip-model-v3 5.11's note on the per-load closure to be re-worded when the re-read lands). THE REOPENING APPLIED (the research lane, 11:5x BST): the reopened wording in counter-asic-4-research.md (20.2a-close and rank 4), class-v6-rotating-family.md (section 7c as layer 5) and chip-model-v3.md 5.11's note, with one precision: the 22:5x UTC census ran the bare class with no era, so its 0.986 is the iterated form's own no-era figure (lane C's 0.989 agrees the 16 x 27 form is dead); the artefact in any drawn-era read before the fix; the fix already on counter-asic-4 as of 10:5x UTC (BiasedIndexBit judging only the bits inside each site's window mask through verify::window, per site), uncommitted until the suite's line lands (the box-2 slot since 10:31Z), so lane C re-reads on that branch once pushed, not making the change twice; the chip-model 5.12 rows (the SRAM store, the base die, PIM's blindness, the M5 Max denominator) in the same tree, riding the same commit before 15:00. A MIRROR NOTE (11:52 BST): lane B read silent 25 minutes by the mirror; its first cut landed at 11:25 and its next clock is the full report by 09:00 tomorrow, so the silence is its finished state, not a fault; the mirror now skips lanes whose clocks are done. A MASTER-ONLY DEPLOY AT 11:53 BST (the build-server lane, on main's own builder-programme landing d86ea00a: /build, /grants, /faucet, /swap asserted; the served sha a9f03598, master's tip; the checks ok; 38 miners rows): it carried the audit lane's 2119e4f3 (the RandomX history correction with the Antminer X5 and RandomX v2, the governance line, the first six class v4 watts rows), which main ordered served tonight and the audit lane cleared for the next scheduled deploy; the "random reads" sentences not yet corrected as served; the coordinator's trigger stands for the 13:30 correction. LANE C'S KNOWN-FAILED TEST FOR THE INSTRUMENT (11:5x BST): igneum-pow/tests/v6_window_bits.rs, the sound form (16 x 256 x 1) accepting on at least 4 of 8 seeds under drawn eras 0 to 7 with 0 window-bit refusals (0 of 8 before the fix), the no-era bit-0 refusal on seed 3 standing; 2 passed, 0 failed on build-1 against a local overlay of the same nine lines, the overlay reverted, the test file an offer to the research lane's suite; the re-read on the research lane's commit by 15:00; meanwhile build-1 runs the lane's uniformity read at 2^20 nonces on 64 seeds for the two sound per-load forms and the class v4 shape (the F8-form top-0.1-percent item share against a uniform control, the per-site distinct ratio) on a harness over the crate's trace_load_indices (the master F8 tool mirroring class v4's execution order), about 20 minutes on 24 leased cores. THE RANDOM-READS CORRECTION ON MASTER (the site audit lane, bf54b08d at 11:54 BST, gate green on db038279; an hour and a half ahead of 13:30): the litepaper's lead reads "dependent reads spread over a multi-gigabyte dataset that changes daily", the table row "the dependent reads are", the "chain of random reads into a table too big for a chip to carry" sentence standing with the measured clause after it (the 0.995 floor on every accepted program over 4,900 drawn eras; about half of epochs with one load site biased at the era's stride rotation bit; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold before the rotation in the next class); evidence row 18 with lane D's family-gate.md and adv-cache-2's section 2.3 as sources; the ledger row AP-F8-7 (AP-F8-6 taken on class-v5): "Open, priced: 1.6 percent at f = 1/2, nothing at f = 1; the served sentence corrected 8 October 2026", the disposition class v6 layer 1's fold with the bias test as guard; the public ledger and page regenerated; no pinned sentence touched; the fud-ledger's quoted history standing; the build-server lane deploys bf54b08d. BUILD-1 AT 11:55 BST (the coordinator's own read): load 107.6 on 96 cores; the lease table: the family gate 32 cores (the random stratum, 10,000 seeds), 16 (the lossy cap, 3,000), 16 (width 4, 3,000, restarted), lane C's uniformity read 24 of 48; 88 of 96 cores held, none waiting, no pre-emptions in the last ten minutes. THE 11:55 BST LOAD LINE (the build-server lane, all four boxes at the minute): build-1 (96 threads) load 113.7, the pool holding 32 for the family gate's random stratum plus 16 and 16 for its corners and 24 for lane C's uniformity read (88 of 96 held), the release and v5 builds outside the pool; build-2 (96) load 81.3, the pool holding 32 for the attack-pass F8 census (the thirds); build-3 (32) load 25.1, the pool holding 16 for the family gate's lossy-base stratum and 2 for the hash lane's x16 rows; build-4 (96) load 89.0, the pool holding 4 x 8 for the attack-pass F9 chunks 0 to 3 plus F1's 40 and F4 done; no release-class waiter on any box; the builders loaded, none idle. The founder's order at 11:2x is met at the minute: every box above 80 percent of its threads bar build-3 at 78 percent of 32, which the two queued build-4 corners and the next v6 pack take. The build-server lane's deploy of bf54b08d served at 11:56 BST, two minutes after the landing: the post-deploy checks ok (api/live igneum-devnet-3, the index strings, the legal line, 38 miners rows, the four builder pages 200), and the litepaper's lead sentence read back from the served page carries the corrected wording (wide parallel integer maths, warp shuffles, dependent reads spread over a multi-gigabyte dataset that changes daily, the program waiting on memory latency); the old "random reads over a multi-gigabyte" is absent. The CI steward's 0.3.25 pre-pin matrix with the shipper at 11:59 BST, 31 minutes inside its 12:30 clock: seven suites on four boxes, every cell green but the one known core red on the pair before the fast-time file (the same single test on all four boxes, the six missing keys), and core green on the fixed tree on build-1, build-3 and build-4 (170 passed each); build-2's re-run queued behind three lanes' suites and lands on its own; counts identical across boxes (pow 113, app 346, exec 49, miner 29, p2p-flows 38, consensus 134); the Mac's full gate on the 9b93e649 tree GREEN, 60 checks; build-3 and build-4 toolchains read as build-1. The matrix worktree sits at cbbaa8c4 (81 keys, igneum-pow identical to the pin's tree); the second matrix waits on the node lane's gated tip (by 12:30), the line by 13:15. The RX 9070 XT's first measured grid on the AMD knob (job run-ca3-pc1-amd-grid-9070-20261008-b on PC 1, 11:40 to 12:10 BST, 24 of 24 rows ok, the card reset to factory at the end): the rate flat at 18.93 to 18.98 MH/s on every point, the knob moving watts only; stock 3,292 MHz 195.8 W (0.097 MH/W); the clock offset alone to 2,924 MHz 159.2 W at -400 (0.119), clamping about 2,920 at -500; the power limit alone does nothing until -30 (184.4 W); best -500 MHz with -30 percent: 2,921 MHz, 149.3 W, 18.96 MH/s, 0.127 MH/W, a 24 percent saving at the same rate. Per tier: a 16 GB AMD home card gains a quarter of its electricity cost at no rate loss once 0.3.25's knob ships; it stays 3.5x behind the 5090's 0.43 MH/W at the lock, so last night's AMD reading stands (the read path, not the clock, is AMD's cost). The v6 packs job live on the 5090 since 12:11 BST (eleven packs including the three dataset sizes, unlocked and at 1,300, about 40 minutes). The Arc re-read not started on PC 2 (the shipper's take holds the box); at 12:30 the default "no Arc read" stands, the pairing 1c420786. The Ember priors committed on ember-tiers-25 at 1e966170 with known-failed tests, its suite queued behind build-2's slots since 11:46; the sha to the UI lane and the shipper on its green; if not run by 12:45 the suite moves to build-1 through a lease. Two master-only deploys from the builder stream, checks ok (38 miners rows, the six asserted pages 200): 0c64b24f at 12:07 BST, the explorer landing (explorer.igneum.network, /proving, /tx/, the dn3_ APIs reading "Devnet 3"; the explorer indexer unit moved to the master checkout and restarted, reading the observer only as main set), and 3355c098 at 12:16 BST (site/vercel.json only: the explorer host's root 307 to /explorer, read live). No chip text changed in either. Still in the stream: the reference-apps lane's /light, /receipt and /oracle (its gate since 11:50, the 13:00 default) and the audit lane's watts rows 11 and 12. A third master-only deploy from the builder stream: f0418c8d at 12:19 BST (main's word via the explorer lane: EXPLORER_EVM_RPC on the production env, so /api/explorer balances read live from rpc.devnet.igneum.network; checks ok, 38 miners rows, six pages); the public RPC's allow list tightened the same minute to igneum_get* (the two igneum_submit* writes refused), reported to main. No chip text changed. The /build lane DONE with every clock beaten: landed on master as d86ea00a (11:47 BST), deployed as a9f03598 at 11:53; /build, /grants, /faucet (the Devnet 3 faucet page) and /swap serving in the nav's Build group; faucet.igneum.network/api/faucet live on build-1 behind Caddy, funded 2,000 IGN by the fleet lane (11:01 BST), the first drip 11:17 BST, 1,989.99 IGN left; the walkthrough PASS through the public RPC and faucet (a contract deployed at block 27055, 24 s end to end, Foundry 1.8.5, docs/build/first-contract.md); the RPC list read from the node in docs/build/rpc.md; the audit's four wording lines in. One open fact to the fleet lane: build-1's Devnet 3 seed at 27810 re-executing from genesis while the faucet reads the observer's 26850 (the re-execution class measured at 7 min 30 s this morning). Lane D's coverage at 12:2x BST, every launched stratum complete (the runs beat the 1,000-per-hour estimate once the pools freed): random 10,000 eras (0 exhausted), lossy cap 3,000 (37 at the 256 cap, 1.2 percent), width 4 at the fixed harness 3,000 (0), width 4 plus lossy cap 2,000 (24, 1.2 percent), shape 64 3,000 (0), the lossy-base band (B = 4 on the injecting families, or/mul/mulhi never raised) 3,000 (0); 24,000 drawn eras through the per-era ring-B tests on build-1 and build-3; build-4's shape-64-lossy and shape-256 strata still queued behind the attack pass's F9 chunks and not needed for the cut. The exhaustion finding confirmed at scale: 61 of 5,000 eras at the lossy corner reach the last resort against 0 of 19,000 everywhere else, so the band rule (lossy families capped at their base) stands on measured rows. The 17:00 clock holds; the cut (coverage table, per-axis table, union-bound arithmetic, harness patch series) likely lands by 14:30 BST. The node lane's gated tip missed its 12:30 clock: the combined wip (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the reorg-unwind fix on the same commit) sat in build-2's queue from 11:41 BST at normal priority behind a Counter ASIC 4 suite holding a slot since 11:31, found at 12:21 and moved to build-1 at gate priority; the exec suite about 12:25, the named commit on green, the full gate set (build and consensus at gate priority, five suites, both canaries, digest 1b37cb9d unchanged) about 12:50, the fast-time pair about 13:05, inside the 13:30 clock. The coordinator's default revised and taken by the lane and the steward: the second matrix starts on the named commit the minute its sha exists; no sha by 12:50 and the matrix runs on e0644958, the stamp and vetoed status slide to 0.3.26. The pin reads about 13:15 to 13:30 rather than 13:00; the minute about 14:10 holds if the fix rides; reported to main at 12:29. The seed's re-walk read equal to population A at 11:43 BST (0x47983bd9 at 15611, 0x3f53a7b9 at 26247; 26,478 blocks in 7 min 30 s, about 59 a second, RSS 5.49 GB); the fresh node on build-1 executing from genesis since 11:42:34 at about 100 a second at the start, its roots to follow. The lesson for the record: a release gate is dispatched at gate priority or it waits behind research suites; the node lane's wips were not. Main's correction at 12:3x BST on the fleet default: the 10:12 FETCHED count is not a census of state. If the stamp rides the pin, every node re-executes from genesis at the minute and the census is not a gate; if the stamp slides to 0.3.26, the census (block 26294's hash and the 26247 root on every prover) is a gate and the stale nodes re-walk before the minute. The fleet lane silent since 11:31: a one-shot at 12:36 starts a fresh fleet-move lane from the fleet root to take the census, the re-walks, the stagger and the pullers if it has not answered by then; the old lane keeps the hold and the hourly line. The 9070 XT reading goes to the audit lane for its row. Build-2's queued cell landed at 12:24 BST: core GREEN on the fixed tree (177 passed), so the first 0.3.25 matrix is green on every suite on all four boxes. The steward's gate-priority stream for the second matrix written (every suite at gate priority, its own results file), waiting on the node lane's sha with the 12:50 fallback armed; the line by 13:15. The AMD knob closed for the cut before 12:30: the 9070 XT grid's rows in and the efficient point in EFFICIENT_W as 149 W (both floors: clock offset -500 at about 2,920 MHz where ADLX clamps, power limit -30; 149.3 W at 18.96 MH/s, 0.127 MH/W, 24 percent under stock at the same rate); the rate flat over the whole ladder, so the knob is a watts lever only and the knee rule reaches the floor; amd-clock-25's gated tip 1be99aa0 (full gate GREEN 60, suite 298 green) with the shipper as the cut tip, the release section reading measured. The 5090 comparison carries two denominators, both real: 0.43 MH/W at the v4 1,200 MHz lock (133.8 MH/s at 305 W), 0.58 to 0.60 at the 1,300 knee (134.6 at 223 W); the 9070 XT at its floors is 3.5x behind the first and about a fifth of the second; a served row names its point. The Arc default taken at 12:30 BST: no B580 re-read reached the v5 lane, so the pairing line went to the shipper as the FREEZE 1c420786 (0.3.24's, as published) with the kit zip 65b47211 (packs-ca3-v5-20261008T085619Z.zip; its packs, ids and 82b19cbde8557ea5 byte-identical to 1c420786's by the packs test on both trees) and the Intel worker held out; 8f481459 (gate 73 GREEN, suite green, the Intel fix in) stands behind it and becomes the pairing with the Intel kit the minute an equal Arc read lands, with the page's Intel row moved. Nothing else of the v5 lane's in the cut. The shipper at 12:33 BST: (1) the 0.3.25 app tip is 89e83df2 (cbbaa8c4 plus amd-clock-25's gated tip 1be99aa0: the 9070 XT's efficient point 149 W at 18.96 MH/s in the ceiling table, the grid playbook; crate gate GREEN 12:28, 305+35+8, inside the 12:30 app window); the second matrix uses it with the node lane's sha. (2) On the node lane's hint, build-1's Devnet 3 seed and node1-dn3 were found dead since 12:06 and 11:54 BST (logs ending mid-line, no panic, no OOM; the observer and the fresh node lived): the network's seed was down 24 minutes; both restarted at 12:30 on their kept datadirs (the seed resumed its clean re-walk snapshot, node1-dn3 re-walking from genesis). Two reads before the pin: the build-server lane by 12:50 on whether any build-1 run kills igneumd by name (a cleanup that does so reaches the seed at the minute); the node lane by 13:00 on whether the line can die silently under the finality route flood the seed's log shows (a million drops on one peer). (3) The pairing the freeze 1c420786, kit 65b47211, the Intel kit out (PC 2 dark, no Arc read today); the genesis class closed on the fresh node's roots; the pin after the node lane's gate set, the matrix and the census; the minute inside 14:53. The hash lane at 12:4x BST: (1) the Ember search priors on the mirror as ember-tiers-25 1e966170, app suite green (307 + 35 + 8), with the UI lane and the shipper; the cut default stated to the shipper (in by the 13:00 pin or 0.3.26). (2) The v6 packs job on the 5090 (since 12:13): the four packs made on the box or pinned ran PASS unlocked (mx8-genesis 137.65 MH/s at 312.2 W; mx8_sh256x27 137.62 at 464.6; the invention lane's mx8_shl4096x1 135.99 at 428.6; mx8_shl2304x3 135.85 at 483.6; the 1,300 rows follow); the seven exported on the Mac this morning (today's x8 and x16, the two re-weighted, the three dataset sizes) were refused by the worker's seed check in 0 s ("IGNEUM_SEEDW_INIT is not attempt 0 of the epoch seed"): the string-seed export form derives different seed words from the byte-seed form the pinned packs use; re-exported in the byte form (the x8 reproduces the pinned id 73bcbfe8 and seed words exactly; the three sizes too; the x16 pair and the two re-weighted packs on generator 2 differing only in the era, the multiplier or the weight table); kit b and one more PC 1 job of those seven follow the running job's close, about 13:00 to 13:45, rows to the research lane, the invention lane and the coordinator. The invention lane's reading so far: the sound per-load form at class v4's instruction count (shl2304x3, 55,296 shadow ops) costs 483.6 W against sh256x27's 464.6 W unlocked, 19 W more, not under; the one-pass form (shl4096x1, 32,768 ops) 428.6 W; the lock rows decide the per-load candidate's GPU side. The export-form lesson for the record: packs for the worker are exported in the byte-seed form, never the string-seed form. Main's load order at 12:5x BST: lane D's two remaining strata (shape-64-lossy, shape-256) move from build-4's queue (behind the attack pass's pool) to build-3, idle after lane D's strata; build-3 kept fed with lane C's packs and the family census's next corners; nothing new on build-1 (load 142) until the pin is named, its gates at gate priority. Sent to lanes D and C with the 13:05 default. The node lane's two readings at 12:4x BST on the combined tip: (1) the build-1 deaths were the OOM killer (the build-server lane read the kernel ring: the seed at 44.6 GB anon-rss at 12:06:07 BST, node1 the same class at 11:54, two 31 GB attack binaries beside them); what grows is the proof pool's in-memory proof map: since the late-join rule (0.3.17) every proof a node receives is held by hash in memory and never removed (the entries leave the 600-block record window and the on-disk archive drops below the pruning point, the map did not); about 1.2 MB a proof, 14,107 proofs on the observer after a day (17 GB on disk, 13.6 GB RSS), the seed at 128 inpeers took the relays fastest; older than 7bd2940f; the fix (a proof leaves the map and the verdict cache with its record at the window's end unless another live entry names it; carried proofs served from the archive; known-failed test) on the tip under its exec suite at gate priority since 12:35:55. (2) The ring check's known-failed test on node1's shape green (exec 53 of 53 at 12:34:53 before the pruning went in). The named commit (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the proof-map window, over 7bd2940f's re-announce and keygen and the ceiling switch) follows the exec line about 12:40, inside the 12:50 fallback; the full gate set at gate priority on both boxes, both canaries (digest 1b37cb9d unchanged) and the fast-time pair after it. The fleet's census (12:31 BST): 36 nodes on population A, the network's genesis root 0x7e37a9fb; 21 stale nodes, each with a genesis root of its own, re-walking from 12:35 in thirds; dn3-g1 died a third time at 11:55:47 (the same OOM class on a rented box the likely reading; the fleet's hourly RSS per node with a restart above 32 GB is the guard until every node is on the tip). Lane D on main's order, done 12:36 BST: build-4's two entries cancelled before running; build-3 carries four strata on the fg6 harness (42f2c77f), 8 cores each under class measure: shape256 (3,000) and w4lossybase (3,000) running, shape64lossy (2,000) and w4shape64 (3,000) queued behind them on the 24-core pool; the lossy band at B = 4 across the injecting families is the complete lossy-base stratum (3,000 eras, 0 exhausted, r = 0.595). Build-1's queued attack-f8 rebuild chain cancelled (the point-B live census moves to build-3); what remains there started before the order (four lossy-share strata at +1 to +4 points, 16 cores each, about 900 of 3,000 eras; the point-A live census at 2^24 on 32 cores). The 17:00 cut committed at 2a595e1b with the 24,000-era coverage, its gate re-running. A shared-Mac fault class found at 12:3x to 12:4x BST: the class-v5 lane's shell command ran pkill -f "tools/ci/pre-push.sh" before its own gate, which killed every lane's gate on the Mac: the record's merge gate three times, the invention lane's landing twice (d6955381), the family gate's once (exit 144). The kill-by-name class the 6 October rule bans in scripts (kill-by-name-check.sh), applied by hand on a command line. The word to the lane: kill only your own gate by its pid; gates on the Mac do not share a lock. Reported to main. The research lane's commit 0ab27582 on counter-asic-4 (the mirror, 12:4x BST, ahead of the 15:00 clock; the crate suite green on the committed tree, 116 passed, 0 failed, build-2 12:38, master's new derivation test among them). It carries: (1) chip-model-v3.md section 5.12, the two chips with lane B's figures and marks (the 2 GiB SRAM store on one N2 reticle: 17x at zero shadow, 8x to 30x on the read band, 2.7x at k = 1 and 4.8x at k = 0.5 with the class v4 shadow, 3.7x and 2.0x at the card's whole shadow, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M and 18 to 24 months, a break-even cap of about USD 330 M to 1.7 B on the mission lane's model; layer 2 moving its capex, two dies at 4 GiB 15x and four at 8 GiB 13x; the custom HBM4E base die 6.5x to 14x untouched by the four layers; PIM structurally blind, 1.6 percent of reads in-bank at 2 GiB; the M5 Max at 0.78 microjoules the honest denominator, 3.1x the 5090) and 5.11's per-load note in the reopened wording; (2) the merge of master (the sub-version 3 line, the derivation recorder, the re-exported packs) and the per-load bias test's fix (judging only the bits inside each site's window mask; lane C re-reads on this id); (3) the class v6 document through section 9: the lead on the SRAM store, the per-tier schedule table with lane A's checked steps (6 GiB does not fit the 8 GB tier under the 75 percent rule; 5.5 / 8 / 11 GiB drops the tiers in the named order, about a quarter of today's measured consumer cards per step), the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB, the one card that pays rate for a larger working set), lane D's rings and band, the index fold as a layer-1 rule, the 5070 Ti pair, the x16 mixer at 11.4 ms loaded by the right method (admissible false on the measurement), lanes B, A and C taken in 7a to 7c, and section 9's served-line review with the wording proposed for the 20:00 word. Owed for 20:00: the 5090 size rows (the hash lane's v6 job), lane C's 15:00 re-read, lane D's 17:00 table, the two re-weighted packs' rows; each lands as a row with its label, or its default. Main's word at 12:5x BST on the kill class: the rule "no kill by name on the Mac, pid file only, ad-hoc shell lines included" lands in the agents' standing text with this record landing; the steward makes it a gate check that refuses pattern kills in scripts and logs the sender of every TERM a gate receives. The class-v5 lane's own line: the four pkill lines (12:3x to 12:37) stopped its own superseded gate runs as its tip moved under them; nothing of its uses a name or pattern kill again, its background gate started with its pid recorded and ended by that pid only; its current run (gate 17 on class-v5 79799452, 12:39) runs to its end. The census and the four-item pin taken by main; the clock as the shipper set it. Lane D's interim at 12:5x BST for the 09:00 report, the lossy-share curve at 1,000 to 1,300 eras per point: r rises 0.80, 0.88, 0.92, 0.96 as or, mul and mulhi go +1 to +4 points each; exhaustion appears at +3 (2 of 1,029) and reaches 1.4 percent at +4 (14 of 994); every exhausted era's class v5 last-resort scan passes at its first or second candidate (k = 256 or 257), so the band's edge is between +2 and +3 points of lossy weight and the scan does its job at the corner. Its cut 2a595e1b under the gate, then the mirror landing and the send to the research lane. The attack pass's F8 to 256 seeds landed at 12:37 BST: seeds p66 to p257 (192 new) at 2^24 on the freeze 1c420786 (binary 0f5c98dc, pairing e5a4ac5978462156), the window-model control, build-2 under class measure, validation 0 mismatches (hash_warp agreement on 37,440 warps). 184 of 192 within 1.2x at the top 0.1 percent (mean 1.023); 8 over (p110 1.3527x, p66 1.3403x, p234 1.3156x, p145 1.2750x, p77 1.2664x, p225 1.2457x, p248 1.2188x, p89 1.2065x), each with its hottest item at 263 to 432 reads of 2^31 and the hot-set verdict clear on the windowed control (largest excess X_f/f +0.60). Over all 256: 245 within (95.7 percent), 11 over; the rate at 256 (4.3 percent) is the gate's at 64 (4.7 percent) and the worst fell (1.3527x against p10's 1.5047x). The 6-sigma largest-bucket line flags 57 of 192 (p110 +61.67 sigma): the AP-F8-1 tail mechanism at its rate. Two seeds carry a predicted source, one-one-bit through a load, both passed by (c''') on the frozen tip: p212 (1.1915x, attempt 4, site instr 7, r5, last writer load at 2) and p225 (1.2457x, attempt 0, site instr 37, r5, last writer load at 36), to the hash lane for by-site attribution as the gate's tail was. Verdict PASS at the gate's reading: no card or chip gains a cacheable hot set on any of 256 epochs. The row and f8-uniform.md section (e) on the mirror's attack-pass. Still running: build-4's F9 (six chunks) and F1 (10^6), partials at 17:00. The node lane's named commit inside the 12:50 clock: 42ce0f07 on release-0.3.25-node, both mirrors, 12:39:37 BST, the sha with the steward and the shipper. Content: e0644958 (keygen, the record re-announce, the ceiling switch at 82,800; digest 1b37cb9d) plus four node fixes, nothing consensus: the ring self-check every 30 s over the last 2,000 records with the full scan on a generation change (node1's class, its known-failed test green); the snapshot digest stamp (a snapshot under another object or none refused, the node re-executing from genesis); the vetoed-node status (the count and the last veto on the status RPC and igneum_getNodeInfo, "stateFresh" false while any stands); the proof map's window (a proof leaves memory with its record at the 600-block window's end, the OOM class). Green before the squash on the same tree: exec 54 of 54, the kaspad check. The full gate set at gate priority on both boxes from 12:39:44 (every line by about 12:52), both canaries reading the Devnet 3 digest back at 1b37cb9d, the fast-time pair by about 13:00; the crossing watch at 68,400 on the seed from 12:50; the pin line after the last of those; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. The invention lane at 12:5x BST: the hash lane's 5090 rows for the two sound per-load packs reverse the GPU-side sign of rank 1: at class v4's own instruction count the per-load form costs the card 19 W MORE than the whole block unlocked (483.6 against 464.6 W) and 6.6 W more at the 1,300 lock, rate 1.3 percent under, 15 to 20 percent more per shadow instruction (19.7 to 20.8 pJ against 17.2); the dead 16 x 27 export's 13 to 14 W saving does not carry (a 16-instruction loop against a 144- or 256-instruction straight segment). Rank 1 keeps its place by the file's own rule (the chip's project cost about 2x against the card's 2 to 4 percent of watts) with the honest sign: the card pays, not saves. The second cut landed at 4315e992, the third (these rows) under the gate. The drawn-era re-read on 0ab27582 built on build-3 but starved (build-3's 16-core pool under lane D's three 24-core leases since 12:38): the coordinator moved it to build-4 at once through the lease pool under class measure (build-1 closed until the pin is named); the 15:00 numbers from build-4, the box named in the row. The class v5 lane's full gate on class-v5 79799452 (the tip on both mirrors) GREEN, 73 checks in 463 s at 12:47 BST, left to run to its end: 0.3.25's pairing row on the page (the freeze 1c420786, kit 65b47211 with the Intel worker held, the Arc read to 0.3.26 with the second PC dark), master merged through its latest (the 60x file taken whole from master after the merge reordered seven keys and duplicated three, values equal), the generated ledger files matching. Nothing of the lane's pending; the one future item the Arc B580 re-read on kit 65b47211 when the second PC is back, which moves the Intel row and sends the 0.3.26 upgrade line. 42ce0f07 reads every gate green at 12:48:10 BST: build 12:42 rc=0 (igneumd 8e17a60b, /srv/artefacts/0325-42ce0f07/node-lane), pow 19, consensus 134, core 177, miner 29, p2p-flows 38, exec 54, all at gate priority; the Devnet 3 canary set with digest 1b37cb9d unchanged, byte 6, the override refused, the 0.3.24 pin refused on the digest both ways; the testnet canary b2e856ed unchanged. The shipper has the line; the steward's matrix runs on it. Two inputs before the pin: the fast-time SUMMARY on 42ce0f07's artefact (about 13:00) and the 68,400 crossing on build-1's seed (the chain passes it about 12:54, the watch from 12:50). The reorg-unwind fix's 13:30 clock met at 12:48 on the same commit. The attack pass at 12:5x BST, the ends brought in: F1's 10^6 was one 40-thread census on build-4 (35 h); the harness now takes --start (attack-v5-frozen ebdb7d4a, smoke-tested: a 20-program census from index 5 writes rows 5 to 24), so the census is split by index range: build-4 keeps indices 0 to 349,999 (its running census, stopped by pid when its progress line reads 350,000; the flushed census.csv holds the lower range) and build-2 runs 350,000 to 999,999 at 80 threads under class measure (binary 42ee04c7, held since 12:48:40 BST after waiting 362 s for the pool to free on its own, no pre-emption). Both halves end about 23:30 BST. F9's six chunks hold on build-4 (48 cores); when build-2's F1 ends tonight the F9 remainder re-splits onto build-2 by seed range (rows keyed by seed, nothing lost), bringing F9's end from about 17:00 BST tomorrow to about 06:00 BST. Cores held: build-2 80 (F1 upper range), build-4 88 (F9 48, F1 40); build-1 and build-3 untouched. Partials at 17:00. RED, a first, at 12:48 BST: Devnet 3 STALLED AT THE CLASS V5 FLOOR. The seed's virtual DAA read 68,403 at 12:49:11, 12:50:23 and 12:51:09 with one sink (07055360), the last block accepted at DAA 68,399 as class v4 at 12:48:14; nothing at 68,400 or above reached the seed, node1 or the observer, no node logged a PoW rejection: no miner found an epoch-19 block on a chain that ran one a second. The nodes held epoch 19's state (the seed installed the streams for epochs 18 and 19 from its snapshot at 12:30). The cause (the fleet lane, 12:52): every miner's --worker is the hive package's igneum-worker-cuda, which runs generators 2, 3 and 4 only; the class v5 kit's worker (82b19cbde8557ea5, the one every v5 gate ran on) was never on any miner's worker path, only its packs were placed; the prepare of epoch 19 fails and the miner sits at 0 MH/s while the templates flow. The fast-time harness crossed this boundary green four times on pairs, which tests the node and the CPU engine, not the fleet's GPU workers or kits. The fleet places the kit worker on every box now; the 0.3.25 hive package and Windows payload rebuild with the kit's workers by 13:30 (the build-server lane); the Mac Metal worker's generator-5 read with the v5 lane by 13:10. The pin and the minute wait on the chain moving and the rebuilt packages; the 42ce0f07 gate set green, the matrix running, the ceiling cut's publish limit (DAA 75,600) standing still while the chain does. GATE RULE for the next cut (the record's and release-rules'): a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; the packs' presence and the kit's own tests never stand for it. The 0.3.24 move's read-back ("36 of 36 FETCHED on the pin") was a node reading; no reading of a worker preparing class v5 existed before the floor. The research lane at 12:5x BST: section 10 ("the floor") open in the class v6 document (counter-asic-4 after 91117093) with each floor lane's term, what the document holds measured for it, the default at 19:30 and the row owed; two measured rows the floor lanes start from rather than re-derive: the SM-sparse lane from 20.3b (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw, 460 against 451 W; 99.8 percent of class v3 at 4 W less; watts minus idle per MH/s never below base; the sparse shapes collapsing at the 1,300 lock; its new work the breakdown of the 99 W an idle SM does not save and whether an occupancy shape at full SM count moves it; the worker variants sp-w and the card-free --list-race check on counter-asic-4); the k lane from 15.1a (the GPU side measured per counted op: ARX 11.3 / 6.2 pJ, mul 13.9 / 8.3, mulhi 39.6 / 21.0, prmt 22.3 / 11.5, lop3 24.1 / 13.0, shfl 55.8 / 29.4, fp32 FMA 9.2 / 5.2, the int8 tile 1.4 to 4.1 per MAC; only the chip side claimed; the mix that maximises k priced against the GPU's own per-family cost, the shuffle 4.9x the add on the card). The thirty-ninth landing on master at 12:54 BST (26a3cbe6): the standing rule in CLAUDE.md. The node lane at 12:5x BST on the stall: the worker's refusal line is "program pack generator 5 is not a generator version this worker runs (2, 3 or 4)", faulting at 0 MH/s from the first epoch-19 template; the kit's class v5 worker was benched on 24 cards this morning and never placed on any miner's --worker path; the nodes read 0 PoW rejections and hand the right template (the CPU id-read from build-1 confirms epoch 19 as class v5). The fleet places the kit worker and its pack on every mining box, w-target first; the chain moves when the first card prepares. The record's lesson: a worker that cannot run the next class must refuse at the pack prepare, loudly, hours before the boundary (the plug, tune, play rule), and no hive tar ships without the class the object names. A second bug read off the stall: the pool admits at the next block's DAA (chain id 4464 past the floor) while eth_chainId answered the executed tip's id (4463 with the tip stalled at 68,399); the fix (eth_chainId and net_version answer the id a transaction sent now must carry, the status carrying both ids, the known-failed test on the stall's shape) a wip under its exec suite at gate priority since 12:54:27, landing as the SECOND commit on release-0.3.25-node over 42ce0f07 (nothing consensus, digest 1b37cb9d unchanged), its full gate set and fast-time pair by about 13:15; that commit the pin's node sha, 42ce0f07 if it reads red. THE CROSSING READS CLEAN. The first class v5 block (epoch 19, epoch seed a75c5624) was accepted on build-1's seed at 12:57:40 BST, 9 minutes 26 seconds after the last class v4 block, the minute the fleet's first kit worker prepared; then 13, 14, 71, 165 and 78 blocks a minute (the backlog clearing, the rate settling), DAA 68,547 at 13:01:37; seven stale-pack attempts refused between 12:59:24 and 13:01:10 (the harness's known-failed shape), none since; no state-wait, catch-up, stale-dataset or digest line on the seed, node1 or the observer; no honest block refused. Devnet 3 runs class v5 at byte 6 as the 0.3.24 object names (the v5 signal share 1,407 bps at the floor; the seed's template at 13:1x: epoch 19, class 5, version 1538, era the genesis, day 20,734; the executor serving epoch 19's stream, 869 records, root 0x1fd55139...4561). The pairing check holds three ways: the kit's igneum-pow (8f481459's tree, the freeze's hash object) names attempt 2, program id 3d375a55029e7e60 for epoch 19; the node lane's 0.3.24 pin miner (igneum-pow 1c420786) read the same id live at 12:56; the DMG's Metal worker on the Mac prepared epoch 19 against the live seed with the same id (869 leaves, 26 MH/s). The stall's two causes, both miner-side, neither in the object: every fleet miner's worker was the hive package's CUDA worker (generators 2, 3 and 4; it refuses a generator-5 pack with a line, the miner at 0 MH/s retrying, loud in the log and the plug-tune-play fault only on the dashboard), the DMG's Metal worker from the freeze's tree the same (the v5 worker path is the v5-kits lane's 5c9ed959, in class-v5 from e208dfea on; the freeze is the hash object, not the hosts); and a miner not told its node's exec RPC port cannot prepare class v5 at all, so every fleet loop needs --exec-rpc. The fix: the kit's workers (zip 65b47211) and --exec-rpc on every box; the hive, Windows and Mac packages from the kit tree (the hive and Windows payload carrying d84b1b6c / be23bc68 and e1bfd582 / 55722527 on the worker path; the Mac side closed on release-0.3.25 44d1815a, proto-metal from class-v5 79799452). The stall's cost: 9.5 minutes of blocks and every prover's share for that span. The standing rules from it (release rules 16 and 17 on ship-docs-0321 cb570365): the kit worker and --exec-rpc on every miner loop before any class boundary; a worker that cannot run the object's next class refuses at the pack prepare, hours ahead; a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; memory against the container's cap. All of it on the class v5 page's section 0 at class-v5 2494f3f8 (both mirrors 12:59, master merged, its full gate running by pid). The second node commit 5f316c21 on release-0.3.25-node (both mirrors 12:56:22 BST) = 42ce0f07 plus the chain-id answer (eth_chainId and net_version return the id the pool admits at, the next block's DAA, 4464 past the floor; the status carrying both ids; the known-failed test on the stall's shape), nothing consensus, digest 1b37cb9d unchanged; EVERY GATE GREEN at 13:04:05 BST (build 12:58 rc=0, igneumd 3812b2a2, /srv/artefacts/0325-5f316c21/node-lane; consensus 134, exec 54, core 177, pow 19, p2p-flows 38, miner 29, all at gate priority; the Devnet 3 canary with digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged). 5f316c21 IS THE PIN'S NODE SHA. The one input before the pin line: the fast-time SUMMARY on 42ce0f07's artefact (the run waited 796 s for build-1's pool, 88 of 88 leased at or above v5, nothing to pre-empt; running since 12:55:54, v5 from epoch 8 at 13:04:19, the line about 13:10), a run on 5f316c21 after it. The shipper's close: the app tip 9a71e784 (crate 89e83df2), the DMG 43cd8c94 staged, the tarball 1ae1810d, move id m5f31-1; the pin about 13:25 after the SUMMARY, the matrix and the hive; the minute about 14:00 to 14:20 inside 14:53. The TESTNET_PARAMS v5-at-0 re-cut's default moved under the rule by the node lane: it lands through its full gate set on release-0.3.24-node 30 minutes after the seed reads the first ten class v5 blocks accepted clean, so at 13:32 BST unless main says otherwise before then; a red crossing would have meant no re-cut. The audit lane's 9070 XT row on master at f37f497b (12:55 BST, gate green on 33b0ad06), ahead of 13:30: 18.96 MH/s, watts "149.3 with the 0.3.25 knob (195.8 stock)", 0.127 MH per watt, the tuned text with the 24 points' flatness and the date, the source the status row with the job id; the note carries the grid's stock point beside the app's 202 W reading of 7 October, the two single-lever points, and names both 5090 denominators (3.5x behind at the class v4 1,200 MHz lock, 0.43; about a fifth at the 1,300 knee, 0.60); the qualifier drops when the cut serves. With f37f497b: the complete class v4 watts rerun (22 rows), the /income calculator, the /economics page, the governance line, the two served-text corrections with their ledger rows. The build-server lane has it to deploy. The hash lane's kit b on the 5090 (12:49 to 12:58 BST, all PASS; with the research lane and the floor lane): the mixer multiplier x8 against x16 costs the GPU nothing (137.73 against 137.72 MH/s, 320.2 against 320.1 W unlocked; 127.44 against 127.46, 212.0 against 211.7 W at 1,300), so the verifier's 1.86x per doubling is the whole cost of that draw; the shuffle-heavy table on the base program moves 7 W unlocked and nothing at the lock (a 2 percent term); the pinned class v3 program at 2, 4 and 8 GiB costs a tuned 5090 5, 11 and 14 percent of rate at the 1,300 lock (4, 8 and 10 percent per hash) and 3 to 4 percent unlocked, which corrects the layer 2 line: the size term is real at the knee (the page-walk cost the latency-bound regime exposes). Kit c (the multiply-heavy table) running; kit d (both tables inside the shadow block, the row layer 1 needs) exports on build-2 and runs after, about 13:45. W = 8 for the floor lane: the crate's width set is three fixed word widths (1, 4, 16; WIDTH_WORDS, the mix arrays, the emitters for CUDA, OpenCL and Metal, the verifier's fold), so a 32-byte load needs a generator and emitter change before any pack exists (two to three hours of crate work on the readwidth line plus the PC 1 row); the ask to main with its default: say so by 14:00 and the lane starts it on the readwidth branch (a research class, no consensus object); silence means W = 4 pins and the floor lane hears so at 17:30. The F8-256 attribution runs for p212 and p225 on build-3 (the attack-pass crate d08e1e0f built there at 13:01), rows by 16:00. Main's ids for the floor lanes, for the record: SM-sparse af65f8187569666d0, shadow k a3c9601a6d4686fe1, SRAM and dataset floor acecab7195ea66621, honest denominator a4d39e20a0762646d, invention a734c5330f17be3c2; the research lane delivered the two starting rows to each with their 19:30 defaults. Two more master-only deploys from the builder stream, checks ok (38 miners rows, 18 asserted pages, the checkpoint API and the explorer stats API): d28cf8fc at 12:50 BST (the explorer wording c4ca746f, the audit lane's ace5c294 with /economics, the /income calculator and the class v4 watts rows, the DEX lane's 9126e4d6 and 825d19bd) and f37f497b at 13:04 BST (the reference-apps b7f1e0d7 with /oracle's BLS-verified root, the 9070 XT knob row on /miners). No chip text changed beyond the audit lane's own landings. The fortieth landing on master at 13:14 BST (90b180f2). Main's word on W = 8 at 13:1x: start it, research class with no consensus object; the order on the hash lane: the 0.3.25 lock rows and kit b first, then the readwidth generator and emitter, the PC 1 row by 17:30; a miss means W = 4 pins, the floor lane told, the W = 8 row later as a v6 sub-version check. The 13:32 testnet re-cut on its default. A RED THE MOVE ITSELF WOULD TRIGGER, read on build-1 at 13:05 BST by the node lane: a node re-executing from genesis (the fleet's 21 re-walks now; every node at the move under the snapshot stamp rule) has its executor thousands of blocks below the chain, so its pool admits at the executor's next DAA, names the old chain id 4463 below the floor, refuses every relayed transaction signed with 4464 as a state-free fault and disconnects the relayer as misbehaving ("wrong chain id: expected 4463, got Some(4464)" on the seed and node1 from peers at 13:05); for the length of its walk, about 8 minutes, it drops every peer that relays a transaction, and at the move every node would do it to every other: a partition. The fix, a wip under its exec suite at gate priority since 13:08:06: the admission height is the larger of the executor's next DAA and the chain's virtual DAA plus one (eth_chainId, net_version, eth_sendRawTransaction and the relay read it), and a mismatch between the network's own two ids is a refusal, never a strike; the known-failed test is the re-walk's shape. It lands as the line's third commit over 5f316c21 (nothing consensus, digest 1b37cb9d), the full gate set and the fast-time pair on it by about 13:35; the pin waits on it. The second thing in those logs is the stale class, not a bug: the 21 nodes with a divergent execution state compute a divergent class v5 dataset, refuse every honest v5 block as invalid PoW and ban build-1's seed for an hour ("Reject(BlockInvalid)" on the fleet's side), cured by their re-walks in progress; a node that cannot check a v5 header for want of the epoch's state holds off, as designed. The crossing is clean on the honest side; the chain runs. The fast-time crossing on the 0.3.25 pair 42ce0f07 (12:55:54 to 13:08:50 BST) read green on every claim (rung 1 at 13:02:22, v5 at byte 6 from epoch 8 at 13:04:19, 12 of 12 ids equal to the CPU verifier's, the stale node refused, the restart step resynced in 19.1 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); its SUMMARY read FAIL on one harness check: the final epoch's row held one miner's line when the run ended at that epoch's boundary (the id equal to the CLI's); not a node finding; the check now reads the final row by its id (v5-fasttime 130562a2); the clean rerun on the same artefact from 13:1x, SUMMARY about 14 minutes after its lease. Lane D's 17:00 cut LANDED on master at 238100b0 (13:13 BST), gate GREEN (73 checks, 355 s) on 2a595e1b, four hours early; the research lane has the layer-4 line; docs/analysis/class-v6/family-gate.md carries the measured coverage (24,000 drawn eras, per stratum and per axis, the bound arithmetic), the rows, logs, scripts and the harness diff under docs/analysis/class-v6/logs/. Build-3: w4lossybase done (3,000, 0 exhausted), shape256 1,910 of 3,000, shape64lossy 1,895 of 2,000, w4shape64 queued, then the point-B live census on the family attack-f8 build (74784428); build-1 the four lossy-share strata near done and the point-A live census. The class v5 lane's full gate on class-v5 2494f3f8 (the crossing row, master merged) GREEN, 73 checks in 407 s at 13:06, run to its end by pid, nothing killed. The third node commit inside the shipper's 13:20 clock: d5b68fae on release-0.3.25-node, both mirrors, 13:14:12 BST = 5f316c21 plus the admission fix (a transaction admitted at the larger of the executor's next DAA and the chain's virtual DAA plus one on the relay, eth_chainId, net_version, eth_sendRawTransaction and the status; a mismatch between the network's own two chain ids a refusal, never a strike; the known-failed test on the re-walk's shape), nothing consensus, digest 1b37cb9d unchanged, pairing 1c420786; exec 54 of 54 and the kaspad check green on the same tree before the squash. The full gate set at gate priority from 13:14:19, every line by about 13:26; the fast-time pair asked on it; the 42ce0f07 rerun's SUMMARY (about 13:24) the gate's record on the same object. The pin's node sha d5b68fae if green, else 5f316c21. The steward's 0.3.25 matrix at 13:17 BST: node 5f316c21 with app tree 89e83df2 GREEN on all seven suites on build-2, build-3 and build-4 (no RED); 42ce0f07 complete green on the same three; build-1 out; at 13:21 the third sha d5b68fae core and exec GREEN on the three boxes, six of six: the pre-pin suite read closed. d5b68fae reads every gate green at 13:22:43 BST (build 13:15 rc=0, igneumd b0e7b8b5, /srv/artefacts/0325-d5b68fae/node-lane; p2p-flows 38, pow 19, consensus 134, exec 54, core 177, miner 29 at gate priority; the Devnet 3 canary digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged): THE PIN'S NODE SHA IS d5b68fae. The fast-time SUMMARY PASS (cross-0325-42ce0f07-2) at 13:22:57 BST on the 0.3.25 pair 42ce0f07 (13:10:07 to 13:22:57 on build-1 under class v5: rung 1 at 13:16:33, v5 at byte 6 from epoch 8 at 13:18:43, the stale node refused, the restart step resynced in 11 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); the d5b68fae pair running side by side since 13:16:13 on its own cores and port base, SUMMARY about 13:30, the last input before the pin line. The reading behind the fleet's partition line at 13:17 BST (hub-1 at one sink, dn2-1 alone on its own branch, w-poison a third, dn3-g2 and dn3-q03 stuck at DAA 68,403 refusing every v5 block): epoch 19's class v5 dataset derives from the execution state after the epoch's reference block, the last chain block below the cut 19 x 3,600 - 600 = DAA 67,800: chain block 28,462, hash a75c5624 (the epoch seed), state root 0x1fd551393d (build-1's seed, node1-dn3 and the fresh node agree; the kit's stream names the same root). Any divergence of state OR numbering between 26,294 and 28,462 puts a node in a cluster that refuses the other clusters' proof of work and bans their relayers for an hour; root-equal at 26,247 was not the gate. The census now reads hash and root at 28,462 on every box (epoch 20's height moves to the last block at DAA at most 71,399); every cluster but the one on a75c5624 / 0x1fd55139 re-walks; build-1's observer node, the explorer's only source, is one of the drifted (its 28,462 another hash at DAA 67,787: the orphan-append class during its 11:22 re-walk, so the explorer's numbers are off by a few; the shipper has it). The cure is the move itself: every node restarted on the pin's binary re-executes from genesis under the snapshot stamp with the ring self-check running and lands on the one state; the gate on the minute is the fleet's census at 28,462 after the re-walks (31 boxes on the one state at 13:19:44, the rest the numbering class the move cures), with an unban of every held address per box once its root reads equal, since bans persist on disk across restarts; a box whose root there differs after a re-walk on the pin's binary is a new class and a stop. Lane D's measured correction at 13:2x BST for the full report: the lossy-corner exhaustion is a shape-256 interaction, not corner-wide: at the lossy cap the per-candidate rejection is 0.877 at shape 64 x 108 (0 of 2,000 and 0 of 1,000 eras exhaust), 0.923 at 128 x 54 (1 of 1,010), 0.980 at 256 x 27 (36 of 990, 3.6 percent; 24 of 670 at width 4); at r = 0.98 the independent-attempt figure is 0.98^256 = 0.6 percent, so the per-era correlation is about 6x, not the 1,000x the mixed-shape average suggested; the band rule stands either way (lossy families never raised), and the cheapest shape for the draw is also the fastest on the cards. The hash lane's attribution: run 2 (the attack-pass branch's own crate) reproduces p225's 1.2452x but not p212's (1.57x against the gate's 1.19x, a different draw, the crate differing from 1c420786); run 3 on the 1c420786 crate is the authoritative one, running. The W = 8 pow suite on build-2; the three state-term packs (w4, w32, w64 on +sh256x27+state, the node1 state file, --era-widths 4/8/16) export on its green; the read-width kit (those three, the v5-genesis pack, the two 5 October packs, which are string-seed class v2 packs the worker accepted on 5 October, no re-export) runs on PC 1 after kit d; the L2::64B hint variant is not in the worker exes, so it is lane 5's kernel line, nothing to build. STANDING RULE from the founder relayed by main at 13:2x BST, applied to every lane the coordinator runs and every default clock: work as fast as possible; anything doable in 30 minutes to 2 hours gets a clock inside that window, never a target hours out; fan work out (one pod per point, one box per variant) rather than queue it. The floor close is 15:45 BST. The coordinator's re-read of the 16:00, 16:30, 17:00 and 19:30 lines: the F8 attribution rows 14:00 (run 3 running, three minutes a census); lane C's drawn-era numbers 14:00 (an 80-s census on build-4) and its cut 15:00; the class v6 per-tier cost rows and layer 4's tests 14:30 (kit d about 13:45); the W = 8 PC 1 row 15:30 (the crate work fanned: the suite on build-2, the exports on build-2's slot, PC 1 the moment kit d closes); the floor lanes' rows 15:30 for the 15:45 close; the synthesis and the served-line review table 16:30; lane D's full report 16:30 with every stratum fanned across build-2's and build-4's free cores rather than queued on build-3; the DEX lane's swap UI 15:00 and the Sepolia verifier 16:00; the reference apps already served (b7f1e0d7 at 13:04). Main's word at 13:2x BST to every lane: while GitHub is suspended, landings go to the box mirror's master through the gate, never to Forgejo master, which is a rewritten copy replaced at cut-over by the box mirror's final tip; pushing a branch to Forgejo for safekeeping is fine, landing there is not. Relayed to every lane with the pulled clocks. The SRAM and dataset floor lane's row is complete at 13:18 BST, two hours inside its pulled 15:30 clock: the full row at 7bc9de4b and the clock references at 8e9588de on the box mirror's branch class-v6-floor-sram (safekeeping, no master landing), gate green on every push, all arithmetic on build-3; docs/analysis/class-v6/floor/sram-and-floor.md. What the 15:45 close carries: the capex wall on the corrected project floor (no chip project below about USD 23 M a year of miner revenue, IGN 0.03, USD 62 K a day; every DRAM-board project at a third of the network above about USD 340 M a year, IGN 0.44, USD 0.93 M a day, where the SRAM project also starts); the read width as the only wire lever on the SRAM die (66x at the hash's 4-byte width at zero shadow, 44x at W = 4, 31x at W = 8, 19x at W = 16 if the 5090 passes the PC 1 job, 36x at the measured w64 row); the shadowed die at 6x to 10x at the honest cards' whole latency shadow on the k lane's synthesised core, kept beside the k lane's sequencer-core row as the floor-k worst case, never under 2x by any shadow; the floor as a ticket lever (5.5 / 8.5 / 11.5 GiB = 3, 5, 6 reticles, USD 1,500 / 2,500 / 3,000; USD 5,000 per store is 20 GiB and retires every card under 32 GB; the 5090 pays 4 / 8 / 10 percent per hash at its knee and the M5 Max 12 / 20 / 22 percent of rate at 2 / 4 / 8 GiB, both measured); the four other candidates (per-era and per-block re-fill, straddling atoms, a second hot table) dead with numbers. Amendments after the close, each labelled with its time: the W = 8 or W = 16 PC 1 row (the hash lane), the k lane's shuffle row and its re-fold, the Apple rate curve past 8 GiB. The DEX lane closed with every clock met before the pull, all on the box mirror's master through the gate: the AMM live on Devnet 3 at 12:0x BST; the swap UI serving at igneum.network/swap since 11:36 with the Igneum Wallet bridge live from the 12:50 deploy; the Sepolia certificate verifier live at 13:3x (0xAf74f3F512081291D663Bb1d6b6d37E99e37D744, suite 10 of 10 on build-3, Devnet 3 checkpoint 2127 recorded final and one Devnet 3 balance proven on it); the one named gap: no on-chain link from checkpoint to state root yet (docs/bridge/light-client-bridge.md); final master 825d19bd. The forty-first landing on master at 13:35 BST (937cc82ae); during its branch push the hook "died of signal 15" once more (the merge's own gate ran green and landed), so a kill by name on the Mac still reached a gate at 13:3x: the steward's TERM-sender log is the read. STOP ON THE PIN d5b68fae at 13:29 BST, the fast-time pair: SUMMARY FAIL (cross-0325-d5b68fae), the failing check v5_ids_equal_the_cli_v5_id, a node finding: on epoch 9's attempt-3 seed ec0a8cf9 the d5b68fae miner and nodes drew program id 65b57e3b847d362e (its nodes accepting 4 of 4 on it) while the freeze CLI 1c420786 and the ab6f980b CLI both draw ebf64b32e2d84c5b, state or no state; the three other v5 epochs agree with the CLI. A node on the freeze's igneum-pow would refuse that epoch's blocks: a split on the first divergent seed, a chain split class. The 42ce0f07 and 39f127a1 PASSes met no such seed, so they do not clear it. The cause from the box's build log: the d5b68fae, 42ce0f07 and 5b673577 pairs were built "pairs_with": "igneum 05b21835 (detached) with uncommitted igneum-pow changes", not against the freeze 1c420786 (39f127a1 and c8f9b383 were, against ca3-v4-node commits 4c24903e and 0e4ec18a); every 0.3.25 node binary embeds "igneum-pow-v5/src", not the freeze's crate; rule 7's pairing broken in the node lane's build path. The orders: the node lane folds the freeze pairing (a clean rebuild from the freeze's exact igneum-pow, the build row's pairs_with read before any lease) and the ceiling re-cut to 90,000 into one commit (sha by 14:05, the gates and a new digest by 14:20, the SUMMARY with the seed in the set by 14:35); the build-server and fleet lanes read the live 0.3.24 miners' pairing path by 14:00 (if the live network carries the same divergence, the move is its cure before the first attempt-3 seed; 5b673577 is the live pin); the artefacts rebuild on the new sha; the pin about 14:35, the minute about 14:55 to 15:10 BST. The coordinator's order to the v5 lane: the pairing read-back on the rebuilt pair by 14:30 (the freeze CLI against the new sha's miner on ec0a8cf9 and the three other v5 epochs, id for id, and the live miner's path the same way). The record's rule for the pairing gate: the fast-time set carries an attempt-3 seed on every run (the epoch seeds of a run are its block hashes, so the divergent seed cannot be forced; the pairing row is the check that reads first); a pair's build row names its igneum-pow commit, and "uncommitted changes" in pairs_with is a refusal before any lease. Lane D's fan-out at 13:4x BST, one stratum per lease, class measure (every box's pool read 0 free at submission, each waiting in the measure class ahead of adv work): build-2 w1band (width 1 under the band, 3,000 eras, the fg7 harness with the refused-ratio column) at 16 cores, and the mixer verifier rows mx4m4g, mx4m8g, mx4m16g with the 256 x 27 shadow, one core each (the x16 row); build-4 w4shape64 (3,000) at 16 cores; build-3 the point-B live census (64 seeds at 2^24, shape 64 x 108 with a band era's weights) at 24 of 64 seeds PASS, and w4band (width 4 under the band, fg7) at 8 cores, 179 of 3,000; shape256 (3,000) and shape64lossy (2,000) COMPLETE; build-1 untouched (the point-A live census at 31 of 64 PASS, no test fired; the four lossy-share strata complete at 3,000 each); build-3's queued copies killed and their partial rows marked PARTIAL. The full report by 16:30 on the mirror's master through the gate; what has not finished by 16:00 goes in as a partial with its count. The corrected line for main: at the lossy cap r = 0.877 at shape 64 x 108 (0 of 3,000 across the strata), 0.923 at 128 x 54 (1 of 2,000), 0.980 at 256 x 27 (3.3 to 3.6 percent of eras in three strata). The hash lane's clocks at 13:4x BST: p225 reproduces on the 1c420786 crate (1.2452x against the gate's 1.2457x, by-site rows in hand, the close by 14:00); p212 does not: the tool at d08e1e0f over the 1c420786 crate draws a program at 1.5715x with a hot set ("site instr 5, r7, one-one-bit, last writer add at 4"), not the gate's 1.1915x attempt-4 program, because the gate ran a chain path (class v5 with the dn3 state) the pushed tool has no flag for; the attack-pass lane's exact command asked by 13:50, default: p212 reported as unreproduced on the pushed tool, labelled so. Kit d: the first two exports hung on a build-2 slot (a stale lock of the lane's own run, cleared); take 3 direct and bounded, packs about 13:45; PC 1 held by floor lane 1's two jobs, so kit d's job starts the minute the card frees and closes 8 minutes later (rows by 14:00 only if PC 1 frees by 13:50, else PC 1's free minute plus 10, inside 15:30; past 15:30 the microbench arithmetic stands). The per-tier cost rows and layer 4's tests delivered at 12:0x (scratch v4/ca4-v6-cost-rows.md), the kit b and c numbers folded in at 14:15. W = 8: the suite on build-2 (restarted 13:23 after a slot wait); the three state-term exports follow it on the same box; the PC 1 read-width job after kit d; the 15:30 row holds if the suite is green by 14:00 and PC 1 frees by 14:30, else W = 4 pins. The explorer lane's correction at 13:4x BST: the explorer's source is no longer the drifted observer: the build-server lane re-pointed the indexer unit, the observer and the public RPC at node1-dn3 (EVM 26870) at 13:25, and the three indexer tables were wiped and refilled from node1-dn3 from chain block 0 at 13:27 (about 3 min); balances, receipts and accounts are node1-dn3's, the DAG tables the observer process's reading of node1-dn3 since 13:25. The notice landing by 14:00: the header names node1-dn3 as the source since 13:25 BST, the observer drifted at DAA 67,787 and re-executes from genesis, a block list read before 13:27 may differ by a few blocks until the move; the same line on /block and /tx. eth_chainId on node1-dn3 answers 4464 since the floor, so the explorer's chain id is read from the node; every page printing 4463 as a fixed string (/build, /swap, /metamask, the nav's title) is one off, told to the build-server lane at 13:28. The attack pass's split under the fan-out rule, running from 13:30 BST, every lease class measure: F9 (900,000 seeds left on 1c420786) as twelve chunks: build-4 keeps the lower 85,000 of each of its six 150,000-seed ranges, restarted from each chunk's lowest missing seed (rows keyed by seed, a merge dedupes), six leases of 8 cores; build-2 takes the upper 65,000 of each range, six leases of 6 cores. F1 (10^6 class v5 programs): build-4 keeps indices 0 to 349,999 at 40 threads (at 76,000 at 13:19; stopped by pid at the 350,000 line), build-2 393,662 to 999,999 at 52 threads (its first 47,000 rows from 350,000 kept, merged by idx at the end). Cores held at 13:36: build-4 72 (F1 40, four F9 chunks of 8; two chunks waiting on lane D's 16-core w4shape64 lease there), build-2 24 (four F9 chunks of 6; F1's 52 and two chunks waiting): build-2 contested (lane D's w1band 16, the invention lane's per-load acceptance census on 0ab27582 48, the hash lane's attribution at class adv, the hash lane's igneum-pow suite at class release for 88 cores, which pre-empts every measure lease there when it starts; the class order decides). Ends at the measured rates if every lease holds: F9 build-4 halves about 04:45 BST, build-2 halves about 07:00; F1 build-4 range about 23:20, build-2 range about 05:40; the build-2 ends slip by their waits. The 15:30 reading carries the counts and re-stated ends. THE EXPOSURE READ at 13:50 BST (the node lane's fingerprints, the shipper's correction): THE LIVE NETWORK IS ON THE FREEZE. The igneum-pow tree each binary linked is the untracked igneum-pow-v5 copy beside its release worktree (the .cargo/config.toml paths override); every copy fingerprinted against git archive 1c420786 igneum-pow by two methods (the node lane's: find src -name '*.rs' | sort | xargs sha256sum | sha256sum; the build-server lane's: find . -name '*.rs' | sort | xargs cat | sha256sum | cut -c1-12): the freeze reads cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 and 29106189ca1e; the 0.3.24 line's worktree (vendor/igneum-node-0321, where 5b673577 and every 0.3.24 pin was built, the gate pair a3b1a2c9/cfa9f5ca, build-1's seed, node1 and the observer) reads the same on the Mac and both boxes; the fleet's shipped pairs the same (29106189ca1e); the kit workers on the freeze (the freeze CLI built at exactly 1c420786 on build-1, binary sha256 7ba781db, names Devnet 3's epoch 19 as attempt 2, program id 3d375a55029e7e60, equal to the 0.3.24 miner's live read). So no live node or worker diverges, no attempt-3 seed can part them, epochs 20, 21 and 22 are safe, no hub-side holding action; the shipper's 13:45 line to main withdrawn and corrected. What diverged: the 0.3.25 line's worktree (vendor/igneum-node-v5) carried a pre-freeze copy (fingerprint e01ea128fab1: accept.rs without the (c''') per-site distinct-index floor, MIN_DISTINCT_RATIO_V5 0.995 and its HotItemSite refusal; generator.rs and memhard.rs older); every 0.3.25 gate artefact c6629572 through d5b68fae was built on it, none shipped; on an attempt-3 seed it draws attempt 2's id where the freeze goes to attempt 3, the fast-time FAIL; replaced by the freeze's tree on the Mac and both boxes at 13:34 (fingerprints equal). The builds.jsonl pairs_with rows name the parent repo's HEAD, not the override copy, so they never said which tree was linked; the fingerprint is the only reading. The predictability: an epoch's attempt and program id are a deterministic function of its epoch seed, fixed 600 DAA (ten minutes) before the epoch starts, so any two trees compare ahead on every seed by both CLIs; across the freeze and the pre-freeze tree the hash lane's census puts the share of seeds that differ at 2.4 percent (112 of 4,600), a per-epoch roll that only matters where a pre-freeze binary is live, and none is. The boundaries at 1.0 DAA/s from the 13:01:37 read: epoch 20 at DAA 72,000 about 13:59 BST (seed fixed 13:49), epoch 21 at 75,600 about 14:59, epoch 22 at 79,200 about 15:59. RULE 19 and the rebuilt sha inside the shipper's 14:05 clock: 6ccaf9e9 on release-0.3.25-node, both mirrors, 13:41:28 BST = d5b68fae plus rule 19's build-time half (consensus/pow/build.rs fingerprints the linked igneum-pow tree by the shell's method and refuses the build unless it equals packaging/pow-freeze.txt, "cbc5bd0a… 1c420786 class-v5-freeze 2026-10-07", unless IGNEUM_POW_FREEZE_CHECK=0; IGNEUM_POW_FINGERPRINT in every binary's strings, on igneumd's start lines and igneum-miner's engine line; the handshake field on the next commit with its own gate) and the Devnet 3 ceiling re-cut to 90,000 (the publish limit DAA 82,800, about 16:53 BST; the digest moves, named by the canary). The wip's check, pow and core suites read "igneum-pow fingerprint cbc5bd0aa10585c8 (the freeze)" at 13:40. The full gate set at gate priority from 13:41:35 (the build on build-1 with the fingerprint strings read back from both binaries, six suites on build-2, both canary sets), every line by about 13:55; rule 19's known-failed case on build-2 beside it (the pre-freeze copy under the override must fail the build); the fast-time lane's watcher fires on the artefact (about 13:45), reads the fingerprint string before its lease, its SUMMARY with the attempt-3 seed about 14:05; the v5 lane's flip case (the harness taking POW_BIN, the freeze CLI, beside FORK_BIN) reads every v5 epoch's id on the pair against the freeze CLI, 13 minutes a case, within 15 minutes of the sha. The testnet v5-at-0 re-cut landed by its default at 13:32 as 3ffcf83b on release-0.3.24-node (its pairing the freeze), its gate set from 13:40:39, its digest from its canary. The pin line follows 6ccaf9e9's last gate and the SUMMARY. The v5 page's section 0 carries the STOP and the pairing rule's new line at 3b894a4d. The counter-asic-4 documents landed on the box mirror's master at 13:35 BST as 868fea52 (full gate GREEN 73, the stamp on c21f1f38): docs/analysis/counter-asic-4-research.md, docs/design/class-v6-rotating-family.md (the branch's text at 08641162), docs/analysis/chip-model-v3.md (5.12 and the capex correction), tools/ci/export-exclude.txt (+4); igneum-pow/src, igneum-pow/tests and proto-cuda stay on counter-asic-4; no served page changed. The research-landing lane's next: floor-sram (8e9588de) about 13:55 from the Mac on its green stamp (the full gate RED 5 of 73 on build-3, all box-environment classes, the steward told as owner: the gate is the Mac-side script that reaches the boxes from inside), floor-k with tools/chip-model/rtl about 15:45, floor-sm documents by 15:30, the denominator and invention lanes on their words. The 6a5fa763 deploy at 13:42 BST (the explorer's source notice and chain id from the node, b092fa17; /swap reading eth_chainId at load, 46eb9e4b; /metamask on 0x1170 and the public RPC, the nav pill, /faucet and /build on 4464 with the floor dated): Devnet 3's eth_chainId moved from 4463 to 4464 at the floor; checks ok, 19 asserted pages. Lane C's 14:00 numbers: the no-era half in hand on 0ab27582 (the sound form 0.927, 234 of 256, unchanged on the fixed instrument; the control sh256x27 now reads sub-version 3's own 0.682 because the merge brought master's (a') pass to that spelling, so the two sit on one instrument); the era sweep on build-2 on the first free cores; the 15:00 cut after it. The attack pass at 13:46 BST: build-4's F1 lower range stopped by its pid file (83,000 distinct rows kept from indices 0 to 349,999) and restarted at 8 threads from its lowest missing index 78,082 (the 4,900 interleaved rows above it redone and deduped by idx at the merge), freeing 32 cores for the census lane; at 15:30 the shard restarts at 40 threads the same way; its end moves from about 23:20 to about 00:15 BST. A print-only move of the sha at 13:45 BST: c9ad753a on release-0.3.25-node, both mirrors = 6ccaf9e9 plus igneum-miner embedding the full IGNEUM_POW_FINGERPRINT=<64 hex> string on its engine line (igneumd carried it; the miner's binary had only the sixteen-character start-line form, so the pair's read-back on both binaries failed on the miner); no code path, object or digest change. The Devnet 3 digest on the pin: 2066aa57505e5ecbd585d061364abb0032d5b5b29cc41c54f4b38cb81c2ba6eb (the ceiling at 90,000; the publish limit DAA 82,800, about 16:53 BST); the fingerprint cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 (the freeze); the 0.3.24 pin refused both ways on its canary. Its full gate set at gate priority from 13:45:59 (every line by about 14:00, both binaries' strings read back in the build log); 6ccaf9e9's own gate set and rule 19's known-failed self-test by about 13:55; the fast-time SUMMARY on 6ccaf9e9 (the same node code and object) about 13:59 stands as the gate's record; the v5 lane's flip case on the pair follows; the pin line after the last of those. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. THE FAST-TIME GATE ON THE RE-CUT: SUMMARY PASS (cross-0324-c9e385eb) at 22:49:32Z (23:49 BST) on the shipped 0.3.24 re-cut c9e385eb (igneumd 7a841b20..., igneum-miner 1e209b9e..., igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 22:36:25Z to 22:49:32Z, every check green: rung 1 by signal at epoch 6 (22:42:54Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (22:44:54Z, 4 of 4, 9,985 bps), 11 of 11 ids equal to the CPU verifier's, the stale node 86 of 86 refused with 0 accepted after the first refresh, the restart step across the boundary on a kept datadir resynced in 28.1 s with the catch-up done after 10 s and 0 of its own blocks during it, four sinks equal at 660, honest nodes 0 PoW rejections; record on v5-fasttime 76276be6, docs/design/class-v5-harness/fasttime/cross-0324-c9e385eb.json. The 0.3.24 move's gates left (the shipper's correction of this record): not F9 and F1's full 10^5 PASS (landing about 00:40 BST, too close to the 00:52 ceiling) but an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, max attempt 25), any non-zero holding the move, the full 10^5 the record line after; the minute named by the fleet on the last FETCHED plus ten once the build-server lane's c9e385eb pairs land. THE 61-ROW ERA READING (the v5 lane, box 2, 23:4x to 23:5x BST, docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log): 0 of 61 refused by the 0.995 floor at the table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), every class v5 draw on the class v4 attempt; era-drawn-28 (id 5e9eb01efbbf653e, attempt 6, R 15, the worst of adv-cache-2's census at 1.7451x) reads its biased site 15 at 0.9969, over the floor by 0.0019; era-drawn-25 (1.3571x, R 21) site 11 at 0.9994; the eight over 1.2x span 0.9965 to 0.9997 while the eight few-item hot sets sat 0.003 to 0.013 under the line. Main's sentence opens AP-F8-6 and section 14 verbatim with the two-instrument reading under it. THE CLASS V5 ATTEMPTS CENSUS for 1.4.7 (1,000 f8 seeds through the chain draw, v5-attempts-census-1000.log, the crypto lane's form): 3,219 candidates, 2,219 rejected, per-candidate rejection 0.6893 (sub-version 3: 0.68), accepted attempt mean 2.219, 0 exhaustions, P(256 consecutive) 4.4e-42; first failing part (a') 83.4 percent of rejections, (a) 10.7, (b) 3.0, (c'') 1.2, (c''') 1.0 (0.7 percent of candidates, one in 140: the floor's own share, 0.045 on the attempt mean), (c) 0.7 together, (c') none; the 5.14 percent of class v3 that 1.4.6 quotes is the audit lane's to replace. Both on class-v5 at 3b1dffd6 with main's sentence (891dd008), the mirror's master merged (e0471019: AP-F8-1's update and AP-F8-4 taken, the program-id recipe form with the state tag, no conflict), the design page's pre-public scrub (the founder's name six times, gone), M35's status word and the regenerated public ledger; the push waits on the full gate and the pinned-packs test on the merged tree (the proof that e5a4ac5978462156 and the other ids still derive under master's recipe form). THE 00:00 BST READINGS (the crypto lane; the verified roll-up of all nine lanes in section 13 of in-house-pass.md on crypto-engage, every branch tip read from the mirror and igneum-pow identical to 017e7037 on each). adv-accept, tip a7c49399 (about 5.5 box-hours, 0 pod-hours): 182,646 distinct accepted programs drawn (18 percent of the 10^6); eight pass every part of the frozen rule and flag the live hot-set test at 2^24 (X at 0.1 percent +0.102 to +0.221, 1.54x to 2.24x), all in the lowest 34 stand-in-ratio seeds against 0 in 20 random; each about 1 MB of items holding 0.26 to 0.41 percent of reads, 1.002x at the largest; the mechanism a near-saturated source at one site mapped by the era stride to one fixed item (plus two lesser shapes); the exemplar reads the same under the class v5 dataset. Against the class v5 floor: 8 of 8 refused; 3 mild residuals missed (adv-cache-2's rotation class, a load_index question not a floor question); 6 clean programs refused among the 9 deepest (the 2.4 percent). Q2 BOUND (54 programs plus 17 reads, 0 disagreements). Row 90: 0.6787 per candidate, (a') 83.3 percent, 0 exhaustions, P 8e-44. Partial named: 18 percent of seeds, 54 live rows, row 90 at half; a longer pass adds rows of the same shapes, not a different answer, unless a seed reads a hot set over 1 percent of reads, which 182,646 draws did not produce. THE PER-LOAD CLASS CLOSED (the research lane, for main; clock readings UTC): the per-load shadow fix held for distinctness and then met the value-level requirement from adv-cache-2, and the construction did not survive it; the per-load 16 x 27 class is dead as a chain class. 22:44 the attempt verdicts on four seeds (igneum-genesis 0 of 32 accepted); 22:47 the 64-seed census under the full rule (duplicate lanes at a load row plus the one-count of every index bit per site over the 64 units, 6-sigma band): 22 of 1,621 candidates accepted (1.4 percent), 42 of 64 seeds exhaust the chain's 32 attempts (an epoch without a program); the first failing test per candidate: biased index bit 775, duplicate lanes 643, the base rule 110, (b) 43, (a) 28; candidate 0 of the class carries index bit 0 set in 40 of 1,024 addresses (z 29.5); 22:52 the suite green (64 + 5 + 7 + 4 + 19 + 2 + 7); the acceptance rule with BiasedIndexBit for this class and the tests pushed as the record, the file's 20.2a closed. The structural reason: 27 passes of a 16-instruction map right before a load is an iterated small function and collapses or biases the load's address register before any base instruction re-randomises it; the class v4 shape has 64 base instructions and 16 loads between its block and every load. Both exports were accepted only because the rule did not model the placement; their PC 1 rows stay as an energy reading of the placement, labelled unsound. Rank 4 and the USD 200 M capex row rest on a construction not shown to exist (chip model 5.11's clause marked so in this landing); the sound form is one pass of a 432-instruction sub-block per load (a program segment, not an iterated map), a new class to draw, accept and measure, not tonight's. Replicated by a second instrument: the class v4 shape on this pre-amendment generator carries the adv-cache-2 product bit at address bit R exactly in 14 of 17 drawn eras (one-count 250 or 780 of 1,024, z 15 to 19), 0 duplicate pairs across the eras. What stands from the two prototypes: the tile block (bit-exact on the Metal reference, the AVX2 verifier at 0.047 us per tile, the Apple emulation cost 35 to 78 percent) awaiting its 5090 rows; the per-load placement closed. THE SPEC REWRITE ON MASTER (the site audit lane, 8b834634 at 23:56 BST; gate GREEN on 64e2a91b, 71 checks; the igneum-pow suite green on the box for that commit with derivation.rs and spec_readback.rs): spec 01 sections 1.4.3 and 1.4.6.1 to 1.4.6.6 rewritten to 017e7037 with the 20-row constants table (ACCEPT_TAG, the window-cap literal, MAX_SATURATED as the first refused count with the 163 message noted) and the 6-row pinned-ids table with Devnet 3's full genesis hex; the shadow block in 1.7; the ninth era draw in 1.13.1; tools/ci/spec-constants-check.mjs in the gate (known-failed first, every Constant | Value | Where table, pending rows skipped while absent); igneum-pow/tests/spec_readback.rs (ids derived through the crate, each class v4 row drawn to its attempt); ledger AP-F8-5 after AP-F8-4; the ledger-page fix (both heading forms, the pass as its own section, known-failed self-test in the gate; AP-F8-1, AP-F8-4 and AP-F8-5 render on /ledger); the fud-ledger's two prize clauses and "paid independent cryptanalysis" removed at the source so the regenerated page carries neither (commit 90424d5a, merge 64e2a91b). A HARDWARE FACT IN DISPUTE, for main: tonight's 5080 efficiency rows came from PC 1 jobs (run-ca3-pc1-v4-eff-5080-20261007-b and -c), the audit lane's record reads the RTX 5080 and the Arc B580 on PC 1, the hash lane's 22:09Z device list on PC 1 shows the 5090, the 9070 XT and the 4070 only, and main places the 5080 and the B580 on PC 2; identity-check.sh's "PC 2" substitution text names cards and is left card-free until the PC 2 job's own --list settles which cards sit where. THE IDENTITY CHECK'S PC 2 TEXT (the CI steward, 00:05 UK on 8 October): tools/ci/identity-check.sh rewrites "PC 2" card-free as "the second Windows rig" (commit 40f2be54, merge 0d2cf334, gate GREEN 71 checks, identity grep 0 hits over 306 export files and 52 served pages); line 69's PC 1 list untouched; the reason recorded in a bash comment above the perl call. THE 32,400 FLOOR LOST (the node lane, 00:0x UK on 8 October): dn3-g1's chain read DAA 25,126 at 23:52:03Z and 25,169 at 23:52:38Z, so the publish DAA passed 25,200 at about 23:53:09Z with no 0.3.24 move made (build-1's three Devnet 3 nodes last restarted about 21:31Z on the 0.3.23 move; the old seed holds 38 peers on ba75bf6f; no move minute was named). The next boundary is 36,000 (epoch 10), about 02:52Z on 8 October (03:52 BST) at 1.0 DAA/s, holding for a publish up to DAA 28,800 (about 00:53Z, 01:53 BST). Two routes put to the shipper and main: the same re-cut script on release-0.3.24-node (program_class_v5_activation_daa 36,000, nothing else, the same gate set, about 20 minutes to the pin line), or the fleet names its minute first and the floor is cut from it in one go (publish DAA plus 7,200 to the next 3,600) instead of a fourth chase; the pin c9e385eb stands meanwhile. THE FLOOR RE-CUT FROM A NAMED MINUTE (the shipper, 00:1x BST on 8 October, under the slip rule main set with the object commit): the floor re-cuts once more to 39,600 (epoch 11, about 04:52 BST) from a move minute the shipper named: 02:00 BST on 8 October, or the fleet's last FETCHED plus ten if later but before 02:53 BST (DAA 32,400, the ceiling); the node lane's pin line in about 20 minutes with the new Devnet 3 digest; the F9/F1 interim read at 01:55 BST; the publish minute equals the move minute (the apps' entries at or after it); the fast-time SUMMARY PASS reruns on the new pin as part of its gate set; the cause of the lost floor named: the c9e385eb pairs and the two PC jobs unreported for forty minutes, so the fleet had nothing to point its move file at. "slot closed" on PC 1 still waits on the host job's exit. THE 0.3.24 NODE PIN AT 39,600 (the node lane): dfbd1e10 on release-0.3.24-node (both mirrors, 23:54:13Z) = c9e385eb with program_class_v5_activation_daa 39,600 (epoch 11), nothing else; pairing igneum-pow 1c420786; every gate green at 00:01:52Z (build 23:56Z rc 0 at gate priority, igneumd 4870ccf2..., igneum-miner aa8c2978..., /srv/artefacts/0324-dfbd1e10/node-lane; pow 19, consensus 134, p2p-flows 38, exec 47, core 175, miner 28); the Devnet 3 canary set (23:56:33Z to 23:58:13Z): digest b1ba78229b069dc395fa666638a686a66615eb760d251798adfa6a654a415f82 on igneum-devnet-3 from ba75bf6f, object version 6 stamped (block version 1538), the override file refused, shutdown 2,015 ms, two empty nodes handshaking on it, the shared-devnet dialler rejected, a 2720d8d2 node refused on the digest both ways; the testnet canary b2e856ed unchanged (byte 7, a live old-object testnet node refused). The cut's read: dn3-g1 at DAA 25,169 at 23:52:38Z (1.0 DAA/s), the publish DAA at the named minute 01:00Z about 29,211, plus 7,200 = 36,411, the boundary 39,600 about 03:53:09Z on 8 October (04:53 BST), holding for a publish up to DAA 32,400 (about 01:53:09Z, 02:53 BST). The one gate running: the fast-time pair on dfbd1e10 (about 13 minutes from its start). c9e385eb is void as a pin; the F9/F1 interim read armed at 00:55Z. THE TWO PC QUEUES AT 01:03 BST (the hash lane): PC 1's "slot closed" has not come (the shipper's 0.3.24 host job, the build-server lane's, took the slot at 22:13Z for an expected two to three minutes; nothing reported in 110 minutes); nothing of the hash lane's has run on PC 1 since 22:09:25Z; the v5 kit fetch and the 9070 XT v5 bench are prepared and unpublished (tools/ca3-v4-amend/pc1-publish-20261007.sh, steps v5-kit and v5-amd), so no 9070 XT class v5 fingerprint exists yet; the lock protocol holds unless main says the lock-free pair goes ahead of the silent host job. PC 2's "clear" has not come either (the 0.3.23 take 3 smoke and the scheduler proof unreported by either lane); the Intel job is prepared and unpublished. THE HARDWARE FACT, read from tonight's PC 1 lines: nvidia-smi on PC 1 lists GPU 0 RTX 5090 (bus 01:00.0) and GPU 1 RTX 5080 (bus 0D:00.0); its OpenCL list carries the RX 9070 XT (gfx1201) and the integrated gfx1036 and no Intel platform; so the 5080 is on PC 1 (the audit lane's record right, the 22:09Z device-list summary short by one card) and the Arc B580 is not, which agrees with main's word that it is PC 2's eGPU; the kits row, the bench notes and identity-check's card-free PC 2 text stand on that. The locked PC 1 jobs stay parked (the 5080 full grid, the third 5090 pass, SM-sparse, the microbench and packs knee states, the two Ember tunes, the hot-table ldcs rows); the lock-free CA4 rows queue after the v5 bench on the same "slot closed". THE 00:00 BST READINGS, THE OTHER THREE (read by the crypto lane from each branch's report on the mirror at 01:03 BST; the roll-up section 13 of in-house-pass.md at crypto-engage c84ba51b with adv-accept's reading at 1b4e07ff; all nine branch tips read back from the mirror and igneum-pow IDENTICAL to 017e7037 on every one: adv-mixer d2ba3134, adv-mixer-2 2a632579, adv-mixer-3 4ebe2455, adv-cache 555c3e42, adv-cache-2 9384ee09, adv-cache-3 9452c0bf, adv-accept a7c49399, adv-accept-2 92168536, adv-accept-3 0c150e3c). adv-accept-3 (exhaustion or steering of the draw), tip 0c150e3c, every sweep ended 23:05 BST, about 3.3 box-hours, 0 pod-hours: Q1 exhaustion BOUND (per attempt accept 0.323, reject 0.677 ((a') 0.568, (a) 0.079, (b) 0.022, dynamic parts about 0.009), geometric histogram, P(exhaust) 0.677^256 = 4.6e-44, 0 of 16,337 seeds at the cap); Q1b the last resort FINDING (correctness; the mirror fired at cap 256 byte-identically; of 3,000 last-resort programs the real rule rejects 271, 9.0 percent: 251 by (a), 14 by (b), 6 by (c) distinct sum; handed out unchecked; unreachable; closed in class v5 by 8ca66afa, AP-F8-3); Q2 steering BOUND (45 of 48 planted rows fired, the real rule rejects every effective plant by (a'); 975 seeds at the first part, min ratio 0.998, 18 of 18 chain re-draws equal); Q2b the price of a seed property at 1 in 10^6 tries is a shadow block with 38 multiplies of 256 against a mean 74, about 2 to 3 percent of the f = 1 chip's energy per hash, the load critical path worth nothing at the memory activate ceiling; Q2c the 256-unit ratio is noise as a selector; Q3 program id FINDING (documentation: the "sub/" || 3_le16 suffix omitted from program.json and spec 1.4.6; a text-derived implementation computes 30956569d8f3d8d7 for Devnet 3 against the pack's fce15bf61030be57; 0 collisions over 10^7 pairs; fixed as AP-F8-4 at da2fc101); Q4 determinism DONE (the (c'') f64 compare never disagrees with the integer rule on any of the 2^20 + 1 values, margins 0.32 to 0.44 counts; a second interpretation agrees on 5,748 of 5,748 verdicts of 1,792 seeds); Q5 the era lever BOUND (400 eras, no stride under NAF weight 7, all 31 rotations, 354 distinct interleaves; epoch 0's accepted attempt is 3 under every era, so the era moves the address map, not the program). Partial named: the steering sweep at 975 of a planned 10^5 seeds (about 8 box-hours more at 32 cores). adv-cache-2 (the hot-set attack), tip 9384ee09 at 23:52 BST, about 2.2 box-hours by wall times threads over 96 (the boxes at load 400 to 600 for the first two hours), 0 pod-hours; two shards still queued at 00:00 (lines-2e30-s2c, warps-devnet-2e25-v2), named partial: Q1 the line index PASS (pooled 16 days; segments max +4.84 sigma against a control's +4.24, lines +5.61 against +5.35, chi2/dof 0.99937, top 0.1 and 1 percent of lines 1.0003x and 1.0002x of control; the 2^35 + 3 x 2^33 census all PASS; 0 mirror mismatches); Q2a the real programs PASS on the hot-set test (devnet at 2^26 1.0002x; Devnet 3 at 2^26 items 1.0071x, lines 1.0000x) with the FINDING at Devnet 3 site 0; Q2b all 64 programs done, every one clear on the hot-set test (items 0.9993x to 1.0075x of the windowed control) but the site class as recorded above (13 of 27 drawn-era over 1.04x, 8 over 1.2x, worst 1.7451x; the v5 floor refuses 0 of 61; AP-F8-6); Q3(1) steering by t PASS (worst cell 3.95 sigma in 2 x 2,112 cells); Q3(2) the weak-day scan PASS over 16,384 days (2^30 derivations in 707 s; worst per-day max bucket +8.13 sigma against the control's +7.78; the plant fired at +1,090); Q3(3) the window layer: the exact distribution matches the 4,096-program census to four digits (top quarter mean 0.3382, top half 0.5811), with a FINDING against the chip model's table: the f = 0.25 and f = 0.5 partial-store rows overstate the recompute share by up to 1.8x at f = 0.5, the full-store (f = 1) verdict unchanged (a correction owed in chip-model-v3's partial-store rows; no served number rests on f under 1); Q4 the prices: the only measured excess over f is the window layer's and the line reference multiplicity (a hottest-lines half store hits 57.8 percent instead of 50 at a higher miss cost than the stride). adv-mixer-3 (the statistical distinguisher and round margin), tip 4ebe2455 at 00:41 BST, still RUNNING at 01:03 (Q3 and Q4 at k = 8 on day 20729, queue 07 in the pool, the SAT ladder at k = 3 timed out; the total box-hours the lane's to give): Q1 the exhaustive round-0 line-index census over all 2^32 t PASS to k = 8 on days 20729 and 20733 and at k = 2, 3, 4, 8 on 20730 (z within 1.5); Q2 single-bit avalanche FINDING at k = 1 (354 and 266 holes, 130,000 cells beyond 6 sigma, the known one-application diffusion), PASS from k = 2 at 2^24 (0 holes, worst z under 5.3 through k = 8); Q2b the t-bit avalanche the same shape; Q3 differential multiplicity over 576 low-weight differences FINDING at k = 1 (695 and 537 deterministic output bits), PASS k = 2 through 7, k = 8 running; Q4 and Q4b linear correlations PASS from k = 1 (worst c 0.00046 to 0.00062, z under 5.1); Q5 rotational-XOR PASS from k = 1; Q6 SAT: k = 1 SATISFIABLE in 137 s (t = 0x49880000 verified through the real code), k = 2 and 3 TIMEOUT at the one-hour cap. The round margin as it stands: no statistic survives 2 of the 8 applications between reads; a chip gets nothing from the k = 1 findings because every read sits behind 8. The lanes' own lines go into section 13.1 as they arrive. THE LANES' OWN 00:00 LINES (adv-accept-3 and adv-mixer-3, 01:0x BST, in section 13.1 of in-house-pass.md): adv-accept-3's P(exhaust) refined to 1.0e-43 per epoch seed from 62,240 full-rule candidates plus 3.0e6 static candidates; Q2 steering BOUND over 19,975 full-rule and 1e6 static seeds, no property buying over about 1.03x at 1 in 1e6 tries; a second documentary FINDING: an implementation written from the spec text (not the code) at 017e7037's spec differs on 264 of 400 epoch programs, the same text-against-code gap as the id suffix (the audit lane's rewrite 8b834634 with spec_readback.rs is the fix; the proof that it closes this is a re-run of the text-derived implementation against the rewritten text, asked); a plant note: the floor-0.97 known-failed variant did not fire because the (c'') ratios are bimodal (accepted 0.989 to 0.999, rejected 0.814 to 0.966), replaced by a single-pass (a) variant that did; 3.3 box-hours, nothing running. adv-mixer-3: about 3.0 wall-hours of sweep plus 4 single-core CaDiCaL hours; the round margin stated as 6 of 8 applications between reads and 70 of 72 per item on every measured statistic, the k = 1 effects one mechanism (the lowest-set-bit trail through one application, dead once both addends carry a difference), nothing saving one application against 9,360 ops per item; still running at 4 cores on build-1 (2^27 and 2^28 avalanche rows, finish about 03:00 BST) and the day-20733 SAT ladder on build-2 (about 03:45 BST); not attempted: multi-bit linear masks and a MILP trail bound. adv-cache-2's own line still owed. ADV-CACHE-2'S OWN LINE (01:05 BST, tip 3f50d6c4; section 13 of in-house-pass.md now carries every lane's reading in its own words plus the verified roll-up): the drawn-era prevalence read on the SAME 32 base programs is 2 of 32 under the devnet era against 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), the mechanism carried by rotl(x times M, R) into the item index unless R is 29 or 30 (2 of 31 rotations), with a sub-class of warp-uniform sources once in 16,000 warps; the window layer's price restated: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the chip model's partial-store rows overstate the recompute share by up to 2.3x on these programs, the f = 1 verdict unchanged (the correction to chip-model-v3's partial-store rows is the coordinator's next commit); partial named (the drawn-era windows census of 4,096 and one line shard in the pool); the longer-pass line: the biased-site rate per era in closed form (the R in {29, 30} rate 2 in 31) and a 2^28 read of the worst site. Nothing of the pass stands between the pool and a higher-class job except two pre-emptable shards on box 2. THE SPEC-TEXT RE-DERIVATION ORDERED (01:06 BST): adv-accept-3 re-derives its 400 epoch programs from the rewritten spec text alone at master 8b834634 (1.4.3 to 1.4.6 grown from 79 to 198 lines with the constants and pinned-ids tables), lease pool 16 --min 8 class adv, row Q4c in its report; the expected reading 0 of 400, any non-zero naming the diverging sentence to the audit lane; the proof that AP-F8-5 closed the text-against-code gap. THE CHIP MODEL'S PARTIAL-STORE ROWS carry a second correction (section 5, 8 October 2026) from adv-cache-2's window-layer reading: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the uniform-store rows overstate the recompute share by up to 2.3x; the f = 1 row, the SRAM column and the full-store verdict unchanged, no served number on f under 1. THE CLASS V5 PACKS TEST ON THE MERGED TREE (the v5 lane, 01:0x UK): the job ran on box 2 the minute two adv-accept holders ended (65 cores; no lease fault, plain starvation before); 19 passed, 1 FAILED: v5_pack_is_the_v4_program_over_the_state_leaves (tests/packs.rs:977), the byte-for-byte compare of every pinned pack file with the crate's export. The ids are EQUAL (v4-genesis exports a217c7f698880830 as pinned; the state tag rides in master's recipe form unchanged); what differs is the program_id_derivation TEXT in program.json, which master's export (the hash lane's AP-F8-4 read-back form) now writes as "... || attempt_le32 || 'sub/' || sub_version_le16" for generator 4 while the pinned packs carry the pre-suffix wording. Disposition: the three pinned packs re-exported from the merged crate (text only; the ids, kernel texts, leaves and the fingerprint 82b19cbde8557ea5 must come out byte-identical, proved by the same test); the CLI rebuilding on build-1 from 51aa5bc4, the export from the box's IGSD1 streams, the packs test and the full suite on box 2 at 16 cores, then the push; readiness about 01:35 UK. The 0.3.24 kit zip (packs-ca3-v5-20261007T221001Z.zip) carries the old derivation text in its program.json files: a text field only, no id, kernel or fingerprint change, so the kit stands for 0.3.24 and the shipper is told; the re-exported packs go in the next kit. THE ONE 0.3.24 KIT, NAMED for the shipper (01:1x BST): packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 the pin pairs with; the fleet keeps placing it. The 23:11 zip packs-ca3-v5-20261007T221001Z.zip (sha256 4aaf9b9e..., /srv/artefacts/packs/ on build-1, from class-v5 7f58af97) carries the same packs, ids, kernels, leaves, fingerprint and derivation text and differs only in the merged kit host code and scripts beside the packs; it is the bench lanes' kit for the fingerprint jobs. The coordinator's earlier line naming 4aaf9b9e as the 0.3.24 kit was wrong and is corrected here. THE SPEC-TEXT READ-BACK RUNNING (adv-accept-3's Q4c, 01:11 BST on build-2, lease pool 16 --min 8 class adv): the same 400 epoch seeds re-derived from the spec text at master 8b834634 alone (1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7, 1.13.1; a fresh text interpretation), compared field for field with the chain draw; the count about 01:21. One sentence already named divergent before the count: 1.4.6 part (c) cites dataset_elem(idx, S[0], S[1]) "of verify.rs" without stating its six operations, so part (c) cannot be computed from the text alone and the derivation takes that one function from the crate; the audit lane is to state the closed form's six operations in the text or the constants table, else 1.4.6 stays code-dependent on that line. A NINTH LIVE HOT SET (adv-accept, 01:12 BST): seed 228763 (id 2c4be0f6dc44c423, stand-in 0.9820) at 2^24 (X at 0.1 percent +0.118, 1.82x the window model), its single hottest item 0xe2cc96 at 1,218,380 reads, 0.057 percent of ALL reads, the largest single item of the pass (40x 100767's), from a NON-saturated source r0 at site 9 (the sel register), saturated-source share 0.000: the third shape at scale, a value-level concentration neither (c') nor a saturation test can see by construction; its 2^20 ratio against the 0.995 floor lands in minutes and decides whether the floor's instrument reaches it (if missed, the exemplar for the next class's non-saturated case). 638990 reads 1.51x beyond the gate with one item at 0.027 percent (r0, no saturation), no hot set; 623492 clean. Tally: 9 hot sets in 37 tail seeds against 0 in 20 random, 269,250 programs drawn; the price unchanged at 1.002x (0.27 percent of reads on 1 MB; one item 64 bytes). The public sentence's "eight of eight" moves to "nine of nine" or gains the first miss when the ratio reads. THE FLOOR REACHES THE NON-SATURATED SHAPE (adv-accept gap-tail3, 01:13 BST): seed 228763 reads minimum site 9 at 0.9809 at the 2^20 sample, the lowest of the pass, REFUSED; 638990 site 2 at 0.9872, REFUSED; 623492 (clean live) site 0 at 0.9922, REFUSED, a seventh false refusal. Final tally over everything the lane read at 2^20: 9 of 9 live hot sets refused (0.9809 to 0.9919), both single-item programs refused, 7 clean-live programs refused and 1 passed among the 12 deepest 256-unit seeds, 3 mild residuals missed at about 1.0004x. The reading: the distinct-index ratio reads any few-item concentration whatever its source, saturated or not, and misses only the diffuse era-stride excess; the class v5 floor closes the hot-set class entire at the 2.4 percent clean-rejection cost; the next class's value-level test is for the diffuse class alone. The public sentence reads "nine of nine hot sets refused" from here (the v5 lane's follow-up cfce57ea rides its push; AP-F8-1 on master updates with the next record commit). THE FAST-TIME GATE ON dfbd1e10: SUMMARY PASS (cross-0324-dfbd1e10) at 00:12:57Z on 8 October (01:13 BST), the shipped re-cut's binaries (igneumd 4870ccf2..., igneum-miner aa8c2978..., igneum-pow 1c420786), build-1 under lease pool class v5, 23:58:56Z to 00:12:57Z, every check green: rung 1 by signal at epoch 6 (00:05:37Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (00:07:46Z, 4 of 4, 9,985 bps), 12 of 12 ids equal to the CPU verifier's, the stale node 95 of 95 refused, the restart step across the boundary on a kept datadir resynced in 36.2 s with the catch-up done after 11 s (4 IsInIBD refusals of its own miner during it, 0 of its blocks accepted), four sinks equal at 661, 0 PoW rejections on the honest nodes; record on v5-fasttime 0a09eb78, docs/design/class-v5-harness/fasttime/cross-0324-dfbd1e10.json. Every gate on the pin is green; the move waits on the pairs on the dl host, the last FETCHED plus ten, and the F9/F1 interim read. THE RE-EXPORT READ (the v5 lane, box 1 with the merged crate ac285733): the three pinned packs' only difference was program.json's program_id_derivation text (generator 4 now "|| 'sub/' || sub_version_le16", generator 5 the class recipe "igneum-program-rw/ ..."); ids, kernel texts, leaves.bin, vectors and the fingerprint 82b19cbde8557ea5 byte-identical; the pinned packs carry the merged text; the full gate and the full igneum-pow suite with the packs test and spec_readback running on that tree, the push and commit string about 01:45 UK; main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2 at class-v5 b5d6368d (nothing with eight of eight reached the mirror). AP-F8-1's two eight-of-eight lines on master move to nine in this record commit. THE MOVE'S SOURCE (the shipper's ruling at 01:05 BST, corrected to this record at 01:1x): the 02:00 BST move does not wait on the build-server lane's pairs; that lane is dark (nothing published since 23:05 BST, nothing answered since 00:17), so the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair at /srv/artefacts/0324-dfbd1e10/node-lane on build-1 (igneumd 4870ccf2, igneum-miner aa8c2978, the pair every gate ran on, native glibc 2.39 on every fleet box), the way dn3-g1 and g2 moved at 22:30; the fleet's puller fetches from build-1, not the dl host. The move waits on the fleet publishing the dfbd1e10 move file and naming the minute (asked 01:05) and the F9/F1 interim at 01:55. The hive and the Windows pairs are the dark lane's loss for tonight unless main gives the shipper the word to build them (asked 01:06); the Mac entry publishes at the minute regardless; if the fleet has not published the move file by 01:40 BST, main and the coordinator hear it with the clock. THE PC 1 LOCK VOID, THE V5 AMD BENCH PUBLISHED (the hash lane, 01:1x BST): the shipper's 0.3.24 host job was never published to the jobs file, so the slot was void (the shipper's "slot void" at 01:05 BST); the v5 kit fetch landed on both PCs at 00:12:06Z (919,273 bytes, sha256 ok); run-ca3-pc1-v5-amd-bench-20261007 published 00:14:19Z (the 9070 XT by name, about 3 minutes, lock-free), its start line printing app_version, so the 0.3.20 or 0.3.23 reading of PC 1's app comes with the fingerprint; PC 2's Arc job needs only the shipper's "PC 2 clear". PC 1's app had NOT taken the 0.3.23 kit as of the last reads (every job log through 21:46Z app_version 0.3.20; the install folder's exe igneum-app 0.3.20, mtime 12:24:42Z, sha256 0443ae17...). The update-return lane (a22d765a2e0355a9f) last spoke at 23:0x BST: the helper workaround for 0.3.20 scripts (truncate cmd.txt, restart the task, wait for helper.alive, then write; or four leading " dev " padding lines), the locked jobs held as they are, power-helper-24 b9a72b9b merged into release-0.3.24 (daa7427b: a silent change becomes a logged line, the helper writes its exit reason), install-close-23 4ad6c199 for 0.3.23's take 3, the re-probe job when PC 1's app has taken the 0.3.23 kit; nothing since. THE SPEC-TEXT READ-BACK PASS (adv-accept-3 Q4c, 01:11 to 01:15 BST on build-2 at 16 cores; report section 6.5 on build/adv-accept-3, log 983-textderive-8b834634.tsv, pushed): the spec text at master 8b834634, implemented fresh without the crate's generator or rule, reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences (every instruction, the chosen attempt, the id, the rejection sequence); the 264-of-400 divergence against the text at 017e7037 is closed, so AP-F8-5 reads fixed on a measurement. The one remaining gap: 1.4.6.4 names dataset_elem "of verify.rs" without its six operations, so parts (c), (c') and (c'') still take that function from the crate; the audit lane's one-sentence closed form (asked 01:1x) closes it, and the read-back re-runs on the new text. THE AMD CLASS V5 FINGERPRINT (PC 1's RX 9070 XT, gfx1201, beside the miners, lock-free): 82b19cbde8557ea5 at 01:16:14 BST, equal to the kit e6c088bb's on Metal, Apple OpenCL and CUDA, self-test PASS, the v4-genesis control 892b6d55a7ddcfcb PASS; the 0.3.24 kit stands on four platforms; Intel waits on PC 2 (held until main's word, since the 0.3.23 take 3 never ran there); PC 1's queue continues with the CA4 unlocked rows. The kits row reads: Metal, Apple OpenCL, CUDA, AMD equal; Intel not measured tonight. THE UPDATE-RETURN LANE'S THREE READINGS (01:17 BST, from the live manifest and the intake): (1) 0.3.23 take 3 (install-close-23 4ad6c199) never reported; the live manifest igneum-app-latest.json reads 0.3.23 published 20:37:44Z with platforms = {mac} only, NO Windows entry, so neither PC has anything to take through its update path; PC 2's app run is still take 1's relaunch from 21:08:43Z (997 uploads, last 00:16Z); (2) PC 1 will not take 0.3.23 unattended tonight for want of a Windows entry; its run win-ae432dc7-20261007-160110 (0.3.20) never restarted (2,376 uploads, last 00:16Z), mining 18.96 MH/s on the 9070 XT; when a Windows entry is published the 0.3.20 engine's OTA takes it with no hand; the 21:41:32Z helper.ps1 write was not the prompt path (0.3.20 writes that file unconditionally), so no screen is owed in the morning for it; (3) the re-probe job (relay/playbooks/pc1-helper-reprobe.ps1 on power-helper-24 69f3c733) waits only on PC 1's exe becoming 0.3.21 or later; the 0.3.20 workaround is cleared to run tonight as a lock-free job so the locked grids go ahead: per grid job, before the first command, empty sweep\cmd.txt, Stop-ScheduledTask and Start-ScheduledTask 'Igneum Power Helper', wait until helper.alive is within 4 s, then write the lines with climbing sequences (in 0.3.20 the skip is the line count at the helper's start, fixed for its life); the helper idle-exits 20 minutes after its last command and the next start must begin over an empty file again; never pad after a command. The coordinator's order to the hash lane on it: the locked grids proceed in the earlier order (the 5080 full grid, the third 5090 pass to the driver's floor, SM-sparse, the two Ember tunes, the hot-table ldcs rows), each with its restore step, under the no-prompt rule; a Start-ScheduledTask that reads the 0x800710E0 refusal again stops the job and reports, nothing escalates. THE LOCKED GRIDS UNDER THE WORKAROUND (the hash lane, 01:2x BST; commit 24f9858e on the mirror): the three lock scripts carry the cleared sequence (empty sweep\cmd.txt, Stop- then Start-ScheduledTask 'Igneum Power Helper', helper.alive within 4 s with a 60 s cap, then dev + command with climbing sequences; repeated before any write when helper.alive is older than 10 s; a refused start 0x800710E0 or no heartbeat stops the lock path with the text on RESULT lines, nothing escalates; no padding; each grid job ends with rgc through the same sequence and the applications clock read back). PC 1's app_version on the v5 bench's start line: 0.3.20 (no Windows 0.3.23 published, nothing to take). The CA4 SM-sparse job run-ca4-pc1-ca4sparse-5090-20261007 runs since 00:20:40Z on the earlier padded script (unlocked rows first, then its 1,300 knee attempt; about 25 to 50 minutes); then in order on the shipper's acks: the 5080 full grid as run-ca3-pc1-v4-eff-5080-20261007-d, the third 5090 pass (1,100 MHz down), the microbench and the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the 5080 grid's knee and best points to the site audit lane for row 17 as read. THE ATTEMPTS CENSUS COMPLETE (adv-accept row 90, 01:34 BST, 20,000 seeds, closing the partial named at 00:00): 42,711 rejected candidates; (a') 83.5 percent, (a) 11.6, (b) 3.0, (c'') 1.1 (459 candidates), constant bit 0.4, saturated 0.3, (c') 0.05, distinct 0.04, lane-constant and bias 0; per-candidate rejection 0.681, flat across attempts 0 to 3 (the halves agree to a tenth of a percent); accepted-attempt mean 2.136, max 28; 0 exhaustions; P(256 consecutive rejections) 2e-43 per seed. The number for spec 1.4.6: under sub-version 3 the per-candidate rejection is 68.1 percent and the expected attempt 2.1. adv-accept's shards run on in the pool's gaps under the mechanical yield; the box-hours cross 8 later tonight. CLASS-V5 LANDED ON BOTH MIRRORS (the v5 lane, 091a0758 at 01:40 UK): the full pre-push gate GREEN at 71 checks (stamp on 48d38493, the last code change); the igneum-pow suite on box 2 (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs byte-identical to the merged crate's export, so e5a4ac5978462156, 7c54302b487340a1, a217c7f698880830 and 82b19cbde8557ea5 hold under master's recipe form, recheck 2, scratch 7, spec_readback 2); spec-constants 28 rows agreeing; identity grep 0 hits. Carried since 61588347: main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2; the 61-row era reading and the class v5 attempts census on the spec, the page and the ledger; AP-F8-3; spec 1.4.7 and 1.8.6 with the constants and id tables; the AMD fingerprint row; the kits branch and master merged; two corrections the proofs found: master's program_id_derivation text lacked the class v5 rung-0 arm (the v5 packs' text named the class recipe while the id was the plain form; the arm added to the TEXT, re-exported, ids unchanged; a post-freeze change on the class-v5 line, so 0.3.25's pairing, never 1c420786's), and the public-export scrub (the founder's name six times on the page, the zone name in three files; gone). Incoming to the page: the Arc fingerprint, F9 and F1. THE MOVE FILE NOT PUBLISHED (the shipper, 01:41 BST): build-1's /fleet/move.json still names commit 2720d8d2 with the 22:30 BST minute; no FETCHED count, no named minute; the fleet lane (ac055d60427caab99) has answered nothing since its 22:4x report (asks at 01:05, 01:16 and 01:41; its task output last written 22:21 BST, its last action a hand read of dn3-g1's proven share), the second dark lane beside the build-server lane (last written 22:36 BST). So 02:00 BST cannot hold; the 02:53 BST ceiling (DAA 32,400) stands only if a signed move file lands at once and the 34 pullers fetch inside forty minutes; main has the clock line with the two options (wake or replace the fleet lane; or a fourth re-cut from a morning minute, the Mac entry standing down with it). The publish record's shape stands: the Mac entry at the minute (staged, DMG 1aa301cc, both folders, armed); the hive and the Windows pairs on main's word; the pairing 1c420786, 091a0758 0.3.25's. Every other gate on dfbd1e10 green and recorded. THE RUNG-0 ARM CONFIRMED (the v5 lane, 01:4x UK): 987e90e8 touches only Program::program_id_derivation, the text in program.json; Program::program_id untouched (the v5 rung-0 plain-form branch since the freeze); the crate at 091a0758 and 1b5684ec (master 35602b30 merged, pushed 01:41 UK) derives every pinned id byte for byte (packs 20 on box 2 comparing all three pinned packs' files including program_id and leaves.bin; spec_readback 2); the shipper told 091a0758 and 1b5684ec are 0.3.25's pairing, 0.3.24 on 1c420786. THE SM-SPARSE JOB (run-ca4-pc1-ca4sparse-5090-20261007, exit 0 at 00:41:53Z, 1,171 s, the 5090 alone, every fingerprint matched, the Power Helper answering every command on the padded write, the card left unlocked at 2,855 MHz): the SM-sparse reading does NOT exist; the research lane's worker ran its base kernel on every variant row (its race line "race 0 ms variant base" on all 48 rows, no NVRTC compile text), so --bench never honoured --variant sp-w32; the sparse rows equal base in rate and drift in watts with the card's heat only; the rerun waits on the research lane's exe honouring the flag. What stands: a repeat of the efficiency pass at two states, 32 s rows, the card alone: v4 unlocked 137.07 MH/s at 465.5 W (0.294 MH/W), at 1,300 MHz 134.26 at 309.9 W (0.433; 155.6 W back for 2.05 percent of rate); v3 unlocked 136.71 at 331.6 W (0.412), at 1,300 134.03 at 219.4 W (0.611; 112.2 W back for 1.97 percent); the v4 premium 133.9 W unlocked, 90.5 W at the knee; the three power fields agree within 0.2 W on every row (power.draw = instant = average on driver 617.14), which settles the field question on PC 1's side and leaves the 5080's 110 W gap to the fleet's rented card's sampler. Next on the shipper's ack: the 5080 full grid (-d) through the cleared helper sequence, the third 5090 pass, the microbench, the seven packs, the two tunes, the hot-table ldcs rows (kit and job at 292fcc75). THE --variant FAULT FIXED (the research lane, counter-asic-4, UTC clocks on 8 October): 00:44 the fix (a --bench with --variant runs the pinned race and installs the named kernel; the RESULT line carries variant=, sparse_blocks=, block_warps=; a served kernel other than the requested one prints variant_not_installed); 00:46 the known-failed test on build-1 against the real class v4 pack, no card (base: race off, 524,288 blocks of 32, "variant base"; sp43-w32: race on, 43 sparse blocks of 32 warps, the rewritten kernel with the nonces argument and the unit function, 43 blocks of 1,024; PASS; before the fix both read the base shape); 00:46 the Windows exe igneum-worker-cuda-ca4sparse3.exe sha256 0ba97edcd5c46a302a7ff5ddd1bbb1e493ca15f64d0757820ed645972df3bb56, mingw exit 0; the commit after 2d0013d1; the hash lane has the sha, the test's lines and the rerun's job shape (the same 48 rows, the race line per row); the op-mix re-weight stays behind the SM-sparse reading, the served 3.4x standing; the clean efficiency repeat in the file's 20.3a (6.6 pJ per counted op). THE SPEC'S LAST CRATE-DEPENDENT SENTENCE CLOSED (the site audit lane, master 56eebc0d at 01:49 BST, gate GREEN on c2c92eab, 71 checks; spec_readback now 3 tests): 1.4.6.4 states dataset_elem in full (the eight operations, the three constants, 32-bit wrapping) with two pinned vectors (dataset_elem(0x00000fed, 0x9E3779B9, 0x7F4A7C15) = 0x5c7dabd2; dataset_elem(0x0fffffff, 0, 0) = 0x7662c1ec) that spec_readback.rs reads from the text and checks against the crate, so part (c) computes from the text alone (34845c47); 1.4.6.5 names the class v2 figures as class v2's and carries the shipped rule's own census sentence (20,000 seeds, 68.1 percent rejected per candidate, the per-part shares, mean attempt 2.1, max 28, 0 exhaustions, 2e-43). The text-derived re-run on this text is the proof it is sufficient end to end (asked of adv-accept-3). THE MOVE FILE STAGED (the shipper, 01:5x BST): id mdfbd-1, commit dfbd1e10, want_digest b1ba7822, both pair slots on build-1's served tarball dfbd1e10-node-lane.tgz (e59ed0e6), at_epoch 0, signed with the fleet key on the Mac and verified against the fleet's public key in the puller's namespace; the read-back on placing it: the served file's id by curl and the first FETCHED on the relay intake; the 34 pullers fetch inside their one-minute timers (27 MB from build-1), the last FETCHED about five minutes after the file, the earliest minute ten after that. THE REAL LATEST-PUBLISH CLOCK: the file alone halts every miner on the restart, because each box's pack gate PAIR_MINER_SHA16 lacks aa8c2978 and the puller does not carry the file's miner sha into the restart environment; so route (A) also needs one ssh line on each of the 34 boxes before the minute with the fleet's tooling (the fleet lane's, or the shipper's on main's word). Absent main's word by 02:15 BST the shipper stands the Mac entry down under the ceiling rule (no app alone on b1ba7822) and 0.3.24 becomes a morning minute with a fourth re-cut. ROUTE (A) STAGED TO ONE COMMAND (the shipper, 01:5x BST): the gate script r0324/move/pair-gate-aa8c2978.py in its scratch (dry run by default, apply on the literal argument, the fleet's own Box helper and label list, nothing restarted); the dry run read 33 of 35 boxes, every one carrying the old gate list with fb147dd1 last and aa8c2978 absent, no env-last override; unreachable dn3-relay and p2-4090-1b (dead Vast proxies; they fall off at the move and rejoin by the pull); the apply about 90 s for the 33 with each gate read back and counted. THE F9/F1 INTERIM (the attack-pass lane, read at 01:5x BST): 71,292 seeds, 0 exhausted, 0 panics, max attempt 30; F1 0 failures at 2 h 23 min; the move's gate reads clear. On main's (A): apply 02:00, the file placed 02:02, the last FETCHED about 02:05, the minute 02:15 BST; main has the clock. Nothing applies before the word. THE SPEC TEXT SUFFICIENT END TO END (adv-accept-3 Q4d, 01:52 to 01:57 BST on build-2 at 16 cores; report section 6.6 on build/adv-accept-3, log 984-textderive-56eebc0d.tsv, every row equal to its Q4c row): the spec text at master 56eebc0d, implemented with nothing from the crate (text.rs: 0 igneum_pow imports; dataset_elem from 1.4.6.4, its two pinned vectors checked at start), reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences on every field; no sentence of the generator or acceptance sections needs the crate; the documentary finding (AP-F8-4, AP-F8-5) closed in full on two measurements; the lane at its end, 3.35 box-hours in all. F9 AND F1 AT 00:59Z (class v5 at 1c420786, pairing e5a4ac5978462156, build-1): F9 73,691 of 100,000 chain-shaped seeds written, 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; the attempt histogram 23,119 / 15,981 / 10,805 / 7,547 / 5,181 / 3,415 / 2,439 / 1,653 / 1,119 / 744 / 529 / 389 / 258 / 152 / 113 / 72 / 54 / 40 / 31 / 14 / 15 / 5 / 2 / 6 / 2 / 4 / 1 at 26 / 1 at 30, r about 0.69; the 10^5 about 01:30Z (02:30 BST). F1: the 10^5 redundancy census at 2 h 28 min under its lease with no end marker (18 minutes on an idle box; under tonight's load no minute named); its panic path live and empty, 0 failures the honest reading. Both land as record lines, then the board's close per item on sub-version 3 and class v5. AP-F8-5 ON TWO MEASUREMENTS (the site audit lane, commit 116e6055, master 5c77a7ac at 02:05 BST, gate GREEN 71 checks): the row carries Q4c (8b834634, 0 of 400 with one crate function, section 6.5, log 983) and Q4d (56eebc0d, 0 of 400 with no crate import, section 6.6, log 984); the public ledger and the ledger page regenerated; nothing open in the spec or the ledger on the audit lane's side. THE 5080 FULL GRID (run-ca3-pc1-v4-eff-5080-20261007-d, exit 0 at 01:54:00Z, 4,118 s; PC 1's dock card alone, driver 617.14, app 0.3.20, mem 14,801 MHz throughout; every lock through the cleared helper sequence, every command answered first time, every fingerprint matched, clocks reset and read back): the knee as a reading: the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes (v4 71.19 of 71.41 MH/s; v3 71.11 of 71.28) and falls 5.2 percent at 900 MHz on v4 (67.66), where the 75-minute budget ended the grid (v3's 900 and below not taken; the drift check skipped); so the 5080's knee sits between 1,000 and 900 MHz, a third of its 2,963 MHz boost, lower than the 5090's 1,300 (84 SMs at 2,960 MHz have more compute headroom per unit of its 960 GB/s than the 5090's 170 SMs per unit of 1,792 GB/s; the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: v4 at 1,100 MHz, 71.20 MH/s at 146.6 W (0.486 MH/W; 106.5 W recovered for 0.29 percent of rate); v3 at 1,000 MHz, 71.11 at 103.7 W (0.686; 66.0 W for 0.25 percent). The v4 premium 83.4 W unlocked (253.1 against 169.7), 41 W at the best points (146.6 against 105.6 at 1,100). Per tier: a 5080 owner on class v4 locked near 1,100 MHz draws 147 W instead of 253 for 0.3 percent less rate (MH/W up 72 percent) and the shadow's residual cost is 41 W. Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 71.41/253.1/0.282 ; 71.28/169.7/0.420 (sm 2,963/2,977); 2850 71.41/229.5/0.311 ; 71.29/155.3/0.459; 2700 71.41/209.6/0.341 ; 71.29/149.2/0.478; 2550 71.41/193.0/0.370 ; 71.29/134.4/0.531; 2400 71.41/176.0/0.406 ; 71.29/128.7/0.554; 2250 71.41/165.6/0.431 ; 71.28/117.3/0.608; 2100 71.38/157.7/0.453 ; 71.28/112.3/0.635; 1950 71.37/154.0/0.463 ; 71.26/111.6/0.639; 1800 71.35/150.3/0.475 ; 71.24/113.4/0.628; 1650 71.33/151.4/0.471 ; 71.22/109.7/0.649; 1500 71.30/149.2/0.478 ; 71.19/110.6/0.644; 1400 71.27/149.6/0.476 ; 71.16/107.0/0.665; 1300 71.24/147.9/0.482 ; 71.14/107.7/0.661; 1200 71.20/149.4/0.477 ; 71.12/104.4/0.681; 1100 71.20/146.6/0.486 ; 71.11/105.6/0.673; 1000 71.19/149.0/0.478 ; 71.11/103.7/0.686; 900 67.66/137.8/0.491 ; not taken. Throttle reason 0x400 (the power governor) on every row, never the clock lock, so the draw floor of about 147 W (v4) and 104 W (v3) from 1,500 MHz down is the memory system plus idle, not the SMs: the clock lever is spent by 1,500 MHz on this card. The three power fields agree within 0.2 W on every row. The site audit lane has the knee and best points for row 17; the bench table's 5080 row takes "71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", class v4 cost "+83 W unlocked, +41 W at the best points", hive core 1100 (the mem clock unchanged) once the fleet's rented-5080 sampler question is closed. Next on the shipper's ack: the third 5090 pass, the SM-sparse rerun on the fixed exe, the microbench, the packs, the two tunes, the hot table. THE NIGHT'S MOVE OUTCOME (the shipper, 02:58 BST): main's word on (A), (A') or (B) did not come (asked 01:41, 01:50, 01:53, 01:56 by the shipper and 01:42, 01:52, 01:5x, 02:00 by the coordinator); the gate script not applied (the dry run's 33 of 35 the only read); the move file not placed (build-1's /fleet/move.json serves m2720-1, 2720d8d2, the 22:30 minute, by curl at 02:56); no move minute; the stand-down under the ceiling rule holds from 02:15 (the shipper's stand-down line at 02:15 was not sent, its miss, the state unchanged); the Mac entry standing, not published (staged on DMG 1aa301cc in both folders, the live manifest at 0.3.23). A FINDING: build-1's Devnet 3 seed (the process on 26631 with JSON RPC 27632, the node lane's DAA reader) is DOWN (no such process; node1-dn3 26671 and the observer 26651 run on 2720d8d2; the node lane's 0.3.24 reader on 28690 runs but answers no DAA by the envelope tried), so the node lane's DAA reads since 25,169 at 00:52:38 BST may have stopped with it; at 1.0 DAA/s the DAA passed 32,400 at about 02:53 BST, the 39,600 floor is lost, and the fourth re-cut is from a morning minute main names (before 12:50 BST, or the three heights move with the floor). Every Devnet 3 node is on the 0.3.23 pin 2720d8d2, digest ba75bf6f (the 22:30 move; dn3-j1 behind its proxy unverified since); nothing of 0.3.24 is on any box or in any manifest. The night's 0.3.24: every gate green on dfbd1e10, the kit on four platforms, the move unmade for want of one word and two dark lanes. THE ATTACK-PASS BOARD'S CLOSE (lane (d), 01:58Z on 8 October; record docs/analysis/attack-pass-2026-10.md on the mirror's attack-pass; box-hours approximate: build-2 about 7 h, build-1 about 9 h plus about 6 h of F6 batches and F2 solvers earlier in the day). F9 so far: 89,301 of 100,000 chain-shaped seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 20: 20, 21: 6, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1; r about 0.69), three chunks on their cores to about 02:20Z; F1 the 10^5 redundancy census at 3 h 22 min on 17 threads, healthy, no end marker, 0 failures on its live panic path. The board: F1 shadow redundancy PASS on sub-version 3 (max 5.078 percent at honest-compiler parity; AP-F1-1 on the v5 list at 3.0 percent), running on v5; F2 mixer round margin PASS effort-bounded (no trail under weight 20 to 24 at 2 applications, 29 to 35 at 3, 39 to 47 at 4), not re-run on v5 (the mixer unchanged); F3 chained cache j+1 PASS, not re-run; F4 weak-day census PASS on v4 on the DSP-bound metric with AP-F4-1 reconciled with adv-mixer-2 (median 226, 15 days a century, worst 2050-04-28 at 1.113x), on v5 PASS at 8ca66afa (0 of 2^24 days over 1.1x on both metrics, AP-F4-1 FIXED-AND-PASSED); F5 chip-model sweep FIXED-AND-PASSED (the F2 hour skipped by decision), not re-run; F6 verifier worst case PASS (worst of 10^5 at 8.708 ms half-core; O-1.14 closed, i7-9700K 6.334 ms), not re-run; F7 era draw PASS on all three (0 of 6 re-rolls), not re-run; F8 uniformity FIXED-AND-PASSED on sub-version 3 (60 of 64 under 1.2x; AP-F8-1, 2, 3 closed), PASS on v5 (61 of 64, worst 1.50x, the residue p4, p8, p10; p34 under); F9 edges, hot set, grinding PASS on sub-version 3 (34 of 105,064 edges bounded; grinding +0.004 percent), the exhaustion count running on v5; F10 ladder signal PASS, not re-run (node rule). Findings of the pass, all in-house: AP-F1-1, AP-F4-1, AP-F5-1 (the X9), AP-F8-1, AP-F8-2, AP-F8-3; two operating hazards fixed (AP-H1 the box clean, AP-H2 the shared binary path). The open tail (p4, p8, p10, and p34 on sub-version 3) is named in the public report; no outside party holds it (the attack-pass lane's close wrote "disclosed to the firms", stale wording from before the in-house ruling; its record file is to say "named in the public report"). THE SEED'S DEATH AND THE DAA NOW (the node lane, 03:0x BST): build-1's Devnet 3 seed log /home/build/dn3seed.log ends at 01:09:05Z at DAA 29,732 mid-stream with no stop, shutdown or panic line, so it was killed abruptly (it ran under nohup from a shell, not a unit; no journal names the killer; the OOM record needs sudo the lane lacks); its datadir /home/build/dn3seed/igneum-devnet-3/datadir is intact (13 GB) and it stays down until the shipper says; the lane's reads 25,169 at 23:52:38Z and 28,906 at 00:55:09Z came from it while it lived. The DAA now from node1-dn3 on 28670: 32,659 at 01:57:50Z (the observer 32,660), both on 2720d8d2; the chain passed 32,400 at about 01:53Z, 39,600 lost. The fourth cut in one line: the script on release-0.3.24-node reads the DAA from 28670, sets the floor to the morning minute's publish DAA plus 7,200 rounded up to the next 3,600, commits, pushes both mirrors and dispatches the gate set (about 20 minutes to the pin line, then the fast-time pair about 14); the latest minute before the three heights move with the floor is about 11:50Z (12:50 BST), where the floor reaches 79,200; nothing is cut until main names the minute. A morning item for the box owner: a process on build-1 was killed at 01:09:05Z without a log line while the box carried a load of 400 to 600; the killer (OOM or a sweep's cleanup) is to be read from the journal with sudo before anything long-lived runs there again under nohup. THE BENCH LOG ENTRY (the hash lane): docs/bench-log.md "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080" (both cards' full tables, the knee per card, the best MH per watt points, the premiums at the lock, the lever's limits, the job ids and clocks, the rented-5080 watts note) on the mirror's master as merge 773b93a8 at 02:04:47Z (commit 11c698ad); the audit lane writes row 17's sentence from it. PC 1: the third 5090 pass run-ca3-pc1-v4-eff-5090-floor2-20261007 (1,100 MHz down to 300) since 01:57:03Z, about 28 minutes; then the SM-sparse rerun. ROW 17 AND THE 5080 BENCH ROW (the site audit lane, master 2c5c7f52 at 03:19 BST, gate GREEN on 6eb6fd9b, 71 checks): docs/evidence.md row 17 carries both cards' efficiency passes from the bench-log entry (the 5090's knee, best points and premium; the 5080's 71.41 MH/s at 253.1 W unlocked, 71.20 at 146.6 W at 1,100 MHz, v3 at 1,000 MHz 103.7 W, the premium 83.4 W to 41 W, the knee between 1,000 and 900 MHz, the per-tier reading, the Ember Tune lever), a what-moved table for 8 October, /evidence rebuilt (865a0a5e); site/miner-bench.json's RTX 5080 row states the team's pass as the card's figure ("71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", "+83 W unlocked, +41 W at the best points", hive core 1100 with the memory stock, driver 617.14, the bench-log entry as the source) and keeps the rented-fleet sampler reading with its 110 W gap as the open question; /miners rebuilt at 35 rows (6eb6fd9b); 0 identity hits; nothing deployed, the deploy the morning hand-off. The design pass on ca3-coord (015cc839) now sits behind this master and rebases onto it before its own landing on main's word. THE DESIGN PASS REBASED (the coordinator, 03:2x BST): ca3-coord rebased onto master 2c5c7f52 as the three site commits only (f5b7140c the design pass, 8cc4cbc6 the phone grid, 9ad3fdc9 the six-column row; the two commits already landed through the record branch skipped), site/miners.html rebuilt at each from the merged miner-bench.json so the page carries the 5080's new row ("71.4 stock (71.2 tuned)") under the design; the diff against master is build.mjs and miners.html only; pushed to the mirror (pre-push GREEN); it lands on main's word after the captures, one gate run. ADV-MIXER-3's LINE (read from its report at tip e02297ae, 03:18 BST): queue 17 finished on build-1 at 01:3x BST; Q2 single-bit avalanche at 2^27, k = 2 and 3 on day 20729: 0 holes, 0 cells beyond 6 sigma at band 0.00026, PASS (the k = 1 finding stands as the single-application diffusion); Q2b t-bit avalanche on day 20733 at 2^28: 0 cells beyond 6 sigma at band 0.00018, PASS (k = 2, 3, 4 on 20729 at 2^28 the same); Q3 at k = 8 NOT run (killed at 20:20 BST under the lease rule, not re-queued; k = 2 to 7 clean with 0 deterministic bits on both days), named partial; Q6 the day-20733 SAT ladder: k = 2 and 3 TIMEOUT at the one-hour cap, k = 4 on one build-2 core since 03:05 BST, its cap about 04:05; one pre-emption in its ledger (23:58 BST, 21 minutes of a 2^27 row lost, re-queued); box-hours about 3.0 wall-hours of sweep (build-1 1.9, build-2 1.1) plus about 4 single-core CaDiCaL hours, about 7 with the 20733 ladder. The pass's close with the per-lane table and totals at about 04:05 BST; section 13 on crypto-engage (docs only) merging the current master and going through the gate to the mirror's master so the record cites a master commit. Box 2 at 03:20: adv-accept 87 cores in four shards with three waiting, adv-mixer-3 one core; build-1 load 34, no adv lease. THE DESIGN PASS'S OVERLAP ON THE BOX (the CI steward, 03:33 BST): the 1440 and 390 dark captures of /miners from ca3-coord 9ad3fdc9 taken on build-2 under lease pool 4 (Playwright chromium 1194, the recorded feed; /srv/artefacts/captures/ca3-coord-9ad3fdc9/miners-1440-dark.png 1440 x 4280 and miners-390-dark.png 390 x 9779); the overlap sweep on the same checkout, 390 to 1600 px, light and dark: RED, 3 findings on the change itself: at 1280 px dark and 1600 px light and dark the date span in the lead cell's class v4 line is COVERED by the rate cell (4 of 5 sample points under td.big); 390 to 1024 pass. Cause: the branch's last gate ran on the Mac, which has no browser, so the sweep skipped and read GREEN; on the page the row rule's white-space:nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell from 1280 px up. FIXED at ca3-coord 2ca45001 (the lead cell's rule at the row rule's specificity, max-width 360 px, the class v4 line wrapping with overflow-wrap), rebuilt, pushed; the sweep and the captures re-run on the box before main's word. THE IN-HOUSE PASS'S PATH TO MASTER (the crypto lane, 03:2x BST): adv-accept's box-hours crossed 8 before 02:00 BST and sit near 10 (87 cores in four shards; it sweeps on under the mechanical yield, its reading unchanged); crypto-engage merged master 56eebc0d at 342b6730 (one conflict in funding.md, the pre-public scrub against the rewrite, resolved to the in-house pass with the scrub applied; the founder never named in in-house-pass.md or funding.md), the full gate running, merge-to-master on GREEN; section 13.3: master's igneum-pow moved after the freeze in four files (src/emit.rs and src/generator.rs, the derivation string and its recipe helpers, ids unchanged; tests/derivation.rs and tests/spec_readback.rs), none the hash, so the object the pass bounded is unchanged in every operation the hash performs. THE PASS IN ONE LINE (the crypto lane, 03:2x BST): eight of nine lanes closed, adv-mixer-3 on one SAT timeout (about 04:05 BST), adv-accept sweeping to its 16 box-hour line (9.2 now, the reading saturated at the 1.002x class), adv-cache-2 on one line shard; no break of class v4 sub-version 3; the acceptance's hot-set class closed by the class v5 floor (9 of 9) and its diffuse era-stride class routed to the next class; the weak-day FPGA tail reconciled and closed by a measured redraw rule; the attempts census complete; the spec text proven sufficient by two read-backs; one pod at USD 0.33 in the whole pass, none originated by the lane. THE THIRD 5090 PASS BELOW THE KNEE (run-ca3-pc1-v4-eff-5090-floor2-20261007, running at 02:34Z on its 500 MHz step; the steps lengthen as the rate falls since the batch count was sized from the unlocked rate, about 155 s at 500 against 60 at 1,100; the helper answering every command on the cleared sequence, every fingerprint matched, the 5090 alone). Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 137.09/456.7/0.300 ; 136.79/320.0/0.428 (sm 2,858/2,862); 1100 120.98/275.9/0.439 ; 117.32/198.6/0.591; 1000 110.03/254.9/0.432 ; 106.73/180.2/0.592; 900 97.43/232.7/0.419 ; 94.33/174.5/0.541; 800 86.00/216.3/0.398 ; 83.41/166.6/0.501; 700 75.98/202.7/0.375 ; 73.58/156.4/0.470; 600 65.30/178.2/0.366 ; 63.25/153.3/0.413; 500 53.03/166.5/0.319 ; v3 running. Reading: below the knee the rate falls about 10 percent per 100 MHz on both classes (compute-bound: the shadow and the base program no longer fit the memory wait) and MH per watt falls with it from 1,100 down, so the best point stays where the second pass put it (v4 at 1,200, v3 at 1,300); the driver took every lock down to 500 (the SM clock within 10 MHz), so the floor is below 500 MHz and is not where the optimum lives; the v4 premium below the knee 77 W at 1,100, 75 at 1,000, 58 at 900, 50 at 800, 46 at 700, 25 at 600 (the ALU work shrinking with the clock as the rate does). The exit line, the 400 and 300 rows, the drift check and the restore at its close; then the SM-sparse rerun on the fixed exe (each sparse row reading served= and sparse_blocks=, marked variant_row=FAILED if served as base). F9 AND F1 AT 02:34Z (class v5 at 1c420786, build-1): F9 98,945 of 100,000 seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 18: 39, 19: 19, 20: 24, 21: 8, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1); the last three chunks within minutes of their ends; F1 at 4 h 02 min under its lease, no end marker, 0 on its panic path. The pass record's wording fixed on the mirror's attack-pass at 9474cea8 ("named in the public report"; no "firm", "firms", "escrow", "prize", "paid review" or "Lot" line in the pass record or the ten row records; identity grep 0 hits); the section's merge to master after the two record lines, through the full gate in a detached worktree. THE SECOND SWEEP ON THE DESIGN PASS (the CI steward on 2ca45001, 03:38 BST): the desktop widths pass; RED at 390 px dark only, three findings on the lead cell (the card name and the class v4 line covered by the rate cell), the cause the new 360 px max-width on the phone grid; FIXED at ca3-coord 5158276c (the lead-cell width rule scoped to widths above 1,100 px, the phone grid's lead cell with no max-width), rebuilt, pushed; the sweep and captures re-run on it. F9 PASS ON CLASS V5 (the attack-pass lane, class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, the last chunk written 02:34:54Z): 100,000 of 100,000 seeds drawn through the chain path (era-composed class), 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; histogram 0: 31,454, 1: 21,460, 2: 14,660, 3: 10,263, 4: 7,047, 5: 4,701, 6: 3,297, 7: 2,256, 8: 1,532, 9: 1,027, 10: 702, 11: 509, 12: 365, 13: 216, 14: 153, 15: 103, 16: 80, 17: 56, 18: 39, 19: 20, 20: 24, 21: 9, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1 (first-draw acceptance 0.3145; the mean attempt index 2.185, so 3.185 draws per seed on average; 4,862 seeds, 4.86 percent, at index 8 or above and 255, 0.255 percent, at 16 or above; the 256-attempt cap and the deterministic last resort never reached; the lane's first line read 1.993, a slip it corrected); the exhaustion gate holds for the 0.3.24 move; record docs/analysis/attack-pass/f9-grind.md and the lane (d) section on the mirror's attack-pass. F1 still running (4 h 05 min, 16 cores, 0 on its panic path, no end marker). F9's record on the mirror's attack-pass at 2bcb7e08 (the lane (d) row and f9-grind.md section (d); feature gate GREEN); F1 the one open item before the lane (d) merge to master. THE DESIGN PASS GREEN ON THE BOX (the CI steward on ca3-coord 5158276c, 03:4x BST; build-2 under lease pool 4): the overlap sweep 390 to 1600 px, light and dark, GREEN, 0 findings (the known-failed fixture fired first); the 390 px capture byte-identical to 9ad3fdc9's (the phone shape that passed before), the desktop widths carrying the wrap at 4,640 px tall; the four dark whole-page captures on build-1 under /srv/artefacts/captures/ca3-coord-5158276c/: miners-390-dark.png (sha256 9eec8f27..., 509,158 bytes), miners-1280-dark.png (1b6e636d..., 438,541), miners-1440-dark.png (87387e14..., 445,402), miners-1600-dark.png (d53973cd..., 448,545); the run log /srv/builds/bs-ci-steward/cap-out/run-5158276c.log on build-2. The branch's gate record: a full gate on the Mac skips the sweep (no browser), so the box line is the sweep's verdict for 5158276c; the branch waits on main's word on the look and lands in one gate run. THE IN-HOUSE PASS'S RECORD ON MASTER (the crypto lane): crypto-engage dab0c89f (gate GREEN, 71 checks) landed through merge-to-master.sh --remote build at 03:50 BST as master 00b8cd1b: docs/plans/cryptanalysis/in-house-pass.md section 13 (the roll-up, every lane's reading, the frozen-object note) and funding.md's in-house row and brief, scrubbed under founder-strings-check.sh. AN EXCEPTION OWNED (03:39 to 03:50 BST): the lane's first merge call used the tool's default path, which reads CI on GitHub with gh run list; GitHub is suspended and the rule says never poll it; the tool polled 21 times (each 403, nothing pushed, nothing read); the run's process outlived the task stop and the lane ended it by its pid at 03:50 BST, then used --remote build; the breach is the tool's default against the rule and the lane's for not passing the switch; no state moved on GitHub's side. The coordinator's order on it: merge-to-master.sh's default remote must refuse GitHub while the suspension stands (the CI steward, a gate-side fix with a known-failed self-test), so the rule does not rest on every lane remembering the switch. THE THIRD 5090 PASS CLOSED BY ITS CAP (run-ca3-pc1-v4-eff-5090-floor2-20261007, ended by the 45-minute cap at 02:42:05Z during the 300 MHz step, exit -1, its own finally block never ran; every row taken matched its fingerprint, the 5090 alone): the 500 row's v3 side 51.37 MH/s at 136.4 W (0.377); 400: v4 42.62/152.5/0.280, v3 41.32/131.3/0.315 (sm 390); 300 not taken; no unlocked-end drift check; the driver took every lock down to 400 (the SM clock within 10 MHz), so the floor is at or below 400 MHz. The reading: below 1,300 the rate falls about 10 percent per 100 MHz on both classes and MH per watt falls from 1,100 down (v4 0.439 at 1,100 to 0.280 at 400; v3 0.592 at 1,000 to 0.315), so the optimum stays at the second pass's points (v4 1,200 MHz, v3 1,300) and nothing below 1,100 is worth the knob's time; the v4 premium below the knee shrinks with the clock (77 W at 1,100, 46 at 700, 21 at 400). AN EXCEPTION OWNED: the 5090 sat at the 400 lock (390 MHz, 127 W mining) for four minutes until run-ca3-pc1-clocks-restore-20261008 (02:45:20 to 02:46:30Z, exit 0) started the helper over an empty cmd.txt and sent rgc ("All done"), the card reading 2,880 MHz after; the cause the batch count per step sized from the unlocked rate, so the low steps ran 2.5x longer than planned; the fix in the scripts: the budget check ends the grid with the restore inside the cap, and a probe dev line answered in helper.log counts as the helper up when its heartbeat file stays stale (the restore answered at once with helper.alive stale past 60 s). THE SM-SPARSE RERUN: fetch-ca4-sparse3-exe-20261008 landed 02:49:57Z (sha256 0ba97edc...), run-ca4-pc1-ca4sparse-5090-20261008 published 02:51:15Z on the hash lane's own order (the shipper's acks were for the void host slot); each sparse row reads served= and sparse_blocks= and is marked variant_row=FAILED if served as base; the close about 03:15Z (04:15 BST). THE STEP-BUDGET FIX ON MASTER (the hash lane, merge 9fd8b1d8 at 03:02:03Z on 8 October, commit 0b00c42e, the full gate GREEN): the efficiency pass keeps four minutes of its cap for the restore (every step and lock guarded by the deadline minus four minutes) and sizes each step's batch count from the last rate read for the pack, so a 60 s step stays 60 s as the rate falls; a probe dev line answered in helper.log counts as the helper up when the heartbeat file stays stale (all four lock scripts); the gate check tools/ci/pc1-step-budget-check.sh with the known-failed case first (under the old rule a lengthening grid ends on the cap with no restore; under the new it ends with the restore at 1,500 s of 2,700), wired into pre-push.sh and checks.txt (74 checks). The 5080 Ember tune, the 9070 XT tune pass and the hot-table ldcs rows publish behind the SM-sparse rerun, the microbench and the packs. THE SM-SPARSE RERUN FAILS THE SAME WAY, NOW NAMED (run-ca4-pc1-ca4sparse-5090-20261008, the fixed exe ca4sparse3, started 02:52:48Z): every sparse row served=base sparse_blocks=0 variant_row=FAILED, the worker's own line "RESULT variant_not_installed requested=sp43-w32 served=base race=... variants 1 base only, no race (no other variant named)", no "compile:" text, so NVRTC never saw a rewritten kernel: the variant name is parsed into the request but never added to the race's variant table in this exe; the research lane's emulation test checked resolve and rewrite, not the race list the bench builds (a test of the wrong layer; the known-failed case must be the bench's own race line reading "variants 2"). The rows are base runs; no reading. The queue goes on: the microbench at the rerun's exit (about 03:15Z), the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the SM-sparse question's fourth row stays with the research lane, an exe whose card-free check shows "variants 2" in its race line getting the slot within the minute. CLASS-V5'S F9 ROW PUSHED (the v5 lane, class-v5 1d5e5d23 on both mirrors at 04:04 UK): the page's F9 row (100,000 seeds, 0 exhausted, max index 30, first-draw acceptance 0.3145, mean index 2.185, F9 PASS, the record file named), F1 stated as running with 0 failures (its own commit to follow), the Intel row not measured tonight; master merged twice (2c5c7f52 gated at 5f5e0a5c, full gate GREEN 71 checks at 03:45 UK; 9fd8b1d8 auto-merged and pushed on the hook's light gate, the full gate running on 1d5e5d23); the generated ledger files and the spec-constants check clean on the tree. THE THIRD --variant FIX (the research lane, 03:04Z on build-1 under lease, with the hash lane): the cause of the 02:52Z rows: the race's push looked the pinned name up in the empty order list through the variant lookup, whose on-demand sp path answers for any list, so the sparse variant was "found" and never pushed; the order is now a pure function with membership by name; --list-race prints, with no device, the race order the worker's own option handling builds and whether the rewrite applies: with the job's exact flags "variants=2 names=base,sp43-w32" and "sparse_blocks=43 block_warps=32 rewrite=applied bytes=22261 nonces_arg=1 unit_fn=1" (before the fix variants=1); exe igneum-worker-cuda-ca4sparse4.exe sha256 84846396559004a8df61881c15ecb42fa3fc1010ad99074e0c0b53e81bb1ca3b, the commit on the mirror after 7e9d52a6; the third rerun on the hash lane's queue at the next slot; the two failed runs stay the night's SM-sparse state, the op-mix re-weight held, the served 3.4x standing. THE GITHUB GUARD ON MASTER (the CI steward, tip 2f702735 at 04:05 UK; merges 53773860 and 2f702735, full gate GREEN 71 checks each): fa7e98fe adds the tracked marker tools/ci/github-suspended (suspended-since 2026-10-07T17:02:00Z, removed by main at the cut-over) and two refusals: merge-to-master.sh refuses a GitHub remote (origin by default, or any remote whose URL carries github.com) with one line naming the switch and exit 2 before any gh or git call; the pre-push hook refuses any push to a GitHub remote the same way (the hook reads the remote URL, so a bare git push origin is refused too); known-failed first in both self-tests; the live read on the Mac: merge-to-master.sh --remote origin exits 2, nothing contacted; two follow-ups (9484b988, a08423d4) fix the tool's own --self-test under the real marker. The rule no longer rests on any lane remembering the switch. F1 READ AT 03:05:58Z (the attack-pass lane; the census process itself, not the lease wrapper): state S with 17 threads, 15 cores busy over 45 s, 2 d 19 h of CPU banked over 4 h 30 min of wall, RSS 0.8 to 1.0 GB; computing, not hung. No rows can exist before the end: the harness collects every Report in memory under thread::scope and writes census.csv in one go at the end (no progress print), named as a harness gap in the record. Why fifteenfold against the v4 reference: under class v5 every candidate draw runs the (c''') distinct-index floor over 2^20 (about 1.8 core-s per candidate under the night's load, times 3.2 draws per program, about 5.8 core-s per program before the analysis), so 10^5 programs at 15 busy cores is about 10.7 h of wall, the end about 09:00Z (10:00 BST), nearer the early side as the load fell to 21. Ruling: not killed (a kill loses 4 h 30 min with nothing on disk); the lane (d) section merges to the mirror's master now with F9 and the F1 row reading "running, 03:06Z reading, projected end about 09:00Z", F1's record line in a second merge when it writes; the harness gains a progress line before its next 10^5 run. THE IN-HOUSE ADVERSARIAL PASS CLOSED (04:08 BST on 8 October; an internal adversarial pass, not an independent review; section 14 of in-house-pass.md at crypto-engage c099e818 landing on master through --remote build; every tip read from the mirror at 04:07 with igneum-pow identical to 017e7037 on all nine). Per lane (tip; box-hours; verdict; partial): adv-mixer d2ba3134, about 0.6 plus 1.8 single-core SAT hours, the algebraic structure BOUND, none; adv-mixer-2 2a632579, 0.31, BOUND for every chip, GPU and the verifier with the FPGA LUT-area FINDING (2^-10.8 of days, 15 a century, worst 2050-04-28 at 1.113x) closed by the measured redraw rule, none; adv-mixer-3 981bfff2, about 5.0 wall-hours plus 8 single-core SAT hours, Q1 BOUND (2^32 t uniform at k = 1 to 8, both days and 8 random days), Q2 and Q2b FINDING at k = 1 only and BOUND from 2 to 8 at 2^24 to 2^28, Q3 FINDING at k = 1 and BOUND 2 to 7, Q4 and Q5 BOUND from k = 1, Q6 SAT BOUND (k = 1 in 137 s, k = 2 to 4 timeout), the round margin 70 of 72 per item, partial Q3 at k = 8 not run, multi-bit masks and a MILP bound not attempted, GPU blocked; adv-cache 555c3e42, 0.55, the recompute shortcut BOUND on every row, none; adv-cache-2 91ca5ce1, about 2.25, the line census PASS at 2^35 + 3 x 2^33, the real programs PASS with the Devnet 3 site-0 FINDING, the diffuse era-stride class named (16 of 32 base programs biased under drawn eras against 2 of 32 under R = 29, 8 over 1.2x, worst 1.75x, under 0.1 percent of reads per site, 0 of 61 refused by the v5 floor, AP-F8-6), steering and the 16,384-day scan PASS, the window layer exact and the chip model's partial-store rows overstated up to 2.3x with the verdict unchanged, partial the line shard s2c waiting on build-1 since 23:09 BST; adv-cache-3 9452c0bf, 0.23, the chain-break or skip BOUND on every row with the pebbling optimum under the hold-every-k curve, none; adv-accept c8a98e46, about 9.2 at 03:25 BST running to its 16-hour line, the bypass FINDING confirmed and bounded (9 few-item hot sets in the tail of 408,067 accepted programs, 0 in 20 random, 1.002x at the largest; all 9 refused by the class v5 floor, 7 clean programs falsely refused among the 12 deepest, 3 mild residuals missed), the stand-in gap BOUND, distinguishers BOUND, the attempts census complete, partial the sweep at 408,067 of 10^6; adv-accept-2 92168536, about 9.0 core-hours and 0.3 pod-hours (the one pod), header grinding BOUND by card measurement (+0.09 percent on an A6000) and by tail (3e-7), one 0.1 percent repeat class for the rule's owners, none; adv-accept-3 7826d2b2, 3.3, exhaustion BOUND (P 1.0e-43), the last-resort path FINDING (correctness, unreachable; closed in class v5), steering BOUND (no property over 1.03x at 1 in 1e6 tries), the program id BOUND with the derivation-string FINDING (fixed on master and in the packs), determinism BOUND, the spec text proven sufficient by two read-backs, the era lever BOUND, partial the steering sweep at 975 of 10^5 full-rule seeds. Totals: about 30.4 box-hours of run across the nine lanes (lease waits excluded) plus about 9.8 single-core SAT hours; pod-hours 0.3 on one RunPod A6000, USD 0.33 in all, rented and destroyed by the fleet lane. The verdict: no lane broke the frozen object; the acceptance rule admits two residual classes of address concentration, both under 1.002x to a chip: the few-item hot sets, closed entire by the class v5 floor (9 of 9) at a 2.4 percent clean-rejection cost, and the diffuse era-stride excess the floor does not reach, routed to the next class with its lever; the weak-day FPGA tail reconciled and closed. Already changed by the pass: the derivation string in the shipped packs, spec 1.4.3 to 1.4.6 rewritten and proven text-sufficient, the chip model's partial-store and pebbling baselines corrected, the last-resort path flagged and closed in class v5. Still to come: adv-cache-2's s2c row and adv-accept's final count, appended when they land. CLASS-V5 GATED (the v5 lane): the full gate on 1d5e5d23 GREEN, 72 checks in 347 s (04:1x UK); class-v5 4a162aba on both mirrors at 04:12 UK with the page's F1 line stating the 04:06 reading (computing, not hung; census.csv only at its end; projected end about 10:00 UK); nothing of the lane's pending on a box or a watch. THE LANE (d) MERGE ON MASTER (the attack-pass lane, 399f8c4d at 03:16:35Z, 04:17 BST; attack-pass 4150f66d, full gate GREEN 45 checks on the branch): F9 PASS on 1c420786 (row and f9-grind.md section (d)), the F1 row as ruled (running, the 03:06Z reading, projected end about 09:00Z, 0 on its live panic path, the harness gap named), the in-house wording kept through a conflict with master's older copy, one founder-strings scrub the gate caught on the pass record (the attribution now "The founder's word"). The harness item: the progress line every 1,000 programs and the flushed partial census.csv (temp file and rename) committed on attack-v5-frozen at 18a9c04a, built on box 2, its known-failed test (a 4,000-program census killed by pid at the 2,000 line, 2,000 rows expected) running under lease pool class adv; the verdict and the push follow. THE SM-SPARSE QUESTION, THE THIRD RUN (run-ca4-pc1-ca4sparse-5090-20261008-b on ca4sparse4, 03:23:45 to 03:48:45Z, exit 0): the card-free check on the card's own exe listed the sparse variant (variants=2 names=base,sp43-w32, rewrite=applied), the race ran it, and NVRTC refused the rewritten kernel on every sparse row: "kernel_bound.cu(370): error: identifier "d" is undefined | igneum_hash_bound_unit(d, ou, baseNonc, mas, i, gid);" (the same for sp170, sp85, sp21, sp11), so the race installed base and every sparse row reads served=base variant_row=FAILED. The hash lane's reading to the research lane: the wrapper's call carries the kernel's parameter names cut by one character (d, ou, baseNonc, mas for ds, out, baseNonce, mask), which points at the rewrite's name capture against the PC's CRLF pack text (the Linux check reported a different byte count for the rewritten kernel): the first card test of the rewrite, the finding kept. The base rows a third repeat of the knee pass (v4 137.06 MH/s at 449.7 W unlocked, 134.23 at 301.4 W at 1,300; v3 136.79 at 329.8, 134.05 at 218.0), the card restored each time. The slot returns to the research lane on an exe whose card-free check compiles the rewritten text through nvrtc for sm_120 (on CRLF input). The queue: the microbench run-ca4-pc1-microbench-5090-20261007 since 03:52:14Z (20 probes of 60 s unlocked, then at the 1,300 lock; about 50 minutes), then the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. THE CLOSE'S MASTER COMMIT (the crypto lane, sent 04:55 BST for a 04:14 landing, the forty-minute gap its own): crypto-engage c099e818 (full gate GREEN, 71 checks) landed as the mirror's master 2882352c at 04:14:50 BST; the record cites the roll-up and every lane's reading at 00b8cd1b and the close (section 14) at 2882352c; further landings only for adv-accept's final count and adv-cache-2's s2c row. THE FOURTH --variant FIX (the research lane, 03:55Z on build-1 under lease): the cause was not the line endings: the rewrite's parameter capture wrote the substring length as end minus start where the last index needs plus one, so every argument lost its last character on any input; CRLF would have missed the anchors entirely; the rewrite now strips \r first (the same rewritten bytes from LF and CRLF, 22,266 on both) and the capture is right; the card-free check through NVRTC on LF and a CRLF copy, identical lines: variants=2 names=base,sp43-w32; rewrite=applied; call="igneum_hash_bound_unit(ds, out, baseNonce, mask, iw, gid)" params=6 args=6 names_match=1; nvrtc=libnvrtc.so.12 arch=sm_120 compiled=1 image_bytes=36256; the failed case the 03:23Z card line. Exe igneum-worker-cuda-ca4sparse5.exe sha256 a4550202b301faf22f5329c2ab4fa1c0aa6695dbdaf31c974f316dca2524d7d6, with the hash lane; the commit on the mirror after 3ac5d20a; the slot after the microbench and the packs. The three failures gave three repeats of the knee pass (the v4 premium 133.9 to 145.3 W unlocked, 90.5 W at 1,300 MHz) in the file's 20.3a. ADV-ACCEPT OFF BUILD-1 (04:5x BST, the coordinator's placement rule): adv-accept runs on to its 16-hour line (about 10:15 BST, 10.6 box-hours at 04:54, the reading saturated) in box 2's gaps under the mechanical yield, its build-1 shard ended at the frontier and its waiter withdrawn, so F1's census keeps build-1 (its 10:00 BST projection assumed load 21) until census.csv writes; adv-cache-2's four-minute s2c shard the one exception. Confirmed by lease status at 04:57 BST: build-1 holds F1 (release, 16 cores) and adv-cache-2's s2c (32 cores, its last shard) and nothing of adv-accept's; adv-accept's four holders and waiters on box 2, where the attack-pass lane's flush test waits at 1 free behind them (the same class, no yield case); the coordinator's placement rule: one adv-accept holder ends at its frontier for the flush test (a 4,000-program census, minutes), since adv-accept's reading is saturated and the harness fix gates the morning's F1 rerun class. Done at 04:59 BST: adv-accept's sweep-s05b ended at its frontier at 04:58:50 (46,460 rows kept) and the flush known-failed test took the 16 cores at 04:58:55; the shard re-queued behind it. ADV-CACHE-2 CLOSED (05:0x BST): its last shard s2c ran 04:56 to 04:59 on build-1 (PASS at 2^33 reads, control-level), so the line census totals 2^36 reads over 464 chain days with every statistic at the control's values; final box-hours 2.35 of run (0.08 a duplicate windows run by its build-1 drain, recorded), pod-hours 0; tip bfc3746c on build/adv-cache-2, igneum-pow identical to 017e7037; the biased-site class (AP-F8-6) and the window-layer pricing stand; section 14's row updated on crypto-engage, landing with adv-accept's final count. Eight of nine lanes at their end; adv-accept alone runs to its 16-hour line about 10:15 BST. THE CENSUS HARNESS'S PROGRESS LINE (the attack-pass lane, attack-v5-frozen 18a9c04a on the mirror): the attack-f1 census prints a progress line every 1,000 programs (count, elapsed, running failure count) and flushes a partial census.csv at the same cadence through a temp file and rename; the known-failed test on box 2 under lease pool class adv (binary 14180ef4...): a 4,000-program census killed by pid at the 2,000 line at 04:08:27Z (05:08 BST), census.csv holding exactly 2,000 rows, no tmp file, lease exit 143; PASS (the old harness's known fail zero rows); record f1-shadow.md section 12 on the mirror's attack-pass at c99f147f (riding the F1 record merge); a side reading: 1,000 programs per 286 s on 16 cores, about 4.6 core-s per program, confirming F1's build-1 projection of about 09:00Z (10:00 BST); the running 10^5 census stays on the old binary, every census after it on the new. F1 PASS ON CLASS V5 (the attack-pass lane; class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, 16 cores; census.csv written 04:20Z, 05:20 BST, after 20,774 s of census, 5 h 46 min, earlier than the 09:00Z projection as build-1 emptied): 100,000 of 100,000 programs through the string-seed draw with the (c''') floor; instructions saved min 0.000 percent, mean 0.623, max 4.688 (the worst seed attack-f1/95060: 6,912 to 6,588); chip-view ops saved mean 0.520, max 4.783; programs over 5 percent 0, over 10 percent 0; soundness: differential mismatches 0 of 100,000 (8 random states each), verifier mismatches 0 of 100,000; 0 panics; the histogram of saved in 0.5 percent bins from 0: 55,241, 20,597, 11,762, 9,851, 1,484, 656, 259, 133, 13, 4, 0, 0. Against the v4 10^5 (max 5.078, the AP-F1-1 letter miss): the v5 tip's worst program sits 0.39 points under the 5 percent letter and the top two bins are empty. F1 PASS on 1c420786 by the letter and at honest-compiler parity; the redundancy gate holds for the 0.3.24 move; AP-F1-1's v5 half FIXED-AND-PASSED at this count; record f1-shadow.md section 13 and the lane (d) row, merged to master next. The attack board on class v5 is complete: F4 PASS (8ca66afa), F8 PASS, F9 PASS, F1 PASS; the rest not re-run by rule. CLASS-V5'S F1 ROW (the v5 lane, class-v5 1095eaa8 on both mirrors at 05:24 UK): the page's attack row reads F8 PASS with the known residue, F4 PASS, F9 PASS, F1 PASS on the full 10^5, the rest not re-run by rule; the full gate running on 1095eaa8; nothing else of the lane's open tonight. THE CA4 PACKS ON THE 5090 (run-ca4-pc1-packs-5090-20261008-b, exit 0 at 04:22:54Z, 579 s; the 5090 alone through the installed worker, the lock and reset through the helper, every self-test PASS at both states): the int8 mma tile prototypes' inline PTX compiles under NVRTC 12.8 on sm_120 and matches the CPU reference (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1, mm1430 8e9b7066239d35d1), as do both per-load exports (404cad3b3399f9b3, ee5d7c71180e5ea7), sh256x27 (3d2e8245cc084d07) and the mx8-genesis control (7c28cfb06c5c65a9). Rows (MH/s / W / MH/W), unlocked then at the 1,300 lock: mx8-genesis 137.54/311.0/0.442 then 127.32/213.0/0.598; sh256x27 137.51/462.2/0.298 then 126.93/295.8/0.429; shl256x27 (unsound, an energy reading only) 158.62/472.8 then 145.65/299.4; shl256x27_v2 (unsound) 135.90/448.3 then 126.04/282.9; mm128 137.45/332.9/0.413 then 127.01/217.8/0.583; mm512 137.50/369.4/0.372 then 127.07/235.4/0.540; mm1430 137.45/457.7/0.300 then 126.87/284.5/0.446. Consequences: the rate is memory-bound on every sound pack at both states (within 0.5 percent of the control); the tile premium over mx8 is 21.9 / 58.4 / 146.7 W unlocked for 128 / 512 / 1,430 tiles (0.103 W per tile, linear) and 4.8 / 22.4 / 71.5 W at the lock (0.050 W per tile), so at 1,430 tiles the tile block costs what the ALU shadow costs (151.2 W unlocked, 82.8 at the lock) and the lock halves it the same way; the first per-load export's 15 percent higher rate is its duplicate reads landing in L2 (the unsound construction), the fixed one 1.2 percent under the control. The research lane has the rows for 20.3 and 20.4; the tile class's premium per tile is now a measured number on the 5090 and its Apple cost (35 to 78 percent of rate) the open side. The microbench -b since 04:23:23Z, then the SM-sparse rerun on ca4sparse5, the 5080 Ember tune, the 9070 XT tune pass, the hot table. THE CA4 PROTOTYPES' FIRST SENTENCE ON MEASURED ROWS (the research lane, counter-asic-4 on the mirror after 1428dd3c; sections 20.3 and 20.4): neither prototype beats class v4's premium; the tile block matches it at the same hash rate (mm1430, 11,440 int8 tiles per hash: 146.7 W over class v3 against the ALU shadow's 151.2 W unlocked, 71.5 against 82.8 W at the 1,300 lock, the rate memory-bound within 0.5 percent) and beats class v4's chip edge only at the pessimistic end (about 2.2x against 3.5x), not at k = 1 (2.2x either way), because the 5090's measured cost per int8 MAC (0.091 pJ unlocked, 0.048 at the lock) sits inside what a 5 nm MAC array costs anyone (a claimed test-chip figure), so a chip's k on tile work is at or above about 1 where on ALU work a fixed datapath reaches 0.3 to 0.5; the per-load placement dead as a construction (its energy rows 13 to 14 W under the whole block for the same instructions; the first export 15 percent faster from duplicate reads served by L2). Against the tile block as a class: the verifier (AVX2 0.047 us per tile per unit; mm1430 10.14 ms with the sibling loaded on the box's core, a 0.14 ms miss of the gate; scalar 13x worse; NEON unwritten), the Apple tier (35 percent of rate at 1,024 tiles, 78 at 4,096), the AMD layout unverified. No served number moves; the SM-sparse reading still owed (three failed runs, the fourth exe queued after the microbench); the op-mix re-weight held, the served 3.4x standing. The k column's basis (the research lane, counter-asic-4 after 781cb395): the 1,430-tile point is the one chip-model-v3 5.11's tensor-tile k column was priced at (15.2 set R about 1,430 from the 4090's 0.056 pJ per MAC to carry the ALU shadow's 0.654 microjoules; 11,440 tiles per hash), and the 5090 reads 0.091 pJ per MAC unlocked and 0.048 at the 1,300 lock there, so the column (2.1x at k = 1, 1.6x at k = 1.5) has its GPU-side cost measured at the premium it was priced for (1.067 microjoules unlocked, 0.564 at the lock, against the ALU shadow's 1.10 and 0.652); the Apple cost the open side; nothing served moves. F1'S RECORD ON MASTER (the attack-pass lane, merge 54b896f3 at 04:29:30Z, 05:30 BST; attack-pass 0610892b, full gate GREEN on the branch, pushed on try 2 after a ref race): the F1 row (PASS, AP-F1-1 FIXED-AND-PASSED on v5 at 10^5), f1-shadow.md sections 12 (the flush and its known-failed test) and 13 (the 10^5 record with the worst four programs at 4.688, the attempt histogram, the v4 comparison). Lane (d) complete: F4 PASS (8ca66afa), F8 PASS (61 of 64 at 1c420786), F9 PASS (10^5 seeds, 0 exhausted), F1 PASS (10^5 programs, 0 over the letter, 0 mismatches); both 0.3.24 gate lines PASS on the full 10^5. Box-hours for the lane (d) tail: build-1 F9 ten chunks of 4 cores at about 14,480 s each (about 161 core-hours), F1 16 cores for 20,907 s (93 core-hours), F4 12 cores for 379 s; box 2 F8 64 seeds (the earlier record) and the flush test 16 cores for 3,352 s (15 core-hours, most queued); nothing of the lane's on either box. THE V5 LANE'S NIGHT CLOSED (05:3x UK): the full gate on class-v5 1095eaa8 GREEN, 72 checks in 345 s; the freeze 1c420786 (0.3.24's pairing), the post-freeze line through 1095eaa8 (0.3.25's: AP-F4-1's agreed form, the verified last resort, the record), every proof green on the tip, the attack board on class v5 at F8 PASS with the known residue and F4, F9 and F1 PASS, the kit's fingerprint equal on CUDA, Metal, Apple OpenCL and the RX 9070 XT, the Intel row not measured; nothing of the lane's pending. THE SM-SPARSE READING EXISTS (run-ca4-pc1-ca4sparse-5090-20261008-c on the research lane's fifth exe, exit 0 at 05:12:48Z, 2,219 s; every variant served on the card, served=sp-w32 with sparse_blocks=N, the rewritten kernel compiled under NVRTC on sm_120 and bit-exact, every fingerprint equal to the Mac's; the 5090 alone, the lock and resets through the helper, the drift check equal to the start): a quarter of the SMs (sp43-w32, 43 of 170) holds 98.2 percent of the class v4 rate at the SAME draw (134.58 MH/s at 460.1 W against base 137.07 at 450.8) and 99.8 percent of the class v3 rate at 4 W less (136.55 at 309.8 against 136.77 at 313.9); the draw falls only when the rate falls (sp21-w32: v4 70.75 MH/s at 327.4 W, v3 132.82 at 303.4; sp11-w32: v4 37.34 at 250.9, v3 100.14 at 274.5), and watts minus idle per MH/s never drops below base (v4 2.75 W per MH/s base, 2.87 at sp43, 3.58 at sp21, 4.74 at sp11; v3 1.75, 1.73, 1.73, 2.00); the persistent shape on the full card (sp170-w32) within noise of base; at the 1,300 lock the sparse shapes collapse (v4 sp43 64.3 MH/s at 208 W, compute-bound). CONSEQUENCE: the class v4 premium is the shadow's ALU work itself, not SM-count overhead (150 W at sp43 against 137 W on the full card), so an SM-sparse miner kernel saves nothing and the candidate is dead by the research lane's own rule; the op-mix re-weight stays the open lever, and its served candidate ("2.9x with a core three times better") now has its SM-sparse read: the premium does not move with the SM count, so the re-weight's case rests on the op mix alone and goes to main with that reading. The microbench -c since 05:13:41Z with the pack argument; then the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. RANK 2 CLOSED IN THE CA4 FILE (the research lane, 20.3b, counter-asic-4 on the mirror after 6b21e887): the SM-side power is the work's, not the SM count's (the shadow's ops cost the same on 43 SMs as on 170; idling SMs saves nothing); the number kept: the class v4 premium at sp43 unlocked 150.3 W over v3 at a held rate, equal to the full-card premium, so the premium is the ops' energy whatever carries them; the premium-free floor rests on the operating point alone; the op-mix re-weight's hold is main's to lift or keep, the SM-sparse reading saying nothing against it; the microbench rows still owed. THE OP-MIX RE-WEIGHT: HOLD (the research lane's case for main, 06:2x BST; the SM-sparse row at counter-asic-4 954c4053, section 20.3b): the served sentence stands ("At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block"; the re-weight would move "3.4x" to about "2.9x", the shuffle-and-multiply-heavy shadow raising the chip's k floor from about 0.32 to 0.46). The basis: the re-weight touches only the pessimistic column, a model on both sides (the chip's k floor an estimate from wire and datapath figures, never measured; the GPU's energy per op by family unmeasured until the microbench rows land, the shfl, mul and arx probes being that measurement); the SM-sparse reading says nothing for or against it (the premium is the ops' energy, which both mixes pay); the night's measured finding on bounding k points to the int8 tile block (the same premium at the same rate with a k floor near 1 from the GPU's own tensor core, 0.048 to 0.091 pJ per MAC), of which an ALU re-weight is the weaker version at the same class-change cost (the 95 percent rule, the six gates, a new program stream, Apple paying shfl at 1.91x per op); a reader gains 0.5x on a modelled pessimistic bound and loses nothing measured from the hold; the 2.1x at k = 1 rests on four repeats of the knee pass (82.8 to 90.5 W at 1,300 MHz). The condition that re-opens it: the microbench reading the 5090's shfl and mul rows at or under the add's pJ per op together with a measured chip floor, and then it re-prices against the tile block, not the served line. Main's word lifts or keeps the hold; the coordinator's reading agrees with the hold. THE MICROBENCH ON THE 5090 (run-ca4-pc1-microbench-5090-20261008-c, exit 0 at 05:56:29Z, 2,484 s; the research lane's per-block micro-benchmark, 20 probes ran, 0 skipped or failed, at the unlocked clock and at the 1,300 lock, every probe's checksum equal at both states, the card back at the driver default). Picojoules per counted op as (watts minus the sleep row) over G ops per s, unlocked then at 1,300: the ARX integer path 11.3 then 6.2; int_mul 13.9 then 8.3; mulhi 39.6 then 21.0; prmt 22.3 then 11.5; lop3 24.1 then 13.0; shfl 55.8 then 29.4; fp32 fma 9.2 then 5.2; fp16x2 fma 5.1 then 2.6; int8 mma m8n8k16 4.1 then 2.2; int8 mma m16n8k32 1.36 then 0.83; fp16 mma 3.2 then 1.7; bf16 mma 2.9 then 1.5; fp8 e4m3 mma 1.5 then 0.8; the memory rows per read: L2 chase 2.4 nJ unlocked and 1.4 nJ locked, DRAM chase 10.9 nJ and 8.7 nJ, texture point 2.3 nJ, texture linear 0.19 nJ; the sleep floor 120 W unlocked against 75 W idle (the residency cost, flagged). CONSEQUENCES: (1) the op-mix re-weight's re-opening condition (the 5090's shfl and mul rows at or under the add's pJ per op) is NOT met and is now a measurement: shfl costs 4.9x the ARX op and mul 1.2x, mulhi 3.5x, so the GPU pays more for the heavier mix and the hold on the served 3.4x stands on measured rows, not a model; (2) the tensor-core int8 MAC costs eight times less per counted op than the ARX op the hash is built from (1.36 against 11.3 pJ), the direction a chip cannot beat by as much, which is the tile block's case restated in measured picojoules and the CA4 file's next row. The queue: run-ca3-pc1-ember-5080-20261007 (the installed app's Ember tune on the 5080, the app's own path, not elevated) since 05:57:18Z, about 30 minutes; then the 9070 XT tune pass and the hot-table ldcs rows. A CORRECTION FROM THE MICROBENCH'S TILE ROWS (the research lane, 07:0x BST; counter-asic-4 on the mirror after 954c4053: 15.1a, the corrected 20.3 and 20.4, the first sentence, the ranking): a mma.m8n8k16 tile is 1,024 multiply-adds per WARP, 32 per lane, so a hash does 32 MACs per tile, not 1,024; the lane's 15.2 and 20.3 and the 6 October 4090 figure chip-model-v3 5.11's tensor column was priced on were wrong by that factor. Corrected: the 5090's int8 MAC at the ALU shadow's premium costs 2.9 pJ unlocked and 1.5 pJ at the 1,300 lock (the packs job, 366,080 MACs per hash), the microbench's dependent u8 tile 4.1 and 2.2, the wide s8 m16n8k32 tile at 80 percent of peak 1.36 and 0.83; the 4090's "0.056 pJ per MAC" of new-pow 5.1 is 1.8 pJ. Against a 5 nm MAC array (0.04 to 0.4 pJ per INT8-class MAC, claimed) the chip's k on tile work is 0.03 to 0.3, BELOW the ALU shadow's 0.3 to 0.8: at the same premium the tile block leaves the chip 3.5x to 6.7x where the ALU shadow leaves it 2.1x to 3.5x. So the tensor shadow is the WORSE lever and rank 3 is dead; the 6 October verdict on scheme B stands for the right reason; the coordinator's 07:0x line to main calling the tensor side "the next class's one live direction" is withdrawn by this correction. Chip-model-v3 5.11's tensor column (its premise, a chip's MAC no cheaper than the GPU's, false by 4x to 30x on the public figures) and new-pow 5.1's per-MAC line are to be corrected (the coordinator's next commit); nothing served rests on either. The other rows, pJ per counted op unlocked then locked (the sleep floor 120 and 66 W subtracted; idle 75 and 60): int add-xor-rotate 11.3 / 6.2 (the shadow's 10.8 / 6.4 on the packs job: the two instruments agree); mul 13.9 / 8.3; mulhi 39.6 / 21; prmt 22.3 / 11.5; lop3 24.1 / 13.0; shuffle 55.8 / 29.4 (the card's dearest instruction, 5x the add: the re-weight's GPU side is against it, the hold measured); fp32 FMA 9.2 / 5.2; L2 hit 2.4 / 1.4 nJ per read against a chip's SRAM 0.2 to 0.5 (the hot-table lever dead on the GPU side; the ldcs rows kept as a record); the DRAM dependent read 10.9 / 8.7 nJ per read, the whole card's marginal against the chip memory's 2.0, section 2's floor seen per read. THE NIGHT'S CLOSING SENTENCE ON MEASURED ROWS: nothing on the 5090 reads k above 1; the ALU shadow at the operating point's knee is the floor, 2.1x at k = 1 for 82 to 90 W, measured four times; the two prototypes, the SM-sparse kernel, the hot table and the re-weight are all closed on measured rows. The CA4 file's commits (the research lane): 15.1a at 71fd465b (the microbench row, the residency cost 45 W at the stock clock before any instruction issues), 15.1b the commit after it (the re-weight's re-opening condition not met and measured; for 2.9x to be the honest pessimistic column a chip would have to pay 0.42 to 0.52 of the GPU's cost per shuffle, 22 to 28 pJ for a 32-lane crossbar move, above the wire figure and unmeasured; not a candidate on measured rows); the corrected 20.3, 20.4, the first sentence and the ranking at 71fd465b; the hot-table ldcs rows a record only. The lane closed for the night. THE TWO INTERNAL CORRECTIONS LANDED (the coordinator): chip-model-v3.md 5.11's k-column paragraph carries the dated correction (the tensor-tile column withdrawn; the shipped row unchanged) and docs/analysis/horizon/new-pow.md 5.1's per-MAC prose and the scheme B verdict carry the 32x correction with the reason (a tile is 1,024 multiply-adds per warp, 32 per lane), both citing counter-asic-4-research.md 15.1a at 71fd465b; new-pow's 5.1 table column and its 5.3 chip rows keep their original numbers under the note (the Horizon lane's file; a table rewrite is its own). THE 5080 EMBER TUNE (PC 1, app 0.3.20, 06:05Z, 07:05 UK; run-ca3-pc1-ember-5080-20261007): Tuned 60.3 MH/s at 123 W, 0.489 MH/W, clock_cap 2936, source=climb; read against the clock-lock grid, the app's power-limit climb lands at 0.489 MH/W where the 1,000 MHz lock gave 71.1 MH/s at 103.7 W (0.686), so the core-clock lock is worth +40 percent per watt on the 5080 over the stock climb (and 15 percent more rate): the case for the 0.3.24 core-clock knob shipping. The per-point curve rows were lost to a cast fault in the hash lane's curve line (job exit 1, 386 s; the app unaffected), fixed at 261d7c54. Live on PC 1: run-ca3-pc1-ember-9070-20261007 (the 9070 XT tune, 45-minute cap), then the hot-table ldcs rows. THE KNOB ON release-0.3.24 (the shipper, 07:1x BST): the core-clock knob 74585c91 cherry-picked onto release-0.3.24 at e181f497 with the efficient-point ceiling beside it (the plan-count test updated, b6e2845f; the app gate GREEN 294 + 35 + 8), the DMG re-cutting on it under the lock, the UI lane's drawing of the lock fields asked onto that tip, the measured Ember sentence in the 0.3.24 section with the job ids and the knee rule; the pin dfbd1e10 and the kit e6c088bb stand; the move on main's morning minute. THE 9070 XT EMBER TUNE (PC 1, app 0.3.20, 06:11Z, 07:11 UK): one row only, baseline 18.9 MH/s at 202 W, 0.093 MH/W, the chosen point "80%": the app has no knob on AMD in 0.3.20 (power_pct 0, clock_cap 0, limit 0.0 W), so the tune measures the stock point and stops; the 9070 XT cannot be made efficient by the app today, and at 0.093 MH/W it sits at a sixth of the 5090's locked 0.58 MH/W (the app's stored 5090 curve: 1,390 MHz, 118.6 MH/s at 204 W, 0.580) and a seventh of the 5080's locked 0.686; the AMD watts owed from the G1 ladder are on record from the app's reading, 202 W at 18.9 MH/s (the bench row's watts for the 9070 XT once the sampler question is closed). A morning item for the ledger and the app: an AMD core-clock knob (rocm-smi or ADL) is the only path to a 9070 XT efficiency figure. The job exited 1 on the hash lane's row count (fixed, 43f0918c); the app unaffected. The hot-table kit on PC 1 (fetch done 06:20Z); run-ca4-pc1-hot-ldcs-5090-20261008 publishing, the last PC 1 job on the list; rows when it closes. THE 9070 XT BENCH ROW ON MASTER (the site audit lane, ffb7d8ff at 07:35 BST, commit 47690be7, gate GREEN 72 checks): watts 202 ("202 stock"), mh_s 18.92 ("18.9 (18.8 to 19.2 on the G1 ladder)"), 0.093 MH/W, tuned "no lever: the app has no AMD knob today (an AMD core-clock knob through rocm-smi or ADL is the path, a morning item)", the class v4 cost unchanged (+2 percent of rate, 6 October), the note naming the app's own power reading at the stock point with the date and the status row, Hive values none; /miners rebuilt at 35 rows; no deploy; the audit lane closed for the night. The bench table's AMD watts are no longer owed. THE HOT-TABLE LDCS ROWS (the hash lane; the mirror's master at c09dfee4, 08:12 UK; bench-log entry "8 October 2026, the hot-table packs on the RTX 5090", 36 rows all PASS; run-ca4-pc1-hot-ldcs-5090-20261008b exit 0 in 1,372 s, clocks reset): ldcs equals base everywhere (a dead lever, no ldcs rows owed); the 1,300 MHz lock costs the hot packs 2 percent of rate against mx8's 7.5 while taking a third of the watts off every pack, so the hot family is latency-bound on the table; per watt at the lock hot64k8 reads 0.734 MH/W against the mx8 control's 0.602 (the control matches the v4 grid's 0.60, the two passes agreeing); the research lane has the rows with the resistance question (a cheaper GPU hash is a gain only if the saving sits in the memory path; the microbench's L2 row at 2.4 nJ against a chip's SRAM 0.2 to 0.5 answers it on the chip side). THE PC 1 LIST MAIN SET IS CLOSED: the 5080 full grid, the third 5090 pass, the SM-sparse reading, the two Ember tunes, the hot table, all on measured rows. Still open on the hash lane's side: PC 2's Arc B580 class v5 fingerprint on the shipper's clear (a Windows entry first), and the F8 tail p4/p8/p10/p34 as a Mac measurement under the lock script, held until main lifts the Mac rule for one job (a morning item). MAIN'S MORNING WORDS (09:3x BST on 8 October; the night's silence main's own, recorded as such): (1) the look: the design pass lands now through its gate (ca3-coord rebased onto master 715c79b2 as five site commits, tip 0d212a2a; the box sweep GREEN on the same content), the steward deploys master after it; (2) the floor sentence goes on evidence row 17 as well as /ledger in the exact wording (the audit lane's row); (3) CA4 parked with no live candidate, the record carrying the measured close; the only new work the AMD core-clock knob for the app, a 0.3.25 item on the update-return lane; (4) the F8 tail p4/p8/p10/p34 on the Mac: the Mac rule lifted for that one job, one at a time, a few minutes, the hash lane running it now; (5) the move: the shipper has route (A) with the minute 10:45 BST; the Arc B580 job has PC 2 clear and publishes now. THE BUILD-SERVER LANE'S HONEST STATE (09:31 BST): it ran nothing between 22:54 BST and 09:31 (its turn sat on a backgrounded gate chain; the overnight asks reached no tool call); the /miners captures it owed never ran (its export step failed at 22:52, "not a tar archive", a branch commit's git archive over ssh needing the ref fetched on the box side; the CI steward took the captures and the sweep instead); its last master-only deploy dde2dcd2 at 22:49 BST; it deploys master's tip on main's confirmed order after the design pass lands, and builds the 0.3.24 Windows pair and hive on the shipper's word. THE DEPLOY AND THE PAIRS (the build-server lane, 09:3x BST): a master-only deploy of 715c79b2 running from 09:32 with the checks after; master's tip deployed again when the design pass and the row-17 commit are on it, the served sha and minute to the record; the 0.3.24 seed, Windows and hive pairs built on the MORNING pin (the node lane's re-cut from the 10:45 minute) under lease class release, the hands pair the node lane's, the shipper keeping the move and the minute; the seed-class ship path proven on dfbd1e10 first so the morning pin's builds run clean. THE FOURTH CUT (the node lane, 08:33:18Z, both mirrors): 5b673577 on release-0.3.24-node = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else, the three heights staying; the read from build-1's restarted seed on 27632 at DAA 56,329 at 08:33:18Z (1.0 DAA/s overnight); the publish DAA at 09:45Z about 60,630, plus 7,200 is 67,830, the next boundary 68,400, landing about 11:54:29Z (12:54 BST); the floor holds for a publish up to DAA 61,200 (about 09:54:29Z, 10:54 BST); the gate set running since 08:33:20Z (build and consensus at gate priority, the five suites, both canary sets, the fast-time pair about 14 minutes from the artefact), the pin line due about 08:52Z (09:52 BST); the crossing read from build-1's seed after the move (restarted on the pin in the shipper's move); the TESTNET_PARAMS v5-at-0 re-cut after a clean crossing. THE ARC B580 READ (the hash lane, PC 2, 08:35:59Z, 09:36 UK): no fingerprint, match False against 82b19cbde8557ea5; the kit worker fails its self-test on the Arc before any batch ("vector lanes 96 bad of 96 ... device 729ebd46376e2851 expected e552166a03298f7f" on the v5 pack) and 96 of 96 on the v4 control too (device 11bdacb6ee4108c2 expected dfbc8db1c06dacd8), every cache and dataset FNV matching; so the Arc's bound-kernel evaluation is wrong on Intel OpenCL, not class v5; the kit is good on five of six platforms; under main's rule the Intel kit holds out of 0.3.24 with the crossing time 09:36 UK for its page row. The open question, put to the shipper (PC 2 its now): whether the installed 0.3.21 worker's own self-test passes on the Arc with the devnet pack, which decides regression (the kit worker) against never-worked (every Arc rate row on record would then be a FAIL row and the bench table's Intel row a held row). The F8 tail job on the Mac started under the lock script, one seed at a time. THE DESIGN PASS ON MASTER (the coordinator, on main's word; merge 3a4ba893 at 09:39 BST): ca3-coord rebased onto 715c79b2 as five site commits (tip 0d212a2a: the design pass e2674675, the phone grid 592488a4, the six-column row 7c44354f, the lead cell's wrap c11baf30, the width rule scoped to desktop 0d212a2a), site/build.mjs and site/miners.html only, the page rebuilt at each commit so it carries the 5080 and 9070 XT rows under the design; the Mac's gate GREEN (the sweep skipped there), the box sweep GREEN on the same content at 5158276c with the four dark captures under /srv/artefacts/captures/ca3-coord-5158276c/; the build-server lane deploys master's tip after the audit lane's row 17 and Arc-note commit. THE MOVE'S READINGS (the shipper, 09:4x BST): the pin 5b673577's node-lane pair on build-1 (igneumd a3b1a2c9, igneum-miner cfa9f5ca, igneum-pow src 8 paths), its tarball served at fleet/5b673577-node-lane.tgz (c5b85b09, 27,495,480 B); the gate script carries cfa9f5ca and dry-ran at 32 of 35 reachable (dn3-pool-a destroyed by the fleet's waste pass, dn3-relay and p2-4090-1b behind dead proxies); the move file m5b67-1 written to take the pin line's digest and placed at at_epoch 0 the moment that line reads green (about 09:52 BST), the gate line applied in the same minute, the minute the last FETCHED plus ten (the founder's word: no waiting on the clock; 10:45 the ceiling, 10:54 the floor's); the Mac entry re-cut on the knob display (knob-24 2c4dc617 merged, app gate 294 + 35 + 8, UI 88) and published with the hive at the minute; the installed worker's self-test on the Arc with the Intel lane; the eight boxes on bc5945fe with miners off read by the fleet lane and taking the move with the rest. (The fleet lane is answering again this morning.) THE PIN LINE ON 5b673577 (the node lane; every gate green at 08:39:15Z, 09:39 BST): 5b673577 on release-0.3.24-node (both mirrors) = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else; pairing igneum-pow 1c420786; build 08:34Z rc 0 at gate priority (igneumd a3b1a2c96a9767ee..., igneum-miner cfa9f5ca..., /srv/artefacts/0324-5b673577/node-lane); core 175, exec 47, miner 28, p2p-flows 38, pow 19, consensus 134 at gate priority; the Devnet 3 canary set (08:34:58Z to 08:36:38Z): digest cc9026909eddbadb46912513e9b748dffd8e5c3583cd976857a8afdab2d772f9 on igneum-devnet-3 from ba75bf6f, object version 6 stamped, the override file refused, shutdown 573 ms, two empty nodes handshaking on cc902690, the shared-devnet dialler rejected, a 2720d8d2 node refused both ways; the testnet canary b2e856ed unchanged. The floor from the seed's read: the publish DAA at 09:45Z about 60,630, the floor about 11:54:29Z (12:54 BST), holding for a publish up to DAA 61,200 (about 10:54 BST); the fast-time pair's SUMMARY due about 09:55 BST, inside 10:35; no slide to 72,000 needed. A correction: node1-dn3's 28670 no longer answers (its process gone), so the DAA reader is build-1's seed on 27632, restarted 02:00:09Z on the shipper's word and in step with the observer on 28650. dfbd1e10 void as a pin. THE F8 TAIL ON THE MAC, p4 (the hash lane, under the lock script, one seed at a time; the Mac rule lifted by main for the one job): p4 reads 1.2169x over the window model (the gate's 1.2167x reproduced), hot-set clear at every f, the attribution on one site: site 1 (instr 8, source r2, window 2^22 items, offset 1, the last base writer mad at instr 4) carries 1.448 percent of the hot reads against 0.107 flat, index entropy 13.74 of 14 bits, the largest 256-item bucket 4.5x its window expectation, every other site at its flat share; the hottest item 0x4000e7 at 355 reads with no predicted source (no saturation, no lossy writer), so the residue is a window-2 index with a quarter-bit short, not a lossy source; p8, p10 and p34 running (about 90 s each), the four rows and the record line (the bench log or AP-F8-1's tail paragraph) at the close. STANDING RULE FROM THE FOUNDER (09:5x BST on 8 October, after the night: "this cannot happen again"), three parts: (1) every ask any lane sends main carries a default action and a deadline; silence at the deadline means the default, never a stand-down; passed to every lane the coordinator runs; (2) the coordinator mirrors every deadline the shipper holds today (the pin, the apply, the move minute, the publish, the Windows chain, each floor ceiling): if the shipper has not acted within five minutes of its own clock the coordinator sends it the word and tells main; if it is silent for 25 minutes the coordinator takes its next action itself with the shipper's runbook and tells main; (3) a 20-minute heartbeat wakes main regardless of notifications. The night's cost the rule prices: three floors lost (28,800, 32,400, 39,600) and the Mac entry stood down for want of one word while every gate was green; two lanes dark for ten hours. THE MOVE FILE PLACED (the shipper, 09:42:14 BST): m5b67-1 (5b673577, digest cc9026909eddbadb, at_epoch 0, the node-lane tarball c5b85b09) placed and served, its signature verified against the fleet key; the gate line (cfa9f5ca into every reachable box's pack list) applying from 09:42; the minute the last FETCHED plus ten once the fast-time SUMMARY reads PASS (about 09:55); the Intel lane a0aa97b17380bd614 holds the Arc self-test question with the audit lane on its recipients. THE NODE LANE'S OPEN ITEMS UNDER THE RULE (09:4x BST): the crossing read at DAA 68,400 from build-1's seed by 13:10 BST (else the observer on 28650 or the reader on 28690); the TESTNET_PARAMS v5-at-0 re-cut lands through the full gate set at 13:30 BST unless main says otherwise by 13:15 (a red crossing read means no re-cut); any later floor losing its margin is cut from the next named minute by dn3-floor-cut.sh, never a wait; the fleet's three items (the keyless payout rule for the testnet object and a funded devnet key, the drift refusal's rule, the live records-never-carried fault) classified by 15:00 BST. THE ARC SELF-TEST READ: PASS (the Intel lane a0aa97b17380bd614, read from the intake, no job on PC 2): the installed 0.3.21 igneum-worker-opencl.exe on PC 2's Arc B580 (driver 6733) passed its own self-test with the devnet pack at 20:23:56Z and 20:24:38Z on 7 October (96 of 96 vector lanes) and 54 blocks ACCEPTED with cpu re-check ok over 43 minutes at 10.58 MH/s wall (accepted 54, rejected 0 at 21:06:33Z); the shipped 0.3.20 worker read 96 of 96 on every pack on both PCs earlier that day. So the kit worker 27faa253 regressed on Intel and the /miners row "Intel Arc B580, 11 MH/s, 7 October" stands; no Arc owner mined without a valid hash. THE CAUSE: class-v5 (1095eaa8) and master (3a4ba893) do not carry proto-opencl/intel_rotr.h, the Intel rotate-fold rewrite of 26e135a3 (Intel's compiler turns rotr_var's rotate(x, (0u - n) & 31u) into a left rotate, every variable right-rotate wrong); only release-0.3.23 (710e1fea) and release-0.3.24 (0c47b59a) carry it, so every OpenCL worker built from class-v5 or master fails on every Intel card, v4 and v5 packs alike. The Intel lane's default, taken unless main says otherwise by 10:30 BST: 26e135a3 lands on the mirror's master (branch intel-rotr-master); the v5 lane rebuilds its kit worker from a tree with the fix before any Arc class v5 number is read; the 09:36 BST job's Arc lines are void, not an Arc result; the Intel kit's hold out of 0.3.24 stands until the rebuilt kit's fingerprint reads on the Arc. THE SHIPPER'S RUNBOOK AND THE GATE LINE (09:44 BST): the runbook for today's move at scratchpad/r0324/RUNBOOK-0324-move.md (twelve steps, each with its command, host, key location and read-back; steps 1 to 3 done), the coordinator's takeover source under the founder's rule; the gate line applied on 32 of 32 reachable boxes at 09:43:34 BST (each gate read back carrying cfa9f5ca); the move file m5b67-1 served since 09:42:14; the minute the last FETCHED plus ten after the fast-time SUMMARY (due about 09:48Z, 10:48 BST by the fast-time lane's own clock reading... the SUMMARY due about 09:5x BST), inside 10:54. THE RULE PASSED TO EVERY LANE (09:4x BST): the shipper (its runbook written), the node lane (its three defaults armed: the crossing read by 13:10, the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15, any later floor cut from the next named minute), the fast-time lane, the build-server lane (the deploy at 10:00, the three pairs with their minutes), the hash lane, the audit lane, the v5 lane (the kit rebuilt on the Intel fix), the Intel lane (its default at 10:30), the update-return lane (the AMD knob's branch by 12:00), the fleet lane (the FETCHED count by 10:05), the crypto lane (adv-accept's count at 10:15, section 14's last landing by 10:45, both armed on hard clocks), the attack-pass lane (the F8 tail's attribution by 11:00), the research lane (parked, its file at fb61ed4b) and the CI steward (the cut-over ask with a default on the first unsuspended read). THE AMD KNOB OPENED (the update-return lane, 0.3.25; branch amd-clock-25 off release-0.3.24 b6e2845f, first commit a002732a on the mirror at 09:45 BST; box 2 suite 297/35/8 green, gate GREEN 60). Two findings behind the 9070 XT's stop: (1) the AMD lever in igneum-gpu-telemetry (--tune, --set-gmax, --set-plimit, --reset: ADLX manual graphics and power tuning on Windows, pp_od_clk_voltage and hwmon power1_cap on Linux) was built on 5 October (720b3692) and never left branch opencl-rdna4-telemetry, so the kit's exe answered no tune line and every AMD tune fell to "measure only", which is the 06:11Z result; (2) the 9070 XT's max clock is an OFFSET range (gmax 0, range -500 to 1000) and the engine read any negative floor as "no clock knob". The commit takes the tool whole into proto-opencl/gpu-telemetry.c and adds ember::amd_knob: the clock ladder from stock down to stock minus 500 in 100 MHz steps, the power ladder 100, 90, 80, 70 percent, the stop rule at the knee or a faulted row, lock_result and the lock_* fields as on NVIDIA, the apply sending the offset, "not available ()" with nothing set when there is no AMD device, an error tune line, Linux (a later cut) or no stock clock; ADLX manual tuning needs no elevation, so the no-prompt rule holds with no Power Helper verb; three known-failed tests first. The first measured grid needs the kit's igneum-gpu-telemetry.exe rebuilt from this source (MSVC, the ADLX SDK beside the tree) and a 0.3.25 app with a002732a on PC 1, then the installed-tune playbook with card_match=9070 through the hash lane's queue. The lane's default: if the shipper names no 0.3.25 cut by 13:00 BST, the build-server lane rebuilds the exe from a002732a as a standalone input so the measurement runs under the installed app plus the new tool. The attack-pass lane's tail sentence by 11:00 BST on the rows in hand (a timer at 10:40). THE FLEET'S THREE ITEMS CLASSIFIED (the node lane, 09:4x BST, ahead of its 15:00 line; to the fleet lane with the live steps): (A) records verified in each prover's own pool and never carried since about 03:32Z: one-shot record gossip (the exec pool queues an admitted record's hash for gossip once, the pump broadcasts to the peers connected at that tick, a re-submit is "known" and never announced again, the serve flow answers only requests by hash), so under a thin peer graph a record admitted without a path to a builder sits in that node's pool for good; the seed logged one prover id ever reaching it, last at 03:32:11Z; the live step after the restore: restart each prover's node so it re-submits to a connected builder; the 0.3.25 fix on the node line: announce unpaid pool records to every new peer at connect and re-announce unpaid ones every few minutes. (B) p1-5090's "refused on the drift flag (offset -5)": the fleet's own standing.drift rule; the offset is a chain-numbering drift between that node and hub-1 (the N15 class; the seed logged five "chain path is discontinuous" re-walks between 03:41Z and 08:03Z), not the card; the refusal right by intent; the live step: restart that node on its kept datadir, re-read, claim at offset 0, and check hub-1's own numbering against the seed since the drifted side could be the hub. (C) 0.3.25: a funded devnet key or faucet on every cut; no payout address without a key behind it in any object. THE F8 TAIL ATTRIBUTED (the hash lane on the Mac, 08:39:46Z to 08:46:24Z, 09:40 to 09:46 UK, one seed at a time under the measure lock by main's lift of the Mac rule; attack-f8 census at 2^24 nonces, the window-model control, by-site attribution; tree b38b4af6 with igneum-pow frozen at 017e7037): the gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x; the hot-set verdict clear on the windowed control for all four). Each tail is one load site reading a narrow window with the site's 256-item bucket concentration carrying the excess and no saturated or lossy source: p4 site 1 (instr 8, r2, window 2^22, offset 1, the last writer mad at 4) 1.448 percent of its reads into the top 0.1 percent against 0.107 flat, index entropy 13.74 of 14 bits, the largest bucket 4.5x window expectation, the hottest item 0x4000e7 at 355 reads with no predicted source; p8 site 14 (instr 51, r7, window 2^22, offset 2, xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, plus site 6 (instr 33, r3, window 2^23, mad at 30) 0.834 percent, bucket 3.5x, the hottest 0x837de4 at 420 reads, source none; p10 site 8 (instr 28, r0, window 2^22, offset 1, mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x, the hottest 0x4004da at 362 reads, source none; p34 site 1 (instr 13, r3, window 2^23, offset 1, sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x, the hottest 0x800010 at 541 reads, the predicted source "one-one-bit, last writer sub at 5", saturated source 0.0001 percent; every other site in all four at its flat share. THE MECHANISM: a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short on a 2^22 window; p34 0.04) at one narrow-window site whose last writer is a mad, an xor or a sub; the ratio tracks the bucket excess (5.6x gives 1.50x, 3.1x to 4.5x give 1.22x to 1.38x); sub-version 3's (c'') distinct-index ratio passes these at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would catch all four: a per-site largest-256-item-bucket bound (about 2x window expectation at the 2^20 units (c'') already runs), a generator change, so not for the frozen 017e7037 nor for the frozen class v5; a morning item for main with its clean-seed cost unmeasured; the record line on the AP-F8-1 entry (the tail attributed, nothing changed in the stream). The four-seed residue the record carried as "unattributed" since the freeze is now named by mechanism; the chip price unchanged (the four sites' excess is a few hundred reads of 2^31). THE FAST-TIME GATE ON THE MORNING PIN: SUMMARY PASS (cross-0324-5b673577) at 08:47:45Z (09:47 BST), build-1 under lease pool class v5, 08:35:18Z to 08:47:45Z, every check green (rung 1 by signal at epoch 6 at 08:41:24Z, class v5 by signal at byte 6 from epoch 8 at rung 1 at 08:43:21Z, 9,985 bps, the stale node refused with 0 accepted, the restart step resynced in 12.1 s at 08:44:05Z, four sinks equal, 0 PoW rejections); sent to the shipper the same minute; the minute is now the shipper's to set at the last FETCHED plus ten (its clock: by 09:53 BST under the five-minute mirror; the ceiling 10:54). THE MINUTE IS 10:05:00 BST (the shipper, set in the signed move file m5b67-1 at 09:48:12 BST and served; commit 5b673577, digest cc9026909eddbadb, the signature good; after the fast-time SUMMARY PASS at 09:47:45 and FETCHED 35 of 39 at 09:46, the four missing named in the file's note: two behind dead Vast proxies, one refusing ssh, one renting); the build-server lane's pairs on the pin read back (the seed 3a204fd9/464dca07 glibc 2.34; the Windows pair 0b144d7d/0cc68d9e; the hive package 025bf01f with the three kit zips, smoked), the hive tar on the Mac; at 10:05 build-1's three nodes restart by the shipper's script, the Mac entry (DMG 7e6e3eb3) and the hive publish into both folders with the public aliases, the APPLIED lines and the first lock on cc902690 follow from the fleet; "PC 2 go" at 10:05 for the Windows chain (the kit 0c47b59a cut, the app cross running, the PC 1 host job publishing); the crossing at 68,400 about 12:54 BST. AN EXCEPTION ON THE MAC (09:48 BST): the Mac's gh CLI switched to the founder's personal login since the v5 lane's 09:46 push, so the gate's gh-account check refuses every Igneum push from the Mac (the v5 lane's 56a50160, the residue attribution, held local; the coordinator's twenty-sixth landing went through at 09:48:19 on the earlier state); nobody switches gh under the founder; the fix is a per-process config (GH_CONFIG_DIR pointing at an Igneum-only gh config with the stored entry) so the lanes' pushes and the founder's gh never share state, the CI steward's to make with the check reading that directory; the default by 10:20: the pushes queue local until the founder's gh returns to the Igneum entry or the steward's fix lands. ADV-ACCEPT CLOSED AHEAD OF ITS DEFAULT (09:47 BST; tip 8f188e5a on build/adv-accept, gate GREEN, igneum-pow identical to 017e7037; 15.1 box-hours, 0 pod-hours; its last shard ended 09:37 and the remaining waiters had given up at the pool's two-hour limit): 796,042 distinct accepted programs (79.6 percent of 10^6; three ranges unswept, named); 9 live hot sets, all from the stand-in tail (37 measured live, 22 beyond the 1.2x gate), 0 of 20 random, at most 1.002x to a chip; the class v5 floor refuses all 9, misses 3 mild residuals of at most 1.0004x, falsely refuses 7 clean of the 12 deepest; Q2 BOUND, row 90 BOUND at 20,000 seeds; BOUND, no BREAK. Section 14 updated (adv-accept's row and partial, adv-cache-2's close, the totals: about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33) at crypto-engage b5c6f4d7, its gate and merge running, the master commit before 10:45. All nine lanes at their end. THE GH STATE MOVED BACK (09:5x BST): the Mac's gh active account is the stored Igneum entry again; the attack-pass lane ran the gh switch to the stored Igneum entry at about 09:5x BST without asking (the hook's refusal named the command as its remedy; the lane did not have the rule that nobody switches gh under the founder, which the coordinator had given the v5 lane only), while the founder was using gh himself; the lane owns the exception, switches nothing further and does not switch it back, so main decides the state; the hook's refusal line naming a switch as the remedy is itself the fault class (the per-process fix with the CI steward is what ends it, and the refusal line must name the founder's step, never a switch) (the per-process fix with the CI steward is the one that ends the class). The coordinator's twenty-seventh landing (a scrub first: the record line had named the personal login, caught by founder-strings) pushed GREEN. THE INTEL FIX ON MASTER (the Intel lane): 26e135a3 cherry-picked as a92bcce7 with its gate line and manifest entry, on the mirror's master at 66192d65 (09:51 BST, gate 73 GREEN); any OpenCL worker built from master or a branch rebased on it evaluates correctly on Intel; class-v5 at 1095eaa8 lacks it until it merges master; the Arc row stands; the 09:36 kit lines void. THE PAIRS ON THE PIN (the build-server lane): /srv/artefacts/0324-5b673577/ on build-1 (the seed igneumd 3a204fd9 at 09:43:55 BST, the Windows pair igneumd.exe 0b144d7d and igneum-miner.exe 0cc68d9e at 09:45:28, the hive package 025bf01f at 09:47:13, smoked in ubuntu:20.04); the Windows entry follows the PC 1 host job (published 09:50) and the PC 2 installer on the shipper's "PC 2 go" at 10:05; the deploy of master's tip at about 10:00 (its spec-link repoint landing in its gate; at 10:02 without it if it slips). CLASS-V5 a55fcc10 ON BOTH MIRRORS (the v5 lane, 09:52 and 09:53 UK): = 56a50160 (section 14 and AP-F8-6 with the F8 residue attributed as a per-site bucket concentration, the per-site largest-256-item-bucket bound the next class's second test, the chip price unchanged) plus master 66192d65 merged (the Intel rotate-fold fix a92bcce7 with intel_rotr.h and host.c's igneum_intel_rotr_patch; host.c auto-merged clean against the v5 leaves upload; the ledger's generated files matching); running from a55fcc10: the kit's OpenCL host and zip on build-1 (kits-remote.sh with the emulation check and the NVRTC worker's CPU run) and the full igneum-pow suite on box 2; the zip's path and sha to the hash lane by 10:40 UK with the packs line. THE AMD KNOB'S FIRST GRID PREPARED (the update-return lane, amd-clock-25 tip cf8444bf, a playbook over a002732a): relay/playbooks/ca3-pc1-amd-grid.ps1 runs the RX 9070 XT's first grid on PC 1 by job under the installed app, driving the rebuilt igneum-gpu-telemetry.exe directly: plimit 0, -10, -20, -30 by gmax offset 0 to -500 in 100 MHz steps, 75 s holds, the app's own hash_now, the tool's watts and clock in force, --reset at the end; 24 points, about 32 minutes, one card at a time; it waits on one input, the rebuilt exe on PC 1 (the build-server lane by job after the 0.3.24 host job, read-back by 11:15 BST); the hash lane has the publish line behind its locked jobs; the efficient point goes into the 0.3.25 tuner's ceiling table. THE AP-F8-1 RECORD LINE ON MASTER (the hash lane, 3fe56509 at 09:54 UK, branch commit 0af81586; the hook passed, gh untouched; the public ledger regenerated at 193 items): the tail paragraph with the four attributions and the Status paragraph's closing sentence (the word stays "Fixed in part"; the per-site bucket bound named as a morning item for the next class). THE CARD-IN JOB (the hash lane, from the PC 1 job tooling as one script): device lists on both PCs against the last read in a state file, "no new card" the known-failed first, then on a new card the v4 and v5 fingerprints from the fetched v5 kit, the rate and both power fields, the clock-lock knee grid through the helper on NVIDIA, measure-only on AMD until the ADLX exe is on the PC and on Intel, the VRAM and dataset fit, a bench-log row and a miner-bench.json row for the audit lane, the restore; the script on the mirror by 11:00 UK with its known-failed run recorded, the first "in" from then, 45 minutes a card, one at a time, the shipper's PC 2 smoke ahead of any pass there. Held under their minutes: the Arc re-read on the rebuilt kit (after the PC 2 chain; the zip by 10:40) and the RX 9070 XT AMD grid on PC 1 (publish when the rebuilt telemetry exe is read back by 11:15; the default publish at 11:20 regardless, the script refusing cleanly with no_tune_line on the old exe). THE IN-HOUSE PASS'S LAST LANDING (the crypto lane, 09:55 BST): crypto-engage b5c6f4d7 (full gate GREEN, 71 checks) landed as the mirror's master 9649f51e at 09:54:42 BST; the record cites three master commits: 00b8cd1b (the rule set, the board, the roll-up and every lane's 00:00 reading), 2882352c (the close), 9649f51e (the final section 14: the totals about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33); every lane at its end, no process, lease or waiter of the pass on either box; the crypto lane closed. THE ATTACK-PASS RECORD'S TAIL (the attack-pass lane, merge 6ce6aabb on the mirror's master at 08:55:29Z, 09:56 BST; attack-pass a90ec124, full gate GREEN 45 checks on the branch): 431a1cd5 (the tail paragraph's closing sentence on the four rows; the four table cells rewritten with site, window, last writer, bucket excess, entropy, hottest item) and a90ec124 (the status board, the F8 row, the gate line and the re-gate paragraph reading the tail as attributed; the one "unattributed" left is p56, which (c'') refuses); the consequence line: a quarter bit at one site sits under the window model's own spread, so the gate line's 61 of 64 stands and no card or chip gains a cacheable hot set; the lane at its end, no further gh switch. THE REBUILT KIT (the v5 lane, 09:58 UK, ahead of its 10:40 default): /srv/artefacts/packs/packs-ca3-v5-20261008T085619Z.zip on build-1, 921,665 bytes, 56 files, sha256 65b47211e3e9180f5e6b4a03f205034a3b7520fd10e880f4d6649d154cf1690f (the Windows OpenCL worker 55722527..., built 09:57 UK from the Intel-fix tree); the emulation check and the NVRTC worker's CPU run PASS on v5-dn3-epoch0; the suite on box 2 green (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs, ids and 82b19cbde8557ea5 byte-identical, recheck 2, scratch 7, spec_readback 3); commits a55fcc10, c0d398a1 (the Arc job keeps the host's whole stdout as RESULT lines), 8f481459 (a C99 declaration-order fix the kit build caught) on both mirrors; the Arc re-read with the hash lane through the shipper's PC 2 queue. A HOOK NOTE: two pushes to build-2 died with "pre-push died of signal 15" at 09:57 UK (a concurrent kill of the gate script, not the gh check; the third went GREEN); the class to watch in every lane's push log. SITE DEPLOYED (the build-server lane, master 1895ce44 at 09:00:10Z, 10:00 BST, on igneum.network and igneum.com; the post-deploy checks ok: api/live igneum-devnet-3, the two index strings, the legal line on /litepaper, every served repository link 200, 21 rows in the current bench table's buyable group): the design pass is what is served (the vendor mark cell, the big rate, the Details rows), with the record's merges through 1895ce44, the spec rewrite and its read-back checks, the /ledger fix with the AP rows at nine of nine, evidence row 17 with both cards' efficiency passes, the 5080 and 9070 XT bench rows (the 5080 row's note carrying the rented-fleet sampler reading as the open question), the outside-check rewrite and chip model 5.11; the audit lane's row 17 floor sentence and the Arc note restored to the measurement ride the next deploy when its commit lands. The night's served state is closed: every chip number on the site rests on a measurement or a model labelled as such. ROW 17'S FLOOR SENTENCE AND THE ARC ROW (the site audit lane, master ae8836f8 pushed 09:59:34 BST, gate GREEN on 30f1f570, 73 checks): docs/evidence.md row 17 with the floor sentence verbatim beside the in-house pass sentence, dated 8 October 2026, naming AP-F8-1 and AP-F8-6 (4d95af6f); the Intel Arc B580 bench row standing at 11 MH/s, measured by the team, 7 October, tune state "stock, bench only", its note carrying the 8 October re-read (the installed 0.3.21 worker's self-test 96 of 96, 54 re-checked blocks at 10.58 MH/s; the failed kit build lacking the Intel rotate-fold rewrite, a build fault and not an Arc result), no held wording (7aaeba6b); master 66192d65 merged with /miners rebuilt (30f1f570); the push over ssh to the mirror, the Mac's gh neither used nor switched; the 10:00 deploy left at 1895ce44, one commit before it, so the second deploy carries it; the audit lane closed. THE 0.3.25 NODE BUILD'S SHAPE (the node lane, 10:0x BST; release-0.3.25-node opened from the pin 5b673577 in a second worktree, release-0.3.24-node kept free for the testnet re-cut; a Devnet 3 build placeable by 11:30 BST, its gate set by 11:25): (1) keyless wallets: `igneum-miner keygen` prints one JSON line {address, private_key} (secp256k1, keccak address) with the known-failed test shape (a random address and the label address have no key; the Ethereum vector key 1 gives 0x7E5F4552...; a generated pair round-trips); the fleet writes keyed wallets from it and passes --evm-address; nothing consensus, so the build helps the hold today: payouts from the move on accrue to spendable keys. (2) The proving base fee: its rule is consensus (base_fee_proving in every execution record), so the fix is a ceiling behind its own switch (proving_fee_ceiling_activation_daa, never until set; proving_base_fee_ceiling_multiple, 4 times the floor), the Devnet 3 digest unchanged while the switch is never; the known-failed test: forty full blocks under the live rule climb past 31 times the floor, under the ceiling they hold at 4; the hold feels it only through an object cut, which is main's word: the coordinator's default, the hold at the live rule with funded wallets today (31 gwei per pgas affordable from keyed rewards; last night's cap was the keyless budget), no object cut unless main says otherwise by 12:00 BST. (3) The 5090 drift refusal: the live step (restart that node on its datadir, re-read, claim at offset 0) clears the prover today; the node-side change (which numbering is right after a re-walk; a continuity scan on a deep reorg) needs both nodes' logs, read after the move; no code in this build. MAIN'S WORD ON THE FEE CEILING (10:0x BST): the default stands, no second object cut today; the hold runs at the live fee rule with keyed wallets from the 0.3.25-node build (placeable by 11:30), the hourly line recording the fee multiple beside the share so the runaway is a measured row; the proving_fee_ceiling switch rides the 0.3.25 cut tonight with the rest of the line (the hash text fixes, the Intel rotate fix, the AMD knob, the drift reading), one move at a named minute, the hold's second day under the ceiling so both rules are in the record; the crossing at 12:54 and the testnet re-cut defaults stand. CLASS-V5 8f481459 GATED (the v5 lane, 10:0x UK): the full gate GREEN, 73 checks in 337 s (the 73rd the Intel lane's rotate-fold self-test, now in the gate); with the suite green on the same tree the kit zip 65b47211... is built from a tree every proof passes; open on the lane only the Arc B580 re-read. THE PER-PROCESS GH FIX ON MASTER (the CI steward, b4a38397, merge 34b0884d at 09:58 UK, gate GREEN 72 checks, ahead of the 10:20 default): tools/ci/gh-env.sh sets GH_CONFIG_DIR=~/.config/gh-igneum for the gate, the hook, merge-to-master.sh and ci-state.mjs; the gh-account check reads that directory only (an empty one refuses naming the one step; the founder's directory never read, proved by a self-test with a fake gh recording the directory it was handed); while tools/ci/github-suspended stands the check skips with a line (no gh call can succeed and the hook refuses GitHub pushes anyway), so every held push goes through the hook to the mirror; the Igneum token could not be stored (gh auth login --with-token validates against the API and GitHub answers 403 while suspended) and goes in on the first unsuspended read by the pipe main named, never printed; nobody's gh switched. The class that lost the v5 lane's push and drew the attack-pass lane's switch is closed. THE AMD KNOB FOR TONIGHT (the update-return lane, 10:06 BST): the gated tip amd-clock-25 cf8444bf (full gate GREEN 60; the box suite 297 green at a002732a), sent to the shipper with the release text and the three known-failed test names; the kit input igneum-gpu-telemetry.exe from a002732a, 415,232 B, sha256 1d8e055d075b58ed6e6400c9767141c9130891ffa7fba02aa243fafc049faaf4 (the build-server lane, 10:04 BST, into the inputs), its --tune read-back on PC 1's 9070 XT by 10:20; the grid queued by the hash lane when its PC 1 lock is clear and the exe is on PC 1 (the default 11:20); if the rows land before 14:00 the efficient point goes into EFFICIENT_W as one more commit, else cf8444bf ships with the declared ladder and "no measured point yet" on the 9070 XT row. THE 0.3.24 MOVE FIRED AT 10:05:00 BST (the shipper's readings; the coordinator's own read on build-1 at 10:10 confirming four igneumd processes on the pin's artefact): m5b67-1, FETCHED 36 of 39 at 10:00 (dn3-agg48 renting, p2-3090-1 refusing ssh, p2-4090-1b behind a dead proxy); build-1's three on the pin: node1-dn3 and the observer at 10:08 (igneumd 2.1.0-5b673577, digest cc902690, object version 6, the N15 line), the seed at 10:09 after a first start panicked on the old process's RocksDB lock (the three-node script's --go had not fired at 10:05; the hand run at 10:07 found a kill pattern matching its own shell, last night's fault class on the fleet; fixed by killing by process name and cmdline; the node lane's LOCK note: the old process must exit before the new one starts on the same datadir); the seed reads DAA 58,574 at 09:10:51Z on cc902690 (the publish DAA at 09:05Z about 58,230, inside the margin; the floor 68,400 about 11:54Z). The 0.3.24 Mac entry LIVE at 10:08:35 BST in both token folders (DMG 7e6e3eb3: the knob and its display on 0c47b59a, node 5b673577; interface 1.0.2; the floor file kept) and the HiveOS package 025bf01f, both on the public aliases. Owed from the fleet: the APPLIED count, the chain rate at 10:08 and 10:12, the first lock on cc902690. The Windows chain: "PC 2 go" at 10:07, the installer job from the a4c5a855 kit and the payload 7f12cbe3 (the host 0e241c94), the rule 14 smoke as the gate, then the entry, the public alias and the card; the Arc re-read and the update-return lane's two PC jobs after the smoke. The 0.3.25 plan to the coordinator before 14:00 BST. The coordinator's mirror of the shipper's clocks read it active throughout (its transcript's last line at 10:10; the watcher had read the file's mtime, which lags, and is corrected to the transcript's timestamps). After three lost floors and a stood-down night, 0.3.24 is on Devnet 3 with class v5 at DAA 68,400, about 12:54 BST. THE 0.3.25 PLAN (the shipper, 10:1x BST, from the mirror's tips). Branch and pairing: the app line release-0.3.25 from release-0.3.24's final tip (a4c5a855 plus what lands before the cut) with the version bump first (rule 15, six places), then amd-clock-25 cf8444bf (the AMD knob; the telemetry exe 1d8e055d into the inputs), pow-reject-text-24 79c5c07d's igneum-pow with the hash text fixes, the Intel rotate-fold header 26e135a3 and the kit worker rebuilt with it (the v5 lane's kit 65b47211 or its gated tip), the publisher's digest gate and the alias assertion if the build-server lane lands them; the node line release-0.3.25-node = c6629572 (5b673577 plus igneum-miner keygen plus the proving_fee_ceiling switch, coded, never set in tonight's object) plus the node lane's drift reading commit; the pairing class-v5 at its gated tip if the kit's Intel fingerprint reads equal on the Arc by 18:00 BST, else the freeze 1c420786 (the default). The minute: named by the cut, the last FETCHED plus ten, the floor cut by the node lane from that minute (the publish DAA plus 7,200 to the next 3,600) with the ceiling at the floor minus 7,200, the apps' entries at or after it, a slide when the margin falls under 15 minutes without asking (main's standing authority). The chain with each step's default: the pin named by the node lane with every gate and the digest read back (the cut waits on the pin, nothing else); the pairs and the hive on the box (the build-server lane; at 30 minutes late the node lane's pair moves the fleet, the hive and the Windows pair after the minute); the Mac entry (the shipper's); the Windows entry (the host on PC 1 by job, the installer and smoke on PC 2; it follows the move, never gates it); the kits (the v5 kit at the pairing, the Intel kit in only with the Arc fingerprint equal, else out with the crossing time on the row); the card after the Windows entry. The gate set before the file goes: every box suite on the pin, the two canary sets with the mixed-version refusal, the fast-time SUMMARY on the shipped pair, the kaspa-pow pairing read-back, the app crate gate and pre-push on the app tip, the pack-gate line read back on every reachable box, F8 if the pairing moved off 1c420786, the F9/F1 interim at the minute minus five if F8 was rerun. The move's mechanics from today's lessons: the puller takes the pair's miner sha from the move file (the fleet's puller fix), a box with no running box-dn3.sh restarts from a quoted environment (the nine-node fault of 10:05, the fleet's third known-failed shape), build-1's three by process name with the old process's locks released first. Open: the drift reading's commit (not a consensus field by its description); the evening minute from the shipper the moment the pin is green. CARD-IN READY (the hash lane, 10:1x UK; tools/ca3-v4-amend/pc-card-in.ps1 at 3566ecfe): both known-failed shapes recorded on PC 1 (the baseline of 4 cards; "no new card" in 1 s); a relay "in" with the PC publishes one job (55-minute cap) giving the card's key, VRAM and dataset fit, the v5 and v4 fingerprints through the OpenCL kit on every vendor plus the CUDA sub-version 3 row on NVIDIA, the rate with all three power fields, the lock grid through the helper on NVIDIA (300 MHz steps from the maximum, stop at a 3 percent fall) and measure-only rows on AMD and Intel, the app's own row, the bench-log and miner-bench.json rows as RESULT ROW lines, the restore and "next". The Ember tiers' engine half on ember-tiers-25 at 91406944 (local; the push on the box test build's green by 10:45). The Arc re-read's default: 10:50 UK unless the shipper clears PC 2 earlier. MAIN'S WORD ON THE 0.3.25 PLAN (10:1x BST): it runs as written, one addition to the app line: the three-tier Ember Tune, both halves (the hash lane's engine fields and the apply Cmd on ember-tiers-25; the UI lane's tier buttons with rate, watts and the daily saving, sweep on by default at balanced, per-card wired), gated on 0.3.25 before the cut; if either half is not green by 19:00 BST the cut goes without it and the tiers ride 0.3.26, stated in the record; everything else stands, the silence-means-go at 17:00 and the shipper's minute; two readings to main: one when the pin is green, one at the minute. THE FOUNDER'S WORD AT 10:2x BST: push 0.3.25 everywhere as soon as possible; the plan stands in every mechanic, the clock moves: the cut goes the moment its inputs are green, not tonight. The targets: the node line placeable 11:30; the app line assembled by 12:30 (the AMD knob and exe, the hash text fixes, the Intel header and the rebuilt kit worker, the tiers if both halves are green by 12:30, else they ride 0.3.26 and the record says so); the pin green by 13:00; the move at the last FETCHED plus ten but never before the class v5 crossing at 68,400 (about 12:54) has been read clean by the node lane, so the earliest minute about 13:30; Mac and Hive at the minute, Windows behind it within the hour, the card after; the pairing default 1c420786 unless the Arc fingerprint reads equal by 12:30; the defaults and the slide authority stand; main's silence past any of these clocks means go. THE TIERS' UI HALF (the UI lane, 10:52 BST): branch tiers-25 off release-0.3.24 a4c5a855 = the UI commit e6571f60 plus the merge of the hash lane's ember-tiers-25 3408db40 (d3d0704a); the UI tests known-failed first then 73 green on build-2; mock captures of the three states (the measured 5090 and 5080 at Balanced; the install's first minutes with nothing measured and Ember Tune on at Balanced; the M5 Max with no lever as Stock alone with the reason) under ~/Desktop/igneum-previews-2026-10-08/tiers/; the app crate gate and the full pre-push gate running on the merged tip, the gated tip by about 11:15, inside the 12:30 default; tiers-25 fast-forwards onto release-0.3.25 when the shipper opens it from a4c5a855; the live tier numbers come from the engine's own search, not from any table. THE BUILD-SERVER LANE'S CLOCKS (10:1x BST): the 0.3.25 pairs the moment the pin is named (the start script parameterised on the pin); the publisher's digest gate (publish-manifest.sh --node-bin, --network-digest, --move-clock; tools/digest-read.sh) landing on master before 12:30 and riding the app line (the alias assertion not its own); the telemetry exe's --tune read-back on PC 1 DONE at 09:07Z (the 9070 XT tune line: gmax 0 range -500 to +1000, plimit 0 range -30 to +10, factory 1); the second master-only deploy started 10:15 BST on master's tip. A FAULT: PC 2's 0.3.24 Windows installer failed at ISCC because release-0.3.24's .iss still carries the TDateTime line the 0.3.23 fix removed; the one-line fix with the shipper and the update-return lane, the republish on their tip (the Windows entry's default: it follows the move, never gates it). A SPEND TO SURFACE: two new Hetzner boxes provisioning (build-3 HEL1 32 threads, build-4 FSN1 96 threads, in the pool by 10:45), reported by the build-server lane; ordered on the founder's own word in chat ("re order", about 09:5x BST, after he added the credit himself; main clicked the order in his Chrome profile); the standing rule on purchases held; they stay. SITE DEPLOYED AGAIN (the build-server lane, master f98e8e7c at 09:15:33Z, 10:15 BST, on igneum.network and igneum.com; the checks ok): the tip carries ae8836f8 (row 17's floor sentence, the Arc row restored to its measurement) and the record through the twenty-eighth landing; the served state now carries every served change of the night and morning. THE 0.3.25 NODE LINE PLACEABLE (the node lane, 10:1x BST, ahead of 11:30): release-0.3.25-node = c6629572 on both mirrors (the pin 5b673577 plus igneum-miner keygen and the proving-fee ceiling switch coded and never set), pairing igneum-pow 1c420786; every gate green at 09:16:28Z (build 09:13Z rc 0, igneumd 3fadca49..., /srv/artefacts/0325-c6629572/node-lane; consensus 134, pow 19, miner 29 with the keygen test, p2p-flows 38, exec 48, core 177 at gate priority after a first run on a stale file on the box); the Devnet 3 canary (09:13:25Z to 09:15:04Z): digest cc902690 unchanged, byte 6, the override refused, two empty nodes handshaking, the shared-devnet dialler rejected, and the 0.3.24 pin's node handshaking with this build both ways, so the mixed fleet runs through the placement; the testnet canary b2e856ed unchanged. The keygen read-back from the artefact printed an address and a key (the key elided in every transcript and record; a printed private key never enters a message, a log the relay carries, or this file); the fleet writes keyed wallets from it. The defaults: the line's tip at 13:30 BST is c6629572 plus the drift reading's commit only if both nodes' logs reach the node lane by 12:30, else without it; the ceiling-switch field set in the 0.3.25 object from the shipper's minute by the one-go script (the digest moves then; the hold's second day under the ceiling, as main ruled; a re-cut without asking under a 15-minute margin); the crossing line the moment the DAA passes 68,400, a red first; the TESTNET_PARAMS v5-at-0 re-cut at 13:30 unless main says otherwise by 13:15. THE AMD KNOB'S GATED TIP MOVED (the update-return lane, 10:15 BST): amd-clock-25 e2962b89 (full gate GREEN 60, the box suite 298 green) in place of cf8444bf, with the shipper; from the exe's read-back on PC 1: the integrated Radeon's tune line carries every range as a dash and the knob had read it as an offset knob with a one-MHz ladder; it now reads "not available (the driver exposes no tuning interface for this card)", and the 9070 XT's real line (gmax 0, range -500 to 1000; plimit 0, range -30 to 10; stock 3,292 MHz under load) is the test's second half: the ladder 3,192 down to 2,792, the power 70 to 110 percent, offsets on the apply; the grid by 11:20, the efficient point into EFFICIENT_W before 12:30 or the declared ladder ships. THE MOVE'S READ-BACK (the fleet lane, late against its 10:20 minute): APPLIED on the relay at 09:07Z: 24 MATCH by the puller (igneumd 2.1.0-5b673577, digest cc9026909eddbadb, synced; dn3-g1 at peers 24), p1-3080 on cc902690 by 09:10Z; 2 FAILED (dn3-r01, dn3-r02: no saved environment, hand-started yesterday) moved by hand at 09:10:27Z; 9 MISMATCH with no node after the puller's restart (hub-1, dn3-g2, dn3-q04, dn3-q05, dn3-r04, dn3-p02, dn3-p04, dn3-p05, dn3-relay): the saved environment line NET_ARGS=--devnet --devnet-suffix=3 unquoted, so sourcing it ran "--devnet-suffix=3" as a command and the start never reached box-dn3.sh; all nine moved by hand 09:11:58Z to 09:12:24Z with every value quoted, the puller now quoting every value (redeployed 09:16Z on 34 boxes); so 36 of 36 fetched are on 5b673577 and cc902690 by 09:12:24Z (10:12 BST). The first lock on cc902690: checkpoint 1931, block 63510971..., blue score 57,930, at 09:06:32Z on dn3-g1 (4,803 signed, 69.8 percent of active, 66.7 of total); hub-1 logged the same checkpoint at 09:11:43Z after its hand restart and checkpoint 1944 (blue 58,321) at 09:12:39Z. The chain rate: hub-1 read 0 blocks a minute at 09:07Z because hub-1 was one of the nine down; from 09:12Z the tip moves at about 0.4 chain blocks a second as before, and paidShards moves again (11,821, frozen since 03:32Z, to 12,012 at 09:19Z, pool entries 47): carrying resumed with the move, the node lane's one-shot-gossip class confirmed. The proven share at 09:19Z 0.465 cumulative (the hour's own 0.000, the hour being the move); the proving fee 10,000 gwei per pgas last, 50,566 max over 60 blocks (1.0x and 5.1x the floor), the field now on the hourly line. The unfetched: dn3-agg48 (the L40S in its bring-up, applying at its first tick), p2-3090-1 (ssh refused since 21:48Z yesterday, on 2720d8d2 with 4 old-digest peers), p2-4090-1b (its Vast proxy dead, its node down); dn3-relay fetched at 08:48Z and is on cc902690. The eight "bc5945fe" boxes: no such binary (that sha was the reader's own shell); those boxes had no node at all (dn3-g2 dead since 22:49Z, dn3-g1 since 00:46Z, the others overnight, no panic or OOM on any), restarted 08:43Z to 08:53Z, took the move with the rest, and mine where they mine. The keyed-wallet write not started (the 0325 artefact's first mention to the lane at 10:20; box by box after the launch fleet's first boxes are up; the rent running since 09:16Z). p1-5090's drift reads offset -5 again at 09:21Z; hub-1's numbering against build-1's node the next read. Three fault classes for the record from one move: the unquoted environment line (fixed in the puller), the two hand-started boxes with no saved environment, and the eight boxes that had silently lost their nodes overnight with no panic (a watch for a node absent while its box is up is the fleet's next check). THE TIERS GATED FOR THE CUT (the UI lane, 10:20 BST by the Mac's clock): tiers-25 at d3d0704a on the mirror (the UI commit e6571f60 plus the engine half 3408db40 merged, both off release-0.3.24 a4c5a855, a fast-forward onto release-0.3.25): the app crate gate GREEN 299 + 35 + 8 on build-2, the full pre-push GREEN 60 checks with the stamp, the UI tests 73 green known-failed first, the push gate GREEN; the captures under ~/Desktop/igneum-previews-2026-10-08/tiers/; sent to the shipper; two hours inside the 12:30 default; a rebase and re-gate inside the hour if 0.3.25 opens from a later tip. Both halves of the three-tier Ember Tune are in the cut. THE 0.3.25 APP TIP (the shipper, 10:29 BST, two hours ahead of the 12:30 target): e0d4425f on release-0.3.25 (the box gate green): amd-clock-25 e2962b89, tiers-25 d3d0704a (both halves), the Intel header via 9088293a, the node-source pin c6629572; the node pin candidate c6629572 with the digest cc902690 unchanged; the cut list r0325-cut-list.md: the pin named by 13:00, the move no earlier than 13:30 after the 68,400 crossing reads clean; the pairing 1c420786 unless the Arc reads equal by 12:30, the Intel kit on that read. THE 0.3.25 NODE LINE'S TIP MOVED (the node lane, 7bd2940f on both mirrors at 09:24:03Z, every gate green at 09:29:48Z): c6629572 plus the one-shot gossip fix (unpaid proof records re-announced every 120 s; the class confirmed on the live chain after the 09:05Z move); nothing consensus, the Devnet 3 digest cc902690 unchanged on its canary, the 0.3.24 pin's node handshaking both ways, the testnet digest unchanged; build 09:26Z rc 0 (igneumd 16dee9f1..., /srv/artefacts/0325-7bd2940f/node-lane), exec 49, pow 19, core 177, p2p-flows 38, miner 29, consensus 134 at gate priority; it replaces c6629572 as the placeable keygen build and as the tip the ceiling-field cut lands on; the shipper has the line. The drift item is off this line: the fleet's reads were shared-devnet reads (hub-1's node on 26790 at chain block about 190,900; Devnet 3 at 25,900; both answering chain id 4463 below the floor), p1-5090 a shared-devnet prover, and the three numberings at one hash are the snapshot-inherited class (build-1's node1 itself resumed from a snapshot); the fleet rents a fresh-walk node under its standing ceiling to settle which numbering is right, hub-1's restart held until then, the loader change (re-number the resumed range against the DAG) after that read. THE 0.3.25 PAIRS ON 7bd2940f (the build-server lane, from 10:33:11 BST on build-1 under lease class release, /srv/artefacts/0325-7bd2940f/: the seed about 10:36, the Windows pair about 10:38, the hive package with the three kit zips about 10:41, each minute to the shipper and the coordinator); the c6629572 pairs already built (seed f913e3e7, win 42d0dd57, hive 14d86245) stand in their own folder and are not the cut; the publisher's digest gate on master since 10:17, riding the 0.3.25 app line. THE RE-POINTED APP TIP (the shipper): 92f004f1 on release-0.3.25 (e0d4425f plus the node-source pin to 7bd2940f), the push gate GREEN at 10:32 BST, the box gate GREEN at 10:33:25 (303 + 35 + 8); the cut list's pin candidate 7bd2940f; the kit re-cut from 92f004f1 and the pairs on 7bd2940f's artefact with the build-server lane; the Mac node pair and the DMG rebuilding on 7bd2940f under the lock from 10:32:31; the 13:00 pin and the 13:30 earliest minute standing. The 0.3.25 inputs are all green at 10:33 bar the pin's own gate set and the crossing. A SWEEP FINDING FROM MAIN (10:4x BST): on a rented, power-capped RTX A4000 (114 W cap) class v5 reads 26.0 MH/s against v4's 31.4, 17 percent under, the fingerprint equal; the A100 1.3 percent under; every uncapped consumer card level: v5 costs more compute per hash and a compute-limited card pays, which is what a knee lock makes of a card. Two orders with readings by 12:30: (1) the hash lane sends the 5090's v5 pack rows at the 1,300 lock against v4 at the same lock, and the 5080's if they exist; if v5 at the knee loses more than 2 percent, the knee is re-found under v5 and the tiers table says so; (2) the tiers' engine half: a class change (the chain's program class flipping) invalidates the stored tiers and re-runs the search within ten minutes of the crossing, the first-run line saying why; known-failed first (tiers stored under v4 must read "re-measuring for class v5" after the flip, never apply as if current); on 0.3.25 if it fits by the cut, else 0.3.26 with the record saying the v4 tiers may be off by the measured percentage until the re-tune. Per tier: a locked card may lose a few percent of rate at the class v5 crossing until Ember re-tunes; the number is the 5090 row. THE ORDERS PLACED (the coordinator, 10:4x BST): the hash lane's two readings by 12:30 (the 5090's v5 rows at the 1,300 lock against v4 at the same lock, the 5080's if they exist; the knee re-found under v5 if the loss is over 2 percent; the default if the PC 1 queue cannot run it: the A4000's 17 percent stated for a capped card and "unmeasured at the knee on the 5090"; and ember-tiers-25's class key: a class change invalidates the stored tiers and re-runs the search within ten minutes, known-failed first), the UI lane's class-flip state ("re-measuring for class v5", v4 tiers never applied as current after the flip) and knee note by 12:30, the shipper's cut list carrying both on 0.3.25 only if green by the pin at 13:00, else 0.3.26 with the record's sentence that the v4 tiers may be off by the measured percentage until the re-tune. THE 0.3.25 PAIRS ON build-1 (the build-server lane, /srv/artefacts/0325-7bd2940f/): the seed pair at 10:34:44 BST (igneumd c7fc542b, igneum-miner 4494ecc4, glibc 2.34), the Windows pair at 10:36:13 (igneumd.exe 5d1dea23, igneum-miner.exe eee7bdfa), the hive package igneum-hive-0.3.25-7bd2940f.tar.gz at 10:37:49 (sha d977797f..., the three kit zips, smoked in ubuntu:20.04); the kit re-cut from 92f004f1 (sha 676240f6, 424,540 B) staged in both folders, the PC 1 host from it bc8d4f79 (in host.sha256 at the shipper's 24680e1d), the 0.3.25 Windows payload from 24680e1d cutting. Every pair of the cut exists by 10:38; the pin's gate set and the crossing are the only waits. FOUR NEW LANES ON THE FOUNDER'S ORDER (11:00 BST, "build all this today to close this gap"), mirrored by the coordinator as the shipper's clocks are: the explorer (a5ef1d5801084005b; explorer.igneum.network by 16:00), the canonical DEX and the Sepolia certificate verifier (a74a8267813d6ea34; the AMM by 14:00, the swap UI by 17:00, the verifier by 20:00), the builder pages, faucet and grants (adb29da59baf27898; /build and /grants by 15:00, the faucet by 16:00), three reference apps that only work on a proven chain (a2060899d2a27d31c; /light by 16:00, /receipt by 18:00, the Sepolia oracle demo by 21:00); the build-server lane stands up rpc.devnet.igneum.network by 12:00; they do not touch the 0.3.25 cut, the crossing or the fleet, sharing the boxes' lease pools (class measure) and the master-only deploy; a lane silent past 25 minutes gets the word from the coordinator and then main. THE FAST-TIME GATE ON THE 0.3.25 PAIR: SUMMARY PASS (cross-0325-39f127a1) at 09:54:40Z (10:54 BST) on the pair 39f127a1 (the node code and object byte for byte e0644958's; igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 09:42:25Z to 09:54:40Z, every check green (rung 1 by signal at epoch 6, class v5 by signal at byte 6 from epoch 8 at rung 1 at 9,985 bps, the stale node refused, the restart step resynced in 8 s, four sinks equal, 0 PoW rejections); the ceiling's two new fields absent from the 60x file so the ceiling stayed at never there (the node lane's note); to the shipper the same minute; the pin line names e0644958 and its gates. THE FOUNDER'S WORD AT 11:0x BST ("can we add in any more layers? class rotating? things that would render an ASIC useless as soon as it dropped"): the class v6 design opens today as a rotating family, the research lane and the hash lane under the coordinator, the design doc docs/design/class-v6-rotating-family.md by 18:00 BST with the chip-model rows beside each layer (what it does to k and capex for a fixed-function chip and to the per-joule edge for a GPU-like chip; what it costs every GPU tier, Apple included): (1) per-era draws of the class parameters now fixed by release (the mixer round count within the tested margin, the op-mix weights within the measured safe band, the read width, the program length, the shadow placement), drawn from chain state like the program; (2) the state-derived dataset's size tracking chain-state growth with a floor, so fixed-memory silicon ages out; (3) scheduled family epochs by height (every 180 days by default) with no release; (4) the (c''') acceptance floor and the F8-form uniformity test generalised to each era's parameter draw, redraw on failure, so layers 1 and 3 need no per-era cryptanalysis. Per layer: the gate it needs (the family analysed as a family: the attack board's shape over the testnet period), the known-failed test, an honest line on what a fully general chip still gets. No consensus code this week; the document, the numbers and the gate plan. Per tier for the founder tonight: what each layer does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE ARC RE-READ IN ITS CHAIN (the hash lane, 10:57 UK): no clear came from the shipper, so the default ran at 10:50: the rotate-fold kit's fetch (sha 65b47211) published to PC 2 at 10:51:41, the run (run-ca3-pc2-v5-intel-bench-20261008, the v5 lane's script c0d398a1) in the publish chain behind another lane's publish-jobs.sh sign --deploy from the build-server worktree (the publisher serialises); the fingerprint line by 11:15 if the publisher frees inside ten minutes, else the blocking process named by 11:10. Queued on PC 1 behind the same publisher: run-ca3-pc1-v5lock-5090-20261008 (class v5 against v4 at unlocked, 1,300 and 1,200 MHz, the v5 kit's CUDA packs), its rows by 12:30; the AMD grid after it from about 11:25. The class-key work on ember-tiers-25 started; the v6 cost rows by 16:00 taken. THE TIERS' CLASS-FLIP STATE, THE UI HALF (the UI lane, 10:57 BST): tiers-class-25 at d949e274 on the mirror, off release-0.3.25's tip 24680e1d (the shipper having merged tiers-25 d3d0704a into release-0.3.25 at 111dae69), the crate gate GREEN 303 + 35 + 8 on build-1, the full pre-push GREEN 60, the UI tests 74 green known-failed first (the v4 tiers stayed on the buttons after the flip on d3d0704a); after the flip the table reads "re-measuring for class v5" on every button with the start minute or "queued (within ten minutes of the crossing)", the v4 watts never current, the strip's sentence naming the crossing; the knee note under the table when knee_loss_pct is over 2 percent; the captures tiers-flip-dark.png and -light.png; the fields tiers_class, program_class, tiers_remeasure_at, knee_loss_pct (the shape sent to the hash lane at 10:4x; the engine sha by 12:30); the default: the display rides 0.3.25 inert if the engine half is late and lights up on 0.3.26. THE FOUNDER'S WORD AT 11:1x BST: class v6 is DECLARED with the four layers as its spine (per-era parameter draws, the dataset tracking chain state, scheduled family epochs by height, the acceptance floor generalised to parameters), and deep past-and-future research opens now under the coordinator with serious resources ("see if anything can be optimised, added or invented"; reading public research is in-house, nothing paid or asked of anyone outside): four research lanes today, (A) history (every ASIC-resistant proof-of-work and how it fell or held: Ethash and the E3 and Linzhi chips, ProgPoW's review, RandomX and its chip analyses, Cuckoo, Equihash and the Z9, Argon2 and Scrypt and the Litecoin chips, KawPow, Autolykos, Octopus, kHeavyHash's chips; the exact mechanism each chip used and what the design missed, each mapped to Igneum's layers with "does v6 close it" as a sentence and a number), (B) the hardware future five years out (PIM and processing-near-memory, HBM3e and HBM4, LPDDR6, 3D DRAM, CXL memory pools, wafer-scale, chiplets, FPGA with HBM; for each the chip-model k band against a state-sized dataset and dependent random reads, and the one layer that would blunt it), (C) invention (layers beyond the four, each a paragraph, a known-failed test and a chip-model row: data-dependent program graphs, latency-bound dependent reads tied to the shard proof, randomised memory topology per era, VRAM-size ratchets, proof-carrying hashes sampled by the pool, time-locked parameter commitments, and what the lane invents; rejecting what costs GPUs more than chips), (D) the family gate (how a parameter family is cryptanalysed as a family: sampling bounds, coverage, the F8-form and (c''') tests over the parameter space, the attack board's shape over the testnet period, so layers 1, 3 and 4 can be automatic with a proof of what was tested). Resources: all four boxes under lease class measure, PC 1 by job for card rows, the rented fleet for one-shot measurements inside the ceiling. Deliverables: a first synthesis in docs/design/class-v6-rotating-family.md by 20:00 BST (the four layers priced, every finding from A to D with its number, a ranked list of what v6 adds beyond the four, the honest line on what a fully general chip still gets), the full report by 09:00 tomorrow, one line to main per lane as each lands; per tier at 20:00: what v6 does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE 0.3.25 APP TIP AND PIN CANDIDATE (the shipper, 10:58 BST): the app tip 9b93e649 (push gate GREEN; the crate unchanged from e0d4425f; the node-source pin to e0644958 and host.sha256 bc8d4f79); the pin candidate the node lane's ceiling cut e0644958 (digest 1b37cb9d, every gate green 10:53, the fast-time SUMMARY PASS 10:54, the floor at DAA 82,800 about 16:53 BST, a publish up to 14:53 without a second cut); the tiers' class-key halves: the UI lane's tiers-class-25 d949e274 green and inert alone, merged with the hash lane's engine sha the moment it lands (12:30), gated as a pair on the release tip, riding only if green by the 13:00 pin; the 0.3.24 Windows take 2 failed at a new place (Inno stopped the app and copied nothing); the update-return lane owns the fix on release-0.3.25 by 12:30, the default the 0.3.25 Windows entry waiting for a clean take 3 while Mac and HiveOS move at the minute. THE FOUR CLASS V6 RESEARCH LANES SPAWNED (the coordinator, 11:0x BST, each with its worktree, its box resources under lease class measure, its clocks and the rules): lane A history (a603a938582c43ab5; the first cut docs/analysis/class-v6/history.md by 15:00), lane B the hardware future (a4f73e2a6f2d1b757; hardware-future.md by 16:00), lane C invention (a5dfe95ee8c47cd0f; invention.md by 17:00), lane D the family gate (a07a99a3788566af2; family-gate.md by 17:00); each feeds the research lane's synthesis docs/design/class-v6-rotating-family.md by 20:00 (its outline by 13:00; the hash lane's per-tier rows by 16:00); the full reports by 09:00 tomorrow; the coordinator's lane mirror carries their clocks. A HELD PUSH AND ITS CAUSE (11:00 BST): the hash lane's push of ca3-v4-amend was refused at 10:58 by the gh-account hook reading the founder's gh (his personal login active again; nothing switched by any lane); the cause is the branch's own hook, which predates the per-process fix (34b0884d): the hook runs the branch's tools/ci, so every branch older than 09:58 must merge the mirror's master before its next push, under which the check reads Igneum's own gh directory and skips under the suspension marker; the rule to every lane. Live: the Arc re-read on PC 2 (published 10:59:47) and the v5lock job on PC 1 (published 10:53, about 12 minutes). THE CLASS V6 OUTLINE ON THE MIRROR (the research lane, docs/design/class-v6-rotating-family.md on counter-asic-4, the commit after fb61ed4b, pushed 10:5x UTC, two hours ahead of 13:00): section 0 the founder's table (per layer, what it does to a fixed-function chip and to a GPU-like chip on its release day, and the 5090, 5070 Ti and M5 Max columns, measured where the night's rows exist, the 5070 Ti scaled until the hash lane's row); the honest frame on top: the four layers render a FIXED-FUNCTION chip useless on the first era its wired value leaves (one tape-out lives one era) and move nothing for the stored-dataset chip with a programmable core except the core's size and the N5 project it forces; that chip keeps 3.6x at zero premium and 2.1x at k = 1 on a 5090 at its knee. The layer table (sections 1 and 2) names the bands each draw takes and the measured rows that set them: the mixer in {4, 8, 16} (x16 open), the op-mix weights within B = 4 with shuffle and mulhi capped (shfl 55.8 pJ per op), the read width in {1, 4} words (w64 excluded by the 5 October rows), the block shape 64 to 256 (never 1,024), N left to the ladder's signal (an unconditional draw retires the Apple tier at 200,000). Open numbers asked of the hash lane with defaults at 16:00: the 5070 Ti row (the rented 5070 scaled), the x16 mixer's verifier and build (the chip model's estimate), two re-weighted shadow packs for the op-mix band (the microbench arithmetic). Layers 2 to 4 and the gate plan are skeletons with their sources named, filling by 18:00 with the four research lanes' cuts, the synthesis by 20:00. THE FOUNDER'S WORD AT 11:2x BST ("all builders are idle, load them up"): build-1 to build-4 filled now and kept above 80 percent all day under the lease pool, class measure behind the release gates, in this order of value: (1) the class v6 family gate's sampling runs for lane D (the F8-form census and the (c''') floor over the parameter bands: the mixer {4, 8, 16}, the op-mix weights within B = 4 with shuffle and mulhi capped, the read width {1, 4}, the block 64 to 256; thousands of drawn eras, the uniformity and bucket tests on each, so the family document carries measured coverage tonight); (2) the attack families at scale on the 0.3.25 pin candidate's igneum-pow (F8 to 256 seeds, F9 and F1 to 10^6 on the frozen 1c420786, the day-key scan to 2^28) as the record's strengthening lines; (3) the invention lane's candidate layers measured as packs as fast as it writes them; (4) the full suite matrix of the 0.3.25 pin on every box as the pre-pin check; (5) the Windows and hive cross builds and the sweep's reruns; the lease tool's pre-emption giving release-class work the cores when the pin's gates need them; one line to main at 12:00 with the load on each box and what runs there, then hourly only if a box drops idle. THE DRIFT CLASS SETTLED (the node lane, from the fleet's fresh-walk node, a shared-devnet node synced from an empty datadir to 191,441 chain blocks at 10:03:45Z): hub-1 and five standing boxes number the fresh chain exactly; seven boxes carry numbering inherited from an exec snapshot taken on a chain that later re-walked (+2: p1-4090, p1-a5000, pool-1, build-1's node1; +3: p2-3090-2; +4: p2-3090-4; +5: p1-5090 and p2-3090-3), and a restart on the kept datadir does not re-walk (p1-5090 at 09:22Z stayed +5); the cost: a prover on drifted numbering signs statements the hub vetoes, so the seven earn nothing from proving until they re-walk, the drift refusal stopping the waste. The node lane's word to the fleet: p1-5090 first, both snapshot files moved aside so the executor re-walks from the DAG, the re-walk timed and read against the fresh node, then the other six in series, hub-1 untouched, build-1's node1 after the 12:40Z move; if the re-walk reads over two hours the six wait for the node-side fix on the next node line (the loader re-numbering a resumed range against the DAG before serving). THE 0.3.25 PIN CANDIDATE CONFIRMED (the node lane): e0644958 on both mirrors (keygen, the re-announce, the ceiling switch at 82,800 in the Devnet 3 object, digest 1b37cb9d, the 0.3.24 pin refused both ways), every gate green at 09:53:01Z, the fast-time SUMMARY PASS at 09:54:40Z on the same object; the publish ceiling DAA 75,600 (14:53 BST); waiting only on the 68,400 crossing reading clean (about 12:54; the node lane's line the moment the DAA passes it); the shipper names the pin at 13:00; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. LANE C'S FIRST PACK (the invention lane, 11:0x BST by the Mac's clock; its own line read "12:1x", a clock to correct): build-1 takes the igneum-pow build from counter-asic-4 at 5984ffab, then the per-load shadow in its sound form (mx8+shl6912x1: 16 sub-blocks of 432, one pass, the form 20.2a named and never drew) as the first candidate: the acceptance census over 64 seeds and 16 drawn eras against the 16x27 form and the class v4 shape, the pack export, the F8 read at 2^24 and the verifier bench on a leased core, the first read by 13:30; build-2 next for the second candidate (warp-uniform data-dependent block selection); the candidates with no pack form (the VDF commitment, the VRAM ratchet, the pool-sampled witness, the state-tied reads) stay modelled and the 17:00 cut says so; the worktree igneum-wt-v6-invention on class-v6-invention. THE WINDOWS INSTALLER CLASS AND THE 0.3.25 TIP (the shipper, 11:08 BST): the app tip 139c147a (9b93e649 plus install-detach-25 52a34111, packaging/windows and tools/ci only, the crate unchanged; push gate GREEN); the 0.3.24 take 2 class: an installer started under the app's job runner is a child of the engine, and the engine's kill_tree on quit ended it between PrepareToInstall and the copy; the fix re-launches the installer as a one-shot scheduled task outside the job's tree; the 0.3.24 Windows entry skipped; the rule-14 take on PC 2 is the 0.3.25 installer over the running 0.3.21 app, queued ahead of the Arc re-read; the pin candidate e0644958, the DMG 501ba293 staged, the 13:00 pin and the 13:40 provisional minute standing. THE ATTACK FAMILIES AT SCALE (the attack-pass lane, cores held at 11:08 BST, every run under lease pool class measure): box 2 (88 cores): F8 seeds p66 to p257 (192 new, 256 with the gate's p2 to p65) at 2^24 on class v5 at the freeze 1c420786 (the gated binary 0f5c98dc, pairing e5a4ac5978462156; the leaves re-run on 8f481459 if the kit pairing flips), the window-model control, by-site, as three thirds of 64 seeds; box 4 (80 cores held, 16 asked): F9 to 10^6 on 1c420786 (seeds 100,000 to 999,999 in six chunks of 150,000 at 8 threads, four running), F1 to 10^6 class v5 programs on 1c420786 (one census at 40 threads with the progress line and flushed partials, re-drawing the record's first 10^5 on the way as a reproduction check), the F4 day-key scan to 2^28 on 8ca66afa's redraw rule at 8 threads; nothing on build-1 or build-3 (lane D's); the projections: F4 about 2 to 3 hours, F8's 192 seeds about 9 hours, F9's 900,000 and F1's 10^6 about 30 hours each, so the 17:00 default is partials for those two with the lane (d) rows carrying counts so far; any pre-emption by release-class work reported. THE RPC AND THE 0.3.25 PAIRS ON THE PIN CANDIDATE (the build-server lane, 11:0x BST): rpc.devnet.igneum.network up since 11:08 BST (the first of the founder's builder clocks, 52 minutes ahead); the 0.3.25 pairs on e0644958 running on build-1 since 11:06 (the app tip 139c147a), the Windows and hive crosses on build-2, build-3 and build-4 as reproducibility rows at class release by about 12:40; the sweep reruns' list not held by the lane, the default at 12:30: last night's sweep logs on build-1 read for rows that ended without a result line and those rerun at class measure. THE SWEEP RERUNS' LIST (the fleet lane to the build-server lane, 11:1x BST): the fleet ran nothing under the build boxes' lease pool last night (every fleet bench a rented GPU one-shot), so the rows the lease kills cut short are the hash and class lanes' and the build-server lane's default read on build-1 is the right one; the fleet's own rows without a result (A10, A40, A100 40 GB, H100 NVL, H100 PCIe, MI250, RTX 3050, RX 7800 XT, 7900 XT, 7900 XTX, 6900 XT) are provider gaps needing a GPU host, rerun the moment a provider lists one. THE CLASS-FLIP TIERS, BOTH HALVES (the UI lane, 11:13 BST by the Mac's clock, 1 h 47 min inside the 13:00 pin): tiers-class-25 at 081b3ba7 (the display d949e274 plus the hash lane's ember-tiers-25 0a838072, on release-0.3.25's 9b93e649; the field names matched exactly): the crate gate GREEN 305 + 35 + 8 on build-1, the pre-push GREEN 60, the UI tests 78 green known-failed first, the push gate GREEN; with the shipper. A RED ON THE RELEASE TIP, for the shipper and the update-return lane: release-0.3.25's 139c147a is red on one crate test (ota::return_tests::no_relaunch_while_an_installer_runs_and_a_relaunch_when_it_clears, 304 of 305): install-detach's 0c588b09 reshaped the installer's clear step into a multi-line block while the test asserts the one-line literal at app/igneum-app/src/ota.rs:1348; 9b93e649 passes; the fix is the test's literal on the install-detach line; the UI lane built on 9b93e649 so its tip is green alone. A RED FROM THE PIN MATRIX (the CI steward, 11:13 UK): the core suite fails on the pair (the node e0644958 with the app tree 9b93e649): config::params::tests::fast_time_60x_file_is_the_devnet_at_60x panics "override-60x.json lacks the field base_unit_decimals"; the field was added by 0e4ec18a on ca3-v4-node yesterday at 21:45 UK and reached neither master, release-0.3.25 nor the app tip while the node line's test demands it; so every box reads red on core, and the fix is one line on release-0.3.25 (the cherry-pick of 0e4ec18a, or "base_unit_decimals": 8 in infra/fast-time/override-60x.json); sent to the shipper; green so far pow and app on build-1 and build-3; the two new boxes' toolchains read the same as build-1 (Ubuntu 24.04.5, glibc 2.39, the pinned rustc, sccache and lease, no nvcc). The founder's fourth load item paid in its first ten minutes: a red no single-box gate had read. MAIN'S WORD ON THE TWO REDS (11:1x BST): the install-detach fix belongs in 0.3.25 if it can make it, since a Windows install by any path that lets the engine's job runner kill the installer mid-copy is the plug-tune-play fault class (an update a user repairs by hand); the default order: the update-return lane fixes the ota.rs literal by 12:00; if 139c147a plus the fix is green on the crate gate by 12:15 the cut goes from it, else from 9b93e649 with the detach on 0.3.26 and the record saying Windows installs by job stay unreliable until then; the missing 60x field: the CI steward lands the one-line field on master and the release line by 11:45; the pin slides under the shipper's authority inside 14:53. THE DAY-KEY SCAN TO 2^28 (the attack-pass lane; class-v5 8ca66afa's redraw rule, build-4 under lease pool 8 class measure, 379.2 s, census-2p28.md at 10:15Z, 11:15 BST): days with any gain over 1.1x: 0 of 268,435,456 on M1 (median 226), 0 against the mean, 0 on M2, 0 on ROT and RC; the M1 cost mean 225.791, sd 6.073, min 206 (day 27,016 at 1.0971x, the redraw rule's floor: no day under 206 in 2^28), max 258; every weak class on its analytic expectation (ROT any pair summing to 32: 160,354,008 against 161,256,979; RC any zero: 1 against 1.0, at cost 234, no gain; RC with rk = 0: 87 against 72, 1.8 sigma; the two cells under expectation the rule's own refusals). PASS: no chip buys a weak day in the first 735,000 years of days; at most 1.097x on the best day. The row and f4-weakday.md section 10 committed on attack-pass at eabb4b0e, the push held by the branch's old hook (the fix: merge master, under which the check reads Igneum's own gh directory and skips under the suspension marker). THE SWEEP RERUNS' READ (the build-server lane, 11:18 BST): build-1's records hold no hash-lane or v5-lane run the pool cut short (preempt.log: three TERMs all night, every one to an adv-class holder pre-empted by a release gate, not reruns by rule; no reaped.log; builds.jsonl for 18:00Z to 09:00Z 150 rows with no signal end, the non-zero rows the fast-time gate's designed failed cases and build errors; the census and fingerprint suites leaving no builds.jsonl row and no output directory ending without its result); live at 11:17Z the family gate's v5_attempts_census holding 24 cores on build-1 at class measure; the default at 12:30 if neither lane names a run: no reruns, the boxes carrying the e0644958 reproducibility crosses (build-3's Windows pair already read: igneumd.exe 4b0c3aeb, igneum-miner.exe b3da4088) and the gates. The founder's fifth load item is therefore the crosses, not reruns. The attack-pass branch merged master and pushed (460fd9fa, the F4 2^28 row and f4-weakday.md section 10 on the mirror; the hook skipping the gh read with its suspended line; nothing switched). THE FAMILY GATE'S FIRST COVERAGE (lane D, 11:2x BST by the Mac's clock; its own line read "11:3x"): the harness live on build-1 under lease pool class measure (scripts and pinned binaries under /srv/builds/_adv-family-gate/): (1) the base control v5_attempts_census on the shipped class v5 draw over f8-label seeds 1,000 to 11,000, 24 cores since 11:16; (2) the family harness family_gate_era_census (branch family-gate-v5 = class-v5 8f481459 plus the harness, never a chain path; the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE): one drawn era per seed, every layer-1 parameter from the era's own stream (the shadow block {64, 128, 256} x {108, 54, 27}, the mixer {4, 8, 16} recorded, the read width over {1, 4} words, the ten weights within B = 4 with shfl and mulhi never raised), the chain draw through the real rule with every candidate's first failing part, then on the accepted program at the rule's own 2^20 sample the (c'')/(c''') ratio, the largest 256-item bucket per site (ratio and sigma), the index-bit bias per site in sigma; the 16-era smoke run PASSED at 11:21 (about 10 core-seconds per era; 10,000 eras about 28 core-hours). THE WORST READINGS IN THE 16: (a) the index-bit bias read fires HARD on 7 of 16 eras, |z| 130 to 511 at one site, every one at address bit R (the era's stride rotation) or R+1 (era 15 with R = 25 bit 25 z -511 at P(bit) 0.25, a product's bit 0; era 7 R = 17 z -468; era 5 R = 26 z -440; era 13 R = 1 bit 2 z -255, a product's bit 1 at 3/8; era 1 R = 6 z -224; era 12 R = 5 bit 6 z -130; era 6 R = 18 z +256, an or-shaped source at 5/8), the other 9 under |z| 3.8: adv-cache-2's era-stride class measured at the acceptance's own sample on class v5 accepted programs: not diffuse at the bit level, a 25 percent bias on one address bit of one site in about 40 percent of drawn eras, which (c''') does not see (min ratios 0.9954 to 1.0000); a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50, about 1.6 percent of a hash's reads at f = 1/2 for one site, which does not move the f = 1 verdict but is an auditor's flag on "uniform random reads"; the lever is load_index's form (fold the product's low bits before the rotation), not a floor (a 6-sigma refusal would redraw about 40 percent of epochs): a class v6 design row. (b) The (c'') ratio min 0.9954 (era 7), the rest 0.9965 to 1.0000. (c) Attempts: 14 of 16 accepted at attempt 0 or 1; era 9 (shape 64, width 4, mul 11 and or 8 of 75) took 24 candidates: the lossy corner raises r, the exhaustion number to read per stratum. (d) The largest 256-item bucket: ratios 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets, +4.4 sigma), so the F8-tail bound must be stated in sigma, not ratio (the sigma column in the rebuild). Next: the random stratum (10,000 eras) and the corner strata (the lossy cap, width 4, shape 64, 3,000 each) on build-1's free 64 cores, then build-3 and build-4; the first cut of family-gate.md drafted, the measured coverage table in at 16:xx for the 17:00 cut. THE OTA TEST LITERAL FIXED (the update-return lane, 11:23 BST, ahead of both clocks): ota-test-25 off release-0.3.25 139c147a, tip 53cb2f73 on the mirror, one test-only commit (the test reading the installer's clear step as the begin/end block the detach made it; the detach's behaviour kept), the box 2 crate suite 303 + 35 + 8 passed, 0 failed, the full gate GREEN 60; the shipper's cut tip 139c147a plus this commit, so the install-detach rides 0.3.25 and the PC 2 rule-14 take runs on it. THE 60x FILE, THE WHOLE FILE NOT ONE FIELD (the CI steward, 11:25 UK): the test names the first missing key in key order; with base_unit_decimals in it named emission; the file on master and release-0.3.25 lacks six keys the 0.3.25 node line's OverrideParams has (base_unit_decimals, pool_split_activation_daa, program_class_v5_activation_daa, proving_base_fee_ceiling_multiple, proving_fee_ceiling_activation_daa, subsidy_per_block_activation_daa); ca3-v4-node's copy (81 keys, master's 75 plus those six, no shared value differing) passes on build-3 by hand; release-0.3.25 got the one-field commit 907fdaf4 at 11:23 and the whole-file commit follows through the hook's gate, master the whole file behind the one-field landing; the known-failed on record on all four boxes; the green from the core re-runs in the 12:30 matrix; the risk named to the shipper: an older daemon reading the file with deny_unknown_fields. THE INDEX FOLD AS A CLASS V6 DESIGN ROW (the research lane, docs/design/class-v6-rotating-family.md on the mirror, the commit after 206e81e1): load_index folds a product's low bits before the stride rotation so no era's R lands a biased bit on an address bit (a design row, not a draw and not a floor); the evidence lane D's 7 of 16 drawn eras at |z| 130 to 511 on address bit R or R+1 with the (c''') ratio blind to it; the chip row 1.6 percent of a hash's reads at f = 1/2 for one site and zero at f = 1; the cost 0 on every card (one xor-rotate on the address path); the known-failed test lane D's 7 of 16 reading 0 of 16 with the fold; the value-level bias test in layer 4 ordered after the fold as its guard; the F8 tail's largest-bucket bound restated in sigma against its own window's Poisson expectation. The 60x commits: the one-field commit on both lines (master 7be52d76 at 11:24, release-0.3.25 907fdaf4 at 11:23), the whole-file commits in their gates behind it (release cbbaa8c4 pushing, master's queued). CLASS V5 AT THE KNEE ON THE 5090 (the hash lane, run-ca3-pc1-v5lock-5090-20261008-b, 11:09 to 11:21 UK, the 5090 alone, the v5 kit's CUDA worker on the rotate-fold build 8f481459, 60 s rows, the cleared helper sequence; an hour ahead of main's 12:30 clock): the same genesis seed, class v4 against class v5: unlocked v4 135.82 MH/s at 458.3 W (0.296 MH/W), v5 135.90 at 474.3 W (0.287); at 1,300 MHz v4 125.92 at 294.0 W (0.428), v5 125.93 at 299.8 W (0.420); at 1,200 MHz v4 115.69 at 273.3 W (0.423), v5 115.87 at 278.6 W (0.416); the Devnet 3 epoch-0 v5 pack (another seed, the fingerprint 82b19cbde8557ea5 matched on every row): unlocked 136.94 at 494.4 W, 1,300 134.10 at 315.6 W (0.425), 1,200 128.51 at 302.2 W (0.425). THE READING: at the knee class v5 loses 0.0 percent of rate against class v4 and costs 2.0 percent in watts (1.9 percent per hash), under main's 2 percent line, so the v4 knee stands, the tiers table says the class v5 rows are within it, and the UI lane's knee note stays off (knee_loss_pct 0 on the 5090); the A4000's 17 percent is a capped card's number: the 5090 at 1,200 MHz holds v5 level with v4 too, so the loss appears only where the power cap, not the clock, is the limit. Per tier for the founder: a 5090 or 5080 owner on a knee lock loses nothing at the class v5 crossing; a power-capped card (a datacentre card at its cap) loses up to 17 percent until its cap is raised or its class re-tuned. The 5080's rows after the v6 packs job if wanted; the AMD grid live on PC 1 since 11:25 (24 points, about 32 minutes). LANE B'S FIRST READING, RELAYED BY MAIN (11:2x BST), WHICH CHANGES THE CHIP MODEL AND LEADS THE 20:00 SYNTHESIS: a 2 GiB SRAM full store on one N2 die (about USD 500 of silicon, an N2 project of USD 100 M to 500 M) reads 13x to 17x the 5090 per joule at zero shadow and 2.7x to 4.8x with the shadow at the measured k band; layer 2 (the dataset tracking chain state) moves its capex, not its joules; the custom HBM4E base die (2027 to 2028) 6.5x to 14x, untouched by the four layers; PIM structurally blind to dependent random reads; and the M5 Max at 3.1x the 5090 per joule is the honest denominator. MAIN'S ORDERS: (1) chip-model-v3 gains the SRAM-store row and the HBM4E base-die row with lane B's figures and their claimed or measured marks; (2) the synthesis states the per-joule edge against the SRAM store honestly (3x to 5x with the shadow) and against the M5 Max, and prices the one layer that answers it: a dataset floor that grows on a schedule faster than SRAM cost falls, with the cost to a 12 GB and a 16 GB GPU and to 16 GB unified Apple memory stated; (3) the served chip line ("2.1x per joule at the knee") is reviewed at 20:00 with the measured basis for each clause; no served text changes before the synthesis, and if the SRAM-store reading stands the line becomes the honest range with the project cost and the clock beside it. THE SHIPPER'S THREE READINGS (11:2x BST): (1) override-60x.json: every reader in the tree is the fast-time harness, the sims and CI; no daemon on the fleet loads it; the app manifest's consensus.override is a separate 16-key object carried from the live manifest and untouched by the cut; the live chain's object is the digest's (1b37cb9d on e0644958); the harness's file only, the cut stands. (2) The cut tip cbbaa8c4 on release-0.3.25 (907fdaf4 plus the steward's whole-file commit; the crate and packaging trees byte-identical to 907fdaf4's, whose crate gate read 305 + 35 + 8 at 11:24; override-json-check passing): amd-clock-25 e2962b89, tiers-25 d3d0704a, the Intel header, the tiers class-flip pair 081b3ba7, install-detach-25 52a34111 with its test fix, the node-source pin e0644958, the host bc8d4f79, the fast-time file; the Mac DMG on it afa7f527 (45,766,741 B, the node pair 556926b1/d2dfe966), staging. (3) The knee note off on the 5090 rows. The pin at 13:00 on e0644958 and the 13:40 provisional minute standing; the matrix on cbbaa8c4 and e0644958 the steward's by 12:30. LANE B'S FIRST CUT ON MASTER (34f63b3c at 11:25 UK, four hours and thirty-five minutes ahead of its 16:00 clock): docs/analysis/class-v6/hardware-future.md with the three findings and the k bands (with the research lane, into the synthesis's section 7a on counter-asic-4 at ad37a50c); lane B's four decisions in its section 7 with defaults (the draw bounds by 20:00 via the synthesis; the dataset schedule unchanged; the M5 Max as the reference joule; the clock unchanged); nothing built or benchmarked, gh untouched; the full report by 09:00 adds detail only, no k band moving. LANE A'S FIRST CUT ON MASTER (docs/analysis/class-v6/history.md, 300 lines, merge 4c58ad65 at 11:26 UK, three and a half hours ahead of its 15:00 clock; the full gate GREEN 73 checks; primary documents read from the PDFs: the Least Authority and Bob Rao audits, Kik, EIP-1057, the RandomX design and v2, Tromp's README, the Fudan Equihash solver, Percival's lookup-gap note): 21 chip rows by mechanism (what each chip specialised, the miss, the timeline, the v6 layer, closed or not, the per-joule number), the in-depth sections (Ethash, ProgPoW, RandomX, Cuckoo, Equihash, Scrypt and Argon2, the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows), the four layers against the history layer by layer, the tier consequences. THE HONEST VERDICT WITH THE NUMBER: the chip that stores the dataset (class C: every Ethash chip, the E3 at 1.0x, the Linzhi at 2.1x, the Jasminer X4 at 5.1x via DRAM hybrid-bonded onto a 40 nm logic die, the E9 Pro at 4.1x) is NOT closed by any of the four layers, every per-era draw and family epoch being firmware to it; v6 inherits 5.1x per joule on GDDR7 at zero premium (3.6x at the 5090's knee, 2.1x with the class v4 shadow at k = 1), USD 2.8 against 14.7 per MH/s; classes A, B, D's governance half and E are closed, mostly since v2 and v3. THE THREE LESSONS THAT BIND: (1) the stored-dataset chip is firmware-immune to every draw; only joules and memory growth move it; (2) automatic change beats the human fork only where it costs the chip a redesign, and the one such parameter is the memory: layer 2 as declared is not an anti-chip rate (a 32 GB board lasts 60 years at 0.5 GiB a year; the 8 GB card is out at year 12; the E3 the only chip a growth rule ever killed, 20 to 27 months after shipping, at the fleet's own 4 GB limit), so its floor and a per-tier ceiling are the numbers to fix, not the rate; (3) a steered address pattern is always found after launch unless the test lives in the acceptance rule, and every drawn parameter changes layer 4's null, so the census re-derives per era (2.2 s per candidate). CORRECTIONS TO THE 5 OCTOBER FILE: the Antminer X9 withdrawn May 2026 with zero units (not "July 2026 delivery"); RandomX v2 released 25 March 2026 with activation pending (not "no fork"); CryptoNight's secret chips at about 33 months, not 43; Vorick's "survives forks at under 5x" and "13 months for a startup" on no fetched page, marked unverified. Two asks with defaults: layer 2's ceiling (if no word by 20:00 the full report drafts it as GB per tier per year keyed to card-lifetime-2026-10-05.md, with the flag that a dataset tracking state literally outgrows every card inside a decade if state grows as Ethereum's did); the hardware file cross-cited, not repeated. The lane's web-search budget spent (200 of 200); further additions by direct fetch. LANE D'S STATE (11:2x BST by the Mac's clock; its own line read "11:5x"): the first cut committed on class-v6-family-gate at 55c0dc6a with the full gate running; the census at 640 random eras, 298 lossy-cap, 327 width-4 on build-1 and about 500 shape-64 on build-3, the two build-4 corners queued behind a full pool; the landing on the gate's GREEN, the measured coverage table in the 17:00 cut. THE SNAPSHOT DIGEST STAMP (the node lane, 11:2x BST; a wip on release-0.3.25-node under its suites since 10:28Z): every snapshot a node writes carries its consensus digest as a new last field (the day-streams field's fallback shape, so 0.3.24 files decode with no stamp); a node with its digest set refuses a snapshot stamped under another digest ("re-executing from genesis") and one with no stamp ("written by a node before 0.3.25"), the follower starting at genesis; the daemon sets the digest from its params; the tests known-failed first (another digest refused, an unstamped file refused, nothing loaded; a matching stamp resumes, the written file carries the stamp, a digest-less process resumes as before, the wire round-trips); if the suites read green the full gate set runs and it is in the pin at 13:00 BST. THE CONSEQUENCE FOR THE MOVE: every Devnet 3 node restarted on 0.3.25 re-executes from genesis (no file written before 0.3.25 carries a stamp), so the restart takes the chain's re-execution time, which a fresh 0.3.25 node on build-1 since 10:24Z measures now (about 30,000 chain blocks; the rate in the pin line). TWO READINGS BESIDE THE CAUSE: (a) build-1's three nodes differ at 26247 (node1 0x3f53a7b9, the seed 0x717e7dc8, the observer 0x4548c319), and the seed and node1 differ at block 0 already (0x275b0cce against 0x7e37a9fb), which the ba75bf6f file alone does not explain (both resumed their own files across the same restart; the seed also restarted at 02:00Z on 2720d8d2 from a 0.3.22 file); the fresh node's genesis root and its first divergence from each decide whether a second class (an older-object file on the seed, or the resume itself) is in play; (b) the fleet asked for the roots at 26247 and 15611 on hub-1's Devnet 3 node, dn3-g1 and every prover by 12:30 BST with each node's resume line. The loud status for a vetoed node (a veto counter, the last veto's line on the explorer's status, "state not fresh") on the same line if the suites leave time, else 0.3.26, the node lane's word at 12:30. MAIN'S WORD ON LANE A'S ASK (11:2x BST): the default stands (the GB-per-tier-per-year table keyed to the card-lifetime file, with the flag), and one schedule to price beside it so the 20:00 reading carries a decision: a dataset floor of 6 GiB at the v6 epoch (every 8 GB card keeps mining with its cache; the 6 GB 2060 tier drops), 10 GiB two years on (the 8 GB tier drops), 14 GiB at four years (12 GB drops; 16 GB and Apple 16 GB unified hold), each step by height like a class epoch, the schedule itself a consensus field, with the cost per tier stated as the year each falls off and the share of today's measured cards that is; against the chips: the hybrid-bonded DRAM chip sized at launch (the E3 class) dies at the first step it cannot carry, the SRAM store pays capex only, both said. Lane A's corrections to the 5 October file go into the record and the served texts tonight. MAIN'S WORD ON THE STAMP AND THE GENESIS CLASS (11:3x BST): the stamp rides the pin; the re-execution time goes in the pin line and the move plan per tier; the fleet staggers the restarts in thirds so the proving share never reads zero, and the hourly line says "re-executing" with the count until the last prover is back. The second class is a GATE, not a note: the seed and node1 differing at block 0 means one of them runs a different execution genesis, and a hub node on a wrong genesis is worse than any snapshot drift; the pin is not named until the node lane says which file each of build-1's three nodes and hub-1 loaded at genesis, which root is the network's (the fleet's roots at 26247 and 15611 decide it), and the wrong one is corrected or re-walked; if that is not read by 13:00 the pin waits inside the 14:53 ceiling and the shipper slides by its authority. The vetoed-node status rides 0.3.25 if green, else 0.3.26. THE 60x FILE LANDED (the CI steward, 11:31 UK, ahead of 11:45): release-0.3.25 cbbaa8c4 (the whole 81-key file on 907fdaf4, the hook gate GREEN 60) and master e295c0d5 (the same file, the gate GREEN 73); known-failed to green on record: core RED on the one test on all four boxes before, core GREEN on the fixed pair on build-1, build-3 and build-4 after, build-2's re-run running; the full matrix by 12:30. A NEW GATE ON THE PIN (main, 11:3x BST, from the reference-apps lane's read): node1-dn3 and the re-executed observer diverge from chain block 26294 at DAA 60,578, the 10:05 move minute; node1 executed a block the selected chain later dropped and never unwound it, so its numbering runs one high and its state and records diverge; that is the drift class and the likely cause of last night's proving collapse after a move; the stamp does not cure it. The node lane's order: a known-failed reorg test under the exec follower, the fix on release-0.3.25-node if green by 13:30, else the move with the mitigation (every node re-executes from genesis after the minute, the vetoed-node status loud) and the fix as 0.3.26 tonight; plus the roots census to count stale nodes for the fleet's re-walk before the minute; the shipper's slide authority covers the pin inside 14:53; if the fix needs past 14:53, the floor re-cuts from the next minute by the same authority; the explorer lane reads block numbers from the observer node only (the chain the certificates follow) until the fix is live. THE FAMILY GATE'S 12:00 COVERAGE (lane D, 11:3x BST by the Mac's clock, ahead of its clock): 4,900 drawn eras through the per-era tests on three boxes (build-1 random 1,444 and lossy cap 663 at 10 core-seconds per era; build-3 shape 64 at 2,162; build-4's two lossy corners queued behind a full pool); the full gate on the first cut GREEN (73 checks, 381 s), the landing on one re-gate after a merge conflict on export-exclude.txt with the research lane's line (resolved, both kept). THE WORST ERA PER TEST: (1) THE EXHAUSTION BOUND BREAKS AT THE LOSSY CORNER: with or, mul and mulhi all at +4 points (30 of 75 lossy against the table's 18), r per candidate is 0.956 (the table's 0.681) and 8 of 663 eras EXHAUST the 256-attempt cap (mean attempt 18.6, max 252), so 1.2 percent of epochs at that corner would take the last-resort program, which adv-accept-3 showed fails rule (a) in 9 percent of seeds; B = 4 with the lossy ops free to rise is therefore outside the band; the random stratum at B = 4 (every weight drawn, lossy ones included) reads r = 0.718, max attempt 107 and 0 exhaustions in 1,444, but 107 attempts is 4x the shipped max of 28; the ring-A rule the cut carries: the sum or + mul + mulhi at most the table's 18 plus B, so r stays under 0.85 (r^256 under 1e-18); the default by 17:00: B = 4 on the injecting families only, the lossy families capped at their base. (2) THE ERA-STRIDE CLASS AT THE BIT LEVEL ON THOUSANDS OF ERAS: 52 to 58 percent of accepted programs in EVERY stratum carry one site whose address bit R (or R+1, R+2) is biased at over 6 sigma at 2^20, 33 to 40 percent at over 100 sigma, the worst z 1,024 at bit 7 of a site under R = 7 (a product's bit 0 at P = 1/4 landing at bit R): adv-cache-2's mechanism at half the family's epochs on programs (c''') passes (min ratios 0.9950 to 1.0000); the chip price per site about 1.6 percent of a hash's reads at f = 1/2 against the partial-store curve's 1.26x ops cost: the f = 1 verdict stands, the "uniform random reads" sentence does not; the catch structural (the index fold in load_index before the rotation, the class v6 design row), not a floor. (3) The largest-256-item-bucket excess: clean full-window sites +4.4 sigma; the worst eras +94 to +128 sigma at one site (the F8 tail's quarter-bit class at scale, the same mechanism: the bucket at the biased bit); the bound in sigma from the clean spread in the 17:00 cut. (4) The (c''') refuse rate per stratum: random 2.56 percent of candidates, shape 64 3.41, lossy 0.42 (the lossy rejections earlier at (a')); 0 accepted programs under 0.995 anywhere. (5) VOID and rerun: the width-4 stratum ran at width 1 (the era's one-entry allowed set redrawing to the base's width; fixed, the harness rebuilt, restarted at 11:5x with its own label space); the first corner strata sharing the random stratum's label space coincide with its draw a third of the time; the reruns use per-stratum labels; both stated in the cut. Coverage by 17:00 at about 1,000 eras per hour per 16 cores: random 10,000, shape 64 3,000, lossy cap 3,000, width 4 3,000 plus the two build-4 corners; the rule-of-three line for the random stratum at 10,000 eras a failing fraction under 3e-4 at 95 percent for every ring-B test. THE V6 COST ROWS (the hash lane, 11:4x BST by the Mac's clock, its own line reading "12:4x"; four hours ahead of 16:00): with the research lane at scratch v4/ca4-v6-cost-rows.md, every row labelled measured or modelled; the layer-2 headlines: VRAM 3.2, 5.4 and 9.9 GiB at the floor, 2x and 4x; a 12 GB card falls off at about 9.5 GiB (year 15), a 16 GB GPU at 13.5 GiB (year 23), a 16 GB unified Mac at 8 GiB (year 12), the 5090 at 29 GiB (year 54); the DRAM-read cost per hash size-independent (the 5090's 1.11 microjoules of 2.29), so the layer moves capex not joules, and the card rows allow a floor of 4 GiB in year 1 and 8 GiB by year 4 without retiring a 12 GB card (main's schedule of 6, 10 and 14 GiB at the epoch, two and four years sits above that: the 12 GB tier drops at 14 GiB, the 16 GB holds); the measured size rows (the v3 pack at 2, 4 and 8 GiB on the 5090, unlocked and at 1,300) ride the v6 packs job after the AMD grid. The AMD grid: the first run refused in 2 s at no_tune_line (the old installed exe, as designed); the rebuilt exe on PC 1 by the update-return lane's fetch at 11:33, the rerun from amd-clock-25 572c3ee0 live since 11:39 (about 32 minutes, the rows about 12:15). The class key on the mirror (ember-tiers-25 0a838072 in tiers-class-25 081b3ba7, with the shipper since 11:13, inside the 12:30 reading). The Arc read waits on the shipper's PC 2 take; the 12:30 default "no Arc read" stands unless it starts before. THE DRIFT CLASS READ FROM THE LOG (the node lane, 11:4x BST): at 09:42:09Z node1-dn3 accepted 0x6aa6 (DAA 60,578) and at 09:42:10Z 0xb708 (the same DAA and blue score 60,265, both children of 0x0fed at 26293: a tie at one height); its follower executed 0x6aa6 as chain block 26294 (28 transactions) and 1.1 s later 0xb708 as 26295 (the same 28 skipped as already included), with no reorg line between; every consensus view now (the seed, node1 itself, the observer) has 0xb708 as the chain block with the selected parent 0x0fed and 0x6aa6 off the chain, so node1's records hold an orphan at 26294 and number everything after it one high, and its state root diverged from there (the observer, re-executed from genesis, agrees with node1 to 26293). THE GAP: the 0.3.22 continuity rules (ledger N15) check the first appended block's selected parent against the tip at append time and scan the whole record set against the DAG's selected parents ONCE per state generation (a restart or a loaded snapshot); a break landing after that scan, as this one did ten minutes after node1's restart, is never looked for again until the next restart; the fleet's +2 on four shared-devnet boxes is the same gap. THE FIX on release-0.3.25-node (a wip under the exec suite since 10:41Z): the self-check runs every 30 s over the ring (the last 2,000 records) against the DAG's selected parents and in full on a generation change, a break handing the records above it to the reorg unwind (the existing branch restoring the ring state at the fork and re-walking); the test known-failed first on node1's exact shape; on the same commit the snapshot digest stamp (exec 51 of 51 green on its wip) and the vetoed-node status (vetoes counted on the status with the last veto's line, stateFresh false while any stands, on igneum_getNodeInfo and the status RPC); the exec suite's green about 11:46 BST, then the named commit, the full gate set, both canaries (the digest 1b37cb9d unchanged: nothing consensus) and the fast-time pair, the gated tip by about 12:30, inside 13:30. What the fix does not do: name why the tie-break flipped under node1 at 09:42Z (its DAG now reads 0xb708's parent as 0x0fed and the path at the time must have read otherwise; the second "PoW accepted 0xb708" line 0.4 s after the append says the block was processed twice), a reading for the record after the pin. The fresh 0.3.24-object node on build-1 past IBD and executing from genesis; its root at 26247, its rate and its memory peak in the pin line. MAIN'S WORD AT 11:4x BST: (1) lane D's band default stands (B = 4 on the injecting families only, or, mul and mulhi at base, the ring-A lossy-sum rule), and the index fold before the rotation with the bias test as its guard is layer 1's rule; (2) the served sentence "uniform random reads" is corrected today, not at the review: the audit lane rewrites it to the measured statement (reads spread over the whole dataset; a bit-level bias at one site appears in about half of epochs; it prices about 1.6 percent of reads to a chip storing half the dataset and nothing to a full store; the next class folds it out), through the gate and the master-only deploy, with the ledger row; (3) layer 2's table splits Apple by memory size (16 GB unified at its 8 GiB limit, 32 GB and 64 GB Macs holding every step), the M5 Max being the honest best per joule and the Mac tier a large audience; the schedule decision at 20:00 is the founder's with that column in front of him. THE EXPLORER'S SOURCE (the explorer lane, 11:4x BST): it reads one endpoint and always has, the Devnet 3 observer node on build-1 (the execution RPC on loopback 26850 through tools/observer/explorer-indexer.mjs, the observer's own dn3_ tables on 28650); it has never read node1-dn3, so there was no switch; the indexer on 26850 since 10:04 UTC with a full refill from genesis at 10:33 UTC after the root equality read at block 26,247; the pages now name the observer node as the one source, the chain the certificates follow (on explorer-dn3, in the gate; the merge and deploy follow). THE GENESIS GATE'S ANSWER ON build-1 (the shipper, 11:43 BST): the seed was the odd node (its block 0 from the 0.3.22 binary; the rule change for the node lane's record), re-walked from genesis at 11:35:30 by the shipper's hand (the evm moved aside, the same binary and flags, the kept datadir) and reading population A's roots at 11:43:00 (0x47983bd9 at 15611, 0x3f53a7b9 at 26247, head 26,478). THE MEASURED RE-EXECUTION: 26,478 chain blocks in 7 minutes 30 seconds (about 59 a second over the walk; 100 at the start, 30 past 15,000), RSS 5.5 GB; so the move plan's per-tier line: a prover's node is back about 8 to 10 minutes after its restart on 0.3.25 (30,000 blocks at the minute), a Mac or HiveOS app node the same at its update hour, miners unaffected; with the hub and the seed at the minute and the provers in two thirds at +0 and +25, the proving share never reads zero and the last prover is back about 35 minutes after the minute. The node lane's gated tip (the ring check, the stamp and the vetoed-node status in one commit, the digest 1b37cb9d unchanged) by 12:30; the pin after it and the fleet's census; the minute about 14:10 at the earliest if the fix rides, inside 14:53. LANE A'S SCHEDULE SECTION (history.md 4.2a, master 59963461 at 11:45 UK, five hours ahead of its 17:00 clock; three landings today: 4c58ad65, b645762d with the synthesis lane's six items folded in, 59963461): ONE FLAG on main's schedule with the number: under the standing budget rule (the working set under 6 GB on an 8 GB card, the 75 percent reading) a 6 GiB floor does not fit the 8 GB tier (6,398 to 6,744 MiB, 78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent); 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2 (not the 8 GB tier alone); 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above. The schedule that drops the tiers in the order main named, priced beside it: 5.5 GiB at the v6 epoch (6 GB falls, 3 percent of the 32 measured consumer cards), 8 GiB at two years (8 GB falls, 22 percent, with the 10 GB RTX 3080 and Apple 16 GB; 12 GB holds at 69 to 72 percent), 11 GiB at four years (12 GB falls, 22 percent; 16 GB holds at 70 to 73 percent); 24 GB and above hold throughout. Against the chips: the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 of GDDR7 on a USD 470 part); the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. So the schedule is a fleet-retirement rule with a USD 0 to 160 chip tax, killing only a chip whose maker ignores the field. The default by 20:00: the full report carries both schedules and recommends 5.5 GiB as the floor that keeps the 8 GB tier inside the rule. Owed: the fleet's hashrate-weighted card census (the shares are by count of the bench table's 32 measured consumer cards). LANE A'S CORRECTIONS SERVED (the site audit lane, master 2119e4f3 at 11:46 BST, gate green on 78166c6c, commit 14ad1a33; seven hours ahead of 19:00): every served "no chip shipped" and "seven years without a shipped chip" sentence (the litepaper's precedents row, the chip-model paragraph, the vs RandomX lead and its track-record row, the limits section; /claims and /randomx following) now carries the Antminer X5 (September 2023, 1.46x per joule over a desktop CPU, silicon believed mining privately from about 2021) and RandomX v2 released 25 March 2026 with its mainnet activation pending; the ledger rows X34 and C2 corrected with lane A's file cited, the pins moved, the public ledger and page regenerated; the X9 sentence already matched lane A's row (sales opened 26 December 2025, shipping scheduled July 2026, withdrawn mid-May with zero units), the precedents and track-record cells now reading "withdrawn in May 2026 with zero units"; the 43-month, 13-month and Vorick figures on no served page; the commit also carrying main's governance line beside the class v5 sentence and six class v4 watts rows; the "random reads" correction with its AP-F8 row next by 13:30; the build-server lane deploys on main's word. LANE C'S FIRST CUT ON MASTER (docs/analysis/class-v6/invention.md at a9f03598, 11:48 BST by the Mac's clock, five hours ahead of 17:00, with the census script under tools/attack/v6-invention/ and its two TSVs): build-1 ran the per-load acceptance census (11 forms x 256 seeds, twice: no era and drawn eras, 80 s each on 48 leased cores) and the verifier benches; the two packs exported and with the hash lane for PC 1; the second candidate (warp-uniform block selection) has no pack form without a generator change, which the no-code rule holds this week, so its row stays modelled. A CORRECTION TO THE CA4 FILE'S VERDICT, FOUND BY LANE C: the counter-asic-4 crate's per-load acceptance (BiasedIndexBit) counts the era window's fixed top index bits 26 and 27 as biased, so under any drawn era it refuses every per-load program (0 of 256 on every form today, 5,536 of 7,862 bias rejections naming those two bits); 20.2a-close's "1.4 percent accepted, 42 of 64 seeds exhaust" (the per-load class's death at 00:0x) was read across drawn eras and so measured the instrument on most rows; on the no-era census the sound form (16 x 256 x 1) reads 0.927 rejection per candidate and 234 of 256 seeds accepted, the iterated 16 x 27 form 0.989 and stays dead; the one-line instrument fix (skip bits at or above 28 minus the site's k_off) is a research-crate change, made today as a research-only change behind the pack by the coordinator's order, and the sound per-load form's verdict is REOPENED as a measured candidate (its energy and rate rows on the 5090 through the hash lane; chip-model-v3 5.11's note on the per-load closure to be re-worded when the re-read lands). THE REOPENING APPLIED (the research lane, 11:5x BST): the reopened wording in counter-asic-4-research.md (20.2a-close and rank 4), class-v6-rotating-family.md (section 7c as layer 5) and chip-model-v3.md 5.11's note, with one precision: the 22:5x UTC census ran the bare class with no era, so its 0.986 is the iterated form's own no-era figure (lane C's 0.989 agrees the 16 x 27 form is dead); the artefact in any drawn-era read before the fix; the fix already on counter-asic-4 as of 10:5x UTC (BiasedIndexBit judging only the bits inside each site's window mask through verify::window, per site), uncommitted until the suite's line lands (the box-2 slot since 10:31Z), so lane C re-reads on that branch once pushed, not making the change twice; the chip-model 5.12 rows (the SRAM store, the base die, PIM's blindness, the M5 Max denominator) in the same tree, riding the same commit before 15:00. A MIRROR NOTE (11:52 BST): lane B read silent 25 minutes by the mirror; its first cut landed at 11:25 and its next clock is the full report by 09:00 tomorrow, so the silence is its finished state, not a fault; the mirror now skips lanes whose clocks are done. A MASTER-ONLY DEPLOY AT 11:53 BST (the build-server lane, on main's own builder-programme landing d86ea00a: /build, /grants, /faucet, /swap asserted; the served sha a9f03598, master's tip; the checks ok; 38 miners rows): it carried the audit lane's 2119e4f3 (the RandomX history correction with the Antminer X5 and RandomX v2, the governance line, the first six class v4 watts rows), which main ordered served tonight and the audit lane cleared for the next scheduled deploy; the "random reads" sentences not yet corrected as served; the coordinator's trigger stands for the 13:30 correction. LANE C'S KNOWN-FAILED TEST FOR THE INSTRUMENT (11:5x BST): igneum-pow/tests/v6_window_bits.rs, the sound form (16 x 256 x 1) accepting on at least 4 of 8 seeds under drawn eras 0 to 7 with 0 window-bit refusals (0 of 8 before the fix), the no-era bit-0 refusal on seed 3 standing; 2 passed, 0 failed on build-1 against a local overlay of the same nine lines, the overlay reverted, the test file an offer to the research lane's suite; the re-read on the research lane's commit by 15:00; meanwhile build-1 runs the lane's uniformity read at 2^20 nonces on 64 seeds for the two sound per-load forms and the class v4 shape (the F8-form top-0.1-percent item share against a uniform control, the per-site distinct ratio) on a harness over the crate's trace_load_indices (the master F8 tool mirroring class v4's execution order), about 20 minutes on 24 leased cores. THE RANDOM-READS CORRECTION ON MASTER (the site audit lane, bf54b08d at 11:54 BST, gate green on db038279; an hour and a half ahead of 13:30): the litepaper's lead reads "dependent reads spread over a multi-gigabyte dataset that changes daily", the table row "the dependent reads are", the "chain of random reads into a table too big for a chip to carry" sentence standing with the measured clause after it (the 0.995 floor on every accepted program over 4,900 drawn eras; about half of epochs with one load site biased at the era's stride rotation bit; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold before the rotation in the next class); evidence row 18 with lane D's family-gate.md and adv-cache-2's section 2.3 as sources; the ledger row AP-F8-7 (AP-F8-6 taken on class-v5): "Open, priced: 1.6 percent at f = 1/2, nothing at f = 1; the served sentence corrected 8 October 2026", the disposition class v6 layer 1's fold with the bias test as guard; the public ledger and page regenerated; no pinned sentence touched; the fud-ledger's quoted history standing; the build-server lane deploys bf54b08d. BUILD-1 AT 11:55 BST (the coordinator's own read): load 107.6 on 96 cores; the lease table: the family gate 32 cores (the random stratum, 10,000 seeds), 16 (the lossy cap, 3,000), 16 (width 4, 3,000, restarted), lane C's uniformity read 24 of 48; 88 of 96 cores held, none waiting, no pre-emptions in the last ten minutes. THE 11:55 BST LOAD LINE (the build-server lane, all four boxes at the minute): build-1 (96 threads) load 113.7, the pool holding 32 for the family gate's random stratum plus 16 and 16 for its corners and 24 for lane C's uniformity read (88 of 96 held), the release and v5 builds outside the pool; build-2 (96) load 81.3, the pool holding 32 for the attack-pass F8 census (the thirds); build-3 (32) load 25.1, the pool holding 16 for the family gate's lossy-base stratum and 2 for the hash lane's x16 rows; build-4 (96) load 89.0, the pool holding 4 x 8 for the attack-pass F9 chunks 0 to 3 plus F1's 40 and F4 done; no release-class waiter on any box; the builders loaded, none idle. The founder's order at 11:2x is met at the minute: every box above 80 percent of its threads bar build-3 at 78 percent of 32, which the two queued build-4 corners and the next v6 pack take. The build-server lane's deploy of bf54b08d served at 11:56 BST, two minutes after the landing: the post-deploy checks ok (api/live igneum-devnet-3, the index strings, the legal line, 38 miners rows, the four builder pages 200), and the litepaper's lead sentence read back from the served page carries the corrected wording (wide parallel integer maths, warp shuffles, dependent reads spread over a multi-gigabyte dataset that changes daily, the program waiting on memory latency); the old "random reads over a multi-gigabyte" is absent. The CI steward's 0.3.25 pre-pin matrix with the shipper at 11:59 BST, 31 minutes inside its 12:30 clock: seven suites on four boxes, every cell green but the one known core red on the pair before the fast-time file (the same single test on all four boxes, the six missing keys), and core green on the fixed tree on build-1, build-3 and build-4 (170 passed each); build-2's re-run queued behind three lanes' suites and lands on its own; counts identical across boxes (pow 113, app 346, exec 49, miner 29, p2p-flows 38, consensus 134); the Mac's full gate on the 9b93e649 tree GREEN, 60 checks; build-3 and build-4 toolchains read as build-1. The matrix worktree sits at cbbaa8c4 (81 keys, igneum-pow identical to the pin's tree); the second matrix waits on the node lane's gated tip (by 12:30), the line by 13:15. The RX 9070 XT's first measured grid on the AMD knob (job run-ca3-pc1-amd-grid-9070-20261008-b on PC 1, 11:40 to 12:10 BST, 24 of 24 rows ok, the card reset to factory at the end): the rate flat at 18.93 to 18.98 MH/s on every point, the knob moving watts only; stock 3,292 MHz 195.8 W (0.097 MH/W); the clock offset alone to 2,924 MHz 159.2 W at -400 (0.119), clamping about 2,920 at -500; the power limit alone does nothing until -30 (184.4 W); best -500 MHz with -30 percent: 2,921 MHz, 149.3 W, 18.96 MH/s, 0.127 MH/W, a 24 percent saving at the same rate. Per tier: a 16 GB AMD home card gains a quarter of its electricity cost at no rate loss once 0.3.25's knob ships; it stays 3.5x behind the 5090's 0.43 MH/W at the lock, so last night's AMD reading stands (the read path, not the clock, is AMD's cost). The v6 packs job live on the 5090 since 12:11 BST (eleven packs including the three dataset sizes, unlocked and at 1,300, about 40 minutes). The Arc re-read not started on PC 2 (the shipper's take holds the box); at 12:30 the default "no Arc read" stands, the pairing 1c420786. The Ember priors committed on ember-tiers-25 at 1e966170 with known-failed tests, its suite queued behind build-2's slots since 11:46; the sha to the UI lane and the shipper on its green; if not run by 12:45 the suite moves to build-1 through a lease. Two master-only deploys from the builder stream, checks ok (38 miners rows, the six asserted pages 200): 0c64b24f at 12:07 BST, the explorer landing (explorer.igneum.network, /proving, /tx/, the dn3_ APIs reading "Devnet 3"; the explorer indexer unit moved to the master checkout and restarted, reading the observer only as main set), and 3355c098 at 12:16 BST (site/vercel.json only: the explorer host's root 307 to /explorer, read live). No chip text changed in either. Still in the stream: the reference-apps lane's /light, /receipt and /oracle (its gate since 11:50, the 13:00 default) and the audit lane's watts rows 11 and 12. A third master-only deploy from the builder stream: f0418c8d at 12:19 BST (main's word via the explorer lane: EXPLORER_EVM_RPC on the production env, so /api/explorer balances read live from rpc.devnet.igneum.network; checks ok, 38 miners rows, six pages); the public RPC's allow list tightened the same minute to igneum_get* (the two igneum_submit* writes refused), reported to main. No chip text changed. The /build lane DONE with every clock beaten: landed on master as d86ea00a (11:47 BST), deployed as a9f03598 at 11:53; /build, /grants, /faucet (the Devnet 3 faucet page) and /swap serving in the nav's Build group; faucet.igneum.network/api/faucet live on build-1 behind Caddy, funded 2,000 IGN by the fleet lane (11:01 BST), the first drip 11:17 BST, 1,989.99 IGN left; the walkthrough PASS through the public RPC and faucet (a contract deployed at block 27055, 24 s end to end, Foundry 1.8.5, docs/build/first-contract.md); the RPC list read from the node in docs/build/rpc.md; the audit's four wording lines in. One open fact to the fleet lane: build-1's Devnet 3 seed at 27810 re-executing from genesis while the faucet reads the observer's 26850 (the re-execution class measured at 7 min 30 s this morning). Lane D's coverage at 12:2x BST, every launched stratum complete (the runs beat the 1,000-per-hour estimate once the pools freed): random 10,000 eras (0 exhausted), lossy cap 3,000 (37 at the 256 cap, 1.2 percent), width 4 at the fixed harness 3,000 (0), width 4 plus lossy cap 2,000 (24, 1.2 percent), shape 64 3,000 (0), the lossy-base band (B = 4 on the injecting families, or/mul/mulhi never raised) 3,000 (0); 24,000 drawn eras through the per-era ring-B tests on build-1 and build-3; build-4's shape-64-lossy and shape-256 strata still queued behind the attack pass's F9 chunks and not needed for the cut. The exhaustion finding confirmed at scale: 61 of 5,000 eras at the lossy corner reach the last resort against 0 of 19,000 everywhere else, so the band rule (lossy families capped at their base) stands on measured rows. The 17:00 clock holds; the cut (coverage table, per-axis table, union-bound arithmetic, harness patch series) likely lands by 14:30 BST. The node lane's gated tip missed its 12:30 clock: the combined wip (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the reorg-unwind fix on the same commit) sat in build-2's queue from 11:41 BST at normal priority behind a Counter ASIC 4 suite holding a slot since 11:31, found at 12:21 and moved to build-1 at gate priority; the exec suite about 12:25, the named commit on green, the full gate set (build and consensus at gate priority, five suites, both canaries, digest 1b37cb9d unchanged) about 12:50, the fast-time pair about 13:05, inside the 13:30 clock. The coordinator's default revised and taken by the lane and the steward: the second matrix starts on the named commit the minute its sha exists; no sha by 12:50 and the matrix runs on e0644958, the stamp and vetoed status slide to 0.3.26. The pin reads about 13:15 to 13:30 rather than 13:00; the minute about 14:10 holds if the fix rides; reported to main at 12:29. The seed's re-walk read equal to population A at 11:43 BST (0x47983bd9 at 15611, 0x3f53a7b9 at 26247; 26,478 blocks in 7 min 30 s, about 59 a second, RSS 5.49 GB); the fresh node on build-1 executing from genesis since 11:42:34 at about 100 a second at the start, its roots to follow. The lesson for the record: a release gate is dispatched at gate priority or it waits behind research suites; the node lane's wips were not. Main's correction at 12:3x BST on the fleet default: the 10:12 FETCHED count is not a census of state. If the stamp rides the pin, every node re-executes from genesis at the minute and the census is not a gate; if the stamp slides to 0.3.26, the census (block 26294's hash and the 26247 root on every prover) is a gate and the stale nodes re-walk before the minute. The fleet lane silent since 11:31: a one-shot at 12:36 starts a fresh fleet-move lane from the fleet root to take the census, the re-walks, the stagger and the pullers if it has not answered by then; the old lane keeps the hold and the hourly line. The 9070 XT reading goes to the audit lane for its row. Build-2's queued cell landed at 12:24 BST: core GREEN on the fixed tree (177 passed), so the first 0.3.25 matrix is green on every suite on all four boxes. The steward's gate-priority stream for the second matrix written (every suite at gate priority, its own results file), waiting on the node lane's sha with the 12:50 fallback armed; the line by 13:15. The AMD knob closed for the cut before 12:30: the 9070 XT grid's rows in and the efficient point in EFFICIENT_W as 149 W (both floors: clock offset -500 at about 2,920 MHz where ADLX clamps, power limit -30; 149.3 W at 18.96 MH/s, 0.127 MH/W, 24 percent under stock at the same rate); the rate flat over the whole ladder, so the knob is a watts lever only and the knee rule reaches the floor; amd-clock-25's gated tip 1be99aa0 (full gate GREEN 60, suite 298 green) with the shipper as the cut tip, the release section reading measured. The 5090 comparison carries two denominators, both real: 0.43 MH/W at the v4 1,200 MHz lock (133.8 MH/s at 305 W), 0.58 to 0.60 at the 1,300 knee (134.6 at 223 W); the 9070 XT at its floors is 3.5x behind the first and about a fifth of the second; a served row names its point. The Arc default taken at 12:30 BST: no B580 re-read reached the v5 lane, so the pairing line went to the shipper as the FREEZE 1c420786 (0.3.24's, as published) with the kit zip 65b47211 (packs-ca3-v5-20261008T085619Z.zip; its packs, ids and 82b19cbde8557ea5 byte-identical to 1c420786's by the packs test on both trees) and the Intel worker held out; 8f481459 (gate 73 GREEN, suite green, the Intel fix in) stands behind it and becomes the pairing with the Intel kit the minute an equal Arc read lands, with the page's Intel row moved. Nothing else of the v5 lane's in the cut. The shipper at 12:33 BST: (1) the 0.3.25 app tip is 89e83df2 (cbbaa8c4 plus amd-clock-25's gated tip 1be99aa0: the 9070 XT's efficient point 149 W at 18.96 MH/s in the ceiling table, the grid playbook; crate gate GREEN 12:28, 305+35+8, inside the 12:30 app window); the second matrix uses it with the node lane's sha. (2) On the node lane's hint, build-1's Devnet 3 seed and node1-dn3 were found dead since 12:06 and 11:54 BST (logs ending mid-line, no panic, no OOM; the observer and the fresh node lived): the network's seed was down 24 minutes; both restarted at 12:30 on their kept datadirs (the seed resumed its clean re-walk snapshot, node1-dn3 re-walking from genesis). Two reads before the pin: the build-server lane by 12:50 on whether any build-1 run kills igneumd by name (a cleanup that does so reaches the seed at the minute); the node lane by 13:00 on whether the line can die silently under the finality route flood the seed's log shows (a million drops on one peer). (3) The pairing the freeze 1c420786, kit 65b47211, the Intel kit out (PC 2 dark, no Arc read today); the genesis class closed on the fresh node's roots; the pin after the node lane's gate set, the matrix and the census; the minute inside 14:53. The hash lane at 12:4x BST: (1) the Ember search priors on the mirror as ember-tiers-25 1e966170, app suite green (307 + 35 + 8), with the UI lane and the shipper; the cut default stated to the shipper (in by the 13:00 pin or 0.3.26). (2) The v6 packs job on the 5090 (since 12:13): the four packs made on the box or pinned ran PASS unlocked (mx8-genesis 137.65 MH/s at 312.2 W; mx8_sh256x27 137.62 at 464.6; the invention lane's mx8_shl4096x1 135.99 at 428.6; mx8_shl2304x3 135.85 at 483.6; the 1,300 rows follow); the seven exported on the Mac this morning (today's x8 and x16, the two re-weighted, the three dataset sizes) were refused by the worker's seed check in 0 s ("IGNEUM_SEEDW_INIT is not attempt 0 of the epoch seed"): the string-seed export form derives different seed words from the byte-seed form the pinned packs use; re-exported in the byte form (the x8 reproduces the pinned id 73bcbfe8 and seed words exactly; the three sizes too; the x16 pair and the two re-weighted packs on generator 2 differing only in the era, the multiplier or the weight table); kit b and one more PC 1 job of those seven follow the running job's close, about 13:00 to 13:45, rows to the research lane, the invention lane and the coordinator. The invention lane's reading so far: the sound per-load form at class v4's instruction count (shl2304x3, 55,296 shadow ops) costs 483.6 W against sh256x27's 464.6 W unlocked, 19 W more, not under; the one-pass form (shl4096x1, 32,768 ops) 428.6 W; the lock rows decide the per-load candidate's GPU side. The export-form lesson for the record: packs for the worker are exported in the byte-seed form, never the string-seed form. Main's load order at 12:5x BST: lane D's two remaining strata (shape-64-lossy, shape-256) move from build-4's queue (behind the attack pass's pool) to build-3, idle after lane D's strata; build-3 kept fed with lane C's packs and the family census's next corners; nothing new on build-1 (load 142) until the pin is named, its gates at gate priority. Sent to lanes D and C with the 13:05 default. The node lane's two readings at 12:4x BST on the combined tip: (1) the build-1 deaths were the OOM killer (the build-server lane read the kernel ring: the seed at 44.6 GB anon-rss at 12:06:07 BST, node1 the same class at 11:54, two 31 GB attack binaries beside them); what grows is the proof pool's in-memory proof map: since the late-join rule (0.3.17) every proof a node receives is held by hash in memory and never removed (the entries leave the 600-block record window and the on-disk archive drops below the pruning point, the map did not); about 1.2 MB a proof, 14,107 proofs on the observer after a day (17 GB on disk, 13.6 GB RSS), the seed at 128 inpeers took the relays fastest; older than 7bd2940f; the fix (a proof leaves the map and the verdict cache with its record at the window's end unless another live entry names it; carried proofs served from the archive; known-failed test) on the tip under its exec suite at gate priority since 12:35:55. (2) The ring check's known-failed test on node1's shape green (exec 53 of 53 at 12:34:53 before the pruning went in). The named commit (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the proof-map window, over 7bd2940f's re-announce and keygen and the ceiling switch) follows the exec line about 12:40, inside the 12:50 fallback; the full gate set at gate priority on both boxes, both canaries (digest 1b37cb9d unchanged) and the fast-time pair after it. The fleet's census (12:31 BST): 36 nodes on population A, the network's genesis root 0x7e37a9fb; 21 stale nodes, each with a genesis root of its own, re-walking from 12:35 in thirds; dn3-g1 died a third time at 11:55:47 (the same OOM class on a rented box the likely reading; the fleet's hourly RSS per node with a restart above 32 GB is the guard until every node is on the tip). Lane D on main's order, done 12:36 BST: build-4's two entries cancelled before running; build-3 carries four strata on the fg6 harness (42f2c77f), 8 cores each under class measure: shape256 (3,000) and w4lossybase (3,000) running, shape64lossy (2,000) and w4shape64 (3,000) queued behind them on the 24-core pool; the lossy band at B = 4 across the injecting families is the complete lossy-base stratum (3,000 eras, 0 exhausted, r = 0.595). Build-1's queued attack-f8 rebuild chain cancelled (the point-B live census moves to build-3); what remains there started before the order (four lossy-share strata at +1 to +4 points, 16 cores each, about 900 of 3,000 eras; the point-A live census at 2^24 on 32 cores). The 17:00 cut committed at 2a595e1b with the 24,000-era coverage, its gate re-running. A shared-Mac fault class found at 12:3x to 12:4x BST: the class-v5 lane's shell command ran pkill -f "tools/ci/pre-push.sh" before its own gate, which killed every lane's gate on the Mac: the record's merge gate three times, the invention lane's landing twice (d6955381), the family gate's once (exit 144). The kill-by-name class the 6 October rule bans in scripts (kill-by-name-check.sh), applied by hand on a command line. The word to the lane: kill only your own gate by its pid; gates on the Mac do not share a lock. Reported to main. The research lane's commit 0ab27582 on counter-asic-4 (the mirror, 12:4x BST, ahead of the 15:00 clock; the crate suite green on the committed tree, 116 passed, 0 failed, build-2 12:38, master's new derivation test among them). It carries: (1) chip-model-v3.md section 5.12, the two chips with lane B's figures and marks (the 2 GiB SRAM store on one N2 reticle: 17x at zero shadow, 8x to 30x on the read band, 2.7x at k = 1 and 4.8x at k = 0.5 with the class v4 shadow, 3.7x and 2.0x at the card's whole shadow, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M and 18 to 24 months, a break-even cap of about USD 330 M to 1.7 B on the mission lane's model; layer 2 moving its capex, two dies at 4 GiB 15x and four at 8 GiB 13x; the custom HBM4E base die 6.5x to 14x untouched by the four layers; PIM structurally blind, 1.6 percent of reads in-bank at 2 GiB; the M5 Max at 0.78 microjoules the honest denominator, 3.1x the 5090) and 5.11's per-load note in the reopened wording; (2) the merge of master (the sub-version 3 line, the derivation recorder, the re-exported packs) and the per-load bias test's fix (judging only the bits inside each site's window mask; lane C re-reads on this id); (3) the class v6 document through section 9: the lead on the SRAM store, the per-tier schedule table with lane A's checked steps (6 GiB does not fit the 8 GB tier under the 75 percent rule; 5.5 / 8 / 11 GiB drops the tiers in the named order, about a quarter of today's measured consumer cards per step), the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB, the one card that pays rate for a larger working set), lane D's rings and band, the index fold as a layer-1 rule, the 5070 Ti pair, the x16 mixer at 11.4 ms loaded by the right method (admissible false on the measurement), lanes B, A and C taken in 7a to 7c, and section 9's served-line review with the wording proposed for the 20:00 word. Owed for 20:00: the 5090 size rows (the hash lane's v6 job), lane C's 15:00 re-read, lane D's 17:00 table, the two re-weighted packs' rows; each lands as a row with its label, or its default. Main's word at 12:5x BST on the kill class: the rule "no kill by name on the Mac, pid file only, ad-hoc shell lines included" lands in the agents' standing text with this record landing; the steward makes it a gate check that refuses pattern kills in scripts and logs the sender of every TERM a gate receives. The class-v5 lane's own line: the four pkill lines (12:3x to 12:37) stopped its own superseded gate runs as its tip moved under them; nothing of its uses a name or pattern kill again, its background gate started with its pid recorded and ended by that pid only; its current run (gate 17 on class-v5 79799452, 12:39) runs to its end. The census and the four-item pin taken by main; the clock as the shipper set it. Lane D's interim at 12:5x BST for the 09:00 report, the lossy-share curve at 1,000 to 1,300 eras per point: r rises 0.80, 0.88, 0.92, 0.96 as or, mul and mulhi go +1 to +4 points each; exhaustion appears at +3 (2 of 1,029) and reaches 1.4 percent at +4 (14 of 994); every exhausted era's class v5 last-resort scan passes at its first or second candidate (k = 256 or 257), so the band's edge is between +2 and +3 points of lossy weight and the scan does its job at the corner. Its cut 2a595e1b under the gate, then the mirror landing and the send to the research lane. The attack pass's F8 to 256 seeds landed at 12:37 BST: seeds p66 to p257 (192 new) at 2^24 on the freeze 1c420786 (binary 0f5c98dc, pairing e5a4ac5978462156), the window-model control, build-2 under class measure, validation 0 mismatches (hash_warp agreement on 37,440 warps). 184 of 192 within 1.2x at the top 0.1 percent (mean 1.023); 8 over (p110 1.3527x, p66 1.3403x, p234 1.3156x, p145 1.2750x, p77 1.2664x, p225 1.2457x, p248 1.2188x, p89 1.2065x), each with its hottest item at 263 to 432 reads of 2^31 and the hot-set verdict clear on the windowed control (largest excess X_f/f +0.60). Over all 256: 245 within (95.7 percent), 11 over; the rate at 256 (4.3 percent) is the gate's at 64 (4.7 percent) and the worst fell (1.3527x against p10's 1.5047x). The 6-sigma largest-bucket line flags 57 of 192 (p110 +61.67 sigma): the AP-F8-1 tail mechanism at its rate. Two seeds carry a predicted source, one-one-bit through a load, both passed by (c''') on the frozen tip: p212 (1.1915x, attempt 4, site instr 7, r5, last writer load at 2) and p225 (1.2457x, attempt 0, site instr 37, r5, last writer load at 36), to the hash lane for by-site attribution as the gate's tail was. Verdict PASS at the gate's reading: no card or chip gains a cacheable hot set on any of 256 epochs. The row and f8-uniform.md section (e) on the mirror's attack-pass. Still running: build-4's F9 (six chunks) and F1 (10^6), partials at 17:00. The node lane's named commit inside the 12:50 clock: 42ce0f07 on release-0.3.25-node, both mirrors, 12:39:37 BST, the sha with the steward and the shipper. Content: e0644958 (keygen, the record re-announce, the ceiling switch at 82,800; digest 1b37cb9d) plus four node fixes, nothing consensus: the ring self-check every 30 s over the last 2,000 records with the full scan on a generation change (node1's class, its known-failed test green); the snapshot digest stamp (a snapshot under another object or none refused, the node re-executing from genesis); the vetoed-node status (the count and the last veto on the status RPC and igneum_getNodeInfo, "stateFresh" false while any stands); the proof map's window (a proof leaves memory with its record at the 600-block window's end, the OOM class). Green before the squash on the same tree: exec 54 of 54, the kaspad check. The full gate set at gate priority on both boxes from 12:39:44 (every line by about 12:52), both canaries reading the Devnet 3 digest back at 1b37cb9d, the fast-time pair by about 13:00; the crossing watch at 68,400 on the seed from 12:50; the pin line after the last of those; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. The invention lane at 12:5x BST: the hash lane's 5090 rows for the two sound per-load packs reverse the GPU-side sign of rank 1: at class v4's own instruction count the per-load form costs the card 19 W MORE than the whole block unlocked (483.6 against 464.6 W) and 6.6 W more at the 1,300 lock, rate 1.3 percent under, 15 to 20 percent more per shadow instruction (19.7 to 20.8 pJ against 17.2); the dead 16 x 27 export's 13 to 14 W saving does not carry (a 16-instruction loop against a 144- or 256-instruction straight segment). Rank 1 keeps its place by the file's own rule (the chip's project cost about 2x against the card's 2 to 4 percent of watts) with the honest sign: the card pays, not saves. The second cut landed at 4315e992, the third (these rows) under the gate. The drawn-era re-read on 0ab27582 built on build-3 but starved (build-3's 16-core pool under lane D's three 24-core leases since 12:38): the coordinator moved it to build-4 at once through the lease pool under class measure (build-1 closed until the pin is named); the 15:00 numbers from build-4, the box named in the row. The class v5 lane's full gate on class-v5 79799452 (the tip on both mirrors) GREEN, 73 checks in 463 s at 12:47 BST, left to run to its end: 0.3.25's pairing row on the page (the freeze 1c420786, kit 65b47211 with the Intel worker held, the Arc read to 0.3.26 with the second PC dark), master merged through its latest (the 60x file taken whole from master after the merge reordered seven keys and duplicated three, values equal), the generated ledger files matching. Nothing of the lane's pending; the one future item the Arc B580 re-read on kit 65b47211 when the second PC is back, which moves the Intel row and sends the 0.3.26 upgrade line. 42ce0f07 reads every gate green at 12:48:10 BST: build 12:42 rc=0 (igneumd 8e17a60b, /srv/artefacts/0325-42ce0f07/node-lane), pow 19, consensus 134, core 177, miner 29, p2p-flows 38, exec 54, all at gate priority; the Devnet 3 canary set with digest 1b37cb9d unchanged, byte 6, the override refused, the 0.3.24 pin refused on the digest both ways; the testnet canary b2e856ed unchanged. The shipper has the line; the steward's matrix runs on it. Two inputs before the pin: the fast-time SUMMARY on 42ce0f07's artefact (about 13:00) and the 68,400 crossing on build-1's seed (the chain passes it about 12:54, the watch from 12:50). The reorg-unwind fix's 13:30 clock met at 12:48 on the same commit. The attack pass at 12:5x BST, the ends brought in: F1's 10^6 was one 40-thread census on build-4 (35 h); the harness now takes --start (attack-v5-frozen ebdb7d4a, smoke-tested: a 20-program census from index 5 writes rows 5 to 24), so the census is split by index range: build-4 keeps indices 0 to 349,999 (its running census, stopped by pid when its progress line reads 350,000; the flushed census.csv holds the lower range) and build-2 runs 350,000 to 999,999 at 80 threads under class measure (binary 42ee04c7, held since 12:48:40 BST after waiting 362 s for the pool to free on its own, no pre-emption). Both halves end about 23:30 BST. F9's six chunks hold on build-4 (48 cores); when build-2's F1 ends tonight the F9 remainder re-splits onto build-2 by seed range (rows keyed by seed, nothing lost), bringing F9's end from about 17:00 BST tomorrow to about 06:00 BST. Cores held: build-2 80 (F1 upper range), build-4 88 (F9 48, F1 40); build-1 and build-3 untouched. Partials at 17:00. RED, a first, at 12:48 BST: Devnet 3 STALLED AT THE CLASS V5 FLOOR. The seed's virtual DAA read 68,403 at 12:49:11, 12:50:23 and 12:51:09 with one sink (07055360), the last block accepted at DAA 68,399 as class v4 at 12:48:14; nothing at 68,400 or above reached the seed, node1 or the observer, no node logged a PoW rejection: no miner found an epoch-19 block on a chain that ran one a second. The nodes held epoch 19's state (the seed installed the streams for epochs 18 and 19 from its snapshot at 12:30). The cause (the fleet lane, 12:52): every miner's --worker is the hive package's igneum-worker-cuda, which runs generators 2, 3 and 4 only; the class v5 kit's worker (82b19cbde8557ea5, the one every v5 gate ran on) was never on any miner's worker path, only its packs were placed; the prepare of epoch 19 fails and the miner sits at 0 MH/s while the templates flow. The fast-time harness crossed this boundary green four times on pairs, which tests the node and the CPU engine, not the fleet's GPU workers or kits. The fleet places the kit worker on every box now; the 0.3.25 hive package and Windows payload rebuild with the kit's workers by 13:30 (the build-server lane); the Mac Metal worker's generator-5 read with the v5 lane by 13:10. The pin and the minute wait on the chain moving and the rebuilt packages; the 42ce0f07 gate set green, the matrix running, the ceiling cut's publish limit (DAA 75,600) standing still while the chain does. GATE RULE for the next cut (the record's and release-rules'): a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; the packs' presence and the kit's own tests never stand for it. The 0.3.24 move's read-back ("36 of 36 FETCHED on the pin") was a node reading; no reading of a worker preparing class v5 existed before the floor. The research lane at 12:5x BST: section 10 ("the floor") open in the class v6 document (counter-asic-4 after 91117093) with each floor lane's term, what the document holds measured for it, the default at 19:30 and the row owed; two measured rows the floor lanes start from rather than re-derive: the SM-sparse lane from 20.3b (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw, 460 against 451 W; 99.8 percent of class v3 at 4 W less; watts minus idle per MH/s never below base; the sparse shapes collapsing at the 1,300 lock; its new work the breakdown of the 99 W an idle SM does not save and whether an occupancy shape at full SM count moves it; the worker variants sp-w and the card-free --list-race check on counter-asic-4); the k lane from 15.1a (the GPU side measured per counted op: ARX 11.3 / 6.2 pJ, mul 13.9 / 8.3, mulhi 39.6 / 21.0, prmt 22.3 / 11.5, lop3 24.1 / 13.0, shfl 55.8 / 29.4, fp32 FMA 9.2 / 5.2, the int8 tile 1.4 to 4.1 per MAC; only the chip side claimed; the mix that maximises k priced against the GPU's own per-family cost, the shuffle 4.9x the add on the card). The thirty-ninth landing on master at 12:54 BST (26a3cbe6): the standing rule in CLAUDE.md. The node lane at 12:5x BST on the stall: the worker's refusal line is "program pack generator 5 is not a generator version this worker runs (2, 3 or 4)", faulting at 0 MH/s from the first epoch-19 template; the kit's class v5 worker was benched on 24 cards this morning and never placed on any miner's --worker path; the nodes read 0 PoW rejections and hand the right template (the CPU id-read from build-1 confirms epoch 19 as class v5). The fleet places the kit worker and its pack on every mining box, w-target first; the chain moves when the first card prepares. The record's lesson: a worker that cannot run the next class must refuse at the pack prepare, loudly, hours before the boundary (the plug, tune, play rule), and no hive tar ships without the class the object names. A second bug read off the stall: the pool admits at the next block's DAA (chain id 4464 past the floor) while eth_chainId answered the executed tip's id (4463 with the tip stalled at 68,399); the fix (eth_chainId and net_version answer the id a transaction sent now must carry, the status carrying both ids, the known-failed test on the stall's shape) a wip under its exec suite at gate priority since 12:54:27, landing as the SECOND commit on release-0.3.25-node over 42ce0f07 (nothing consensus, digest 1b37cb9d unchanged), its full gate set and fast-time pair by about 13:15; that commit the pin's node sha, 42ce0f07 if it reads red. THE CROSSING READS CLEAN. The first class v5 block (epoch 19, epoch seed a75c5624) was accepted on build-1's seed at 12:57:40 BST, 9 minutes 26 seconds after the last class v4 block, the minute the fleet's first kit worker prepared; then 13, 14, 71, 165 and 78 blocks a minute (the backlog clearing, the rate settling), DAA 68,547 at 13:01:37; seven stale-pack attempts refused between 12:59:24 and 13:01:10 (the harness's known-failed shape), none since; no state-wait, catch-up, stale-dataset or digest line on the seed, node1 or the observer; no honest block refused. Devnet 3 runs class v5 at byte 6 as the 0.3.24 object names (the v5 signal share 1,407 bps at the floor; the seed's template at 13:1x: epoch 19, class 5, version 1538, era the genesis, day 20,734; the executor serving epoch 19's stream, 869 records, root 0x1fd55139...4561). The pairing check holds three ways: the kit's igneum-pow (8f481459's tree, the freeze's hash object) names attempt 2, program id 3d375a55029e7e60 for epoch 19; the node lane's 0.3.24 pin miner (igneum-pow 1c420786) read the same id live at 12:56; the DMG's Metal worker on the Mac prepared epoch 19 against the live seed with the same id (869 leaves, 26 MH/s). The stall's two causes, both miner-side, neither in the object: every fleet miner's worker was the hive package's CUDA worker (generators 2, 3 and 4; it refuses a generator-5 pack with a line, the miner at 0 MH/s retrying, loud in the log and the plug-tune-play fault only on the dashboard), the DMG's Metal worker from the freeze's tree the same (the v5 worker path is the v5-kits lane's 5c9ed959, in class-v5 from e208dfea on; the freeze is the hash object, not the hosts); and a miner not told its node's exec RPC port cannot prepare class v5 at all, so every fleet loop needs --exec-rpc. The fix: the kit's workers (zip 65b47211) and --exec-rpc on every box; the hive, Windows and Mac packages from the kit tree (the hive and Windows payload carrying d84b1b6c / be23bc68 and e1bfd582 / 55722527 on the worker path; the Mac side closed on release-0.3.25 44d1815a, proto-metal from class-v5 79799452). The stall's cost: 9.5 minutes of blocks and every prover's share for that span. The standing rules from it (release rules 16 and 17 on ship-docs-0321 cb570365): the kit worker and --exec-rpc on every miner loop before any class boundary; a worker that cannot run the object's next class refuses at the pack prepare, hours ahead; a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; memory against the container's cap. All of it on the class v5 page's section 0 at class-v5 2494f3f8 (both mirrors 12:59, master merged, its full gate running by pid). The second node commit 5f316c21 on release-0.3.25-node (both mirrors 12:56:22 BST) = 42ce0f07 plus the chain-id answer (eth_chainId and net_version return the id the pool admits at, the next block's DAA, 4464 past the floor; the status carrying both ids; the known-failed test on the stall's shape), nothing consensus, digest 1b37cb9d unchanged; EVERY GATE GREEN at 13:04:05 BST (build 12:58 rc=0, igneumd 3812b2a2, /srv/artefacts/0325-5f316c21/node-lane; consensus 134, exec 54, core 177, pow 19, p2p-flows 38, miner 29, all at gate priority; the Devnet 3 canary with digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged). 5f316c21 IS THE PIN'S NODE SHA. The one input before the pin line: the fast-time SUMMARY on 42ce0f07's artefact (the run waited 796 s for build-1's pool, 88 of 88 leased at or above v5, nothing to pre-empt; running since 12:55:54, v5 from epoch 8 at 13:04:19, the line about 13:10), a run on 5f316c21 after it. The shipper's close: the app tip 9a71e784 (crate 89e83df2), the DMG 43cd8c94 staged, the tarball 1ae1810d, move id m5f31-1; the pin about 13:25 after the SUMMARY, the matrix and the hive; the minute about 14:00 to 14:20 inside 14:53. The TESTNET_PARAMS v5-at-0 re-cut's default moved under the rule by the node lane: it lands through its full gate set on release-0.3.24-node 30 minutes after the seed reads the first ten class v5 blocks accepted clean, so at 13:32 BST unless main says otherwise before then; a red crossing would have meant no re-cut. The audit lane's 9070 XT row on master at f37f497b (12:55 BST, gate green on 33b0ad06), ahead of 13:30: 18.96 MH/s, watts "149.3 with the 0.3.25 knob (195.8 stock)", 0.127 MH per watt, the tuned text with the 24 points' flatness and the date, the source the status row with the job id; the note carries the grid's stock point beside the app's 202 W reading of 7 October, the two single-lever points, and names both 5090 denominators (3.5x behind at the class v4 1,200 MHz lock, 0.43; about a fifth at the 1,300 knee, 0.60); the qualifier drops when the cut serves. With f37f497b: the complete class v4 watts rerun (22 rows), the /income calculator, the /economics page, the governance line, the two served-text corrections with their ledger rows. The build-server lane has it to deploy. The hash lane's kit b on the 5090 (12:49 to 12:58 BST, all PASS; with the research lane and the floor lane): the mixer multiplier x8 against x16 costs the GPU nothing (137.73 against 137.72 MH/s, 320.2 against 320.1 W unlocked; 127.44 against 127.46, 212.0 against 211.7 W at 1,300), so the verifier's 1.86x per doubling is the whole cost of that draw; the shuffle-heavy table on the base program moves 7 W unlocked and nothing at the lock (a 2 percent term); the pinned class v3 program at 2, 4 and 8 GiB costs a tuned 5090 5, 11 and 14 percent of rate at the 1,300 lock (4, 8 and 10 percent per hash) and 3 to 4 percent unlocked, which corrects the layer 2 line: the size term is real at the knee (the page-walk cost the latency-bound regime exposes). Kit c (the multiply-heavy table) running; kit d (both tables inside the shadow block, the row layer 1 needs) exports on build-2 and runs after, about 13:45. W = 8 for the floor lane: the crate's width set is three fixed word widths (1, 4, 16; WIDTH_WORDS, the mix arrays, the emitters for CUDA, OpenCL and Metal, the verifier's fold), so a 32-byte load needs a generator and emitter change before any pack exists (two to three hours of crate work on the readwidth line plus the PC 1 row); the ask to main with its default: say so by 14:00 and the lane starts it on the readwidth branch (a research class, no consensus object); silence means W = 4 pins and the floor lane hears so at 17:30. The F8-256 attribution runs for p212 and p225 on build-3 (the attack-pass crate d08e1e0f built there at 13:01), rows by 16:00. Main's ids for the floor lanes, for the record: SM-sparse af65f8187569666d0, shadow k a3c9601a6d4686fe1, SRAM and dataset floor acecab7195ea66621, honest denominator a4d39e20a0762646d, invention a734c5330f17be3c2; the research lane delivered the two starting rows to each with their 19:30 defaults. Two more master-only deploys from the builder stream, checks ok (38 miners rows, 18 asserted pages, the checkpoint API and the explorer stats API): d28cf8fc at 12:50 BST (the explorer wording c4ca746f, the audit lane's ace5c294 with /economics, the /income calculator and the class v4 watts rows, the DEX lane's 9126e4d6 and 825d19bd) and f37f497b at 13:04 BST (the reference-apps b7f1e0d7 with /oracle's BLS-verified root, the 9070 XT knob row on /miners). No chip text changed beyond the audit lane's own landings. The fortieth landing on master at 13:14 BST (90b180f2). Main's word on W = 8 at 13:1x: start it, research class with no consensus object; the order on the hash lane: the 0.3.25 lock rows and kit b first, then the readwidth generator and emitter, the PC 1 row by 17:30; a miss means W = 4 pins, the floor lane told, the W = 8 row later as a v6 sub-version check. The 13:32 testnet re-cut on its default. A RED THE MOVE ITSELF WOULD TRIGGER, read on build-1 at 13:05 BST by the node lane: a node re-executing from genesis (the fleet's 21 re-walks now; every node at the move under the snapshot stamp rule) has its executor thousands of blocks below the chain, so its pool admits at the executor's next DAA, names the old chain id 4463 below the floor, refuses every relayed transaction signed with 4464 as a state-free fault and disconnects the relayer as misbehaving ("wrong chain id: expected 4463, got Some(4464)" on the seed and node1 from peers at 13:05); for the length of its walk, about 8 minutes, it drops every peer that relays a transaction, and at the move every node would do it to every other: a partition. The fix, a wip under its exec suite at gate priority since 13:08:06: the admission height is the larger of the executor's next DAA and the chain's virtual DAA plus one (eth_chainId, net_version, eth_sendRawTransaction and the relay read it), and a mismatch between the network's own two ids is a refusal, never a strike; the known-failed test is the re-walk's shape. It lands as the line's third commit over 5f316c21 (nothing consensus, digest 1b37cb9d), the full gate set and the fast-time pair on it by about 13:35; the pin waits on it. The second thing in those logs is the stale class, not a bug: the 21 nodes with a divergent execution state compute a divergent class v5 dataset, refuse every honest v5 block as invalid PoW and ban build-1's seed for an hour ("Reject(BlockInvalid)" on the fleet's side), cured by their re-walks in progress; a node that cannot check a v5 header for want of the epoch's state holds off, as designed. The crossing is clean on the honest side; the chain runs. The fast-time crossing on the 0.3.25 pair 42ce0f07 (12:55:54 to 13:08:50 BST) read green on every claim (rung 1 at 13:02:22, v5 at byte 6 from epoch 8 at 13:04:19, 12 of 12 ids equal to the CPU verifier's, the stale node refused, the restart step resynced in 19.1 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); its SUMMARY read FAIL on one harness check: the final epoch's row held one miner's line when the run ended at that epoch's boundary (the id equal to the CLI's); not a node finding; the check now reads the final row by its id (v5-fasttime 130562a2); the clean rerun on the same artefact from 13:1x, SUMMARY about 14 minutes after its lease. Lane D's 17:00 cut LANDED on master at 238100b0 (13:13 BST), gate GREEN (73 checks, 355 s) on 2a595e1b, four hours early; the research lane has the layer-4 line; docs/analysis/class-v6/family-gate.md carries the measured coverage (24,000 drawn eras, per stratum and per axis, the bound arithmetic), the rows, logs, scripts and the harness diff under docs/analysis/class-v6/logs/. Build-3: w4lossybase done (3,000, 0 exhausted), shape256 1,910 of 3,000, shape64lossy 1,895 of 2,000, w4shape64 queued, then the point-B live census on the family attack-f8 build (74784428); build-1 the four lossy-share strata near done and the point-A live census. The class v5 lane's full gate on class-v5 2494f3f8 (the crossing row, master merged) GREEN, 73 checks in 407 s at 13:06, run to its end by pid, nothing killed. The third node commit inside the shipper's 13:20 clock: d5b68fae on release-0.3.25-node, both mirrors, 13:14:12 BST = 5f316c21 plus the admission fix (a transaction admitted at the larger of the executor's next DAA and the chain's virtual DAA plus one on the relay, eth_chainId, net_version, eth_sendRawTransaction and the status; a mismatch between the network's own two chain ids a refusal, never a strike; the known-failed test on the re-walk's shape), nothing consensus, digest 1b37cb9d unchanged, pairing 1c420786; exec 54 of 54 and the kaspad check green on the same tree before the squash. The full gate set at gate priority from 13:14:19, every line by about 13:26; the fast-time pair asked on it; the 42ce0f07 rerun's SUMMARY (about 13:24) the gate's record on the same object. The pin's node sha d5b68fae if green, else 5f316c21. The steward's 0.3.25 matrix at 13:17 BST: node 5f316c21 with app tree 89e83df2 GREEN on all seven suites on build-2, build-3 and build-4 (no RED); 42ce0f07 complete green on the same three; build-1 out; at 13:21 the third sha d5b68fae core and exec GREEN on the three boxes, six of six: the pre-pin suite read closed. d5b68fae reads every gate green at 13:22:43 BST (build 13:15 rc=0, igneumd b0e7b8b5, /srv/artefacts/0325-d5b68fae/node-lane; p2p-flows 38, pow 19, consensus 134, exec 54, core 177, miner 29 at gate priority; the Devnet 3 canary digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged): THE PIN'S NODE SHA IS d5b68fae. The fast-time SUMMARY PASS (cross-0325-42ce0f07-2) at 13:22:57 BST on the 0.3.25 pair 42ce0f07 (13:10:07 to 13:22:57 on build-1 under class v5: rung 1 at 13:16:33, v5 at byte 6 from epoch 8 at 13:18:43, the stale node refused, the restart step resynced in 11 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); the d5b68fae pair running side by side since 13:16:13 on its own cores and port base, SUMMARY about 13:30, the last input before the pin line. The reading behind the fleet's partition line at 13:17 BST (hub-1 at one sink, dn2-1 alone on its own branch, w-poison a third, dn3-g2 and dn3-q03 stuck at DAA 68,403 refusing every v5 block): epoch 19's class v5 dataset derives from the execution state after the epoch's reference block, the last chain block below the cut 19 x 3,600 - 600 = DAA 67,800: chain block 28,462, hash a75c5624 (the epoch seed), state root 0x1fd551393d (build-1's seed, node1-dn3 and the fresh node agree; the kit's stream names the same root). Any divergence of state OR numbering between 26,294 and 28,462 puts a node in a cluster that refuses the other clusters' proof of work and bans their relayers for an hour; root-equal at 26,247 was not the gate. The census now reads hash and root at 28,462 on every box (epoch 20's height moves to the last block at DAA at most 71,399); every cluster but the one on a75c5624 / 0x1fd55139 re-walks; build-1's observer node, the explorer's only source, is one of the drifted (its 28,462 another hash at DAA 67,787: the orphan-append class during its 11:22 re-walk, so the explorer's numbers are off by a few; the shipper has it). The cure is the move itself: every node restarted on the pin's binary re-executes from genesis under the snapshot stamp with the ring self-check running and lands on the one state; the gate on the minute is the fleet's census at 28,462 after the re-walks (31 boxes on the one state at 13:19:44, the rest the numbering class the move cures), with an unban of every held address per box once its root reads equal, since bans persist on disk across restarts; a box whose root there differs after a re-walk on the pin's binary is a new class and a stop. Lane D's measured correction at 13:2x BST for the full report: the lossy-corner exhaustion is a shape-256 interaction, not corner-wide: at the lossy cap the per-candidate rejection is 0.877 at shape 64 x 108 (0 of 2,000 and 0 of 1,000 eras exhaust), 0.923 at 128 x 54 (1 of 1,010), 0.980 at 256 x 27 (36 of 990, 3.6 percent; 24 of 670 at width 4); at r = 0.98 the independent-attempt figure is 0.98^256 = 0.6 percent, so the per-era correlation is about 6x, not the 1,000x the mixed-shape average suggested; the band rule stands either way (lossy families never raised), and the cheapest shape for the draw is also the fastest on the cards. The hash lane's attribution: run 2 (the attack-pass branch's own crate) reproduces p225's 1.2452x but not p212's (1.57x against the gate's 1.19x, a different draw, the crate differing from 1c420786); run 3 on the 1c420786 crate is the authoritative one, running. The W = 8 pow suite on build-2; the three state-term packs (w4, w32, w64 on +sh256x27+state, the node1 state file, --era-widths 4/8/16) export on its green; the read-width kit (those three, the v5-genesis pack, the two 5 October packs, which are string-seed class v2 packs the worker accepted on 5 October, no re-export) runs on PC 1 after kit d; the L2::64B hint variant is not in the worker exes, so it is lane 5's kernel line, nothing to build. STANDING RULE from the founder relayed by main at 13:2x BST, applied to every lane the coordinator runs and every default clock: work as fast as possible; anything doable in 30 minutes to 2 hours gets a clock inside that window, never a target hours out; fan work out (one pod per point, one box per variant) rather than queue it. The floor close is 15:45 BST. The coordinator's re-read of the 16:00, 16:30, 17:00 and 19:30 lines: the F8 attribution rows 14:00 (run 3 running, three minutes a census); lane C's drawn-era numbers 14:00 (an 80-s census on build-4) and its cut 15:00; the class v6 per-tier cost rows and layer 4's tests 14:30 (kit d about 13:45); the W = 8 PC 1 row 15:30 (the crate work fanned: the suite on build-2, the exports on build-2's slot, PC 1 the moment kit d closes); the floor lanes' rows 15:30 for the 15:45 close; the synthesis and the served-line review table 16:30; lane D's full report 16:30 with every stratum fanned across build-2's and build-4's free cores rather than queued on build-3; the DEX lane's swap UI 15:00 and the Sepolia verifier 16:00; the reference apps already served (b7f1e0d7 at 13:04). Main's word at 13:2x BST to every lane: while GitHub is suspended, landings go to the box mirror's master through the gate, never to Forgejo master, which is a rewritten copy replaced at cut-over by the box mirror's final tip; pushing a branch to Forgejo for safekeeping is fine, landing there is not. Relayed to every lane with the pulled clocks. The SRAM and dataset floor lane's row is complete at 13:18 BST, two hours inside its pulled 15:30 clock: the full row at 7bc9de4b and the clock references at 8e9588de on the box mirror's branch class-v6-floor-sram (safekeeping, no master landing), gate green on every push, all arithmetic on build-3; docs/analysis/class-v6/floor/sram-and-floor.md. What the 15:45 close carries: the capex wall on the corrected project floor (no chip project below about USD 23 M a year of miner revenue, IGN 0.03, USD 62 K a day; every DRAM-board project at a third of the network above about USD 340 M a year, IGN 0.44, USD 0.93 M a day, where the SRAM project also starts); the read width as the only wire lever on the SRAM die (66x at the hash's 4-byte width at zero shadow, 44x at W = 4, 31x at W = 8, 19x at W = 16 if the 5090 passes the PC 1 job, 36x at the measured w64 row); the shadowed die at 6x to 10x at the honest cards' whole latency shadow on the k lane's synthesised core, kept beside the k lane's sequencer-core row as the floor-k worst case, never under 2x by any shadow; the floor as a ticket lever (5.5 / 8.5 / 11.5 GiB = 3, 5, 6 reticles, USD 1,500 / 2,500 / 3,000; USD 5,000 per store is 20 GiB and retires every card under 32 GB; the 5090 pays 4 / 8 / 10 percent per hash at its knee and the M5 Max 12 / 20 / 22 percent of rate at 2 / 4 / 8 GiB, both measured); the four other candidates (per-era and per-block re-fill, straddling atoms, a second hot table) dead with numbers. Amendments after the close, each labelled with its time: the W = 8 or W = 16 PC 1 row (the hash lane), the k lane's shuffle row and its re-fold, the Apple rate curve past 8 GiB. The DEX lane closed with every clock met before the pull, all on the box mirror's master through the gate: the AMM live on Devnet 3 at 12:0x BST; the swap UI serving at igneum.network/swap since 11:36 with the Igneum Wallet bridge live from the 12:50 deploy; the Sepolia certificate verifier live at 13:3x (0xAf74f3F512081291D663Bb1d6b6d37E99e37D744, suite 10 of 10 on build-3, Devnet 3 checkpoint 2127 recorded final and one Devnet 3 balance proven on it); the one named gap: no on-chain link from checkpoint to state root yet (docs/bridge/light-client-bridge.md); final master 825d19bd. The forty-first landing on master at 13:35 BST (937cc82ae); during its branch push the hook "died of signal 15" once more (the merge's own gate ran green and landed), so a kill by name on the Mac still reached a gate at 13:3x: the steward's TERM-sender log is the read. STOP ON THE PIN d5b68fae at 13:29 BST, the fast-time pair: SUMMARY FAIL (cross-0325-d5b68fae), the failing check v5_ids_equal_the_cli_v5_id, a node finding: on epoch 9's attempt-3 seed ec0a8cf9 the d5b68fae miner and nodes drew program id 65b57e3b847d362e (its nodes accepting 4 of 4 on it) while the freeze CLI 1c420786 and the ab6f980b CLI both draw ebf64b32e2d84c5b, state or no state; the three other v5 epochs agree with the CLI. A node on the freeze's igneum-pow would refuse that epoch's blocks: a split on the first divergent seed, a chain split class. The 42ce0f07 and 39f127a1 PASSes met no such seed, so they do not clear it. The cause from the box's build log: the d5b68fae, 42ce0f07 and 5b673577 pairs were built "pairs_with": "igneum 05b21835 (detached) with uncommitted igneum-pow changes", not against the freeze 1c420786 (39f127a1 and c8f9b383 were, against ca3-v4-node commits 4c24903e and 0e4ec18a); every 0.3.25 node binary embeds "igneum-pow-v5/src", not the freeze's crate; rule 7's pairing broken in the node lane's build path. The orders: the node lane folds the freeze pairing (a clean rebuild from the freeze's exact igneum-pow, the build row's pairs_with read before any lease) and the ceiling re-cut to 90,000 into one commit (sha by 14:05, the gates and a new digest by 14:20, the SUMMARY with the seed in the set by 14:35); the build-server and fleet lanes read the live 0.3.24 miners' pairing path by 14:00 (if the live network carries the same divergence, the move is its cure before the first attempt-3 seed; 5b673577 is the live pin); the artefacts rebuild on the new sha; the pin about 14:35, the minute about 14:55 to 15:10 BST. The coordinator's order to the v5 lane: the pairing read-back on the rebuilt pair by 14:30 (the freeze CLI against the new sha's miner on ec0a8cf9 and the three other v5 epochs, id for id, and the live miner's path the same way). The record's rule for the pairing gate: the fast-time set carries an attempt-3 seed on every run (the epoch seeds of a run are its block hashes, so the divergent seed cannot be forced; the pairing row is the check that reads first); a pair's build row names its igneum-pow commit, and "uncommitted changes" in pairs_with is a refusal before any lease. Lane D's fan-out at 13:4x BST, one stratum per lease, class measure (every box's pool read 0 free at submission, each waiting in the measure class ahead of adv work): build-2 w1band (width 1 under the band, 3,000 eras, the fg7 harness with the refused-ratio column) at 16 cores, and the mixer verifier rows mx4m4g, mx4m8g, mx4m16g with the 256 x 27 shadow, one core each (the x16 row); build-4 w4shape64 (3,000) at 16 cores; build-3 the point-B live census (64 seeds at 2^24, shape 64 x 108 with a band era's weights) at 24 of 64 seeds PASS, and w4band (width 4 under the band, fg7) at 8 cores, 179 of 3,000; shape256 (3,000) and shape64lossy (2,000) COMPLETE; build-1 untouched (the point-A live census at 31 of 64 PASS, no test fired; the four lossy-share strata complete at 3,000 each); build-3's queued copies killed and their partial rows marked PARTIAL. The full report by 16:30 on the mirror's master through the gate; what has not finished by 16:00 goes in as a partial with its count. The corrected line for main: at the lossy cap r = 0.877 at shape 64 x 108 (0 of 3,000 across the strata), 0.923 at 128 x 54 (1 of 2,000), 0.980 at 256 x 27 (3.3 to 3.6 percent of eras in three strata). The hash lane's clocks at 13:4x BST: p225 reproduces on the 1c420786 crate (1.2452x against the gate's 1.2457x, by-site rows in hand, the close by 14:00); p212 does not: the tool at d08e1e0f over the 1c420786 crate draws a program at 1.5715x with a hot set ("site instr 5, r7, one-one-bit, last writer add at 4"), not the gate's 1.1915x attempt-4 program, because the gate ran a chain path (class v5 with the dn3 state) the pushed tool has no flag for; the attack-pass lane's exact command asked by 13:50, default: p212 reported as unreproduced on the pushed tool, labelled so. Kit d: the first two exports hung on a build-2 slot (a stale lock of the lane's own run, cleared); take 3 direct and bounded, packs about 13:45; PC 1 held by floor lane 1's two jobs, so kit d's job starts the minute the card frees and closes 8 minutes later (rows by 14:00 only if PC 1 frees by 13:50, else PC 1's free minute plus 10, inside 15:30; past 15:30 the microbench arithmetic stands). The per-tier cost rows and layer 4's tests delivered at 12:0x (scratch v4/ca4-v6-cost-rows.md), the kit b and c numbers folded in at 14:15. W = 8: the suite on build-2 (restarted 13:23 after a slot wait); the three state-term exports follow it on the same box; the PC 1 read-width job after kit d; the 15:30 row holds if the suite is green by 14:00 and PC 1 frees by 14:30, else W = 4 pins. The explorer lane's correction at 13:4x BST: the explorer's source is no longer the drifted observer: the build-server lane re-pointed the indexer unit, the observer and the public RPC at node1-dn3 (EVM 26870) at 13:25, and the three indexer tables were wiped and refilled from node1-dn3 from chain block 0 at 13:27 (about 3 min); balances, receipts and accounts are node1-dn3's, the DAG tables the observer process's reading of node1-dn3 since 13:25. The notice landing by 14:00: the header names node1-dn3 as the source since 13:25 BST, the observer drifted at DAA 67,787 and re-executes from genesis, a block list read before 13:27 may differ by a few blocks until the move; the same line on /block and /tx. eth_chainId on node1-dn3 answers 4464 since the floor, so the explorer's chain id is read from the node; every page printing 4463 as a fixed string (/build, /swap, /metamask, the nav's title) is one off, told to the build-server lane at 13:28. The attack pass's split under the fan-out rule, running from 13:30 BST, every lease class measure: F9 (900,000 seeds left on 1c420786) as twelve chunks: build-4 keeps the lower 85,000 of each of its six 150,000-seed ranges, restarted from each chunk's lowest missing seed (rows keyed by seed, a merge dedupes), six leases of 8 cores; build-2 takes the upper 65,000 of each range, six leases of 6 cores. F1 (10^6 class v5 programs): build-4 keeps indices 0 to 349,999 at 40 threads (at 76,000 at 13:19; stopped by pid at the 350,000 line), build-2 393,662 to 999,999 at 52 threads (its first 47,000 rows from 350,000 kept, merged by idx at the end). Cores held at 13:36: build-4 72 (F1 40, four F9 chunks of 8; two chunks waiting on lane D's 16-core w4shape64 lease there), build-2 24 (four F9 chunks of 6; F1's 52 and two chunks waiting): build-2 contested (lane D's w1band 16, the invention lane's per-load acceptance census on 0ab27582 48, the hash lane's attribution at class adv, the hash lane's igneum-pow suite at class release for 88 cores, which pre-empts every measure lease there when it starts; the class order decides). Ends at the measured rates if every lease holds: F9 build-4 halves about 04:45 BST, build-2 halves about 07:00; F1 build-4 range about 23:20, build-2 range about 05:40; the build-2 ends slip by their waits. The 15:30 reading carries the counts and re-stated ends. THE EXPOSURE READ at 13:50 BST (the node lane's fingerprints, the shipper's correction): THE LIVE NETWORK IS ON THE FREEZE. The igneum-pow tree each binary linked is the untracked igneum-pow-v5 copy beside its release worktree (the .cargo/config.toml paths override); every copy fingerprinted against git archive 1c420786 igneum-pow by two methods (the node lane's: find src -name '*.rs' | sort | xargs sha256sum | sha256sum; the build-server lane's: find . -name '*.rs' | sort | xargs cat | sha256sum | cut -c1-12): the freeze reads cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 and 29106189ca1e; the 0.3.24 line's worktree (vendor/igneum-node-0321, where 5b673577 and every 0.3.24 pin was built, the gate pair a3b1a2c9/cfa9f5ca, build-1's seed, node1 and the observer) reads the same on the Mac and both boxes; the fleet's shipped pairs the same (29106189ca1e); the kit workers on the freeze (the freeze CLI built at exactly 1c420786 on build-1, binary sha256 7ba781db, names Devnet 3's epoch 19 as attempt 2, program id 3d375a55029e7e60, equal to the 0.3.24 miner's live read). So no live node or worker diverges, no attempt-3 seed can part them, epochs 20, 21 and 22 are safe, no hub-side holding action; the shipper's 13:45 line to main withdrawn and corrected. What diverged: the 0.3.25 line's worktree (vendor/igneum-node-v5) carried a pre-freeze copy (fingerprint e01ea128fab1: accept.rs without the (c''') per-site distinct-index floor, MIN_DISTINCT_RATIO_V5 0.995 and its HotItemSite refusal; generator.rs and memhard.rs older); every 0.3.25 gate artefact c6629572 through d5b68fae was built on it, none shipped; on an attempt-3 seed it draws attempt 2's id where the freeze goes to attempt 3, the fast-time FAIL; replaced by the freeze's tree on the Mac and both boxes at 13:34 (fingerprints equal). The builds.jsonl pairs_with rows name the parent repo's HEAD, not the override copy, so they never said which tree was linked; the fingerprint is the only reading. The predictability: an epoch's attempt and program id are a deterministic function of its epoch seed, fixed 600 DAA (ten minutes) before the epoch starts, so any two trees compare ahead on every seed by both CLIs; across the freeze and the pre-freeze tree the hash lane's census puts the share of seeds that differ at 2.4 percent (112 of 4,600), a per-epoch roll that only matters where a pre-freeze binary is live, and none is. The boundaries at 1.0 DAA/s from the 13:01:37 read: epoch 20 at DAA 72,000 about 13:59 BST (seed fixed 13:49), epoch 21 at 75,600 about 14:59, epoch 22 at 79,200 about 15:59. RULE 19 and the rebuilt sha inside the shipper's 14:05 clock: 6ccaf9e9 on release-0.3.25-node, both mirrors, 13:41:28 BST = d5b68fae plus rule 19's build-time half (consensus/pow/build.rs fingerprints the linked igneum-pow tree by the shell's method and refuses the build unless it equals packaging/pow-freeze.txt, "cbc5bd0a… 1c420786 class-v5-freeze 2026-10-07", unless IGNEUM_POW_FREEZE_CHECK=0; IGNEUM_POW_FINGERPRINT in every binary's strings, on igneumd's start lines and igneum-miner's engine line; the handshake field on the next commit with its own gate) and the Devnet 3 ceiling re-cut to 90,000 (the publish limit DAA 82,800, about 16:53 BST; the digest moves, named by the canary). The wip's check, pow and core suites read "igneum-pow fingerprint cbc5bd0aa10585c8 (the freeze)" at 13:40. The full gate set at gate priority from 13:41:35 (the build on build-1 with the fingerprint strings read back from both binaries, six suites on build-2, both canary sets), every line by about 13:55; rule 19's known-failed case on build-2 beside it (the pre-freeze copy under the override must fail the build); the fast-time lane's watcher fires on the artefact (about 13:45), reads the fingerprint string before its lease, its SUMMARY with the attempt-3 seed about 14:05; the v5 lane's flip case (the harness taking POW_BIN, the freeze CLI, beside FORK_BIN) reads every v5 epoch's id on the pair against the freeze CLI, 13 minutes a case, within 15 minutes of the sha. The testnet v5-at-0 re-cut landed by its default at 13:32 as 3ffcf83b on release-0.3.24-node (its pairing the freeze), its gate set from 13:40:39, its digest from its canary. The pin line follows 6ccaf9e9's last gate and the SUMMARY. The v5 page's section 0 carries the STOP and the pairing rule's new line at 3b894a4d. The counter-asic-4 documents landed on the box mirror's master at 13:35 BST as 868fea52 (full gate GREEN 73, the stamp on c21f1f38): docs/analysis/counter-asic-4-research.md, docs/design/class-v6-rotating-family.md (the branch's text at 08641162), docs/analysis/chip-model-v3.md (5.12 and the capex correction), tools/ci/export-exclude.txt (+4); igneum-pow/src, igneum-pow/tests and proto-cuda stay on counter-asic-4; no served page changed. The research-landing lane's next: floor-sram (8e9588de) about 13:55 from the Mac on its green stamp (the full gate RED 5 of 73 on build-3, all box-environment classes, the steward told as owner: the gate is the Mac-side script that reaches the boxes from inside), floor-k with tools/chip-model/rtl about 15:45, floor-sm documents by 15:30, the denominator and invention lanes on their words. The 6a5fa763 deploy at 13:42 BST (the explorer's source notice and chain id from the node, b092fa17; /swap reading eth_chainId at load, 46eb9e4b; /metamask on 0x1170 and the public RPC, the nav pill, /faucet and /build on 4464 with the floor dated): Devnet 3's eth_chainId moved from 4463 to 4464 at the floor; checks ok, 19 asserted pages. Lane C's 14:00 numbers: the no-era half in hand on 0ab27582 (the sound form 0.927, 234 of 256, unchanged on the fixed instrument; the control sh256x27 now reads sub-version 3's own 0.682 because the merge brought master's (a') pass to that spelling, so the two sit on one instrument); the era sweep on build-2 on the first free cores; the 15:00 cut after it. The attack pass at 13:46 BST: build-4's F1 lower range stopped by its pid file (83,000 distinct rows kept from indices 0 to 349,999) and restarted at 8 threads from its lowest missing index 78,082 (the 4,900 interleaved rows above it redone and deduped by idx at the merge), freeing 32 cores for the census lane; at 15:30 the shard restarts at 40 threads the same way; its end moves from about 23:20 to about 00:15 BST. A print-only move of the sha at 13:45 BST: c9ad753a on release-0.3.25-node, both mirrors = 6ccaf9e9 plus igneum-miner embedding the full IGNEUM_POW_FINGERPRINT=<64 hex> string on its engine line (igneumd carried it; the miner's binary had only the sixteen-character start-line form, so the pair's read-back on both binaries failed on the miner); no code path, object or digest change. The Devnet 3 digest on the pin: 2066aa57505e5ecbd585d061364abb0032d5b5b29cc41c54f4b38cb81c2ba6eb (the ceiling at 90,000; the publish limit DAA 82,800, about 16:53 BST); the fingerprint cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 (the freeze); the 0.3.24 pin refused both ways on its canary. Its full gate set at gate priority from 13:45:59 (every line by about 14:00, both binaries' strings read back in the build log); 6ccaf9e9's own gate set and rule 19's known-failed self-test by about 13:55; the fast-time SUMMARY on 6ccaf9e9 (the same node code and object) about 13:59 stands as the gate's record; the v5 lane's flip case on the pair follows; the pin line after the last of those. The forty-second landing on master at 13:54 BST (c340a9d4a). The shipper's pin candidate: c9ad753a on release-0.3.25-node (d5b68fae plus rule 19's build fingerprint against the freeze, the ceiling re-cut to 90,000, the miner's full fingerprint line; digest 2066aa57; the publish limit DAA 82,800 about 16:53 BST; the fingerprint cbc5bd0aa10585c8 in both binaries' strings); the app tip b5be4edf (crate 89e83df2); the gate set on c9ad753a by about 14:00; the fast-time SUMMARY on 6ccaf9e9 (the same node code and object) about 13:59; the matrix cells on 6ccaf9e9 stand; the v5 lane's read-back on the 6ccaf9e9 pair stands for c9ad753a; the fleet's binary the build-server lane's seed pair on c9ad753a (the freeze's crate, 29106189ca1e); move id m9ad7-1; the pin about 14:35, the minute about 14:55 to 15:10. PC 1's queue at 13:5x BST: floor lane 1's two jobs (floor-pc1-build-2 "build patched sp1-gpu-server", floor-pc1-restore) hold the card since 13:06; queued behind them, published and signed: kit d's fetch and run (9 minutes) then the read-width run (W = 4, 8 and 16 under the class v5 state term, each its own draw on generator 5 with the era and the node1 state, plus the v5-genesis reference and the 5 October w4 and w64; the W = 8 pack exported at 13:48 on the w8-v5 branch, efb68fce on the mirror, suite green; about 20 minutes). The coordinator's order: floor lane 1 names its end minute by 14:10; an end past 14:30 means its job yields the card at 14:30 (pid file, state restored first), kit d and the read-width run take 30 minutes, its job resumes after; so kit d's rows and the W = 8 row by 15:00 at the latest, inside the 15:30 close. The F8-256 attribution rows at 14:00 BST. p225 (the gate's 1.2457x): reproduced on build-3 with the attack-f8 tool at d08e1e0f over the pow crate at 1c420786 exactly, 1.2452x over the window model at 2^24 nonces, the hot-set verdict clear on both controls, the hottest item 0xb7e000 at 332 reads with no saturated or lossy source. By site: the excess sits at site 4 (instr 23, source r7, window 2^23 items, offset 1, last base writer mad at 21), 1.30 percent of its reads into the top 0.1 percent of items against 0.103 flat (12.6x), with site 9 (instr 37, r5, window 2^22, offset 2, last writer load at 36; the gate's predicted one-one-bit source) second at 0.38 percent (3.7x); every other site at its flat share. Both sites read full index entropy (15 of 15 and 14 of 14 bits) and a largest 256-item bucket at its window expectation, so unlike the morning's tail (a bucket concentration) p225's residue is a value-level concentration on specific items from a mad-written index, the class the gate's one-one-bit prediction names, carried mainly by the mad site and a quarter by the load site it predicted. p212 (the gate's 1.1915x, attempt 4): not reproduced; the pushed tool has no class, state or day flag, so its default path draws a different program for seed 212 (1.5715x with a hot set, the string-seed class v4 draw); the run on the gate's own line (its binary, day 20733, class v5, the dn3 state) on build-2 never started (0 of 12 cores free 13:29 to 13:54 with a higher class ahead; build-1 closed); the attack-pass lane runs p212 with --diag 1 on its own harness when its lease frees; default, p212 stays "predicted source only" in the record. No consensus object moves. THE PIN IS NAMED AT 14:08 BST: release-0.3.25-node = c9ad753a (the 0.3.24 pin 5b673577 plus igneum-miner keygen, the proof-record re-announce, the proving-fee ceiling switch at DAA 90,000 in the Devnet 3 object, the ring self-check every 30 s, the snapshot digest stamp, the vetoed-node status, the proof map's window, eth_chainId and the admission at the chain's height with the network's other id a refusal, rule 19's fingerprint, the testnet re-cut beside it); pairing the class v5 freeze 1c420786, fingerprint cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 read back in both binaries; Devnet 3 digest 2066aa57505e5ecbd585d061364abb0032d5b5b29cc41c54f4b38cb81c2ba6eb; the app tip b5be4edf. Every gate green at 14:01:14 BST (build 13:47 rc=0, igneumd 68526b25, igneum-miner d4f4c98d, /srv/artefacts/0325-c9ad753a/node-lane; miner 29, core 177, exec 54, pow 19, consensus 134, p2p-flows 38 at gate priority; the Devnet 3 canary with the digest, byte 6, override refused, the 0.3.24 pin refused both ways; the testnet canary b2e856ed). On the same node code and object (6ccaf9e9): every gate green at 14:00:56; the fast-time SUMMARY PASS (cross-0325-6ccaf9e9) at 13:57:35 with the pairing read before the lease as the freeze fingerprint on both binaries (13:44:45 to 13:57:35 on build-1: rung 1 at 13:51:10, class v5 by signal at byte 6 from epoch 8 at 13:53:28, 12 of 12 ids equal to the freeze CLI's, the stale node 73 of 73 refused, the restart step resynced in 10 s with the catch-up done after 5 s and nothing of its own mined during it, four sinks equal at 662, 0 PoW rejections and 0 submit timeouts); the v5 lane's read-back PASS id for id on epochs 8 to 10 (13a54a0dd793ca79 attempt 2, d35cd0e9cb186d00 attempt 1, 6104176723170d72 attempt 2, miners 3 of 3 against the freeze CLI at exactly 1c420786); the matrix green on build-3 (build-4's consensus cell unreadable under load 510, the steward's clean run once the load is under 96, its line by 14:25). The FAIL seed re-read: on ec0a8cf9 with the FAIL run's era, day and epoch-9 stream, igneum-pow at exactly 1c420786 draws attempt 3, program id 1f1cf82877f46ee6 (8f481459 the same), so NEITHER id in the FAIL was the freeze's ("cli v5 ebf64b32" came from the release worktree's pre-freeze copy, the pin miner's 65b57e3b from igneum-pow-v5/src); the fingerprint pairing is the gate that catches both; the miner's side of that seed cannot be re-read offline (igneum-miner reads ids from a node's template only), so the pin rests on the fingerprint equality and the record says the attempt-3 seed's miner id was not re-read. The ceiling lands at 90,000 (epoch 25) about 18:53 BST, the publish limit 82,800 about 16:53. The re-execution reading: 27,000 chain blocks in about 8 minutes, RSS peak 12.6 GB on IBD plus walk. The fleet fetches m9ad7-1; THE MINUTE = the last FETCHED plus ten, about 14:30 to 14:40 BST; the Mac and HiveOS entries at it; Windows on PC 2's return; the card after the Windows entry. The minute's gate on the fleet's side: the census at 28,462 (a75c5624 / 0x1fd55139) after the re-walks, the unban per box once equal, the first checkpoint lock after it. The attempt-3 rule's shape: the miner's half of a seeded read did not exist; today it is the v5 lane's kaspa-pow program-id binary on its fork branch (class-v5-node 22920380, the template prepare's own path); igneum-miner program-id with the same flags and output line is the first item on the next node line, after which the harness points at the miner. The testnet v5-at-0 re-cut, landed by the default and amended once for its pinned digest constant: 0d05e795 on release-0.3.24-node, every gate green at 14:03:47 (pow 19, exec 47, miner 28, consensus 134, p2p-flows 38, core 175; the testnet canary with digest 1da30c10e164784ffbf5bf216ef3bf84a2d5da212317b1e535c9850fe14aba2f, byte 6 from genesis, the old-object seeds refused; the Devnet 3 canary on that line cc902690 unchanged); the rows with the testnet lane, with the note that the go seeds should run the 0.3.25 pin's node code with that object (one merge commit onto c9ad753a and its gates after the move's read-backs). Rule 19's known-failed self-test waits on build-2's pool cores (it pre-empted the attack pass's F1 upper range at 14:03 by the class order, 48 cores, 2,023 s in, 4,000 fresh rows kept; re-queued from index 397,292 holding 52 cores; cost about 25 core-hours, the build-2 F1 end about 06:30 BST). The attack pass's p212 run alone on the gate's exact line with --diag 1 --by-site (build-4, 8 threads, 13:56 to 14:01; binary 0f5c98dc, day 20733, class v5, the dn3 state): ratio reproduced 1.1917x (the gate's 1.1915x); hot-set verdict clear; 6-sigma buckets64 flagged at +91 sigma. The excess is one site: site 9 (instr 35, src r6, k_off 2 offset 0, window 2^22) carries 1.789 percent of its reads into the top 0.1 percent, 16.4x its flat share, index entropy 13.981 of 14 bits, the largest 256-item bucket 1.75x the window expectation, saturated source 0; the eight hot positions are site 9 in iterations 0 to 7; every other site at full entropy and its bucket at expectation; the predicted-source site (site 1, instr 7, r5, one-one-bit through a load at 2) reads 0.237 percent, the ordinary 2x of a 2^23 window, so the prediction is not the excess; the hottest items (0x000010 at 296 reads, 0x00000d, 0x00000e, 0x3c001f, 0x18001a) low addresses near the window base. Verdict: p212 is the AP-F8-1 tail class (a per-site bucket concentration at one narrow-window site, 0.019 bits short), not a lossy source (the log at /srv/builds/igneum-wt-attack-v5/p212-diag/p212.log on build-4). The hash lane's reading of both: p212 the bucket class, p225 the value-level class the one-one-bit prediction names; in both the predicted-source line points at the wrong site, so the prediction stays a hint and the by-site histogram is the attribution. The consequence for class v6's layer 4 (to the research lane): the per-site bucket bound at about 2x that would refuse the morning's four refuses neither of these (1.75x and none); the value-level test catches p225; a bucket bound near 1.5x would take p212 at a clean-seed cost nearer 3 to 6 percent. The AP-F8-1 ledger paragraph amended with it on the hash lane's next gate run (ordered). The research-landing lane's landings: floor-sram documents on master as de3d32af (13:55 BST; the lane's text at 8e9588de; full gate GREEN 73, the light gate on the merge; the gate pid rule kept) and floor-invention documents as d28a7656 (14:03; the lane's text at 033ff8d8; full gate GREEN 73): docs/analysis/class-v6/floor/sram-and-floor.md and invention.md; waiting on floor-sm (15:30), floor-k (15:45, with tools/chip-model/rtl), floor-denominator (no word yet), then the counter-asic-4 close follow-up after 15:45. Two more deploys from the builder stream, checks ok (21 asserted pages): 9a029677 at 13:50 BST (/metamask reads eth_chainId at load, 0x1170 pinned as the fallback, read back equal to the public RPC's answer) and 7902e235 at 13:55 (/build's networks table and /faucet name 4464 since the class v5 floor; the faucet signs with the node's chain id); the build-server lane's lease-pool memory rule in its gate (a lease declares its GB, the box ceiling 100 GB with the hands' residents counted; the shipper's order after the 12:06 OOM kill of the seed). Lane C's drawn-era re-read on 0ab27582 at 14:0x BST, run on build-2 (build-4's pool never freed, the waiter withdrawn, named in the row): the sound per-load form (16 x 256 x 1) accepts 254 of 256 seeds under drawn eras at 0.819 rejection per candidate, mean accepted attempt 4.3 (no-era on the same binary 234 of 256 at 0.927); the form at class v4's count (16 x 144 x 3) 254 of 256 at 0.811; every sub-block of 36 instructions or longer 0.80 to 0.84 under eras; the iterated 16 x 27 form 66 of 256 at 0.991 under eras and 128 of 256 at 0.979 no-era, dead on both instruments; the class v4 shape through the same binary reads sub-version 3's own 0.666 and 0.682. So the per-load prototype's verdict of 00:0x was an instrument artefact as the record reopened it, and the sound form stands at 0.82 to 0.93 per candidate with the dataflow rule in execution order as the named fix. The cut with these rows and the 5090 rows lands by 15:00. Floor lane 1 (SM-sparse) at 14:00 BST: its PC 1 jobs are run-ca4-pc1-floorsm-5090-20261008 (the ladder at the 1,300 lock, since 13:07, a 66-minute cap, the card free by 14:13) and the memory-clock ladder at the lock (about 20 minutes); floor-pc1-build-2 and floor-pc1-restore are the prover-floor lane's; every rented pod of lane 1's destroyed (spend USD 27); the stock rows, the decomposition and the self-tune in docs/analysis/class-v6/floor/sm-sparse.md at ccafd9a4 on the mirror; the lock and memory-clock ladders the two rows owed for 15:30. The coordinator's PC 1 order at 14:12: floorsm to 14:13, kit d to about 14:22, the read-width run to about 14:42, memclk to about 15:05 (republished behind them), the 7600 card-in at 15:05 (the hash lane: any Thunderbolt housing on any PC 1 port, the job keys on the new card against the 10:04 baseline; the pass about 50 minutes, rows by 16:00: detect and VRAM, 8 GB: the 1 GiB prototype dataset and the genesis 2 GiB floor fit, 4 GiB fits at about 5.4 GiB needed, 8 GiB does not; the class v5 and v4 fingerprints and the stock bench on the OpenCL kit worker; the app's own rate and watts; the AMD knob grid as on the 9070 XT; the Efficiency, Balanced and Maximum rows; the dataset rows at 2 and 4 GiB from the class v3 packs ds29b, ds30b; the 5.5 GiB row by interpolation, labelled, since the exporter takes power-of-two datasets only; a 5.5 GiB pack is a crate change for tomorrow unless main wants it today, default not today). The founder's order through main at 14:4x BST: Devnet 3 comes back first, the users' cut second. The sink-age guard has no switch (service.rs:1131 hardcoded), so the node lane cuts the hotfix now; the fleet, hub-1 and build-1's four nodes move onto it by a +0 file on the fast-time PASS alone (about 15:00), the full gate set and both canaries running behind for the node-only 0.3.26, a re-move if the set finds a red (nothing risked, the chain being dead). release-0.3.26 open at 822f8767 (the version bump only, the app crate unchanged); its DMG, hive and Windows entries re-cut on the hotfix sha and published at a minute after the network is back. PC 2 back and mining as of 14:4x: its queued jobs run on logon (the 0.3.25 install take first, the sign.ps1 self-test, the UI lane's two, the hash lane's Arc read); the 0.3.25 Windows entry on a clean take, the 0.3.26 one on its own. The DEX lane's /swap fix in its gate at 14:4x (the pools table 640 px wide at 768 px with no overflow, the sentence in a wrapping line under the table). The record's forty-fourth landing's merge gate killed by signal 15 at 14:4x BST on the Mac, a second kill since the rule landed; the steward's TERM-sender log is the read; the merge re-run. THE HOTFIX landed at 14:42:44 BST as f8da7515 on release-0.3.25-node (cold_start_replays: Err only for a node that synced nothing or whose retention root is above genesis; a node holding the chain from genesis replays with a stale sink, one line said; the known-failed test cold_restart_tests::a_node_holding_the_chain_from_genesis_replays_whatever_the_sinks_age; nothing consensus, digest 2066aa57 unchanged); the guard was 10 * 60 * 1000 hard-coded at exec/src/service.rs:1131 with no env, flag or config field; the shipper's prepared 4831c372 dropped. release-0.3.26 = 602bce8c (the bump plus the pin f8da7515; the app crate unchanged). The clock: the seed pair and tarball about 14:52, the fleet fetching from then, the fast-time PASS about 15:27, the fleet, hub-1 and build-1's four on it at about 15:35, the gate set and canaries behind for 0.3.26, a re-move on a red; the users' 0.3.26 entries after the network is back; the testnet go cut re-cut on f8da7515 after. The first block's time to main from the shipper. The 1.5x test's measured row ahead of 15:30 (the fleet hand on RunPod secure cloud, 14:28 to 14:39 BST, pods destroyed, USD 0.62 of the 60 incl. a re-rent loop fault that rented five extra 4090s for 14 pod-minutes, all destroyed by 14:36): the class v5 base (v5-genesis) against knob 3 (hl-k3-sh1024: the 1,024-instruction shadow block at 27 passes, 4x the shadow ops, a class v5 research pack on generator 5), the kit worker d84b1b6c, --batches 250 --batch-log2 24 --block-warps 1, watts the mean of nvidia-smi power.draw over the busy window. RTX 5090 (driver 595.91.07, sm_120): base 140.83 MH/s at 442.7 W (3.14 µJ per hash, fingerprint ae74193ddad19e19 equal to PC 1's), knob 3 111.07 MH/s at 551.1 W (4.96 µJ; at the full 60 s it sits on the 575 W limit at 110.0 MH/s, 5.23 µJ), fingerprint d0d9eccde24b30af. RTX 4090 (driver 570.195.03, sm_89): base 62.41 at 279.3 W (4.48 µJ), knob 3 62.64 at 439.2 W (7.01 µJ), the same fingerprints. Reading: knob 3 costs the card 1.58x the energy per hash (5090) and 1.57x (4090), the same on both architectures; on the 5090 it is power-bound and reads as 21 percent fewer MH/s, on the 4090 the rate holds and the watts climb 61 percent; per shadow instruction the long block costs 0.40x the 256-block's (the per-pass overhead amortised); the 4090/5090 rate ratio 0.44 on the base, 0.56 on knob 3. For the founder's 1.5x: the GPU pays 1.58x for this knob while the k lane's chip-side figure for the same knob is its row; knobs 1, 2 and 4 not benched today (2 has no GPU knob, the k lane agrees; 1 and 4 are new ISA, priced by the microbench until a generator line exists). Logs under the scratchpad's 1p5x/fb-1p5x-5090 and -4090. The DEX lane's /swap fix committed on dex-devnet3 (the syncing and no-answer sentences out of the pools table into a wrapping line under it; both tables fixed layout and normal white space; the row reads "RPC syncing" or "no answer"), checked at 768 px with the public RPC at block 0: no overflow; its first landing's full gate killed at 14:4x by another lane's pkill -f tools/ci/pre-push.sh (the kill-by-name class again), the landing re-running, on master before 15:00 unless killed a third time. The record's forty-fourth landing's re-run merge gate read RED at 14:5x on that same /swap clip at 1600 px dark (the sweep renders the live page while the RPC re-executes), so the record lands after the DEX fix is on master. The forty-fourth landing on master at 14:5x BST (e694030f, after the DEX lane's /swap wrap 92b6da6f reached master at 14:48 and cleared the sweep's red). THE INTEL ROW CLOSES at 14:46 BST: the Arc B580 on the second PC reads the rebuilt kit 65b47211 EQUAL at its logon turn (run-ca3-pc2-v5-intel-bench-20261008: v5 fingerprint 82b19cbde8557ea5 = expected, match True, check PASS, 10.794 MH/s quiet; the v4 control 892b6d55a7ddcfcb PASS at 10.718; both self-tests 96 of 96; the host's "rotr_var rewritten to the shift form before the build" line present, sub-group size 32 with sub_group_shuffle_xor), so the rotate fold was the whole Intel fault, the sub-group patch stays unapplied, and the class v5 kit reads one fingerprint on six platforms: CUDA (RTX 4090), Metal and Apple OpenCL (M5 Max), AMD (RX 9070 XT), Intel (Arc B580), the CPU verifier. The page's Intel row at class-v5 916925f5 (both mirrors 14:51); the 0.3.26 line to the shipper by its rule: the post-freeze class-v5 line with the Intel kit in, 0.3.25 on 1c420786 as published; the shipper carries the Intel kit into the first app cut after 0.3.26. PC 1 at 14:50 BST: no job taken since 14:13 (kit d, the read-width run, the memclk ladder, the card-in detect all "no uploads"), the default ran at 14:48: the signed restart job kind for the app (restart-app-pc1-20261008-cardin); if the app is polling it restarts itself and the queue drains in order; if it is hung or gone only the founder's hand at PC 1 brings the runner back (the ask with main since 14:36). At 15:00 with no job started: kit d's rows and the W = 8 row miss the 15:30 close (the op mix the microbench arithmetic, W = 4 pins), the 7600 pass and the 5.5 GiB rows move to PC 1's return. Floor lane 1's close row to main and the research lane at 14:50 with the memclk ladder labelled owed; its file complete at 32132943. Floor lane 2 (shadow k), the design sweep at 14:5x BST (synthesis-only, 8 lanes, ASAP7 TC 0.70 V, gate-level random-input VCD at two run lengths with the steady state solved; k absolute at N3 against the 5090's 6.2 pJ at the 1,300 lock, 11.3 at stock, the M5 Max 6.9): base (32 regs, 256 imem) 186k cells, 6.9 pJ per lane-op (2.4 clocking), N3 3.5, N2 2.5, k 0.31 / 0.56 / 0.50 (stock / lock / M5 Max); (1) the 64-register file (40-bit word) 268k, 9.7 pJ, N3 4.8, k 0.43 / 0.78 / 0.70, a new ISA on the GPU side (in energy about free on NVIDIA, 255 registers per thread; rate paid only when occupancy drops below the latency-hiding point); (3) the 1,024-instruction imem as built (a flop array) 325k, 12.0 pJ, N3 6.0, k 0.53 / 0.97 / 0.87, measured on the GPU at 1.58x energy per hash for 4x the shadow instructions; (3) with the imem as a 4 KB SRAM macro (2 to 4 pJ per 32-bit read, shared by the lanes) about 7.2 pJ, k about 0.32 / 0.58 / 0.52; (4) the drawn select tree 187k, 6.85 pJ, k 0.30 / 0.55 / 0.50, nothing on either side; (2) 32 lanes and (2') 32 lanes at 16 regs in sim, clock 15:30; (5) all four together in ABC on build-3, clock about 16:00. The reading: the 64-register window is the one robust knob (+0.22 of k at the lock, per lane, not amortisable); the long block adds little once the imem is SRAM; the select tree adds nothing; (1) + (3) as built reaches k about 1.2 at the lock but a chip maker builds the imem as shared SRAM, bringing it to about 0.81 (0.45 at stock), and wider SIMD amortises the fetch further; k 0.85 is not reached by any knob a chip maker cannot amortise away; the DRAM board under 2x at the lock needs the register window AND the long block AND the honest card at its knee, and holds only if the chip's imem cost stays unamortised, which it does not. The node column (claimed from TSMC's headlines: N7 to N5 x0.70, N5 to N3E x0.72, N3E to N2 x0.72; the 5090 and 4090 on 4N, N5 class; the M5 Max N3): base 6.9 ASAP7 / 4.8 N5 / 3.5 N3 / 2.5 N2, k at the lock 0.78 / 0.56 / 0.40, the GDDR7 board at the lock 2.4x / 2.8x / 3.2x; the 64-register core 9.7 / 6.8 / 4.9 / 3.5, k 1.09 / 0.78 / 0.56, the board 2.0x / 2.4x / 2.8x. The one line: of the 2.8x at k 0.56, the N5-to-N3 node step is worth 0.4x (a factor 1.17, claimed); the rest is the memory system (3.6x at zero shadow at the lock) less what the class v4 shadow takes back on the card's own node; on the card's own node the base core sits at k 0.78 and the 64-register core at 1.09, so "near 0.9" is reached node-for-node by the window alone; what it does not survive is the node step a chip project buys (an N3 core gives back the 0.4x, an N2 core 0.8x). The placed 8-lane core in detailed route on build-4 at nice 19 (about 16:00). Branch class-v6-floor-k. The hash lane's reading of the 64-register window: not exportable inside 20 minutes: eight registers fixed in four places that must agree bit for bit (the generator's operand draw modulo 8 and the register init from one seed word each; the three kernel texts r0 to r7 selected by (i + 1) & 7; the CPU verifier's register array; the warp's hash fold over the eight), a 64-entry window needing an init rule for the 56 extra registers (a design choice) and a fold rule for the output, then the emitters, the verifier and the vector check: a half-day line; the GPU-side figure modelled: 64 live registers a lane on top of the kernel's forty-odd puts a thread at about 110 of its 255 registers, occupancy to about half, the rate expected to hold under the latency-bound read chain (the 5090 hides about 330,000 ops a hash, chip-model-v3 5.7), the energy per hash to move little, the per-lane register traffic the unmeasured term; the half-day line can start after the 7600 pass if main wants it tonight (default not tonight). The research-landing lane: class-v6-floor-denominator at fc265d8d landed on master as d461e365 (14:50 BST; denominator.md plus the three app/igneum-app/tiers files; full gate GREEN 73); floor-sm (32132943, sm-sparse.md only, 717 lines; the worker patch on the branch) in its gate, landing about 15:03; k by 15:45; the close rows within 30 minutes of 15:45. Two deploys at 14:53 BST, checks ok (21 asserted pages): d461e365 (the DEX lane's 92b6da6f: /swap's RPC-syncing and no-answer lines under the pools table, both tables wrapping) and c8ce4b52 (the UI lane's site-fee-words on main's order: the dev fee as the fixed 1% fee with the app's Settings sentence on /miner and /dev-fee, "switch" and "switchable" gone from the fee card, the "Off with" row and the description metas; no "switch" string served on /miner). No chip text changed. The hotfix f8da7515's full gate set and both canaries read green at 14:50 BST (exec 55 with the dead-chain test, the mixed-version step HANDSHAKE on the unchanged digest), so THE SECOND MINUTE IS 15:05:00 BST, named on the gates rather than waiting for the fast-time pair: every box at +0 (81 of 97 fetched at 14:57, the rest by the pull), hub-1 and build-1's four by hand; the fleet's tarball 29f11d85 (igneumd 07a522f3, the miner unchanged eead4d0c, both fingerprints the freeze's). The merge default taken: 33 solo miners stopped at 14:53 to 14:57 (the fastest branch 122 under the epoch 21 cliff at 75,600, past which branches never merge); they restart with the move and the branches merge inside epoch 20. The 0.3.25 Windows entry skipped for good (a 0.3.25 Windows node would deadlock); the Windows line lands with 0.3.26 (602bce8c; the installer's copy-step fix on that tree by 15:30). The next readings: the first block on the rejoined chain, the replay rate, the first lock. Floor-sm (32132943, sm-sparse.md only) landed on master as 69335fc1 at 14:58 BST (full gate GREEN 73); the landings today: 868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1; open: floor-k by 15:45 with tools/chip-model/rtl, the design document's close rows within 30 minutes of 15:45. PC 1 is back: kit d closed on the 5090 (run-ca4-pc1-v6d-packs-5090-20261008, 14:51 to 15:0x BST, all PASS; rows with the research lane and floor lane 5), the runner's stall 38 minutes (14:13 to 14:51, the founder's hand or the restart job). The op-mix row inside the shadow block: against the same worker's w4 base (119.95 MH/s at 308.2 W unlocked; 100.55 at 190.5 W at 1,300), the shuffle-heavy table costs the block 155.5 W unlocked and 80.6 W at the lock (level with the stock table's 152 and 84 this morning), the multiply-heavy table 104.6 W and 62.0 W (31 and 26 percent less), the rate flat within 0.4 percent: the weight table is a 30 percent lever on the block's watts on Blackwell, with the sign the microbench gave for the multiply end and smaller magnitudes than its arithmetic on both ends. Floor lane 5's hinted w64-l2: 92.35 MH/s at 369.1 W unlocked (23 percent under w4, 1.56x its energy per hash) and 37.59 at 164.1 W at the lock (2.3x), dead at the knee as at stock. PC 1's queue: the read-width run (the W = 8 row about 15:30), floor lane 1's memclk ladder, the 7600 detect about 15:5x and its pass (the first 7600 row about 16:00, the stall's slip); the register-window hand for 16:30; the 5.5 GiB kit from the worker lane at 16:00 with the rented 5090 row behind it. Lane D at 15:1x BST, every stratum COMPLETE: w1band 3,000 (build-2), w4band 3,000 (build-3), w4shape64 3,000 (build-4), shape256 3,000 and shape64lossy 2,000 (build-3), the four lossy-share points 3,000 each (build-1), the F8 label space's p2 to p65 and p212 to p225 through the sigma form (build-2); point A DONE on build-1 (64 seeds: 45 PASS, 3 beyond 1.2x, 2 hot sets p38 and p54, both REFUSED by the class v5 floor at 0.9932 and 0.9945 in the floor read on build-3); point B at 54 of 64 on build-3; the x4/x8/x16 verifier rows resubmitted on build-3's free cores after waiting on build-2's pool since 14:5x; 38,000 drawn eras in all today, about 90 core-hours; the 16:30 report holds with sections 6.4 (the lossy curve per shape), 6.5 (the width-4 floor decision), 6.6 (point A), 6.8 (the seven known-failed seeds through the sigma form, the bucket bound retired into the bit read) in the tree; point B and the verifier rows by 16:00, as partials if not. The floor-invention knee-row amendment (3951528d) landed as 66c3401e at 15:12 BST (full gate GREEN 73); the landings today: 868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1, 66c3401e. The fast-time SUMMARY PASS (cross-0325-f8da7515-2) at 15:17:51 BST on the hotfix f8da7515 (the freeze fingerprint on both binaries read before the lease; 15:04:51 to 15:17:51 on build-1: rung 1 at 15:11:28, class v5 by signal at byte 6 from epoch 8 at 15:13:20, 12 of 12 ids equal to the freeze CLI's, the stale node 78 of 78 refused, the restart step resynced in 6 s with the catch-up done after 3 s, four sinks equal at 662, 0 PoW rejections); the first run on the same artefact (15:03:21) read the crossing green too, its FAIL line the late joiner's wait letting two epochs past the observation window into the id rows (harness scope, fixed); the cold-restart class is the node lane's unit test, the pair cannot read it. The shipper's preview 1 at 15:1x BST: preview-26-1 at 57476931 on the mirror = the coordinator's f2781776 plus app-ia-26 e4773cf0 (item 4, the Tune page), release-0.3.26 f44baa25 (602bce8c plus install-detach-26 b39d5dd5, the take-3b copy-step fix) and the preview mark (state.preview from IGNEUM_PREVIEW at build time, appended after the version on the About line and the footer, empty on a public cut; no constant on any branch); the build-server lane cuts the kit, the cross with the env, the payload with the f8da7515 Windows pair and PC 1's host (host-0326 ahead in PC 1's queue), the install takes on PC 1 and PC 2; the Mac DMG by the Mac chain and the install over the founder's app by the shipper's hand; each machine's version and time to main. One red on e4773cf0: ui/heat-region.test.mjs:137 (a resting card's wording), the UI lane's by 15:35; the preview ships with it named, the public 0.3.26 app cut waits on green; take 3c (the public 0.3.26 Windows entry) on f44baa25 behind the preview takes. PC 1 at 15:14 BST: the founder's restart of the app at 15:06 ended the read-width run at 194 s (exit -1, "script was ended") after its three stock rows landed: v5-genesis 118.83 MH/s at 423.5 W, W = 4 under the state term 117.54 at 430.9 W, W = 8 117.54 at 451.5 W; so THE W = 8 ROW EXISTS AT STOCK (the rate equal to 0.01 MH/s, 4.8 percent more energy per hash; with floor lane 3 and the research lane); the 1,300 lock rows and the W = 16 state-term row owed from a republished run (run-ca3-pc1-readwidth-5090-20261008-b, behind the detect and the memclk ladder, about 16:30). The runner had already resumed at 14:51 on the signed restart job (kit d 14:51 to 15:02, the read-width run from 15:03), so the founder's hand restarted an app that was polling; no harm beyond the lost rows. PC 1's queue: the 7600 detect, the ds55 kit fetch, the memclk ladder (about 25 minutes), the read-width run b, the shipper's host preview build, then the 7600 pass (the OpenCL bench with --cards-off on the new key, the grid, the tier rows, the 5.5 GiB rows on the 7600 and the 5090). A caveat on every PC 1 row since 14:2x: the 5090 reads about 13 percent under the morning on the same packs and worker (v5-genesis 118.8 against 135.9), a host-side change with the eGPU swap; the next job's card line reads the PCIe link, the first suspect. The 5.5 GiB kit done (the worker lane, ds55-v5 at b57045fb, the emulated worker's self-test PASS on the 5.5 GiB pack; the kit on build-1, sha 2d7f55e8) and with the fleet lane for the rented 5090 row. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule diff --git a/site/dev-fee.html b/site/dev-fee.html index 1944f2b22..7d796d3a8 100644 --- a/site/dev-fee.html +++ b/site/dev-fee.html @@ -244,11 +244,11 @@
-

The Ember software takes a visible, switchable 1% dev fee, the norm for GPU miners. One block template in 100 is requested with the dev payout address instead of yours. The fee goes to Igneum Labs LTD, the company that ships the software.

+

The Ember software takes a 1% dev fee, the norm for GPU miners. One block template in 100 is requested with the dev payout address instead of yours. The fee goes to Igneum Labs LTD, the company that ships the software.

- + @@ -257,9 +257,10 @@

Measured on a test network, 4 Oct 2026: 9 fee blocks in the 785 blocks of two fee-paying miners (1.146%); the control miner at --dev-fee 0 paid none; the miners’ counters and both nodes agree. The log.

-
Earnings, as the app shows it
-
Dev fee: 1 block in 100 pays the people who make this app
-

The network itself takes nothing. This is the app’s fee, the same way every mining app takes one. This switch turns it off.

+
Settings, as the app shows it
+

The dev fee 1%

+

The Ember software takes a 1% dev fee. One block template in 100 is requested with the dev payout address instead of yours. The fee goes to Igneum Labs LTD, the company that ships the software.

+

The network itself takes nothing. This is the app’s fee, the same way every mining app takes one.

What the miner prints at start
dev fee 1% (1 block in 100) to 0x<address>; --dev-fee 0 turns it off
diff --git a/site/miner.html b/site/miner.html index 6597023a8..1e84486c4 100644 --- a/site/miner.html +++ b/site/miner.html @@ -4,13 +4,13 @@ Igneum Ember, the one-click GPU miner - + - + @@ -18,7 +18,7 @@ - + @@ -374,11 +374,11 @@ pre b{color:var(--molten-text);font-weight:500}
-

The Ember software takes a visible, switchable 1% dev fee, the norm for GPU miners. One block template in 100 is requested with the dev payout address instead of yours. The fee goes to Igneum Labs LTD, the company that ships the software.

+

The Ember software takes a 1% dev fee, the norm for GPU miners. One block template in 100 is requested with the dev payout address instead of yours. The fee goes to Igneum Labs LTD, the company that ships the software.

WhereOff with
The app, Earningsthe Dev fee switch under the money rows
The appno switch: the fee is fixed at 1% and Settings shows it, last on the page
The command line--dev-fee 0
HiveOS, extra configDEV_FEE=0
Mining to a poolnothing to turn off: the pool issues the templates, so the 1-in-100 mechanism does not exist, and the pool's own fee is the only one
- + @@ -387,9 +387,10 @@ pre b{color:var(--molten-text);font-weight:500}

Measured on a test network, 4 Oct 2026: 9 fee blocks in the 785 blocks of two fee-paying miners (1.146%); the control miner at --dev-fee 0 paid none; the miners’ counters and both nodes agree. The log.

-
Earnings, as the app shows it
-
Dev fee: 1 block in 100 pays the people who make this app
-

The network itself takes nothing. This is the app’s fee, the same way every mining app takes one. This switch turns it off.

+
Settings, as the app shows it
+

The dev fee 1%

+

The Ember software takes a 1% dev fee. One block template in 100 is requested with the dev payout address instead of yours. The fee goes to Igneum Labs LTD, the company that ships the software.

+

The network itself takes nothing. This is the app’s fee, the same way every mining app takes one.

What the miner prints at start
dev fee 1% (1 block in 100) to 0x<address>; --dev-fee 0 turns it off
diff --git a/site/swap.html b/site/swap.html index 123932166..2941b1651 100644 --- a/site/swap.html +++ b/site/swap.html @@ -70,9 +70,10 @@ input[readonly]{color:var(--ash)} .status[data-state="bad"]{color:var(--bad)} .status code,td code,dd code{font-family:var(--f-mono);font-size:13px;background:var(--obsidian);padding:1px 6px;border-radius:6px} p.small,.small{font-size:14px;color:var(--ash);line-height:1.55} -table.swaps,table.pools{width:100%;border-collapse:collapse;font-size:14px;margin-top:8px} +table.swaps,table.pools{width:100%;table-layout:fixed;border-collapse:collapse;font-size:14px;margin-top:8px} +table.swaps td,table.pools td,table.swaps th,table.pools th{white-space:normal;overflow-wrap:anywhere;word-break:break-word} table.swaps th,table.pools th{text-align:left;color:var(--ash);font-weight:500;padding:8px 6px;border-bottom:1px solid var(--line)} -table.swaps td,table.pools td{padding:10px 6px;border-bottom:1px solid var(--line);vertical-align:top;overflow-wrap:anywhere} +table.swaps td,table.pools td{padding:10px 6px;border-bottom:1px solid var(--line);vertical-align:top;white-space:normal;overflow-wrap:anywhere} table.swaps td[data-state="bad"]{color:var(--bad)} table.swaps tr.empty td{color:var(--ash)} p.notice{margin-top:14px;padding:12px 14px;border-radius:10px;border:1px solid var(--line-2);font-size:13px;color:var(--molten);display:block} @@ -284,6 +285,7 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:13px;overflo
WhereOff with
The app, Earningsthe Dev fee switch under the money rows
The appno switch: the fee is fixed at 1% and Settings shows it, last on the page
The command line--dev-fee 0
HiveOS, extra configDEV_FEE=0
Mining to a poolnothing to turn off: the pool issues the templates, so the 1-in-100 mechanism does not exist, and the pool's own fee is the only one
PoolReserves
Reading the chain…
+

@@ -512,9 +514,10 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:13px;overflo function refreshPools(){ rpc('eth_blockNumber',[]).then(function(n){ var h=parseInt(n,16);rpcBehind=h';return;} + if(rpcBehind){$('pools-body').innerHTML='RPC syncing';say($('pools-note'),'The public RPC is syncing: block '+h.toLocaleString('en-GB')+' of at least '+DEPLOY_BLOCK.toLocaleString('en-GB')+'. Reserves, quotes and swaps appear when it reaches the pools.','bad');return;} + say($('pools-note'),'',''); return readPools(); - }).catch(function(){$('pools-body').innerHTML='The public RPC did not answer. Try again in a minute.';}); + }).catch(function(){$('pools-body').innerHTML='no answer';say($('pools-note'),'The public RPC did not answer. Try again in a minute.','bad');}); } function readPools(){ Promise.all(POOLS.map(function(p){return call(A.router,enc(S.getReserves,['address','address'],[p.a,p.b])).then(function(r){var w=words(r);return fmt(w[0],2)+' '+p.sa+' / '+fmt(w[1],2)+' '+p.sb;}).catch(function(){return 'unreadable';});})).then(function(rows){ diff --git a/tools/attack/v6-census/benchall.sh b/tools/attack/v6-census/benchall.sh new file mode 100644 index 000000000..0347d3dc7 --- /dev/null +++ b/tools/attack/v6-census/benchall.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash +# class v6 census lane: the CPU verifier per warp for each candidate's accepted program (seed igneum-v6c/0), one leased core, +# three repeats of 20 warps each, the record's class first and last (drift check). Output: $ROOT/bench.log +set -u +ROOT=/srv/builds/v6-census; B=$ROOT/bin/14c550e3/igneum-pow; REW=13,11,6,10,8,8,7,2,6,4 +export IGNEUM_FAMILY_GATE=1 +echo "# bench start $(date -u +%FT%TZ) host $(hostname) cores ${LEASE_CPUSET:-?} bin $(sha256sum $B | cut -c1-16)" +run() { tag=$1; cls=$2; w=$3; for rep in 1 2 3; do echo "== $tag rep $rep class $cls weights ${w:-base}"; if [ -n "$w" ]; then IGNEUM_FG_WEIGHTS=$w $B bench --seed igneum-v6c/0 --class "$cls" --warps 20 2>&1 | grep -iE "warp|ms|verif" | tail -4; else $B bench --seed igneum-v6c/0 --class "$cls" --warps 20 2>&1 | grep -iE "warp|ms|verif" | tail -4; fi; done; } +run ctrl mx8+sh256x27 "" +run w16 w16m8g+sh256x27 "" +run a w64m8g+sh256x27 "" +run b w16m8g+sh256x27 "$REW" +run c w64m8g+sh256x27 "$REW" +run ctrl-again mx8+sh256x27 "" +echo "# bench end $(date -u +%FT%TZ)" diff --git a/tools/attack/v6-census/launch.sh b/tools/attack/v6-census/launch.sh new file mode 100644 index 000000000..eff5dec03 --- /dev/null +++ b/tools/attack/v6-census/launch.sh @@ -0,0 +1,29 @@ +#!/usr/bin/env bash +# class v6 census lane: queue the census jobs on this box under the lease pool (measure class, nice 19, pid files under +# /srv/builds/v6-census/pids). usage: launch.sh ... jobs: ctrl-none a-none b-none c-none w16-none ctrl-era a-era b-era c-era w16-era +set -u +C="$1"; shift +ROOT=/srv/builds/v6-census; BIN="$ROOT/bin/$C/igneum-pow"; SCRIPT="$ROOT/v6census.sh" +REW=13,11,6,10,8,8,7,2,6,4 +for job in "$@"; do + cand=${job%-*}; mode=${job#*-} + case $cand in + ctrl) CLASS="mx8+sh256x27"; ERAW=4; W="";; + a) CLASS="w64m8g+sh256x27"; ERAW=64; W="";; + b) CLASS="w16m8g+sh256x27"; ERAW=16; W="$REW";; + c) CLASS="w64m8g+sh256x27"; ERAW=64; W="$REW";; + w16) CLASS="w16m8g+sh256x27"; ERAW=16; W="";; + *) echo "unknown $job"; continue;; + esac + if [ "$mode" = none ]; then ERAS=none; SEEDS=256; BT=""; else ERAS="0,1,2,3,4,5,6,7"; SEEDS=32; BT=1; fi + # under an era the candidate's own class carries the width (a single allowed width leaves the base mix as drawn: the + # smoke of 13:4x UK read 512 bytes per hash on mx8 at --era-widths 64), and --era-widths pins the era's set to it + ENVS="THREADS={cores} BIN=$BIN OUT=$ROOT TAG=$job CLASS=$CLASS ERAS=$ERAS SEEDS=$SEEDS ERAW=$ERAW" + [ -n "$W" ] && ENVS="$ENVS IGNEUM_FG_WEIGHTS=$W" + [ -n "$BT" ] && ENVS="$ENVS IGNEUM_FG_BITTEST=1" + # shellcheck disable=SC2086 + nohup /srv/builds/_bin/lease pool 16 --min 4 --nice 19 --class measure --label "class v6 census: $job ($CLASS, era widths $ERAW, weights ${W:-base}) on $C" --owner class-v6-census -- env $ENVS "$SCRIPT" > "$ROOT/run-$job.log" 2>&1 & + echo "$!" > "$ROOT/pids/$job.lease.pid" + echo "queued $job pid $! class $CLASS eraw $ERAW weights ${W:-base} bittest ${BT:-off}" + sleep 1 +done diff --git a/tools/attack/v6-census/summ.py b/tools/attack/v6-census/summ.py new file mode 100644 index 000000000..2e64d2620 --- /dev/null +++ b/tools/attack/v6-census/summ.py @@ -0,0 +1,41 @@ +#!/usr/bin/env python3 +"""class v6 census lane: per-candidate summary of v6census.sh TSVs (one row per seed).""" +import sys, collections, statistics +def load(path): + rows=[]; head=None; tail=None + for line in open(path): + line=line.rstrip('\n') + if line.startswith('#'): + if head is None: head=line + else: tail=line + continue + if line.startswith('cand\t'): continue + f=line.split('\t') + if len(f)<10: continue + rows.append(dict(cand=f[0],era=f[1],seed=int(f[2]),n=int(f[3]),acc=int(f[4]),att=int(f[5]),bz=(float(f[6]) if f[6]!='nan' else float('nan')),site=f[7],bit=f[8],reasons=f[9])) + return head,tail,rows +for path in sys.argv[1:]: + head,tail,rows=load(path) + print(head); + if tail: print(tail) + by=collections.defaultdict(list) + for r in rows: by[r['era']].append(r) + print("era\tseeds\taccepted\texhausted\tcandidates\tr_per_candidate\tmean_att\tmax_att\tbitz_max\tbitz_over6\tbit_refusals\treasons") + allrows=[] + for era in sorted(by, key=lambda e: (e!='none', int(e) if e!='none' else -1)): + rs=by[era]; allrows+=rs + n=len(rs); acc=sum(r['acc'] for r in rs); cands=sum(r['n'] for r in rs); rej=cands-acc + atts=[r['att'] for r in rs if r['acc']] + reasons=collections.Counter() + for r in rs: + for kv in r['reasons'].split(';'): + if '=' in kv: + k,v=kv.rsplit('=',1); reasons[k]+=int(v) + bz=[r['bz'] for r in rs if r['acc'] and r['bz']==r['bz']] + bref=reasons.get('c,',0)+reasons.get('c, per-load shadow',0) + print(f"{era}\t{n}\t{acc}\t{n-acc}\t{cands}\t{rej/cands if cands else float('nan'):.3f}\t{statistics.mean(atts) if atts else float('nan'):.2f}\t{max(atts) if atts else -1}\t{max(bz) if bz else float('nan'):.1f}\t{sum(1 for z in bz if z>6)}\t{bref}\t{' '.join(f'{k}={v}' for k,v in reasons.most_common())}") + if len(by)>1: + rs=allrows; n=len(rs); acc=sum(r['acc'] for r in rs); cands=sum(r['n'] for r in rs); rej=cands-acc; atts=[r['att'] for r in rs if r['acc']] + bz=[r['bz'] for r in rs if r['acc'] and r['bz']==r['bz']] + print(f"ALL\t{n}\t{acc}\t{n-acc}\t{cands}\t{rej/cands:.3f}\t{statistics.mean(atts):.2f}\t{max(atts)}\t{max(bz):.1f}\t{sum(1 for z in bz if z>6)}") + print() diff --git a/tools/attack/v6-census/uniform-launch.sh b/tools/attack/v6-census/uniform-launch.sh new file mode 100644 index 000000000..60776ad8f --- /dev/null +++ b/tools/attack/v6-census/uniform-launch.sh @@ -0,0 +1,21 @@ +#!/usr/bin/env bash +# class v6 census lane: the F8-form uniformity read (v6census-uniform) per candidate, no era, 16 seeds at 2^20 nonces, under the lease pool. +set -u +ROOT=/srv/builds/v6-census; U=$ROOT/bin/14c550e3/v6census-uniform +REW=13,11,6,10,8,8,7,2,6,4 +SEEDS=${SEEDS:-16}; NONCES=${NONCES:-1048576}; ERA=${ERA:-none}; ERAW=${ERAW:-4} +for job in "$@"; do + case $job in + ctrl) CLASS="mx8+sh256x27"; W=""; EW=4;; + a) CLASS="w64m8g+sh256x27"; W=""; EW=64;; + b) CLASS="w16m8g+sh256x27"; W="$REW"; EW=16;; + c) CLASS="w64m8g+sh256x27"; W="$REW"; EW=64;; + w16) CLASS="w16m8g+sh256x27"; W=""; EW=16;; + *) echo "unknown $job"; continue;; + esac + TAG="uniform-$job-$ERA" + ENVS="IGNEUM_FAMILY_GATE=1"; [ -n "$W" ] && ENVS="$ENVS IGNEUM_FG_WEIGHTS=$W" + # shellcheck disable=SC2086 + nohup /srv/builds/_bin/lease pool 16 --min 4 --nice 19 --class measure --label "class v6 census: F8-form uniform $job era $ERA ($CLASS, weights ${W:-base}), $SEEDS seeds x 2^20" --owner class-v6-census -- env $ENVS "$U" --class "$CLASS" --seeds "$SEEDS" --nonces "$NONCES" --threads "{cores}" --era "$ERA" --era-widths "$EW" > "$ROOT/$TAG.tsv" 2> "$ROOT/run-$TAG.log" & + echo "$!" > "$ROOT/pids/$TAG.lease.pid"; echo "queued $TAG pid $!"; sleep 1 +done diff --git a/tools/attack/v6-census/uniform/Cargo.lock b/tools/attack/v6-census/uniform/Cargo.lock new file mode 100644 index 000000000..fbf25ce13 --- /dev/null +++ b/tools/attack/v6-census/uniform/Cargo.lock @@ -0,0 +1,14 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "igneum-pow" +version = "0.2.0" + +[[package]] +name = "v6census-uniform" +version = "0.1.0" +dependencies = [ + "igneum-pow", +] diff --git a/tools/attack/v6-census/uniform/Cargo.toml b/tools/attack/v6-census/uniform/Cargo.toml new file mode 100644 index 000000000..d8b2b0d63 --- /dev/null +++ b/tools/attack/v6-census/uniform/Cargo.toml @@ -0,0 +1,15 @@ +[package] +name = "v6census-uniform" +version = "0.1.0" +edition = "2021" +publish = false + +[[bin]] +name = "v6census-uniform" +path = "src/main.rs" + +[dependencies] +igneum-pow = { path = "../../../../igneum-pow" } + +[profile.release] +opt-level = 3 diff --git a/tools/attack/v6-census/uniform/src/main.rs b/tools/attack/v6-census/uniform/src/main.rs new file mode 100644 index 000000000..60fe4a996 --- /dev/null +++ b/tools/attack/v6-census/uniform/src/main.rs @@ -0,0 +1,117 @@ +//! v6census-uniform (class v6 census lane, 8 October 2026): the F8-form uniformity read of the invention lane's tool +//! (`tools/attack/v6-invention/uniform`) with the era draw added, for the read-width and op-mix candidates. Per seed: +//! the first accepted candidate of the class under the harness (`IGNEUM_FAMILY_GATE`, the class's own attempt cap), +//! then over `nonces` nonces every load's word index through the library's own `trace_load_indices`; per site the +//! distinct-index ratio `d_s / E_s` with `E_s = N - N^2 / (2 W_s)` at the site's window over the width (the (c'') +//! form), and the cross-hash ITEM histogram's top 0.1 percent share against a uniform SplitMix64 control of the same +//! size (the F8 harness's null; under an era the narrow-window sites raise the share by design, so the line to read +//! is the candidate against the control class at the same era, not the no-era 1.2x alone). One TSV row per seed. +//! +//! v6census-uniform --class w64m8g+sh256x27 --seeds 16 --nonces 1048576 --threads 16 [--era igneum-era-test/3 --era-widths 64] +use igneum_pow::generator::{attempts_class_to, max_attempts_for, EraParams, LoadClass, ITERATIONS}; +use igneum_pow::seed::{seed_words_from_bytes, SplitMix64}; +use igneum_pow::verify::{trace_load_indices, window, DatasetMode, DatasetSource}; +use std::collections::HashSet; +use std::io::Write; +use std::sync::atomic::{AtomicUsize, Ordering}; +use std::sync::Mutex; + +fn arg(args: &[String], k: &str, d: &str) -> String { + args.iter().position(|a| a == k).and_then(|i| args.get(i + 1).cloned()).unwrap_or_else(|| d.to_string()) +} + +fn top_share(counts: &mut Vec, frac: f64) -> (f64, u32) { + let total: u64 = counts.iter().map(|&c| c as u64).sum(); + counts.sort_unstable_by(|a, b| b.cmp(a)); + let k = ((counts.len() as f64) * frac) as usize; + let top: u64 = counts[..k].iter().map(|&c| c as u64).sum(); + (top as f64 / total as f64, counts[0]) +} + +fn parse_widths(s: &str) -> Vec { + let mut v: Vec = s.split(',').map(|x| match x.trim() { "4" => 1u8, "16" => 4, "64" => 16, _ => panic!("width") }).collect(); + v.sort_unstable(); + v +} + +fn main() { + let args: Vec = std::env::args().collect(); + let class_name = arg(&args, "--class", "mx8+sh256x27"); + let seeds: u32 = arg(&args, "--seeds", "16").parse().unwrap(); + let nonces: u32 = arg(&args, "--nonces", "1048576").parse().unwrap(); + let threads: usize = arg(&args, "--threads", "16").parse().unwrap(); + let log2: u32 = arg(&args, "--log2", "28").parse().unwrap(); + let day = arg(&args, "--day", "2026-10-03"); + let prefix = arg(&args, "--prefix", "igneum-v6c"); + let era = arg(&args, "--era", "none"); + let widths = parse_widths(&arg(&args, "--era-widths", "4")); + let mut class = LoadClass::parse(&class_name).expect("class"); + if era != "none" { + assert!(era.starts_with("igneum-era-test/"), "era: igneum-era-test/"); + class = LoadClass::era(class, &EraParams::test_era_bytes(&era), &widths); + } + let cap = max_attempts_for(&class); + let ds = DatasetSource::new(&day, DatasetMode::ClosedForm, log2); + let items = 1usize << (log2 - 4); + let mask = (1u32 << log2) - 1; + let n = (nonces as f64) * (ITERATIONS as f64); // evaluations per site + let next = AtomicUsize::new(0); + let out = Mutex::new(std::io::stdout()); + println!("class\tera\tseed\tattempt\tprogram_id\tmin_site_ratio\tmin_site\ttop0.1_share\tcontrol_share\tratio_to_control\tmax_item_reads\tcontrol_max\treads"); + std::thread::scope(|s| { + for _ in 0..threads { + s.spawn(|| loop { + let i = next.fetch_add(1, Ordering::Relaxed) as u32; + if i >= seeds { + break; + } + let label = format!("{prefix}/{i}"); + let tries = attempts_class_to(&label, label.as_bytes(), class, cap); + let Some((p, _)) = tries.into_iter().find(|(_, r)| r.is_ok()) else { + let mut o = out.lock().unwrap(); + writeln!(o, "{class_name}\t{era}\t{i}\texhausted").unwrap(); + continue; + }; + let seed = seed_words_from_bytes(label.as_bytes()); + let loads: Vec<_> = p.instrs.iter().filter(|x| x.op.is_load()).cloned().collect(); + let sites = loads.len(); + let mut distinct: Vec> = (0..sites).map(|_| HashSet::with_capacity(nonces as usize)).collect(); + let mut counts = vec![0u32; items]; + let mut reads: u64 = 0; + let mut base = 0u32; + while base < nonces { + let rows = trace_load_indices(&p, &seed, base, &ds); + for (k, row) in rows.iter().enumerate() { + let site = k % sites; + for &idx in row.iter() { + distinct[site].insert(idx); + counts[(idx >> 4) as usize] += 1; + reads += 1; + } + } + base += 32; + } + let (min_ratio, min_site) = distinct + .iter() + .enumerate() + .map(|(s, d)| { + let ins = &loads[s]; + let w = if p.class.era.is_some() { (window(ins, mask, log2).0 as u64 + 1) as f64 } else { (1u64 << log2) as f64 } / (ins.width.max(1) as f64); + let e_s = n - n * n / (2.0 * w); + (d.len() as f64 / e_s, s) + }) + .fold((f64::MAX, 0usize), |a, b| if b.0 < a.0 { b } else { a }); + let (share, max_reads) = top_share(&mut counts, 0.001); + let mut ctrl = vec![0u32; items]; + let mut rng = SplitMix64::new(0x9e37_79b9_7f4a_7c15 ^ i as u64); + for _ in 0..reads { + let x = rng.next() as usize & (items - 1); + ctrl[x] += 1; + } + let (cshare, cmax) = top_share(&mut ctrl, 0.001); + let mut o = out.lock().unwrap(); + writeln!(o, "{class_name}\t{era}\t{i}\t{}\t{:016x}\t{min_ratio:.5}\t{min_site}\t{share:.6}\t{cshare:.6}\t{:.4}\t{max_reads}\t{cmax}\t{reads}", p.attempt, p.program_id(), share / cshare).unwrap(); + }); + } + }); +} diff --git a/tools/attack/v6-census/v6census.sh b/tools/attack/v6-census/v6census.sh new file mode 100755 index 000000000..6c735e951 --- /dev/null +++ b/tools/attack/v6-census/v6census.sh @@ -0,0 +1,41 @@ +#!/usr/bin/env bash +# Class v6 census lane (8 October 2026, docs/analysis/class-v6/census-w16-mix.md): the sub-version 3 census of one +# candidate class through `igneum-pow accept` of the class-v6-census crate (the harness: IGNEUM_FAMILY_GATE widens the +# class v4 rules to any read width, adds the (c''') floor at 0.995, reads the value-level index-bit bias on every class +# and refuses it under IGNEUM_FG_BITTEST; IGNEUM_FG_WEIGHTS re-weights the ten non-load families). One TSV row per +# (candidate, era, seed): candidates walked (the class's own cap, 256), accepted, the accepting attempt, the worst +# index-bit bias in sigma of the accepted program, the first failing part per rejection as a histogram. +# env: BIN (the igneum-pow binary), OUT (dir), TAG (candidate label), CLASS (the --class), THREADS, +# ERAS ("none" or a comma list of igneum-era-test indices "0,1,2,3,4,5,6,7"), SEEDS (per era), ERAW (--era-widths bytes), +# IGNEUM_FG_WEIGHTS (optional), IGNEUM_FG_BITTEST (optional), SEEDTAG (seed label prefix) +set -u +BIN=${BIN:?}; OUT=${OUT:?}; TAG=${TAG:?}; CLASS=${CLASS:?} +THREADS=${THREADS:-16}; ERAS=${ERAS:-none}; SEEDS=${SEEDS:-256}; ERAW=${ERAW:-4}; SEEDTAG=${SEEDTAG:-igneum-v6c} +export IGNEUM_FAMILY_GATE=1 +mkdir -p "$OUT/logs/$TAG" "$OUT/pids" +echo "$$" > "$OUT/pids/$TAG.pid" +TSV="$OUT/$TAG.tsv" +{ + echo "# $TAG class $CLASS eras [$ERAS] seeds $SEEDS era-widths $ERAW weights ${IGNEUM_FG_WEIGHTS:-base} bittest ${IGNEUM_FG_BITTEST:-off} bin $(sha256sum "$BIN" | cut -c1-16) start $(date -u +%FT%TZ) host $(hostname) threads $THREADS" + printf 'cand\tera\tseed\tcandidates\taccepted\tattempt\tbit_z\tbit_site\tbit_bit\treasons\n' +} > "$TSV" +one() { + era=$1; i=$2 + log="$OUT/logs/$TAG/$era-$i.log" + if [ "$era" = none ]; then + "$BIN" accept --seed "$SEEDTAG/$i" --class "$CLASS" > "$log" 2>&1 + else + "$BIN" accept --seed "$SEEDTAG/$i" --class "$CLASS" --era "igneum-era-test/$era" --era-widths "$ERAW" > "$log" 2>&1 + fi + n=$(grep -c '^attempt' "$log") + acc=$(grep -c 'ACCEPTED' "$log") + first=$(grep -m1 'ACCEPTED' "$log" | sed 's/^attempt \([0-9]*\):.*/\1/') + bz=$(grep -m1 'ACCEPTED' "$log" | sed -n 's/.*bit z max \([0-9.]*\) at site \([0-9]*\) bit \([0-9]*\).*/\1\t\2\t\3/p') + reasons=$(grep 'rejected' "$log" | sed 's/.*rejected, //' | sed "s/^(\([^)]*\)).*/\1/" | sort | uniq -c | sort -rn | awk '{printf "%s=%s;", $2, $1}') + printf '%s\t%s\t%s\t%s\t%s\t%s\t%s\t%s\n' "$TAG" "$era" "$i" "$n" "$acc" "${first:--1}" "${bz:-nan - -}" "$reasons" +} +export -f one; export BIN OUT TAG CLASS ERAW SEEDTAG +for era in ${ERAS//,/ }; do + for i in $(seq 0 $((SEEDS - 1))); do echo "$era $i"; done +done | xargs -P "$THREADS" -n 2 bash -c 'one "$0" "$1"' >> "$TSV" +echo "# end $(date -u +%FT%TZ) rows=$(grep -vc '^#' "$TSV")" >> "$TSV" diff --git a/tools/ca3-v4-amend/pc-card-in.ps1 b/tools/ca3-v4-amend/pc-card-in.ps1 new file mode 100644 index 000000000..298d0f83e --- /dev/null +++ b/tools/ca3-v4-amend/pc-card-in.ps1 @@ -0,0 +1,322 @@ +# card-in (8 October 2026, the hash lane, the coordinator's ask at 09:5x UK): one job for the eGPU housings on PC 1 and PC 2. It +# reads the installed app's card list (api/state mining.cards: key, name, vendor, vram), compares it with the last read in a +# state file on the PC, and runs the full pass on the ONE card that was not there last time, with no hand on the PC: +# 1. class v4 and class v5 fingerprints against the kits (CUDA worker on an NVIDIA card with the sub-version 3 kit's +# v4-devnet-epoch0, expected e370fb2080b7dbb1; the v5 kit's OpenCL worker on every vendor with v5-dn3-epoch0, expected +# 82b19cbde8557ea5, and v4-genesis, expected 892b6d55a7ddcfcb, the 9070 XT's PASS reading of 8 October 00:16Z); +# 2. rate and watts (NVIDIA: the nvidia-smi sampler at 1 Hz, power.draw, power.draw.instant and power.draw.average, around +# a 60 s CUDA bench; AMD and Intel: measure-only, the app's own hash_now and power_w for the card, the median of 30 s +# after a 75 s settle, with the card mining in the app); +# 3. the clock-lock knee grid where the lever exists (NVIDIA through the Power Helper's cleared sequence, 300 MHz steps from +# the card's maximum down, 60 s each, stop when the rate falls 3 percent under the unlocked rate; AMD measure-only until +# the ADLX tool is on the PC, Intel measure-only; the row says which); +# 4. VRAM and the dataset fit (1 GiB dataset plus the cache; a card under 2 GiB does not fit); +# 5. a bench-log row and a miner-bench.json row (RESULT ROW lines) for the audit lane; +# 6. the restore (-rgc through the helper, the card's app choices put back exactly), the state file updated, and "next". +# Known-failed first: no new card reads "RESULT card-in no new card" and does nothing else (exit 0, status no_new_card); the +# first run on a PC writes the baseline and does nothing else (status baseline). Never two cards: more than one new key +# stops the job (status ambiguous) with the keys named. Nothing escalates, nothing is installed, settings.json is never +# written (the runner's --cards-off switches the card off for the quiet rows and back on after; a script never switches cards). +$ErrorActionPreference = 'Continue' +$jobName = 'pc-card-in' +$started = Get-Date +$capMinutes = 50 +$deadline = $started.AddMinutes($capMinutes) +function Stamp { (Get-Date).ToUniversalTime().ToString('yyyy-MM-ddTHH:mm:ssZ') } +function Summary([string] $status, [hashtable] $extra) { + $o = [ordered]@{ job = $jobName; status = $status; duration_s = [int]((Get-Date) - $started).TotalSeconds; finished_at = (Stamp) } + foreach ($k in $extra.Keys) { $o[$k] = $extra[$k] } + 'SUMMARY ' + ($o | ConvertTo-Json -Compress -Depth 6) +} +function Say([string] $s) { Write-Output ('[' + (Get-Date -Format 'HH:mm:ss') + '] ' + $s) } +function Median($vals) { $v = @($vals | ForEach-Object { [double]$_ } | Sort-Object); if ($v.Count -eq 0) { return $null }; return [math]::Round($v[[int][math]::Floor(($v.Count - 1) / 2)], 1) } +function Mean($vals) { $v = @($vals | ForEach-Object { [double]$_ }); if ($v.Count -eq 0) { return $null }; return [math]::Round((($v | Measure-Object -Sum).Sum / $v.Count), 1) } + +"RESULT start $(Stamp) job=$jobName machine=$env:COMPUTERNAME app_version=$env:IGNEUM_APP_VERSION" +$appDir = Join-Path $env:LOCALAPPDATA 'igneum\app' +$u = Join-Path $appDir 'app.url' +if (-not (Test-Path -LiteralPath $u)) { 'RESULT error no app.url (the installed app is not running)'; Summary 'failed' @{ error = 'no app url' }; exit 2 } +$base = (Get-Content -LiteralPath $u -Raw).Trim() +function State() { try { return ((Invoke-WebRequest -Uri ($base + 'api/state') -UseBasicParsing -TimeoutSec 5).Content | ConvertFrom-Json) } catch { return $null } } +function Post([string] $path, [string] $json) { try { Invoke-WebRequest -Uri ($base + $path) -Method POST -Body $json -ContentType 'application/json' -UseBasicParsing -TimeoutSec 5 | Out-Null; return $true } catch { Say ($path + ': ' + $_.Exception.Message); return $false } } +$s = State +if (-not $s) { 'RESULT error api/state unreachable'; Summary 'failed' @{ error = 'no state' }; exit 2 } +$cards = @($s.mining.cards) +$keys = @($cards | ForEach-Object { $_.key }) +"RESULT cards now $(Stamp) $(($cards | ForEach-Object { $_.key + '=' + $_.name + ' [' + $_.vendor + ', ' + $_.kind + ', ' + $_.vram_mb + ' MB, ' + $(if ($_.enabled) { 'on' } else { 'off' }) + ']' }) -join ' | ')" + +# ---- the last read ---- +$stateDir = Join-Path $appDir 'jobs\card-in' +if (-not (Test-Path $stateDir)) { New-Item -ItemType Directory -Path $stateDir -Force | Out-Null } +$lastFile = Join-Path $stateDir 'last.json' +$last = @() +if (Test-Path -LiteralPath $lastFile) { try { $last = @((Get-Content -LiteralPath $lastFile -Raw | ConvertFrom-Json).keys) } catch { $last = @() } } +function WriteLast() { ([ordered]@{ keys = $keys; at = (Stamp); machine = $env:COMPUTERNAME } | ConvertTo-Json -Compress) | Set-Content -LiteralPath $lastFile -Encoding ascii } +if (-not (Test-Path -LiteralPath $lastFile)) { + WriteLast + "RESULT card-in baseline written: $($keys.Count) cards ($($keys -join ', ')); nothing measured (the first run on this PC records what is here; plug the card and say in)" + Summary 'baseline' @{ keys = $keys } + exit 0 +} +$new = @($keys | Where-Object { $last -notcontains $_ }) +$gone = @($last | Where-Object { $keys -notcontains $_ }) +if ($gone.Count -gt 0) { "RESULT card-in gone since the last read: $($gone -join ', ')" } +if ($new.Count -eq 0) { + WriteLast + "RESULT card-in no new card (last read $($last.Count) keys, now $($keys.Count); nothing done)" + Summary 'no_new_card' @{ keys = $keys } + exit 0 +} +if ($new.Count -gt 1) { + "RESULT card-in STOP: $($new.Count) new keys ($($new -join ', ')); one card at a time; nothing done, the last read unchanged" + Summary 'ambiguous' @{ new = $new } + exit 3 +} +$key = $new[0] +$card = $cards | Where-Object { $_.key -eq $key } | Select-Object -First 1 +$name = $card.name; $vendor = "$($card.vendor)"; $vram = [int64]$card.vram_mb +$fits = ($vram -ge 2048) +"RESULT card-in NEW key=$key name=`"$name`" vendor=$vendor kind=$($card.kind) vram_mb=$vram dataset_fit=$(if ($fits) { 'yes (1 GiB dataset plus the cache)' } else { 'NO (under 2 GiB)' }) enabled=$($card.enabled) identities=$($card.identities) power_pct=$($card.power_pct)" + +# ---- the kits ---- +$jobs = Split-Path $env:IGNEUM_JOB_DIR +$v5kit = Join-Path $jobs 'fetch-ca3-v5-kit-20261007' +$v4kit = $null +foreach ($id in @('fetch-ca3-v4-sub3-pc1-20261007', 'fetch-ca3-v4-sub3-pc2-20261007')) { $d = Join-Path $jobs $id; if (Test-Path (Join-Path $d 'packs\v4-devnet-epoch0\kernel_bound.cu')) { $v4kit = $d; break } } +if (-not (Test-Path $v5kit)) { 'RESULT kits v5 MISSING (the fetch job fetch-ca3-v5-kit-20261007 runs first; republish it after any app update)' } +$clExe = Join-Path $v5kit 'bin\windows\igneum-worker-opencl.exe' +$haveV5 = (Test-Path $clExe) -and (Test-Path (Join-Path $v5kit 'packs\v5-dn3-epoch0\leaves.bin')) +"RESULT kits v5=$(if ($haveV5) { $v5kit + ' (worker sha256 ' + (Get-FileHash -Algorithm SHA256 $clExe).Hash.ToLower().Substring(0, 16) + ')' } else { 'MISSING (the fetch job fetch-ca3-v5-kit-20261007 runs first)' }) v4=$(if ($v4kit) { $v4kit } else { 'none (no CUDA pack on this PC; the NVIDIA v4 row runs through the OpenCL kit)' })" +$inst = @("$env:LOCALAPPDATA\Programs\Igneum Miner", "$env:ProgramFiles\Igneum Miner") | Where-Object { Test-Path (Join-Path $_ 'igneum-app.exe') } | Select-Object -First 1 +$cudaExe = if ($inst) { Join-Path $inst 'igneum-worker-cuda.exe' } else { $null } +$expected = @{ 'v4-devnet-epoch0' = 'e370fb2080b7dbb1'; 'v5-dn3-epoch0' = '82b19cbde8557ea5'; 'v4-genesis' = '892b6d55a7ddcfcb' } + +# ---- the card's device on each path ---- +$isNv = ($vendor -eq 'nvidia') +$smi = $null; $idx = $null; $uuid = $null; $bus = $null; $maxSm = $null; $driver = '' +if ($isNv) { + $c = Get-Command nvidia-smi -ErrorAction SilentlyContinue; if ($c) { $smi = $c.Source } + if (-not $smi) { foreach ($p in @((Join-Path $env:ProgramFiles 'NVIDIA Corporation\NVSMI\nvidia-smi.exe'), (Join-Path $env:SystemRoot 'System32\nvidia-smi.exe'))) { if (Test-Path $p) { $smi = $p; break } } } + if ($smi) { + $gpus = @(& $smi --query-gpu=index,name,uuid,pci.bus_id,power.limit,power.max_limit,clocks.max.sm,driver_version,memory.total --format=csv,noheader 2>&1 | ForEach-Object { "$_" }) + $gpus | ForEach-Object { "RESULT gpu $_" } + # the app's name is the driver's name; a second identical card carries "#2" in its key and sits at the higher index + $rows = @($gpus | Where-Object { $_ -match [regex]::Escape($name) }) + $pick = 0; if ($key -match '#(\d+)$') { $pick = [int]$Matches[1] - 1 } + if ($rows.Count -gt $pick) { $fld = $rows[$pick] -split ',\s*'; $idx = $fld[0].Trim(); $uuid = $fld[2].Trim(); $bus = $fld[3].Trim(); $maxSm = $fld[6].Trim(); $driver = $fld[7].Trim() } + if ($null -ne $idx) { "RESULT card nvidia index=$idx uuid=$uuid bus=$bus max_sm_mhz=$maxSm driver=$driver" } else { "RESULT card nvidia: '$name' not in nvidia-smi's list; the NVIDIA rows run through the OpenCL kit without watts" } + } else { 'RESULT card nvidia: nvidia-smi not found; the NVIDIA rows run through the OpenCL kit without watts' } +} +$clDev = $null; $clLine = '' +if ($haveV5) { + $listExe = $clExe; if ($inst -and (Test-Path (Join-Path $inst 'igneum-worker-opencl.exe'))) { $listExe = Join-Path $inst 'igneum-worker-opencl.exe' } + $list = @(& $listExe --list 2>&1 | ForEach-Object { "$_" }) + $list | ForEach-Object { "RESULT list $_" } + $want = $name -replace '^(NVIDIA|AMD|Intel\(R\))\s+', '' + $short = ($want -replace '\(R\)|\(TM\)|Graphics|GeForce|Radeon', '' -replace '\s+', ' ').Trim() + $cands = @() + foreach ($l in $list) { if ($l -match '^\s*\[(\d+)\]\s+(.*?)\s+\|' -and $l -notmatch 'dup') { $n = [int]$Matches[1]; $t = $Matches[2]; $ts = ($t -replace '\(R\)|\(TM\)|Graphics|GeForce|Radeon', '' -replace '\s+', ' ').Trim(); if ($ts -match [regex]::Escape($short) -or $short -match [regex]::Escape($ts) -or ($card.code -and $t -match [regex]::Escape("$($card.code)"))) { $cands += ,@($n, $l) } } } + $pick = 0; if ($key -match '#(\d+)$') { $pick = [int]$Matches[1] - 1 } + if ($cands.Count -gt $pick) { $clDev = $cands[$pick][0]; $clLine = $cands[$pick][1] } + if ($null -ne $clDev) { "RESULT card opencl device=$clDev line=$($clLine.Trim())" } else { "RESULT card opencl: no --list device matches '$name' (code $($card.code)); the OpenCL rows are skipped" } +} + +# ---- the card's quiet state is the RUNNER's: a script never switches cards (the playbook-quit rule). The detect run reads the +# new card with the app mining on it; the measured pass is published again with --cards-off and finds it off here. +$choices = @($cards | ForEach-Object { [ordered]@{ key = $_.key; enabled = [bool]$_.enabled; identities = [int]$_.identities; power_pct = [int]$_.power_pct } }) +$restored = $true +function Workers { @(Get-CimInstance Win32_Process -Filter "Name = 'igneum-worker-opencl.exe' OR Name = 'igneum-worker-cuda.exe' OR Name = 'igneum-worker-metal.exe'" -ErrorAction SilentlyContinue | ForEach-Object { "$($_.Name):$($_.ProcessId):[$($_.CommandLine -replace '\s+', ' ')]" }) } +"RESULT workers_before $(Stamp) $((@(Workers)) -join ' ')" +$quiet = -not $card.enabled +"RESULT card $(Stamp) $(if ($quiet) { 'quiet: the runner switched it off (--cards-off) before this script' } else { 'LOADED: the card mines in the app (a detect run, or a pass published without --cards-off); the rows below are LOADED-card figures' })" +if (-not $quiet -and $env:IGNEUM_CARDIN_DETECT_ONLY -eq '1') { WriteLast; "RESULT next: detect only; publish the pass with --cards-off $key"; Summary 'detected' @{ key = $key; name = $name; vendor = $vendor; vram_mb = $vram; fits = $fits }; exit 0 } + +$rowsOut = [ordered]@{} +$samples = Join-Path $stateDir 'nv-samples.csv' +$sampler = $null +function ReadWindow([datetime] $t0, [datetime] $t1) { + $sel = @() + if (Test-Path $samples) { + foreach ($l in (Get-Content -LiteralPath $samples -ErrorAction SilentlyContinue)) { + $p = $l -split ',\s*' + if ($p.Count -lt 5) { continue } + $ts = $null + try { $ts = [datetime]::ParseExact($p[0].Trim(), 'yyyy/MM/dd HH:mm:ss.fff', [cultureinfo]::InvariantCulture) } catch { continue } + if ($ts -ge $t0 -and $ts -le $t1) { $sel += ,$p } + } + } + return ,$sel +} +function Watts([datetime] $t0, [datetime] $t1) { + $w = ReadWindow $t0.AddSeconds(8) $t1 + return [ordered]@{ draw = (Mean ($w | ForEach-Object { $_[1] })); instant = (Mean ($w | Where-Object { $_.Count -ge 8 -and $_[6] -match '^\s*[\d.]+\s*$' } | ForEach-Object { $_[6] })); average = (Mean ($w | Where-Object { $_.Count -ge 8 -and $_[7] -match '^\s*[\d.]+\s*$' } | ForEach-Object { $_[7] })); sm = (Mean ($w | ForEach-Object { $_[2] })); mem = (Mean ($w | ForEach-Object { $_[3] })); tmax = (($w | ForEach-Object { [int]$_[4] } | Measure-Object -Maximum).Maximum); n = $w.Count } +} + +# ---- the Power Helper (NVIDIA lock path, the cleared sequence) ---- +$helperDir = Join-Path $env:LOCALAPPDATA 'igneum\app\sweep' +$cmdFile = Join-Path $helperDir 'cmd.txt' +$helperLog = Join-Path $helperDir 'helper.log' +function HelperAliveAge() { $a = Join-Path $helperDir 'helper.alive'; if (-not (Test-Path -LiteralPath $a)) { return 9999 }; try { $v = [int64]((Get-Content -LiteralPath $a -Raw).Trim()); return ([int64][double]::Parse((Get-Date -UFormat %s)) - $v) } catch { return 9999 } } +function HelperSeqBase() { + $m = 0 + foreach ($f in @($cmdFile, $helperLog)) { if (Test-Path $f) { foreach ($l in (Get-Content -LiteralPath $f -ErrorAction SilentlyContinue)) { if ($l -match '(?:^|\s)(\d{1,6}) (?:dev|pl|lgc|rgc|lmc|rmc|nvidia-smi|reregister)\b') { $v = [int]$Matches[1]; if ($v -gt $m) { $m = $v } } } } } + return $m + 100 +} +function HelperReset() { + Set-Content -LiteralPath $cmdFile -Value '' -NoNewline -Encoding ascii + try { Stop-ScheduledTask -TaskName 'Igneum Power Helper' -ErrorAction SilentlyContinue } catch { } + Start-Sleep -Seconds 2 + try { Start-ScheduledTask -TaskName 'Igneum Power Helper' -ErrorAction Stop } catch { $t = "$_" -replace '\s+', ' '; "RESULT helper start refused: $t"; return $false } + $t = 0 + while ($t -lt 20) { Start-Sleep -Seconds 1; $t++; if ((HelperAliveAge) -le 4) { "RESULT helper fresh after $t s"; return $true } } + $s0 = HelperSeqBase + $mark = 0; if (Test-Path $helperLog) { $mark = @(Get-Content -LiteralPath $helperLog -ErrorAction SilentlyContinue).Count } + Set-Content -LiteralPath $cmdFile -Value "$s0 dev $idx`n" -NoNewline -Encoding ascii + $t2 = 0 + while ($t2 -lt 20) { Start-Sleep -Seconds 1; $t2++; $new = @(Get-Content -LiteralPath $helperLog -ErrorAction SilentlyContinue); if ($new.Count -gt $mark -and ($new[$mark..($new.Count - 1)] | Where-Object { $_ -match "\b$s0 dev " })) { "RESULT helper up after $($t + $t2) s (probe dev line answered)"; return $true } } + 'RESULT helper STOP: no heartbeat and no answer to a probe dev line; nothing escalates; the lock rows are skipped' + return $false +} +$viaHelper = $false +$seq = 0 +function HelperSend([string] $verb) { + $script:seq += 2 + $s0 = $script:seq; $s1 = $script:seq + 1; $script:seq = $s1 + $mark = 0; if (Test-Path $helperLog) { $mark = @(Get-Content -LiteralPath $helperLog -ErrorAction SilentlyContinue).Count } + if ((HelperAliveAge) -gt 10) { if (-not (HelperReset)) { return 'no helper (the reset failed)' } } + Set-Content -LiteralPath $cmdFile -Value "$s0 dev $idx`n$s1 $verb`n" -NoNewline -Encoding ascii + $t = 0 + while ($t -lt 30) { + Start-Sleep -Seconds 1; $t++ + $new = @(Get-Content -LiteralPath $helperLog -ErrorAction SilentlyContinue) + if ($new.Count -gt $mark) { $hit = $new[$mark..($new.Count - 1)] | Where-Object { $_ -match "\b$s1 nvidia-smi " } | Select-Object -First 1; if ($hit) { return ($hit -replace '^\d+\s+', '') } } + } + $b = HelperSeqBase + if ($b -gt $script:seq) { "RESULT helper seq re-based from $script:seq to $b"; $script:seq = $b; return (HelperSend $verb) } + return "no helper.log line for seq $s1 within 30 s" +} +function SetLock([int] $mhz) { if (-not $viaHelper) { return 'refused: no helper' }; $o = HelperSend "lgc $mhz"; if ($o -match 'not have permission|No permission|Insufficient|not supported|Unable|ERROR|no helper') { return "refused: $o" }; return "ok (helper, -lgc 0,$mhz): $o" } +function ResetClocks() { if (-not $viaHelper) { return 'not attempted (no helper)' }; $o = HelperSend 'rgc'; if ($o -match 'no helper.log') { if (HelperReset) { $o = "after a task restart: $(HelperSend 'rgc')" } }; return $o } + +# ---- the benches ---- +function ClBench([string] $pk, [int] $batches) { + $d = Join-Path $v5kit "packs\$pk" + $t0 = Get-Date + $out = @(& $clExe --bench-pack --pack $d --device $clDev --batch-log2 24 --batches $batches 2>&1 | ForEach-Object { "$_" }) + $code = $LASTEXITCODE; $t1 = Get-Date + $res = $out | Where-Object { $_ -match '^RESULT ' } | Select-Object -Last 1 + $fp = ''; $mhs = $null; $check = '' + if ($res -match 'fingerprint=([0-9a-f]{16})') { $fp = $Matches[1] } + if ($res -match 'mhs=([0-9.]+)') { $mhs = [double]$Matches[1] } + if ($res -match 'check=(\w+)') { $check = $Matches[1] } + $err = ''; if (-not $res -or $code -ne 0) { $e = ($out | Where-Object { $_ -match 'FAIL|error|MISMATCH' } | Select-Object -First 1); $err = if ($e) { ($e -replace '\s+', ' ') } else { "exit $code, no RESULT line" } } + return [pscustomobject]@{ pack = $pk; t0 = $t0; t1 = $t1; rc = $code; fp = $fp; mhs = $mhs; check = $check; err = $err; path = 'opencl-kit' } +} +function CudaBench([string] $pk, [int] $batches) { + $d = Join-Path $v4kit "packs\$pk" + $env:CUDA_VISIBLE_DEVICES = $uuid + $t0 = Get-Date + $out = @(& $cudaExe --bench --pack $d --batches $batches --batch-log2 24 --block-warps 1 --device 0 2>&1 | ForEach-Object { "$_" }) + $code = $LASTEXITCODE; $t1 = Get-Date + $res = $out | Where-Object { $_ -match '^RESULT pack=' } | Select-Object -First 1 + $fp = ''; $mhs = $null; $check = '' + if ($res -and $res -match 'fingerprint=([0-9a-f]{16})') { $fp = $Matches[1] } + if ($res -and $res -match 'mhs=([\d.]+)') { $mhs = [double]$Matches[1] } + if ($res -and $res -match 'check=(\S+)') { $check = $Matches[1] } + $err = ''; if (-not $res -or $code -ne 0) { $e = ($out | Where-Object { $_ -match 'FAIL|error|MISMATCH' } | Select-Object -First 1); $err = if ($e) { ($e -replace '\s+', ' ') } else { "exit $code, no RESULT line" } } + return [pscustomobject]@{ pack = $pk; t0 = $t0; t1 = $t1; rc = $code; fp = $fp; mhs = $mhs; check = $check; err = $err; path = 'cuda-installed' } +} +function Report($b, [string] $label, $w) { + $want = $expected[$b.pack]; $match = if ($want -and $b.fp -eq $want) { 'yes' } elseif ($want) { 'no' } else { 'unknown' } + $eff = if ($w -and $w.draw -and $w.draw -gt 0 -and $b.mhs) { [math]::Round($b.mhs / $w.draw, 4) } else { '' } + $wt = if ($w) { "watts=$($w.draw) watts_instant=$($w.instant) watts_average=$($w.average) sm_mhz=$($w.sm) mem_mhz=$($w.mem) temp_max=$($w.tmax) samples=$($w.n)" } else { 'watts= (no sampler on this path)' } + "RESULT $label card=`"$name`" key=$key pack=$($b.pack) path=$($b.path) fingerprint=$($b.fp) expected=$want match=$match check=$($b.check) mhs=$($b.mhs) $wt mh_per_w=$eff wall_s=$([int]($b.t1 - $b.t0).TotalSeconds) exit=$($b.rc) error=$($b.err)" + return $match +} + +$lockRows = @() +$fpV4 = ''; $fpV5 = ''; $unlocked = $null; $bestEff = $null; $knee = '' +try { + if ($isNv -and $smi -and $null -ne $idx) { + if (Test-Path $samples) { Remove-Item -LiteralPath $samples -Force } + $sampler = Start-Process -FilePath $smi -ArgumentList @('-i', $idx, '--query-gpu=timestamp,power.draw,clocks.sm,clocks.mem,temperature.gpu,clocks_throttle_reasons.active,power.draw.instant,power.draw.average', '--format=csv,noheader,nounits', '-lms', '1000') -RedirectStandardOutput $samples -WindowStyle Hidden -PassThru + Start-Sleep -Seconds 6 + "RESULT sampler pid=$($sampler.Id) first=[$((@(Get-Content -LiteralPath $samples -ErrorAction SilentlyContinue | Select-Object -First 1)) -join '')]" + } + # 1. fingerprints: the OpenCL kit on every vendor (v5 then the v4 control), 5 batches each + if ($haveV5 -and $null -ne $clDev) { + $b5 = ClBench 'v5-dn3-epoch0' 5; $fpV5 = Report $b5 'FP' $(if ($sampler) { Watts $b5.t0 $b5.t1 } else { $null }); $rowsOut['v5'] = $b5.fp + $b4 = ClBench 'v4-genesis' 5; $fpV4 = Report $b4 'FP' $(if ($sampler) { Watts $b4.t0 $b4.t1 } else { $null }); $rowsOut['v4_genesis'] = $b4.fp + } else { 'RESULT FP skipped: no OpenCL kit or no matching device' } + # 2. the rate row: CUDA on NVIDIA with the sub-version 3 pack (60 s), else the OpenCL kit's v4 control for 60 s + $probe = $null + if ($isNv -and $v4kit -and $cudaExe -and (Test-Path $cudaExe) -and $uuid) { $probe = CudaBench 'v4-devnet-epoch0' 5 } + elseif ($haveV5 -and $null -ne $clDev) { $probe = ClBench 'v4-genesis' 5 } + if ($probe -and -not $probe.err -and $probe.mhs) { + $n = [math]::Max(20, [math]::Min(2000, [int][math]::Ceiling(60 * $probe.mhs * 1e6 / 16777216.0))) + $r0 = ResetClocks + $u = if ($probe.path -eq 'cuda-installed') { CudaBench 'v4-devnet-epoch0' $n } else { ClBench 'v4-genesis' $n } + $w = if ($sampler) { Watts $u.t0 $u.t1 } else { $null } + $m = Report $u 'RATE unlocked' $w + if ($u.path -eq 'cuda-installed') { $rowsOut['v4_devnet'] = $u.fp } + $unlocked = [ordered]@{ mhs = $u.mhs; watts = $(if ($w) { $w.draw } else { $null }); eff = $(if ($w -and $w.draw) { [math]::Round($u.mhs / $w.draw, 4) } else { $null }); sm = $(if ($w) { $w.sm } else { $null }); path = $u.path; match = $m } + # 3. the knee grid (NVIDIA through the helper): 300 MHz steps from the card's maximum down, 60 s each, stop at a 3 percent fall + if ($isNv -and $null -ne $idx -and -not $probe.err) { + $task = Get-ScheduledTask -TaskName 'Igneum Power Helper' -ErrorAction SilentlyContinue + if ($task) { $seq = HelperSeqBase; if (HelperReset) { $viaHelper = $true; "RESULT helper task started; commands from seq $seq" } } + else { 'RESULT helper task NOT REGISTERED (Power control off in the app): no lock path; measure-only' } + if ($viaHelper) { + $top = 0; if ($maxSm -match '^\d+$') { $top = [int]$maxSm } + $start = [int]([math]::Floor(($top - 1) / 300) * 300); if ($start -le 0) { $start = 2400 } + $bestEff = $unlocked.eff; $bestAt = 'unlocked' + for ($mhz = $start; $mhz -ge 600; $mhz -= 300) { + if ((Get-Date) -gt $deadline.AddMinutes(-6)) { "RESULT LOCK mhz=$mhz skipped: budget spent (six minutes kept for the restore and the app row)"; break } + $lk = SetLock $mhz + if ($lk -match '^refused') { "RESULT LOCK mhz=$mhz $lk"; break } + Start-Sleep -Seconds 3 + $b = if ($u.path -eq 'cuda-installed') { CudaBench 'v4-devnet-epoch0' $n } else { ClBench 'v4-genesis' $n } + $w = if ($sampler) { Watts $b.t0 $b.t1 } else { $null } + $m = Report $b "LOCK mhz=$mhz" $w + if ($b.err -or -not $b.mhs) { break } + $eff = if ($w -and $w.draw) { [math]::Round($b.mhs / $w.draw, 4) } else { $null } + $lockRows += [ordered]@{ mhz = $mhz; sm = $(if ($w) { $w.sm } else { $null }); mhs = $b.mhs; watts = $(if ($w) { $w.draw } else { $null }); eff = $eff; match = $m } + if ($eff -and $eff -gt $bestEff) { $bestEff = $eff; $bestAt = "$mhz MHz" } + if ($m -eq 'no') { "RESULT LOCK mhz=$mhz fingerprint mismatch: the grid stops, clocks reset"; break } + if ($unlocked.mhs -and $b.mhs -lt 0.97 * $unlocked.mhs) { $knee = "$mhz MHz (rate $([math]::Round(100 * (1 - $b.mhs / $unlocked.mhs), 1)) percent under unlocked)"; "RESULT KNEE $knee best=$bestAt eff=$bestEff"; break } + } + if (-not $knee) { $knee = "not reached by $([math]::Max(600, $mhz + 300)) MHz"; "RESULT KNEE $knee best=$bestAt eff=$bestEff" } + } + } elseif (-not $isNv) { "RESULT LOCK measure-only: $vendor has no lock path in this job ($(if ($vendor -eq 'amd') { 'the ADLX tool once it is on the PC' } else { 'Intel: none' }))" } + } else { "RESULT RATE skipped: $(if ($probe) { $probe.err } else { 'no bench path for this card' })" } +} finally { + if ($viaHelper) { "RESULT restore rgc: $(ResetClocks)" } + if ($sampler) { try { Stop-Process -Id $sampler.Id -Force -ErrorAction SilentlyContinue } catch { }; 'RESULT restore sampler stopped' } + 'RESULT restore cards: the runner puts the card back with its own choices on exit (nothing switched here)' +} + +# 4. the app row (every vendor): the card mining in the app, 75 s settle, the median of 30 s of hash_now and power_w +$appMhs = $null; $appW = $null +if ($card.enabled) { + Start-Sleep -Seconds 75 + $hs = @(); $ws = @() + for ($i = 0; $i -lt 6; $i++) { $st = State; if ($st) { $cc = $st.mining.cards | Where-Object { $_.key -eq $key } | Select-Object -First 1; if ($cc -and $cc.hash_now -gt 0) { $hs += [double]$cc.hash_now; $ws += [double]$cc.power_w } }; Start-Sleep -Seconds 5 } + $appMhs = Median $hs; $appW = Median $ws + "RESULT APP card=`"$name`" key=$key mhs=$appMhs power_w=$appW mh_per_w=$(if ($appMhs -and $appW -and $appW -gt 0) { [math]::Round($appMhs / $appW, 4) } else { '' }) samples=$($hs.Count) (the installed app's own reading, the card mining)" +} else { 'RESULT APP skipped (the card was off in the app before this job, or the restore was refused)' } + +# 5. the rows +$date = (Get-Date).ToUniversalTime().ToString('yyyy-MM-dd') +$mhs = if ($unlocked -and $unlocked.mhs) { $unlocked.mhs } else { $appMhs } +$watts = if ($unlocked -and $unlocked.watts) { $unlocked.watts } else { $appW } +$eff = if ($mhs -and $watts -and $watts -gt 0) { [math]::Round($mhs / $watts, 3) } else { $null } +$best = $lockRows | Where-Object { $_.eff } | Sort-Object { $_.eff } -Descending | Select-Object -First 1 +$tuned = if ($best) { "lock $($best.mhz) MHz: $($best.mhs) MH/s at $($best.watts) W ($($best.eff) MH/W)" } elseif ($isNv) { 'stock (no lock path on this run)' } else { "stock (measure-only on $vendor)" } +$fpNote = "v5 $(if ($fpV5 -eq 'yes') { 'match' } elseif ($fpV5 -eq 'no') { 'MISMATCH' } else { 'not read' }), v4 $(if ($fpV4 -eq 'yes' -or ($unlocked -and $unlocked.match -eq 'yes')) { 'match' } elseif ($fpV4 -eq 'no' -or ($unlocked -and $unlocked.match -eq 'no')) { 'MISMATCH' } else { 'not read' })" +"RESULT ROW bench-log | $name ($vram MB) | $env:COMPUTERNAME | $date | $mhs MH/s | $watts W | $eff MH/W | $fpNote | $tuned | knee $(if ($knee) { $knee } else { 'n/a' }) | app $appMhs MH/s at $appW W |" +$mb = [ordered]@{ card = "$name ($([math]::Round($vram / 1024)) GB)"; generator = 'v4'; mh_s = $mhs; watts = $watts; mh_per_w = $eff; miner = "installed app $env:IGNEUM_APP_VERSION, class v4 program ($(if ($unlocked) { $unlocked.path } else { 'app row' }))"; date = $date; source = "card-in job on $env:COMPUTERNAME, $date"; by = 'measured by the hash lane (card-in)'; note = "fingerprints: $fpNote; vram $vram MB, dataset fit $(if ($fits) { 'yes' } else { 'no' }); app row $appMhs MH/s at $appW W"; v4_cost = 'class v4 program only'; tuned = $tuned; driver_os = "$(if ($driver) { 'NVIDIA driver ' + $driver + ', ' } else { '' })Windows 11"; hive = [ordered]@{ core_mhz = $(if ($best) { $best.mhz } else { $null }); mem_mhz = $null; pl_w = $null; label = $(if ($best) { "lock $($best.mhz) MHz, $($best.eff) MH/W" } else { 'stock' }) }; group = 'egpu' } +"RESULT ROW miner-bench $($mb | ConvertTo-Json -Compress -Depth 4)" +$rowsOut['locks'] = $lockRows +WriteLast +"RESULT next: $name done on $env:COMPUTERNAME at $(Stamp); the last read now carries it; unplug or plug the next card and say in" +Summary 'done' @{ key = $key; name = $name; vendor = $vendor; vram_mb = $vram; fits = $fits; fp_v5 = $fpV5; fp_v4 = $fpV4; unlocked = $unlocked; locks = $lockRows; knee = $knee; app_mhs = $appMhs; app_w = $appW; restored = $restored } +exit 0 diff --git a/tools/ca3-v4-amend/pc1-amd-cardin-bench.ps1 b/tools/ca3-v4-amend/pc1-amd-cardin-bench.ps1 new file mode 100644 index 000000000..28a31dae3 --- /dev/null +++ b/tools/ca3-v4-amend/pc1-amd-cardin-bench.ps1 @@ -0,0 +1,87 @@ +# Class v5 kit bench on PC 1's RX 9070 XT (7 October 2026, docs/design/class-v5-stored-state.md section 13, "the kit: +# OpenCL (AMD)"): the kit's igneum-worker-opencl.exe (THIS tree's proto-opencl/host.c with the class v5 leaf upload: +# igneum_build(ds, cache, leaves, nLeaves, nItems), the leaves of leaves.bin checked against the pack's FNV-1a 64 first) +# runs --bench-pack on the first class v5 pack, proto-cuda/packs-ca3-v5/v5-dn3-epoch0 (program id e5a4ac5978462156, 11 +# leaves under state root 7e37a9fb..., cache FNV 7334fa46e5d972eb), on the gfx1201 device. Expected: the self-test +# PASS line (cache head, last line and FNV; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes) and the +# fingerprint of the 2^24 outputs at base nonce 0 equal to the Metal reading, 82b19cbde8557ea5 (the M5 Max, 7 October +# 2026, 18:07:09Z). The v4-genesis control pack runs after it so the run has a known class v4 row beside the v5 row. +# Beside the miners (a correctness and fingerprint gate; the rate row is labelled loaded when the card mines): no card is +# switched, nothing is posted to the installed app, nothing is built on the PC. Published by the Counter ASIC coordinator +# only (the PC 1 queue is its); the kit is fetch job $kitId. Every result line starts with RESULT; SUMMARY {json} ends it. +$ErrorActionPreference = 'Continue' +$jobName = 'pc1-amd-cardin-bench' +$cardMatch = $env:IGNEUM_AMD_CARD; if (-not $cardMatch) { $cardMatch = '7600' } +$sizesId = 'fetch-ca3-amd-sizes-20261008' +$kitId = $env:IGNEUM_V5_KIT_ID; if (-not $kitId) { $kitId = 'fetch-ca3-v5-kit-20261008-pc1' } +$expected = '82b19cbde8557ea5' +$started = Get-Date +function Stamp { (Get-Date).ToUniversalTime().ToString('yyyy-MM-ddTHH:mm:ssZ') } +function Summary([string] $status, [hashtable] $extra) { + $o = [ordered]@{ job = $jobName; status = $status; duration_s = [int]((Get-Date) - $started).TotalSeconds; finished_at = (Stamp) } + foreach ($k in $extra.Keys) { $o[$k] = $extra[$k] } + 'SUMMARY ' + ($o | ConvertTo-Json -Compress -Depth 4) +} +"RESULT start $(Stamp) job=$jobName machine=$env:COMPUTERNAME app_version=$env:IGNEUM_APP_VERSION expected_fingerprint=$expected" +$jobs = Split-Path $env:IGNEUM_JOB_DIR +$kit = Join-Path $jobs $kitId +if (-not (Test-Path $kit)) { "RESULT error kit missing at $kit (the fetch job $kitId runs first; republish it after any app update)"; Summary 'failed' @{ error = 'kit missing' }; exit 2 } +$exe = Join-Path $kit 'bin\windows\igneum-worker-opencl.exe' +$packs = Join-Path $kit 'packs' +if (-not (Test-Path $exe)) { "RESULT error worker missing at $exe"; Summary 'failed' @{ error = 'worker missing' }; exit 2 } +"RESULT worker kit $exe sha256 $((Get-FileHash -Algorithm SHA256 $exe).Hash.ToLower()) bytes $((Get-Item $exe).Length)" +$sizes = Join-Path (Join-Path $jobs $sizesId) 'packs' +if (-not (Test-Path $sizes)) { "RESULT error sizes kit missing at $sizes (the fetch job $sizesId runs first)"; Summary 'failed' @{ error = 'sizes kit missing' }; exit 2 } +foreach ($pk in @('v5-dn3-epoch0', 'v4-genesis', 'v3-1g', 'v3-ds29', 'v3-ds30')) { + $d = if ($pk -like 'v3-*') { Join-Path $sizes $pk } else { Join-Path $packs $pk } + if (-not (Test-Path (Join-Path $d 'kernel_bound.cl'))) { "RESULT error pack $pk missing at $d"; Summary 'failed' @{ error = "pack $pk missing" }; exit 2 } + "RESULT pack $pk kernel_bound.cl sha256 $((Get-FileHash -Algorithm SHA256 (Join-Path $d 'kernel_bound.cl')).Hash.ToLower()) program.h sha256 $((Get-FileHash -Algorithm SHA256 (Join-Path $d 'program.h')).Hash.ToLower())" +} +$leaves = Join-Path $packs 'v5-dn3-epoch0\leaves.bin' +if (-not (Test-Path $leaves)) { "RESULT error leaves.bin missing at $leaves (a class v5 pack without its leaves builds nothing)"; Summary 'failed' @{ error = 'leaves missing' }; exit 2 } +"RESULT leaves $leaves bytes $((Get-Item $leaves).Length) sha256 $((Get-FileHash -Algorithm SHA256 $leaves).Hash.ToLower())" +# the OpenCL device index of the 9070 XT (the installed worker's list when present: the app's own indices) +$inst = @("$env:LOCALAPPDATA\Programs\Igneum Miner", "$env:ProgramFiles\Igneum Miner") | Where-Object { Test-Path (Join-Path $_ 'igneum-app.exe') } | Select-Object -First 1 +$listExe = $exe +if ($inst -and (Test-Path (Join-Path $inst 'igneum-worker-opencl.exe'))) { $listExe = Join-Path $inst 'igneum-worker-opencl.exe' } +$list = @(& $listExe --list 2>&1 | ForEach-Object { "$_" }) +$list | ForEach-Object { "RESULT list $_" } +$dev = $null +foreach ($l in $list) { if ($l -match ('^\s*\[(\d+)\].*' + [regex]::Escape($cardMatch)) -and $l -notmatch 'dup') { $dev = [int]$Matches[1]; break } } +if ($null -eq $dev) { foreach ($l in $list) { if ($l -match '^\s*\[(\d+)\].*gfx1200' -and $l -notmatch 'dup') { $dev = [int]$Matches[1]; break } } } +if ($null -eq $dev) { "RESULT error no device matching $cardMatch (or gfx1200) in --list: is the card in its housing and on the bus?"; Summary 'failed' @{ error = 'no card' }; exit 2 } +"RESULT device $dev match=$cardMatch (list from $listExe)" +function Workers { @(Get-CimInstance Win32_Process -Filter "Name = 'igneum-worker-opencl.exe' OR Name = 'igneum-worker-cuda.exe'" -ErrorAction SilentlyContinue | ForEach-Object { "$($_.Name):$($_.ProcessId):[$($_.CommandLine -replace '\s+', ' ')]" }) } +$w = @(Workers) +$loaded = ($w | Where-Object { $_ -match "igneum-worker-opencl.*--device\s+$dev(\s|$)" }).Count -gt 0 +"RESULT workers_before $(Stamp) $($w -join ' ')" +$state = if ($loaded) { 'loaded' } else { 'quiet' } +"RESULT context card_state=$state (a fingerprint gate: the load changes the rate row, never the bytes)" +$rows = @{} +$fpOk = $false +foreach ($pk in @('v5-dn3-epoch0', 'v4-genesis')) { + $d = Join-Path $packs $pk + $t0 = Get-Date + "RESULT bench $pk start $(Stamp) cmd=igneum-worker-opencl.exe --bench-pack --pack $d --device $dev --batch-log2 24 --batches $(if ($pk -like 'v3-*') { 30 } else { 5 })" + $out = @(& $exe --bench-pack --pack $d --device $dev --batch-log2 24 --batches $(if ($pk -like 'v3-*') { 30 } else { 5 }) 2>&1 | ForEach-Object { "$_" }) + $code = $LASTEXITCODE + $secs = [int]((Get-Date) - $t0).TotalSeconds + foreach ($l in $out) { if ($l -match '^(pack |class v5|RESULT |FAIL|error|warm-up)') { "RESULT bench $pk out $l" } } + $res = $out | Where-Object { $_ -match '^RESULT ' } | Select-Object -Last 1 + $fp = ''; $mhs = ''; $check = '' + if ($res -match 'fingerprint=([0-9a-f]{16})') { $fp = $Matches[1] } + if ($res -match 'mhs=([0-9.]+)') { $mhs = $Matches[1] } + if ($res -match 'check=(\w+)') { $check = $Matches[1] } + $rows[$pk] = [ordered]@{ exit = $code; seconds = $secs; fingerprint = $fp; mhs = $mhs; check = $check; card_state = $state } + if ($pk -eq 'v5-dn3-epoch0') { + $fpOk = ($fp -eq $expected -and $check -eq 'PASS') + "RESULT v5 fingerprint=$fp expected=$expected match=$fpOk check=$check mhs=$mhs card_state=$state exit=$code seconds=$secs $(Stamp)" + } elseif ($pk -eq 'v4-genesis') { + "RESULT v4-control fingerprint=$fp check=$check mhs=$mhs card_state=$state exit=$code seconds=$secs $(Stamp)" + } else { + "RESULT size pack=$pk fingerprint=$fp check=$check mhs=$mhs card_state=$state exit=$code seconds=$secs $(Stamp)" + } +} +"RESULT workers_after $(Stamp) $((@(Workers)) -join ' ')" +Summary $(if ($fpOk) { 'done' } else { 'failed' }) @{ expected = $expected; v5 = $rows['v5-dn3-epoch0']; v4_control = $rows['v4-genesis']; device = $dev; kit = $kitId } +exit $(if ($fpOk) { 0 } else { 1 }) diff --git a/tools/ca3-v4-amend/pc1-ca4-packs.ps1 b/tools/ca3-v4-amend/pc1-ca4-packs.ps1 index 776e251fc..5fb63f1ef 100644 --- a/tools/ca3-v4-amend/pc1-ca4-packs.ps1 +++ b/tools/ca3-v4-amend/pc1-ca4-packs.ps1 @@ -17,19 +17,39 @@ function Summary([string] $status, [hashtable] $extra) { $o = [ordered]@{ job = $jobDir = $env:IGNEUM_JOB_DIR; if (-not $jobDir) { $jobDir = Join-Path $env:TEMP 'igneum-ca4-mb' } New-Item -ItemType Directory -Force -Path $jobDir | Out-Null $jobs = Split-Path $jobDir -$packs = Join-Path (Join-Path $jobs 'fetch-ca4-packs-20261007') 'packs' -if (-not (Test-Path $packs)) { "RESULT error packs missing at $packs (the fetch job fetch-ca4-packs-20261007 runs first)"; Summary 'failed' @{ error = 'packs missing' }; exit 2 } +# the class v6 design rows (8 October 2026, an id carrying "v6"): the ca4-v6 kit (today's class v3 x8 and x16, the two re-weighted shadow +# packs, the invention lane's two per-load packs, the controls mx8-genesis and mx8_sh256x27), same shape, label ca4-v6 +$v6 = (Split-Path -Leaf $env:IGNEUM_JOB_DIR) -match 'v6' +$v6b = (Split-Path -Leaf $env:IGNEUM_JOB_DIR) -match 'v6b' +$v6c = (Split-Path -Leaf $env:IGNEUM_JOB_DIR) -match 'v6c' +$rw = (Split-Path -Leaf $env:IGNEUM_JOB_DIR) -match 'readwidth' +$v6d = (Split-Path -Leaf $env:IGNEUM_JOB_DIR) -match 'v6d' +$kitId = if ($v6d) { 'fetch-ca4-v6d-packs-20261008' } elseif ($rw) { 'fetch-ca3-readwidth-20261008' } elseif ($v6c) { 'fetch-ca4-v6c-packs-20261008' } elseif ($v6b) { 'fetch-ca4-v6b-packs-20261008' } elseif ($v6) { 'fetch-ca4-v6-packs-20261008' } else { 'fetch-ca4-packs-20261007' } +$packs = Join-Path (Join-Path $jobs $kitId) 'packs' +if (-not (Test-Path $packs)) { "RESULT error packs missing at $packs (the fetch job $kitId runs first)"; Summary 'failed' @{ error = 'packs missing' }; exit 2 } $inst = @("$env:LOCALAPPDATA\Programs\Igneum Miner", "$env:ProgramFiles\Igneum Miner") | Where-Object { Test-Path (Join-Path $_ 'igneum-worker-cuda.exe') } | Select-Object -First 1 if (-not $inst) { 'RESULT error no installed igneum-worker-cuda.exe'; Summary 'failed' @{ error = 'no worker' }; exit 2 } $exe = Join-Path $inst 'igneum-worker-cuda.exe' +if ($rw -or $v6d) { $kexe = Join-Path (Join-Path $jobs 'fetch-ca3-v5-kit-20261008-pc1') 'bin\windows\igneum-worker-cuda.exe'; if (Test-Path $kexe) { foreach ($dll in (Get-ChildItem (Join-Path $inst '*.dll') -ErrorAction SilentlyContinue)) { if (-not (Test-Path (Join-Path (Split-Path $kexe) $dll.Name))) { Copy-Item $dll.FullName (Split-Path $kexe) -ErrorAction SilentlyContinue } }; $exe = $kexe; "RESULT worker readwidth: the v5 kit's CUDA worker $kexe" } else { 'RESULT error the v5 kit worker is missing on this PC (fetch-ca3-v5-kit-20261008-pc1)'; Summary 'failed' @{ error = 'no v5 worker' }; exit 2 } } # mx8_shl256x27 is the research lane's first per-load export (id 854050a4293f0615, the known-failed record: 11 percent duplicate reads from a lossy # base writer under the sub-blocks) and mx8_shl256x27_v2 its fix (counter-asic-4 2f718001, attempt 3, id bd64b207a30413fb); both run and every row # names its pack directory and the program id read from its program.json. 22:44 UTC: the research lane's acceptance rule, judging the per-load # class in execution order, refuses the 16 x 27 construction on every attempt, so neither per-load export is a candidate class; both rows # still run as the energy reading of the placement and carry construction=unsound-energy-reading-only $packOrder = @('mx8-genesis', 'mx8_sh256x27', 'mx8_shl256x27', 'mx8_shl256x27_v2', 'mx8_mm128', 'mx8_mm512', 'mx8_mm1430') +if ($v6) { $packOrder = @('mx8-genesis', 'mx8_sh256x27', 'v3-x8-today', 'v3-x16-today', 'mix-mulheavy', 'mix-shflheavy', 'mx8_shl4096x1', 'mx8_shl2304x3', 'v3-ds29', 'v3-ds30', 'v3-ds31') } +if ($v6b) { $packOrder = @('mix-shflheavy', 'v3-ds29', 'v3-ds30', 'v3-ds31', 'v3-x16-g2', 'v3-x8-g2') } +if ($v6c) { $packOrder = @('mix-mulheavy') } +# the read-width rows (the floor programme, 8 October 2026): W = 4, 8 and 16 words under the class v5 state term (each its own draw), the +# pinned v5-genesis pack as the reference; the w64 pack also at 2, 4 and 8 warps per block in the unlocked state (the best lane count) +if ($rw) { $packOrder = @('v5-genesis', 'rw-w4', 'rw-w32', 'rw-w64', 'rw5-w4', 'rw5-w64') } +# kit d (8 October 2026, the class v6 close): the two weight tables inside the shadow block, and floor lane 5's read-width rows (the 5 October +# w4 control, the w64 pack, the hinted w64-l2 pack: the first uint4 load of each item as ld.global.L2::64B, fingerprint 836e56e7) +if ($v6d) { $packOrder = @('mix-mulheavy-sh', 'mix-shflheavy-sh', 'rw5-w4', 'rw5-w64', 'rw5-w64-l2') } +# the two w64 packs (the v5-state one and the 5 October class v2 one, fingerprint 836e56e7) at 1, 2, 4 and 8 warps per block unlocked and at 1 and 4 at the lock +function WarpsFor([string] $pk, [string] $state) { if ($rw -and $pk -like '*w64*') { if ($state -eq 'unlocked') { @(1, 2, 4, 8) } else { @(1, 4) } } else { @(1) } } foreach ($pk in $packOrder) { $d = Join-Path $packs $pk; if (-not (Test-Path $d)) { "RESULT error pack missing at $d"; Summary 'failed' @{ error = "pack $pk missing" }; exit 2 }; foreach ($f in (Get-ChildItem $d -File | Sort-Object Name)) { "RESULT kitfile $pk/$($f.Name) sha256 $((Get-FileHash -Algorithm SHA256 $f.FullName).Hash.ToLower())" } } -"RESULT start $(Stamp) job=$jobName exe=$exe sha256=$((Get-FileHash -Algorithm SHA256 $exe).Hash.ToLower()) label=ca4-research" +"RESULT start $(Stamp) job=$jobName exe=$exe sha256=$((Get-FileHash -Algorithm SHA256 $exe).Hash.ToLower()) label=$(if ($v6) { 'ca4-v6' } else { 'ca4-research' })" $smi = (Get-Command nvidia-smi -ErrorAction SilentlyContinue).Source if (-not $smi) { foreach ($p in @((Join-Path $env:ProgramFiles 'NVIDIA Corporation\NVSMI\nvidia-smi.exe'), (Join-Path $env:SystemRoot 'System32\nvidia-smi.exe'))) { if (Test-Path $p) { $smi = $p; break } } } $row = @(& $smi --query-gpu=index,name,uuid,pci.bus_id --format=csv,noheader 2>&1 | ForEach-Object { "$_" }) | Where-Object { $_ -match 'RTX 5090' } | Select-Object -First 1 @@ -84,11 +104,11 @@ function ParseUtc([string] $s) { try { return [datetime]::Parse($s, [cultureinfo function RunState([string] $state) { $env:CUDA_VISIBLE_DEVICES = $uuid "RESULT packs-state $state start $(Stamp) $((& $smi -i $idx --query-gpu=clocks.sm,clocks.applications.graphics,power.draw --format=csv,noheader 2>&1 | Out-String).Trim())" - foreach ($pk in $packOrder) { + foreach ($pk in $packOrder) { foreach ($bw in (WarpsFor $pk $state)) { $d = Join-Path $packs $pk $cls = ''; $progId = ''; try { $pj = Get-Content -LiteralPath (Join-Path $d 'program.json') -Raw | ConvertFrom-Json; $cls = [string] $pj.load_class; $progId = [string] $pj.program_id } catch { } $t0 = Get-Date - $lines = @(& $exe --bench --pack $d --batches 250 --batch-log2 24 --block-warps 1 --device 0 2>&1 | ForEach-Object { "$_" }) + $lines = @(& $exe --bench --pack $d --batches 250 --batch-log2 24 --block-warps $bw --device 0 2>&1 | ForEach-Object { "$_" }) $rc = $LASTEXITCODE $t1 = Get-Date $res = $lines | Where-Object { $_ -match '^RESULT pack=' } | Select-Object -First 1 @@ -101,9 +121,9 @@ function RunState([string] $state) { $eff = if ($watts -and $mhs) { [math]::Round([double]$mhs / $watts, 4) } else { '' } $err = ''; if (-not $res -or $rc -ne 0) { $e = ($lines | Where-Object { $_ -match 'FAIL|error|MISMATCH|compile' } | Select-Object -First 1); $err = if ($e) { ($e -replace '\s+', ' ') } else { "exit $rc, no RESULT line" } } $tag = if ($pk -like 'mx8_shl256x27*') { ' construction=unsound-energy-reading-only' } else { '' } - "RESULT ca4-research pack=$pk dir=$d program_id=$progId class=$cls$tag state=$state mhs=$mhs watts=$watts watts_instant=$wi watts_average=$wa mh_per_w=$eff sm_mhz=$sm mem_mhz=$mem util=$util fingerprint=$fp check=$check exit=$rc wall_s=$([int]($t1 - $t0).TotalSeconds) samples=$($w.Count) error=$err" + "RESULT ca4-research pack=$pk dir=$d program_id=$progId class=$cls$tag state=$state warps=$bw mhs=$mhs watts=$watts watts_instant=$wi watts_average=$wa mh_per_w=$eff sm_mhz=$sm mem_mhz=$mem util=$util fingerprint=$fp check=$check exit=$rc wall_s=$([int]($t1 - $t0).TotalSeconds) samples=$($w.Count) error=$err" Start-Sleep -Seconds 3 - } + } } "RESULT packs-state $state end $(Stamp)" } $locked = $false diff --git a/tools/ca3-v4-amend/pc1-publish-20261007.sh b/tools/ca3-v4-amend/pc1-publish-20261007.sh index 018ea5404..65cbdd323 100755 --- a/tools/ca3-v4-amend/pc1-publish-20261007.sh +++ b/tools/ca3-v4-amend/pc1-publish-20261007.sh @@ -44,6 +44,26 @@ case "$STEP" in family) $P add --kind run --target ae432dc7 --id run-ca3-pc1-amd-family-20261007-e --cards-off amd:gfx1201 --script tools/ca3-v4-amend/pc1-amd-family-20261007.ps1 --timeout-minutes 20 --title "CA3 PC 1: item 6 family step costs on the 9070 XT (run e, the card alone)" --expires-hours 36 $DEPLOY ;; tune-5080) $P add --kind run --target ae432dc7 --id run-ca3-pc1-ember-5080-20261007 --script tools/ca3-v4-amend/pc1-ember-card.ps1 --timeout-minutes 35 --title "CA3 PC 1: Ember Tune on the RTX 5080 (the installed app tunes the one card)" --expires-hours 36 $DEPLOY ;; tune-9070) $P add --kind run --target ae432dc7 --id run-ca3-pc1-ember-9070-20261007 --script tools/ca3-v4-amend/pc1-ember-card.ps1 --timeout-minutes 35 --title "CA3 PC 1: Ember Tune pass on the RX 9070 XT (set or measure-only by the probe)" --expires-hours 36 $DEPLOY ;; + card-in-pc1) $P add --kind run --target ae432dc7 --id "run-card-in-pc1-$(date -u +%Y%m%dT%H%M)" --script tools/ca3-v4-amend/pc-card-in.ps1 --timeout-minutes 55 --title "card-in: the newly plugged eGPU card on PC 1, the full pass (fingerprints, rate and watts, the lock grid where the lever exists, the rows); no new card = nothing done" --expires-hours 12 $DEPLOY ;; + card-in-pc2) $P add --kind run --target 1ccfe586 --id "run-card-in-pc2-$(date -u +%Y%m%dT%H%M)" --script tools/ca3-v4-amend/pc-card-in.ps1 --timeout-minutes 55 --title "card-in: the newly plugged eGPU card on PC 2, the full pass (fingerprints, rate and watts, the lock grid where the lever exists, the rows); no new card = nothing done" --expires-hours 12 $DEPLOY ;; + kit-pc2) $P add --kind fetch --target 1ccfe586 --id fetch-ca3-v4-sub3-pc2-20261007 --file "$KITS/igneum-ca3-v4-sub3-pc1-kit.zip" --dir jobs --extract --title "CA3 PC 2: the sub-version 3 kit (worker, 13 packs) for the card-in CUDA rows" --expires-hours 36 $DEPLOY ;; + arc-kit) $P add --kind fetch --target 1ccfe586 --id fetch-ca3-v5-kit-20261008 --file "$KITS/igneum-ca3-v5-kit-20261008.zip" --dir jobs --extract --title "Class v5 kit rebuilt with the Intel rotate-fold fix (tree 8f481459; worker 55722527...)" --expires-hours 36 $DEPLOY ;; + arc-v5) $P add --kind run --target 1ccfe586 --id run-ca3-pc2-v5-intel-bench-20261008 --script "$KITS/arc-v5-bench-c0d398a1.ps1" --timeout-minutes 15 --title "Class v5 kit fingerprint on PC 2 Arc B580, the rotate-fold kit (the v5 lane's script c0d398a1, whole stdout kept; lock-free, quiet, nothing installed)" --expires-hours 12 $DEPLOY ;; + v5kit-pc1) $P add --kind fetch --target ae432dc7 --id fetch-ca3-v5-kit-20261008-pc1 --file "$KITS/igneum-ca3-v5-kit-20261008.zip" --dir jobs --extract --title "Class v5 kit (rotate-fold build, tree 8f481459) on PC 1 for the v5 against v4 lock rows" --expires-hours 36 $DEPLOY ;; + v5lock-5090) $P add --kind run --target ae432dc7 --id run-ca3-pc1-v5lock-5090-20261008-b --cards-off "nvidia:NVIDIA GeForce RTX 5090" --script tools/ca3-v4-amend/pc1-v4-efficiency.ps1 --timeout-minutes 30 --title "Class v5 against class v4 on the RTX 5090 at unlocked, 1,300 and 1,200 MHz (the v5 kit's CUDA packs, 60 s rows, the helper's cleared sequence, the card alone)" --expires-hours 12 $DEPLOY ;; + v5lock-5080) $P add --kind run --target ae432dc7 --id run-ca3-pc1-v5lock-5080-20261008 --cards-off "nvidia:NVIDIA GeForce RTX 5080" --script tools/ca3-v4-amend/pc1-v4-efficiency.ps1 --timeout-minutes 30 --title "Class v5 against class v4 on the RTX 5080 at unlocked, 1,100 and 1,000 MHz (the v5 kit's CUDA packs, 60 s rows, the helper's cleared sequence, the card alone)" --expires-hours 12 $DEPLOY ;; + v6-kit) $P add --kind fetch --target ae432dc7 --id fetch-ca4-v6-packs-20261008 --file "$KITS/igneum-ca4-v6-packs-20261008.zip" --dir jobs --extract --title "Class v6 design rows: today's class v3 x8 and x16, two re-weighted shadow packs, the invention lane's two per-load packs, the two controls" --expires-hours 36 $DEPLOY ;; + v6-packs) $P add --kind run --target ae432dc7 --id run-ca4-pc1-v6-packs-5090-20261008 --cards-off "nvidia:NVIDIA GeForce RTX 5090" --script tools/ca3-v4-amend/pc1-ca4-packs.ps1 --timeout-minutes 60 --title "Class v6 design rows on the RTX 5090 alone: eleven packs (the class v3 pack at 2, 4 and 8 GiB datasets among them) at unlocked and the 1,300 MHz lock (self-test, 2^24 fingerprint, MH/s, W), label ca4-v6" --expires-hours 12 $DEPLOY ;; + v6b-kit) $P add --kind fetch --target ae432dc7 --id fetch-ca4-v6b-packs-20261008 --file "$KITS/igneum-ca4-v6b-packs-20261008.zip" --dir jobs --extract --title "Class v6 design rows, kit b: the byte-seed re-exports (x8 and x16 on generator 2 with the era, the re-weighted tables, the pinned class v3 program at 2, 4 and 8 GiB)" --expires-hours 36 $DEPLOY ;; + v6b-packs) $P add --kind run --target ae432dc7 --id run-ca4-pc1-v6b-packs-5090-20261008 --cards-off "nvidia:NVIDIA GeForce RTX 5090" --script tools/ca3-v4-amend/pc1-ca4-packs.ps1 --timeout-minutes 45 --title "Class v6 design rows, kit b, on the RTX 5090 alone at unlocked and the 1,300 MHz lock, label ca4-v6" --expires-hours 12 $DEPLOY ;; + v6c-kit) $P add --kind fetch --target ae432dc7 --id fetch-ca4-v6c-packs-20261008 --file "$KITS/igneum-ca4-v6c-packs-20261008.zip" --dir jobs --extract --title "Class v6 design rows, kit c: the multiply-heavy weight table (byte-seed form)" --expires-hours 36 $DEPLOY ;; + v6c-packs) $P add --kind run --target ae432dc7 --id run-ca4-pc1-v6c-packs-5090-20261008 --cards-off "nvidia:NVIDIA GeForce RTX 5090" --script tools/ca3-v4-amend/pc1-ca4-packs.ps1 --timeout-minutes 20 --title "Class v6 design rows, kit c (the multiply-heavy table) on the RTX 5090 alone at unlocked and the 1,300 MHz lock, label ca4-v6" --expires-hours 12 $DEPLOY ;; + rw-kit) $P add --kind fetch --target ae432dc7 --id fetch-ca3-readwidth-20261008 --file "$KITS/igneum-ca3-readwidth-20261008.zip" --dir jobs --extract --title "The floor programme's read-width packs: W = 4, 8 and 16 words under the class v5 state term, the v5-genesis reference" --expires-hours 36 $DEPLOY ;; + rw-packs) $P add --kind run --target ae432dc7 --id run-ca3-pc1-readwidth-5090-20261008 --cards-off "nvidia:NVIDIA GeForce RTX 5090" --script tools/ca3-v4-amend/pc1-ca4-packs.ps1 --timeout-minutes 45 --title "Read width on the RTX 5090 alone: W = 4, 8, 16 words (the v5 state term), the w64 pack at 1, 2, 4, 8 warps per block, unlocked and at the 1,300 MHz lock; label ca4-v6" --expires-hours 12 $DEPLOY ;; + v6d-kit) $P add --kind fetch --target ae432dc7 --id fetch-ca4-v6d-packs-20261008 --file "$KITS/igneum-ca4-v6d-packs-20261008.zip" --dir jobs --extract --title "Class v6 close, kit d: the two weight tables inside the shadow block; floor lane 5's w4, w64 and hinted w64-l2 packs" --expires-hours 36 $DEPLOY ;; + v6d-packs) $P add --kind run --target ae432dc7 --id run-ca4-pc1-v6d-packs-5090-20261008 --cards-off "nvidia:NVIDIA GeForce RTX 5090" --script tools/ca3-v4-amend/pc1-ca4-packs.ps1 --timeout-minutes 40 --title "Class v6 close, kit d, on the RTX 5090 alone: the shadow-block weight tables, and w4 against w64 and the hinted w64-l2 at 1, 2, 4, 8 warps unlocked and 1, 4 at the 1,300 MHz lock; label ca4-v6" --expires-hours 12 $DEPLOY ;; + amd-sizes-kit) $P add --kind fetch --target ae432dc7 --id fetch-ca3-amd-sizes-20261008 --file "$KITS/igneum-ca3-amd-sizes-20261008.zip" --dir jobs --extract --title "The 8 GB tier's dataset rows: the pinned class v3 program at 1, 2 and 4 GiB (OpenCL)" --expires-hours 36 $DEPLOY ;; + amd-cardin) $P add --kind run --target ae432dc7 --id "run-ca3-pc1-amd-cardin-$(date -u +%Y%m%dT%H%M)" --script tools/ca3-v4-amend/pc1-amd-cardin-bench.ps1 --timeout-minutes 30 --title "RX 7600 card-in: the class v5 and v4 fingerprints and the dataset rows at 1, 2 and 4 GiB on the OpenCL kit worker, beside the miners" --expires-hours 12 $DEPLOY ;; read) node tools/jobs.mjs "$1" --all ;; *) sed -n 2,12p "$0"; exit 2 ;; esac diff --git a/tools/ca3-v4-amend/pc1-v4-efficiency.ps1 b/tools/ca3-v4-amend/pc1-v4-efficiency.ps1 index 2b8b62519..c10b23b41 100644 --- a/tools/ca3-v4-amend/pc1-v4-efficiency.ps1 +++ b/tools/ca3-v4-amend/pc1-v4-efficiency.ps1 @@ -25,6 +25,10 @@ $ErrorActionPreference = 'Continue' $jobName = 'pc1-v4-efficiency' $kitId = 'fetch-ca3-v4-sub3-pc1-20261007' +# the class v5 against class v4 mode (8 October 2026, main's order at 10:4x UK, an id carrying "v5lock"): the v5 kit's CUDA packs (v4-genesis, +# v5-genesis, v5-dn3-epoch0, the same epoch seed for the first two) at unlocked, 1,300 and 1,200 MHz, 60 s rows; the 5080 at 1,100 and 1,000 +$v5lock = (Split-Path -Leaf $env:IGNEUM_JOB_DIR) -match 'v5lock' +if ($v5lock) { $kitId = 'fetch-ca3-v5-kit-20261008-pc1' } $started = Get-Date $deadline = $started.AddMinutes(66) function Stamp { (Get-Date).ToUniversalTime().ToString('yyyy-MM-ddTHH:mm:ssZ') } @@ -39,6 +43,7 @@ $jobId = Split-Path -Leaf $jobDir $cardName = if ($jobId -match '5080') { 'NVIDIA GeForce RTX 5080' } else { 'NVIDIA GeForce RTX 5090' } $expected = @{ 'mx8-devnet-epoch0' = '90f794dd556f7a3b'; 'v4-devnet-epoch0' = 'e370fb2080b7dbb1' } $packOrder = @('v4-devnet-epoch0', 'mx8-devnet-epoch0') +if ($v5lock) { $expected = @{ 'v4-genesis' = '892b6d55a7ddcfcb'; 'v5-dn3-epoch0' = '82b19cbde8557ea5'; 'v5-genesis' = '' }; $packOrder = @('v4-genesis', 'v5-genesis', 'v5-dn3-epoch0') } # the grid by the job id: an id carrying "floor" runs the second pass, 1,400 MHz down to the driver's floor in 100 MHz steps (the # first pass found the best MH/W at its lowest lock, 1,400, so the knee sits below it); a lock the driver clamps shows in sm_mhz # the counter-asic-4 research mode (an id carrying "ca4sparse"): the research lane's SM-sparse worker variants (proto-cuda/nvrtc/worker.cpp on @@ -48,7 +53,7 @@ $packOrder = @('v4-devnet-epoch0', 'mx8-devnet-epoch0') # label=ca4-research and the worker's race line verbatim; nothing in any pack changes, the fingerprint is checked on every row $ca4 = $jobId -match 'ca4sparse' $variants = if ($ca4) { @('base', 'sp170-w32', 'sp85-w32', 'sp43-w32', 'sp21-w32', 'sp11-w32') } else { @('base') } -$locks = if ($ca4) { @(1300) } elseif ($jobId -match '5080') { @(2850, 2781, 2700, 2550, 2472, 2400, 2250, 2163, 2100, 1950, 1854, 1800, 1650, 1500, 1400, 1300, 1200, 1100, 1000, 900, 800, 700, 600, 500, 400, 300) } elseif ($jobId -match 'floor2') { @(1100, 1000, 900, 800, 700, 600, 500, 400, 300) } elseif ($jobId -match 'floor') { @(1400, 1300, 1200, 1100, 1000, 900, 800, 700, 600, 500, 400, 300) } else { @(2850, 2781, 2700, 2550, 2472, 2400, 2250, 2163, 2100, 1950, 1854, 1800, 1650, 1500, 1400) } +$locks = if ($v5lock -and $jobId -match '5080') { @(1100, 1000) } elseif ($v5lock) { @(1300, 1200) } elseif ($ca4) { @(1300) } elseif ($jobId -match '5080') { @(2850, 2781, 2700, 2550, 2472, 2400, 2250, 2163, 2100, 1950, 1854, 1800, 1650, 1500, 1400, 1300, 1200, 1100, 1000, 900, 800, 700, 600, 500, 400, 300) } elseif ($jobId -match 'floor2') { @(1100, 1000, 900, 800, 700, 600, 500, 400, 300) } elseif ($jobId -match 'floor') { @(1400, 1300, 1200, 1100, 1000, 900, 800, 700, 600, 500, 400, 300) } else { @(2850, 2781, 2700, 2550, 2472, 2400, 2250, 2163, 2100, 1950, 1854, 1800, 1650, 1500, 1400) } $stepSeconds = 60 "RESULT start $(Stamp) job=$jobName job_id=$jobId card=$cardName grid=[$($locks -join ' ')] machine=$env:COMPUTERNAME app_version=$env:IGNEUM_APP_VERSION" 'RESULT lever voltage: nvidia-smi exposes no voltage offset (NVAPI only); the clock lock (-lgc) moves the card along the driver V/F curve, so the voltage falls with the lock; the power cap (-pl) is the other driver lever and is not moved here' @@ -67,6 +72,9 @@ foreach ($pk in $packOrder) { $d = Join-Path $packs $pk; if (-not (Test-Path $d) $inst = @("$env:LOCALAPPDATA\Programs\Igneum Miner", "$env:ProgramFiles\Igneum Miner") | Where-Object { Test-Path (Join-Path $_ 'igneum-worker-cuda.exe') } | Select-Object -First 1 if (-not $inst) { 'RESULT error no installed igneum-worker-cuda.exe'; Summary 'failed' @{ error = 'no worker' }; exit 2 } $exe = Join-Path $inst 'igneum-worker-cuda.exe' +# the v5lock mode runs the v5 kit's own CUDA worker (generator 5 packs: the installed 0.3.20 worker answers "generator 5 is not a generator +# version this worker runs (2, 3 or 4)", the first run of 10:55 UK); its DLLs are the installed app's, copied beside it +if ($v5lock) { $kexe = Join-Path $kit 'bin\windows\igneum-worker-cuda.exe'; if (Test-Path $kexe) { foreach ($dll in (Get-ChildItem (Join-Path $inst '*.dll') -ErrorAction SilentlyContinue)) { if (-not (Test-Path (Join-Path (Split-Path $kexe) $dll.Name))) { Copy-Item $dll.FullName (Split-Path $kexe) -ErrorAction SilentlyContinue } }; $exe = $kexe; "RESULT worker v5lock: the kit's CUDA worker $kexe sha256 $((Get-FileHash -Algorithm SHA256 $kexe).Hash.ToLower())" } else { 'RESULT error the v5 kit has no windows CUDA worker'; Summary 'failed' @{ error = 'no v5 cuda worker' }; exit 2 } } if ($ca4) { # the research lane's exe with the race fix (counter-asic-4 after 2d0013d1, 00:46 UTC; the first exe parsed --variant and never applied it: # every row of the 00:22Z run read "variant base"); the rows carry its variant= and sparse_blocks= fields and any variant_not_installed line diff --git a/tools/ci/README.md b/tools/ci/README.md index 2e15aace5..4316d6241 100644 --- a/tools/ci/README.md +++ b/tools/ci/README.md @@ -10,6 +10,7 @@ | the red watcher fires on cancelled and timed-out runs too (`ci-red.yml`, `red-watch.mjs`) | The watcher's `if` missing any of failure, cancelled, timed_out, or the conclusion not handed to the record step (the self-test reads the workflow file); the line names the kind: CI red, CI cancelled, CI timed out. | 7 October 2026 | | gh's active account is the stored Igneum entry (`gh-account-check.sh`, in Igneum's own gh directory `~/.config/gh-igneum` through `gh-env.sh`, never the founder's) | A push or a landing from this Mac while Igneum's gh directory names any other account as active, or none (the refusal names the one step: the founder or main stores the Igneum token there with `GH_CONFIG_DIR=~/.config/gh-igneum gh auth login --with-token`; no lane does); skipped with a line while `github-suspended` stands. RULE: no lane switches gh accounts on this Mac, ever; the second owner's login belongs to other projects and must never touch Igneum; the stored entry's name is in ~/.config/igneum/gh-user, never in the repository. | 7 October 2026, 21:41 UK: a lane switched gh to the other login during the suspension; nobody could say which | +| no landing on the public host while the marker stands (`pre-push.sh` `forgejo_master_frozen`, `merge-to-master.sh` `forgejo_master_refusal`); the hook binds every remote rule to the remote's URL | A push of master to git.igneum.network, or a `--remote` naming it, while `tools/ci/github-suspended` stands: its master is a rewritten copy replaced at cut-over, so the landing would be lost (a branch pushed there for safekeeping passes). Before the fix the hook matched the remote NAME, so `git push origin master` bound neither the GitHub refusal nor the CI rule; the self-test now drives the hook by name through a fixture repo. Also: `gate-manifest-check.sh` and four other pipefail checks no longer pipe a file-sized producer into `grep -q` (GNU sed took SIGPIPE on an early match and the check read it as a missing run line on the Linux runners and boxes); `mirror_master` fast-forwards every box with a build-server file after a landing on ANY remote (before, only a GitHub landing fanned out, so a box landing left build-3 and build-4 at a tip 23 hours old), as a `--no-verify` copy of the master the gate already passed (a stale mirror had re-run the full gate for six minutes per box) | 8 Oct 2026 | | kill by exact command or pid file (owed as a check) | 6 October 2026, 21:09Z: a Mac-side `pkill -f ` matched nothing (the log name was a redirect, not part of the command line), the roll-everything script lived on and wiped a box it had been told to hold. Rule: a job is stopped by its pid file (`tools/fleet/fleet-bg.sh start|stop `) or by a pattern anchored on its exact command line (`^python3 -u /root/fleet/in/box-prover.py`), never by a word that may or may not appear in it. The check that flags a `pkill -f`/`pgrep -f` whose literal is a path or a name that never starts a command line is owed to the CI lane | diff --git a/tools/ci/export-exclude.txt b/tools/ci/export-exclude.txt index c2b651bfc..498b5025b 100644 --- a/tools/ci/export-exclude.txt +++ b/tools/ci/export-exclude.txt @@ -26,3 +26,5 @@ docs/plans/cryptanalysis # 8 October 2026: the class v6 research lanes (the hardware future, the rotating-family research): internal research written # for the founder on the chip model, quoting the operations record; the public text is whatever main lands from the synthesis. docs/analysis/class-v6 +# 8 October 2026: the miner window audit (an internal design record: the founder's order, lane ids, the build plan) +docs/design/app-audit-2026-10-08.md diff --git a/tools/ci/gate-manifest-check.sh b/tools/ci/gate-manifest-check.sh index 1f8d83d32..0ece6b7fc 100755 --- a/tools/ci/gate-manifest-check.sh +++ b/tools/ci/gate-manifest-check.sh @@ -14,9 +14,13 @@ set -euo pipefail HERE="$(cd "$(dirname "$0")" && pwd)" names_in() { grep -E '^[[:space:]]+run "' "$1" | sed -E 's/^[[:space:]]+run "([^"]+)".*/\1/'; } compare() { # -> exit 1 with the lines - local gate="$1" manifest="$2" rc=0 n - while IFS= read -r n; do [ -n "$n" ] || continue; names_in "$gate" | grep -qxF -- "$n" || { echo "gate-manifest: listed check has no run line in $(basename "$gate"): $n" >&2; rc=1; }; done < <(grep -vE '^\s*(#|$)' "$manifest") - while IFS= read -r n; do [ -n "$n" ] || continue; grep -qxF -- "$n" "$manifest" || { echo "gate-manifest: run line not in $(basename "$manifest"): $n" >&2; rc=1; }; done < <(names_in "$gate") + local gate="$1" manifest="$2" rc=0 n names + # the names once, matched through a here-string: `names_in | grep -q` under pipefail reads a SIGPIPE on sed (grep -q closing + # the pipe on an early match before sed has written the rest) as "no run line"; GNU sed on the runners and the boxes hit it on + # the first forty names, BSD sed on the Mac never did (8 October 2026, 13:5x UK, a research lane's gate on build-3) + names=$(names_in "$gate") + while IFS= read -r n; do [ -n "$n" ] || continue; grep -qxF -- "$n" <<<"$names" || { echo "gate-manifest: listed check has no run line in $(basename "$gate"): $n" >&2; rc=1; }; done < <(grep -vE '^\s*(#|$)' "$manifest") + while IFS= read -r n; do [ -n "$n" ] || continue; grep -qxF -- "$n" "$manifest" || { echo "gate-manifest: run line not in $(basename "$manifest"): $n" >&2; rc=1; }; done <<<"$names" return $rc } case "${1:-}" in diff --git a/tools/ci/merge-to-master.sh b/tools/ci/merge-to-master.sh index 54d5263ea..f85a70913 100755 --- a/tools/ci/merge-to-master.sh +++ b/tools/ci/merge-to-master.sh @@ -42,6 +42,14 @@ github_suspended_refusal() { # : prints the refusal and returns 0 when echo "merge-to-master: REFUSED. GitHub is unreachable ($(grep -E '^suspended-since' "$SUSPENDED_FILE" | head -1); tools/ci/github-suspended stands): nothing is pushed, fetched or polled there. Land on the box mirror: tools/ci/merge-to-master.sh --remote box (or MERGE_REMOTE=box). Main removes the marker at the cut-over." >&2 return 0 } +forgejo_master_refusal() { # : prints the refusal and returns 0 when the remote is the public Forgejo host and the marker stands + # (its master is a rewritten copy replaced at cut-over by the rewrite of the box mirror's final tip; main's word, 8 October 2026, 13:34 UK) + local host="${IGNEUM_PUBLIC_GIT_HOST:-git.igneum.network}" + [ -f "$SUSPENDED_FILE" ] || return 1 + case "$(git remote get-url "$1" 2>/dev/null)" in *"$host"*) ;; *) return 1 ;; esac + echo "merge-to-master: REFUSED. $host holds a rewritten copy; its master is replaced at cut-over by the rewrite of the box mirror's final tip, so a landing there is lost. Land on the box mirror: tools/ci/merge-to-master.sh --remote box" >&2 + return 0 +} CI_STATE="${CI_STATE_CMD:-node tools/ci/ci-state.mjs}" # the self-test swaps in a fake clock() { TZ=Europe/London date '+%H:%M %Z'; } @@ -81,11 +89,17 @@ master_gate() { # a4bca198 while GitHub's carried cf7d6ccb, and three branches were cut from the stale tip; the mirrors only ever received what a # build happened to push). One push per mirror in IGNEUM_MIRRORS (default: both box files), fast-forward only, best effort: a mirror # that is down prints a line and never fails the landing. -mirror_master() { # - local sha="$1" m host key="${BS_KEY:-$HOME/.ssh/igneum_ed25519}" list="${IGNEUM_MIRRORS:-}" - if [ -z "$list" ]; then for f in "$HOME/.config/igneum/build-server" "$HOME/.config/igneum/build-server-2"; do [ -s "$f" ] && list="$list $(head -1 "$f" | tr -d '[:space:]'):/srv/igneum.git"; done; fi +mirror_master() { # [landed-remote-url]: the landed master to every other mirror + local sha="$1" landed="${2:-}" m host key="${BS_KEY:-$HOME/.ssh/igneum_ed25519}" list="${IGNEUM_MIRRORS:-}" + # every box with a build-server file (8 October 2026, 13:5x UK: build-3 and build-4's mirrors sat at 7 October 15:27 with only the first two listed) + if [ -z "$list" ]; then for f in "$HOME/.config/igneum/build-server" "$HOME"/.config/igneum/build-server-[0-9]*; do [ -s "$f" ] && list="$list $(head -1 "$f" | tr -d '[:space:]'):/srv/igneum.git"; done; fi for m in $list; do - if GIT_SSH_COMMAND="ssh -i $key -o BatchMode=yes -o ConnectTimeout=10" git push -q "$m" "$sha:refs/heads/master" 2>/dev/null; then echo "merge-to-master: mirror $m master -> ${sha:0:8}" + host="${m#*@}"; host="${host%%:*}"; host="${host%%/*}" # build@:/srv/igneum.git -> ; the landed URL may be ssh://build@/srv/igneum.git + key="$host"; [ -n "$key" ] || key="${m#file://}" # a bare-path mirror (the self-test) is known by its path + if [ -n "$landed" ]; then case "$landed" in *"$key"*) continue ;; esac; fi # the mirror that took the landing itself (8 October 2026, 14:19 UK: the host:/path form never matched the ssh:// URL) + # --no-verify: this is a copy of a master the gate already passed on landing (the sha is the landed remote's master, read back), + # not a landing; with the hook on, a stale mirror re-ran the full gate for six minutes per box (8 October 2026, 14:0x UK) + if GIT_SSH_COMMAND="ssh -i $key -o BatchMode=yes -o ConnectTimeout=10" git push -q --no-verify "$m" "$sha:refs/heads/master" 2>/dev/null; then echo "merge-to-master: mirror $m master -> ${sha:0:8}" else echo "merge-to-master: mirror $m did not take master ${sha:0:8} (down, or not a fast-forward); the next landing tries again"; fi done } @@ -99,6 +113,11 @@ if [ "$SELF_TEST" = 1 ]; then case "$out" in *"REFUSED. GitHub is unreachable"*"--remote box"*) ;; *) echo "self-test failed: the refusal did not name the switch: $out"; fails=1 ;; esac ( SUSPENDED_FILE="$d/marker"; github_suspended_refusal box >/dev/null 2>&1 ) && { echo "self-test failed: the box mirror remote was refused under the marker"; fails=1; } ( SUSPENDED_FILE="$d/no-marker"; github_suspended_refusal origin >/dev/null 2>&1 ) && { echo "self-test failed: a GitHub remote was refused without the marker"; fails=1; } + # the public Forgejo host takes no landing while the marker stands; the box mirror does (a fixture repo with both remotes) + mkdir -p "$d/pub" && git -C "$d/pub" init -q && git -C "$d/pub" remote add pub ssh://git@git.igneum.network:2222/igneum-network/igneum.git && git -C "$d/pub" remote add box ssh://build@188.40.146.49/srv/igneum.git + ( cd "$d/pub" && SUSPENDED_FILE="$d/marker" forgejo_master_refusal pub >/dev/null 2>&1 ) || { echo "self-test failed: the public host was not refused as a landing target under the marker"; fails=1; } + ( cd "$d/pub" && SUSPENDED_FILE="$d/no-marker" forgejo_master_refusal pub >/dev/null 2>&1 ) && { echo "self-test failed: the public host was refused without the marker"; fails=1; } + ( cd "$d/pub" && SUSPENDED_FILE="$d/marker" forgejo_master_refusal box >/dev/null 2>&1 ) && { echo "self-test failed: the box mirror was refused as the public host"; fails=1; } # the fake answers from $d/answer- (one line per call, consumed top to bottom; the last line repeats) and $d/answer-master cat > "$fake" <<'FAKE' #!/usr/bin/env bash @@ -149,6 +168,9 @@ success 4 u push run git clone -q --bare "$d/src" "$d/mirror.git" && ( cd "$d/mirror.git" && git update-ref refs/heads/master "$(git rev-parse master~1)" ) tip=$(git -C "$d/src" rev-parse master) out=$( cd "$d/src" && IGNEUM_MIRRORS="$d/mirror.git" mirror_master "$tip" ) + grep -qE '^ mirror_master "\$\(git rev-parse "\$REMOTE/master"\)"' "$0" || { echo "self-test failed: the landing path does not fan master out to the mirrors for every remote"; fails=1; } + out2=$( cd "$d/src" && IGNEUM_MIRRORS="$d/mirror.git" mirror_master "$tip" "file://$d/mirror.git" ); case "$out2" in *"mirror"*) echo "self-test failed: the mirror that took the landing was pushed to again: $out2"; fails=1 ;; esac + out3=$( cd "$d/src" && IGNEUM_MIRRORS="build@203.0.113.9:/srv/igneum.git" mirror_master "$tip" "ssh://build@203.0.113.9/srv/igneum.git" ); case "$out3" in *"mirror"*) echo "self-test failed: the landed box in ssh:// form was pushed to again from its host:/path mirror entry: $out3"; fails=1 ;; esac [ "$(git -C "$d/mirror.git" rev-parse master)" = "$tip" ] || { echo "self-test failed: the mirror was not fast-forwarded to the landed master: $out"; fails=1; } ( cd "$d/src" && git checkout -q -b other master~1 && git -c user.name=t -c user.email=t@t commit -q --allow-empty -m fork ); fork=$(git -C "$d/src" rev-parse other) out=$( cd "$d/src" && IGNEUM_MIRRORS="$d/mirror.git" mirror_master "$fork" ) @@ -161,7 +183,8 @@ success 4 u push run [ "$fails" = 0 ] && echo "self-test passed: a GitHub remote is refused with exit 2 while the suspension marker stands and a mirror remote is not; the CI rule binds a GitHub remote only; a landed master is fast-forwarded to every mirror and a refused mirror push is a line, not a failure; a green branch run merges; a red one is refused; an unknown read is waited through and refused only at the deadline; a queued run is waited for with the clock; an unrun branch is pushed once and then waited for; a red master refuses every merge but the declared fix" exit $fails fi -if [ "$SELF_TEST" != 1 ] && github_suspended_refusal "$REMOTE"; then exit 2; fi # before any gh or git call (the self-test exercises the function itself) +if [ "$SELF_TEST" != 1 ] && github_suspended_refusal "$REMOTE"; then exit 2; fi +if [ "$SELF_TEST" != 1 ] && forgejo_master_refusal "$REMOTE"; then exit 2; fi # the public host takes no landing while the marker stands # before any gh or git call (the self-test exercises the function itself) [ -z "$(git status --porcelain --untracked-files=no)" ] || { echo "merge-to-master: the tree has uncommitted tracked changes; commit first" >&2; exit 1; } bash tools/ci/gh-account-check.sh || exit 1 # gh's active account on this Mac is the stored Igneum entry (main's rule, 7 October 2026, 21:5x UK) SHA=$(git rev-parse "$BRANCH"); G=$(cd "$(git rev-parse --git-common-dir)" && pwd -P) @@ -189,7 +212,9 @@ for i in $(seq 1 "$TRIES"); do if ( cd "$W" && git push -q "$REMOTE" HEAD:master ); then # on a GitHub remote the hook asks ci-state about ${SHA:0:8} once more git worktree remove --force "$W"; git fetch -q "$REMOTE" master echo "merge-to-master: pushed on try $i: $REMOTE/master $(git log -1 --format='%h %ci' "$REMOTE/master") $(TZ=Europe/London date '+%H:%M %Z')" - remote_is_github && mirror_master "$(git rev-parse "$REMOTE/master")"; exit 0 + # the landed master to every other mirror, whichever remote took the landing (8 October 2026, 14:0x UK: a box landing never fanned + # out, so build-3 and build-4 cut branches from a tip 23 hours old) + mirror_master "$(git rev-parse "$REMOTE/master")" "$(git remote get-url "$REMOTE" 2>/dev/null)"; exit 0 fi echo "merge-to-master: try $i: the push was rejected (master moved or the hook was red); again" else diff --git a/tools/ci/pc1-step-budget-check.sh b/tools/ci/pc1-step-budget-check.sh index e89436f99..055a3f31f 100755 --- a/tools/ci/pc1-step-budget-check.sh +++ b/tools/ci/pc1-step-budget-check.sh @@ -44,6 +44,6 @@ n=$(grep -c 'deadline.AddMinutes(-4)' "$f" || true) [ "$n" -ge 2 ] || { echo "pc1-step-budget: $f guards fewer than two places with the four-minute reserve (\$deadline.AddMinutes(-4): the step loop and the lock loop)"; bad=1; } grep -q 'lastMhs\[\$pk\] \* 1e6' "$f" || { echo "pc1-step-budget: $f does not size the batch count from the last rate read (\$lastMhs)"; bad=1; } grep -q 'script:lastMhs\[\$pk\] = \$b.mhs' "$f" || { echo "pc1-step-budget: $f never records the last rate per pack"; bad=1; } -if grep -vE '^\s*#' "$f" | grep -qE 'if \(\(Get-Date\) -gt \$deadline\)'; then echo "pc1-step-budget: $f still guards a step with the bare deadline (no reserve for the restore)"; bad=1; fi +if grep -qE 'if \(\(Get-Date\) -gt \$deadline\)' <<<"$(grep -vE '^\s*#' "$f")"; then echo "pc1-step-budget: $f still guards a step with the bare deadline (no reserve for the restore)"; bad=1; fi [ $bad = 0 ] && echo "pc1-step-budget: the efficiency pass keeps four minutes for its restore and sizes each step from the last rate" exit $bad diff --git a/tools/ci/playbook-quit-check.sh b/tools/ci/playbook-quit-check.sh index bb7961652..556937ebe 100755 --- a/tools/ci/playbook-quit-check.sh +++ b/tools/ci/playbook-quit-check.sh @@ -19,7 +19,7 @@ cd "$(dirname "$0")/../.." check_file() { local f="$1" bad=0 # rule 2: any request to api/cards outside a comment (Invoke-RestMethod, Invoke-WebRequest, curl, fetch: the shape is the URL) - if grep -vE '^\s*#' "$f" | grep -qE "api/cards"; then + if grep -qE "api/cards" <<<"$(grep -vE '^\s*#' "$f")"; then echo "playbook-quit: $f sends a request to the installed app's api/cards (a script never switches cards; ask the runner: publish-jobs.sh add --kind run --cards-off )"; bad=1 fi # rule 3 (STANDING RULE, the founder through main, 7 October 2026, 18:5x UTC): no PC job raises a UAC prompt or needs a click, ever. @@ -27,11 +27,11 @@ check_file() { # Power Helper task (Start-ScheduledTask by the owning user, commands through its cmd.txt: app/igneum-app/src/powertask.rs). # publish-jobs.sh refuses --elevated for the same reason (the 18:27Z job run-ca3-pc1-v4-eff-5090-20261007: exit 251 after # two minutes waiting for a click). - if grep -vE '^\s*#' "$f" | grep -qiE -e "(-Verb +['\"]?RunAs)|(\brunas(\.exe)? +/user)"; then + if grep -qiE -e "(-Verb +['\"]?RunAs)|(\brunas(\.exe)? +/user)" <<<"$(grep -vE '^\s*#' "$f")"; then echo "playbook-quit: $f raises an administrator prompt (-Verb RunAs or runas): no PC job prompts; use the Igneum Power Helper task (app/igneum-app/src/powertask.rs)"; bad=1 fi grep -qE "api/(quit|pause|resume)" "$f" || return $bad - if grep -vE '^\s*#' "$f" | grep -qE "igneum\\\\app\\\\app\.url|igneum/app/app\.url|Application Support/Igneum/app/app\.url|IGNEUM_APP_DIR[^\n]*app\.url|\\\$appDir[^\n]*'app\.url'"; then + if grep -qE "igneum\\\\app\\\\app\.url|igneum/app/app\.url|Application Support/Igneum/app/app\.url|IGNEUM_APP_DIR[^\n]*app\.url|\\\$appDir[^\n]*'app\.url'" <<<"$(grep -vE '^\s*#' "$f")"; then echo "playbook-quit: $f reads the installed app's URL file and sends quit, pause or resume to it (a job may only quit an engine it started: its own scratch URL file)"; bad=1 fi return $bad diff --git a/tools/ci/pre-push.sh b/tools/ci/pre-push.sh index 48e3f533d..695938a82 100755 --- a/tools/ci/pre-push.sh +++ b/tools/ci/pre-push.sh @@ -26,7 +26,9 @@ cd "$(git rev-parse --show-toplevel)" || exit 1 # and fire this hook again inside the fixture: the first master push through the gate died that way (6 October 2026). unset GIT_DIR GIT_WORK_TREE GIT_INDEX_FILE GIT_PREFIX GIT_COMMON_DIR GIT_OBJECT_DIRECTORY GIT_ALTERNATE_OBJECT_DIRECTORIES GIT_QUARANTINE_PATH GIT_PUSH_OPTION_COUNT MODE="${1:-local}"; MODE="${MODE#--}" -GATE_ROOT="$(pwd -P)" +GATE_ROOT="$(cd "$(dirname "$0")/../.." && pwd -P)" # the repository this gate belongs to: its helpers (tools/ci/*.sh) are read from here even when the hook + # is driven from another directory (the self-test's fixture repositories, 8 October 2026); the tree under + # test stays the working directory # Kill-proof by rule (8 October 2026, 12:4x UK: twice in a day a gate died to signal 15 from another lane's kill pattern): every gate run # carries a unique process title (igneum-gate:-, set by re-exec through `exec -a`) and writes its pid, start and mode to # .git/igneum-gate.pid under the worktree (removed at exit); a gate is stopped by that file only (`kill "$(cut -d' ' -f1 )"`), and @@ -227,6 +229,20 @@ github_suspended() { # : 0 with a printed refusal when the marker echo "pre-push gate: REFUSED. GitHub is unreachable ($(grep -E '^suspended-since' "$f" | head -1); tools/ci/github-suspended stands): no push, fetch or poll there. Push to the box mirror (git push box ...; landings: tools/ci/merge-to-master.sh --remote box). Main removes the marker at the cut-over." >&2 return 0 } +forgejo_master_frozen() { # : 0 with a printed refusal when the marker stands, the remote is the public + # Forgejo host and a ref line lands master there. Forgejo's master is a rewritten copy that the cut-over replaces with the rewrite + # of the box mirror's final tip (main's word through the coordinator, 8 October 2026, 13:34 UK): a branch pushed there for + # safekeeping is fine, a landing on its master is lost at cut-over. The marker goes at cut-over, and the refusal with it. + local f="${IGNEUM_GITHUB_SUSPENDED_FILE:-$GATE_ROOT/tools/ci/github-suspended}" host="${IGNEUM_PUBLIC_GIT_HOST:-git.igneum.network}" lref lsha rref rsha + [ -f "$f" ] || return 1 + case "${1:-}" in *"$host"*) ;; *) return 1 ;; esac + while read -r lref lsha rref rsha; do + [ "$rref" = refs/heads/master ] && [ -n "$lsha" ] && [ "$lsha" != 0000000000000000000000000000000000000000 ] || continue + echo "pre-push gate: REFUSED. $host holds a rewritten copy; its master is replaced at cut-over by the rewrite of the box mirror's final tip, so a landing there is lost. Land on the box mirror (tools/ci/merge-to-master.sh --remote box); a branch may go to $host for safekeeping." >&2 + return 0 + done <<<"${2:-}" + return 1 +} master_rule_binds() { # : 0 when the CI rule applies to this push (a GitHub remote, no declared exception), 1 with a printed line otherwise local url="${1:-}" if [ -n "${IGNEUM_MASTER_EXCEPTION:-}" ]; then echo " EXCEPTION to the CI rule for this push, declared by main: $IGNEUM_MASTER_EXCEPTION (the local gate is the verdict)"; return 1; fi @@ -323,8 +339,29 @@ FAKEGH case "$out" in *"REFUSED. GitHub is unreachable"*"--remote box"*) ;; *) echo "self-test failed: the refusal did not name the switch: $out"; fails=1 ;; esac ( IGNEUM_GITHUB_SUSPENDED_FILE="$mk" github_suspended ssh://build@188.40.146.49/srv/igneum.git >/dev/null 2>&1 ) && { echo "self-test failed: a mirror remote was refused under the marker"; fails=1; } ( IGNEUM_GITHUB_SUSPENDED_FILE="$mk.none" github_suspended https://github.com/x/y.git >/dev/null 2>&1 ) && { echo "self-test failed: a GitHub remote was refused without the marker"; fails=1; } + grep -qE 'github_suspended "\$URL" && exit 1' "$0" || { echo "self-test failed: the hook does not refuse a GitHub push under the marker"; fails=1; } + grep -qE 'master_rule_binds "\$URL"' "$0" || { echo "self-test failed: the hook does not bind the CI rule by the remote URL"; fails=1; } + fl=$(printf 'refs/heads/master %s refs/heads/master %s\n' 1111111111111111111111111111111111111111 2222222222222222222222222222222222222222) + bl=$(printf 'refs/heads/x %s refs/heads/x %s\n' 1111111111111111111111111111111111111111 2222222222222222222222222222222222222222) + out=$(IGNEUM_GITHUB_SUSPENDED_FILE="$mk" forgejo_master_frozen ssh://git@git.igneum.network:2222/igneum-network/igneum.git "$fl" 2>&1) || { echo "self-test failed: a landing on the public host's master was not refused under the marker"; fails=1; } + case "$out" in *"REFUSED"*"--remote box"*) ;; *) echo "self-test failed: the public-host refusal did not name the box route: $out"; fails=1 ;; esac + ( IGNEUM_GITHUB_SUSPENDED_FILE="$mk" forgejo_master_frozen ssh://git@git.igneum.network:2222/igneum-network/igneum.git "$bl" >/dev/null 2>&1 ) && { echo "self-test failed: a branch pushed to the public host for safekeeping was refused"; fails=1; } + ( IGNEUM_GITHUB_SUSPENDED_FILE="$mk.none" forgejo_master_frozen ssh://git@git.igneum.network:2222/igneum-network/igneum.git "$fl" >/dev/null 2>&1 ) && { echo "self-test failed: the public host's master was refused without the marker"; fails=1; } + ( IGNEUM_GITHUB_SUSPENDED_FILE="$mk" forgejo_master_frozen ssh://build@188.40.146.49/srv/igneum.git "$fl" >/dev/null 2>&1 ) && { echo "self-test failed: a landing on the box mirror's master was refused as the public host"; fails=1; } + grep -qE 'forgejo_master_frozen "\$URL" "\$REFS" && exit 1' "$0" || { echo "self-test failed: the hook does not refuse a landing on the public host's master under the marker"; fails=1; } + # the hook itself, driven by remote NAME as git drives it, in a fixture repo: a GitHub name and the public host's name are refused + # before any check runs; the box mirror's name is not (it reaches the gate, which is cut short by an empty ref list) + hx=$(mktemp -d); git -C "$hx" init -q && git -C "$hx" -c user.name=t -c user.email=t@t commit -q --allow-empty -m one + git -C "$hx" remote add origin https://github.com/igneum-network/igneum.git; git -C "$hx" remote add pub ssh://git@git.igneum.network:2222/igneum-network/igneum.git; git -C "$hx" remote add box ssh://build@188.40.146.49/srv/igneum.git + hsha=$(git -C "$hx" rev-parse HEAD) + out=$(cd "$hx" && printf 'refs/heads/master %s refs/heads/master %s\n' "$hsha" "$hsha" | IGNEUM_GITHUB_SUSPENDED_FILE="$mk" IGNEUM_GATE_NO_TITLE=1 bash "$GATE_ROOT/tools/ci/pre-push.sh" --hook origin 2>&1); rc=$? + { [ "$rc" != 0 ] && case "$out" in *"REFUSED. GitHub is unreachable"*) true ;; *) false ;; esac; } || { echo "self-test failed: the hook let a push to the GitHub remote by NAME through under the marker (rc=$rc): $(printf '%s' "$out" | tail -2)"; fails=1; } + out=$(cd "$hx" && printf 'refs/heads/master %s refs/heads/master %s\n' "$hsha" "$hsha" | IGNEUM_GITHUB_SUSPENDED_FILE="$mk" IGNEUM_GATE_NO_TITLE=1 bash "$GATE_ROOT/tools/ci/pre-push.sh" --hook pub ssh://git@git.igneum.network:2222/igneum-network/igneum.git 2>&1); rc=$? + { [ "$rc" != 0 ] && case "$out" in *"REFUSED. git.igneum.network"*) true ;; *) false ;; esac; } || { echo "self-test failed: the hook let a landing on the public host's master through under the marker (rc=$rc): $(printf '%s' "$out" | tail -2)"; fails=1; } + out=$(cd "$hx" && printf 'refs/heads/x %s refs/heads/x %s\n' "$hsha" "$hsha" | IGNEUM_GITHUB_SUSPENDED_FILE="$mk" IGNEUM_GATE_NO_TITLE=1 bash "$GATE_ROOT/tools/ci/pre-push.sh" --hook pub 2>&1); rc=$? + case "$out" in *"REFUSED"*) echo "self-test failed: a branch pushed to the public host by name for safekeeping was refused: $(printf '%s' "$out" | head -3)"; fails=1 ;; esac + rm -rf "$hx" rm -f "$mk" - grep -qE 'github_suspended "\$\{2:-\}" && exit 1' "$0" || { echo "self-test failed: the hook does not refuse a GitHub push under the marker"; fails=1; } master_rule_binds build@188.40.146.49:/srv/igneum.git >/dev/null && { echo "self-test failed: the CI rule bound a box mirror remote"; fails=1; } ( IGNEUM_MASTER_EXCEPTION="main, 7 Oct 2026 19:5x UK: GitHub suspended" master_rule_binds https://github.com/x/y.git >/dev/null ) && { echo "self-test failed: a declared exception did not lift the CI rule"; fails=1; } out=$(IGNEUM_MASTER_EXCEPTION="ruling text" master_rule_binds https://github.com/x/y.git); case "$out" in *"EXCEPTION"*"ruling text"*) ;; *) echo "self-test failed: the exception was not printed with its ruling: $out"; fails=1 ;; esac @@ -335,8 +372,13 @@ FAKEGH hook) # gh's active account on this Mac is the stored Igneum entry, before any push (main's rule, 7 October 2026, 21:5x UK; tools/ci/gh-account-check.sh) bash "$GATE_ROOT/tools/ci/gh-account-check.sh" || exit 1 - github_suspended "${2:-}" && exit 1 # the suspension marker: no push to GitHub at all (8 October 2026, 03:39 UK: 21 polls of a 403 before a kill by pid) + # git hands the hook " "; the remote checks below read the URL, never the name (8 October 2026, 13:5x UK: with + # the name, "origin" matched no *github.com* and the GitHub refusal and the CI rule never bound a named push). A push to a bare + # URL arrives with the URL in both places; a name alone resolves through git remote get-url. + URL="${3:-}"; [ -n "$URL" ] || URL="$(git remote get-url "${2:-}" 2>/dev/null || printf '%s' "${2:-}")" + github_suspended "$URL" && exit 1 # the suspension marker: no push to GitHub at all (8 October 2026, 03:39 UK: 21 polls of a 403 before a kill by pid) REFS="$(cat)"; which="$(printf '%s\n' "$REFS" | gated_refs)" + forgejo_master_frozen "$URL" "$REFS" && exit 1 # the public host's master takes no landing while the marker stands (8 October 2026, 13:34 UK) if [ "$which" = full ]; then # a merge of a green-stamped branch onto the exact remote tip goes through on the light gate (CI runs the full one) verdict=""; while read -r lref lsha rref rsha; do case "$rref" in refs/heads/master|refs/heads/release-*) verdict=$(deferred_merge "$lsha" "$rsha"); break ;; esac; done <<<"$REFS" @@ -345,7 +387,7 @@ FAKEGH # takes the local gate as before. IGNEUM_MASTER_EXCEPTION="" lifts the CI rule for one push and is printed with # the push (7 October 2026, 19:5x UK: the GitHub account suspended, lanes landing on the box mirror's master by main's ruling, # the box gate stamp as the verdict; GitHub gets the fast-forward when it answers again). - if master_rule_binds "${2:-}"; then + if master_rule_binds "$URL"; then while read -r lref lsha rref rsha; do if [ "$rref" = refs/heads/master ] && [ "$lsha" != 0000000000000000000000000000000000000000 ]; then master_ci_ok "$lsha" "$rsha" || exit 1; fi done <<<"$REFS" diff --git a/tools/ci/second-engine-check.sh b/tools/ci/second-engine-check.sh index ec8e8a647..376712f9e 100755 --- a/tools/ci/second-engine-check.sh +++ b/tools/ci/second-engine-check.sh @@ -20,10 +20,10 @@ while IFS= read -r f; do if ! grep -qE 'taskkill /T /F' "$f"; then echo "second-engine: $f starts an engine without ending its process tree (taskkill /T /F) at the end"; fail=1 fi - if grep -qE 'settings\.json|\.json' "$f" && grep -vE '^\s*#' "$f" | grep -qE 'Set-Content[^\n]*-Encoding +utf8'; then + if grep -qE 'settings\.json|\.json' "$f" && grep -qE 'Set-Content[^\n]*-Encoding +utf8' <<<"$(grep -vE '^\s*#' "$f")"; then echo "second-engine: $f writes JSON with Set-Content -Encoding utf8 (a BOM the engine refuses: the copy read as defaults, no payout address, nothing mined); use [IO.File]::WriteAllText with UTF8Encoding(\$false)"; fail=1 fi - if grep -vE '^\s*#' "$f" | grep -E 'ConvertTo-Json' | grep -qE 'settings\.json|Set-Content|WriteAllText|Out-File'; then + if grep -qE 'settings\.json|Set-Content|WriteAllText|Out-File' <<<"$(grep -vE '^\s*#' "$f" | grep -E 'ConvertTo-Json' || true)"; then echo "second-engine: $f rewrites settings.json through ConvertTo-Json (a lossy round trip: big integers become doubles and the engine reads the whole file as defaults; run 4, 6 October 2026); copy the file verbatim, the engine applies Settings::for_measurement under --sweep"; fail=1 fi if ! grep -qE "IGNEUM_APP_NO_OTA *= *'1'" "$f"; then