Merge build/master 1bd2b75b into spec-accept-23 (class-v5's 1.4.7 and 1.8.6 and its re-pointed LITERALS row taken; no conflict)

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

docs/analysis/chip-model-v3.md

@@ -205,6 +205,8 @@ Per row: reads per hash = 128 f; items recomputed = 128 (1 - f); ops per hash =
 
 Correction, 7 October 2026 (the in-house adversarial pass, lane adv-cache-3, report 091edc34): the partial-store rows above and adv-cache's Q1b table price a chip that holds every k-th line of the 64-line chain and recomputes a read at offset o in o evaluations ((k - 1) / 2 on average). The exact pebbling optimum for the chain (dynamic programming, checked against exhaustive search at 10 to 16 lines) sits under that curve: blocks per read 16.0 against 31.5 at f = 1/64 (the one held line belongs at line 32, not line 0), 10.5 against 15.5 at 2/64, 6.09 against 7.5 at 4/64, 3.17 against 3.5 at 8/64, 1.45 against 1.5 at 16/64, equal from f = 1/2. So a chip holding 1/64 of the cache pays 9.3x the item's ops, not 17.4x; at f = 1/2 and above nothing moves, and the SRAM column and the full-store verdict stand (no point on the curve beats the full store under the op budget or under energy).
 Memory-bound rate = the ceiling / (128 f). Compute-bound rate = 50 T op/s / ops per hash (the section 1 budget).
+
+Second correction, 8 October 2026 (the in-house adversarial pass, lane adv-cache-2, report section 2.3 and its Q3(3) window-layer reading, tip 3f50d6c4): the partial-store rows model a chip that holds a fraction f of the ITEMS chosen uniformly, so it serves f of the reads and recomputes 1 - f. The item-read distribution is not uniform: the exact window-layer distribution (matching the 4,096-program census to four digits; top quarter mean 0.3382, top half 0.5811 of reads) lets a chip holding the hottest f of items serve 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75 on the measured programs, so the f = 0.25 and f = 0.5 rows overstate the recompute share by up to 2.3x (1.8x on the first shard's read) and the f = 0.75 row by about 2.3x on the miss side. The f = 1 row, the SRAM column and the full-store verdict do not move (a chip that holds everything recomputes nothing either way), and no served number rests on f under 1; the partial-store rows stay as the uniform-store bound with this note until the hottest-f rows are drawn from the window distribution, which is the next pass of this section.
 The rate is the smaller; "binding" names it. Power = rate x (128 f x E_read + 128 (1 - f) x 6.3 nJ) + static (memory,
 controller, and 20 W for the recompute die's clocks and leakage when `f < 1`). Energy per hash = power / rate. "Gain,
 rate" = rate / 136.1 MH/s (per chip, the section 2 metric); "with the 3x factor" multiplies the compute-bound rate by

docs/fud-ledger.md

@@ -2503,7 +2503,7 @@ Owed (recorded, not run, by the founder's word): G2 (the CPU verifier on 1,024 h
 
 Owed (recorded, not run, by the founder's word): G2 (the CPU verifier on 1,024 hashes per card) on the amended stream; G3 (the Metal fuzz, edge, stats and determinism runs) on the amended stream; the hash-rate ladder re-measure on the M5 Max and the RTX 5090 (the amendment changes the base program's source draws, not the op mix or the load count, so the latency-bound rows of `docs/analysis/latency-shadow-2026-10-06.md` are expected to hold within their spread; unmeasured); AMD (the RX 9070 XT, PC 1); the 2019-class verifier core (O-1.14); F8's phase E (the 64-seed dynamic census) on the amended stream, which is the attack-pass lane's and the test of the per-op table. The row reads FIXED-AND-PASSED only after phase E passes against the amended class.
 
-Status: Fixed in part, finding bounded, stated (7 October 2026, night, the Counter ASIC lane's words): class v4 sub-version 3 (igneum-pow 017e7037, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under 1.2x with the four-seed tail accepted by the coordinator as the window model's unattributed residue (no chip consequence); the pass then attributed the class by value (eight live hot sets at 1.54x to 2.24x in the lowest 30 of 29,032 accepted programs, each about 1 MB of items at 0.3 percent of reads, 1.002x to a chip); class v5 (1c420786, frozen 21:53 UK) carries the fix as rule (c'''), the per-site distinct-index floor at 0.995 on the state flag (its census refuses 2.435 percent of accepted programs; seven of seven live hot sets refused at 0.9821 to 0.9919; the eighth's ratio owed tonight), with a named residual (three mild shadow-block-written concentrations at 0.9992 to 0.9997, about 1.0004x, a value-level test in the next class); the record is `docs/plans/counter-asic-3-status.md` section 7c and the class v5 design's section 14. The eighth live hot set (seed 122960, id 4be7393ab6c84802, the deepest found: X_f +0.111 percent, 1.54x the window model, its hottest item at 475,616 reads from an all-ones source) reads minimum site 12 at 0.9824 at the acceptance's own 2^20 sample (live 0.9822), refused by class v5's (c''') floor at 0.995; so the floor refuses eight of eight live hot sets by X_f at or above f found in the tail of 88,051 accepted programs (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; what it misses stays the three mild shadow-block-written concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x to a chip, the value-level test in the next class (22:41 BST; the logs under `docs/analysis/cryptanalysis/logs/adv-accept/` on branch adv-accept; the v5 design's section 14). The public sentence (the coordinator's wording, 7 October 2026, night): eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test. The reason, read by the in-house pass (adv-cache-2) and the class v5 lane together: the distinct-index count at 2^20 sees concentration on few word indices (the hot sets put about 3 percent of a site's reads on 512 indices, so the ratio falls to 0.98 to 0.992) and not a diffuse excess over the top 0.1 percent of items (16,384 items), which is what the era-stride low-bit law produces (13 of 27 drawn-era programs carry a site over 1.04x, 8 over 1.2x, worst 1.75x; 0 of 29 refused at the 2^20 sample, minimum sites 0.9965 to 1.0000); its chip value is about 1.0024x at the worst site read, under this row's bound by an order; the row for it is AP-F8-6. The RTX 5080 grid's knee is not in tonight; X37 keeps the 5080's stock premium only.
+Status: Fixed in part, finding bounded, stated (7 October 2026, night, the Counter ASIC lane's words): class v4 sub-version 3 (igneum-pow 017e7037, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under 1.2x with the four-seed tail accepted by the coordinator as the window model's unattributed residue (no chip consequence); the pass then attributed the class by value (eight live hot sets at 1.54x to 2.24x in the lowest 30 of 29,032 accepted programs, each about 1 MB of items at 0.3 percent of reads, 1.002x to a chip); class v5 (1c420786, frozen 21:53 UK) carries the fix as rule (c'''), the per-site distinct-index floor at 0.995 on the state flag (its census refuses 2.435 percent of accepted programs; seven of seven live hot sets refused at 0.9821 to 0.9919; the eighth's ratio owed tonight), with a named residual (three mild shadow-block-written concentrations at 0.9992 to 0.9997, about 1.0004x, a value-level test in the next class); the record is `docs/plans/counter-asic-3-status.md` section 7c and the class v5 design's section 14. The eighth live hot set (seed 122960, id 4be7393ab6c84802, the deepest found: X_f +0.111 percent, 1.54x the window model, its hottest item at 475,616 reads from an all-ones source) reads minimum site 12 at 0.9824 at the acceptance's own 2^20 sample (live 0.9822), refused by class v5's (c''') floor at 0.995; so the floor refuses eight of eight live hot sets by X_f at or above f found in the tail of 88,051 accepted programs (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; what it misses stays the three mild shadow-block-written concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x to a chip, the value-level test in the next class (22:41 BST; the logs under `docs/analysis/cryptanalysis/logs/adv-accept/` on branch adv-accept; the v5 design's section 14). The public sentence (the coordinator's wording, 7 October 2026, night; the count moved to nine at 01:13 BST on 8 October when the ninth live hot set, seed 228763 from a non-saturated source, read 0.9809 and was refused): nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test. The reason, read by the in-house pass (adv-cache-2) and the class v5 lane together: the distinct-index count at 2^20 sees concentration on few word indices whatever their source, saturated or not (the hot sets put about 3 percent of a site's reads on 512 indices, so the ratio falls to 0.981 to 0.992; the final tally 9 of 9 live hot sets and both single-item programs refused, 7 clean-live programs refused among the 12 deepest, 3 mild residuals missed) and not a diffuse excess over the top 0.1 percent of items (16,384 items), which is what the era-stride low-bit law produces (13 of 27 drawn-era programs carry a site over 1.04x, 8 over 1.2x, worst 1.75x; 0 of 29 refused at the 2^20 sample, minimum sites 0.9965 to 1.0000); its chip value is about 1.0024x at the worst site read, under this row's bound by an order; the row for it is AP-F8-6. The RTX 5080 grid's knee is not in tonight; X37 keeps the 5080's stock premium only.
 
 ### AP-F8-4. The program id's derivation text omitted generator 4's sub-version suffix (interoperability, documentation; no object change)
 

docs/plans/release-0.3.22.md

@@ -172,3 +172,5 @@ The 0.3.23 node's heights move Devnet 3's digest to ba75bf6f, and the one-box-at
 **The pin: release-0.3.24-node = dfbd1e10**, every gate green at 01:01:52 BST (build at gate priority 00:56 BST, igneumd 4870ccf2 / igneum-miner aa8c2978 under /srv/artefacts/0324-dfbd1e10/node-lane, igneum-pow-v5 8 paths; pow 19, consensus 134 at gate priority, p2p-flows 38, exec 47, core 175, miner 28; the Devnet 3 canary with digest b1ba7822, object version 6 in the headers, the override refused, shutdown 2,015 ms, two empty nodes handshaking, a 2720d8d2 node refused both ways; the testnet canary on b2e856ed refusing a live old-object seed). The object: the class v5 floor at 39,600 (epoch 11, about 04:53 BST on 8 October), the Devnet 3 digest b1ba7822 from ba75bf6f, holding for a publish up to DAA 32,400 at about 02:53 BST; everything else as c9e385eb. The fast-time SUMMARY on it runs on its lane. The app side: release-0.3.24 = 20213a7b (the Windows pin to dfbd1e10 on 9854030b's crate), the Mac node pair (igneumd 7907e161, igneum-miner e0979436) and the DMG 1aa301cc (45,653,186 B) built under the lock at 00:59 BST, the Mac entry re-staged in both token folders (interface 1.0.2, the floor file kept) and armed for the fleet's minute.
 
 **The build-server lane dark (read at 01:04 BST):** the dl host's jobs file was last published at 23:05 BST and carries no 0.3.24 host job for PC 1 and no 0.3.23 take 3 for PC 2 (its last jobs there: 0.3.23's host build and upload, take 2's ISCC log read); the lane answered nothing after 00:17 BST to asks at 23:43, 00:57 and 01:04. With it sit the c9e385eb and dfbd1e10 hands, seed and Windows pairs, the 0.3.24 hive with the v5 kit, the 0.3.24 Windows chain, 0.3.23's Windows entry (and so the card), and its tooling commits (the detached-helper rule, the inline-rm check, the publisher's digest gate, the alias assertion, push-inputs' overrides). Rulings by the shipper, main asked to confirm: "slot void" to the hash lane at 01:05 BST (PC 1's lock-free queue moves: the v5 kit fetch, the 9070 XT v5 bench, the CA4 unlocked rows); the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair (native glibc 2.39, the fleet's boxes' class), as dn3-g1 and g2 did at 22:30, aa8c2978 into the pack gate's list, build-1's three nodes restarted by the fleet itself on the minute; the 0.3.24 deploy publishes the Mac entry alone if no hive exists by the minute (the HiveOS alias stays on 0.3.23 and that gap is recorded; the public Mac alias moves in the same publish by main's rule); the Windows app chain waits for daylight or another builder, so tonight's 0.3.24 is Mac (and HiveOS if the shipper takes the package on main's word), with the 0.3.23 and 0.3.24 Windows entries and the card behind them. Main's word asked on three points: the shipper taking the hive and the Windows node pair through build-remote (the lease tool or plain), the Windows app chain's owner and hour, and take 3's publisher.
+
+**The 0.3.24 class v5 kit, one line for a reader diffing kits (the Counter lane, 01:1x BST):** the 0.3.24 packs are packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb, the kits lane's export byte-identical to the frozen igneum-pow 1c420786 the pin pairs with (the v5-dn3-epoch0 pack, program id e5a4ac5978462156, fingerprint 82b19cbde8557ea5); packs-ca3-v5-20261007T221001Z.zip (4aaf9b9e, from class-v5 7f58af97) carries the same three packs, ids, kernels and leaves and differs only in the kit host code beside them (the bench lanes' kit for the fingerprint jobs, not the miners' pack set); the next export changes the program_id_derivation TEXT field only (the "sub/" suffix wording), the ids unchanged. The fleet places e6c088bb on every Devnet 3 box; the hive carries it.