igneum-network/igneum
1
0
Fork 0
Code Issues Pull requests Releases Activity

Merge ca3-coord-record 7fdd094a into master (gate: green on 7fdd094a, recorded by tools/ci/pre-push.sh; landed on the build mirror)

Browse source
This commit is contained in:
igneum-labs 2026-10-08 14:58:07 +00:00
commit da5e1e8a69
2 changed files with 3 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
docs/plans/counter-asic-3-public-text-2026-10-07.md
View file

@ -4,6 +4,8 @@ Three texts and one ledger row, written by the Counter ASIC lane, which owns the
## 1. The home page's chip line (replaces the hero sentence served since 6 October 16:21Z) ## 1. The home page's chip line (replaces the hero sentence served since 6 October 16:21Z)
SUPERSEDED on the served pages on 8 October 2026 (the class v6 floor close, docs/design/class-v6-rotating-family.md section 10, amended into three statements at the founder's word): the served chip text is now the audit lane's spec-accept-23 wording (the 64-register window, 2.2x to 2.4x modelled against the GPU tier, 2.0x on the GPU's own node; economic resistance stated as conditions, not a forecast; response capability per boundary), with the 2.1x/3.4x line, the 5x to 9x baseline, the k about 0.33 column and the lifetime claim struck. The text below is the 7 October wording, kept as the record of what was served between 7 October and the 8 October landing.
Built for graphics cards. At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block; a 5090 locked at its knee pays 82 W for that shadow work. Class v5 then makes the dataset the chain's own state, so a chip that stores it or recomputes it is wrong on every item. Without class v4 the same chip would reach 5x to 9x. The model and every measurement are public. Built for graphics cards. At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block; a 5090 locked at its knee pays 82 W for that shadow work. Class v5 then makes the dataset the chain's own state, so a chip that stores it or recomputes it is wrong on every item. Without class v4 the same chip would reach 5x to 9x. The model and every measurement are public.
## 2. The litepaper's chip section (replaces the paragraph that begins "The chip model: 5x to 9x per joule") ## 2. The litepaper's chip section (replaces the paragraph that begins "The chip model: 5x to 9x per joule")

2
docs/plans/counter-asic-3-status.md
View file

File diff suppressed because one or more lines are too long