igneum-network/igneum
1
0
Fork 0
Code Issues Pull requests Releases Activity

Class v6 10.0e: the node column (node-for-node the window core is k 1.09 and the DRAM board 2.0x at the 5090's knee; N3 buys the chip 0.4x, N2 0.8x)

Browse source 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
This commit is contained in:
igneum-labs 2026-10-08 13:53:36 +00:00
parent 1f1a3b361e
commit d9a08bc753
1 changed files with 10 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
docs/design/class-v6-rotating-family.md
View file

@ -362,6 +362,16 @@ The chip's class v4 shadow on the window core is 102,100 x 4.8 pJ = 0.49 microjo
**Stated plainly: with the window the GPU-tier floor is about 2.2x to 2.4x per joule against the chip anyone can build, and under 2x only against the Apple tier (1.5x); Monero's RandomX measured 1.0x to 1.5x beside it (10.0b, the Antminer X5 after 46 months). The lifetime cost-per-hash sentence stays the headline: under 1x per hash over a 180-day class life only above about USD 300 M a year of miner revenue (10.0a).** Against the SRAM die the window reads 3.8x to 4.3x on the NVIDIA floors and 2.6x on the M5 Max, with the N2 project's ticket (10.3) and its capex wall beside it.
The node column (the k lane, 15:0x UK; the factors claimed from TSMC's per-node headlines: N7 to N5 x0.70, N5 to N3E x0.72, N3E to N2 x0.72; ASAP7 is a predictive 7 nm-class PDK so "N5" is ASAP7 x0.70; the 5090 and 4090 are TSMC 4N, N5 class; the M5 Max N3). Absolute; the GDDR7 board at the lock = 2.33 / (0.466 + 102,100 x e_chip):
| Core | pJ per lane-op ASAP7 / N5 / N3 / N2 | k at the lock N5 / N3 / N2 | GDDR7 at the lock N5 / N3 / N2 | Label |
|---|---|---|---|---|
| base (32 registers, 256 imem) | 6.9 / 4.8 / 3.5 / 2.5 | 0.78 / 0.56 / 0.40 | 2.4x / 2.8x / 3.2x | synthesised; scaling claimed |
| the 64-register file | 9.7 / 6.8 / 4.9 / 3.5 | 1.09 / 0.78 / 0.56 | **2.0x** / 2.4x / 2.8x | synthesised; scaling claimed |
| all four together | ABC on build-3, about 16:00 | | | owed |
In one line: of the 2.8x at k 0.56, the N5-to-N3 node step is 0.4x (2.4x node-for-node, a factor 1.17, claimed); the rest is the memory system's 3.6x at zero shadow less what the shadow takes back on the card's own node, which is the design. **Node-for-node the base core is k 0.78 and the window core 1.09, so with the window a chip on the GPU's own node reaches 2.0x against a 5090 at its knee and 1.8x against the 5080; what a chip project buys back with N3 is 0.4x and with N2 0.8x.** This is the honest form of the served "with a core as good as a GPU lane": on the same node the window core is one.
#### 10.0d The rotation schedule the close adopts (the rotation lane, `docs/design/class-rotation-four-layers.md` on class-v6-rotation at bd43f808, build-3, gate green, 14:4x UK; one line per layer; both of this document's constraints held: the 180-day family epoch not shorter, W = 4 not drawn)
| Layer | Boundaries a year | What it draws, from where | Exposure per boundary (this document's units) | Chip | Label |