diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md
index adf592017..e7ef7356d 100644
--- a/docs/plans/counter-asic-3-status.md
+++ b/docs/plans/counter-asic-3-status.md
@@ -327,6 +327,15 @@ A script never switches the installed app's cards: a POST of enabled false to /a
 
 the project lead gave the go in advance for tonight: the shipper runs publish 1 on the 0.3.15 canary line, then publish 2 once every online node and worker reads 0.3.15, miners first, hands last; the rehearsal chain ends on the line that publish 2's digest is read back on every node (its miners off, the boxes to the standing roster or run A). The evidence folder's last entry: `counter-asic-3-gate/class-v4-20261006-rehearsal-PASS.json`. The public bench-log entry (numbers only, no box names): `docs/bench-log.md` "6 October 2026, Counter ASIC 3.0: the class v4 rehearsal". The 3.0 lane is closed.
 
+## 7c. Reopened on the v4 seam, 7 October 2026 (morning): AP-F8-1, the item read map's skew
+
+| Item | State |
+|---|---|
+| The finding (the attack-pass lane, F8 phase D, one class v4 program, 2^26 nonces; `docs/analysis/attack-pass/f8-uniform.md` on branch attack-pass) | the top 0.1 percent of items take 0.520 percent of reads against 0.115 uniform (4.05x); the top 1 percent 2.49 (1.37x); one item 0xca5b92 takes 78,479 reads, 153x the mean; read site 15 feeds 6.37 percent of its reads into the top 0.1 percent in all 8 iterations; the excess grows with N. The ask: a generator fix on the v4 seam with the gate "top 0.1 percent within 1.2x of uniform over 2^26 nonces on 64 seeds"; the attack-pass lane re-gates with `tools/attack/f8-uniform` |
+| The lane's framing | class v4's item map is not designed to be uniform per program: layer 8's per-site windows (k_off = below(3): the whole dataset, a half or a quarter per site, under the era stride and interleave) concentrate a quarter-window site 4x on its quarter, which is the 4.05x; the null is the window model from the program's own 16 draws; the 153x item is the number to explain (coinciding windows under the era mapping with a stated tail, or a low-entropy source at site 15, a fault); the chip consequence a 1.7 MB hot-set cache serving 0.5 percent of reads, under one percent of rate |
+| The cut consequence | v4 is on the live devnet's vote and the class lives in the binary: any generator change to v4 is a class change (new vectors, the six gates) that must reach every node before the flip or the chain splits; unless F8's phase E census shows a fault beyond the window model, the answer is the documented null and, for a tighter tail, an acceptance bound in the next class, not in v4; a fault beyond the model is main's and the shipper's decision (a class amendment before the flip, or the flip held by the floor) |
+| Who | the hash lane, branch ca3-v4-uniform from master: the model, the reproduction with F8's harness on the v4 packs and the mixer harness's 200 programs, the census, the re-priced row; a fix only on a fault |
+
 ## 8. Close
 
 Closed 6 October 2026, 18:1x UTC. The lanes: item 1 (ca3-analysis), item 2 (ca3-derive), items 4 and 5 (ca3-detector), item 3 (ca3-crypto-brief), items 6 and 7 (ca3-reserve), item 8 (ca3-shadow), the PC 1 AMD jobs (ca3-pc1-amd), the hash gates (ca3-v4-hash) and the node gates with both preconditions (ca3-v4-node and the fork): thank you, every one of you, for the numbers and for the faults you found in your own work and in mine before they reached a cut.