diff --git a/docs/analysis/chip-model-v3.md b/docs/analysis/chip-model-v3.md index 0510d7ce0..1d47b2f72 100644 --- a/docs/analysis/chip-model-v3.md +++ b/docs/analysis/chip-model-v3.md @@ -35,12 +35,12 @@ silicon" = bare x (750 - SRAM) / 750 x 3: the SRAM takes die area the logic does |---|---|---|---|---|---|---|---|---| | v2 as shipped (the M16 and scratch-soundness row) | x1 | 149,760 | 334 MH/s | 256 MiB | 128 / $46 | 2.45x (2.39x against 139.7) | 7.4x | 6.1x | | v2 at w16 (not adopted; the chip's cost is items, not bytes: unchanged) | x1 | 149,760 | 334 | 256 MiB | 128 / $46 | 2.39x against 139.8 | 7.2x | 5.9x | -| v3: mixer x4 | x4 | 599,040 | 83.5 MH/s | 256 MiB | 128 / $46 | 0.61x | 1.84x | 1.53x | +| x4 (the candidate measured beside v3; not v3) | x4 | 599,040 | 83.5 MH/s | 256 MiB | 128 / $46 | 0.61x | 1.84x | 1.53x | | MEASURED, NOT ADOPTED (layer 5 decided out of v3 on the PC rows, coordinator 21:40 UTC): v3 plus a 32 MiB hot table, added form (16 dataset loads and k hot loads): the honest card pays the hot loads, this chip pays SRAM only | x4 | 599,040 (a hot load is one SRAM read, no item) | 83.5 | 288 MiB | 144 / $53 | 0.66x at the Mac's g = 0.93 (126.6 MH/s); 0.70x at the 5090's g = 0.87 (118.4); the 9070 XT's g 0.84 | 1.98x (Mac g), 2.11x (5090 g) | 1.60x, 1.71x | | MEASURED, NOT ADOPTED: v3 plus a 64 MiB hot table, added form | x4 | 599,040 | 83.5 | 320 MiB | 160 / $61 | 0.71x at the Mac's g = 0.87 (118.4 MH/s); 0.73x at the 5090's g = 0.84 (114.3); the 9070 XT's g 0.80 | 2.12x (Mac g), 2.19x (5090 g) | 1.67x, 1.73x | | v3 at year 4 (cache 512 MiB under option C, dataset 4 GiB), no hot table | x4 | 599,040 | 83.5 | 512 MiB | 255 / $111 | 0.61x | 1.84x | 1.21x | | v3 at year 12 (cache 1 GiB, dataset 8 GiB) | x4 | 599,040 | 83.5 | 1 GiB | 510 / $306 | 0.61x | 1.84x | 0.59x | -| v3 with the mixer at x8 (the candidate under the coordinator's rule of 21:30 UTC: in if the verify stays under 10 ms per warp on one Mac core and the daily 1 GiB build under 1 s on every discrete card) | x8 | 1,198,080 | 41.7 | 256 MiB | 128 / $46 | 0.31x | 0.92x | 0.76x | +| **v3: mixer x8** (decided 22:05 UTC under the delegated rule: verify 2.1 ms per unit on one Mac core against the 10 ms gate, the daily 1 GiB build 23 to 77 ms on the 5090 and the 9070 XT) | x8 | 1,198,080 | 41.7 | 256 MiB | 128 / $46 | 0.31x | 0.92x | 0.76x | | x8 at year 4 | x8 | 1,198,080 | 41.7 | 512 MiB | 255 / $111 | 0.31x | 0.92x | 0.61x | The era draws of spec 1.13.1 cost the chip nothing in this model: the mixer round count is not drawn, the op @@ -64,12 +64,13 @@ not a forecast). The combined headline row is the mixer row alone (layer 5 is out: the added form costs the 5090 13 to 16 percent and the 9070 XT 16 to 20 percent against the 0.97 bar, coordinator 21:40 UTC; the width stays 4 bytes; the era -draws and the cache growth cost this chip nothing at year 0). At x4 it reads 1.84x with the 3x factor at an equal -integer budget, 1.53x with the SRAM area deducted; at x8 0.92x and 0.76x. The hot-table rows above are kept as -measured, not adopted: against THIS chip an added hot table is a cost to the honest card and none to the chip, so -it would have moved the row the wrong way by the card's own `g` (2.11x to 2.19x at the 5090's g). The claim is -"under 2x" at x4 on both conventions, with the margin thin on the equal-budget one; at x8 the chip is under 1x on -both: +draws and the cache growth cost this chip nothing at year 0), and class v3 is x8 (decided 22:05 UTC). The headline: +**the on-die-cache recompute chip at 50 T op/s reaches 41.7 MH/s against the 5090's 136.1, 0.31x bare, 0.92x with +the 3x fixed-function factor, 0.76x with the mirror's area deducted: under 1x with the factor, 0.92x, a margin of 8 +percent on the factor (a 3.3x factor reads 1.0x) and of 9 percent on the budget (55 T op/s reads 1.0x).** The x4 +candidate, measured beside it, read 1.84x and 1.53x. The hot-table rows above are kept as measured, not adopted: +against THIS chip an added hot table is a cost to the honest card and none to the chip, so it would have moved the +row the wrong way by the card's own `g`. The margin, plainly: - the 3x fixed-function factor is approximate and from memory; at 3.3x the equal-budget row reads 2.0x; - the denominator is one card's measured rate on one night (136.1 against 139.7 the night before: 2.6% apart); @@ -78,15 +79,15 @@ both: the PC rows), which raises the chip's gain by the same share, 1.84x or more if the hot loads are free, higher if not; the hot table's only cost to this chip is 16 to 32 mm^2 of die. -What keeps it under 2x is the mixer, and nothing else in Counter ASIC 2.0 moves this chip (the scratch at any share +What keeps it under 1x is the mixer, and nothing else in Counter ASIC 2.0 moves this chip (the scratch at any share gave 2.4x, `docs/analysis/scratch-soundness.md` section 3.4; the hot table taxes the DRAM-only chip, not this one; the cache growth taxes it only in die area, which is cheap at year 0 and real at year 12). The next levers, in order: -1. Mixer x8: 0.18x bare and 0.55x with the factor in the M16 table (0.31x and 0.92x against 136.1 here; the M16 - table's denominator is 229 MH/s); the CPU verifier at 3.3 to 9.6 ms per warp scaled from the version 1 range, - at the edge of the 10 ms gate; the measured v3 row of `docs/plans/mixer-x4.md` section 6 is what to scale from - now, and whether a 2019-class laptop core (unmeasured, O-1.14) passes 10 ms is what decides it. +1. Mixer x16 (the next step of the same lever): 0.16x bare and 0.46x with the factor against 136.1; the verifier + by the measured increments (+0.63 ms at x4, +1.46 at x8 on the M5 Max core: about +3.1 ms at x16, 3.7 ms per + unit, 9 ms on a 2.5x slower laptop core, approximate) is at the edge of the 10 ms gate, so a 2019-class laptop + core measurement (O-1.14) decides it, not this model. 2. The hot table: adopted or not on the PC rows (`docs/plans/hot-table.md`); in the added form it costs the GPU 7 to 17 percent on the Mac and the chip die area only, so against this chip it is a lever in the wrong direction and against a DRAM-only chip the first lever; if it is adopted, the mixer must carry the extra `1/g` diff --git a/docs/bench-log.md b/docs/bench-log.md index 8550d873c..f18651b36 100644 --- a/docs/bench-log.md +++ b/docs/bench-log.md @@ -1664,3 +1664,6 @@ Timings, `with-lock.sh measure`, one session 21:40:12 to 21:40:23 UTC, one core, Reading: the mixer multiplies the verifier's ALU part only (the 8 dependent misses per item are unchanged), hence 1.45x and 2.1x and not 4x and 8x; the Mac's GPU build is latency-bound and does not move with the mixer, so the "under 1 s on every discrete card" half of the x8 rule is the PC job (five packs, `relay/playbooks/mixer-x4-pc1-bench.ps1`, waiting for the go). Verification throughput (C19): a quiet 2026 core serves about 1,100 shares per second at x4 and 800 at x8 (1,660 at v2, re-cutting spec 09's 2,270), a 22,000-member pool at one share per 10 s needs 2 cores at x4 and 3 at x8, IBD over 108,000 headers is 1.6 min at x4 and 2.3 at x8 on that core; the 10 ms gate keeps 8.0 ms (x4) and 7.1 ms (x8) of margin on the loaded core, 6 to 7 ms on a 2019-class laptop core (approximate, unmeasured, O-1.14). Chip model (`docs/analysis/chip-model-v3.md`): the on-die-cache recompute chip at 50 T op/s against the 5090's measured 136.1 MH/s: v2 334 MH/s, 2.45x bare, 7.4x with the 3x fixed-function factor; x4 83.5 MH/s, 0.61x bare, 1.84x with the factor, 1.53x with the 128 mm^2 N5 mirror deducted at equal silicon; x8 41.7 MH/s, 0.31x, 0.92x, 0.76x. The claim at x4 is "under 2x" with the margin thin on the equal-budget convention (a 3.3x factor or a 10 percent larger budget reads 2.0x); the hot table in the added form would have raised it to 2.1x to 2.2x at the 5090's g (kept as measured, not adopted). Nothing here is a measurement of a chip. + +**Addendum, 22:15 UTC: the verifier regression, the PC 1 build rows, and x8 into v3.** The era agent measured the same v2 input with readwidth's binary (0.604 ms) and ca2-v3 HEAD's (1.33) in one minute; bisected under the measure lock to this branch's 0fc0ad1 (seam 6c75dad 0.610, 0fc0ad1 1.332; the "loaded box" reading above was wrong by that factor, the load was real but the 2x was the code). Cause: the item loop (`derive_items`) inlined into `MemhardCpu::fetch`; the mask hoisted, the mask constant, and the constant-mask loop inlined all stayed at 1.33, the same loop `#[inline(never)]` read 0.60 to 0.62. Fix: `derive_items_mask`, out of line, one instance per cache size with the line mask a constant. Measured the era agent's way (readwidth's binary beside the fixed one, same input, same minute, 22:07 UTC): v2 0.607 / 0.610 against 0.609 / 0.611; on the fixed binary x4 1.238 / 1.237 (2.0x), x8 2.077 / 2.058 (3.4x), worst cold 2.15 ms; the increments (+0.63, +1.46 ms per unit) equal the slow binary's. Lesson, the class: an inlined item loop costs 2.2x and nothing in the suite sees it; a verifier benchmark with a pinned bound in the crate's CI is filed for the next cut, and until then every change to the item loop is measured against the previous binary on the same input in the same minute. PC 1 (job run-mixer-x4-pc1-20261005, 22:00 to 22:04 UTC, the worker's `cache ... dataset ... ms` wall line): RTX 5090 dataset 23 to 25 ms at v2, x4 and x8; RX 9070 XT (gfx1201) 72 to 77 ms at all three; every fingerprint equal to the Mac's; rates the v2 rate (136.5 to 137.4 and 18.0 to 18.2 MH/s). Decision under the delegated rule (coordinator, 22:05 UTC): x8 enters class v3 (`V3_CLASS = MX8`); pinned packs mx8-genesis (7c28cfb06c5c65a9) and mx8-devnet-epoch0 through the chain path with the era inside (90f794dd556f7a3b, Metal and Apple OpenCL, 22:12 UTC); the x4 packs kept as the candidate's record. Chip headline at x8: 41.7 MH/s, 0.31x bare, 0.92x with the 3x factor, 0.76x at equal silicon (`docs/analysis/chip-model-v3.md`). + diff --git a/docs/plans/mixer-x4.md b/docs/plans/mixer-x4.md index ce91b34d5..cc5ae2067 100644 --- a/docs/plans/mixer-x4.md +++ b/docs/plans/mixer-x4.md @@ -222,6 +222,18 @@ and 21.7 ms GPU (mx4-devnet-epoch0) for 1 GiB; Apple OpenCL 55 and 56 ms wall. T this card is 0.6 to 2.1 ms cache fill and a 1 GiB build the bench-log's memory-hard entry puts at 13 to 30 ms; the x4 build on the GPU is the row the measure lock will settle. +### 6.2a The packs as pinned after the x8 decision (`with-lock.sh run`, 22:12 UTC, the fixed binary's exports) + +| Pack | How exported | Program id | Unit 0 lane 0 | Fingerprint 2^24 (Metal = Apple OpenCL) | Vectors, self-tests | +|---|---|---|---|---|---| +| mx8-genesis | `--program-class v3` (generator 3, V3_CLASS = mx8) | e323b9dcaf283a6f | 19b56348bc85304d | 7c28cfb06c5c65a9 | 3/3 + 3/3, 96 of 96, PASS | +| mx8-devnet-epoch0 | the chain path, `--program-class v3 --era-hex ` (the era drawn inside the class, load class `mx8-erad810f22d`) | 73bcbfe8ccf988f1 | d424577fce4a7a60 | 90f794dd556f7a3b | 3/3 + 3/3, 96 of 96, PASS | +| mx4-genesis (the x4 record) | `--class mx4` (generator 2, the class in the id) | 951b89584750bd75 | 63acd2d273f475ba | 6f48d5a2aa0dbe5f | 3/3 + 3/3, 96 of 96, PASS | +| mx4-devnet-epoch0 (the x4 record) | `--class mx4` on the chain seeds | (program.json) | 212c6442b51e87ae | 73caaebb28e808fe | 3/3 + 3/3, 96 of 96, PASS | + +The PC 1 rows of 6.5 ran the earlier mx8-devnet-epoch0 (the load-class export, fingerprint bbb183f72692f840, era +not inside); the composed pack's PC fingerprints are owed with the next PC round (section 9). + ### 6.3 Soundness suite on the v3 construction (commit 66eeba3 and after; `with-lock.sh build` for cargo, `run` for the GPU) | Suite | Command | Result | @@ -292,6 +304,26 @@ two cores); at x8 about 800 (three cores). A node's block verification stays a f remaining margin is what Counter ASIC 3.0 has to spend, and on the unmeasured laptop core it is 6 to 7 ms at x4 and about 6 at x8, which is the number the 2019-class measurement (O-1.14) must confirm before x8 is final. +### 6.4a The same session on the fixed binary (section 6.6), `with-lock.sh measure`, 22:06:59 to 22:07:06 UTC + +The verifier of section 6.4 was measured on a binary that carried the inlining regression of section 6.6; after the +fix, readwidth's binary and the fixed one on the same v2 input in the same minute (checksum 19297e99c7b9a55e), then +x4 and x8 on the fixed binary; load average 5.5 (the same box, so the ratios of 6.4 stand and the absolute row is +now the measured one): + +| Construction | Verifier, ms per unit, avg of 50 (round 1 / round 2) | Worst cold unit of three | Against v2 | +|---|---|---|---| +| v2, readwidth e752fc7's binary | 0.607 / 0.610 | 0.666 | 1 | +| v2, the fixed binary | 0.609 / 0.611 | 0.657 | 1.00 | +| x4 (mx4) | 1.238 / 1.237 | 1.396 | 2.03x | +| x8 (mx8, class v3) | 2.077 / 2.058 | 2.145 | 3.4x | +| x4, the devnet seeds | 1.240 | 1.289 | | +| x8, the devnet seeds | 2.058 | 2.144 | | + +The added cost per unit is the same as on the slow binary (x4 + 0.63 ms, x8 + 1.46 ms: the regression was a +constant 0.72 ms per unit in the shared item loop), so the ALU reading of 6.4 holds; the ratios against v2 are +2.0x and 3.4x once v2 is back at 0.61. The 10 ms gate keeps 7.9 ms at x8 (worst cold 2.15 ms) on this core. + ### 6.5 The daily build per tier, and the x4 / x8 rule The coordinator's rule (21:30 UTC): x8 enters v3 if the per-warp verify stays under 10 ms on one Mac core AND the @@ -301,34 +333,68 @@ per day, so its consequence is per-day dataset reuse in the workers or a restart | Card | Build at x1 | x4 | x8 | Source | |---|---|---|---|---| -| RTX 5090 (PC 2) | 13.4 ms (1 GiB) | owed (PC job, section 8) | owed | bench-log, 3 October, memory-hard entry | -| RX 9070 XT (PC 1, eGPU) | owed | owed | owed | PC job, section 8 | +| RTX 5090 (PC 1, job run-mixer-x4-pc1-20261005, 22:00 to 22:04 UTC, the worker's `cache ... dataset ... ms` wall line, two dispatches per pack) | 23 to 25 ms | 23 to 25 ms | 23 ms | the PC 1 job (13.4 ms GPU time on 3 October: the wall line carries the launch) | +| RX 9070 XT (PC 1, gfx1201 on the eGPU, the same job) | 74 ms | 73 to 77 ms | 72 to 76 ms | the PC 1 job | | M5 Max, Metal | 13 to 30 ms (the two runs of the memory-hard entry; tonight's run-lock figures 21.7 to 30.2 ms at x4 and 22.0 to 30.0 at x8 say the Mac's build is latency-bound, not mixer-bound) | section 6.4 | section 6.4 | this file | | Radeon integrated gfx1036 (PC 2), OpenCL, per prepare | 6.9 / 9.4 / 11.7 s prepare total with the 1 GiB build inside | about 28 to 47 s (approximate: scaled x4; the iGPU's build is arithmetic-bound at x1 already) | about 55 to 94 s (approximate) | `docs/plans/epoch-length.md` section 7 (branch ca2-epoch), M11 table | | gfx1036 beside WSL build jobs (PC 1) | 55 / 116 / 124 s | about 4 to 8 min (approximate) | about 7 to 17 min (approximate) | same | | 8 GB-class discrete card (not owned; about a tenth of the 5090's rate, approximate) | about 0.13 s | about 0.5 s | about 1 s, on the edge of the rule | scaled from the 5090 row, approximate | -Reading, before the measured rows: on the discrete cards the rule is about the 5090 and 9070 XT rows (owed, the PC -job). The integrated tier misses the rule at x4 already: a per-prepare build of 28 to 47 s is a tenth to a quarter +Decision (coordinator under the delegated rule, 22:05 UTC, on these rows): x8 enters class v3. Both halves pass: +the verifier at x8 is 2.1 ms per unit on one M5 Max core (6.4a) against the 10 ms gate, and the daily 1 GiB build +does not move with the mixer on any discrete card we own (5090 23 to 25 ms, 9070 XT 72 to 77 ms, M5 Max 21 ms at +x1, x4 and x8: latency-bound), 13x to 40x under the 1 s bar. `V3_CLASS = { era: None, hot: None, ..LoadClass::MX8 }`; +the pinned v3 packs are mx8-genesis and mx8-devnet-epoch0 (the latter through the chain path with the era inside the +class); the x4 packs stay pinned as the candidate's record (generator 2, the class in the id). + +Reading of the integrated tier: on the discrete cards the rule is settled by the 5090 and 9070 XT rows above. The integrated tier misses the rule at x4 already: a per-prepare build of 28 to 47 s is a tenth to a quarter of the 600-DAA-second lead the devnet gives the next program (spec 1.12), and under load it is the whole lead; so if x4 or x8 goes in, the iGPU tier needs the workers to build the day's dataset once a day and keep it across epochs (today a prepare rebuilds it: `proto-opencl/host.c` prepareTask builds the pair's cache and dataset per prepare), or to restart per epoch. The node agent is asked whether the per-day reuse is bounded tonight (coordinator, 21:45 UTC); until then the iGPU consequence stands as written. +### 6.6 The verifier regression of 0fc0ad1, found and fixed (5 October 2026, 21:59 to 22:07 UTC) + +The era agent measured the same v2 input with two binaries in one minute: readwidth's 0.604 ms per unit, ca2-v3 +HEAD's 1.33. Bisected under the measure lock (one session, four binaries, two rounds, checksum 19297e99c7b9a55e): +readwidth e752fc7 0.607 / 0.609; the ca2-v3 seam 6c75dad (before this branch) 0.610 / 0.609; this branch's 0fc0ad1 +1.332 / 1.316; ca2-v3 88dafbc 1.325 / 1.347. So the 2.2x was in 0fc0ad1's `derive_items`, on the version 2 path the +devnet verifies with, and section 6.4's "loaded box" reading was wrong: the load was real (the same session shows +it) but the 2x was the code. + +Variants, each a one-change copy measured against readwidth's binary in the same session: + +| Variant | ms per unit | Reading | +|---|---|---| +| 0fc0ad1 as written (the line mask read from the cache at run time, the loop inlined into `MemhardCpu::fetch`) | 1.33 | the regression | +| the mask hoisted into a local before the item loop | 1.32 to 1.37 | not the reload | +| `Cache::line` with the constant mask, on the 0fc0ad1 tree | 0.60 to 0.65 | fixed there | +| the same constant mask on the merged ca2-v3 tree | 1.33 to 1.46 | not the mask either | +| one instance per cache size with the mask a constant, `#[inline(always)]` | 1.32 to 1.39 | not the mask | +| the same instances `#[inline(never)]` | 0.604 / 0.617 / 0.618 / 0.624 | the fix | + +So it is inlining: the item loop inlined into its callers (`fetch`, `fetch_wide`, `word_at`) runs at 2.2x the +out-of-line loop, and which small change tips LLVM's decision depends on the rest of the tree (the constant mask +tipped it on one tree and not on the other). The fix (`memhard::derive_items`): the loop is `derive_items_mask`, +`#[inline(never)]`, one instance per cache size the growth rule reaches (2^26 to 2^30 words) with the line mask a +constant, and a run-time-mask instance for every other size (tests). Measured in 6.4a: 0.609 / 0.611 against +readwidth's 0.607 / 0.610. + +The class, not the instance: a verifier benchmark with a pinned bound in the crate's CI (the v2 unit at a known +input against a stored ms-per-unit on a named core, failing on a 1.3x drift) would have caught this at the first +commit; filed for the next cut (section 9). Until then the era agent's two-binary check (same input, same minute) +is the rule for every change that touches the item loop. + ## 7. The chip model `docs/analysis/chip-model-v3.md`. ## 8. What is unverified -1. The 5090's and the 9070 XT's dataset build at x4 and x8 (the "under 1 s on every discrete card" half of the x8 - rule): the PC 1 job (`relay/playbooks/mixer-x4-pc1-bench.ps1`, package `mixer-x4-pcjob.zip` sha256 - ec3be97e...bdf87, five packs, the worker's `cache ... dataset ... ms` line per pack) waits for the coordinator's - go after the era job; by the M16 arithmetic the 5090 is 54 ms at x4 and 107 ms at x8 if its build is - arithmetic-bound and 13.4 ms if it is latency-bound like the Mac, both far under 1 s; the gfx1036 is the tier - that fails (section 6.5 of the build table), and its consequence (per-day dataset reuse in the workers) is with - the node agent. +1. The 5090's and the 9070 XT's dataset build at x4 and x8 are measured (6.5, the PC 1 job): both latency-bound, + under 0.1 s. The gfx1036 is the tier that fails the per-prepare build (6.5), and its consequence (per-day dataset + reuse in the workers) is with the node agent. 2. The absolute verifier figures were taken on a loaded core (load average 5.6); the ratios are the measurement and the quiet-core figures are scaled. A 2019-class laptop core has not run any construction (O-1.14). 3. The mixer has had no cryptanalysis (spec 1.8.4); `m` applications with distinct round keys is `m` times the @@ -343,9 +409,10 @@ prepare), or to restart per epoch. The node agent is asked whether the per-day r | Item | Owner | When | |---|---|---| -| PC 1 run of the five packs (the build-time rows, the v3 fingerprints on NVIDIA and AMD) | ca2-mixer, on the coordinator's go | after the era job, about 22:05 UTC | -| Quiet-box re-run of the verifier session for absolute numbers | ca2-mixer | when the Mac is quiet | -| The x4 / x8 choice recorded from the rule, then the vectors re-cut once through the seam | coordinator, then ca2-mixer | after the PC rows | +| PC 1 run of the five packs | done 22:04 UTC (run-mixer-x4-pc1-20261005; 6.5 and 6.2a) | | +| A verifier benchmark with a pinned bound in the crate's CI (section 6.6, the class rule) | ca2-mixer | the next cut | +| GPU bit-exactness of the re-exported mx8-devnet-epoch0 (the composed class, the era inside) and the mx4 record packs on the PCs (the Mac rows are in 6.2a) | ca2-mixer | the next PC round | +| The x4 / x8 choice recorded from the rule, then the vectors re-cut once through the seam | done 22:05 UTC: x8 (6.5), V3_CLASS = MX8, mx8 packs re-exported | | | `Epoch::chain_dataset_day` wired to the genesis day index in the node (`days_since_genesis(day_index(header), day_index(genesis))`) and `pow_genesis_dataset_log2` in the override | ca2-node | the integration | | The spec text of section 2 into `docs/spec/01-lottery-hash.md` 1.8.5 and 1.13.3 (with the v3 vectors into 1.17) | the integration | after the choice | | The 2019-class laptop core measurement that fixes the gate (O-1.14) | cryptographer | gate 1 | diff --git a/igneum-pow/src/generator.rs b/igneum-pow/src/generator.rs index 1ca1d894b..5201d950b 100644 --- a/igneum-pow/src/generator.rs +++ b/igneum-pow/src/generator.rs @@ -404,7 +404,7 @@ impl LoadClass { /// the per-warp verify stays under 10 ms on one Mac core and the daily 1 GiB build under 1 s on every card): /// the same loads and growth rule, the mixer applied 8 times per round. Name "mx8". pub const MX8: LoadClass = - LoadClass { mix: [100, 0, 0], load_slots: LOAD_SLOTS as u8, scratch: None, scratch_kb: 0, mixer_mult: 8, growth: true, era: None, hot: None }; + LoadClass { mixer_mult: 8, ..LoadClass::MX4 }; /// A fixed width (1, 4 or 16 words) with `load_slots` loads per program. pub fn fixed(width_words: u8, load_slots: u8) -> LoadClass { @@ -701,7 +701,7 @@ pub enum ProgramClass { /// placeholder of the seam (w16) is replaced here; nothing else in the seam names the class. /// Composed on 5 October 2026 (branch ca2-era): the era layout of `docs/plans/era-layout.md` is drawn inside this class by /// [`generate_from_seed_bytes_program_class`] (`LoadClass::era(V3_CLASS, era, &V3_ALLOWED)`); here `era` is `None`. -pub const V3_CLASS: LoadClass = LoadClass { era: None, hot: None, ..LoadClass::MX4 }; +pub const V3_CLASS: LoadClass = LoadClass { era: None, hot: None, ..LoadClass::MX8 }; /// The width set class v3's era draw chooses from: 4 bytes only (the read-width decision of 5 October 2026; the /// draw is consumed, so widening the set at genesis keeps the derivation). diff --git a/igneum-pow/src/memhard.rs b/igneum-pow/src/memhard.rs index 5a0ecd8a5..4458ab865 100644 --- a/igneum-pow/src/memhard.rs +++ b/igneum-pow/src/memhard.rs @@ -384,6 +384,13 @@ impl Cache { &self.words[o..o + 16] } + /// [`Cache::line`] with the mask as a constant (the verifier's hot path, see [`derive_items`]). + #[inline(always)] + pub fn line_const(&self, a: u32) -> &[u32] { + let o = (a & LINE_MASK) as usize * 16; + &self.words[o..o + 16] + } + /// FNV-1a 64 over the cache as little-endian bytes (what `vectors.h` carries as `IGNEUM_CACHE_FNV64`). pub fn fnv1a64(&self) -> u64 { fnv1a64_words(&self.words) @@ -474,8 +481,29 @@ impl HotTable { /// (`mp.shape.mixer_mult`) round `r` applies `M` with keys `round_key(r m + j)` for `j = 0 .. m - 1` before its /// one cache read; the final mixer applies `M` with keys `round_key(8 m + j)`. `m = 1` is version 2. pub fn derive_items(ts: &[u32], mp: &MixParams, cache: &Cache, out: &mut [[u32; 16]]) { + // The item loop lives in its own function, one instance per cache size the growth rule can reach with the line + // mask a constant, never inlined into the callers. Inlined into `MemhardCpu::fetch` it ran at 1.33 ms per unit + // against 0.61 out of line (the version 2 verifier, bisected on one core under the measure lock, 5 October 2026, + // `docs/plans/mixer-x4.md` section 6.6: the constant mask alone, or the mask hoisted into a local, or the + // constant with the loop still inlined, all stayed at 1.33; the out-of-line instances read 0.60 to 0.62). Any + // other cache size (tests) takes the instance with the run-time mask. + match cache.log2_words { + 26 => derive_items_mask::<{ (1u32 << 22) - 1 }>(ts, mp, cache, out), + 27 => derive_items_mask::<{ (1u32 << 23) - 1 }>(ts, mp, cache, out), + 28 => derive_items_mask::<{ (1u32 << 24) - 1 }>(ts, mp, cache, out), + 29 => derive_items_mask::<{ (1u32 << 25) - 1 }>(ts, mp, cache, out), + 30 => derive_items_mask::<{ (1u32 << 26) - 1 }>(ts, mp, cache, out), + _ => derive_items_mask::<0>(ts, mp, cache, out), + } +} + +/// [`derive_items`] with the cache line mask as a constant (`LINE_MASK = 0`: the cache's own run-time mask). Kept +/// out of line on purpose (see [`derive_items`]). +#[inline(never)] +fn derive_items_mask(ts: &[u32], mp: &MixParams, cache: &Cache, out: &mut [[u32; 16]]) { let n = ts.len(); debug_assert!(out.len() >= n); + debug_assert!(LINE_MASK == 0 || LINE_MASK == cache.line_mask); let m = mp.shape.mixer_mult as usize; for k in 0..n { let s = &mut out[k]; @@ -493,7 +521,7 @@ pub fn derive_items(ts: &[u32], mp: &MixParams, cache: &Cache, out: &mut [[u32; } } for s in out[..n].iter_mut() { - let line = cache.line(s[0]); + let line = if LINE_MASK != 0 { cache.line_const::(s[0]) } else { cache.line(s[0]) }; for i in 0..16 { s[i] ^= line[i]; } diff --git a/igneum-pow/tests/mixer.rs b/igneum-pow/tests/mixer.rs index 78de4768f..e3f090b87 100644 --- a/igneum-pow/tests/mixer.rs +++ b/igneum-pow/tests/mixer.rs @@ -236,7 +236,7 @@ fn determinism_v3() { for (w, warp) in [(0u32, 0usize), (4096, 1), (1_000_000, 2)] { assert_eq!(a.hash_warp(w), pa.outs[warp]); } - let dir = PathBuf::from(env!("CARGO_MANIFEST_DIR")).join("../proto-cuda/packs-ca2-mixer/mx4-genesis"); + let dir = PathBuf::from(env!("CARGO_MANIFEST_DIR")).join("../proto-cuda/packs-ca2-mixer/mx8-genesis"); for (name, text) in &pa.files { if name == "vectors.json" || name == "vectors.h" { continue; // the source string differs ("a" here) diff --git a/igneum-pow/tests/packs.rs b/igneum-pow/tests/packs.rs index f03cf6436..d461bae42 100644 --- a/igneum-pow/tests/packs.rs +++ b/igneum-pow/tests/packs.rs @@ -5,10 +5,11 @@ //! //! Packs: igneum-genesis-mh and igneum-devnet-v4-epoch0 (memory-hard; the latter from the devnet genesis hash as //! the epoch seed and the day bytes of 2026-10-04), igneum-genesis and igneum-hourly (closed-form dataset, -//! interpreter regression only); and, under `proto-cuda/packs-ca2-mixer/`, the class v3 packs mx4-genesis and -//! mx4-devnet-epoch0 (Counter ASIC 2.0, 5 October 2026: generator 3 on `V3_CLASS` = mixer x4 with the cache growth -//! rule, the same seeds and days as the two memory-hard v2 packs, so the v2 program and cache carry over and only -//! the dataset words and the hashes change). +//! interpreter regression only); and, under `proto-cuda/packs-ca2-mixer/`, the class v3 packs mx8-genesis and +//! mx8-devnet-epoch0 (Counter ASIC 2.0, 5 October 2026: generator 3 on `V3_CLASS` = mixer x8 with the cache growth +//! rule, decided 22:05 UTC under the delegated rule; the same seeds and days as the two memory-hard v2 packs, so the +//! v2 program and cache carry over and only the dataset words and the hashes change) and the x4 candidate's packs +//! mx4-genesis and mx4-devnet-epoch0 (generator 2 with the load class in the id, the record of the x4 rows). use igneum_pow::accept; use igneum_pow::emit::{ @@ -22,10 +23,18 @@ use serde_json::Value; use std::path::PathBuf; use std::sync::OnceLock; -const PACKS: [&str; 6] = - ["igneum-genesis-mh", "igneum-devnet-v4-epoch0", "igneum-genesis", "igneum-hourly", "mx4-genesis", "mx4-devnet-epoch0"]; -/// The class v3 packs (the last two of `PACKS`). -const PACKS_V3: [&str; 2] = ["mx4-genesis", "mx4-devnet-epoch0"]; +const PACKS: [&str; 8] = [ + "igneum-genesis-mh", + "igneum-devnet-v4-epoch0", + "igneum-genesis", + "igneum-hourly", + "mx8-genesis", + "mx8-devnet-epoch0", + "mx4-genesis", + "mx4-devnet-epoch0", +]; +/// The class v3 packs (generator 3 through the seam). +const PACKS_V3: [&str; 2] = ["mx8-genesis", "mx8-devnet-epoch0"]; fn packs_dir() -> PathBuf { PathBuf::from(env!("CARGO_MANIFEST_DIR")).join("../proto-cuda/packs") @@ -33,7 +42,7 @@ fn packs_dir() -> PathBuf { /// The directory a pack lives in: the class v3 packs under packs-ca2-mixer, the rest under packs. fn pack_dir(pack: &str) -> PathBuf { - if pack.starts_with("mx4-") { + if pack.starts_with("mx4-") || pack.starts_with("mx8-") { PathBuf::from(env!("CARGO_MANIFEST_DIR")).join("../proto-cuda/packs-ca2-mixer").join(pack) } else { packs_dir().join(pack) @@ -84,7 +93,11 @@ fn epoch(pack: &str) -> &'static Epoch { let era = j.get("era_seed_bytes").map(unhex); generate_from_seed_bytes_program_class(seed, &seed_bytes, ProgramClass::V3, era.as_deref()) } - _ => generate_from_seed_bytes(seed, &seed_bytes), + // a generator 2 pack with a load class (the x4 candidate's packs): the class from program.json + _ => match j.get("load_class").and_then(|c| c.as_str()) { + Some(c) => generate_from_seed_bytes_class(seed, &seed_bytes, LoadClass::parse(c).expect("a load class name")), + None => generate_from_seed_bytes(seed, &seed_bytes), + }, }; let shape = Shape::for_class(&program.class); let mut dataset = @@ -154,7 +167,7 @@ fn genesis_program_shape() { #[test] fn mixer_params_match_pack() { - for pack in ["igneum-genesis-mh", "igneum-devnet-v4-epoch0", "mx4-genesis", "mx4-devnet-epoch0"] { + for pack in ["igneum-genesis-mh", "igneum-devnet-v4-epoch0", "mx8-genesis", "mx8-devnet-epoch0", "mx4-genesis", "mx4-devnet-epoch0"] { let j = json(pack, "program.json"); let mp = &epoch(pack).dataset.memhard().unwrap().params; let key: Vec = j["dataset"]["key"].as_array().unwrap().iter().map(hex32).collect(); @@ -318,24 +331,25 @@ fn emitted_sources_match_all_packs() { } /// The whole pack as `export` writes it: vectors.json and vectors.h match, and the file list is the full set. -/// The class v3 packs (Counter ASIC 2.0, `docs/plans/mixer-x4.md`): generator 3 on V3_CLASS = mx4; the program of +/// The class v3 packs (Counter ASIC 2.0, `docs/plans/mixer-x4.md`): generator 3 on V3_CLASS = mx8; the program of /// each is the v2 program of the same seed instruction for instruction (v2 loads take no width roll); the cache is /// the v2 cache (day 0 of the growth rule: 2^26 words, the same FNV-1a 64); the dataset words differ from v2's; /// program.json, program.h and the emitted memhard core say so; the id carries generator 3. #[test] -fn v3_packs_are_the_v2_seeds_under_mixer_x4() { - assert_eq!(V3_CLASS.name(), "mx4"); - assert_eq!(V3_CLASS.mixer_mult, 4); +fn v3_packs_are_the_v2_seeds_under_mixer_x8() { + assert_eq!(V3_CLASS.name(), "mx8"); + assert_eq!(V3_CLASS.mixer_mult, 8); assert!(V3_CLASS.growth); - for (v3, v2) in [("mx4-genesis", "igneum-genesis-mh"), ("mx4-devnet-epoch0", "igneum-devnet-v4-epoch0")] { + assert_eq!(LoadClass { mixer_mult: 4, ..V3_CLASS }, LoadClass::MX4, "the x4 candidate differs from v3 in the multiplier alone"); + for (v3, v2) in [("mx8-genesis", "igneum-genesis-mh"), ("mx8-devnet-epoch0", "igneum-devnet-v4-epoch0")] { let e3 = epoch(v3); let e2 = epoch(v2); let j = json(v3, "program.json"); assert_eq!(j["program_class"].as_str().unwrap(), "v3"); - assert!(j["load_class"].as_str().unwrap().starts_with("mx4"), "{v3}: mx4, or mx4 with the era inside"); - assert_eq!(j["mixer_mult"].as_u64().unwrap(), 4); + assert!(j["load_class"].as_str().unwrap().starts_with("mx8"), "{v3}: mx8, or mx8 with the era inside"); + assert_eq!(j["mixer_mult"].as_u64().unwrap(), 8); assert_eq!(j["cache_growth"].as_bool().unwrap(), true); - assert_eq!(j["dataset"]["mixer_mult"].as_u64().unwrap(), 4); + assert_eq!(j["dataset"]["mixer_mult"].as_u64().unwrap(), 8); assert_eq!(j["dataset"]["cache"]["log2_words"].as_u64().unwrap(), 26); assert_eq!(e3.program.generator, GENERATOR_VERSION_V3); if e3.program.era_bytes.is_some() { @@ -355,7 +369,7 @@ fn v3_packs_are_the_v2_seeds_under_mixer_x4() { assert_eq!(e3.program.program_id(), igneum_pow::generator::program_id(GENERATOR_VERSION_V3, &e3.program.seed, e3.program.attempt)); let m3 = e3.dataset.memhard().unwrap(); let m2 = e2.dataset.memhard().unwrap(); - assert_eq!(m3.shape(), Shape { mixer_mult: 4, cache_log2_words: 26 }); + assert_eq!(m3.shape(), Shape { mixer_mult: 8, cache_log2_words: 26 }); assert_eq!(m3.cache.fnv1a64(), m2.cache.fnv1a64(), "{v3}: the same cache as v2 on day 0"); assert_eq!(m3.params.rot, m2.params.rot); assert_eq!(e3.dataset.log2_words, 28); @@ -364,25 +378,36 @@ fn v3_packs_are_the_v2_seeds_under_mixer_x4() { let h = read(v3, "program.h"); assert!(h.contains("#define IGNEUM_GENERATOR 3\n")); assert!(h.contains("#define IGNEUM_PROGRAM_CLASS \"v3\"\n")); - assert!(h.contains("#define IGNEUM_MIXER_MULT 4")); + assert!(h.contains("#define IGNEUM_MIXER_MULT 8")); assert!(h.contains("#define IGNEUM_CACHE_GROWTH 1")); assert!(h.contains("#define IGNEUM_CACHE_LOG2_WORDS 26\n")); - assert!(h.contains("#define IGNEUM_LOAD_CLASS \"mx4"), "mx4, or mx4 with the era inside"); + assert!(h.contains("#define IGNEUM_LOAD_CLASS \"mx8"), "mx8, or mx8 with the era inside"); for file in ["memhard.h", "memhard.metal", "kernel.cl"] { let text = read(v3, file); - assert_eq!(text.matches("j < 4u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 4u + j + 1u))").count(), 1, "{v3}/{file}"); - assert_eq!(text.matches("j < 4u; ++j) mh_mixer(s, 0x9E3779B9u * (32u + j + 1u))").count(), 1, "{v3}/{file}"); + assert_eq!(text.matches("j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u))").count(), 1, "{v3}/{file}"); + assert_eq!(text.matches("j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u))").count(), 1, "{v3}/{file}"); } for file in ["memhard.h", "memhard.metal", "kernel.cl"] { let text = read(v2, file); - assert_eq!(text.matches("j < 4u").count(), 0, "{v2}/{file}: the v2 text has no multiplier loop"); + assert_eq!(text.matches("j < 8u").count(), 0, "{v2}/{file}: the v2 text has no multiplier loop"); } } // the devnet v3 pack records era 0's stand-in, the devnet genesis hash - let j = json("mx4-devnet-epoch0", "program.json"); + let j = json("mx8-devnet-epoch0", "program.json"); assert_eq!(unhex(&j["era_seed_bytes"]), unhex(&j["seed_bytes"])); - assert!(read("mx4-devnet-epoch0", "program.h").contains("#define IGNEUM_ERA_SEED_HEX \"edc4fa844da9dc98")); - assert!(json("mx4-genesis", "program.json").get("era_seed_bytes").is_none()); + assert!(read("mx8-devnet-epoch0", "program.h").contains("#define IGNEUM_ERA_SEED_HEX \"edc4fa844da9dc98")); + assert!(json("mx8-genesis", "program.json").get("era_seed_bytes").is_none()); + // the x4 candidate's packs: generator 2, the class in the id, the v2 program of the seed, mixer x4 + for (x4, v2) in [("mx4-genesis", "igneum-genesis-mh"), ("mx4-devnet-epoch0", "igneum-devnet-v4-epoch0")] { + let e4 = epoch(x4); + let j = json(x4, "program.json"); + assert_eq!(e4.program.generator, GENERATOR_VERSION); + assert_eq!(j["load_class"].as_str().unwrap(), "mx4"); + assert_eq!(e4.program.class, LoadClass::MX4); + assert_eq!(e4.program.instrs, epoch(v2).program.instrs); + assert_eq!(e4.dataset.memhard().unwrap().shape(), Shape { mixer_mult: 4, cache_log2_words: 26 }); + assert!(read(x4, "memhard.h").contains("j < 4u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 4u + j + 1u))")); + } } fn check_export(pack: &str) { diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cl b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cl index 68d88081b..a32be499b 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cl +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cl @@ -155,12 +155,8 @@ static inline void mh_item(__global const uint* cache, uint t, uint* s) { } for (uint j = 0u; j < 4u; ++j) mh_mixer(s, 0x9E3779B9u * (32u + j + 1u)); } -// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. -static inline uint mh_j(uint w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } -static inline uint mh_t(uint w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } -static inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } -// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). -static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } +// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. +static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } // Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item. // The same constants as memhard.h in this pack (one emitter, three dialects). @@ -173,7 +169,8 @@ __kernel void igneum_build(__global uint* ds, __global const uint* cache, uint n if (t < nItems) { uint s[16]; mh_item(cache, t, s); - for (uint i = 0u; i < 16u; ++i) ds[(ulong)mh_addr(t, i)] = s[i]; + __global uint* d = ds + ((ulong)t * 16u); + for (uint i = 0u; i < 16u; ++i) d[i] = s[i]; } } @@ -203,69 +200,69 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - r7 = r7 ^ r0; // 1 xor - { uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // 2 shfl - r4 = r4 - r1; // 3 sub - r2 = r0 * r4 + r2; // 4 mad - r4 = rotl_imm(r4, 9u); // 5 rotl - r0 = rotr_var(r0, r2); // 6 rotr - r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load - r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load - r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load - r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load - r5 = r5 * r4; // 12 mul - r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load - { uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl - { uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl - r2 = r2 | r7; // 16 or - r0 = rotr_var(r0, r6); // 17 rotr - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add - r7 = rotl_imm(r7, 24u); // 19 rotl - r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add - r2 = r2 | r6; // 21 or - r6 = r5 * r4 + r6; // 22 mad - r1 = r1 | r0; // 23 or - r6 = r6 ^ r1; // 24 xor - r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add - r7 = rotr_var(r7, r0); // 26 rotr - r4 = r5 * r7 + r4; // 27 mad - r3 = r2 * r4 + r3; // 28 mad - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load - r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load - r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load - r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add - r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add - r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add - r2 = mul_hi(r2, r5); // 35 mulhi - r4 = r4 ^ r2; // 36 xor - r6 = r6 * r5; // 37 mul - r7 = r7 ^ r0; // 38 xor - r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add - r2 = rotr_var(r2, r3); // 40 rotr - r7 = r7 - r0; // 41 sub - r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add - { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl - r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add - r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load - r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load - r4 = mul_hi(r4, r2); // 48 mulhi - r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl - r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add - r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load - r6 = rotl_imm(r6, 12u); // 53 rotl - r3 = rotl_imm(r3, 12u); // 54 rotl - r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load - r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add - r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load - r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add - r3 = mul_hi(r3, r2); // 60 mulhi - r6 = r6 | r4; // 61 or - { uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl - r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load + { uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // 1 shfl + r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add + r0 = rotl_imm(r0, 19u); // 3 rotl + r7 = rotr_var(r7, r6); // 4 rotr + r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add + r1 = mul_hi(r1, r7); // 6 mulhi + r4 = r4 ^ ds[r2 & mask]; // 7 load + r7 = r7 ^ ds[r4 & mask]; // 8 load + r0 = r0 ^ ds[r3 & mask]; // 9 load + r5 = r5 ^ ds[r1 & mask]; // 10 load + r1 = r1 ^ ds[r5 & mask]; // 11 load + r3 = mul_hi(r3, r5); // 12 mulhi + r1 = r1 ^ ds[r3 & mask]; // 13 load + r0 = r0 - r3; // 14 sub + r5 = r1 * r3 + r5; // 15 mad + r6 = mul_hi(r6, r1); // 16 mulhi + r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add + r0 = mul_hi(r0, r6); // 18 mulhi + r5 = rotr_var(r5, r3); // 19 rotr + r5 = mul_hi(r5, r2); // 20 mulhi + r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add + r1 = mul_hi(r1, r5); // 23 mulhi + r2 = r2 - r5; // 24 sub + r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add + { uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 26 shfl + r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add + r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add + r2 = r2 ^ ds[r1 & mask]; // 29 load + r5 = r5 ^ ds[r7 & mask]; // 30 load + r2 = r2 ^ ds[r5 & mask]; // 31 load + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r1 = r1 ^ t_; } // 32 shfl + r4 = r5 * r7 + r4; // 33 mad + r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r3 = r3 ^ t_; } // 35 shfl + r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add + r5 = r5 ^ r7; // 37 xor + r2 = r2 | r1; // 38 or + r1 = mul_hi(r1, r0); // 39 mulhi + r6 = rotl_imm(r6, 19u); // 40 rotl + r4 = mul_hi(r4, r6); // 41 mulhi + r6 = r6 - r0; // 42 sub + { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r6 = r6 ^ t_; } // 43 shfl + r4 = r4 ^ ds[r2 & mask]; // 44 load + r1 = r1 ^ r3; // 45 xor + r7 = r7 ^ ds[r0 & mask]; // 46 load + r3 = r3 ^ ds[r1 & mask]; // 47 load + r5 = r5 * r3; // 48 mul + r1 = r1 - r5; // 49 sub + r2 = rotl_imm(r2, 8u); // 50 rotl + r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add + r4 = r4 ^ ds[r7 & mask]; // 52 load + r2 = r2 - r7; // 53 sub + r4 = r4 ^ r0; // 54 xor + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add + r2 = r2 ^ ds[r4 & mask]; // 56 load + r0 = r1 * r4 + r0; // 57 mad + r3 = r3 ^ ds[r5 & mask]; // 58 load + r5 = r5 | r6; // 59 or + r6 = r5 * r7 + r6; // 60 mad + r4 = rotl_imm(r4, 28u); // 61 rotl + r5 = mul_hi(r5, r0); // 62 mulhi + r3 = r3 ^ ds[r6 & mask]; // 63 load } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cu b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cu index 2a0422763..c129edeec 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cu +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel.cu @@ -36,7 +36,8 @@ __global__ void igneum_build(uint32_t* ds, const uint32_t* cache, uint32_t nItem if (t < nItems) { uint32_t s[16]; mh_item(cache, t, s); - for (uint32_t i = 0u; i < 16u; ++i) ds[(size_t)mh_addr(t, i)] = s[i]; + uint32_t* d = ds + (size_t)t * 16u; + for (uint32_t i = 0u; i < 16u; ++i) d[i] = s[i]; } } @@ -59,69 +60,69 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc for (uint32_t it = 0u; it < 8u; ++it) { uint32_t sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - r7 = r7 ^ r0; // 1 xor - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // 2 shfl - r4 = r4 - r1; // 3 sub - r2 = r0 * r4 + r2; // 4 mad - r4 = rotl_imm(r4, 9u); // 5 rotl - r0 = rotr_var(r0, r2); // 6 rotr - r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load - r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load - r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load - r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load - r5 = r5 * r4; // 12 mul - r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load - r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl - r2 = r2 | r7; // 16 or - r0 = rotr_var(r0, r6); // 17 rotr - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add - r7 = rotl_imm(r7, 24u); // 19 rotl - r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add - r2 = r2 | r6; // 21 or - r6 = r5 * r4 + r6; // 22 mad - r1 = r1 | r0; // 23 or - r6 = r6 ^ r1; // 24 xor - r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add - r7 = rotr_var(r7, r0); // 26 rotr - r4 = r5 * r7 + r4; // 27 mad - r3 = r2 * r4 + r3; // 28 mad - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load - r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load - r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load - r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add - r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add - r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add - r2 = __umulhi(r2, r5); // 35 mulhi - r4 = r4 ^ r2; // 36 xor - r6 = r6 * r5; // 37 mul - r7 = r7 ^ r0; // 38 xor - r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add - r2 = rotr_var(r2, r3); // 40 rotr - r7 = r7 - r0; // 41 sub - r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add - r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl - r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add - r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load - r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load - r4 = __umulhi(r4, r2); // 48 mulhi - r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add - r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl - r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add - r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load - r6 = rotl_imm(r6, 12u); // 53 rotl - r3 = rotl_imm(r3, 12u); // 54 rotl - r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load - r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add - r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load - r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add - r3 = __umulhi(r3, r2); // 60 mulhi - r6 = r6 | r4; // 61 or - r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl - r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load + r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // 1 shfl + r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add + r0 = rotl_imm(r0, 19u); // 3 rotl + r7 = rotr_var(r7, r6); // 4 rotr + r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add + r1 = __umulhi(r1, r7); // 6 mulhi + r4 = r4 ^ ds[r2 & mask]; // 7 load + r7 = r7 ^ ds[r4 & mask]; // 8 load + r0 = r0 ^ ds[r3 & mask]; // 9 load + r5 = r5 ^ ds[r1 & mask]; // 10 load + r1 = r1 ^ ds[r5 & mask]; // 11 load + r3 = __umulhi(r3, r5); // 12 mulhi + r1 = r1 ^ ds[r3 & mask]; // 13 load + r0 = r0 - r3; // 14 sub + r5 = r1 * r3 + r5; // 15 mad + r6 = __umulhi(r6, r1); // 16 mulhi + r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add + r0 = __umulhi(r0, r6); // 18 mulhi + r5 = rotr_var(r5, r3); // 19 rotr + r5 = __umulhi(r5, r2); // 20 mulhi + r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add + r1 = __umulhi(r1, r5); // 23 mulhi + r2 = r2 - r5; // 24 sub + r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 26 shfl + r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add + r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add + r2 = r2 ^ ds[r1 & mask]; // 29 load + r5 = r5 ^ ds[r7 & mask]; // 30 load + r2 = r2 ^ ds[r5 & mask]; // 31 load + r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 32 shfl + r4 = r5 * r7 + r4; // 33 mad + r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r7, 8); // 35 shfl + r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add + r5 = r5 ^ r7; // 37 xor + r2 = r2 | r1; // 38 or + r1 = __umulhi(r1, r0); // 39 mulhi + r6 = rotl_imm(r6, 19u); // 40 rotl + r4 = __umulhi(r4, r6); // 41 mulhi + r6 = r6 - r0; // 42 sub + r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl + r4 = r4 ^ ds[r2 & mask]; // 44 load + r1 = r1 ^ r3; // 45 xor + r7 = r7 ^ ds[r0 & mask]; // 46 load + r3 = r3 ^ ds[r1 & mask]; // 47 load + r5 = r5 * r3; // 48 mul + r1 = r1 - r5; // 49 sub + r2 = rotl_imm(r2, 8u); // 50 rotl + r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add + r4 = r4 ^ ds[r7 & mask]; // 52 load + r2 = r2 - r7; // 53 sub + r4 = r4 ^ r0; // 54 xor + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add + r2 = r2 ^ ds[r4 & mask]; // 56 load + r0 = r1 * r4 + r0; // 57 mad + r3 = r3 ^ ds[r5 & mask]; // 58 load + r5 = r5 | r6; // 59 or + r6 = r5 * r7 + r6; // 60 mad + r4 = rotl_imm(r4, 28u); // 61 rotl + r5 = __umulhi(r5, r0); // 62 mulhi + r3 = r3 ^ ds[r6 & mask]; // 63 load } uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cl b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cl index bc66d9ebc..3ae5ef119 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cl +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cl @@ -155,12 +155,8 @@ static inline void mh_item(__global const uint* cache, uint t, uint* s) { } for (uint j = 0u; j < 4u; ++j) mh_mixer(s, 0x9E3779B9u * (32u + j + 1u)); } -// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. -static inline uint mh_j(uint w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } -static inline uint mh_t(uint w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } -static inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } -// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). -static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } +// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. +static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } // Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item. // The same constants as memhard.h in this pack (one emitter, three dialects). @@ -173,7 +169,8 @@ __kernel void igneum_build(__global uint* ds, __global const uint* cache, uint n if (t < nItems) { uint s[16]; mh_item(cache, t, s); - for (uint i = 0u; i < 16u; ++i) ds[(ulong)mh_addr(t, i)] = s[i]; + __global uint* d = ds + ((ulong)t * 16u); + for (uint i = 0u; i < 16u; ++i) d[i] = s[i]; } } @@ -203,69 +200,69 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - r7 = r7 ^ r0; // 1 xor - { uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // 2 shfl - r4 = r4 - r1; // 3 sub - r2 = r0 * r4 + r2; // 4 mad - r4 = rotl_imm(r4, 9u); // 5 rotl - r0 = rotr_var(r0, r2); // 6 rotr - r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load - r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load - r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load - r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load - r5 = r5 * r4; // 12 mul - r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load - { uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl - { uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl - r2 = r2 | r7; // 16 or - r0 = rotr_var(r0, r6); // 17 rotr - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add - r7 = rotl_imm(r7, 24u); // 19 rotl - r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add - r2 = r2 | r6; // 21 or - r6 = r5 * r4 + r6; // 22 mad - r1 = r1 | r0; // 23 or - r6 = r6 ^ r1; // 24 xor - r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add - r7 = rotr_var(r7, r0); // 26 rotr - r4 = r5 * r7 + r4; // 27 mad - r3 = r2 * r4 + r3; // 28 mad - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load - r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load - r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load - r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add - r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add - r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add - r2 = mul_hi(r2, r5); // 35 mulhi - r4 = r4 ^ r2; // 36 xor - r6 = r6 * r5; // 37 mul - r7 = r7 ^ r0; // 38 xor - r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add - r2 = rotr_var(r2, r3); // 40 rotr - r7 = r7 - r0; // 41 sub - r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add - { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl - r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add - r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load - r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load - r4 = mul_hi(r4, r2); // 48 mulhi - r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl - r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add - r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load - r6 = rotl_imm(r6, 12u); // 53 rotl - r3 = rotl_imm(r3, 12u); // 54 rotl - r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load - r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add - r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load - r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add - r3 = mul_hi(r3, r2); // 60 mulhi - r6 = r6 | r4; // 61 or - { uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl - r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load + { uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // 1 shfl + r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add + r0 = rotl_imm(r0, 19u); // 3 rotl + r7 = rotr_var(r7, r6); // 4 rotr + r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add + r1 = mul_hi(r1, r7); // 6 mulhi + r4 = r4 ^ ds[r2 & mask]; // 7 load + r7 = r7 ^ ds[r4 & mask]; // 8 load + r0 = r0 ^ ds[r3 & mask]; // 9 load + r5 = r5 ^ ds[r1 & mask]; // 10 load + r1 = r1 ^ ds[r5 & mask]; // 11 load + r3 = mul_hi(r3, r5); // 12 mulhi + r1 = r1 ^ ds[r3 & mask]; // 13 load + r0 = r0 - r3; // 14 sub + r5 = r1 * r3 + r5; // 15 mad + r6 = mul_hi(r6, r1); // 16 mulhi + r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add + r0 = mul_hi(r0, r6); // 18 mulhi + r5 = rotr_var(r5, r3); // 19 rotr + r5 = mul_hi(r5, r2); // 20 mulhi + r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add + r1 = mul_hi(r1, r5); // 23 mulhi + r2 = r2 - r5; // 24 sub + r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add + { uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 26 shfl + r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add + r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add + r2 = r2 ^ ds[r1 & mask]; // 29 load + r5 = r5 ^ ds[r7 & mask]; // 30 load + r2 = r2 ^ ds[r5 & mask]; // 31 load + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r1 = r1 ^ t_; } // 32 shfl + r4 = r5 * r7 + r4; // 33 mad + r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r3 = r3 ^ t_; } // 35 shfl + r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add + r5 = r5 ^ r7; // 37 xor + r2 = r2 | r1; // 38 or + r1 = mul_hi(r1, r0); // 39 mulhi + r6 = rotl_imm(r6, 19u); // 40 rotl + r4 = mul_hi(r4, r6); // 41 mulhi + r6 = r6 - r0; // 42 sub + { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r6 = r6 ^ t_; } // 43 shfl + r4 = r4 ^ ds[r2 & mask]; // 44 load + r1 = r1 ^ r3; // 45 xor + r7 = r7 ^ ds[r0 & mask]; // 46 load + r3 = r3 ^ ds[r1 & mask]; // 47 load + r5 = r5 * r3; // 48 mul + r1 = r1 - r5; // 49 sub + r2 = rotl_imm(r2, 8u); // 50 rotl + r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add + r4 = r4 ^ ds[r7 & mask]; // 52 load + r2 = r2 - r7; // 53 sub + r4 = r4 ^ r0; // 54 xor + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add + r2 = r2 ^ ds[r4 & mask]; // 56 load + r0 = r1 * r4 + r0; // 57 mad + r3 = r3 ^ ds[r5 & mask]; // 58 load + r5 = r5 | r6; // 59 or + r6 = r5 * r7 + r6; // 60 mad + r4 = rotl_imm(r4, 28u); // 61 rotl + r5 = mul_hi(r5, r0); // 62 mulhi + r3 = r3 ^ ds[r6 & mask]; // 63 load } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); @@ -306,69 +303,69 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - r7 = r7 ^ r0; // 1 xor - { uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // 2 shfl - r4 = r4 - r1; // 3 sub - r2 = r0 * r4 + r2; // 4 mad - r4 = rotl_imm(r4, 9u); // 5 rotl - r0 = rotr_var(r0, r2); // 6 rotr - r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load - r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load - r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load - r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load - r5 = r5 * r4; // 12 mul - r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load - { uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl - { uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl - r2 = r2 | r7; // 16 or - r0 = rotr_var(r0, r6); // 17 rotr - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add - r7 = rotl_imm(r7, 24u); // 19 rotl - r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add - r2 = r2 | r6; // 21 or - r6 = r5 * r4 + r6; // 22 mad - r1 = r1 | r0; // 23 or - r6 = r6 ^ r1; // 24 xor - r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add - r7 = rotr_var(r7, r0); // 26 rotr - r4 = r5 * r7 + r4; // 27 mad - r3 = r2 * r4 + r3; // 28 mad - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load - r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load - r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load - r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add - r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add - r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add - r2 = mul_hi(r2, r5); // 35 mulhi - r4 = r4 ^ r2; // 36 xor - r6 = r6 * r5; // 37 mul - r7 = r7 ^ r0; // 38 xor - r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add - r2 = rotr_var(r2, r3); // 40 rotr - r7 = r7 - r0; // 41 sub - r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add - { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl - r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add - r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load - r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load - r4 = mul_hi(r4, r2); // 48 mulhi - r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl - r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add - r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load - r6 = rotl_imm(r6, 12u); // 53 rotl - r3 = rotl_imm(r3, 12u); // 54 rotl - r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load - r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add - r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load - r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add - r3 = mul_hi(r3, r2); // 60 mulhi - r6 = r6 | r4; // 61 or - { uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl - r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load + { uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // 1 shfl + r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add + r0 = rotl_imm(r0, 19u); // 3 rotl + r7 = rotr_var(r7, r6); // 4 rotr + r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add + r1 = mul_hi(r1, r7); // 6 mulhi + r4 = r4 ^ ds[r2 & mask]; // 7 load + r7 = r7 ^ ds[r4 & mask]; // 8 load + r0 = r0 ^ ds[r3 & mask]; // 9 load + r5 = r5 ^ ds[r1 & mask]; // 10 load + r1 = r1 ^ ds[r5 & mask]; // 11 load + r3 = mul_hi(r3, r5); // 12 mulhi + r1 = r1 ^ ds[r3 & mask]; // 13 load + r0 = r0 - r3; // 14 sub + r5 = r1 * r3 + r5; // 15 mad + r6 = mul_hi(r6, r1); // 16 mulhi + r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add + r0 = mul_hi(r0, r6); // 18 mulhi + r5 = rotr_var(r5, r3); // 19 rotr + r5 = mul_hi(r5, r2); // 20 mulhi + r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add + r1 = mul_hi(r1, r5); // 23 mulhi + r2 = r2 - r5; // 24 sub + r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add + { uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 26 shfl + r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add + r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add + r2 = r2 ^ ds[r1 & mask]; // 29 load + r5 = r5 ^ ds[r7 & mask]; // 30 load + r2 = r2 ^ ds[r5 & mask]; // 31 load + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r1 = r1 ^ t_; } // 32 shfl + r4 = r5 * r7 + r4; // 33 mad + r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r3 = r3 ^ t_; } // 35 shfl + r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add + r5 = r5 ^ r7; // 37 xor + r2 = r2 | r1; // 38 or + r1 = mul_hi(r1, r0); // 39 mulhi + r6 = rotl_imm(r6, 19u); // 40 rotl + r4 = mul_hi(r4, r6); // 41 mulhi + r6 = r6 - r0; // 42 sub + { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r6 = r6 ^ t_; } // 43 shfl + r4 = r4 ^ ds[r2 & mask]; // 44 load + r1 = r1 ^ r3; // 45 xor + r7 = r7 ^ ds[r0 & mask]; // 46 load + r3 = r3 ^ ds[r1 & mask]; // 47 load + r5 = r5 * r3; // 48 mul + r1 = r1 - r5; // 49 sub + r2 = rotl_imm(r2, 8u); // 50 rotl + r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add + r4 = r4 ^ ds[r7 & mask]; // 52 load + r2 = r2 - r7; // 53 sub + r4 = r4 ^ r0; // 54 xor + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add + r2 = r2 ^ ds[r4 & mask]; // 56 load + r0 = r1 * r4 + r0; // 57 mad + r3 = r3 ^ ds[r5 & mask]; // 58 load + r5 = r5 | r6; // 59 or + r6 = r5 * r7 + r6; // 60 mad + r4 = rotl_imm(r4, 28u); // 61 rotl + r5 = mul_hi(r5, r0); // 62 mulhi + r3 = r3 ^ ds[r6 & mask]; // 63 load } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cu b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cu index af9003761..9a46b7480 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cu +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/kernel_bound.cu @@ -36,69 +36,69 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba for (uint32_t it = 0u; it < 8u; ++it) { uint32_t sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - r7 = r7 ^ r0; // 1 xor - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // 2 shfl - r4 = r4 - r1; // 3 sub - r2 = r0 * r4 + r2; // 4 mad - r4 = rotl_imm(r4, 9u); // 5 rotl - r0 = rotr_var(r0, r2); // 6 rotr - r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load - r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load - r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load - r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load - r5 = r5 * r4; // 12 mul - r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load - r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl - r2 = r2 | r7; // 16 or - r0 = rotr_var(r0, r6); // 17 rotr - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add - r7 = rotl_imm(r7, 24u); // 19 rotl - r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add - r2 = r2 | r6; // 21 or - r6 = r5 * r4 + r6; // 22 mad - r1 = r1 | r0; // 23 or - r6 = r6 ^ r1; // 24 xor - r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add - r7 = rotr_var(r7, r0); // 26 rotr - r4 = r5 * r7 + r4; // 27 mad - r3 = r2 * r4 + r3; // 28 mad - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load - r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load - r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load - r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add - r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add - r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add - r2 = __umulhi(r2, r5); // 35 mulhi - r4 = r4 ^ r2; // 36 xor - r6 = r6 * r5; // 37 mul - r7 = r7 ^ r0; // 38 xor - r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add - r2 = rotr_var(r2, r3); // 40 rotr - r7 = r7 - r0; // 41 sub - r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add - r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl - r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add - r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load - r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load - r4 = __umulhi(r4, r2); // 48 mulhi - r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add - r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl - r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add - r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load - r6 = rotl_imm(r6, 12u); // 53 rotl - r3 = rotl_imm(r3, 12u); // 54 rotl - r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add - r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load - r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add - r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load - r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add - r3 = __umulhi(r3, r2); // 60 mulhi - r6 = r6 | r4; // 61 or - r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl - r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load + r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // 1 shfl + r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add + r0 = rotl_imm(r0, 19u); // 3 rotl + r7 = rotr_var(r7, r6); // 4 rotr + r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add + r1 = __umulhi(r1, r7); // 6 mulhi + r4 = r4 ^ ds[r2 & mask]; // 7 load + r7 = r7 ^ ds[r4 & mask]; // 8 load + r0 = r0 ^ ds[r3 & mask]; // 9 load + r5 = r5 ^ ds[r1 & mask]; // 10 load + r1 = r1 ^ ds[r5 & mask]; // 11 load + r3 = __umulhi(r3, r5); // 12 mulhi + r1 = r1 ^ ds[r3 & mask]; // 13 load + r0 = r0 - r3; // 14 sub + r5 = r1 * r3 + r5; // 15 mad + r6 = __umulhi(r6, r1); // 16 mulhi + r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add + r0 = __umulhi(r0, r6); // 18 mulhi + r5 = rotr_var(r5, r3); // 19 rotr + r5 = __umulhi(r5, r2); // 20 mulhi + r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add + r1 = __umulhi(r1, r5); // 23 mulhi + r2 = r2 - r5; // 24 sub + r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 26 shfl + r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add + r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add + r2 = r2 ^ ds[r1 & mask]; // 29 load + r5 = r5 ^ ds[r7 & mask]; // 30 load + r2 = r2 ^ ds[r5 & mask]; // 31 load + r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 32 shfl + r4 = r5 * r7 + r4; // 33 mad + r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r7, 8); // 35 shfl + r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add + r5 = r5 ^ r7; // 37 xor + r2 = r2 | r1; // 38 or + r1 = __umulhi(r1, r0); // 39 mulhi + r6 = rotl_imm(r6, 19u); // 40 rotl + r4 = __umulhi(r4, r6); // 41 mulhi + r6 = r6 - r0; // 42 sub + r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl + r4 = r4 ^ ds[r2 & mask]; // 44 load + r1 = r1 ^ r3; // 45 xor + r7 = r7 ^ ds[r0 & mask]; // 46 load + r3 = r3 ^ ds[r1 & mask]; // 47 load + r5 = r5 * r3; // 48 mul + r1 = r1 - r5; // 49 sub + r2 = rotl_imm(r2, 8u); // 50 rotl + r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add + r4 = r4 ^ ds[r7 & mask]; // 52 load + r2 = r2 - r7; // 53 sub + r4 = r4 ^ r0; // 54 xor + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add + r2 = r2 ^ ds[r4 & mask]; // 56 load + r0 = r1 * r4 + r0; // 57 mad + r3 = r3 ^ ds[r5 & mask]; // 58 load + r5 = r5 | r6; // 59 or + r6 = r5 * r7 + r6; // 60 mad + r4 = rotl_imm(r4, 28u); // 61 rotl + r5 = __umulhi(r5, r0); // 62 mulhi + r3 = r3 ^ ds[r6 & mask]; // 63 load } uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.h b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.h index 79d760f44..bbe76f948 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.h +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.h @@ -105,9 +105,5 @@ IGNEUM_HD void mh_item(const uint32_t* cache, uint32_t t, uint32_t* s) { } for (uint32_t j = 0u; j < 4u; ++j) mh_mixer(s, 0x9E3779B9u * (32u + j + 1u)); } -// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. -IGNEUM_HD uint32_t mh_j(uint32_t w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } -IGNEUM_HD uint32_t mh_t(uint32_t w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } -IGNEUM_HD uint32_t mh_addr(uint32_t t, uint32_t j) { uint32_t w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } -// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). -IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } +// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. +IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.metal b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.metal index 89171a047..570224802 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.metal +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/memhard.metal @@ -90,12 +90,8 @@ inline void mh_item(device const uint* cache, uint t, thread uint* s) { } for (uint j = 0u; j < 4u; ++j) mh_mixer(s, 0x9E3779B9u * (32u + j + 1u)); } -// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. -inline uint mh_j(uint w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } -inline uint mh_t(uint w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } -inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } -// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). -inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } +// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. +inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } // One thread per segment (2^16 threads). kernel void igneum_cache_fill(device uint* cache [[buffer(0)]], uint gid [[thread_position_in_grid]]) { @@ -106,5 +102,6 @@ kernel void igneum_build(device const uint* cache [[buffer(0)]], device uint* da uint gid [[thread_position_in_grid]]) { uint s[16]; mh_item(cache, gid, s); - for (uint i = 0u; i < 16u; ++i) dataset[mh_addr(gid, i)] = s[i]; + device uint* d = dataset + gid * 16u; + for (uint i = 0u; i < 16u; ++i) d[i] = s[i]; } diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.h b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.h index e353c0a07..354b473c8 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.h +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.h @@ -13,9 +13,9 @@ #define IGNEUM_SEED_STRING "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000" #define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07" -#define IGNEUM_GENERATOR 3 +#define IGNEUM_GENERATOR 2 #define IGNEUM_PROGRAM_ATTEMPT 0 -#define IGNEUM_PROGRAM_ID 0x73bcbfe8ccf988f1ull +#define IGNEUM_PROGRAM_ID 0xa6892c64d9ddd7f7ull #define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000" #define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000" #define IGNEUM_DAY0 0xceed56d7u @@ -27,14 +27,10 @@ #define IGNEUM_INSTR_COUNT 64 #define IGNEUM_LOADS_PER_HASH 128 #define IGNEUM_WIDE_LOADS_PER_HASH 0 -#define IGNEUM_OP_MIX "load=16 add=15 shfl=6 mad=4 or=4 rotl=4 rotr=4 xor=4 mulhi=3 mul=2 sub=2" -// Program class v3 (Counter ASIC 2.0, docs/plans/counter-asic-2-rollout.md): generator version 3; a worker that -// runs another class refuses this pack, and a job line names the class it wants (class=v3 era=). -#define IGNEUM_PROGRAM_CLASS "v3" -#define IGNEUM_ERA_SEED_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07" +#define IGNEUM_OP_MIX "load=16 add=13 mulhi=9 shfl=5 sub=5 mad=4 rotl=4 xor=3 or=2 rotr=2 mul=1" // Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item // derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule. -#define IGNEUM_LOAD_CLASS "mx4-erad810f22d" +#define IGNEUM_LOAD_CLASS "mx4" #define IGNEUM_CLASS_MIXER_MULT 4 #define IGNEUM_CACHE_GROWTH 1 // 1: cache words = 2^(26 + doublings(day)), doublings = floor(log2(1 + day / 1460)) #define IGNEUM_LOAD_SLOTS 16 @@ -43,18 +39,6 @@ #define IGNEUM_BYTES_PER_HASH 512 #define IGNEUM_FOLD_ROT 11 #define IGNEUM_FOLD_MUL 0x9e3779b1u -// Era layout (5 October 2026, docs/plans/era-layout.md): NOT the lottery hash. Every dataset load reads -// idx = ((rotl(src * STRIDE_MUL, STRIDE_ROT) & window mask) | window offset) & MASK; the window of a load site is the -// dataset, a half or a quarter of it (IGNEUM_ERA_WINDOWS: site:shrink:offset); dataset word w holds word j(w) of item -// t(w) with j's bits at the INTERLEAVE positions (memhard.h: mh_t, mh_j, mh_addr). -#define IGNEUM_ERA_LABEL "d810f22d" -#define IGNEUM_ERA_SEED_WORDS { 0xd810f22du, 0xcf9dc883u, 0x5f3e571fu, 0x2b7d97fcu, 0x810012c4u, 0x002d9798u, 0xa4180c41u, 0xa4562c21u } -#define IGNEUM_ERA_ALLOWED_WIDTHS { 1, 0, 0 } // words, ascending, 0 = unused; one entry pins the width -#define IGNEUM_ERA_WIDTH_WORDS 1 -#define IGNEUM_ERA_STRIDE_MUL 0x9ad30d99u -#define IGNEUM_ERA_STRIDE_ROT 29 -#define IGNEUM_ERA_INTERLEAVE { 0, 2, 12, 13 } -#define IGNEUM_ERA_WINDOWS "7:2:1 8:1:1 9:1:1 10:1:1 11:0:0 13:1:1 29:0:0 30:2:2 31:1:1 44:1:1 46:2:0 47:0:0 52:0:0 56:0:0 58:2:0 63:1:1" // 0 = closed-form dataset (ds_elem), 1 = memory-hard cache construction (MEMHARD.md, memhard.h) #define IGNEUM_DATASET_MODE 1 diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.json b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.json index a78da713a..dcce05422 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.json +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.json @@ -1,8 +1,8 @@ { "format": "igneum-program-pack-3", - "generator": 3, + "generator": 2, "attempt": 0, - "program_id": "0x73bcbfe8ccf988f1", + "program_id": "0xa6892c64d9ddd7f7", "program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32", "dataset_mode": "memory-hard", "seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000", @@ -15,9 +15,7 @@ "iterations": 8, "instruction_count": 64, "loads_per_hash": 128, - "program_class": "v3", - "era_seed_bytes": "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07", - "load_class": "mx4-erad810f22d", + "load_class": "mx4", "mixer_mult": 4, "cache_growth": true, "mixer": "class v3 (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): every mixer application of the item derivation is 4 applications with round keys (r * 4 + j + 1) * 0x9E3779B9, the 8 dependent cache reads per item unchanged; cache growth rule option C: cache words = 2^(26 + doublings(day)), dataset words = 2^(genesis_log2 + doublings(day)), doublings(day) = floor(log2(1 + day / 1460)) for day = days since genesis", @@ -26,21 +24,7 @@ "load_width_counts_4_16_64": [16, 0, 0], "bytes_per_hash": 512, "wide_load": "read-width experiment (5 October 2026, docs/plans/read-width.md), NOT the lottery hash: a load of W words (width field, 4 or 16) reads dataset[b .. b + W) with b = (src & mask) & ~(W - 1) and folds every word into dst: x = dst ^ w[0]; for j in 1..W: x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]; dst = x; width 1 is the plain load; the width is drawn per instruction from the class mix with one extra below(100) draw after the nine of version 2, and the program id is FNV-1a 64 over 'igneum-program-rw/' || generator_le32 || seed words || attempt_le32 || mix[3] || load_slots", - "era": { - "label": "d810f22d", - "seed_words": ["0xd810f22d", "0xcf9dc883", "0x5f3e571f", "0x2b7d97fc", "0x810012c4", "0x002d9798", "0xa4180c41", "0xa4562c21"], - "draw": "docs/plans/era-layout.md 1.1: SplitMix64 seeded with seed_words[0] | seed_words[1] << 32 of seed_words_from_bytes('igneum-era/' || n_le64 || E_n); width = allowed[below(|allowed|)], stride_mul = low32(next()) | 1, stride_rot = 1 + below(31), then four next() draws for a partial Fisher-Yates over positions log2(W)..15 of which 4 - log2(W) are used", - "allowed_widths": [1], - "width_words": 1, - "stride_mul": "0x9ad30d99", - "stride_rot": 29, - "interleave": [0, 2, 12, 13], - "address": "y = rotl(src * stride_mul, stride_rot); k = min(win, D - 26); idx = ((y & (mask >> k)) | ((off & (2^k - 1)) << (D - k))) & mask; a wide load aligns idx down to W words", - "windows": "per instruction, after the width roll: win = below(3), off = low32(next()) & (2^win - 1); used on a load slot (the instruction's win and off fields)", - "dataset_word": "dataset[w] = item(t(w))[j(w)]: j(w) gathers the bits of w at the interleave positions, t(w) is w with those bits removed", - "program_id_suffix": "'era/' || allowed[3] || width_words || stride_mul_le32 || stride_rot_le32 || interleave[4]" - }, - "op_mix": {"load": 16, "add": 15, "shfl": 6, "mad": 4, "or": 4, "rotl": 4, "rotr": 4, "xor": 4, "mulhi": 3, "mul": 2, "sub": 2}, + "op_mix": {"load": 16, "add": 13, "mulhi": 9, "shfl": 5, "sub": 5, "mad": 4, "rotl": 4, "xor": 3, "or": 2, "rotr": 2, "mul": 1}, "register_init": "for i in 0..7: x = nonce ^ seed_words[i]; x += 0x9e3779b9 * (i+1) (mod 2^32); x = splitmix32(x); r[i] = x ^ seed_words[(i+1) & 7]", "splitmix32": "x ^= x>>16; x *= 0x7feb352d; x ^= x>>15; x *= 0x846ca68b; x ^= x>>16", "iteration": "sel = r0 sampled once at the top of each iteration, then all instructions in order", @@ -79,69 +63,69 @@ "word": "dataset[w] = item(w >> 4)[w & 15]" }, "instructions": [ - {"i": 0, "op": "add", "dst": 4, "src": 5, "src2": 7, "imm": "0xea86e152", "imm2": "0x5810667a", "rot": 27, "bit": 13, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 1, "op": "xor", "dst": 7, "src": 0, "src2": 6, "imm": "0xbaab6229", "imm2": "0xed861989", "rot": 26, "bit": 22, "mask": 4, "width": 1, "win": 0, "off": 0}, - {"i": 2, "op": "shfl", "dst": 3, "src": 6, "src2": 2, "imm": "0x5b623116", "imm2": "0xff12e5b2", "rot": 12, "bit": 24, "mask": 1, "width": 1, "win": 0, "off": 0}, - {"i": 3, "op": "sub", "dst": 4, "src": 1, "src2": 1, "imm": "0xe99741c7", "imm2": "0xf5fa5009", "rot": 1, "bit": 21, "mask": 1, "width": 1, "win": 0, "off": 0}, - {"i": 4, "op": "mad", "dst": 2, "src": 0, "src2": 4, "imm": "0x673c2157", "imm2": "0xee02465f", "rot": 20, "bit": 22, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 5, "op": "rotl", "dst": 4, "src": 7, "src2": 7, "imm": "0x946f7818", "imm2": "0x45d3399e", "rot": 9, "bit": 2, "mask": 16, "width": 1, "win": 0, "off": 0}, - {"i": 6, "op": "rotr", "dst": 0, "src": 2, "src2": 4, "imm": "0x5f6a0ed2", "imm2": "0x7043a636", "rot": 19, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0}, - {"i": 7, "op": "load", "dst": 6, "src": 7, "src2": 1, "imm": "0x5c61dcf7", "imm2": "0x7466aa40", "rot": 19, "bit": 9, "mask": 2, "width": 1, "win": 2, "off": 1}, - {"i": 8, "op": "load", "dst": 1, "src": 4, "src2": 5, "imm": "0x85668475", "imm2": "0xdb8cc483", "rot": 29, "bit": 7, "mask": 4, "width": 1, "win": 1, "off": 1}, - {"i": 9, "op": "load", "dst": 1, "src": 2, "src2": 4, "imm": "0x4454980f", "imm2": "0xebd31581", "rot": 10, "bit": 28, "mask": 16, "width": 1, "win": 1, "off": 1}, - {"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1}, - {"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0}, - {"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1}, - {"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0}, - {"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0}, - {"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0}, - {"i": 17, "op": "rotr", "dst": 0, "src": 6, "src2": 1, "imm": "0x26f3ad8a", "imm2": "0x27256f15", "rot": 18, "bit": 5, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 18, "op": "add", "dst": 7, "src": 5, "src2": 7, "imm": "0xf66e7017", "imm2": "0xb9e3577e", "rot": 9, "bit": 12, "mask": 16, "width": 1, "win": 0, "off": 0}, - {"i": 19, "op": "rotl", "dst": 7, "src": 0, "src2": 5, "imm": "0x849ae6ee", "imm2": "0x02b358f9", "rot": 24, "bit": 18, "mask": 8, "width": 1, "win": 0, "off": 0}, - {"i": 20, "op": "add", "dst": 6, "src": 7, "src2": 6, "imm": "0x52334d12", "imm2": "0x8c9f0ef8", "rot": 11, "bit": 23, "mask": 4, "width": 1, "win": 0, "off": 0}, - {"i": 21, "op": "or", "dst": 2, "src": 6, "src2": 5, "imm": "0xb1871e63", "imm2": "0xb2e40191", "rot": 5, "bit": 13, "mask": 4, "width": 1, "win": 0, "off": 0}, - {"i": 22, "op": "mad", "dst": 6, "src": 5, "src2": 4, "imm": "0x97df29e4", "imm2": "0xe60fea84", "rot": 11, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 23, "op": "or", "dst": 1, "src": 0, "src2": 3, "imm": "0x8f30d21d", "imm2": "0x2df685a0", "rot": 31, "bit": 0, "mask": 16, "width": 1, "win": 0, "off": 0}, - {"i": 24, "op": "xor", "dst": 6, "src": 1, "src2": 2, "imm": "0xd2c4025f", "imm2": "0x5269eb4d", "rot": 31, "bit": 21, "mask": 16, "width": 1, "win": 0, "off": 0}, - {"i": 25, "op": "add", "dst": 2, "src": 6, "src2": 5, "imm": "0x659fc3d3", "imm2": "0x9cec0e12", "rot": 6, "bit": 17, "mask": 4, "width": 1, "win": 0, "off": 0}, - {"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0}, - {"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0}, - {"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2}, - {"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1}, - {"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0}, - {"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0}, - {"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0}, - {"i": 35, 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"0xbdaaf46a", "rot": 25, "bit": 23, "mask": 16, "width": 1}, + {"i": 50, "op": "rotl", "dst": 2, "src": 6, "src2": 4, "imm": "0x92d9a412", "imm2": "0x0daf96ea", "rot": 8, "bit": 4, "mask": 4, "width": 1}, + {"i": 51, "op": "add", "dst": 1, "src": 5, "src2": 0, "imm": "0xa900fec4", "imm2": "0x77b9bd43", "rot": 6, "bit": 23, "mask": 2, "width": 1}, + {"i": 52, "op": "load", "dst": 4, "src": 7, "src2": 1, "imm": "0x51392a72", "imm2": "0x99e8bb36", "rot": 11, "bit": 9, "mask": 1, "width": 1}, + {"i": 53, "op": "sub", "dst": 2, "src": 7, "src2": 2, "imm": "0x0ffe2ac7", "imm2": "0x030743df", "rot": 9, "bit": 30, "mask": 16, "width": 1}, + {"i": 54, "op": "xor", "dst": 4, "src": 0, "src2": 4, "imm": "0x9123ff15", "imm2": "0x10c329a7", "rot": 28, "bit": 15, "mask": 2, "width": 1}, + {"i": 55, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1}, + {"i": 56, "op": "load", "dst": 2, "src": 4, "src2": 3, "imm": "0x239de52c", "imm2": "0xf80bae18", "rot": 15, "bit": 24, "mask": 1, "width": 1}, + {"i": 57, "op": "mad", "dst": 0, "src": 1, "src2": 4, "imm": "0x31dede8e", "imm2": "0xd3f619e6", "rot": 29, "bit": 7, "mask": 2, "width": 1}, + {"i": 58, "op": "load", "dst": 3, "src": 5, "src2": 3, "imm": "0x206437d6", "imm2": "0x28d1c290", "rot": 17, "bit": 28, "mask": 4, "width": 1}, + {"i": 59, "op": "or", "dst": 5, "src": 6, "src2": 3, "imm": "0x8fffd674", "imm2": "0x0507903a", "rot": 26, "bit": 27, "mask": 2, "width": 1}, + {"i": 60, "op": "mad", "dst": 6, "src": 5, "src2": 7, "imm": "0xf572bdb9", "imm2": "0xeda2af31", "rot": 21, "bit": 8, "mask": 2, "width": 1}, + {"i": 61, "op": "rotl", "dst": 4, "src": 2, "src2": 7, "imm": "0x84f12ddf", "imm2": "0x81ef22e1", "rot": 28, "bit": 30, "mask": 1, "width": 1}, + {"i": 62, "op": "mulhi", "dst": 5, "src": 0, "src2": 6, "imm": "0xf6bb45ee", "imm2": "0x6bfb632d", "rot": 22, "bit": 0, "mask": 4, "width": 1}, + {"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0x50ec702a", "imm2": "0xae6ee96e", "rot": 20, "bit": 25, "mask": 2, "width": 1} ] } diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.metal b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.metal index 8c0a2d1cd..b899adecb 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.metal +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program.metal @@ -39,69 +39,69 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]], for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + select(0xea86e152u, 0x5810667au, ((sel >> 13u) & 1u) != 0u); // 0 - r7 = r7 ^ r0; // 1 - r3 = r3 ^ simd_shuffle_xor(r6, (ushort)1); // 2 - r4 = r4 - r1; // 3 - r2 = r0 * r4 + r2; // 4 - r4 = rotl_imm(r4, 9u); // 5 - r0 = rotr_var(r0, r2); // 6 - r6 = r6 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & MASK]; // 7 - r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 8 - r1 = r1 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 9 - r7 = r7 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10 - r7 = r7 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11 - r5 = r5 * r4; // 12 - r7 = r7 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13 - r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14 - r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15 - r2 = r2 | r7; // 16 - r0 = rotr_var(r0, r6); // 17 - r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 18 - r7 = rotl_imm(r7, 24u); // 19 - r6 = r6 + r7 + select(0x52334d12u, 0x8c9f0ef8u, ((sel >> 23u) & 1u) != 0u); // 20 - r2 = r2 | r6; // 21 - r6 = r5 * r4 + r6; // 22 - r1 = r1 | r0; // 23 - r6 = r6 ^ r1; // 24 - r2 = r2 + r6 + select(0x659fc3d3u, 0x9cec0e12u, ((sel >> 17u) & 1u) != 0u); // 25 - r7 = rotr_var(r7, r0); // 26 - r4 = r5 * r7 + r4; // 27 - r3 = r2 * r4 + r3; // 28 - r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29 - r2 = r2 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30 - r1 = r1 ^ dataset[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31 - r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32 - r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33 - r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34 - r2 = mulhi(r2, r5); // 35 - r4 = r4 ^ r2; // 36 - r6 = r6 * r5; // 37 - r7 = r7 ^ r0; // 38 - r7 = r7 + r2 + select(0xb8180e9du, 0x32bbd117u, ((sel >> 19u) & 1u) != 0u); // 39 - r2 = rotr_var(r2, r3); // 40 - r7 = r7 - r0; // 41 - r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42 - r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43 - r0 = r0 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44 - r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45 - r3 = r3 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46 - r6 = r6 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47 - r4 = mulhi(r4, r2); // 48 - r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49 - r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50 - r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51 - r5 = r5 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52 - r6 = rotl_imm(r6, 12u); // 53 - r3 = rotl_imm(r3, 12u); // 54 - r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55 - r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56 - r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57 - r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58 - r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59 - r3 = mulhi(r3, r2); // 60 - r6 = r6 | r4; // 61 - r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62 - r3 = r3 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63 + r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // 1 + r3 = r3 + r2 + select(0x2cccb6cau, 0x642e66dbu, ((sel >> 10u) & 1u) != 0u); // 2 + r0 = rotl_imm(r0, 19u); // 3 + r7 = rotr_var(r7, r6); // 4 + r7 = r7 + r4 + select(0xee02465fu, 0xc1535555u, ((sel >> 21u) & 1u) != 0u); // 5 + r1 = mulhi(r1, r7); // 6 + r4 = r4 ^ dataset[r2 & MASK]; // 7 + r7 = r7 ^ dataset[r4 & MASK]; // 8 + r0 = r0 ^ dataset[r3 & MASK]; // 9 + r5 = r5 ^ dataset[r1 & MASK]; // 10 + r1 = r1 ^ dataset[r5 & MASK]; // 11 + r3 = mulhi(r3, r5); // 12 + r1 = r1 ^ dataset[r3 & MASK]; // 13 + r0 = r0 - r3; // 14 + r5 = r1 * r3 + r5; // 15 + r6 = mulhi(r6, r1); // 16 + r5 = r5 + r2 + select(0x697b3d00u, 0x8b965b57u, ((sel >> 28u) & 1u) != 0u); // 17 + r0 = mulhi(r0, r6); // 18 + r5 = rotr_var(r5, r3); // 19 + r5 = mulhi(r5, r2); // 20 + r1 = r1 + r0 + select(0xebcf247au, 0x6d7e8d05u, ((sel >> 1u) & 1u) != 0u); // 21 + r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 22 + r1 = mulhi(r1, r5); // 23 + r2 = r2 - r5; // 24 + r7 = r7 + r4 + select(0x08ffa6c7u, 0x699ef1bbu, ((sel >> 2u) & 1u) != 0u); // 25 + r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 26 + r7 = r7 + r1 + select(0xe60fea84u, 0xb4ead2fbu, ((sel >> 14u) & 1u) != 0u); // 27 + r3 = r3 + r1 + select(0x65c76dabu, 0x8f30d21du, ((sel >> 6u) & 1u) != 0u); // 28 + r2 = r2 ^ dataset[r1 & MASK]; // 29 + r5 = r5 ^ dataset[r7 & MASK]; // 30 + r2 = r2 ^ dataset[r5 & MASK]; // 31 + r1 = r1 ^ simd_shuffle_xor(r7, (ushort)4); // 32 + r4 = r5 * r7 + r4; // 33 + r4 = r4 + r2 + select(0x0480debeu, 0xc7ce690cu, ((sel >> 21u) & 1u) != 0u); // 34 + r3 = r3 ^ simd_shuffle_xor(r7, (ushort)8); // 35 + r7 = r7 + r1 + select(0xc53b542eu, 0xe10c2c95u, ((sel >> 2u) & 1u) != 0u); // 36 + r5 = r5 ^ r7; // 37 + r2 = r2 | r1; // 38 + r1 = mulhi(r1, r0); // 39 + r6 = rotl_imm(r6, 19u); // 40 + r4 = mulhi(r4, r6); // 41 + r6 = r6 - r0; // 42 + r6 = r6 ^ simd_shuffle_xor(r3, (ushort)4); // 43 + r4 = r4 ^ dataset[r2 & MASK]; // 44 + r1 = r1 ^ r3; // 45 + r7 = r7 ^ dataset[r0 & MASK]; // 46 + r3 = r3 ^ dataset[r1 & MASK]; // 47 + r5 = r5 * r3; // 48 + r1 = r1 - r5; // 49 + r2 = rotl_imm(r2, 8u); // 50 + r1 = r1 + r5 + select(0xa900fec4u, 0x77b9bd43u, ((sel >> 23u) & 1u) != 0u); // 51 + r4 = r4 ^ dataset[r7 & MASK]; // 52 + r2 = r2 - r7; // 53 + r4 = r4 ^ r0; // 54 + r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 55 + r2 = r2 ^ dataset[r4 & MASK]; // 56 + r0 = r1 * r4 + r0; // 57 + r3 = r3 ^ dataset[r5 & MASK]; // 58 + r5 = r5 | r6; // 59 + r6 = r5 * r7 + r6; // 60 + r4 = rotl_imm(r4, 28u); // 61 + r5 = mulhi(r5, r0); // 62 + r3 = r3 ^ dataset[r6 & MASK]; // 63 } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program_bound.metal b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program_bound.metal index bc806a1e1..2f0218149 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program_bound.metal +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/program_bound.metal @@ -41,69 +41,69 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]], for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + select(0xea86e152u, 0x5810667au, ((sel >> 13u) & 1u) != 0u); // 0 - r7 = r7 ^ r0; // 1 - r3 = r3 ^ simd_shuffle_xor(r6, (ushort)1); // 2 - r4 = r4 - r1; // 3 - r2 = r0 * r4 + r2; // 4 - r4 = rotl_imm(r4, 9u); // 5 - r0 = rotr_var(r0, r2); // 6 - r6 = r6 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & MASK]; // 7 - r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 8 - r1 = r1 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 9 - r7 = r7 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10 - r7 = r7 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11 - r5 = r5 * r4; // 12 - r7 = r7 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13 - r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14 - r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15 - r2 = r2 | r7; // 16 - r0 = rotr_var(r0, r6); // 17 - r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 18 - r7 = rotl_imm(r7, 24u); // 19 - r6 = r6 + r7 + select(0x52334d12u, 0x8c9f0ef8u, ((sel >> 23u) & 1u) != 0u); // 20 - r2 = r2 | r6; // 21 - r6 = r5 * r4 + r6; // 22 - r1 = r1 | r0; // 23 - r6 = r6 ^ r1; // 24 - r2 = r2 + r6 + select(0x659fc3d3u, 0x9cec0e12u, ((sel >> 17u) & 1u) != 0u); // 25 - r7 = rotr_var(r7, r0); // 26 - r4 = r5 * r7 + r4; // 27 - r3 = r2 * r4 + r3; // 28 - r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29 - r2 = r2 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30 - r1 = r1 ^ dataset[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31 - r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32 - r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33 - r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34 - r2 = mulhi(r2, r5); // 35 - r4 = r4 ^ r2; // 36 - r6 = r6 * r5; // 37 - r7 = r7 ^ r0; // 38 - r7 = r7 + r2 + select(0xb8180e9du, 0x32bbd117u, ((sel >> 19u) & 1u) != 0u); // 39 - r2 = rotr_var(r2, r3); // 40 - r7 = r7 - r0; // 41 - r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42 - r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43 - r0 = r0 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44 - r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45 - r3 = r3 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46 - r6 = r6 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47 - r4 = mulhi(r4, r2); // 48 - r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49 - r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50 - r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51 - r5 = r5 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52 - r6 = rotl_imm(r6, 12u); // 53 - r3 = rotl_imm(r3, 12u); // 54 - r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55 - r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56 - r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57 - r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58 - r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59 - r3 = mulhi(r3, r2); // 60 - r6 = r6 | r4; // 61 - r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62 - r3 = r3 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63 + r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // 1 + r3 = r3 + r2 + select(0x2cccb6cau, 0x642e66dbu, ((sel >> 10u) & 1u) != 0u); // 2 + r0 = rotl_imm(r0, 19u); // 3 + r7 = rotr_var(r7, r6); // 4 + r7 = r7 + r4 + select(0xee02465fu, 0xc1535555u, ((sel >> 21u) & 1u) != 0u); // 5 + r1 = mulhi(r1, r7); // 6 + r4 = r4 ^ dataset[r2 & MASK]; // 7 + r7 = r7 ^ dataset[r4 & MASK]; // 8 + r0 = r0 ^ dataset[r3 & MASK]; // 9 + r5 = r5 ^ dataset[r1 & MASK]; // 10 + r1 = r1 ^ dataset[r5 & MASK]; // 11 + r3 = mulhi(r3, r5); // 12 + r1 = r1 ^ dataset[r3 & MASK]; // 13 + r0 = r0 - r3; // 14 + r5 = r1 * r3 + r5; // 15 + r6 = mulhi(r6, r1); // 16 + r5 = r5 + r2 + select(0x697b3d00u, 0x8b965b57u, ((sel >> 28u) & 1u) != 0u); // 17 + r0 = mulhi(r0, r6); // 18 + r5 = rotr_var(r5, r3); // 19 + r5 = mulhi(r5, r2); // 20 + r1 = r1 + r0 + select(0xebcf247au, 0x6d7e8d05u, ((sel >> 1u) & 1u) != 0u); // 21 + r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 22 + r1 = mulhi(r1, r5); // 23 + r2 = r2 - r5; // 24 + r7 = r7 + r4 + select(0x08ffa6c7u, 0x699ef1bbu, ((sel >> 2u) & 1u) != 0u); // 25 + r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 26 + r7 = r7 + r1 + select(0xe60fea84u, 0xb4ead2fbu, ((sel >> 14u) & 1u) != 0u); // 27 + r3 = r3 + r1 + select(0x65c76dabu, 0x8f30d21du, ((sel >> 6u) & 1u) != 0u); // 28 + r2 = r2 ^ dataset[r1 & MASK]; // 29 + r5 = r5 ^ dataset[r7 & MASK]; // 30 + r2 = r2 ^ dataset[r5 & MASK]; // 31 + r1 = r1 ^ simd_shuffle_xor(r7, (ushort)4); // 32 + r4 = r5 * r7 + r4; // 33 + r4 = r4 + r2 + select(0x0480debeu, 0xc7ce690cu, ((sel >> 21u) & 1u) != 0u); // 34 + r3 = r3 ^ simd_shuffle_xor(r7, (ushort)8); // 35 + r7 = r7 + r1 + select(0xc53b542eu, 0xe10c2c95u, ((sel >> 2u) & 1u) != 0u); // 36 + r5 = r5 ^ r7; // 37 + r2 = r2 | r1; // 38 + r1 = mulhi(r1, r0); // 39 + r6 = rotl_imm(r6, 19u); // 40 + r4 = mulhi(r4, r6); // 41 + r6 = r6 - r0; // 42 + r6 = r6 ^ simd_shuffle_xor(r3, (ushort)4); // 43 + r4 = r4 ^ dataset[r2 & MASK]; // 44 + r1 = r1 ^ r3; // 45 + r7 = r7 ^ dataset[r0 & MASK]; // 46 + r3 = r3 ^ dataset[r1 & MASK]; // 47 + r5 = r5 * r3; // 48 + r1 = r1 - r5; // 49 + r2 = rotl_imm(r2, 8u); // 50 + r1 = r1 + r5 + select(0xa900fec4u, 0x77b9bd43u, ((sel >> 23u) & 1u) != 0u); // 51 + r4 = r4 ^ dataset[r7 & MASK]; // 52 + r2 = r2 - r7; // 53 + r4 = r4 ^ r0; // 54 + r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 55 + r2 = r2 ^ dataset[r4 & MASK]; // 56 + r0 = r1 * r4 + r0; // 57 + r3 = r3 ^ dataset[r5 & MASK]; // 58 + r5 = r5 | r6; // 59 + r6 = r5 * r7 + r6; // 60 + r4 = rotl_imm(r4, 28u); // 61 + r5 = mulhi(r5, r0); // 62 + r3 = r3 ^ dataset[r6 & MASK]; // 63 } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.h b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.h index 9f27cdee1..e111bcddb 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.h +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.h @@ -1,5 +1,5 @@ // Generated by igneum-pow export (generator v2) for seed "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000". Do not edit by hand. -// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset +// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset #pragma once #ifdef __cplusplus #include @@ -11,29 +11,29 @@ static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u }; static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = { { // base nonce 0 - 0xc478aa7b014b314full, 0x5f3b248ea1746690ull, 0x8b8e8d9ea2b748aaull, 0x5feb8eb98d85f482ull, 0x45c41509215309bdull, 0x5e2867e2fe2eed4aull, 0x8aab5a828a90a606ull, 0x570e96ddd777c289ull, - 0x6286e93f7c85d849ull, 0x566c00af118a621aull, 0x5a90210268f469cfull, 0x485984b2c57fc4c3ull, 0x1b42cd7bf2052143ull, 0x61754006818ac84bull, 0x5ab1a0391203c228ull, 0x75085f9f4fec3a81ull, - 0x2d02e728ee7f7b3cull, 0x2bc86c904068d09eull, 0x5e41fedd34afbd06ull, 0xa7792d807213f5b5ull, 0xe22d665d69e17c16ull, 0xb52880c283c7da56ull, 0xdb005f50a716a881ull, 0xea72f35c9f5309bbull, - 0x240401c19d2cab92ull, 0xc83d663994524ce8ull, 0x771c1e871be79867ull, 0xda09af3bd47125f5ull, 0x64d4b67009887d73ull, 0xd6373f5d4afd9c07ull, 0x61ef84e034a884ddull, 0x14c268b894bcd1a4ull + 0x212c6442b51e87aeull, 0xc374795c00839331ull, 0xb6036a220a98f4b3ull, 0xeb8b8013e637367bull, 0xdb5866e9b73930fdull, 0xf3f3d01f46e90333ull, 0x9d913991ab8ed428ull, 0x7ccb1d8fa100a800ull, + 0x3cf45ba44f09a0feull, 0x91acf48ef1a63082ull, 0x6ea46c69fb082f99ull, 0x581f0218977a9d72ull, 0x9a4623a5c62ddf2dull, 0xab6eb5e768f0feb4ull, 0x07b70bdccf8aca12ull, 0xd666311ae5e4311eull, + 0x53114757d669f0a4ull, 0xbd5d6ace87ce2ce4ull, 0xfb712015e8189192ull, 0xa32cec81103e134bull, 0x83f3d18c3289c124ull, 0xfe29f1984b132b3dull, 0xc9ffcf4e3774497aull, 0xac99c9243dc63809ull, + 0xd78a7e8217a32f3cull, 0xab81ad63d242fc31ull, 0x0e4c30b7e00024afull, 0xce014289fff6778dull, 0x64a1292e2a8b4a91ull, 0xd5b8c90e681d7e3aull, 0x06078117673030fdull, 0x51bf77b280173930ull }, { // base nonce 4096 - 0x613fdff51675cbc5ull, 0x33542a1c13240331ull, 0xc12327f1c985c157ull, 0x5983d76c84850677ull, 0x07b876d962db9aeeull, 0x061556b249a2f4edull, 0x7a6a864253cbb666ull, 0x202a4c3f7caf4842ull, - 0xaf47fb1b6f8fd897ull, 0xed86312481032b66ull, 0xe10287d2dc43f393ull, 0x4366d593f75c8a9eull, 0xc265f45fc11562f9ull, 0x23a5ae8634848667ull, 0xb75271a5e58e2e07ull, 0xe2dca00457ff11eeull, - 0x12610d35f18ee235ull, 0x13c1d91de3a5590dull, 0x7af3bbc2e82ce300ull, 0x2725a442d7e70923ull, 0x3938551cfcce0b5eull, 0xb525335b7e13a279ull, 0xf2951f26f6130dcdull, 0x807acf761deff319ull, - 0xafcb894ac5e8cba9ull, 0x1408e0631222a04dull, 0x43a6f79feff89569ull, 0xba577b357fd3b1fcull, 0x424ce7a84318939full, 0xef8f70968010b59eull, 0x8c8a5bcfb16c5a97ull, 0xf2aae270614f2559ull + 0x3c797978566b5950ull, 0x7c759e60185b6411ull, 0x199136b84028d653ull, 0x0ad7b60cb722da50ull, 0x93e5fd443b85acc5ull, 0x4a0fadca2f0b7dc6ull, 0x91b5f2478c1fbd4full, 0xe3debc1f1cdc889aull, + 0x9c39b1635a6aec09ull, 0xbeaea0ab408df45aull, 0x080283b6f52a494aull, 0x9acae9a878c16f2eull, 0xc37dc4e098fee807ull, 0xf3daf9ff09a2c0e5ull, 0xfff82c3572c8f362ull, 0xd96414dfa0b4bd51ull, + 0xecf77498c26cc5abull, 0x72945c7a2e52a90cull, 0xe5b6749102690fa4ull, 0x90eddb84d13a2b9full, 0x6e9186a56dc002c1ull, 0xfa2047ec0ae61fe3ull, 0xa8cd4efd68b7eff5ull, 0xd23b650a6345bf73ull, + 0xe1141a33ea09bae1ull, 0x0e9aae812f5d762aull, 0x9ae3811dcc68797full, 0x0a4dab24c1efff6full, 0xa22d476bc42b9064ull, 0xc7a16d6f59414a2eull, 0x5aff92ecae652329ull, 0x96a903eb9a0ca390ull }, { // base nonce 1000000 - 0xc3b0f31bc9c9a941ull, 0x3dc9db6098337122ull, 0x88ed65e7030bf6e7ull, 0xc3afffd7ef432358ull, 0x4d63429d0816cad6ull, 0xb606c57fc50dfd1bull, 0xbdb00eeb9bd26950ull, 0x379d208ba4c59b68ull, - 0x1b16aa85bffae547ull, 0xf7985ad46430cf69ull, 0x8b5c01051cc55d79ull, 0x0aae8efd1fad2942ull, 0x1256bc0bdfa48f58ull, 0xe657eab8150aa145ull, 0xef6dad537975a2c8ull, 0x805fbcfbccd6710cull, - 0x40be9f4eb86765c6ull, 0x84a5731b7e4ecdacull, 0xd728fb6b057d6ef5ull, 0xa40663757a846c1bull, 0xa38a545e91fd339cull, 0x31629cfa5d2d5d6bull, 0x5d0f4f101daa520full, 0xe57bb2de8033df0full, - 0x892443887a68e483ull, 0xe5066fc7e6b374bfull, 0x5f443c99c6d0f851ull, 0xeaa61aa7109c0fe5ull, 0x9b4a43a24c80dfe6ull, 0x69ad31dea437a76eull, 0x7cb849f7209c482cull, 0x0c42712849a48773ull + 0xd5a8da0568df8ee7ull, 0x68cb69c04208285aull, 0xe3e0c57190a809dbull, 0x87ba27d76aa356d5ull, 0x5a30616d4b8bfcf2ull, 0x66f5d2c31997fd24ull, 0x0447779e26a2854aull, 0x1225eb67933b2faeull, + 0xde78d94be53c669bull, 0x02a3fe00eb77c8cdull, 0x4fd029ba4cfc526aull, 0x2ef8ea603a0463d6ull, 0x345cff9b465b6f12ull, 0x03bb80d5a700b7feull, 0xf7da33ca2094ae26ull, 0xb3adaaa8383ad2e9ull, + 0x68d5eafde2924d62ull, 0xeab53a1b039835e0ull, 0xfd04e678835cb646ull, 0xf25b86a707f333c0ull, 0xa3bb24e6981917deull, 0x791d38b29dd6055aull, 0xfd18f01f064bdbcaull, 0xee051af1de1b70f9ull, + 0x246bfe79acd966eaull, 0xbcb8105b8a73efedull, 0x9b7e8c6fcc25fa92ull, 0xa0ffe2d9e4717892ull, 0x22f52e2324035114ull, 0xcdac38103479920dull, 0x49477ffa08ac4a6cull, 0xf8ca84a1a5d78cf5ull } }; // Dataset self-test: dataset[0..15] and dataset[IGNEUM_MASK] (268435455). static const uint32_t IGNEUM_DS_HEAD[16] = { - 0xafe80d67u, 0xb9fbd029u, 0x7155550bu, 0x32965d99u, 0x6c79f193u, 0x95139ad9u, 0x71bdb5ddu, 0x7de50b28u, - 0xf4980f73u, 0x01fd5739u, 0x5b410497u, 0xe4c84638u, 0x08d1d374u, 0x29058a56u, 0xee171b93u, 0xa4fed894u + 0xafe80d67u, 0xb9fbd029u, 0x6c79f193u, 0x95139ad9u, 0x96310affu, 0x4609f8b1u, 0x75279e63u, 0x28235be1u, + 0x47b17dcbu, 0x718e0ef2u, 0xa52588c8u, 0xa8bf49d5u, 0x19cf243eu, 0x5ec8905eu, 0xa4851f66u, 0xaf9cd9f3u }; static const uint32_t IGNEUM_DS_LAST_INDEX = 268435455u; static const uint32_t IGNEUM_DS_LAST = 0xe6a99c7au; @@ -43,7 +43,7 @@ static const uint32_t IGNEUM_DS_SAMPLE_INDEX[IGNEUM_DS_SAMPLES] = { 59471966u, 217795994u, 208353206u, 42483309u, 172547758u, 148076330u, 183853158u, 214389424u, 267488061u, 169781097u, 184093494u, 153880993u, 84977930u, 46426879u, 3093825u, 225364072u, 44593546u, 260713159u, 168250303u, 52384140u, 223401610u, 45554030u, 95410555u, 175039924u, 79171087u, 267580473u, 24168642u, 37981670u, 171551130u, 195559979u, 204611762u, 140997658u, 138925853u, 86637313u, 20736778u, 219665210u, 160430336u, 264654675u, 8013395u, 228945585u, 213884386u, 104419827u, 44185464u, 142737231u, 99284897u, 132475900u, 61861762u, 132056166u, 262388043u, 91878046u, 117353561u, 124768597u, 71352993u, 190698941u, 46055428u, 55281366u, 165145231u, 106810753u, 171985651u, 232085256u, 159510492u, 40072060u, 209107596u, 39023794u }; static const uint32_t IGNEUM_DS_SAMPLE_VALUE[IGNEUM_DS_SAMPLES] = { - 0xaade6dc9u, 0x1da7efe9u, 0xc41ae56eu, 0xf25480a3u, 0x0d628857u, 0xc506bba7u, 0xfd9b5dc6u, 0xac36cef7u, 0xabb0c725u, 0x2169d0a5u, 0x79f374c8u, 0xd4517909u, 0x105cc0a8u, 0xa5c081f8u, 0x5d91aef0u, 0x13c5930au, 0x9d49f3fcu, 0x9da43ab7u, 0x28bc6d8fu, 0x135b0b0bu, 0x428a8bd8u, 0xc9f90868u, 0x83328bcfu, 0xb02ef21eu, 0xee8098cdu, 0xf0c365feu, 0x32138523u, 0x26c4c59au, 0xd11deb96u, 0x9e1cd011u, 0x0a83dcd4u, 0x6fbf8ce3u, 0x7bf6dd56u, 0xf079569eu, 0x98d970acu, 0xd6feefdfu, 0xbe12559bu, 0x90e64549u, 0x81238e75u, 0x66b80a1du, 0x6637db36u, 0x6682fda0u, 0x0b0b6b0fu, 0xdebcaa14u, 0x78b382b9u, 0xa92cda07u, 0x693ae44bu, 0x13d96cceu, 0x0ad96728u, 0x4615abe5u, 0xc8ef2953u, 0x226c9b04u, 0xea5fe9b4u, 0xa57e1812u, 0x0cfc72c0u, 0x35dfac56u, 0x8d0ae5a7u, 0xfd635e70u, 0xf14b2d3fu, 0x56fb5ff4u, 0x2340e755u, 0x4a4a0aadu, 0x1abd16edu, 0xa7790ffeu + 0x57642b58u, 0xc279baddu, 0xcbccbaadu, 0x32cce392u, 0x71fdb4c6u, 0xf5a268ceu, 0x3ca1d676u, 0x7977b03du, 0xb73a6cb1u, 0xe773c5c9u, 0x2533a3f1u, 0xd7c48638u, 0xfc80830au, 0xab3874e9u, 0xc093812eu, 0xb71e49d6u, 0x0e151e7bu, 0x395af161u, 0x7156ef4eu, 0x9202463fu, 0x562e88c8u, 0xb9b0c5b3u, 0xe3f6102fu, 0xe3a94cbbu, 0x9e26c494u, 0x47ace326u, 0xe20ea113u, 0xce4eefa1u, 0x97a41cc9u, 0xa6d51cb5u, 0x71f3df27u, 0x115df551u, 0x20e273b8u, 0x50bf99ffu, 0xc9b1ae13u, 0x342160c6u, 0xc1b8eb36u, 0x9b11737bu, 0x4b73d48fu, 0x455e9b9eu, 0xe5213a1cu, 0xf7049bc3u, 0x0a026f93u, 0x156a8a99u, 0x1029fe6cu, 0x4f29d205u, 0x273315edu, 0x483e85a2u, 0xec802349u, 0x76023cccu, 0xe37e8135u, 0x0881d277u, 0x56ba9c69u, 0x31ad3b78u, 0xc8ad9363u, 0x8647e3c0u, 0x12e78b02u, 0x2d3a1b5fu, 0xa75e9390u, 0xbe0cebd8u, 0x759af86du, 0x9b4bd567u, 0xd272d0aeu, 0x7a18d82eu }; // Cache self-test (memory-hard mode): cache[0..15], the last 16 words, and FNV-1a 64 over all 2^26 words. static const uint32_t IGNEUM_CACHE_HEAD[16] = { diff --git a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.json b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.json index fa0187758..1bc9a0b51 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.json +++ b/proto-cuda/packs-ca2-mixer/mx4-devnet-epoch0/vectors.json @@ -5,31 +5,31 @@ "dataset_log2_words": 28, "mask": "0x0fffffff", "lanes": 32, - "source": "igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset", + "source": "igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset", "warps": [ {"base_nonce": 0, "expected": [ - "0xc478aa7b014b314f", "0x5f3b248ea1746690", "0x8b8e8d9ea2b748aa", "0x5feb8eb98d85f482", "0x45c41509215309bd", "0x5e2867e2fe2eed4a", "0x8aab5a828a90a606", "0x570e96ddd777c289", - "0x6286e93f7c85d849", "0x566c00af118a621a", "0x5a90210268f469cf", "0x485984b2c57fc4c3", "0x1b42cd7bf2052143", "0x61754006818ac84b", "0x5ab1a0391203c228", "0x75085f9f4fec3a81", - "0x2d02e728ee7f7b3c", "0x2bc86c904068d09e", "0x5e41fedd34afbd06", "0xa7792d807213f5b5", "0xe22d665d69e17c16", "0xb52880c283c7da56", "0xdb005f50a716a881", "0xea72f35c9f5309bb", - "0x240401c19d2cab92", "0xc83d663994524ce8", "0x771c1e871be79867", "0xda09af3bd47125f5", "0x64d4b67009887d73", "0xd6373f5d4afd9c07", "0x61ef84e034a884dd", "0x14c268b894bcd1a4" + "0x212c6442b51e87ae", "0xc374795c00839331", "0xb6036a220a98f4b3", "0xeb8b8013e637367b", "0xdb5866e9b73930fd", "0xf3f3d01f46e90333", "0x9d913991ab8ed428", "0x7ccb1d8fa100a800", + "0x3cf45ba44f09a0fe", "0x91acf48ef1a63082", "0x6ea46c69fb082f99", "0x581f0218977a9d72", "0x9a4623a5c62ddf2d", "0xab6eb5e768f0feb4", "0x07b70bdccf8aca12", "0xd666311ae5e4311e", + "0x53114757d669f0a4", "0xbd5d6ace87ce2ce4", "0xfb712015e8189192", "0xa32cec81103e134b", "0x83f3d18c3289c124", "0xfe29f1984b132b3d", "0xc9ffcf4e3774497a", "0xac99c9243dc63809", + "0xd78a7e8217a32f3c", "0xab81ad63d242fc31", "0x0e4c30b7e00024af", "0xce014289fff6778d", "0x64a1292e2a8b4a91", "0xd5b8c90e681d7e3a", "0x06078117673030fd", "0x51bf77b280173930" ]}, {"base_nonce": 4096, "expected": [ - "0x613fdff51675cbc5", "0x33542a1c13240331", "0xc12327f1c985c157", "0x5983d76c84850677", "0x07b876d962db9aee", "0x061556b249a2f4ed", "0x7a6a864253cbb666", "0x202a4c3f7caf4842", - "0xaf47fb1b6f8fd897", "0xed86312481032b66", "0xe10287d2dc43f393", "0x4366d593f75c8a9e", "0xc265f45fc11562f9", "0x23a5ae8634848667", "0xb75271a5e58e2e07", "0xe2dca00457ff11ee", - "0x12610d35f18ee235", "0x13c1d91de3a5590d", "0x7af3bbc2e82ce300", "0x2725a442d7e70923", "0x3938551cfcce0b5e", "0xb525335b7e13a279", "0xf2951f26f6130dcd", "0x807acf761deff319", - "0xafcb894ac5e8cba9", "0x1408e0631222a04d", "0x43a6f79feff89569", "0xba577b357fd3b1fc", "0x424ce7a84318939f", "0xef8f70968010b59e", "0x8c8a5bcfb16c5a97", "0xf2aae270614f2559" + "0x3c797978566b5950", "0x7c759e60185b6411", "0x199136b84028d653", "0x0ad7b60cb722da50", "0x93e5fd443b85acc5", "0x4a0fadca2f0b7dc6", "0x91b5f2478c1fbd4f", "0xe3debc1f1cdc889a", + "0x9c39b1635a6aec09", "0xbeaea0ab408df45a", "0x080283b6f52a494a", "0x9acae9a878c16f2e", "0xc37dc4e098fee807", "0xf3daf9ff09a2c0e5", "0xfff82c3572c8f362", "0xd96414dfa0b4bd51", + "0xecf77498c26cc5ab", "0x72945c7a2e52a90c", "0xe5b6749102690fa4", "0x90eddb84d13a2b9f", "0x6e9186a56dc002c1", "0xfa2047ec0ae61fe3", "0xa8cd4efd68b7eff5", "0xd23b650a6345bf73", + "0xe1141a33ea09bae1", "0x0e9aae812f5d762a", "0x9ae3811dcc68797f", "0x0a4dab24c1efff6f", "0xa22d476bc42b9064", "0xc7a16d6f59414a2e", "0x5aff92ecae652329", "0x96a903eb9a0ca390" ]}, {"base_nonce": 1000000, "expected": [ - "0xc3b0f31bc9c9a941", "0x3dc9db6098337122", "0x88ed65e7030bf6e7", "0xc3afffd7ef432358", "0x4d63429d0816cad6", "0xb606c57fc50dfd1b", "0xbdb00eeb9bd26950", "0x379d208ba4c59b68", - "0x1b16aa85bffae547", "0xf7985ad46430cf69", "0x8b5c01051cc55d79", "0x0aae8efd1fad2942", "0x1256bc0bdfa48f58", "0xe657eab8150aa145", "0xef6dad537975a2c8", "0x805fbcfbccd6710c", - "0x40be9f4eb86765c6", "0x84a5731b7e4ecdac", "0xd728fb6b057d6ef5", "0xa40663757a846c1b", "0xa38a545e91fd339c", "0x31629cfa5d2d5d6b", "0x5d0f4f101daa520f", "0xe57bb2de8033df0f", - "0x892443887a68e483", "0xe5066fc7e6b374bf", "0x5f443c99c6d0f851", "0xeaa61aa7109c0fe5", "0x9b4a43a24c80dfe6", "0x69ad31dea437a76e", "0x7cb849f7209c482c", "0x0c42712849a48773" + "0xd5a8da0568df8ee7", "0x68cb69c04208285a", "0xe3e0c57190a809db", "0x87ba27d76aa356d5", "0x5a30616d4b8bfcf2", "0x66f5d2c31997fd24", "0x0447779e26a2854a", "0x1225eb67933b2fae", + "0xde78d94be53c669b", "0x02a3fe00eb77c8cd", "0x4fd029ba4cfc526a", "0x2ef8ea603a0463d6", "0x345cff9b465b6f12", "0x03bb80d5a700b7fe", "0xf7da33ca2094ae26", "0xb3adaaa8383ad2e9", + "0x68d5eafde2924d62", "0xeab53a1b039835e0", "0xfd04e678835cb646", "0xf25b86a707f333c0", "0xa3bb24e6981917de", "0x791d38b29dd6055a", "0xfd18f01f064bdbca", "0xee051af1de1b70f9", + "0x246bfe79acd966ea", "0xbcb8105b8a73efed", "0x9b7e8c6fcc25fa92", "0xa0ffe2d9e4717892", "0x22f52e2324035114", "0xcdac38103479920d", "0x49477ffa08ac4a6c", "0xf8ca84a1a5d78cf5" ]} ], - "dataset_head": ["0xafe80d67", "0xb9fbd029", "0x7155550b", "0x32965d99", "0x6c79f193", "0x95139ad9", "0x71bdb5dd", "0x7de50b28", "0xf4980f73", "0x01fd5739", "0x5b410497", "0xe4c84638", "0x08d1d374", "0x29058a56", "0xee171b93", "0xa4fed894"], + "dataset_head": ["0xafe80d67", "0xb9fbd029", "0x6c79f193", "0x95139ad9", "0x96310aff", "0x4609f8b1", "0x75279e63", "0x28235be1", "0x47b17dcb", "0x718e0ef2", "0xa52588c8", "0xa8bf49d5", "0x19cf243e", "0x5ec8905e", "0xa4851f66", "0xaf9cd9f3"], "dataset_last_index": 268435455, "dataset_last": "0xe6a99c7a", - "dataset_samples": [{"index": 59471966, "value": "0xaade6dc9"}, {"index": 217795994, "value": "0x1da7efe9"}, {"index": 208353206, "value": "0xc41ae56e"}, {"index": 42483309, "value": "0xf25480a3"}, {"index": 172547758, "value": "0x0d628857"}, {"index": 148076330, "value": "0xc506bba7"}, {"index": 183853158, "value": "0xfd9b5dc6"}, {"index": 214389424, "value": "0xac36cef7"}, {"index": 267488061, "value": "0xabb0c725"}, {"index": 169781097, "value": "0x2169d0a5"}, {"index": 184093494, "value": "0x79f374c8"}, {"index": 153880993, "value": "0xd4517909"}, {"index": 84977930, "value": "0x105cc0a8"}, {"index": 46426879, "value": "0xa5c081f8"}, {"index": 3093825, "value": "0x5d91aef0"}, {"index": 225364072, "value": "0x13c5930a"}, {"index": 44593546, "value": "0x9d49f3fc"}, {"index": 260713159, "value": "0x9da43ab7"}, {"index": 168250303, "value": "0x28bc6d8f"}, {"index": 52384140, "value": "0x135b0b0b"}, {"index": 223401610, "value": "0x428a8bd8"}, {"index": 45554030, "value": "0xc9f90868"}, {"index": 95410555, "value": "0x83328bcf"}, {"index": 175039924, "value": "0xb02ef21e"}, {"index": 79171087, "value": "0xee8098cd"}, {"index": 267580473, "value": "0xf0c365fe"}, {"index": 24168642, "value": "0x32138523"}, {"index": 37981670, "value": "0x26c4c59a"}, {"index": 171551130, "value": "0xd11deb96"}, {"index": 195559979, "value": "0x9e1cd011"}, {"index": 204611762, "value": "0x0a83dcd4"}, {"index": 140997658, "value": "0x6fbf8ce3"}, {"index": 138925853, "value": "0x7bf6dd56"}, {"index": 86637313, "value": "0xf079569e"}, {"index": 20736778, "value": "0x98d970ac"}, {"index": 219665210, "value": "0xd6feefdf"}, {"index": 160430336, "value": "0xbe12559b"}, {"index": 264654675, "value": "0x90e64549"}, {"index": 8013395, "value": "0x81238e75"}, {"index": 228945585, "value": "0x66b80a1d"}, {"index": 213884386, "value": "0x6637db36"}, {"index": 104419827, "value": "0x6682fda0"}, {"index": 44185464, "value": "0x0b0b6b0f"}, {"index": 142737231, "value": "0xdebcaa14"}, {"index": 99284897, "value": "0x78b382b9"}, {"index": 132475900, "value": "0xa92cda07"}, {"index": 61861762, "value": "0x693ae44b"}, {"index": 132056166, "value": "0x13d96cce"}, {"index": 262388043, "value": "0x0ad96728"}, {"index": 91878046, "value": "0x4615abe5"}, {"index": 117353561, "value": "0xc8ef2953"}, {"index": 124768597, "value": "0x226c9b04"}, {"index": 71352993, "value": "0xea5fe9b4"}, {"index": 190698941, "value": "0xa57e1812"}, {"index": 46055428, "value": "0x0cfc72c0"}, {"index": 55281366, "value": "0x35dfac56"}, {"index": 165145231, "value": "0x8d0ae5a7"}, {"index": 106810753, "value": "0xfd635e70"}, {"index": 171985651, "value": "0xf14b2d3f"}, {"index": 232085256, "value": "0x56fb5ff4"}, {"index": 159510492, "value": "0x2340e755"}, {"index": 40072060, "value": "0x4a4a0aad"}, {"index": 209107596, "value": "0x1abd16ed"}, {"index": 39023794, "value": "0xa7790ffe"}], + "dataset_samples": [{"index": 59471966, "value": "0x57642b58"}, {"index": 217795994, "value": "0xc279badd"}, {"index": 208353206, "value": "0xcbccbaad"}, {"index": 42483309, "value": "0x32cce392"}, {"index": 172547758, "value": "0x71fdb4c6"}, {"index": 148076330, "value": "0xf5a268ce"}, {"index": 183853158, "value": "0x3ca1d676"}, {"index": 214389424, "value": "0x7977b03d"}, {"index": 267488061, "value": "0xb73a6cb1"}, {"index": 169781097, "value": "0xe773c5c9"}, {"index": 184093494, "value": "0x2533a3f1"}, {"index": 153880993, "value": "0xd7c48638"}, {"index": 84977930, "value": "0xfc80830a"}, {"index": 46426879, "value": "0xab3874e9"}, {"index": 3093825, "value": "0xc093812e"}, {"index": 225364072, "value": "0xb71e49d6"}, {"index": 44593546, "value": "0x0e151e7b"}, {"index": 260713159, "value": "0x395af161"}, {"index": 168250303, "value": "0x7156ef4e"}, {"index": 52384140, "value": "0x9202463f"}, {"index": 223401610, "value": "0x562e88c8"}, {"index": 45554030, "value": "0xb9b0c5b3"}, {"index": 95410555, "value": "0xe3f6102f"}, {"index": 175039924, "value": "0xe3a94cbb"}, {"index": 79171087, "value": "0x9e26c494"}, {"index": 267580473, "value": "0x47ace326"}, {"index": 24168642, "value": "0xe20ea113"}, {"index": 37981670, "value": "0xce4eefa1"}, {"index": 171551130, "value": "0x97a41cc9"}, {"index": 195559979, "value": "0xa6d51cb5"}, {"index": 204611762, "value": "0x71f3df27"}, {"index": 140997658, "value": "0x115df551"}, {"index": 138925853, "value": "0x20e273b8"}, {"index": 86637313, "value": "0x50bf99ff"}, {"index": 20736778, "value": "0xc9b1ae13"}, {"index": 219665210, "value": "0x342160c6"}, {"index": 160430336, "value": "0xc1b8eb36"}, {"index": 264654675, "value": "0x9b11737b"}, {"index": 8013395, "value": "0x4b73d48f"}, {"index": 228945585, "value": "0x455e9b9e"}, {"index": 213884386, "value": "0xe5213a1c"}, {"index": 104419827, "value": "0xf7049bc3"}, {"index": 44185464, "value": "0x0a026f93"}, {"index": 142737231, "value": "0x156a8a99"}, {"index": 99284897, "value": "0x1029fe6c"}, {"index": 132475900, "value": "0x4f29d205"}, {"index": 61861762, "value": "0x273315ed"}, {"index": 132056166, "value": "0x483e85a2"}, {"index": 262388043, "value": "0xec802349"}, {"index": 91878046, "value": "0x76023ccc"}, {"index": 117353561, "value": "0xe37e8135"}, {"index": 124768597, "value": "0x0881d277"}, {"index": 71352993, "value": "0x56ba9c69"}, {"index": 190698941, "value": "0x31ad3b78"}, {"index": 46055428, "value": "0xc8ad9363"}, {"index": 55281366, "value": "0x8647e3c0"}, {"index": 165145231, "value": "0x12e78b02"}, {"index": 106810753, "value": "0x2d3a1b5f"}, {"index": 171985651, "value": "0xa75e9390"}, {"index": 232085256, "value": "0xbe0cebd8"}, {"index": 159510492, "value": "0x759af86d"}, {"index": 40072060, "value": "0x9b4bd567"}, {"index": 209107596, "value": "0xd272d0ae"}, {"index": 39023794, "value": "0x7a18d82e"}], "cache_head": ["0xebd9055c", "0x7eaf6b21", "0x9b610855", "0x134a8562", "0xb10059ba", "0x7f459e58", "0x8f3c7873", "0x3523e609", "0x75b8f4ca", "0x750d31b4", "0x0dae0782", "0x26f10015", "0x7ba87a41", "0x0efd8543", "0x691d6368", "0x8929d967"], "cache_last_line": ["0x51474edf", "0xc3cfba93", "0xf21454cf", "0x9b79baac", "0x4d4fce23", "0xd701dfd5", "0x37357ab3", "0x1be693fa", "0xa701cb3b", "0x7467c620", "0x428184e8", "0xf4010df0", "0xe33aa88f", "0xc78d6d62", "0xae9ba9c0", "0xf4bba97e"], "cache_fnv1a64": "0x448274a57f508cbc" diff --git a/proto-cuda/packs-ca2-mixer/mx4-genesis/program.h b/proto-cuda/packs-ca2-mixer/mx4-genesis/program.h index f70b83cca..b4fa96b1a 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-genesis/program.h +++ b/proto-cuda/packs-ca2-mixer/mx4-genesis/program.h @@ -13,9 +13,9 @@ #define IGNEUM_SEED_STRING "igneum-genesis" #define IGNEUM_SEED_BYTES_HEX "69676e65756d2d67656e65736973" -#define IGNEUM_GENERATOR 3 +#define IGNEUM_GENERATOR 2 #define IGNEUM_PROGRAM_ATTEMPT 0 -#define IGNEUM_PROGRAM_ID 0xe323b9dcaf283a6full +#define IGNEUM_PROGRAM_ID 0x951b89584750bd75ull #define IGNEUM_DAY_STRING "2026-10-03" #define IGNEUM_DAY_BYTES_HEX "6461792f323032362d31302d3033" #define IGNEUM_DAY0 0x3067619fu @@ -28,9 +28,6 @@ #define IGNEUM_LOADS_PER_HASH 128 #define IGNEUM_WIDE_LOADS_PER_HASH 0 #define IGNEUM_OP_MIX "load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1" -// Program class v3 (Counter ASIC 2.0, docs/plans/counter-asic-2-rollout.md): generator version 3; a worker that -// runs another class refuses this pack, and a job line names the class it wants (class=v3 era=). -#define IGNEUM_PROGRAM_CLASS "v3" // Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item // derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule. #define IGNEUM_LOAD_CLASS "mx4" diff --git a/proto-cuda/packs-ca2-mixer/mx4-genesis/program.json b/proto-cuda/packs-ca2-mixer/mx4-genesis/program.json index 0971d8d74..8b247276e 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-genesis/program.json +++ b/proto-cuda/packs-ca2-mixer/mx4-genesis/program.json @@ -1,8 +1,8 @@ { "format": "igneum-program-pack-3", - "generator": 3, + "generator": 2, "attempt": 0, - "program_id": "0xe323b9dcaf283a6f", + "program_id": "0x951b89584750bd75", "program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32", "dataset_mode": "memory-hard", "seed": "igneum-genesis", @@ -15,7 +15,6 @@ "iterations": 8, "instruction_count": 64, "loads_per_hash": 128, - "program_class": "v3", "load_class": "mx4", "mixer_mult": 4, "cache_growth": true, diff --git a/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.h b/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.h index 6ed53fb15..f25b26e16 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.h +++ b/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.h @@ -1,5 +1,5 @@ // Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand. -// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset +// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset #pragma once #ifdef __cplusplus #include diff --git a/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.json b/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.json index 0667ecf18..32b421bfb 100644 --- a/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.json +++ b/proto-cuda/packs-ca2-mixer/mx4-genesis/vectors.json @@ -5,7 +5,7 @@ "dataset_log2_words": 28, "mask": "0x0fffffff", "lanes": 32, - "source": "igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset", + "source": "igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset", "warps": [ {"base_nonce": 0, "expected": [ "0x63acd2d273f475ba", "0xe929c78b34b80d4b", "0x0b1011cb19982558", "0x1457a0df5497aa11", "0x957d0f3bb71d98fb", "0xac16901e6e6f6057", "0x8ea1c6279f4b177a", "0xf28146e60bd08ba9", diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cl b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cl index e4f3bb63d..f2cccc4a1 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cl +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cl @@ -155,8 +155,12 @@ static inline void mh_item(__global const uint* cache, uint t, uint* s) { } for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u)); } -// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. -static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } +// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. +static inline uint mh_j(uint w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } +static inline uint mh_t(uint w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } +static inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } +// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). +static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } // Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item. // The same constants as memhard.h in this pack (one emitter, three dialects). @@ -169,8 +173,7 @@ __kernel void igneum_build(__global uint* ds, __global const uint* cache, uint n if (t < nItems) { uint s[16]; mh_item(cache, t, s); - __global uint* d = ds + ((ulong)t * 16u); - for (uint i = 0u; i < 16u; ++i) d[i] = s[i]; + for (uint i = 0u; i < 16u; ++i) ds[(ulong)mh_addr(t, i)] = s[i]; } } @@ -200,69 +203,69 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - { uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // 1 shfl - r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add - r0 = rotl_imm(r0, 19u); // 3 rotl - r7 = rotr_var(r7, r6); // 4 rotr - r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add - r1 = mul_hi(r1, r7); // 6 mulhi - r4 = r4 ^ ds[r2 & mask]; // 7 load - r7 = r7 ^ ds[r4 & mask]; // 8 load - r0 = r0 ^ ds[r3 & mask]; // 9 load - r5 = r5 ^ ds[r1 & mask]; // 10 load - r1 = r1 ^ ds[r5 & mask]; // 11 load - r3 = mul_hi(r3, r5); // 12 mulhi - r1 = r1 ^ ds[r3 & mask]; // 13 load - r0 = r0 - r3; // 14 sub - r5 = r1 * r3 + r5; // 15 mad - r6 = mul_hi(r6, r1); // 16 mulhi - r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add - r0 = mul_hi(r0, r6); // 18 mulhi - r5 = rotr_var(r5, r3); // 19 rotr - r5 = mul_hi(r5, r2); // 20 mulhi - r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add - r1 = mul_hi(r1, r5); // 23 mulhi - r2 = r2 - r5; // 24 sub - r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add - { uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 26 shfl - r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add - r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add - r2 = r2 ^ ds[r1 & mask]; // 29 load - r5 = r5 ^ ds[r7 & mask]; // 30 load - r2 = r2 ^ ds[r5 & mask]; // 31 load - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r1 = r1 ^ t_; } // 32 shfl - r4 = r5 * r7 + r4; // 33 mad - r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r3 = r3 ^ t_; } // 35 shfl - r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add - r5 = r5 ^ r7; // 37 xor - r2 = r2 | r1; // 38 or - r1 = mul_hi(r1, r0); // 39 mulhi - r6 = rotl_imm(r6, 19u); // 40 rotl - r4 = mul_hi(r4, r6); // 41 mulhi - r6 = r6 - r0; // 42 sub - { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r6 = r6 ^ t_; } // 43 shfl - r4 = r4 ^ ds[r2 & mask]; // 44 load - r1 = r1 ^ r3; // 45 xor - r7 = r7 ^ ds[r0 & mask]; // 46 load - r3 = r3 ^ ds[r1 & mask]; // 47 load - r5 = r5 * r3; // 48 mul - r1 = r1 - r5; // 49 sub - r2 = rotl_imm(r2, 8u); // 50 rotl - r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add - r4 = r4 ^ ds[r7 & mask]; // 52 load - r2 = r2 - r7; // 53 sub - r4 = r4 ^ r0; // 54 xor - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add - r2 = r2 ^ ds[r4 & mask]; // 56 load - r0 = r1 * r4 + r0; // 57 mad - r3 = r3 ^ ds[r5 & mask]; // 58 load - r5 = r5 | r6; // 59 or - r6 = r5 * r7 + r6; // 60 mad - r4 = rotl_imm(r4, 28u); // 61 rotl - r5 = mul_hi(r5, r0); // 62 mulhi - r3 = r3 ^ ds[r6 & mask]; // 63 load + r7 = r7 ^ r0; // 1 xor + { uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // 2 shfl + r4 = r4 - r1; // 3 sub + r2 = r0 * r4 + r2; // 4 mad + r4 = rotl_imm(r4, 9u); // 5 rotl + r0 = rotr_var(r0, r2); // 6 rotr + r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load + r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load + r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load + r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load + r5 = r5 * r4; // 12 mul + r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load + { uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl + { uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl + r2 = r2 | r7; // 16 or + r0 = rotr_var(r0, r6); // 17 rotr + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add + r7 = rotl_imm(r7, 24u); // 19 rotl + r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add + r2 = r2 | r6; // 21 or + r6 = r5 * r4 + r6; // 22 mad + r1 = r1 | r0; // 23 or + r6 = r6 ^ r1; // 24 xor + r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add + r7 = rotr_var(r7, r0); // 26 rotr + r4 = r5 * r7 + r4; // 27 mad + r3 = r2 * r4 + r3; // 28 mad + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load + r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load + r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load + r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add + r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add + r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add + r2 = mul_hi(r2, r5); // 35 mulhi + r4 = r4 ^ r2; // 36 xor + r6 = r6 * r5; // 37 mul + r7 = r7 ^ r0; // 38 xor + r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add + r2 = rotr_var(r2, r3); // 40 rotr + r7 = r7 - r0; // 41 sub + r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add + { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl + r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add + r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load + r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load + r4 = mul_hi(r4, r2); // 48 mulhi + r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl + r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add + r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load + r6 = rotl_imm(r6, 12u); // 53 rotl + r3 = rotl_imm(r3, 12u); // 54 rotl + r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load + r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add + r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load + r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add + r3 = mul_hi(r3, r2); // 60 mulhi + r6 = r6 | r4; // 61 or + { uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl + r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cu b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cu index c129edeec..2a0422763 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cu +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel.cu @@ -36,8 +36,7 @@ __global__ void igneum_build(uint32_t* ds, const uint32_t* cache, uint32_t nItem if (t < nItems) { uint32_t s[16]; mh_item(cache, t, s); - uint32_t* d = ds + (size_t)t * 16u; - for (uint32_t i = 0u; i < 16u; ++i) d[i] = s[i]; + for (uint32_t i = 0u; i < 16u; ++i) ds[(size_t)mh_addr(t, i)] = s[i]; } } @@ -60,69 +59,69 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc for (uint32_t it = 0u; it < 8u; ++it) { uint32_t sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // 1 shfl - r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add - r0 = rotl_imm(r0, 19u); // 3 rotl - r7 = rotr_var(r7, r6); // 4 rotr - r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add - r1 = __umulhi(r1, r7); // 6 mulhi - r4 = r4 ^ ds[r2 & mask]; // 7 load - r7 = r7 ^ ds[r4 & mask]; // 8 load - r0 = r0 ^ ds[r3 & mask]; // 9 load - r5 = r5 ^ ds[r1 & mask]; // 10 load - r1 = r1 ^ ds[r5 & mask]; // 11 load - r3 = __umulhi(r3, r5); // 12 mulhi - r1 = r1 ^ ds[r3 & mask]; // 13 load - r0 = r0 - r3; // 14 sub - r5 = r1 * r3 + r5; // 15 mad - r6 = __umulhi(r6, r1); // 16 mulhi - r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add - r0 = __umulhi(r0, r6); // 18 mulhi - r5 = rotr_var(r5, r3); // 19 rotr - r5 = __umulhi(r5, r2); // 20 mulhi - r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add - r1 = __umulhi(r1, r5); // 23 mulhi - r2 = r2 - r5; // 24 sub - r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 26 shfl - r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add - r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add - r2 = r2 ^ ds[r1 & mask]; // 29 load - r5 = r5 ^ ds[r7 & mask]; // 30 load - r2 = r2 ^ ds[r5 & mask]; // 31 load - r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 32 shfl - r4 = r5 * r7 + r4; // 33 mad - r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r7, 8); // 35 shfl - r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add - r5 = r5 ^ r7; // 37 xor - r2 = r2 | r1; // 38 or - r1 = __umulhi(r1, r0); // 39 mulhi - r6 = rotl_imm(r6, 19u); // 40 rotl - r4 = __umulhi(r4, r6); // 41 mulhi - r6 = r6 - r0; // 42 sub - r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl - r4 = r4 ^ ds[r2 & mask]; // 44 load - r1 = r1 ^ r3; // 45 xor - r7 = r7 ^ ds[r0 & mask]; // 46 load - r3 = r3 ^ ds[r1 & mask]; // 47 load - r5 = r5 * r3; // 48 mul - r1 = r1 - r5; // 49 sub - r2 = rotl_imm(r2, 8u); // 50 rotl - r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add - r4 = r4 ^ ds[r7 & mask]; // 52 load - r2 = r2 - r7; // 53 sub - r4 = r4 ^ r0; // 54 xor - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add - r2 = r2 ^ ds[r4 & mask]; // 56 load - r0 = r1 * r4 + r0; // 57 mad - r3 = r3 ^ ds[r5 & mask]; // 58 load - r5 = r5 | r6; // 59 or - r6 = r5 * r7 + r6; // 60 mad - r4 = rotl_imm(r4, 28u); // 61 rotl - r5 = __umulhi(r5, r0); // 62 mulhi - r3 = r3 ^ ds[r6 & mask]; // 63 load + r7 = r7 ^ r0; // 1 xor + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // 2 shfl + r4 = r4 - r1; // 3 sub + r2 = r0 * r4 + r2; // 4 mad + r4 = rotl_imm(r4, 9u); // 5 rotl + r0 = rotr_var(r0, r2); // 6 rotr + r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load + r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load + r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load + r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load + r5 = r5 * r4; // 12 mul + r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load + r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl + r2 = r2 | r7; // 16 or + r0 = rotr_var(r0, r6); // 17 rotr + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add + r7 = rotl_imm(r7, 24u); // 19 rotl + r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add + r2 = r2 | r6; // 21 or + r6 = r5 * r4 + r6; // 22 mad + r1 = r1 | r0; // 23 or + r6 = r6 ^ r1; // 24 xor + r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add + r7 = rotr_var(r7, r0); // 26 rotr + r4 = r5 * r7 + r4; // 27 mad + r3 = r2 * r4 + r3; // 28 mad + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load + r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load + r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load + r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add + r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add + r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add + r2 = __umulhi(r2, r5); // 35 mulhi + r4 = r4 ^ r2; // 36 xor + r6 = r6 * r5; // 37 mul + r7 = r7 ^ r0; // 38 xor + r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add + r2 = rotr_var(r2, r3); // 40 rotr + r7 = r7 - r0; // 41 sub + r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add + r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl + r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add + r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load + r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load + r4 = __umulhi(r4, r2); // 48 mulhi + r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add + r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl + r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add + r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load + r6 = rotl_imm(r6, 12u); // 53 rotl + r3 = rotl_imm(r3, 12u); // 54 rotl + r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load + r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add + r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load + r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add + r3 = __umulhi(r3, r2); // 60 mulhi + r6 = r6 | r4; // 61 or + r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl + r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load } uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cl b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cl index 51b5d85d6..d4dedee89 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cl +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cl @@ -155,8 +155,12 @@ static inline void mh_item(__global const uint* cache, uint t, uint* s) { } for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u)); } -// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. -static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } +// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. +static inline uint mh_j(uint w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } +static inline uint mh_t(uint w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } +static inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } +// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). +static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } // Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item. // The same constants as memhard.h in this pack (one emitter, three dialects). @@ -169,8 +173,7 @@ __kernel void igneum_build(__global uint* ds, __global const uint* cache, uint n if (t < nItems) { uint s[16]; mh_item(cache, t, s); - __global uint* d = ds + ((ulong)t * 16u); - for (uint i = 0u; i < 16u; ++i) d[i] = s[i]; + for (uint i = 0u; i < 16u; ++i) ds[(ulong)mh_addr(t, i)] = s[i]; } } @@ -200,69 +203,69 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - { uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // 1 shfl - r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add - r0 = rotl_imm(r0, 19u); // 3 rotl - r7 = rotr_var(r7, r6); // 4 rotr - r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add - r1 = mul_hi(r1, r7); // 6 mulhi - r4 = r4 ^ ds[r2 & mask]; // 7 load - r7 = r7 ^ ds[r4 & mask]; // 8 load - r0 = r0 ^ ds[r3 & mask]; // 9 load - r5 = r5 ^ ds[r1 & mask]; // 10 load - r1 = r1 ^ ds[r5 & mask]; // 11 load - r3 = mul_hi(r3, r5); // 12 mulhi - r1 = r1 ^ ds[r3 & mask]; // 13 load - r0 = r0 - r3; // 14 sub - r5 = r1 * r3 + r5; // 15 mad - r6 = mul_hi(r6, r1); // 16 mulhi - r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add - r0 = mul_hi(r0, r6); // 18 mulhi - r5 = rotr_var(r5, r3); // 19 rotr - r5 = mul_hi(r5, r2); // 20 mulhi - r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add - r1 = mul_hi(r1, r5); // 23 mulhi - r2 = r2 - r5; // 24 sub - r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add - { uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 26 shfl - r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add - r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add - r2 = r2 ^ ds[r1 & mask]; // 29 load - r5 = r5 ^ ds[r7 & mask]; // 30 load - r2 = r2 ^ ds[r5 & mask]; // 31 load - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r1 = r1 ^ t_; } // 32 shfl - r4 = r5 * r7 + r4; // 33 mad - r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r3 = r3 ^ t_; } // 35 shfl - r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add - r5 = r5 ^ r7; // 37 xor - r2 = r2 | r1; // 38 or - r1 = mul_hi(r1, r0); // 39 mulhi - r6 = rotl_imm(r6, 19u); // 40 rotl - r4 = mul_hi(r4, r6); // 41 mulhi - r6 = r6 - r0; // 42 sub - { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r6 = r6 ^ t_; } // 43 shfl - r4 = r4 ^ ds[r2 & mask]; // 44 load - r1 = r1 ^ r3; // 45 xor - r7 = r7 ^ ds[r0 & mask]; // 46 load - r3 = r3 ^ ds[r1 & mask]; // 47 load - r5 = r5 * r3; // 48 mul - r1 = r1 - r5; // 49 sub - r2 = rotl_imm(r2, 8u); // 50 rotl - r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add - r4 = r4 ^ ds[r7 & mask]; // 52 load - r2 = r2 - r7; // 53 sub - r4 = r4 ^ r0; // 54 xor - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add - r2 = r2 ^ ds[r4 & mask]; // 56 load - r0 = r1 * r4 + r0; // 57 mad - r3 = r3 ^ ds[r5 & mask]; // 58 load - r5 = r5 | r6; // 59 or - r6 = r5 * r7 + r6; // 60 mad - r4 = rotl_imm(r4, 28u); // 61 rotl - r5 = mul_hi(r5, r0); // 62 mulhi - r3 = r3 ^ ds[r6 & mask]; // 63 load + r7 = r7 ^ r0; // 1 xor + { uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // 2 shfl + r4 = r4 - r1; // 3 sub + r2 = r0 * r4 + r2; // 4 mad + r4 = rotl_imm(r4, 9u); // 5 rotl + r0 = rotr_var(r0, r2); // 6 rotr + r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load + r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load + r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load + r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load + r5 = r5 * r4; // 12 mul + r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load + { uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl + { uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl + r2 = r2 | r7; // 16 or + r0 = rotr_var(r0, r6); // 17 rotr + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add + r7 = rotl_imm(r7, 24u); // 19 rotl + r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add + r2 = r2 | r6; // 21 or + r6 = r5 * r4 + r6; // 22 mad + r1 = r1 | r0; // 23 or + r6 = r6 ^ r1; // 24 xor + r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add + r7 = rotr_var(r7, r0); // 26 rotr + r4 = r5 * r7 + r4; // 27 mad + r3 = r2 * r4 + r3; // 28 mad + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load + r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load + r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load + r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add + r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add + r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add + r2 = mul_hi(r2, r5); // 35 mulhi + r4 = r4 ^ r2; // 36 xor + r6 = r6 * r5; // 37 mul + r7 = r7 ^ r0; // 38 xor + r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add + r2 = rotr_var(r2, r3); // 40 rotr + r7 = r7 - r0; // 41 sub + r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add + { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl + r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add + r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load + r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load + r4 = mul_hi(r4, r2); // 48 mulhi + r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl + r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add + r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load + r6 = rotl_imm(r6, 12u); // 53 rotl + r3 = rotl_imm(r3, 12u); // 54 rotl + r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load + r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add + r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load + r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add + r3 = mul_hi(r3, r2); // 60 mulhi + r6 = r6 | r4; // 61 or + { uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl + r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); @@ -303,69 +306,69 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - { uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // 1 shfl - r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add - r0 = rotl_imm(r0, 19u); // 3 rotl - r7 = rotr_var(r7, r6); // 4 rotr - r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add - r1 = mul_hi(r1, r7); // 6 mulhi - r4 = r4 ^ ds[r2 & mask]; // 7 load - r7 = r7 ^ ds[r4 & mask]; // 8 load - r0 = r0 ^ ds[r3 & mask]; // 9 load - r5 = r5 ^ ds[r1 & mask]; // 10 load - r1 = r1 ^ ds[r5 & mask]; // 11 load - r3 = mul_hi(r3, r5); // 12 mulhi - r1 = r1 ^ ds[r3 & mask]; // 13 load - r0 = r0 - r3; // 14 sub - r5 = r1 * r3 + r5; // 15 mad - r6 = mul_hi(r6, r1); // 16 mulhi - r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add - r0 = mul_hi(r0, r6); // 18 mulhi - r5 = rotr_var(r5, r3); // 19 rotr - r5 = mul_hi(r5, r2); // 20 mulhi - r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add - r1 = mul_hi(r1, r5); // 23 mulhi - r2 = r2 - r5; // 24 sub - r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add - { uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 26 shfl - r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add - r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add - r2 = r2 ^ ds[r1 & mask]; // 29 load - r5 = r5 ^ ds[r7 & mask]; // 30 load - r2 = r2 ^ ds[r5 & mask]; // 31 load - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r1 = r1 ^ t_; } // 32 shfl - r4 = r5 * r7 + r4; // 33 mad - r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add - { uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r3 = r3 ^ t_; } // 35 shfl - r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add - r5 = r5 ^ r7; // 37 xor - r2 = r2 | r1; // 38 or - r1 = mul_hi(r1, r0); // 39 mulhi - r6 = rotl_imm(r6, 19u); // 40 rotl - r4 = mul_hi(r4, r6); // 41 mulhi - r6 = r6 - r0; // 42 sub - { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r6 = r6 ^ t_; } // 43 shfl - r4 = r4 ^ ds[r2 & mask]; // 44 load - r1 = r1 ^ r3; // 45 xor - r7 = r7 ^ ds[r0 & mask]; // 46 load - r3 = r3 ^ ds[r1 & mask]; // 47 load - r5 = r5 * r3; // 48 mul - r1 = r1 - r5; // 49 sub - r2 = rotl_imm(r2, 8u); // 50 rotl - r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add - r4 = r4 ^ ds[r7 & mask]; // 52 load - r2 = r2 - r7; // 53 sub - r4 = r4 ^ r0; // 54 xor - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add - r2 = r2 ^ ds[r4 & mask]; // 56 load - r0 = r1 * r4 + r0; // 57 mad - r3 = r3 ^ ds[r5 & mask]; // 58 load - r5 = r5 | r6; // 59 or - r6 = r5 * r7 + r6; // 60 mad - r4 = rotl_imm(r4, 28u); // 61 rotl - r5 = mul_hi(r5, r0); // 62 mulhi - r3 = r3 ^ ds[r6 & mask]; // 63 load + r7 = r7 ^ r0; // 1 xor + { uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // 2 shfl + r4 = r4 - r1; // 3 sub + r2 = r0 * r4 + r2; // 4 mad + r4 = rotl_imm(r4, 9u); // 5 rotl + r0 = rotr_var(r0, r2); // 6 rotr + r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load + r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load + r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load + r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load + r5 = r5 * r4; // 12 mul + r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load + { uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl + { uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl + r2 = r2 | r7; // 16 or + r0 = rotr_var(r0, r6); // 17 rotr + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add + r7 = rotl_imm(r7, 24u); // 19 rotl + r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add + r2 = r2 | r6; // 21 or + r6 = r5 * r4 + r6; // 22 mad + r1 = r1 | r0; // 23 or + r6 = r6 ^ r1; // 24 xor + r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add + r7 = rotr_var(r7, r0); // 26 rotr + r4 = r5 * r7 + r4; // 27 mad + r3 = r2 * r4 + r3; // 28 mad + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load + r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load + r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load + r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add + r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add + r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add + r2 = mul_hi(r2, r5); // 35 mulhi + r4 = r4 ^ r2; // 36 xor + r6 = r6 * r5; // 37 mul + r7 = r7 ^ r0; // 38 xor + r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add + r2 = rotr_var(r2, r3); // 40 rotr + r7 = r7 - r0; // 41 sub + r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add + { uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl + r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add + r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load + r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load + r4 = mul_hi(r4, r2); // 48 mulhi + r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add + { uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl + r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add + r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load + r6 = rotl_imm(r6, 12u); // 53 rotl + r3 = rotl_imm(r3, 12u); // 54 rotl + r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load + r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add + r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load + r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add + r3 = mul_hi(r3, r2); // 60 mulhi + r6 = r6 | r4; // 61 or + { uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl + r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cu b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cu index 9a46b7480..af9003761 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cu +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/kernel_bound.cu @@ -36,69 +36,69 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba for (uint32_t it = 0u; it < 8u; ++it) { uint32_t sel = r0; r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add - r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // 1 shfl - r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add - r0 = rotl_imm(r0, 19u); // 3 rotl - r7 = rotr_var(r7, r6); // 4 rotr - r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add - r1 = __umulhi(r1, r7); // 6 mulhi - r4 = r4 ^ ds[r2 & mask]; // 7 load - r7 = r7 ^ ds[r4 & mask]; // 8 load - r0 = r0 ^ ds[r3 & mask]; // 9 load - r5 = r5 ^ ds[r1 & mask]; // 10 load - r1 = r1 ^ ds[r5 & mask]; // 11 load - r3 = __umulhi(r3, r5); // 12 mulhi - r1 = r1 ^ ds[r3 & mask]; // 13 load - r0 = r0 - r3; // 14 sub - r5 = r1 * r3 + r5; // 15 mad - r6 = __umulhi(r6, r1); // 16 mulhi - r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add - r0 = __umulhi(r0, r6); // 18 mulhi - r5 = rotr_var(r5, r3); // 19 rotr - r5 = __umulhi(r5, r2); // 20 mulhi - r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add - r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add - r1 = __umulhi(r1, r5); // 23 mulhi - r2 = r2 - r5; // 24 sub - r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 26 shfl - r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add - r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add - r2 = r2 ^ ds[r1 & mask]; // 29 load - r5 = r5 ^ ds[r7 & mask]; // 30 load - r2 = r2 ^ ds[r5 & mask]; // 31 load - r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 32 shfl - r4 = r5 * r7 + r4; // 33 mad - r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add - r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r7, 8); // 35 shfl - r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add - r5 = r5 ^ r7; // 37 xor - r2 = r2 | r1; // 38 or - r1 = __umulhi(r1, r0); // 39 mulhi - r6 = rotl_imm(r6, 19u); // 40 rotl - r4 = __umulhi(r4, r6); // 41 mulhi - r6 = r6 - r0; // 42 sub - r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl - r4 = r4 ^ ds[r2 & mask]; // 44 load - r1 = r1 ^ r3; // 45 xor - r7 = r7 ^ ds[r0 & mask]; // 46 load - r3 = r3 ^ ds[r1 & mask]; // 47 load - r5 = r5 * r3; // 48 mul - r1 = r1 - r5; // 49 sub - r2 = rotl_imm(r2, 8u); // 50 rotl - r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add - r4 = r4 ^ ds[r7 & mask]; // 52 load - r2 = r2 - r7; // 53 sub - r4 = r4 ^ r0; // 54 xor - r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add - r2 = r2 ^ ds[r4 & mask]; // 56 load - r0 = r1 * r4 + r0; // 57 mad - r3 = r3 ^ ds[r5 & mask]; // 58 load - r5 = r5 | r6; // 59 or - r6 = r5 * r7 + r6; // 60 mad - r4 = rotl_imm(r4, 28u); // 61 rotl - r5 = __umulhi(r5, r0); // 62 mulhi - r3 = r3 ^ ds[r6 & mask]; // 63 load + r7 = r7 ^ r0; // 1 xor + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // 2 shfl + r4 = r4 - r1; // 3 sub + r2 = r0 * r4 + r2; // 4 mad + r4 = rotl_imm(r4, 9u); // 5 rotl + r0 = rotr_var(r0, r2); // 6 rotr + r6 = r6 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load + r1 = r1 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load + r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load + r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load + r5 = r5 * r4; // 12 mul + r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load + r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl + r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl + r2 = r2 | r7; // 16 or + r0 = rotr_var(r0, r6); // 17 rotr + r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add + r7 = rotl_imm(r7, 24u); // 19 rotl + r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add + r2 = r2 | r6; // 21 or + r6 = r5 * r4 + r6; // 22 mad + r1 = r1 | r0; // 23 or + r6 = r6 ^ r1; // 24 xor + r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add + r7 = rotr_var(r7, r0); // 26 rotr + r4 = r5 * r7 + r4; // 27 mad + r3 = r2 * r4 + r3; // 28 mad + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load + r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load + r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load + r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add + r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add + r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add + r2 = __umulhi(r2, r5); // 35 mulhi + r4 = r4 ^ r2; // 36 xor + r6 = r6 * r5; // 37 mul + r7 = r7 ^ r0; // 38 xor + r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add + r2 = rotr_var(r2, r3); // 40 rotr + r7 = r7 - r0; // 41 sub + r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add + r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl + r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load + r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add + r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load + r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load + r4 = __umulhi(r4, r2); // 48 mulhi + r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add + r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl + r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add + r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load + r6 = rotl_imm(r6, 12u); // 53 rotl + r3 = rotl_imm(r3, 12u); // 54 rotl + r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add + r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load + r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add + r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load + r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add + r3 = __umulhi(r3, r2); // 60 mulhi + r6 = r6 | r4; // 61 or + r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl + r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load } uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.h b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.h index b16f7a4b7..03fac4c85 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.h +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.h @@ -105,5 +105,9 @@ IGNEUM_HD void mh_item(const uint32_t* cache, uint32_t t, uint32_t* s) { } for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u)); } -// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. -IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } +// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. +IGNEUM_HD uint32_t mh_j(uint32_t w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } +IGNEUM_HD uint32_t mh_t(uint32_t w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } +IGNEUM_HD uint32_t mh_addr(uint32_t t, uint32_t j) { uint32_t w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } +// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). +IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.metal b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.metal index d9fed7f50..1e2971b78 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.metal +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/memhard.metal @@ -90,8 +90,12 @@ inline void mh_item(device const uint* cache, uint t, thread uint* s) { } for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u)); } -// dataset[w] without the dataset: derive item w >> 4 and take word w & 15. -inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; } +// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 0 2 12 13 of w. +inline uint mh_j(uint w) { return ((w >> 0u) & 1u) | (((w >> 2u) & 1u) << 1) | (((w >> 12u) & 1u) << 2) | (((w >> 13u) & 1u) << 3); } +inline uint mh_t(uint w) { w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x00000fffu) | ((w >> 13u) << 12u); w = (w & 0x00000003u) | ((w >> 3u) << 2u); w = (w & 0x00000000u) | ((w >> 1u) << 0u); return w; } +inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 0u) << 1u) | (w & 0x00000000u) | (((j >> 0u) & 1u) << 0u); w = ((w >> 2u) << 3u) | (w & 0x00000003u) | (((j >> 1u) & 1u) << 2u); w = ((w >> 12u) << 13u) | (w & 0x00000fffu) | (((j >> 2u) & 1u) << 12u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 3u) & 1u) << 13u); return w; } +// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w). +inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, mh_t(w), s); return s[mh_j(w)]; } // One thread per segment (2^16 threads). kernel void igneum_cache_fill(device uint* cache [[buffer(0)]], uint gid [[thread_position_in_grid]]) { @@ -102,6 +106,5 @@ kernel void igneum_build(device const uint* cache [[buffer(0)]], device uint* da uint gid [[thread_position_in_grid]]) { uint s[16]; mh_item(cache, gid, s); - device uint* d = dataset + gid * 16u; - for (uint i = 0u; i < 16u; ++i) d[i] = s[i]; + for (uint i = 0u; i < 16u; ++i) dataset[mh_addr(gid, i)] = s[i]; } diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.h b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.h index 3eacb5594..5e6e8a130 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.h +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.h @@ -13,9 +13,9 @@ #define IGNEUM_SEED_STRING "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000" #define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07" -#define IGNEUM_GENERATOR 2 +#define IGNEUM_GENERATOR 3 #define IGNEUM_PROGRAM_ATTEMPT 0 -#define IGNEUM_PROGRAM_ID 0xa696c464d9e9649bull +#define IGNEUM_PROGRAM_ID 0x73bcbfe8ccf988f1ull #define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000" #define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000" #define IGNEUM_DAY0 0xceed56d7u @@ -27,10 +27,14 @@ #define IGNEUM_INSTR_COUNT 64 #define IGNEUM_LOADS_PER_HASH 128 #define IGNEUM_WIDE_LOADS_PER_HASH 0 -#define IGNEUM_OP_MIX "load=16 add=13 mulhi=9 shfl=5 sub=5 mad=4 rotl=4 xor=3 or=2 rotr=2 mul=1" +#define IGNEUM_OP_MIX "load=16 add=15 shfl=6 mad=4 or=4 rotl=4 rotr=4 xor=4 mulhi=3 mul=2 sub=2" +// Program class v3 (Counter ASIC 2.0, docs/plans/counter-asic-2-rollout.md): generator version 3; a worker that +// runs another class refuses this pack, and a job line names the class it wants (class=v3 era=). +#define IGNEUM_PROGRAM_CLASS "v3" +#define IGNEUM_ERA_SEED_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07" // Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item // derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule. -#define IGNEUM_LOAD_CLASS "mx8" +#define IGNEUM_LOAD_CLASS "mx8-erad810f22d" #define IGNEUM_CLASS_MIXER_MULT 8 #define IGNEUM_CACHE_GROWTH 1 // 1: cache words = 2^(26 + doublings(day)), doublings = floor(log2(1 + day / 1460)) #define IGNEUM_LOAD_SLOTS 16 @@ -39,6 +43,18 @@ #define IGNEUM_BYTES_PER_HASH 512 #define IGNEUM_FOLD_ROT 11 #define IGNEUM_FOLD_MUL 0x9e3779b1u +// Era layout (5 October 2026, docs/plans/era-layout.md): NOT the lottery hash. Every dataset load reads +// idx = ((rotl(src * STRIDE_MUL, STRIDE_ROT) & window mask) | window offset) & MASK; the window of a load site is the +// dataset, a half or a quarter of it (IGNEUM_ERA_WINDOWS: site:shrink:offset); dataset word w holds word j(w) of item +// t(w) with j's bits at the INTERLEAVE positions (memhard.h: mh_t, mh_j, mh_addr). +#define IGNEUM_ERA_LABEL "d810f22d" +#define IGNEUM_ERA_SEED_WORDS { 0xd810f22du, 0xcf9dc883u, 0x5f3e571fu, 0x2b7d97fcu, 0x810012c4u, 0x002d9798u, 0xa4180c41u, 0xa4562c21u } +#define IGNEUM_ERA_ALLOWED_WIDTHS { 1, 0, 0 } // words, ascending, 0 = unused; one entry pins the width +#define IGNEUM_ERA_WIDTH_WORDS 1 +#define IGNEUM_ERA_STRIDE_MUL 0x9ad30d99u +#define IGNEUM_ERA_STRIDE_ROT 29 +#define IGNEUM_ERA_INTERLEAVE { 0, 2, 12, 13 } +#define IGNEUM_ERA_WINDOWS "7:2:1 8:1:1 9:1:1 10:1:1 11:0:0 13:1:1 29:0:0 30:2:2 31:1:1 44:1:1 46:2:0 47:0:0 52:0:0 56:0:0 58:2:0 63:1:1" // 0 = closed-form dataset (ds_elem), 1 = memory-hard cache construction (MEMHARD.md, memhard.h) #define IGNEUM_DATASET_MODE 1 diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.json b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.json index 3f423788f..49d433d08 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.json +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.json @@ -1,8 +1,8 @@ { "format": "igneum-program-pack-3", - "generator": 2, + "generator": 3, "attempt": 0, - "program_id": "0xa696c464d9e9649b", + "program_id": "0x73bcbfe8ccf988f1", "program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32", "dataset_mode": "memory-hard", "seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000", @@ -15,7 +15,9 @@ "iterations": 8, "instruction_count": 64, "loads_per_hash": 128, - "load_class": "mx8", + "program_class": "v3", + "era_seed_bytes": "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07", + "load_class": "mx8-erad810f22d", "mixer_mult": 8, "cache_growth": true, "mixer": "class v3 (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): every mixer application of the item derivation is 8 applications with round keys (r * 8 + j + 1) * 0x9E3779B9, the 8 dependent cache reads per item unchanged; cache growth rule option C: cache words = 2^(26 + doublings(day)), dataset words = 2^(genesis_log2 + doublings(day)), doublings(day) = floor(log2(1 + day / 1460)) for day = days since genesis", @@ -24,7 +26,21 @@ "load_width_counts_4_16_64": [16, 0, 0], "bytes_per_hash": 512, "wide_load": "read-width experiment (5 October 2026, docs/plans/read-width.md), NOT the lottery hash: a load of W words (width field, 4 or 16) reads dataset[b .. b + W) with b = (src & mask) & ~(W - 1) and folds every word into dst: x = dst ^ w[0]; for j in 1..W: x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]; dst = x; width 1 is the plain load; the width is drawn per instruction from the class mix with one extra below(100) draw after the nine of version 2, and the program id is FNV-1a 64 over 'igneum-program-rw/' || generator_le32 || seed words || attempt_le32 || mix[3] || load_slots", - "op_mix": {"load": 16, "add": 13, "mulhi": 9, "shfl": 5, "sub": 5, "mad": 4, "rotl": 4, "xor": 3, "or": 2, "rotr": 2, "mul": 1}, + "era": { + "label": "d810f22d", + "seed_words": ["0xd810f22d", "0xcf9dc883", "0x5f3e571f", "0x2b7d97fc", "0x810012c4", "0x002d9798", "0xa4180c41", "0xa4562c21"], + "draw": "docs/plans/era-layout.md 1.1: SplitMix64 seeded with seed_words[0] | seed_words[1] << 32 of seed_words_from_bytes('igneum-era/' || n_le64 || E_n); width = allowed[below(|allowed|)], stride_mul = low32(next()) | 1, stride_rot = 1 + below(31), then four next() draws for a partial Fisher-Yates over positions log2(W)..15 of which 4 - log2(W) are used", + "allowed_widths": [1], + "width_words": 1, + "stride_mul": "0x9ad30d99", + "stride_rot": 29, + "interleave": [0, 2, 12, 13], + "address": "y = rotl(src * stride_mul, stride_rot); k = min(win, D - 26); idx = ((y & (mask >> k)) | ((off & (2^k - 1)) << (D - k))) & mask; a wide load aligns idx down to W words", + "windows": "per instruction, after the width roll: win = below(3), off = low32(next()) & (2^win - 1); used on a load slot (the instruction's win and off fields)", + "dataset_word": "dataset[w] = item(t(w))[j(w)]: j(w) gathers the bits of w at the interleave positions, t(w) is w with those bits removed", + "program_id_suffix": "'era/' || allowed[3] || width_words || stride_mul_le32 || stride_rot_le32 || interleave[4]" + }, + "op_mix": {"load": 16, "add": 15, "shfl": 6, "mad": 4, "or": 4, "rotl": 4, "rotr": 4, "xor": 4, "mulhi": 3, "mul": 2, "sub": 2}, "register_init": "for i in 0..7: x = nonce ^ seed_words[i]; x += 0x9e3779b9 * (i+1) (mod 2^32); x = splitmix32(x); r[i] = x ^ seed_words[(i+1) & 7]", "splitmix32": "x ^= x>>16; x *= 0x7feb352d; x ^= x>>15; x *= 0x846ca68b; x ^= x>>16", "iteration": "sel = r0 sampled once at the top of each iteration, then all instructions in order", @@ -63,69 +79,69 @@ "word": "dataset[w] = item(w >> 4)[w & 15]" }, "instructions": [ - {"i": 0, "op": "add", "dst": 4, "src": 5, "src2": 7, "imm": "0xea86e152", "imm2": "0x5810667a", "rot": 27, "bit": 13, "mask": 2, "width": 1}, - {"i": 1, "op": "shfl", "dst": 2, "src": 0, "src2": 7, "imm": "0xe3c2f9cb", "imm2": "0xde0bea4e", "rot": 6, "bit": 9, "mask": 4, "width": 1}, - {"i": 2, "op": "add", "dst": 3, "src": 2, "src2": 0, "imm": "0x2cccb6ca", "imm2": "0x642e66db", "rot": 27, "bit": 10, "mask": 2, "width": 1}, - {"i": 3, "op": "rotl", "dst": 0, "src": 2, "src2": 1, "imm": "0xb59e83b2", "imm2": "0x19c26fb9", "rot": 19, "bit": 20, "mask": 4, "width": 1}, - {"i": 4, "op": "rotr", "dst": 7, "src": 6, "src2": 5, "imm": "0x6f055f55", "imm2": "0x550e4ea1", "rot": 31, "bit": 20, "mask": 4, "width": 1}, - {"i": 5, "op": "add", "dst": 7, "src": 4, "src2": 7, "imm": "0xee02465f", "imm2": "0xc1535555", "rot": 31, "bit": 21, "mask": 4, "width": 1}, - {"i": 6, "op": "mulhi", "dst": 1, "src": 7, "src2": 5, "imm": "0x7826a6a7", "imm2": "0x946f7818", "rot": 18, "bit": 21, "mask": 8, "width": 1}, - {"i": 7, "op": "load", "dst": 4, "src": 2, "src2": 0, "imm": "0x5d080878", "imm2": "0xdf885578", "rot": 5, "bit": 18, "mask": 4, "width": 1}, - {"i": 8, "op": "load", "dst": 7, "src": 4, "src2": 1, "imm": "0x875bbb36", "imm2": "0x594a838f", "rot": 24, "bit": 4, "mask": 2, "width": 1}, - {"i": 9, "op": "load", "dst": 0, "src": 3, "src2": 1, "imm": "0xe5e607c2", "imm2": "0xa5cd9f75", "rot": 26, "bit": 28, "mask": 4, "width": 1}, - {"i": 10, "op": "load", "dst": 5, "src": 1, "src2": 3, "imm": "0xea3f7b43", "imm2": "0x10c8d4e7", "rot": 5, "bit": 29, "mask": 8, "width": 1}, - {"i": 11, "op": "load", "dst": 1, "src": 5, "src2": 4, "imm": "0x4454980f", "imm2": "0xebd31581", "rot": 10, "bit": 28, "mask": 16, "width": 1}, - {"i": 12, "op": "mulhi", "dst": 3, "src": 5, "src2": 7, "imm": "0xbfd5615c", "imm2": "0xd8224ae2", "rot": 21, "bit": 12, "mask": 2, "width": 1}, - {"i": 13, "op": "load", "dst": 1, "src": 3, "src2": 5, "imm": "0x35c07cc5", "imm2": "0xe82db54f", "rot": 7, "bit": 6, "mask": 8, "width": 1}, - {"i": 14, "op": "sub", "dst": 0, "src": 3, "src2": 0, "imm": "0x587ee0f1", "imm2": "0xfd23eefd", "rot": 16, "bit": 21, "mask": 16, "width": 1}, - {"i": 15, "op": "mad", "dst": 5, "src": 1, "src2": 3, "imm": "0x6974dd29", "imm2": "0xc8148960", "rot": 3, "bit": 11, "mask": 2, "width": 1}, - {"i": 16, "op": "mulhi", "dst": 6, "src": 1, "src2": 7, "imm": "0x3072c3c6", "imm2": "0x55ee21f8", "rot": 26, "bit": 1, "mask": 1, "width": 1}, - {"i": 17, "op": "add", "dst": 5, "src": 2, "src2": 2, "imm": "0x697b3d00", "imm2": "0x8b965b57", "rot": 9, "bit": 28, "mask": 1, "width": 1}, - {"i": 18, "op": "mulhi", "dst": 0, "src": 6, "src2": 3, "imm": "0x2910cacb", "imm2": "0x6ac79431", "rot": 7, "bit": 6, "mask": 4, "width": 1}, - {"i": 19, "op": "rotr", "dst": 5, "src": 3, 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2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 35, "op": "mulhi", "dst": 2, "src": 5, "src2": 6, "imm": "0x5892a9e6", "imm2": "0xc9824c94", "rot": 19, "bit": 26, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 36, "op": "xor", "dst": 4, "src": 2, "src2": 3, "imm": "0x7b5b5474", "imm2": "0x45cfc5dd", "rot": 17, "bit": 18, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 37, "op": "mul", "dst": 6, "src": 5, "src2": 7, "imm": "0xccf564a5", "imm2": "0x873ad101", "rot": 7, "bit": 11, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 38, "op": "xor", "dst": 7, "src": 0, "src2": 6, "imm": "0xcac8f06d", "imm2": "0x6b97c683", "rot": 18, "bit": 28, "mask": 2, "width": 1, "win": 0, "off": 0}, + {"i": 39, "op": "add", "dst": 7, "src": 2, "src2": 4, "imm": "0xb8180e9d", "imm2": "0x32bbd117", "rot": 23, "bit": 19, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 40, "op": "rotr", "dst": 2, "src": 3, "src2": 0, "imm": "0x2d6070bc", "imm2": "0x68ff101e", "rot": 13, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1}, + {"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0}, + {"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0}, + {"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0}, + {"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0}, + {"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0}, + {"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0}, + {"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0}, + {"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1} ] } diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.metal b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.metal index b899adecb..8c0a2d1cd 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.metal +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program.metal @@ -39,69 +39,69 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]], for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + select(0xea86e152u, 0x5810667au, ((sel >> 13u) & 1u) != 0u); // 0 - r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // 1 - r3 = r3 + r2 + select(0x2cccb6cau, 0x642e66dbu, ((sel >> 10u) & 1u) != 0u); // 2 - r0 = rotl_imm(r0, 19u); // 3 - r7 = rotr_var(r7, r6); // 4 - r7 = r7 + r4 + select(0xee02465fu, 0xc1535555u, ((sel >> 21u) & 1u) != 0u); // 5 - r1 = mulhi(r1, r7); // 6 - r4 = r4 ^ dataset[r2 & MASK]; // 7 - r7 = r7 ^ dataset[r4 & MASK]; // 8 - r0 = r0 ^ dataset[r3 & MASK]; // 9 - r5 = r5 ^ dataset[r1 & MASK]; // 10 - r1 = r1 ^ dataset[r5 & MASK]; // 11 - r3 = mulhi(r3, r5); // 12 - r1 = r1 ^ dataset[r3 & MASK]; // 13 - r0 = r0 - r3; // 14 - r5 = r1 * r3 + r5; // 15 - r6 = mulhi(r6, r1); // 16 - r5 = r5 + r2 + select(0x697b3d00u, 0x8b965b57u, ((sel >> 28u) & 1u) != 0u); // 17 - r0 = mulhi(r0, r6); // 18 - r5 = rotr_var(r5, r3); // 19 - r5 = mulhi(r5, r2); // 20 - r1 = r1 + r0 + select(0xebcf247au, 0x6d7e8d05u, ((sel >> 1u) & 1u) != 0u); // 21 - r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 22 - r1 = mulhi(r1, r5); // 23 - r2 = r2 - r5; // 24 - r7 = r7 + r4 + select(0x08ffa6c7u, 0x699ef1bbu, ((sel >> 2u) & 1u) != 0u); // 25 - r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 26 - r7 = r7 + r1 + select(0xe60fea84u, 0xb4ead2fbu, ((sel >> 14u) & 1u) != 0u); // 27 - r3 = r3 + r1 + select(0x65c76dabu, 0x8f30d21du, ((sel >> 6u) & 1u) != 0u); // 28 - r2 = r2 ^ dataset[r1 & MASK]; // 29 - r5 = r5 ^ dataset[r7 & MASK]; // 30 - r2 = r2 ^ dataset[r5 & MASK]; // 31 - r1 = r1 ^ simd_shuffle_xor(r7, (ushort)4); // 32 - r4 = r5 * r7 + r4; // 33 - r4 = r4 + r2 + select(0x0480debeu, 0xc7ce690cu, ((sel >> 21u) & 1u) != 0u); // 34 - r3 = r3 ^ simd_shuffle_xor(r7, (ushort)8); // 35 - r7 = r7 + r1 + select(0xc53b542eu, 0xe10c2c95u, ((sel >> 2u) & 1u) != 0u); // 36 - r5 = r5 ^ r7; // 37 - r2 = r2 | r1; // 38 - r1 = mulhi(r1, r0); // 39 - r6 = rotl_imm(r6, 19u); // 40 - r4 = mulhi(r4, r6); // 41 - r6 = r6 - r0; // 42 - r6 = r6 ^ simd_shuffle_xor(r3, (ushort)4); // 43 - r4 = r4 ^ dataset[r2 & MASK]; // 44 - r1 = r1 ^ r3; // 45 - r7 = r7 ^ dataset[r0 & MASK]; // 46 - r3 = r3 ^ dataset[r1 & MASK]; // 47 - r5 = r5 * r3; // 48 - r1 = r1 - r5; // 49 - r2 = rotl_imm(r2, 8u); // 50 - r1 = r1 + r5 + select(0xa900fec4u, 0x77b9bd43u, ((sel >> 23u) & 1u) != 0u); // 51 - r4 = r4 ^ dataset[r7 & MASK]; // 52 - r2 = r2 - r7; // 53 - r4 = r4 ^ r0; // 54 - r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 55 - r2 = r2 ^ dataset[r4 & MASK]; // 56 - r0 = r1 * r4 + r0; // 57 - r3 = r3 ^ dataset[r5 & MASK]; // 58 - r5 = r5 | r6; // 59 - r6 = r5 * r7 + r6; // 60 - r4 = rotl_imm(r4, 28u); // 61 - r5 = mulhi(r5, r0); // 62 - r3 = r3 ^ dataset[r6 & MASK]; // 63 + r7 = r7 ^ r0; // 1 + r3 = r3 ^ simd_shuffle_xor(r6, (ushort)1); // 2 + r4 = r4 - r1; // 3 + r2 = r0 * r4 + r2; // 4 + r4 = rotl_imm(r4, 9u); // 5 + r0 = rotr_var(r0, r2); // 6 + r6 = r6 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & MASK]; // 7 + r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 8 + r1 = r1 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 9 + r7 = r7 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10 + r7 = r7 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11 + r5 = r5 * r4; // 12 + r7 = r7 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13 + r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14 + r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15 + r2 = r2 | r7; // 16 + r0 = rotr_var(r0, r6); // 17 + r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 18 + r7 = rotl_imm(r7, 24u); // 19 + r6 = r6 + r7 + select(0x52334d12u, 0x8c9f0ef8u, ((sel >> 23u) & 1u) != 0u); // 20 + r2 = r2 | r6; // 21 + r6 = r5 * r4 + r6; // 22 + r1 = r1 | r0; // 23 + r6 = r6 ^ r1; // 24 + r2 = r2 + r6 + select(0x659fc3d3u, 0x9cec0e12u, ((sel >> 17u) & 1u) != 0u); // 25 + r7 = rotr_var(r7, r0); // 26 + r4 = r5 * r7 + r4; // 27 + r3 = r2 * r4 + r3; // 28 + r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29 + r2 = r2 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30 + r1 = r1 ^ dataset[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31 + r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32 + r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33 + r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34 + r2 = mulhi(r2, r5); // 35 + r4 = r4 ^ r2; // 36 + r6 = r6 * r5; // 37 + r7 = r7 ^ r0; // 38 + r7 = r7 + r2 + select(0xb8180e9du, 0x32bbd117u, ((sel >> 19u) & 1u) != 0u); // 39 + r2 = rotr_var(r2, r3); // 40 + r7 = r7 - r0; // 41 + r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42 + r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43 + r0 = r0 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44 + r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45 + r3 = r3 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46 + r6 = r6 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47 + r4 = mulhi(r4, r2); // 48 + r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49 + r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50 + r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51 + r5 = r5 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52 + r6 = rotl_imm(r6, 12u); // 53 + r3 = rotl_imm(r3, 12u); // 54 + r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55 + r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56 + r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57 + r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58 + r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59 + r3 = mulhi(r3, r2); // 60 + r6 = r6 | r4; // 61 + r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62 + r3 = r3 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63 } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program_bound.metal b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program_bound.metal index 2f0218149..bc806a1e1 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program_bound.metal +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/program_bound.metal @@ -41,69 +41,69 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]], for (uint it = 0u; it < 8u; ++it) { uint sel = r0; r4 = r4 + r5 + select(0xea86e152u, 0x5810667au, ((sel >> 13u) & 1u) != 0u); // 0 - r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // 1 - r3 = r3 + r2 + select(0x2cccb6cau, 0x642e66dbu, ((sel >> 10u) & 1u) != 0u); // 2 - r0 = rotl_imm(r0, 19u); // 3 - r7 = rotr_var(r7, r6); // 4 - r7 = r7 + r4 + select(0xee02465fu, 0xc1535555u, ((sel >> 21u) & 1u) != 0u); // 5 - r1 = mulhi(r1, r7); // 6 - r4 = r4 ^ dataset[r2 & MASK]; // 7 - r7 = r7 ^ dataset[r4 & MASK]; // 8 - r0 = r0 ^ dataset[r3 & MASK]; // 9 - r5 = r5 ^ dataset[r1 & MASK]; // 10 - r1 = r1 ^ dataset[r5 & MASK]; // 11 - r3 = mulhi(r3, r5); // 12 - r1 = r1 ^ dataset[r3 & MASK]; // 13 - r0 = r0 - r3; // 14 - r5 = r1 * r3 + r5; // 15 - r6 = mulhi(r6, r1); // 16 - r5 = r5 + r2 + select(0x697b3d00u, 0x8b965b57u, ((sel >> 28u) & 1u) != 0u); // 17 - r0 = mulhi(r0, r6); // 18 - r5 = rotr_var(r5, r3); // 19 - r5 = mulhi(r5, r2); // 20 - r1 = r1 + r0 + select(0xebcf247au, 0x6d7e8d05u, ((sel >> 1u) & 1u) != 0u); // 21 - r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 22 - r1 = mulhi(r1, r5); // 23 - r2 = r2 - r5; // 24 - r7 = r7 + r4 + select(0x08ffa6c7u, 0x699ef1bbu, ((sel >> 2u) & 1u) != 0u); // 25 - r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 26 - r7 = r7 + r1 + select(0xe60fea84u, 0xb4ead2fbu, ((sel >> 14u) & 1u) != 0u); // 27 - r3 = r3 + r1 + select(0x65c76dabu, 0x8f30d21du, ((sel >> 6u) & 1u) != 0u); // 28 - r2 = r2 ^ dataset[r1 & MASK]; // 29 - r5 = r5 ^ dataset[r7 & MASK]; // 30 - r2 = r2 ^ dataset[r5 & MASK]; // 31 - r1 = r1 ^ simd_shuffle_xor(r7, (ushort)4); // 32 - r4 = r5 * r7 + r4; // 33 - r4 = r4 + r2 + select(0x0480debeu, 0xc7ce690cu, ((sel >> 21u) & 1u) != 0u); // 34 - r3 = r3 ^ simd_shuffle_xor(r7, (ushort)8); // 35 - r7 = r7 + r1 + select(0xc53b542eu, 0xe10c2c95u, ((sel >> 2u) & 1u) != 0u); // 36 - r5 = r5 ^ r7; // 37 - r2 = r2 | r1; // 38 - r1 = mulhi(r1, r0); // 39 - r6 = rotl_imm(r6, 19u); // 40 - r4 = mulhi(r4, r6); // 41 - r6 = r6 - r0; // 42 - r6 = r6 ^ simd_shuffle_xor(r3, (ushort)4); // 43 - r4 = r4 ^ dataset[r2 & MASK]; // 44 - r1 = r1 ^ r3; // 45 - r7 = r7 ^ dataset[r0 & MASK]; // 46 - r3 = r3 ^ dataset[r1 & MASK]; // 47 - r5 = r5 * r3; // 48 - r1 = r1 - r5; // 49 - r2 = rotl_imm(r2, 8u); // 50 - r1 = r1 + r5 + select(0xa900fec4u, 0x77b9bd43u, ((sel >> 23u) & 1u) != 0u); // 51 - r4 = r4 ^ dataset[r7 & MASK]; // 52 - r2 = r2 - r7; // 53 - r4 = r4 ^ r0; // 54 - r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 55 - r2 = r2 ^ dataset[r4 & MASK]; // 56 - r0 = r1 * r4 + r0; // 57 - r3 = r3 ^ dataset[r5 & MASK]; // 58 - r5 = r5 | r6; // 59 - r6 = r5 * r7 + r6; // 60 - r4 = rotl_imm(r4, 28u); // 61 - r5 = mulhi(r5, r0); // 62 - r3 = r3 ^ dataset[r6 & MASK]; // 63 + r7 = r7 ^ r0; // 1 + r3 = r3 ^ simd_shuffle_xor(r6, (ushort)1); // 2 + r4 = r4 - r1; // 3 + r2 = r0 * r4 + r2; // 4 + r4 = rotl_imm(r4, 9u); // 5 + r0 = rotr_var(r0, r2); // 6 + r6 = r6 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x04000000u) & MASK]; // 7 + r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 8 + r1 = r1 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 9 + r7 = r7 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10 + r7 = r7 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11 + r5 = r5 * r4; // 12 + r7 = r7 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13 + r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14 + r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15 + r2 = r2 | r7; // 16 + r0 = rotr_var(r0, r6); // 17 + r7 = r7 + r5 + select(0xf66e7017u, 0xb9e3577eu, ((sel >> 12u) & 1u) != 0u); // 18 + r7 = rotl_imm(r7, 24u); // 19 + r6 = r6 + r7 + select(0x52334d12u, 0x8c9f0ef8u, ((sel >> 23u) & 1u) != 0u); // 20 + r2 = r2 | r6; // 21 + r6 = r5 * r4 + r6; // 22 + r1 = r1 | r0; // 23 + r6 = r6 ^ r1; // 24 + r2 = r2 + r6 + select(0x659fc3d3u, 0x9cec0e12u, ((sel >> 17u) & 1u) != 0u); // 25 + r7 = rotr_var(r7, r0); // 26 + r4 = r5 * r7 + r4; // 27 + r3 = r2 * r4 + r3; // 28 + r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29 + r2 = r2 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30 + r1 = r1 ^ dataset[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31 + r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32 + r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33 + r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34 + r2 = mulhi(r2, r5); // 35 + r4 = r4 ^ r2; // 36 + r6 = r6 * r5; // 37 + r7 = r7 ^ r0; // 38 + r7 = r7 + r2 + select(0xb8180e9du, 0x32bbd117u, ((sel >> 19u) & 1u) != 0u); // 39 + r2 = rotr_var(r2, r3); // 40 + r7 = r7 - r0; // 41 + r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42 + r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43 + r0 = r0 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44 + r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45 + r3 = r3 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46 + r6 = r6 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47 + r4 = mulhi(r4, r2); // 48 + r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49 + r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50 + r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51 + r5 = r5 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52 + r6 = rotl_imm(r6, 12u); // 53 + r3 = rotl_imm(r3, 12u); // 54 + r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55 + r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56 + r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57 + r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58 + r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59 + r3 = mulhi(r3, r2); // 60 + r6 = r6 | r4; // 61 + r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62 + r3 = r3 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63 } uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u); uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u); diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.h b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.h index f78994362..acd68d25e 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.h +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.h @@ -1,5 +1,5 @@ // Generated by igneum-pow export (generator v2) for seed "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000". Do not edit by hand. -// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset +// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset #pragma once #ifdef __cplusplus #include @@ -11,29 +11,29 @@ static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u }; static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = { { // base nonce 0 - 0x731250f1008c6f8eull, 0xb89b396aa5e33597ull, 0xbc96ebcdb47c61e4ull, 0xac1414cd0fb91152ull, 0x1cc2d1847875555eull, 0x071f703c82efff0cull, 0x21147b8c58bc96e4ull, 0xf412422862c643e6ull, - 0xb8a5c330668e9283ull, 0x994558a2b24a6557ull, 0xb2fb321e884a1fedull, 0xa8f928a38622b10eull, 0x9ea4cfcfc2c96d8bull, 0xc082abc94d5dfb18ull, 0x695239a4a852e0f9ull, 0xef804c526240ce15ull, - 0x624303d31812df0dull, 0xcfd82ed4955f140aull, 0x6569ae6a4a436a9aull, 0xc17f46cf926a7a0cull, 0x721fe9c93267d13bull, 0xf09fe97d5ce6bfbbull, 0x455d853d3913d6a3ull, 0x4fbb5f43bd1af7eaull, - 0x864d689410bb8ed0ull, 0xe8c93188d7f02b04ull, 0xebaafb6120560360ull, 0xde81676bff855560ull, 0xd0b3ae8111aab7c3ull, 0xacd97035767867caull, 0x1970c0b030b99c03ull, 0x09fed95e63215205ull + 0xd424577fce4a7a60ull, 0x07a04a71b7dc9e24ull, 0x9f3738f74b5781a0ull, 0x3e14bf6f995474dcull, 0xa3341f1327cededfull, 0xbb8340ed0f96a60aull, 0x26bc9988fddcafe8ull, 0x6711837d288eb5b1ull, + 0x2528efd21aaea539ull, 0x9a9e5e921805ad1aull, 0xf8f603042c024e9dull, 0x2023b9f4d4b69a6full, 0x0f68fa939013c11eull, 0x4b2db89527dd4246ull, 0xe30b45f6467fe6daull, 0x09a4ce72a8670daaull, + 0x9b373bcbd8ac276dull, 0x32409c8adad8122bull, 0xf3c9573d9b139a2eull, 0x6ce5852802493cffull, 0x7ec131a18ffea8d3ull, 0x9eca44ce48fcd206ull, 0x9720d6ef2d21f096ull, 0xff5a9e8b9c875129ull, + 0xf090b543042dcc0bull, 0xbdb38142d8f1866aull, 0xa65a997ce2fe84f9ull, 0x82b38b1f4b0389f3ull, 0x744c612dfa85b844ull, 0x1549edd4ebe3e1a1ull, 0x32528ae5d72962b7ull, 0x5eb43d7efa91792aull }, { // base nonce 4096 - 0x3d4f7e76fa55a96aull, 0xd54574ccb1a27843ull, 0xeb1635ddd5f1e181ull, 0x1e49a6cf24085bd9ull, 0x9f929d79ad731c0eull, 0x5caca654a4bd4f0full, 0x33eb9defb51424b9ull, 0x04f1f3c93663c27eull, - 0xad1c775687a46553ull, 0xc57c600167bc7571ull, 0xaf0b8e2f9a316b22ull, 0xa01088974b376d8eull, 0x14555ccee9288fddull, 0x0d1d576ea396fbe7ull, 0x8cf63b15a58299bfull, 0x49f530db99fd5f01ull, - 0x30324c49b12da61bull, 0xeb6fc871f103ad7bull, 0x8ac3271ce7edfc29ull, 0x2804099c65265affull, 0xc4d9377a427c3337ull, 0x566c1e580b940448ull, 0x790b966beb7bebb3ull, 0xba5da14cc619efe0ull, - 0x5da22ad9ae88fcd7ull, 0x24221e506877ef84ull, 0xfcda89486e6e78caull, 0xfd9a09b3587ba8fbull, 0x4fdb52f5b31ca54aull, 0x9cf4a2730edbf331ull, 0xb28717ae699944bbull, 0x0889c8c6adecb410ull + 0xb1a4dad6dac881e3ull, 0xa7c70bd09b22e232ull, 0xfb717dd0ee8c7b3bull, 0x75d13d70eecb7027ull, 0x37e718c5d2899b3dull, 0x4782272ccca87766ull, 0xf1729c252c3e0938ull, 0x5f0f04471bfcb956ull, + 0x093dcb86bfd512c7ull, 0x7a94acb9059c450cull, 0x331dcdd972d3690full, 0x54af5b1f80d22001ull, 0x4ee4a70cac47cb2bull, 0x99250b8d1cc2c845ull, 0xe4c21f96fc9bc9c6ull, 0x0b2f74431eae748aull, + 0x28477c082bd7ce0bull, 0x97b639e1f7ece650ull, 0xbc0eb237c118abdfull, 0xbf4b66de93c3d605ull, 0xec595dd050696fc7ull, 0xca188fcb2e52bf3bull, 0xce6c1500d389901cull, 0x70d98a68e5629e8bull, + 0xb1a99d60c977035aull, 0xb9ca4f57bd634b62ull, 0xab823071d8714434ull, 0x4a64d6115c4a68c3ull, 0x83b8e36475aa97dbull, 0x76a86a5c0b8eb3c3ull, 0x80b50965cb384920ull, 0xebd51aa25f279b52ull }, { // base nonce 1000000 - 0x377dfe4959f008b5ull, 0xd1bc9ed622919f80ull, 0x7c8c576aebc618bbull, 0x7930d463eceb4becull, 0xd7c8081c372c0e96ull, 0xff093d43f46685c2ull, 0x64d59d5e4abdef5cull, 0xd0b6c0699e0d51f8ull, - 0xbf73d4c2e7d7bb5cull, 0xb461b9770521b1b8ull, 0x224eaf296658b9c0ull, 0x81233334fb928726ull, 0xa10c5ee0aecc8251ull, 0xcd1a7e1b3cb970e7ull, 0x573c61ddaaa8fcccull, 0x67dd7ae97a699881ull, - 0x6df554eae8e0482aull, 0x61f528d7eba4cf89ull, 0xc1f241f1f41fc34dull, 0x25e1b51094413da0ull, 0x9be1d90ff6f51065ull, 0x21fc77cf9089f049ull, 0x1fadecae2996b343ull, 0xbd170b4f84703b24ull, - 0x0a7493c2ebd8bfb5ull, 0xd1d6e43170ced136ull, 0xe87fadf2a2c02a52ull, 0x2f873ddc2cf9f022ull, 0xa3963afdf94f3307ull, 0x3dfff37956161da1ull, 0xa60a7a56137b4231ull, 0xb8abcc39f8cb021aull + 0x0075777e728c0393ull, 0xa7fb5870a6991c5cull, 0xfdb4737b88c1fc4eull, 0x20459d2a43909ba9ull, 0x2d05fcdfd72f04b4ull, 0x33a44106a40eded3ull, 0xc365f536aa848b35ull, 0xe4fba4d51458e902ull, + 0x4d490be32f29d621ull, 0x95c5cd90faa84cfaull, 0xe6b90105cb7bec0dull, 0xaf106086897d202eull, 0x74e0a8d95386cab8ull, 0xd82da2ceda8b3794ull, 0x4efb171e065a3ffaull, 0x350246d8be1ac9c4ull, + 0x4134d472c2ecc1f9ull, 0xf57ea25951f560d3ull, 0xad70814322094688ull, 0x7162d5a0882f8aecull, 0x925135af6dd034f0ull, 0x36d01dcac09c0535ull, 0xae05981d39512765ull, 0x347bf7a59a4788aeull, + 0x39cd25ee0ffadb23ull, 0xbcf8c0280e4db403ull, 0x203323bfd810035full, 0x13a3354a07423e16ull, 0xcb70b4756f46eb2eull, 0x1c9941fe799cf7b6ull, 0x007b2b0035a673aeull, 0x4587d1a7e011792cull } }; // Dataset self-test: dataset[0..15] and dataset[IGNEUM_MASK] (268435455). static const uint32_t IGNEUM_DS_HEAD[16] = { - 0x19c6837fu, 0xdf3adfb8u, 0xc5f0629fu, 0x03e38ae8u, 0xc5de2525u, 0xa34a4906u, 0x898367cbu, 0x35b56808u, - 0xb886e673u, 0x1ee29eceu, 0x0cc36c88u, 0xc984181bu, 0x3d9d15f6u, 0x27c7d52au, 0xc268cf69u, 0x99b3c5c2u + 0x19c6837fu, 0xdf3adfb8u, 0xbd3f6aedu, 0xb8bede0du, 0xc5f0629fu, 0x03e38ae8u, 0xc435a60eu, 0xfadee916u, + 0x827e59afu, 0x8cf592f5u, 0x60286061u, 0x5d9abc1cu, 0xa85d0c39u, 0x4247a100u, 0xd41a5b0du, 0x3f33dc64u }; static const uint32_t IGNEUM_DS_LAST_INDEX = 268435455u; static const uint32_t IGNEUM_DS_LAST = 0x8d66c390u; @@ -43,7 +43,7 @@ static const uint32_t IGNEUM_DS_SAMPLE_INDEX[IGNEUM_DS_SAMPLES] = { 59471966u, 217795994u, 208353206u, 42483309u, 172547758u, 148076330u, 183853158u, 214389424u, 267488061u, 169781097u, 184093494u, 153880993u, 84977930u, 46426879u, 3093825u, 225364072u, 44593546u, 260713159u, 168250303u, 52384140u, 223401610u, 45554030u, 95410555u, 175039924u, 79171087u, 267580473u, 24168642u, 37981670u, 171551130u, 195559979u, 204611762u, 140997658u, 138925853u, 86637313u, 20736778u, 219665210u, 160430336u, 264654675u, 8013395u, 228945585u, 213884386u, 104419827u, 44185464u, 142737231u, 99284897u, 132475900u, 61861762u, 132056166u, 262388043u, 91878046u, 117353561u, 124768597u, 71352993u, 190698941u, 46055428u, 55281366u, 165145231u, 106810753u, 171985651u, 232085256u, 159510492u, 40072060u, 209107596u, 39023794u }; static const uint32_t IGNEUM_DS_SAMPLE_VALUE[IGNEUM_DS_SAMPLES] = { - 0xe53754ceu, 0xc6792663u, 0x0ca9fdceu, 0x96159926u, 0xfca71449u, 0x54522663u, 0xd0160df7u, 0x301be5a9u, 0xb0de07c5u, 0xb8f1c964u, 0xcef19286u, 0xc9c7985du, 0x9db14da9u, 0xda9f746du, 0x8747e5a1u, 0x545158e0u, 0xdf31afbbu, 0x4daa9b4cu, 0x1f0762ffu, 0x80a2d158u, 0xf762ad72u, 0x7ee04a69u, 0xd07df0e9u, 0x87cfc4abu, 0x9de7bb05u, 0xcd214af2u, 0xbd15dc85u, 0x89f48a42u, 0xd49c8a27u, 0xbc60a7e1u, 0xafc36693u, 0x4876871fu, 0x703246c4u, 0xbb823e84u, 0xa13f71a1u, 0xf2dd8540u, 0x74b039d1u, 0x84e8a275u, 0x750744bbu, 0x3f690b5fu, 0x5e75ecbdu, 0x36a11cc7u, 0x65e888cfu, 0x2e8538c8u, 0x14f5fec9u, 0x7329f625u, 0x42ad9261u, 0x120aea25u, 0x5374b09fu, 0x4fa85aa3u, 0xcb856f4eu, 0x526707bau, 0x82d847dau, 0xaed963e5u, 0x1516404bu, 0x2e565dddu, 0x46d1dacfu, 0xf7bb9e4cu, 0x61ae3b87u, 0x9daeed43u, 0xcf6bc86fu, 0x24f111d5u, 0x4356a558u, 0x0890de16u + 0xd088e877u, 0x2f25cbd2u, 0x9e26cf29u, 0xd3b102e0u, 0x3250b4a2u, 0xa0716e94u, 0x6497643cu, 0xa9b78313u, 0x69d951fcu, 0xa1b35f16u, 0xfee8e051u, 0x6098ad8cu, 0x27f0b64eu, 0x5c464cb0u, 0x1a3f0ce6u, 0xdbe10965u, 0x41d9309eu, 0xac9f9678u, 0x03d686a8u, 0x67544111u, 0xa7cad073u, 0x4e9c542du, 0xe7c3c2c7u, 0x9c624803u, 0x71780762u, 0xde7bcf5eu, 0xe319f472u, 0x89a3bc8au, 0xa4a01afbu, 0x72c52455u, 0xe877adf6u, 0xea1e321cu, 0xa518e572u, 0x8526fe55u, 0x8bde9bd3u, 0xe5fd50dfu, 0x3f994c85u, 0x02972af2u, 0x8bad5ffdu, 0xfc0becf6u, 0xc03e2465u, 0x0bbe949eu, 0x1e696b57u, 0x593feba2u, 0x1c0b992au, 0x4905aca0u, 0xf6e70116u, 0x427aa5f2u, 0x128898cfu, 0x6acfe21eu, 0x9a0ae2e4u, 0xc025b697u, 0x91f0a3d0u, 0x053041bbu, 0xf7d767d8u, 0xcb7b7b2bu, 0x53597840u, 0xdc45ee7fu, 0x07484a2eu, 0x635c8369u, 0x09a65a56u, 0xd216baeeu, 0x9cbd726cu, 0x5e566286u }; // Cache self-test (memory-hard mode): cache[0..15], the last 16 words, and FNV-1a 64 over all 2^26 words. static const uint32_t IGNEUM_CACHE_HEAD[16] = { diff --git a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.json b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.json index 4e8720b3b..20e7fde27 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.json +++ b/proto-cuda/packs-ca2-mixer/mx8-devnet-epoch0/vectors.json @@ -5,31 +5,31 @@ "dataset_log2_words": 28, "mask": "0x0fffffff", "lanes": 32, - "source": "igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset", + "source": "igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset", "warps": [ {"base_nonce": 0, "expected": [ - "0x731250f1008c6f8e", "0xb89b396aa5e33597", "0xbc96ebcdb47c61e4", "0xac1414cd0fb91152", "0x1cc2d1847875555e", "0x071f703c82efff0c", "0x21147b8c58bc96e4", "0xf412422862c643e6", - "0xb8a5c330668e9283", "0x994558a2b24a6557", "0xb2fb321e884a1fed", "0xa8f928a38622b10e", "0x9ea4cfcfc2c96d8b", "0xc082abc94d5dfb18", "0x695239a4a852e0f9", "0xef804c526240ce15", - "0x624303d31812df0d", "0xcfd82ed4955f140a", "0x6569ae6a4a436a9a", "0xc17f46cf926a7a0c", "0x721fe9c93267d13b", "0xf09fe97d5ce6bfbb", "0x455d853d3913d6a3", "0x4fbb5f43bd1af7ea", - "0x864d689410bb8ed0", "0xe8c93188d7f02b04", "0xebaafb6120560360", "0xde81676bff855560", "0xd0b3ae8111aab7c3", "0xacd97035767867ca", "0x1970c0b030b99c03", "0x09fed95e63215205" + "0xd424577fce4a7a60", "0x07a04a71b7dc9e24", "0x9f3738f74b5781a0", "0x3e14bf6f995474dc", "0xa3341f1327cededf", "0xbb8340ed0f96a60a", "0x26bc9988fddcafe8", "0x6711837d288eb5b1", + "0x2528efd21aaea539", "0x9a9e5e921805ad1a", "0xf8f603042c024e9d", "0x2023b9f4d4b69a6f", "0x0f68fa939013c11e", "0x4b2db89527dd4246", "0xe30b45f6467fe6da", "0x09a4ce72a8670daa", + "0x9b373bcbd8ac276d", "0x32409c8adad8122b", "0xf3c9573d9b139a2e", "0x6ce5852802493cff", "0x7ec131a18ffea8d3", "0x9eca44ce48fcd206", "0x9720d6ef2d21f096", "0xff5a9e8b9c875129", + "0xf090b543042dcc0b", "0xbdb38142d8f1866a", "0xa65a997ce2fe84f9", "0x82b38b1f4b0389f3", "0x744c612dfa85b844", "0x1549edd4ebe3e1a1", "0x32528ae5d72962b7", "0x5eb43d7efa91792a" ]}, {"base_nonce": 4096, "expected": [ - "0x3d4f7e76fa55a96a", "0xd54574ccb1a27843", "0xeb1635ddd5f1e181", "0x1e49a6cf24085bd9", "0x9f929d79ad731c0e", "0x5caca654a4bd4f0f", "0x33eb9defb51424b9", "0x04f1f3c93663c27e", - "0xad1c775687a46553", "0xc57c600167bc7571", "0xaf0b8e2f9a316b22", "0xa01088974b376d8e", "0x14555ccee9288fdd", "0x0d1d576ea396fbe7", "0x8cf63b15a58299bf", "0x49f530db99fd5f01", - "0x30324c49b12da61b", "0xeb6fc871f103ad7b", "0x8ac3271ce7edfc29", "0x2804099c65265aff", "0xc4d9377a427c3337", "0x566c1e580b940448", "0x790b966beb7bebb3", "0xba5da14cc619efe0", - "0x5da22ad9ae88fcd7", "0x24221e506877ef84", "0xfcda89486e6e78ca", "0xfd9a09b3587ba8fb", "0x4fdb52f5b31ca54a", "0x9cf4a2730edbf331", "0xb28717ae699944bb", "0x0889c8c6adecb410" + "0xb1a4dad6dac881e3", "0xa7c70bd09b22e232", "0xfb717dd0ee8c7b3b", "0x75d13d70eecb7027", "0x37e718c5d2899b3d", "0x4782272ccca87766", "0xf1729c252c3e0938", "0x5f0f04471bfcb956", + "0x093dcb86bfd512c7", "0x7a94acb9059c450c", "0x331dcdd972d3690f", "0x54af5b1f80d22001", "0x4ee4a70cac47cb2b", "0x99250b8d1cc2c845", "0xe4c21f96fc9bc9c6", "0x0b2f74431eae748a", + "0x28477c082bd7ce0b", "0x97b639e1f7ece650", "0xbc0eb237c118abdf", "0xbf4b66de93c3d605", "0xec595dd050696fc7", "0xca188fcb2e52bf3b", "0xce6c1500d389901c", "0x70d98a68e5629e8b", + "0xb1a99d60c977035a", "0xb9ca4f57bd634b62", "0xab823071d8714434", "0x4a64d6115c4a68c3", "0x83b8e36475aa97db", "0x76a86a5c0b8eb3c3", "0x80b50965cb384920", "0xebd51aa25f279b52" ]}, {"base_nonce": 1000000, "expected": [ - "0x377dfe4959f008b5", "0xd1bc9ed622919f80", "0x7c8c576aebc618bb", "0x7930d463eceb4bec", "0xd7c8081c372c0e96", "0xff093d43f46685c2", "0x64d59d5e4abdef5c", "0xd0b6c0699e0d51f8", - "0xbf73d4c2e7d7bb5c", "0xb461b9770521b1b8", "0x224eaf296658b9c0", "0x81233334fb928726", "0xa10c5ee0aecc8251", "0xcd1a7e1b3cb970e7", "0x573c61ddaaa8fccc", "0x67dd7ae97a699881", - "0x6df554eae8e0482a", "0x61f528d7eba4cf89", "0xc1f241f1f41fc34d", "0x25e1b51094413da0", "0x9be1d90ff6f51065", "0x21fc77cf9089f049", "0x1fadecae2996b343", "0xbd170b4f84703b24", - "0x0a7493c2ebd8bfb5", "0xd1d6e43170ced136", "0xe87fadf2a2c02a52", "0x2f873ddc2cf9f022", "0xa3963afdf94f3307", "0x3dfff37956161da1", "0xa60a7a56137b4231", "0xb8abcc39f8cb021a" + "0x0075777e728c0393", "0xa7fb5870a6991c5c", "0xfdb4737b88c1fc4e", "0x20459d2a43909ba9", "0x2d05fcdfd72f04b4", "0x33a44106a40eded3", "0xc365f536aa848b35", "0xe4fba4d51458e902", + "0x4d490be32f29d621", "0x95c5cd90faa84cfa", "0xe6b90105cb7bec0d", "0xaf106086897d202e", "0x74e0a8d95386cab8", "0xd82da2ceda8b3794", "0x4efb171e065a3ffa", "0x350246d8be1ac9c4", + "0x4134d472c2ecc1f9", "0xf57ea25951f560d3", "0xad70814322094688", "0x7162d5a0882f8aec", "0x925135af6dd034f0", "0x36d01dcac09c0535", "0xae05981d39512765", "0x347bf7a59a4788ae", + "0x39cd25ee0ffadb23", "0xbcf8c0280e4db403", "0x203323bfd810035f", "0x13a3354a07423e16", "0xcb70b4756f46eb2e", "0x1c9941fe799cf7b6", "0x007b2b0035a673ae", "0x4587d1a7e011792c" ]} ], - "dataset_head": ["0x19c6837f", "0xdf3adfb8", "0xc5f0629f", "0x03e38ae8", "0xc5de2525", "0xa34a4906", "0x898367cb", "0x35b56808", "0xb886e673", "0x1ee29ece", "0x0cc36c88", "0xc984181b", "0x3d9d15f6", "0x27c7d52a", "0xc268cf69", "0x99b3c5c2"], + "dataset_head": ["0x19c6837f", "0xdf3adfb8", "0xbd3f6aed", "0xb8bede0d", "0xc5f0629f", "0x03e38ae8", "0xc435a60e", "0xfadee916", "0x827e59af", "0x8cf592f5", "0x60286061", "0x5d9abc1c", "0xa85d0c39", "0x4247a100", "0xd41a5b0d", "0x3f33dc64"], "dataset_last_index": 268435455, "dataset_last": "0x8d66c390", - "dataset_samples": [{"index": 59471966, "value": "0xe53754ce"}, {"index": 217795994, "value": "0xc6792663"}, {"index": 208353206, "value": "0x0ca9fdce"}, {"index": 42483309, "value": "0x96159926"}, {"index": 172547758, "value": "0xfca71449"}, {"index": 148076330, "value": "0x54522663"}, {"index": 183853158, "value": "0xd0160df7"}, {"index": 214389424, "value": "0x301be5a9"}, {"index": 267488061, "value": "0xb0de07c5"}, {"index": 169781097, "value": "0xb8f1c964"}, {"index": 184093494, "value": "0xcef19286"}, {"index": 153880993, "value": "0xc9c7985d"}, {"index": 84977930, "value": "0x9db14da9"}, {"index": 46426879, "value": "0xda9f746d"}, {"index": 3093825, "value": "0x8747e5a1"}, {"index": 225364072, "value": "0x545158e0"}, {"index": 44593546, "value": "0xdf31afbb"}, {"index": 260713159, "value": "0x4daa9b4c"}, {"index": 168250303, "value": "0x1f0762ff"}, {"index": 52384140, "value": "0x80a2d158"}, {"index": 223401610, "value": "0xf762ad72"}, {"index": 45554030, "value": "0x7ee04a69"}, {"index": 95410555, "value": "0xd07df0e9"}, {"index": 175039924, "value": "0x87cfc4ab"}, {"index": 79171087, "value": "0x9de7bb05"}, {"index": 267580473, "value": "0xcd214af2"}, {"index": 24168642, "value": "0xbd15dc85"}, {"index": 37981670, "value": "0x89f48a42"}, {"index": 171551130, "value": "0xd49c8a27"}, {"index": 195559979, "value": "0xbc60a7e1"}, {"index": 204611762, "value": "0xafc36693"}, {"index": 140997658, "value": "0x4876871f"}, {"index": 138925853, "value": "0x703246c4"}, {"index": 86637313, "value": "0xbb823e84"}, {"index": 20736778, "value": "0xa13f71a1"}, {"index": 219665210, "value": "0xf2dd8540"}, {"index": 160430336, "value": "0x74b039d1"}, {"index": 264654675, "value": "0x84e8a275"}, {"index": 8013395, "value": "0x750744bb"}, {"index": 228945585, "value": "0x3f690b5f"}, {"index": 213884386, "value": "0x5e75ecbd"}, {"index": 104419827, "value": "0x36a11cc7"}, {"index": 44185464, "value": "0x65e888cf"}, {"index": 142737231, "value": "0x2e8538c8"}, {"index": 99284897, "value": "0x14f5fec9"}, {"index": 132475900, "value": "0x7329f625"}, {"index": 61861762, "value": "0x42ad9261"}, {"index": 132056166, "value": "0x120aea25"}, {"index": 262388043, "value": "0x5374b09f"}, {"index": 91878046, "value": "0x4fa85aa3"}, {"index": 117353561, "value": "0xcb856f4e"}, {"index": 124768597, "value": "0x526707ba"}, {"index": 71352993, "value": "0x82d847da"}, {"index": 190698941, "value": "0xaed963e5"}, {"index": 46055428, "value": "0x1516404b"}, {"index": 55281366, "value": "0x2e565ddd"}, {"index": 165145231, "value": "0x46d1dacf"}, {"index": 106810753, "value": "0xf7bb9e4c"}, {"index": 171985651, "value": "0x61ae3b87"}, {"index": 232085256, "value": "0x9daeed43"}, {"index": 159510492, "value": "0xcf6bc86f"}, {"index": 40072060, "value": "0x24f111d5"}, {"index": 209107596, "value": "0x4356a558"}, {"index": 39023794, "value": "0x0890de16"}], + "dataset_samples": [{"index": 59471966, "value": "0xd088e877"}, {"index": 217795994, "value": "0x2f25cbd2"}, {"index": 208353206, "value": "0x9e26cf29"}, {"index": 42483309, "value": "0xd3b102e0"}, {"index": 172547758, "value": "0x3250b4a2"}, {"index": 148076330, "value": "0xa0716e94"}, {"index": 183853158, "value": "0x6497643c"}, {"index": 214389424, "value": "0xa9b78313"}, {"index": 267488061, "value": "0x69d951fc"}, {"index": 169781097, "value": "0xa1b35f16"}, {"index": 184093494, "value": "0xfee8e051"}, {"index": 153880993, "value": "0x6098ad8c"}, {"index": 84977930, "value": "0x27f0b64e"}, {"index": 46426879, "value": "0x5c464cb0"}, {"index": 3093825, "value": "0x1a3f0ce6"}, {"index": 225364072, "value": "0xdbe10965"}, {"index": 44593546, "value": "0x41d9309e"}, {"index": 260713159, "value": "0xac9f9678"}, {"index": 168250303, "value": "0x03d686a8"}, {"index": 52384140, "value": "0x67544111"}, {"index": 223401610, "value": "0xa7cad073"}, {"index": 45554030, "value": "0x4e9c542d"}, {"index": 95410555, "value": "0xe7c3c2c7"}, {"index": 175039924, "value": "0x9c624803"}, {"index": 79171087, "value": "0x71780762"}, {"index": 267580473, "value": "0xde7bcf5e"}, {"index": 24168642, "value": "0xe319f472"}, {"index": 37981670, "value": "0x89a3bc8a"}, {"index": 171551130, "value": "0xa4a01afb"}, {"index": 195559979, "value": "0x72c52455"}, {"index": 204611762, "value": "0xe877adf6"}, {"index": 140997658, "value": "0xea1e321c"}, {"index": 138925853, "value": "0xa518e572"}, {"index": 86637313, "value": "0x8526fe55"}, {"index": 20736778, "value": "0x8bde9bd3"}, {"index": 219665210, "value": "0xe5fd50df"}, {"index": 160430336, "value": "0x3f994c85"}, {"index": 264654675, "value": "0x02972af2"}, {"index": 8013395, "value": "0x8bad5ffd"}, {"index": 228945585, "value": "0xfc0becf6"}, {"index": 213884386, "value": "0xc03e2465"}, {"index": 104419827, "value": "0x0bbe949e"}, {"index": 44185464, "value": "0x1e696b57"}, {"index": 142737231, "value": "0x593feba2"}, {"index": 99284897, "value": "0x1c0b992a"}, {"index": 132475900, "value": "0x4905aca0"}, {"index": 61861762, "value": "0xf6e70116"}, {"index": 132056166, "value": "0x427aa5f2"}, {"index": 262388043, "value": "0x128898cf"}, {"index": 91878046, "value": "0x6acfe21e"}, {"index": 117353561, "value": "0x9a0ae2e4"}, {"index": 124768597, "value": "0xc025b697"}, {"index": 71352993, "value": "0x91f0a3d0"}, {"index": 190698941, "value": "0x053041bb"}, {"index": 46055428, "value": "0xf7d767d8"}, {"index": 55281366, "value": "0xcb7b7b2b"}, {"index": 165145231, "value": "0x53597840"}, {"index": 106810753, "value": "0xdc45ee7f"}, {"index": 171985651, "value": "0x07484a2e"}, {"index": 232085256, "value": "0x635c8369"}, {"index": 159510492, "value": "0x09a65a56"}, {"index": 40072060, "value": "0xd216baee"}, {"index": 209107596, "value": "0x9cbd726c"}, {"index": 39023794, "value": "0x5e566286"}], "cache_head": ["0xebd9055c", "0x7eaf6b21", "0x9b610855", "0x134a8562", "0xb10059ba", "0x7f459e58", "0x8f3c7873", "0x3523e609", "0x75b8f4ca", "0x750d31b4", "0x0dae0782", "0x26f10015", "0x7ba87a41", "0x0efd8543", "0x691d6368", "0x8929d967"], "cache_last_line": ["0x51474edf", "0xc3cfba93", "0xf21454cf", "0x9b79baac", "0x4d4fce23", "0xd701dfd5", "0x37357ab3", "0x1be693fa", "0xa701cb3b", "0x7467c620", "0x428184e8", "0xf4010df0", "0xe33aa88f", "0xc78d6d62", "0xae9ba9c0", "0xf4bba97e"], "cache_fnv1a64": "0x448274a57f508cbc" diff --git a/proto-cuda/packs-ca2-mixer/mx8-genesis/program.h b/proto-cuda/packs-ca2-mixer/mx8-genesis/program.h index 9c99a1697..22647af89 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-genesis/program.h +++ b/proto-cuda/packs-ca2-mixer/mx8-genesis/program.h @@ -13,9 +13,9 @@ #define IGNEUM_SEED_STRING "igneum-genesis" #define IGNEUM_SEED_BYTES_HEX "69676e65756d2d67656e65736973" -#define IGNEUM_GENERATOR 2 +#define IGNEUM_GENERATOR 3 #define IGNEUM_PROGRAM_ATTEMPT 0 -#define IGNEUM_PROGRAM_ID 0x9544515847736361ull +#define IGNEUM_PROGRAM_ID 0xe323b9dcaf283a6full #define IGNEUM_DAY_STRING "2026-10-03" #define IGNEUM_DAY_BYTES_HEX "6461792f323032362d31302d3033" #define IGNEUM_DAY0 0x3067619fu @@ -28,6 +28,9 @@ #define IGNEUM_LOADS_PER_HASH 128 #define IGNEUM_WIDE_LOADS_PER_HASH 0 #define IGNEUM_OP_MIX "load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1" +// Program class v3 (Counter ASIC 2.0, docs/plans/counter-asic-2-rollout.md): generator version 3; a worker that +// runs another class refuses this pack, and a job line names the class it wants (class=v3 era=). +#define IGNEUM_PROGRAM_CLASS "v3" // Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item // derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule. #define IGNEUM_LOAD_CLASS "mx8" diff --git a/proto-cuda/packs-ca2-mixer/mx8-genesis/program.json b/proto-cuda/packs-ca2-mixer/mx8-genesis/program.json index d4e1c079a..1875e9b3c 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-genesis/program.json +++ b/proto-cuda/packs-ca2-mixer/mx8-genesis/program.json @@ -1,8 +1,8 @@ { "format": "igneum-program-pack-3", - "generator": 2, + "generator": 3, "attempt": 0, - "program_id": "0x9544515847736361", + "program_id": "0xe323b9dcaf283a6f", "program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32", "dataset_mode": "memory-hard", "seed": "igneum-genesis", @@ -15,6 +15,7 @@ "iterations": 8, "instruction_count": 64, "loads_per_hash": 128, + "program_class": "v3", "load_class": "mx8", "mixer_mult": 8, "cache_growth": true, diff --git a/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.h b/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.h index 141affeeb..caadb5e25 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.h +++ b/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.h @@ -1,5 +1,5 @@ // Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand. -// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset +// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset #pragma once #ifdef __cplusplus #include diff --git a/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.json b/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.json index 916b155f2..134f4e1a1 100644 --- a/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.json +++ b/proto-cuda/packs-ca2-mixer/mx8-genesis/vectors.json @@ -5,7 +5,7 @@ "dataset_log2_words": 28, "mask": "0x0fffffff", "lanes": 32, - "source": "igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset", + "source": "igneum-pow (Rust) CPU interpreter, generator v3, memory-hard dataset", "warps": [ {"base_nonce": 0, "expected": [ "0x19b56348bc85304d", "0xb08a9cfb44aa720f", "0xe1f8f627f780eff7", "0x2ff3e86ff1696161", "0xb65e0578c257e8ac", "0xf37b5705c2bebaae", "0xb19fef670982389e", "0x2374331b28827a11",