diff --git a/docs/analysis/class-v6/floor/denominator.md b/docs/analysis/class-v6/floor/denominator.md index 7219ab2ed..297b620aa 100644 --- a/docs/analysis/class-v6/floor/denominator.md +++ b/docs/analysis/class-v6/floor/denominator.md @@ -14,9 +14,14 @@ its source) or estimated (with its method). Nothing here moves a consensus objec per hash on class v4's shape (71.20 MH/s at 146.6 W) and about 2.10 under class v5; the RTX 5090 at its 1,300 MHz knee 2.37 (134.76 MH/s at 318.8 W, the v5lock job's +2.0 percent over class v4 applied); the RTX 4070 at its tune point 3.51 to 3.58; the RX 9070 XT at the ADLX grid's best point 7.9 to 8.1; the Apple M5 Max 1.40 to 1.43 at the - GPU-plus-DRAM meter with no lever. The 5080 beats the 5090 per joule at the knee, and the 16 GB and 12 GB Blackwell - cards (5070 Ti, 5070) read lower still by the Blackwell shape (1.7 to 2.1, estimated): **the honest NVIDIA floor is - the mass-market Blackwell card at its knee, not the 5090.** + GPU-plus-DRAM meter with no lever. The class v5 STOCK column is now measured on 14 card classes (the rented sweep, + 13:4x to 14:0x UK, every host refusing the lock): the 5080 3.48, the 4070 5.82, the 4080 4.92, the 5060 3.76, the + 5060 Ti 4.02, the 3090 5.03, the 3060 6.40, the L40S 5.29, the H100 2.58, the A100 2.99, the 4090 5.0 (lane 1), so + the lock is worth 34 to 41 percent of a Blackwell or Ada card's class v5 draw (the 5080 3.48 to 2.10, the 4070 5.82 + to 3.58) for under 2 percent of rate, and the stock column is a different card from the floor column. The 5080 + beats the 5090 per joule at the knee, and the 16 GB and 12 GB Blackwell cards (5070 Ti, 5070) read lower still by + the Blackwell shape (1.7 to 2.1, estimated): **the honest NVIDIA floor is the mass-market Blackwell card at its + knee, not the 5090.** 2. **The chip edge against the honest floor, class v5, the chip's shadow core priced in absolute terms** (3.2 pJ per forced op, the record's k = 0.5 at the 5090's knee; and 6.4 pJ, k = 1): the GDDR7 stored-dataset board reads 2.7x / 1.9x against the 5080's floor, 3.0x / 2.1x against the 5090's, 1.8x / 1.3x against the M5 Max; one HBM3 stack 3.3x / @@ -347,21 +352,26 @@ spread of the morning was that host and not the method. - The sweep's rows (section 6) land through the afternoon; a row that does not land by 19:00 stays "pending" in this file and its estimate stands. -## 9. The reading for the 20:00 BST close (five sentences) +## 9. The reading for the 15:45 BST close (five sentences) The honest joule under class v5 is 2.06 to 2.10 microjoules per hash on a 16 GB Blackwell card at its 1,100 MHz lock (measured), 2.33 to 2.37 on the 5090 at its knee (measured), about 1.7 to 2.1 on the 12 and 16 GB Blackwell cards -(estimated), 1.40 to 1.43 on an Apple M5 Max with nothing to set (measured), and the only software lever that moves it -is the operating point: the core lock on Blackwell and Ada, the cap on Ampere, the ADLX offsets on AMD, nothing on -Apple and Intel. Against those floors the stored-dataset chips read 1.9x to 2.1x on GDDR7, 2.2x to 2.4x on one HBM3 -stack and 2.7x to 3.0x on a 2 nm SRAM die at a core as good as a GPU lane, and 1.3x, 1.5x and 1.8x against the Apple -laptop; the served 2.1x stands as the 5090 figure and the honest headline is now under 2x against a mass-market card. -Five years out the honest tier is Apple's unified-memory part on LPDDR6 at about 1.2 microjoules (modelled), against -which the GDDR7 chip is at parity at k = 1 and the SRAM die 1.5x; the other LPDDR SoC vendors model 3 to 10 -microjoules because their GPUs hide the latency worse, so the reference joule is the Apple tier by name. The class -should state resistance against the best honest joule and keep sizing the shadow by the Apple tier's 5 percent point -(N at 100,000, the band drawn per era), and should not score the acceptance floor per tier; sizing N up to the Apple -ceiling would cost every honest miner 8 to 15 percent of its electricity for about 0.15x of edge. The tiers table -ships the measured points on the 5090, 5080, 4070, 9070 XT and M5 Max and an architecture prior everywhere else, with -the rule that a class flip re-measures from the stored point (the measured v4 to v5 flip moved the knee by nothing), -and the rows still owed are the Ada and Ampere knees, which no rented host can give. +(estimated from their measured stock rows), 1.40 to 1.43 on an Apple M5 Max with nothing to set (measured), and the +only software lever that moves it is the operating point: the core lock on Blackwell and Ada (worth 34 to 41 percent +of the class v5 stock draw measured today on the 5080 and the 4070), the cap on Ampere (10 to 15 percent, and a cap +under the shadow costs rate one for one: the 3080 at 170 W lost a third of its class v5 rate), the ADLX offsets on +AMD (24 percent), nothing on Apple and Intel; the occupancy knob is 1 to 2 percent and the memory clock is untouched. +Against those floors the stored-dataset chips read 1.9x to 2.1x on GDDR7, 2.2x to 2.4x on one HBM3 stack and 2.7x to +3.0x on a 2 nm SRAM die at a core as good as a GPU lane (6.4 pJ per forced op), 2.6x to 3.0x, 3.2x to 3.6x and 4.4x +to 5.0x at the record's 3.2 pJ, and 3.6x to 4.0x, 4.8x to 5.4x and 8.2x to 9.3x at the k lane's 1.1 pJ floor; against +the Apple laptop 1.3x, 1.5x and 1.8x at 6.4 pJ; the served 2.1x stands as the 5090 figure and the honest headline is +under 2x against a mass-market card at a core as good as a GPU lane. Five years out the honest tier is Apple's +unified-memory part on LPDDR6 at about 1.2 microjoules (modelled), against which the GDDR7 chip is at parity at 6.4 pJ +and the SRAM die 1.5x; the other LPDDR SoC vendors model 3 to 10 microjoules because their GPUs hide the latency +worse, so the reference joule is the Apple tier by name. The class should state resistance against the best honest +joule and keep sizing the shadow by the Apple tier's 5 percent point (N at 100,000, the band drawn per era), and +should not score the acceptance floor per tier; sizing N up to the Apple ceiling would cost every honest miner 8 to +15 percent of its electricity for about 0.15x of edge. The tiers table ships the measured points on the 5090, 5080, +4070, 9070 XT and M5 Max, the measured class v5 stock row on 14 classes and an architecture prior for the knee +everywhere else, with the rule that a class flip re-measures from the stored point (the measured v4 to v5 flip moved +the 5090's knee by nothing), and the rows still owed are the Ada and Ampere knees, which no rented host can give.