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Class v6 10.0x: lane 3's pre-read of ECO-05 at the AMD and Intel cells (a 7600 knee at or under 5.4 adds one sustainable world, 10R at 0.10, and no more; a B580 down to 7 adds none; the envelope unchanged)

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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igneum-labs 2026-10-08 18:45:48 +00:00
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docs/design/class-v6-rotating-family.md
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@ -665,7 +665,19 @@ The revenue reference R, sourced: Ethereum Classic's trailing-year miner revenue
**What the failure does and does not rest on:** not a small network (the one sustainable world is the largest), not token appreciation (the ratios are revenue-independent at zero development), not chip death (the rotation enters nowhere); it rests on the measured energy of the AMD, Intel and older NVIDIA classes on this hash and on the standard's cohort-wide new-entry median at MSRP as the test. The coexistence model's seven-condition verdict (the board coexists, the die does not once built; 10.0q to 10.0t) is the operating reading; ECO-05's envelope is the stricter new-entry reading, and the chain fails it as frozen. The boundary, stated as the question it is: the DRAM machine would pass only against a Blackwell-only cohort, which cannot be chosen after the fact; the die and the hybrid against no cohort of today's cards. **What this means for the design, in one line: the class's per-joule gap between vendors (the AMD random-read ceiling, the Intel energy) is now a measured failure of the chain's own commodity participation under the standard, ahead of any chip, and the work that moves it is the hash's energy on AMD and Intel cards (the vendor-specific kernels and operating points, the ADLX and Intel levers), not another layer against a chip.** The second explorer read of R is done (lane 3 at 80178b3b, 18:49 UK): the Ethereum Classic Blockscout explorer's own stats endpoint and block 25,497,000's record carry a miner reward of 1.6384 ETC (ECIP-1017's era 6 from block 25,000,000, about June 2026), an average block time of 12.758 s and USD 7.81, so the first page's 2.56 ETC was era 4's stale figure and its "no halving schedule" line was wrong; R corrected to USD 31.65 M a year (the implied IGN price at R USD 0.041), the frozen section kept and the correction recorded with its minute; the cube re-run at the corrected R on both efficiencies: the verdict unchanged, RUN, FAIL (the one sustainable world still 10R at 0.03, now USD 316 M a year; 0 of 54 cells per specialist pass all three lines; the boundary medians identical, being revenue-independent at zero development; the only adversarial row that moved is the die taking the whole chain with USD 75 M charged, 2.7 to 2.1). Owed before G4: the RX 7600's own knee and the B580's metered watts (the two BLOCKED core rows; now the AMD-and-Intel energy lane's, GPU-03's AMD and Intel cells, named on ECO-05's failure); the independent reviewer's adversarial rows on the package tomorrow.
**The AMD-and-Intel energy lane's first rows (19:5x UK; its file `docs/analysis/class-v6/amd-intel-energy.md` lands by 22:30 UK).** The RX 7600's rate on class v6, measured (PC 1, quiet, rate only): hl-v6-foldrw 15.79 MH/s; hl-v6-all 7.92, which is 15.84 per unit of work (that pack does two units); 1 / 2 / 4 / 5.5 GiB 15.75 / 15.46 / 15.34 / 15.35. The reference population's 13.9 MH/s was the class v4 sub-version 3 card-in rate; on class v6 with that run's 113 W (ADLX, a different class) the stock cell becomes 7.2 microjoules, the 9070 XT's 24 percent knee on it 5.4, and a flat rate at the -30 percent power floor about 5.0 (all three modelled), which is right on the results file's section 5 threshold (a 7600 knee under 5 adds sustainable worlds at 0.03 and 0.10). The metered rows (ADLX at stock, at plimit -30 and at gmax -500 with plimit -30, both class v6 packs) land by 20:45 UK; the Arc B580's watts from a Level Zero sysman sampler on PC 2 by 20:55 UK (a B580 under 8 microjoules needs under about 86 W at 10.7 MH/s). **The named cause, measured: per 32 bits of memory bus the AMD and Intel cards burn about what the 5090 burns (18 to 19 W at their knees, the 7600 28 W at stock) but do 0.22x to 0.47x its dependent random reads a second (the 5090 1.08 G/s per 32 bits, the 9070 XT 0.30, the 7600 0.45 to 0.51, the B580 0.235; memprobes and hash rates), and the hash runs at 87 to 100 percent of each card's random-read ceiling over 128; the ALU, the occupancy and the 64-register window are not the cost (the 7600's window rate cost 0 percent per unit of work).** So the lever is the AMD and Intel memory paths' random-read rate per watt, which no shadow, window or rotation parameter touches; whether a vendor kernel or operating point moves it is the lane's question tonight. Default until the metered rows land: the 7600 at 7.2 stock and 5.4 knee (modelled), the B580 at 10.4 (estimated). The ECO-08 package: eight scripts, five input files with sources and labels, the README with the run commands and the frozen criteria, the ECO-01 fixtures ALL OK on build-4; the two scripts that read coexist2.py from /tmp on the box now read it from beside themselves (this lane's one-line fix at the landing).
**The AMD-and-Intel energy lane's first rows (19:5x UK; its file `docs/analysis/class-v6/amd-intel-energy.md` lands by 22:30 UK).** The RX 7600's rate on class v6, measured (PC 1, quiet, rate only): hl-v6-foldrw 15.79 MH/s; hl-v6-all 7.92, which is 15.84 per unit of work (that pack does two units); 1 / 2 / 4 / 5.5 GiB 15.75 / 15.46 / 15.34 / 15.35. The reference population's 13.9 MH/s was the class v4 sub-version 3 card-in rate; on class v6 with that run's 113 W (ADLX, a different class) the stock cell becomes 7.2 microjoules, the 9070 XT's 24 percent knee on it 5.4, and a flat rate at the -30 percent power floor about 5.0 (all three modelled), which is right on the results file's section 5 threshold (a 7600 knee under 5 adds sustainable worlds at 0.03 and 0.10). The metered rows (ADLX at stock, at plimit -30 and at gmax -500 with plimit -30, both class v6 packs) land by 20:45 UK; the Arc B580's watts from a Level Zero sysman sampler on PC 2 by 20:55 UK (a B580 under 8 microjoules needs under about 86 W at 10.7 MH/s). **The named cause, measured: per 32 bits of memory bus the AMD and Intel cards burn about what the 5090 burns (18 to 19 W at their knees, the 7600 28 W at stock) but do 0.22x to 0.47x its dependent random reads a second (the 5090 1.08 G/s per 32 bits, the 9070 XT 0.30, the 7600 0.45 to 0.51, the B580 0.235; memprobes and hash rates), and the hash runs at 87 to 100 percent of each card's random-read ceiling over 128; the ALU, the occupancy and the 64-register window are not the cost (the 7600's window rate cost 0 percent per unit of work).** So the lever is the AMD and Intel memory paths' random-read rate per watt, which no shadow, window or rotation parameter touches; whether a vendor kernel or operating point moves it is the lane's question tonight. Default until the metered rows land: the 7600 at 7.2 stock and 5.4 knee (modelled), the B580 at 10.4 (estimated).
**Lane 3's pre-read of ECO-05 at those cells (build-4, 19:45 UK; the driver takes per-class overrides so the measured rows drop in as batch 02 without an edit), beside the lane's row:**
| The RX 7600 cell (15.79 MH/s) | The B580 cell (10.7 MH/s) | Sustainable worlds of 48 | Which | The envelope verdict |
|---|---|---|---|---|
| 7.2 (stock, class v6) | 10.4 (estimated, as frozen) | 3 | 10R at 0.03 only, 16 classes across 2 vendors | FAIL, 0 of 54 cells per specialist |
| 5.4 (the modelled knee) | 10.4 | 6 | adds 10R at 0.10 (14 to 16 classes across 2 vendors, 100 percent operating; the equilibrium 1,225 micro-USD, 29 TH/s) | FAIL, 0 of 108 |
| 5.0 (the -30 percent floor) | 10.4 | 6 | the same | FAIL |
| 5.0 | 8.0 | 6 | the same (the B580 entrant stays above the equilibrium) | FAIL |
| 5.0 | 7.0 | 6 | the same | FAIL |
So the measured 7600 knee, if it reads at or under about 5.4, adds exactly one sustainable world (10R at 0.10, USD 316 M a year at 10 cents) and no more, through the two-vendor rule; a B580 anywhere down to 7 microjoules adds none (its entrant at USD 249 for 10.7 MH/s sits over the equilibrium at every world below 10R at 0.03); and the envelope is unchanged in every case (the new world's medians the die 7.3, the hybrid 4.6, the board 3.1; the best core cells 3.9 / 2.4 / 1.63 against the 5080). The first batch's FAIL stands as recorded; batch 02 lands on the measured rows with the one added world if it comes, and the reference population's 7600 row is corrected to the class v6 rate with the measured knee, the class v4 row kept beside it labelled. The ECO-08 package: eight scripts, five input files with sources and labels, the README with the run commands and the frozen criteria, the ECO-01 fixtures ALL OK on build-4; the two scripts that read coexist2.py from /tmp on the box now read it from beside themselves (this lane's one-line fix at the landing).
#### 10.0d The rotation schedule the close adopts (the rotation lane, `docs/design/class-rotation-four-layers.md` on class-v6-rotation at bd43f808, build-3, gate green, 14:4x UK; one line per layer; both of this document's constraints held: the 180-day family epoch not shorter, W = 4 not drawn)