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Class v6 10.0i: the window core's placed row at about 20:50 (the approximate figures carried); the three-row served line both chip lanes stand behind with the 32-lane floor in

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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igneum-labs 2026-10-08 19:19:19 +00:00
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@ -473,7 +473,7 @@ Two corrections this forces on the served numbers: (1) the honest adversary's ba
**The first placed gated row (the k lane, 19:3x UK): the adversary's 32-register base core, placed and routed on ASAP7 (SPEF, a clock tree, 379,633 cells, a VCD with every pin annotated, the register file gated): about 7.0 pJ per lane-op at ASAP7 (one 300-cycle run, the program-load phase subtracted at the synthesis ratio, plus or minus 15 percent; the two-length solve within 20 minutes), 4.9 at N5, 3.5 at N3, 2.5 at N2; a model, never a lower bound. k at the lock 0.79 / 0.56 / 0.40 (N5 / N3 / N2). The GDDR7 board at the lock: 2.4x node-for-node, 2.8x a node ahead, 3.2x two ahead. So the placed gated base lands on this morning's synthesised ungated headline (6.9 pJ, k 0.56 at N3, 2.8x) to the digit: the gating and the placement cancel.** The core-only sentence for the base core is therefore "estimates a 2.8x energy-efficiency advantage (2.4x on the GPU's own node)" as a placed figure; the placed 64-register window core (the defence's chip side) is in detailed route (20:15 UK), expected at 8.5 to 10 pJ (k about 0.7 to 0.8 at N3 at the lock), which would read 2.5x a node ahead and 2.1x node-for-node, approximate until placed. The served sentence stays on the whole-machine rows of 10.0t (1.5x to 3.1x as complete machines), with this core-only row beside it marked.
**The two lanes reconciled (the k lane with the adversary lane, 19:5x UK; both rows placed and routed on ASAP7, the same node factors, DRAM term and GPU side; the joint table with the coordinator).** On the board identity the two genesis cores agree within 6 percent (the k lane's gated-flop 32-register core 2.41x same-node and 2.80x a node ahead; the adversary lane's SRAM-macro 64-register genesis core 2.28x and 2.72x); the adversary's 18-family bank costs a further 0.23x (2.05x and 2.45x); the rest of the gap to the whole machine's 1.5x is the complete-machine terms (the sustained rate at 82 percent of the activate ceiling, core leakage, PSU and VRM x1.21, cooling, the host; modelled, approximate), which the board identity does not carry: 40 percent of the gap is the core, 60 percent the machine terms. **The served line both lanes stand behind: 1.5x to 1.8x for the complete machine and 2.0x to 2.4x for the board alone, same node, both placed; a node ahead 1.8x to 2.1x and 2.45x to 2.8x.** The k lane's placed 64-register window core (the genesis families, gated flops) lands by 20:15 UK and slots between the two genesis rows on the board identity only.
**The two lanes reconciled (the k lane with the adversary lane, 19:5x UK; both rows placed and routed on ASAP7, the same node factors, DRAM term and GPU side; the joint table with the coordinator).** On the board identity the two genesis cores agree within 6 percent (the k lane's gated-flop 32-register core 2.41x same-node and 2.80x a node ahead; the adversary lane's SRAM-macro 64-register genesis core 2.28x and 2.72x); the adversary's 18-family bank costs a further 0.23x (2.05x and 2.45x); the rest of the gap to the whole machine's 1.5x is the complete-machine terms (the sustained rate at 82 percent of the activate ceiling, core leakage, PSU and VRM x1.21, cooling, the host; modelled, approximate), which the board identity does not carry: 40 percent of the gap is the core, 60 percent the machine terms. **The served line both lanes stand behind: 1.5x to 1.8x for the complete machine and 2.0x to 2.4x for the board alone, same node, both placed; a node ahead 1.8x to 2.1x and 2.45x to 2.8x.** The k lane's placed 64-register window core (the genesis families, gated flops) routed at 20:1x UK with its power report about 20:50, so the landing carries the expected 8.5 to 10 pJ per lane-op at ASAP7 (k about 0.7 to 0.8 at N3 at the lock, 2.5x a node ahead and 2.1x node-for-node) labelled approximate, the placed row the amendment with its minute; the placed base's two-length confirmation reads 6.7 pJ (2.4x same-node, 2.8x a node ahead). **The three-row served line both chip lanes stand behind, as the k lane gives it with the 32-lane floor in: 1.5x to 2.1x for the complete machine and 2.0x to 2.9x for the board alone, same node, placed, both lanes; a node ahead 1.8x to 2.4x and 2.45x to 3.2x.**
The row to serve at 18:30 UK (the k lane, 17:5x UK; the placement of the gated 64-register core slipped to about 18:30 on a floorplan timing repair, the other five placed rows by 21:00): on the gated 64-register core, synthesis-only, a model never a lower bound (the GDDR7 board at the 5090's 1,300 MHz lock, 2.33 microjoules; E_chip = 0.466 + 102,100 x e_chip; node factors claimed):