diff --git a/docs/analysis/class-v6/1p5x/x0/README.md b/docs/analysis/class-v6/1p5x/x0/README.md new file mode 100644 index 000000000..1ad421bd1 --- /dev/null +++ b/docs/analysis/class-v6/1p5x/x0/README.md @@ -0,0 +1,185 @@ +# X0: the latest model reconciled with the exact frozen software (the 1.5x programme, 9 October 2026, 10:0x UK) + +The adversary lane with the hash lane's pins (its line of 09:58 UK, every closing report staged with its sha256 at +build-1:/srv/artefacts/tas/x0-pins/.report.txt, SHA256SUMS.txt beside them; the recipe every X lane reads, +build-1:/srv/artefacts/1p5x/gpu-row-recipe.md sha cbab453c). The brief: the founder's +igneum-1p5x-experiment-brief.md (sha256 74ee073286d4a6e2…, landing under docs/plans/igneum-2.0-master/1p5x/). This +file reconciles every served and placed chip figure with the software and the measurements it rests on, names the +assumptions that differ between the served 1.9x to 2.1x hybrid line and the placed 2.4x line, and states the r0 the +programme uses with its range. Nothing here is a new measurement; no PASS is claimed. + +## 1. The frozen control, as pinned + +| Pin | Value | Read back | Label | +|---|---|---|---| +| The generator tree | class-v6 at 1a938abe4 (on branch class-v6, tip 755c2dbcf), generator 6, ProgramClass::V6, class string mx8-erad810f22d+sh256x27+state+reg64c+fold+rw, layer 8 ON, class_v6_family_flags 0xf, CLASS_V6_FLAG_NOWIN (1<<4) defined and off | the fingerprint recipe run on build-1 at 09:34 UK: 5f4d6dc6199294db89042171004e6420c1e5791e716d4b39b73d375818c10b6f, equal to the brief's | read back | +| The dataset policy | 70a6c703 (4 GiB at genesis, no later step) | F0's dataset row | pinned by F0 | +| The signing id | 2a1d6caab4c24564 at (epoch seed af89be5d, era edc4fa84, day 20730, state abb58003) | F0's freeze-candidate row | pinned by F0 | +| The research pairing (never the freeze) | hl-v6-all, id 0x4de7b836cc40a4ea (the genesis seed over node1's state) and the l8off kit's export 0x9d40978601a7df2a (era edc4fa84, day 20730, the node1 state) | the hash lane's line | pinned | + +## 2. The GPU side: every figure, its software, its boundary, its state + +Every figure is the three-card Windows rig's RTX 5090 (or 5080) alone through the runner's cards-off; power is +nvidia-smi board power.draw sampled at 1 Hz, the row's watts the sampler's mean from 8 s in to the end of the timed +dispatches, idle NOT subtracted (the microbench rows are the one exception, residency-subtracted); no wall meter +anywhere; fingerprints equal at every state. No GPU figure carries layer-8-off or a result compaction. + +| Figure (as served) | Job and report sha256 | Software by sha | Pack | State | Where it is used | +|---|---|---|---|---|---| +| The 5090 at its 1,300 MHz lock: 134.764 MH/s at 312.5 W, 2.319 microjoules per hash (served as 2.33) | run-ca3-pc1-v4-eff-5090-20261007-b (7 Oct 18:40 to 19:16Z), report ead72106… | the installed app's igneum-worker-cuda.exe d7a413c7… (0.3.20); kit igneum-ca3-v4-sub3-pc1-kit.zip 1d441f5a… (program.json a746c924…, program.h 18bca6be…, kernel.cu 80e92839…) | v4-devnet-epoch0, the Devnet 3 epoch 0 class v4 program, fingerprint e370fb2080b7dbb1; 491 batches of 2^24 | the knee | the numerator of every served chip ratio (the "served convention") | +| The class v5 control at the lock: v5-genesis 125.932 MH/s at 299.8 W against v4-genesis 125.924 at 294.0 (+2.0 percent watts) | run-ca3-pc1-v5lock-5090-20261008-b, report 0f444306… | the class v5 kit's worker | v5-genesis, v4-genesis | the knee | denominator.md's +2 percent (the 2.37 row) | +| The class v6 control on the frozen tree at the lock: hl-v6-all 70.306 MH/s at 282.0 W (4.011 microjoules); stock 70.526 at 412.0 (5.842) | run-ca3-pc1-l8off-5090-20261008 (9 Oct 02:52 to 03:00Z), report 05f00bd8… | the l8off kit igneum-ca3-l8off-kit-20261008.zip c20999d1…, CUDA worker 218ca414…; fingerprint 59e6708e46f1e87c; 250 batches | hl-v6-all 0x9d40978601a7df2a (the frozen class at the research pairing) | both | NOT yet in any served chip ratio (section 4) | +| The 5080 at its 1,100 lock: 71.201 MH/s at 146.6 W, 2.059 microjoules | run-ca3-pc1-v4-eff-5080-20261007-d (8 Oct 00:45 to 01:54Z), report 6acec71d… | the same worker d7a413c7…, the same pack | v4-devnet-epoch0, e370fb2080b7dbb1 | the knee | the 5080 column | +| The cohort rows (14 rented card classes, stock only) | the fleet lane's rows.jsonl; denominator.md sha a4ec182a… on master | per row | per row | stock | the cohort column (count-weighted about 3.6 microjoules, approximate) | +| Layer 8 off (register row 18, CLOSED 04:49 UK): hl-v6-all against hl-v6-all-nowin 0xec0c3757f8caef4a: stock 70.526 / 412.0 W against 70.209 / 417.2 (rate -0.4, joules +1.7 percent); lock 70.306 / 282.0 against 66.303 / 275.5 (rate -5.7, joules +3.6); the v5 pair the same way, +5.7 percent at the lock | the same job, report 05f00bd8…; the row document docs/analysis/class-v6/rows/pc1-l8off-ds2g-20261009.md sha fb2d5686… (master ac2f143c) | the l8off kit | the four packs | both | the D2 row: performed and closed, the layer stays ON | +| The microbench per-op rows (int_arx 11.3 pJ stock, 6.2 at the lock; the class v4 draw read as 10.3 pJ per op at the lock from the packs job's 10.8 / 6.4) | run-ca4-pc1-microbench-5090-20261008-c (8 Oct 05:15 to 05:56Z), report 62dbb138…; the 10.3 is counter-asic-4-research.md's reading (sha 82af4424…) | igneum-worker-cuda-ca4mb.exe 49aa60c4… | 20 probes x 60 s at full residency | both | the denominator of every per-family k | + +A caveat the hash lane names: since 14:2x UK on 8 October the rig's 5090 reads about 13 percent under the morning +(the enclosure swap), so pairs inside a job are the figures and a job's absolutes are not compared with 7 October's. +The served 2.33 microjoules is a 7 October absolute; the frozen-tree control is a 9 October job. Section 4 carries +what that does to r0. + +## 3. The chip side: every figure, its software, its boundary, its node + +| Figure | Software by sha | What it is | Boundary | Node scaling | +|---|---|---|---|---| +| The placed 8-lane 18-family core: 9.36 pJ per lane-op on the class v4 draw at ASAP7 (8.6 to 11.1), 6.55 at N5, 4.72 at N3 | class-v6-adversary 43c9f7cd8: tools/chip-model/mf (RTL core_mf.v, the flow, results/table.csv), docs/analysis/class-v6/multi-family-adversary.md (landed e3d0208d) | ORFS on ASAP7 (Yosys 0.68, OpenROAD, the orfs docker image), placed and routed with SPEF, OpenSTA power under a gate-level VCD of a random-input simulation; the register window a FakeRAM2.0 64x256 macro per 8 lanes whose dynamic energy is MODELLED (3.5 pJ per access, 2.0 to 7.0) | the core only: no memory controller, no PHY, no host; the machine terms are board.py's (section 5) | ASAP7 to N5 x0.70, to N3 x0.50 (TSMC's claimed per-node reductions at the same speed) | +| The placed 32-lane 18-family core: 9.54 pJ (8.9 to 11.0), 6.68 at N5 | the same; parasitics from the global route, calibrated within 1 percent of SPEF on the 32-lane genesis core; the detailed route did not converge (the fault, multi-family-adversary.md section 14) | | | the same | +| The program the chip rows execute | the testbench's draw with the class v4 WEIGHTS (add 12, xor 10, mul 8, mad 8, shfl 8, rotl 7, sub 6, mulhi 6, rotr 6, or 4), NOT the frozen tree's drawn program: the chip rows are per-op energies by family under the draw's weights; the frozen program's op counts (102,100 shadow ops, 512 base, 128 loads, W = 1) set the per-hash sum | | | | +| The memory system | chip-model-v3.md 5.3 and 5.5 (the GDDR7 board: 2.0 nJ per random read, 1.5 to 2.6; 21.3 G activates per second, the 5090's 82 percent as the sustained fraction; 20 W static, 15 W controller; USD 320 of devices), the N2 SRAM die (floor lane 3, 0.25 nJ per read at W = 1) | modelled on claimed device figures | the devices, controller and PHY | the memory does not scale with the core's node | +| The hybrid's hit rate | adv-cache-2's window-layer distribution on Devnet 3's programs (the hottest half of the items serves 0.7188 of reads: the p98 program), the hash lane's census reconcile (the mean over programs 0.581, coexistence-model.md line 537), census-packs.md's flat-control ratio 1.1 to 1.7x (sha 146b578c…) | measured on programs of the class v5 and v6 crates, the window model as the null | | | +| The complete machine | tools/chip-model/mf/flow/board.py: PSU 92 percent, VRM 90 percent, cooling 3 percent, one full node per 100 machines (85 W, USD 1,500), board and assembly USD 200, the core die sized to the memory's sustained rate | approximate allowances | the wall of the machine, less the host's share | | + +## 4. The reconciliation, line by line + +### 4.1 The served 1.9x to 2.1x hybrid against the placed 2.4x hybrid + +Both are the stored-half hybrid (1 GiB of SRAM beside the 16 GDDR7 devices) against the 5090 at its lock, same +node. They differ in four assumptions, each named: + +| Assumption | The served line (10.0r, "about 2.4x") | This lane's placed line (1.9x to 2.1x) | Which the programme uses | +|---|---|---|---| +| The hit rate of the hottest half | 0.72 (adv-cache-2's p98 program) | 0.581 (the hash lane's reconciled mean over programs) for the 1.93x; 0.72 for the 2.09x | the mean, 0.581: the p98 is the tail, carried beside it | +| The core's energy | the synthesised 8-lane core (4.61 pJ at N5) scaled by the first placed genesis core's factor | the placed 8-lane 18-family core itself, 6.55 pJ at N5 | the placed row | +| The machine terms | the board identity (2.33 over 0.466 + the shadow) with the hybrid's memory term, no power train | the complete machine: PSU, VRM, cooling, the host share, the sustained derate | the complete machine (the review's evidence standard) | +| The node | N5 node-for-node | N5 node-for-node | the same | + +So the 2.4x is the synthesised core at the tail hit rate on the board identity, and the 1.9x to 2.1x is the placed +core at the mean and the tail on the complete machine; the two agree once the three assumptions are aligned +(section 13 of multi-family-adversary.md: 1.93x at 0.581 placed, 2.09x at 0.72 placed; 2.69x at 0.72 synthesised +on the board identity, the 10.0q figure). The programme's hybrid r0 is the placed, complete-machine, mean-hit +figure. + +### 4.2 The window-conditioned 72 percent against the flat control, as the brief states it + +The brief reads: the hottest half serves 72 percent because the window model concentrates traffic, and a flat +distribution would give 50 percent. The record's reading (census-packs.md section 3): the 72 percent is the p98 +program on the window-conditioned null, the mean over programs is 0.581, and a flat control sits at 1.1 to 1.7x of +the window model's top-0.1-percent share (printed beside the census, not used). The layer-8-off experiment is +PERFORMED and CLOSED (register row 18): with the windows removed the hit of the hottest half is exactly 0.50 at +every program (multi-family-adversary.md section 13 (5)), and the honest side at the knee loses 5.7 percent of rate +and 3.6 to 5.7 percent of joules, so the layer stays ON. The chip-side arithmetic of the brief's conditional cache +calculation holds (misses 0.50 against 0.419 at the mean, +19 percent of DRAM reads; against 0.28 at the tail, +79 +percent) and the placed rows say what it buys: the hybrid at hit 0.50 reads 1.85x against 1.93x at the mean and +2.09x at the tail, 4 percent at the mean, 11 at the tail; the honest side pays more than that at the knee. X1 is the +new-consensus-version form of the same question (a class v7 shape without the fixed windows, everything else +frozen) and its traces replace this arithmetic on the hybrid rows when they land. + +### 4.3 Layer-8-off and compaction in any figure + +Layer 8 off is in NO served or placed figure (every GPU row and every chip row above carries the windows ON; the +hit-0.50 row is a labelled variant). Result compaction (X2) is in NO figure on either side. + +### 4.4 The wall-power boundary, both sides + +The GPU side's boundary is the card's board power (nvidia-smi, 1 Hz, idle not subtracted), the card alone through +cards-off: it excludes the host, the PSU's loss and the fans' share beyond the card's own. The chip side's boundary +is the complete machine (the core, the memory, the controller and PHY, PSU and VRM losses, cooling, the host's +share). The two are not the same boundary: the GPU's host, PSU loss and case fans are NOT in its 2.33, while the +chip carries about 21 percent of power-train loss, 3 percent of cooling and 0.85 W of host. The reconciliation the +programme should carry: either add the GPU's own machine terms (a mining rig's PSU at 92 percent and its host share, +about +10 percent on the card's figure, approximate) or read the chip at the board identity; the first is the honest +one and moves every served ratio up by about 0.1x. It is NOT applied in this file's r0 (the served convention is +kept so every row stays comparable); it is the first of the three assumptions below. + +### 4.5 The node scaling applied + +Every chip row is stated at ASAP7 and scaled by claimed factors: N5 (the 5090's class, "same node") x0.70, N3 ("a +node ahead") x0.50, N2 x0.36. The served sentence's "2.0x on the GPU's own node" is the N5 column; "2.2x to 2.4x" +the N3. The memory terms do not scale. The GPU side is measured at its own node and never scaled. + +## 5. The r0 the programme uses + +| Opponent (complete machine, placed core, same node N5) | r0 | Range | Source rows | +|---|---|---|---| +| The pure DRAM board | 1.5x | 1.3x to 1.7x (the SRAM access band and the memory band) | multi-family-adversary.md section 6 at the placed energy; the 32-lane core the same | +| The stored-half hybrid at the mean hit 0.581 | 1.93x | 1.65x to 2.12x | section 13 (placed) | +| The stored-half hybrid at the tail hit 0.72 (the 10.0q case) | 2.09x | 1.78x to 2.29x | section 13 (placed) | +| The N2 SRAM die | 2.3x | 2.0x to 2.7x | section 6 at the placed energy | + +**The reconciled r0 the programme uses is the worst credible opponent's: the pure DRAM board at 1.5x (1.3x to +1.7x) same-node; the hybrid at 1.93x (1.65x to 2.12x) is the X5 sweep's starting row and X1's target.** The +yardstick from 1.5x to 1.5x is nothing; from the hybrid's 1.93x, a 22 percent GPU cut or a 29 percent specialist +rise. A node ahead: the board 1.8x (1.5x to 2.0x), the hybrid 2.4x (2.05x to 2.63x). + +The three assumptions most likely to move r0: +1. The boundary mismatch (4.4): putting the GPU's own PSU loss and host share into its figure moves every ratio up + about 0.1x (the board to about 1.6x, the hybrid to about 2.1x), approximate. +2. The frozen-tree control against the class v4 numerator: the served 2.33 is class v4 on a 7 October job; the + frozen class v6 object reads 4.011 microjoules at the lock on the l8off kit's export at the research pairing (a + 9 October job on a card reading 13 percent low). The chip's shadow at class v6's op count is the same core on + 102,612 ops; if the honest card's class v6 energy per hash is 4.0 against the chip's 1.53, the board ratio reads + 2.6x and the hybrid 3.3x, which is the number the programme must reconcile first: either the class v6 object + costs the 5090 1.7x what class v4 did (then the chip's shadow op count for class v6 must be re-read from the + frozen program, not from class v4's 102,100) or the l8off job's absolute is the enclosure-swap artefact. The + hash lane's paired control (class v4 and class v6 in one session on one card, same kit) decides it; until it + lands r0 stays on the class v4 pair. +3. The SRAM macro's access energy (the one modelled chip term; 2.0 to 7.0 pJ per access gives the band's width) and + the hybrid's hit rate (0.50 with the windows off, 0.581 mean, 0.72 tail). + +## 5a. The decider in (the hash lane, 09:59 UK): assumption 2 is real, and what it does to r0 + +One session on a rented RTX 5090 (Vast 54992886, driver 580.105.08, the gen-6 Linux CUDA worker sha 804a6f7f…, 250 batches of +2^24 per pack, board power at 1 Hz, mean from 8 s in, idle not subtracted, stock only; evidence +build-1:/srv/artefacts/tas/x0-pins/x0-run-fk-5090c/, run-x0.log sha 9bc40685…, smi.csv 7ab9f16f…): class v4 v4-devnet-epoch0 +(0xa785001687d8688a, fingerprint e370fb2080b7dbb1) 141.963 MH/s at 500.0 W = 3,522 nJ per hash; the frozen class v6 hl-v6-all +(0x9d40978601a7df2a, 59e6708e46f1e87c) 70.900 at 445.1 W = 6,278 nJ; the signing object hl-v6-all-cs (0x2a1d6caab4c24564, +01f51b9d4805e5e6) 70.650 at 457.1 W = 6,470 nJ. Class v6 over class v4: 1.78x and 1.84x in joules per hash, 2.00x in rate; the +house 5090's own pair 1.68x at stock and 1.73x at the 1,300 MHz knee (2,319 against 4,011 nJ). So the served numerator (2.33 +microjoules, class v4) understates the frozen object's card cost by about 1.7x, and the only class v6 lock row is 4.01 +microjoules per hash on the house 5090. + +What it does to r0: the chip must be paired with the card on the same program. X4's read of the exported texts (10:0x UK) +gives the frozen object 256 loads per hash against class v4's 128, so the card's doubled cost per hash is doubled work, and +the chip's memory term doubles with it while its shadow (carried at class v4's 102,612 ALU ops until the hash lane's count lands) +does not. On the consistent class v6 pair (the card 4.011 microjoules at the knee, the chip at 256 loads) every ratio moves UP, +not down: X5's sweep (section 2, pair B) reads the DRAM board 1.85x (1.5x to 2.1x), the stored-half hybrid 2.53x, the N2 die 4.0x +(3.4x to 4.4x) same-node. The earlier worry (a 1.7x structural card cost the chip does not share) is not what the data say: the +cost is loads, which the chip pays too. The programme's r0 is therefore pair B's, with pair A (the served class v4 convention: +the board 1.5x, the hybrid 1.93x, the die 2.44x) kept as the served convention's row until the ALU count lands: + +| Opponent, same node | r0, pair A (class v4: the card 2.319, 128 loads) | r0, pair B (the frozen object: the card 4.011, 256 loads, the shadow at class v4's count) | Source | +|---|---|---|---| +| The pure DRAM board | 1.5x (1.3 to 1.7) | 1.85x (1.5 to 2.1) | X5's sweep on the placed core | +| The stored-half hybrid, mean hit | 1.93x (1.65 to 2.12) | 2.53x | the same | +| The N2 SRAM die (the worst credible design) | 2.44x (2.05 to 2.66) | 4.0x (3.4 to 4.4) | the same | + +If the frozen object's shadow is larger than class v4's, pair B's chip energies rise and its ratios fall back toward pair A's; +the ALU count by family is the one input owed. + +## 6. BLOCKED rows + +| Row | Why | Owner | +|---|---|---| +| The class v6 paired control at the lock (the rented pod refuses the clock lock; the stock pair is in, section 5a) | stock done 09:59 UK; the knee pair is the house 5090's 1.73x | the hash lane | +| The frozen program's op count per hash by family (decides whether the chip's shadow scales with the card's class v6 cost) | asked 10:02 UK, default 10:30; a first read from X4 (10:0x UK, the exported texts): the class v6 object executes 256 loads per hash against class v4's 128, so the card's 2x rate cost is work, the default reading; the ALU count still owed | the hash lane | +| The chip's op count on the frozen program (the shadow's 55,296 writes in r0..r7, the base program's 512, the loads' 128 at W = 1: read from 1a938abe4's generator, not from class v4) | the chip rows use the class v4 draw's weights; the frozen program's per-family counts are owed | this lane, with the hash lane | +| The GPU's own machine terms (PSU, host) | not measured; approximate +10 percent | the hash lane (a wall meter on the rig) | + +## 7. Sources + +The hash lane's pin line (09:58 UK) and build-1:/srv/artefacts/tas/x0-pins/; the gpu-row-recipe.md (sha cbab453c…); +docs/analysis/class-v6/multi-family-adversary.md (master e3d0208d); docs/analysis/class-v6/coexistence-model.md (line +537); docs/analysis/class-v6/census-packs.md (sha 146b578c…); docs/design/class-v6-rotating-family.md 10.0h, 10.0i, +10.0q, 10.0r (sha 6eaf43bd…); docs/analysis/counter-asic-4-research.md 15.1a and 20.3 (sha 82af4424…); +docs/analysis/class-v6/floor/denominator.md (sha a4ec182a…); the register rows 18 and 105 to 126. diff --git a/docs/analysis/class-v6/1p5x/x5/README.md b/docs/analysis/class-v6/1p5x/x5/README.md new file mode 100644 index 000000000..31198fb57 --- /dev/null +++ b/docs/analysis/class-v6/1p5x/x5/README.md @@ -0,0 +1,151 @@ +# X5: the co-optimised full opponent sweep (the 1.5x programme, 9 October 2026; first rows 09:4x UK on the frozen control) + +The adversary lane with the floor lanes under it. The sweep: the pure DRAM board, the hybrid at stored fractions 0.25, +0.5 and 0.75, the full SRAM store and recomputation, each as a complete machine (the memory devices, controller and +PHY, the core die sized to the memory's sustained rate, PSU and VRM losses, cooling, the host's share) at the +calibrated node, with its power, area and throughput; the worst credible design retained as the specialist side a. +The tool: `tools/1p5x/x5/sweep.py` (run on build-4 under the lease pool with a pid file; seconds). Every row is a +MODEL on the placed core's measured energies and the record's claimed memory figures; no chip is measured; the +vocabulary is NOT RUN / BLOCKED / FAIL / PASS and this lane never writes PASS. The registry batch for these rows reads +NOT RUN (`tools/ci/batches/adversary-20261009-x5.json`) until X6 runs the model blind. + +## 1. Sources by sha + +- The core: the placed 8-lane 18-family core, 6.55 pJ per lane-op at N5 on the class v4 draw (6.02 to 7.78), class-v6-adversary + f5a82bf6a `tools/chip-model/mf/results/table.csv` (ASAP7 placed with SPEF, gate-level VCD, the SRAM window a FakeRAM 64x256 macro per 8 + lanes with its access energy modelled at 3.5 pJ, 2.0 to 7.0); the node scaling N5 = ASAP7 x0.70, N3 = N5 x0.72 (claimed). +- The frozen control's counts: 102,100 shadow ops, 512 base, 128 loads at W = 1 (X0 section 3; the frozen program's own per-family + counts BLOCKED, X0 section 6). +- The honest card: the 5090 at its 1,300 lock, 2.319 microjoules per hash (X0 section 2, job run-ca3-pc1-v4-eff-5090-20261007-b). +- The memory: chip-model-v3.md 5.3 and 5.5 (GDDR7: 2.0 nJ per random read, 1.5 to 2.6; 21.3 G activates per second, 82 percent + sustained, the high case at the 5090's measured 17.5 G; 20 W static, 15 W controller; USD 320 of devices); the SRAM read at W = 1 + 0.25 nJ (0.20 to 0.35), floor lane 3 2.1; SRAM USD 250 per GiB and 15 W per GiB static (claimed, approximate); the N2 die USD 500. +- The hit rates (the window layer ON, the frozen control): the hottest half serves 0.581 of reads on the mean program (the hash lane's + reconcile, coexistence-model.md line 537), the quarter 0.341 and the three quarters 0.720 scaled from adv-cache-2's distribution by the + same ratio (approximate); the p98 program's 0.7188 is the tail. X1's traces replace these on the hybrid rows when they land. +- The machine terms: `tools/chip-model/mf/flow/board.py` (PSU 92 percent, VRM 90, cooling 3, one node per 100 machines). + +## 2. The rows on the frozen control: two consistent pairs (the first run 09:43 UK; the class v6 pair 10:1x UK, build-4) + +The chip side must be paired with the card side on the SAME program. Two consistent pairs exist today: (A) the class v4 pair, the +served convention (the card 2.319 microjoules per hash at the lock, the program 128 loads and 102,612 ALU ops: X0 section 2); +(B) the class v6 pair, the frozen object (the card 4.011 microjoules at the lock, the house 5090's only class v6 lock row, X0 5a; +the program 256 loads per hash, X4's read of the exported texts, with the ALU count carried at 102,612 until the hash lane's +line). Pair A is the first table (09:43 UK, 128 loads); pair B the second. The yardstick's r0 is pair B's, the frozen object's. + +Pair A (class v4, 128 loads, the card 2.319), same node (N5), the card over the machine; the band is the SRAM access band and +the memory band together; "credible" is a capital per MH/s under ten times the card's USD 15.9: + +| Variant | Sustained MH/s | Machine W | microjoules per hash (band) | Core lanes | Core mm^2 (N5) | Capex USD | USD per MH/s | Ratio (band) | Credible | Retained | +|---|---|---|---|---|---|---|---|---|---|---| +| The pure DRAM board (16 GDDR7 devices) | 136 | 209 | 1.528 (1.380 to 1.851) | 104,960 | 210 | 661 | 4.84 | 1.52x (1.25 to 1.68) | yes | | +| The hybrid, the hottest 25 percent in 0.5 GiB of SRAM (hit 0.341) | 207 | 283 | 1.367 (1.244 to 1.649) | 159,272 | 319 | 825 | 3.98 | 1.70x (1.41 to 1.86) | yes | | +| The hybrid, the hottest 50 percent in 1.0 GiB (hit 0.581) | 326 | 402 | 1.235 (1.128 to 1.483) | 250,502 | 501 | 1,015 | 3.12 | 1.88x (1.56 to 2.06) | yes | | +| The hybrid, the hottest 75 percent in 1.5 GiB (hit 0.720) | 487 | 561 | 1.151 (1.054 to 1.378) | 374,859 | 750 | 1,230 | 2.52 | 2.02x (1.68 to 2.20) | yes | | +| The full SRAM store (one N2 reticle, 2 GiB at W = 1) at a 1 kW budget | 1,419 | 1,350 | 0.951 (0.872 to 1.129) | 1,091,866 | 2,184 | 1,701 | 1.20 | 2.44x (2.05 to 2.66) | yes | the worst credible design on pair A | +| Recomputation: the hottest half in SRAM, the other 42 percent derived on the core, no DRAM | 251 | 1,359 | 5.411 (4.988 to 6.379) | 1,138,480 | 2,277 | 1,285 | 5.11 | 0.43x (0.36 to 0.46) | yes | loses at every point | + +Pair B (the frozen class v6 object, 256 loads, the card 4.011 at the knee), same node: + +| Variant | Sustained MH/s | Machine W | microjoules per hash (band) | Core lanes | Core mm^2 | Capex USD | USD per MH/s | Ratio, the card over the machine (band) | Credible (USD per MH/s under 10x the card) | Retained | +|---|---|---|---|---|---|---|---|---|---|---| +| the pure DRAM board (16 GDDR7 devices, 64 channels, 32 GB) | 68 | 148 | 2.172 (1.944 to 2.661) | 52,480 | 105 | 623 | 9.13 | 1.85x (1.51 to 2.06) | yes | | +| the hybrid, the hottest 25 percent of items in 0.5 GiB of SRAM beside the DRAM (hit 0.341); SRAM USD 125 claimed | 104 | 192 | 1.850 (1.671 to 2.257) | 79,636 | 159 | 767 | 7.41 | 2.17x (1.78 to 2.40) | yes | | +| the hybrid, the hottest 50 percent of items in 1.0 GiB of SRAM beside the DRAM (hit 0.581); SRAM USD 250 claimed | 163 | 258 | 1.585 (1.440 to 1.924) | 125,251 | 251 | 925 | 5.68 | 2.53x (2.08 to 2.79) | yes | | +| the hybrid, the hottest 75 percent of items in 1.5 GiB of SRAM beside the DRAM (hit 0.720); SRAM USD 375 claimed | 244 | 345 | 1.417 (1.292 to 1.715) | 187,429 | 375 | 1,095 | 4.49 | 2.83x (2.34 to 3.10) | yes | | +| the full SRAM store (one N2 reticle, 2 GiB at W = 1) at a 1 kW budget; the die USD 500 claimed; the reconciled ticket USD 1.0 per MH/s (0.5 to 1.6) | 1358 | 1347 | 0.992 (0.905 to 1.187) | 1,044,425 | 2089 | 1,667 | 1.23 | 4.04x (3.38 to 4.43) | yes | WORST CREDIBLE: a | +| recomputation: the hottest half in SRAM, the other 42% of items derived on the core (1,003,991 extra ops per hash), no DRAM; the core-bound rate at a 1 kW budget | 137 | 1359 | 9.907 (9.132 to 11.681) | 1,137,987 | 2276 | 1,284 | 9.36 | 0.40x (0.34 to 0.44) | yes | | + +The retained specialist side: the full SRAM store (one N2 reticle, 2 GiB at W = 1) at a 1 kW budget at 0.992 microjoules per hash (0.905 to 1.187); its ratio from the card's 4.011: 4.04x (3.38 to 4.43). + +A node ahead (N3) on pair B: 2.07x (1.68 to 2.32); 2.48x (2.03 to 2.75); 2.97x (2.44 to 3.27); 3.39x (2.79 to 3.72); 5.34x (4.46 to 5.87); 0.55x (0.47 to 0.60). + +Reading. (1) On the frozen object the card pays 1.73x class v4's joules for twice the loads, and the chip pays 1.42x (the DRAM +board: 2.172 against 1.528 microjoules; its memory term doubles, its shadow does not), so every ratio moves UP on pair B: the +board 1.85x, the hybrids 2.17x to 2.83x, the die 4.0x same-node. The worst credible design is the die on both pairs; the +programme's a is the die's energy per hash on pair B, 0.992 microjoules (0.905 to 1.187), and the ratio to bring to 1.5 is 4.0x +same-node (5.6x a node ahead). The ALU count on the frozen object is the one input still owed (the hash lane, X0 section 6): if the +class v6 shadow is larger than class v4's the chip's energy on pair B rises and every pair-B ratio falls back toward pair A's. +(2) Recomputation loses at every point and is never credible as a design; the hybrids' ratio rises with the stored fraction and +their capital per MH/s falls. (3) The core's lanes are a tenth or less of every machine's capital except the die's, where the core +is 3x the memory's silicon: the die's a depends on the core's density, which no single-port interleaving raises (the port bounds +the throughput at four accesses per op; a second macro copy doubles it for one extra write per op, about +0.4 pJ, and halves the +lanes: the die's capital USD 1.2 to about 0.8 per MH/s, its a within 2 percent); the per-box placements (section 4) bracket the +placement factor instead. (4) The D2(b) rows of multi-family-adversary.md section 13 (1.93x at the half) sit between this file's +pair A (1.88x, 15 W per GiB of SRAM static against 7.5) and are the same model. + +## 3. a, and the ratio from r0 with X1's g + +The programme's a is the worst credible design's energy per accepted hash on the frozen object (pair B): the N2 SRAM die at 0.992 +microjoules (0.905 to 1.187), so r0 for the die is 4.0x same-node (3.4x to 4.4x) and 5.6x a node ahead; the DRAM board 1.85x (1.5x +to 2.1x). r_new = r0 x g / a: from the die's 4.0x the honest card must cut its energy per hash by 63 percent at a = 1 for 1.5x, and +no 15 plus 20 split reaches it (4.0 x 0.85 / 1.20 = 2.8x); from the board's 1.85x, 19 percent at a = 1 or 15 plus 20 to 1.31x. The +X1 candidate's g (the card's class v7 energy over its class v6 energy, same card, same session) and its traces re-run the hybrid +rows and move nothing on the die (the die serves every read whatever the distribution). BLOCKED until X1 lands: g; the hybrid rows +on the traces. BLOCKED on the hash lane: the frozen object's ALU count (pair B's chip energies carry class v4's 102,612). + +## 4. The co-optimised core (the per-variant hosts; PENDING with clocks) + +The 5-phase single-port slot buys the adversary energy (one macro access serves eight lanes; the units isolated) and pays in lanes: +105,000 lanes for the board, 1.1 million for the die. The co-optimised form interleaves four hash contexts per lane group on one +FakeRAM 256x256 macro (4 contexts x 64 registers x 8 lanes), so a lane group issues four ops per five cycles instead of one: the same +accesses per op, a 256-deep macro (its access about 4.5 pJ, 2.5 to 9.0, approximate), a quarter of the lanes and about a third of the +core's silicon and leakage. It changes the die's capital (USD 1.20 to about 0.6 per MH/s) and its leakage (the core's 55 W at 1.1 M +lanes to about 15), and so the die's a by a few percent; it changes the board's row under 1 percent. The RTL variant (`core_mf` with a +context index on the macro address and the phase counter) synthesises and places on the build boxes the coordinator assigns per +variant (the founder's order of 10:2x UK: build-2, 3, 5, 6, 7 and 8, one design each; no rented host); the converged SPEF row of the 32-lane core at 22 percent utilisation runs on build-4 (pid file +build-1:/srv/queue/pids/build-4-floorplan.pid, started 09:35 UK, about 13:30). Rows by 12:30 where the hosts land them; else PENDING +with the morning's clock. + +## 5. How X6 evaluates a (pack, seed) pair blind + +`python3 tools/1p5x/x5/sweep.py --rows tools/chip-model/mf/results/table.csv --node N5 --trace --json ` on any +box with python3, under a pid file. The trace JSON: `{"ops_per_hash": N, "loads_per_hash": L, "hit": {"0.25": h, "0.5": h, "0.75": +h}}`, the pair's own op count, load count and the fraction of its reads served by the hottest quarter, half and three quarters of +its items (the attack-f8 item histogram over the pair's nonces; X6 draws them). The retained design and its energy per accepted work +are the row marked retained; `--node N3` for a node ahead; `--gpu-uj` the card's energy for the same pair. The P03 cost lines (the +GPU-side cost of the candidate against the control) are the hash lane's measured rows, never this tool's. + +## 6. BLOCKED and NOT RUN + +| Row | State | Why | +|---|---|---| +| The hybrid rows on X1's traces | BLOCKED | X1's traces (11:30 UK) | +| g for r_new | BLOCKED | X1's paired card rows | +| The numerator on the frozen class v6 object | BLOCKED | the hash lane's paired class v4 against class v6 control (X0 assumption 2) | +| The co-optimised core's placed rows | PENDING | the assigned build boxes; by 12:30 or the morning's clock | +| The converged SPEF row (32-lane, 22 percent) | PENDING | build-4, about 13:30 | +| Every row of this file in the registry | NOT RUN | X6's blind run | + +## 7. B5 (the research plan's Track B item, the coordinator's ask of 10:0x UK): the full-SRAM design on fresh state and the near-memory design, as WITNESS rows + +The unit is Track B's proof-carrying, input-specific memory-work unit (an MTP / DRSample labelling of N labels of 32 bytes per +instance, the state built fresh per instance, in-degree 2, the proof search small beside the construction); the unit is PROVISIONAL +until the B2 lane defines the lottery-contribution and security-budget comparison, and NO ratio is written (no GPU side exists for +the unit until B3); the design goal for Track B is 1.25x with the guardband of the plan's section 3.6 (1.25 x 1.05 / 0.90 = 1.46) +beside the programme's 1.5x yardstick. Every row is a WITNESS (E_D), a modelled design the specialist could build, never a BOUND +(L), which is the B4 theory lane's. The tool: `tools/1p5x/x5/b5.py` (build-4, seconds; the label hash taken at 1,000 ALU ops on +the placed core, a provisional Blake2-class count the B1 reference replaces; the SRAM write 0.30 nJ per label, 0.25 to 0.45, the +read 0.25, 0.20 to 0.35, the N2 die's wire figures; the PIM in-bank access 0.35 nJ, 0.25 to 0.5, approximate from the HBM2 +breakdown's data-movement share; one hash unit per pseudo-channel, 32 per stack, the chain sequential per instance). + +| Design (WITNESS E_D) | State per instance | Labels N | Core energy per instance (microjoules) | Memory energy per instance | Energy per instance, device (band) | Instances per second per machine | Chains in flight | SRAM held (GiB) | Core lanes | Core mm^2 | Machine W | Energy per instance, whole machine | Capex USD | USD per (instance per second) | +|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| +| fresh-state full SRAM | 32 MiB | 1,048,576 | 6,868 | 576.7 | 7,445 (6,791 to 9,012) | 134,320.33 | 1,055,810 | 32,994.1 | 1,055,810 | 2,112 | 616,960 | 4,593,197 | 8,249,477 | 61 | +| near-memory (PIM) on one HBM3 stack | 32 MiB | 1,048,576 | 6,868 | 734.0 | 7,602 (6,843 to 9,222) | 4.07 | 32 | 0.0 | 256 | 1 | 5 | 1,235,621 | 550 | 135 | +| fresh-state full SRAM | 128 MiB | 4,194,304 | 27,473 | 2,306.9 | 29,780 (27,162 to 36,048) | 33,580.08 | 1,055,810 | 131,976.3 | 1,055,810 | 2,112 | 2,463,910 | 73,374,159 | 32,995,027 | 983 | +| near-memory (PIM) on one HBM3 stack | 128 MiB | 4,194,304 | 27,473 | 2,936.0 | 30,409 (27,372 to 36,887) | 1.02 | 32 | 0.0 | 256 | 1 | 5 | 4,942,483 | 550 | 541 | +| fresh-state full SRAM | 512 MiB | 16,777,216 | 109,891 | 9,227.5 | 119,118 (108,649 to 144,192) | 8,395.02 | 1,055,810 | 527,905.1 | 1,055,810 | 2,112 | 9,851,712 | 1,173,518,537 | 131,977,226 | 15,721 | +| near-memory (PIM) on one HBM3 stack | 512 MiB | 16,777,216 | 109,891 | 11,744.1 | 121,635 (109,488 to 147,547) | 0.25 | 32 | 0.0 | 256 | 1 | 5 | 19,769,931 | 550 | 2,162 | + +Reading. (1) On fresh state the full-SRAM design's cost per instance is the construction's core energy (N hashes at 1,000 ops: 6.9 +joules per 512 MiB instance, 0.43 per 32 MiB), with the SRAM's write and read energy under a percent of it, so the design does +not escape the labelling's cost by holding the state in SRAM: what the SRAM buys it is the sequential chain's speed (a label every +7.5 microseconds on one lane group) and the instances it can hold in flight, and what it pays is the SRAM held (the chains in flight +times the state, 2.4 to 38 GiB for the 32 to 512 MiB instances at 1 kW: the capital column). (2) The near-memory design is bound by +the chain: one instance per hash unit, 32 units per stack, so a 512 MiB instance's stack runs 32 chains and finishes one instance +every 250 ms per unit; its energy per instance is the same core energy (the hash is the cost, not the access) with the in-bank +access a third of the across-interface figure, which changes the device energy under a percent. (3) So for this unit the memory +technology is not where the specialist's energy goes; the hash's per-op energy on the core is, which puts the Track B question +where the plan's B4 puts it: the energy of accepted proofs under partial evaluation, shortcuts and amortisation, a bound, not a +witness. These rows stay the witness the B4 bound must beat. diff --git a/docs/analysis/class-v6/multi-family-adversary.md b/docs/analysis/class-v6/multi-family-adversary.md index f73c81dfc..7ccb061d7 100644 --- a/docs/analysis/class-v6/multi-family-adversary.md +++ b/docs/analysis/class-v6/multi-family-adversary.md @@ -922,4 +922,11 @@ per hash for the whole-window coupling, 1.2 percent of its shadow energy, and th from 1.5x to 1.49x same-node (not to 1.42x, which was the literal fold's cost); the card meanwhile keeps the fold at 6.20 nJ per hash on the 5090 and would pay 7.13 on the prefix form. The two shapes together: the chip's cost of the coupling is 8 nJ (connected-state shape, prefix form) to 56 nJ (shipped shape, literal form), 0.02x to 0.08x -of the bracket, and no design in the record charges the chip a 63-read cost it can avoid. +of the bracket, and no design in the record charges the chip a 63-read cost it can avoid. (6) X4's corrections (10:0x UK, +9 October; tools/1p5x/x4/chip_rows.py on 1p5x-x4, read from the exported class v6 texts): the class executes 256 loads +per hash (32 per iteration x 8), not 128, so the literal fold on the shipped shape is 16,128 ops and reads, 113 nJ at +the slot pricing (23 nJ at the datapath pricing); and the running total gives S but not the prefix P_s the identity +needs at every load, so the cheapest byte-identical form keeps 8 group sums (groups 1..7 moved on the base program's +writes to r8..r63, group 0 recomputed at each load: 7,560 ops, 2,784 extra reads, 36,864 flop bits, +32 B of state per +lane), 10 to 52 nJ per hash (the datapath to the slot pricing), which replaces the 7 nJ (5 to 10) row above; the +bracket moves 0.01x to 0.08x either way. diff --git a/docs/plans/igneum-2.0-test-registry.json b/docs/plans/igneum-2.0-test-registry.json index 84d809bcb..bb8775155 100644 --- a/docs/plans/igneum-2.0-test-registry.json +++ b/docs/plans/igneum-2.0-test-registry.json @@ -2520,21 +2520,21 @@ "manual_page": 27, "owner_lane": "adversary lane (a1a9876a88f5a72fc)", "run_status": "NOT RUN", - "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md", - "run_id": "adversary-20261008-placed-8lane", - "updated": "2026-10-08T20:41:20.327Z", + "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md; docs/analysis/class-v6/1p5x/x5/README.md", + "run_id": "adversary-20261009-x5", + "updated": "2026-10-09T09:11:10.596Z", "evidence_record": { "requirement_id": "ADV-02", "decision": "NOT RUN", "method": "model", - "cell": "adversary:d2b", - "manifest_sha": "3a8874fef", - "run_id": "adversary-20261008-placed-8lane", - "evidence": "docs/analysis/class-v6/multi-family-adversary.md", - "in_progress": true, - "coverage": "memory sharing, partial stores at the measured window-layer hit rates (and hit 0.50 with layer 8 off), recomputation and the set-up amortisation on the complete board (section 13); the formal memory model's terms (section 16)", + "cell": "adversary:x5-sweep", + "manifest_sha": "b54f8519", + "run_id": "adversary-20261009-x5", + "evidence": "docs/analysis/class-v6/1p5x/x5/README.md", + "in_progress": false, + "coverage": "the memory fractions 0.25 / 0.5 / 0.75, the full store and recomputation on the complete board; the hit curve per (pack, seed) pair from a trace JSON", "release_identity": { - "commit": "3a8874fef", + "commit": "b54f8519", "lockfile": "", "binary": "", "network_object": "", @@ -2543,7 +2543,8 @@ }, "claim_impact": "", "reviewer": "", - "at": "2026-10-08T20:41:20.327Z" + "at": "2026-10-09T09:11:10.596Z", + "note": "the co-optimised opponent sweep's rows on the frozen control (the die retained as the worst credible design, 2.44x same-node); NOT RUN until X6's blind run on held-out pairs; the per-box placements and the X1 trace re-runs land as deltas" }, "in_progress_since": "2026-10-08 18:3x UK", "approvals": { @@ -2596,6 +2597,29 @@ "claim_impact": "", "reviewer": "", "at": "2026-10-08T20:41:20.327Z" + }, + "adversary:x5-sweep": { + "requirement_id": "ADV-02", + "decision": "NOT RUN", + "method": "model", + "cell": "adversary:x5-sweep", + "manifest_sha": "b54f8519", + "run_id": "adversary-20261009-x5", + "evidence": "docs/analysis/class-v6/1p5x/x5/README.md", + "in_progress": false, + "coverage": "the memory fractions 0.25 / 0.5 / 0.75, the full store and recomputation on the complete board; the hit curve per (pack, seed) pair from a trace JSON", + "release_identity": { + "commit": "b54f8519", + "lockfile": "", + "binary": "", + "network_object": "", + "activation": "", + "profile_hashes": "" + }, + "claim_impact": "", + "reviewer": "", + "at": "2026-10-09T09:11:10.596Z", + "note": "the co-optimised opponent sweep's rows on the frozen control (the die retained as the worst credible design, 2.44x same-node); NOT RUN until X6's blind run on held-out pairs; the per-box placements and the X1 trace re-runs land as deltas" } } }, @@ -2843,21 +2867,21 @@ "manual_page": 28, "owner_lane": "k lane (a3c9601a6d4686fe1)", "run_status": "NOT RUN", - "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md; docs/analysis/class-v6/floor/shadow-k.md; docs/analysis/class-v6/multi-family-adversary.md", - "run_id": "adversary-20261009-placed-32lane", - "updated": "2026-10-09T07:32:30.503Z", + "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md; docs/analysis/class-v6/floor/shadow-k.md; docs/analysis/class-v6/multi-family-adversary.md; docs/analysis/class-v6/1p5x/x5/README.md", + "run_id": "adversary-20261009-x5", + "updated": "2026-10-09T09:11:10.596Z", "evidence_record": { "requirement_id": "ADV-05", "decision": "NOT RUN", "method": "model", - "cell": "adversary:mf-placed", - "manifest_sha": "aaf3405b", - "run_id": "adversary-20261009-placed-32lane", - "evidence": "docs/analysis/class-v6/multi-family-adversary.md", - "in_progress": true, - "coverage": "partial: the SRAM macros, ports, wiring, clocking and the complete-board terms are modelled in sections 2.3, 5 and 6 with the unmodelled items carried as uncertainty; the calibration against an existing hardware block is the k lane's bare-lane row beside it, owed as a named comparison", + "cell": "adversary:x5-sweep", + "manifest_sha": "b54f8519", + "run_id": "adversary-20261009-x5", + "evidence": "docs/analysis/class-v6/1p5x/x5/README.md", + "in_progress": false, + "coverage": "partial: the complete-board terms (PSU, VRM, cooling, host, controller) and the placed core's energies; the memory and SRAM figures claimed", "release_identity": { - "commit": "aaf3405b", + "commit": "b54f8519", "lockfile": "", "binary": "", "network_object": "", @@ -2866,8 +2890,8 @@ }, "claim_impact": "", "reviewer": "", - "at": "2026-10-09T07:32:30.503Z", - "note": "section 5: the 32-lane genesis core placed with SPEF, the 32-lane 18-family core placed and globally routed (estimate calibrated within 1 percent of SPEF); the SPEF row of the full core follows" + "at": "2026-10-09T09:11:10.596Z", + "note": "the co-optimised opponent sweep's rows on the frozen control (the die retained as the worst credible design, 2.44x same-node); NOT RUN until X6's blind run on held-out pairs; the per-box placements and the X1 trace re-runs land as deltas" }, "in_progress_since": "2026-10-08 18:3x UK", "approvals": { @@ -2921,6 +2945,29 @@ "reviewer": "", "at": "2026-10-09T07:32:30.503Z", "note": "section 5: the 32-lane genesis core placed with SPEF, the 32-lane 18-family core placed and globally routed (estimate calibrated within 1 percent of SPEF); the SPEF row of the full core follows" + }, + "adversary:x5-sweep": { + "requirement_id": "ADV-05", + "decision": "NOT RUN", + "method": "model", + "cell": "adversary:x5-sweep", + "manifest_sha": "b54f8519", + "run_id": "adversary-20261009-x5", + "evidence": "docs/analysis/class-v6/1p5x/x5/README.md", + "in_progress": false, + "coverage": "partial: the complete-board terms (PSU, VRM, cooling, host, controller) and the placed core's energies; the memory and SRAM figures claimed", + "release_identity": { + "commit": "b54f8519", + "lockfile": "", + "binary": "", + "network_object": "", + "activation": "", + "profile_hashes": "" + }, + "claim_impact": "", + "reviewer": "", + "at": "2026-10-09T09:11:10.596Z", + "note": "the co-optimised opponent sweep's rows on the frozen control (the die retained as the worst credible design, 2.44x same-node); NOT RUN until X6's blind run on held-out pairs; the per-box placements and the X1 trace re-runs land as deltas" } } }, @@ -3168,9 +3215,9 @@ "manual_page": 29, "owner_lane": "adversary lane (a1a9876a88f5a72fc)", "run_status": "NOT RUN", - "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md", - "run_id": "adversary-20261009-placed-32lane", - "updated": "2026-10-09T07:32:30.503Z", + "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md; docs/analysis/class-v6/1p5x/x5/README.md", + "run_id": "adversary-20261009-x5", + "updated": "2026-10-09T09:11:10.596Z", "approvals": { "scope_approved": null, "implementation_complete": null, @@ -3200,20 +3247,43 @@ "reviewer": "", "at": "2026-10-09T07:32:30.503Z", "note": "section 5: the 32-lane genesis core placed with SPEF, the 32-lane 18-family core placed and globally routed (estimate calibrated within 1 percent of SPEF); the SPEF row of the full core follows" + }, + "adversary:x5-sweep": { + "requirement_id": "ADV-08", + "decision": "NOT RUN", + "method": "model", + "cell": "adversary:x5-sweep", + "manifest_sha": "b54f8519", + "run_id": "adversary-20261009-x5", + "evidence": "docs/analysis/class-v6/1p5x/x5/README.md", + "in_progress": false, + "coverage": "the worst credible design retained as the specialist side a with its capital gate; X6 re-runs it blind on held-out pairs", + "release_identity": { + "commit": "b54f8519", + "lockfile": "", + "binary": "", + "network_object": "", + "activation": "", + "profile_hashes": "" + }, + "claim_impact": "", + "reviewer": "", + "at": "2026-10-09T09:11:10.596Z", + "note": "the co-optimised opponent sweep's rows on the frozen control (the die retained as the worst credible design, 2.44x same-node); NOT RUN until X6's blind run on held-out pairs; the per-box placements and the X1 trace re-runs land as deltas" } }, "evidence_record": { "requirement_id": "ADV-08", "decision": "NOT RUN", "method": "model", - "cell": "adversary:mf-placed", - "manifest_sha": "aaf3405b", - "run_id": "adversary-20261009-placed-32lane", - "evidence": "docs/analysis/class-v6/multi-family-adversary.md", - "in_progress": true, - "coverage": "the best-cost envelope on the complete machine (section 6) and the SRAM-die ticket reconciliation with lane B (section 15); the unaffiliated second reviewer is not this lane's", + "cell": "adversary:x5-sweep", + "manifest_sha": "b54f8519", + "run_id": "adversary-20261009-x5", + "evidence": "docs/analysis/class-v6/1p5x/x5/README.md", + "in_progress": false, + "coverage": "the worst credible design retained as the specialist side a with its capital gate; X6 re-runs it blind on held-out pairs", "release_identity": { - "commit": "aaf3405b", + "commit": "b54f8519", "lockfile": "", "binary": "", "network_object": "", @@ -3222,8 +3292,8 @@ }, "claim_impact": "", "reviewer": "", - "at": "2026-10-09T07:32:30.503Z", - "note": "section 5: the 32-lane genesis core placed with SPEF, the 32-lane 18-family core placed and globally routed (estimate calibrated within 1 percent of SPEF); the SPEF row of the full core follows" + "at": "2026-10-09T09:11:10.596Z", + "note": "the co-optimised opponent sweep's rows on the frozen control (the die retained as the worst credible design, 2.44x same-node); NOT RUN until X6's blind run on held-out pairs; the per-box placements and the X1 trace re-runs land as deltas" }, "in_progress_since": "2026-10-08T20:41:20.327Z" } diff --git a/tools/ci/batches/adversary-20261009-x5.json b/tools/ci/batches/adversary-20261009-x5.json new file mode 100644 index 000000000..39f0c8253 --- /dev/null +++ b/tools/ci/batches/adversary-20261009-x5.json @@ -0,0 +1,14 @@ +{ + "run_id": "adversary-20261009-x5", + "manifest_sha": "b54f8519", + "evidence_dir": "docs/analysis/class-v6/1p5x/x5/README.md", + "cells": [ + { + "cell": "adversary:x5-sweep", + "status": "NOT RUN", + "method": "model", + "evidence": "docs/analysis/class-v6/1p5x/x5/README.md", + "note": "the co-optimised opponent sweep's rows on the frozen control (the die retained as the worst credible design, 2.44x same-node); NOT RUN until X6's blind run on held-out pairs; the per-box placements and the X1 trace re-runs land as deltas" + } + ] +} diff --git a/tools/ci/test-map.json b/tools/ci/test-map.json index 0f41b7d05..024d04eb9 100644 --- a/tools/ci/test-map.json +++ b/tools/ci/test-map.json @@ -769,6 +769,24 @@ "TV-03": "partial: issuance timing and per-block subsidy for delayed entrants under three same-cap schedules; no genesis audit, no outsider rehearsal, no cohort", "TV-04": "partial: the subsidy's decline and the fee-dependence year at the four multiples; no role costs, fee volatility or zero-external-job scenario" } + }, + "adversary:x5-sweep": { + "command": "python3 tools/1p5x/x5/sweep.py --rows tools/chip-model/mf/results/table.csv --node N5 [--trace ] --json (on a build box under lease pool with a pid file; seconds)", + "box_class": "any box (python3)", + "method": "model", + "fixtures": [ + "F0" + ], + "cases": [ + "ADV-02", + "ADV-05", + "ADV-08" + ], + "coverage": { + "ADV-02": "the memory fractions 0.25 / 0.5 / 0.75, the full store and recomputation on the complete board; the hit curve per (pack, seed) pair from a trace JSON", + "ADV-05": "partial: the complete-board terms (PSU, VRM, cooling, host, controller) and the placed core's energies; the memory and SRAM figures claimed", + "ADV-08": "the worst credible design retained as the specialist side a with its capital gate; X6 re-runs it blind on held-out pairs" + } } }, "not_run": {