Counter ASIC 3.0: item 2's 9070 XT rows (bit-exact, +2.0 s OpenCL compile per pack, no rate cost)

docs/plans/counter-asic-3-derivation.md

@@ -464,3 +464,7 @@ chip ops per hash, 78.2 MH/s, 0.57x bare, 0.69x at 1.2x, 0.86x at 1.5x: under 1x
 | The integrated tier's build with the day program | approximate (5.5); the gfx1036 measurement is a PC 2 OpenCL job, not run today (the one PC 2 job carries the 5090) |
 | A 64-lane interpreter for pools (two units per batch) | unimplemented; it would cut the dispatch share for pool verifiers only |
 | The NVRTC cost of memhard.h inside the per-epoch hash kernel compile and the variant race | the PC 2 job's nvrtc line; the fix, if large, is one module per day for the item function |
+
+## 5.4b The RX 9070 XT rows (PC 1 job run-ca3-pc1-amd-derive-20261006, 6 October 2026, 17:23 to 17:29Z)
+
+Beside the miners (ratios stand, absolutes are loaded-card figures). Both dr736 packs bit-exact on AMD OpenCL (gfx1201, AMD-APP 3683.0): fingerprints 9553f6d5c667205a (devnet epoch 0) and 50e3eaa779da4f1e (genesis), two passes each, self-tests PASS. OpenCL compile 2,070 and 2,092 ms per pack against 41 ms for mx8 (+2.0 s per pack; a once-a-day item module is required on AMD as on NVIDIA). Daily 1 GiB build 168 to 189 ms against 205 to 273 for mx8 in the same session. Rate ratio to mx8 0.982 and 1.006. The 9070 XT row of the owed list is closed; the chip model and the go / no-go are unchanged by it.

docs/plans/counter-asic-3-status.md

@@ -52,6 +52,8 @@ Verifier headroom under the 10 ms gate (bdc07d3, the budget item 8's shadow ops
 
 The 5090 rows (job run-ca3-derive-pc2-20261006, 08:26:43 to 08:28:49Z, exit 0; the card was LOADED: the miner stayed up because the job posted the settings key without the device index, see corrections; ratios valid, absolutes not): bit-exact on CUDA for both dr736 packs (64 samples, 96 lanes, fingerprints 50e3eaa779da4f1e and 9553f6d5c667205a equal to the Mac's); 1 GiB build 42 / 32 ms against x8 40 and v2 46; rates 61 to 62 MH/s on every pack (the v2 control 62.3 against 136 unloaded); NVRTC compile 1,266 ms against x8's 164 ms, +1.1 s per pack because memhard.h's item function sits inside every hash-kernel and race-variant compile, so a once-a-day derivation module is a requirement of the class, not an option. Prover left ON, app untouched.
 
+The RX 9070 XT rows (PC 1 job run-ca3-pc1-amd-derive-20261006, 17:23:56 to 17:29:13Z, exit 0, beside the miners so the absolutes are loaded-card figures and the ratios stand): bit-exact on AMD OpenCL for both dr736 packs (fingerprints 9553f6d5c667205a and 50e3eaa779da4f1e equal to the Mac's and the 5090's, two passes each, self-tests PASS); the OpenCL compile 2,070 to 2,092 ms per dr736 pack against 41 ms for mx8 (+2.0 s per pack, the AMD twin of NVRTC's +1.1 s: the once-a-day derivation module is a requirement on every vendor, and on a one-click AMD miner the shadow-free x8 pack compiles in 0.04 s where the derivation pack takes 2.1); the 1 GiB daily build 168 to 189 ms against 205 to 273 for mx8 in the same loaded session (a build the same size or smaller, inside the noise); the rate ratio to mx8 0.982 and 1.006 (no hash-rate cost). With these the derivation's bit-exactness is on all three vendors and its hash-rate cost is zero on all three.
+
 Consequence: the derivation costs no hash rate on any card and 7 ms a day of build on the Mac (29 against 22 ms; the 5090 and the 9070 XT rows owed, the loaded-iGPU tier is the one to watch); it costs the verifier, and the verifier budget is shared with item 8's shadow ops under the one 10 ms gate, so the class v4 candidate is the pairing that fits, not either lever alone (both workers told).
 
 ### Item 8, the Mac rows (interim, ca3-shadow a050a54; knob d4b7300; `docs/analysis/latency-shadow-2026-10-06.md`; Metal packbench, IOReport GPU + DRAM watts without root; the 5090 rows queued on PC 2; the 9070 XT OWED)