Counter ASIC 3.0 gates (hash): the class v4 amendment for AP-F8-1 (Josh: option A, limited testing). The chain draw of class v4 takes a load's source only from registers whose last writer injects (add, sub, xor, mad, shfl, load) or is a rotate (rotl, rotr), never one last written by or, mul or mulhi (candidate_from_words_class, keyed on the era-composed V4_CLASS; no attempts lost, rule (a) unchanged, v2 and v3 and the generator-2 ladder packs byte-identical). Split protection agreed with the node lane: generator stays 4 and the program id of a generator-4 program appends "sub/" || PROGRAM_SUBVERSION_V4 (= 1) as little-endian u16 bytes inside program_id(), so a pre-amendment binary and this one never share an id for one seed; packs carry IGNEUM_PROGRAM_SUBVERSION 1 and program.json sub_version 1, and packcheck refuses a generator-4 pack whose sub-version is absent or other. The seven gate packs re-exported (devnet epoch 0 and eras 0 to 5): id 1a4230699a6b9c60 (was c120d7963abdcd96, now the must-differ vector in tests/recheck.rs), fingerprints Metal = Apple OpenCL 867dbc45cfb36b4d, 2146ecacc8c75a8e, fe52602393f6d3d4, 3b206471a13912b4, c3f03c4a5d7333aa, f1dfd7209f15bb97, 8c194da64fadf31d; the v3 control 73bcbfe8ccf988f1 / 90f794dd556f7a3b untouched. The mixer harness checks the source rule on every load site of an amended program instead of equality with the v3 base
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
This commit is contained in:
igneum-josh
parent
13e520b141
commit
a0aaca9201
75 changed files with 815 additions and 748 deletions
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@ -9,7 +9,7 @@
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//! One deliberate difference from the Swift: `program_json` writes the cache line mask inside the `"item"` string
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//! as a bare `0x003fffff`. The Swift writes it quoted (`jhex`), which is not valid JSON.
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use crate::generator::{EraParams, Instr, Op, Program, ProgramClass, GENERATOR_VERSION, INSTR_COUNT, ITERATIONS, LOAD_SLOTS};
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use crate::generator::{EraParams, Instr, Op, Program, ProgramClass, GENERATOR_VERSION, INSTR_COUNT, ITERATIONS, LOAD_SLOTS, PROGRAM_SUBVERSION_V4};
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use crate::derive::{instr_line as derive_instr_line, instr_text as derive_instr_text, DERIVE_PROGRAMS};
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use crate::memhard::{
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hot_key, hot_segments, hot_words, Layout, MixParams, Shape, CACHE_LINES_PER_SEGMENT, CACHE_SEGMENT_LOG2_LINES, CACHE_TAG,
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@ -173,6 +173,10 @@ fn program_class_header_lines(p: &Program) -> String {
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s.push_str("// runs another class refuses this pack, and a job line names the class it wants (class=v3 era=<hex>).\n");
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}
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s.push_str(&format!("#define IGNEUM_PROGRAM_CLASS {}\n", jstr(p.program_class().name())));
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if p.program_class() == ProgramClass::V4 {
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// the class v4 stream sub-version (AP-F8-1 amendment): a worker ignores it, packcheck requires it
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s.push_str(&format!("#define IGNEUM_PROGRAM_SUBVERSION {}\n", PROGRAM_SUBVERSION_V4));
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}
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if let Some(era) = &p.era_bytes {
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s.push_str(&format!("#define IGNEUM_ERA_SEED_HEX {}\n", jstr(&hex_bytes(era))));
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}
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@ -1825,6 +1829,9 @@ pub fn program_json(p: &Program, day: &str, ds: &DatasetSource) -> String {
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s.push_str(&format!(" \"loads_per_hash\": {},\n", p.loads_per_hash()));
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if p.program_class() != ProgramClass::V2 {
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s.push_str(&format!(" \"program_class\": {},\n", jstr(p.program_class().name())));
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if p.program_class() == ProgramClass::V4 {
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s.push_str(&format!(" \"sub_version\": {},\n", PROGRAM_SUBVERSION_V4));
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}
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if let Some(era) = &p.era_bytes {
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s.push_str(&format!(" \"era_seed_bytes\": {},\n", jstr(&hex_bytes(era))));
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}
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@ -1030,16 +1030,29 @@ impl Program {
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}
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pub fn program_id(generator: u32, seed: &[u32; 8], attempt: u32) -> u64 {
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let mut b = Vec::with_capacity(PROGRAM_ID_TAG.len() + 4 + 32 + 4);
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let mut b = Vec::with_capacity(PROGRAM_ID_TAG.len() + 4 + 32 + 4 + 6);
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b.extend_from_slice(PROGRAM_ID_TAG);
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b.extend_from_slice(&generator.to_le_bytes());
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for w in seed {
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b.extend_from_slice(&w.to_le_bytes());
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}
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b.extend_from_slice(&attempt.to_le_bytes());
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if generator == GENERATOR_VERSION_V4 {
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// The class v4 sub-version (AP-F8-1 amendment, 7 October 2026): `"sub/" || sub_version as little-endian u16`
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// appended for generator 4 only, so a binary from before the load-source rule (sub-version 0, no suffix) and
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// one after it never share a program id for one seed; the node's id check then catches a split. v2 and v3
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// ids are byte-identical. The node reads the sub-version from [`PROGRAM_SUBVERSION_V4`]; packs carry it as
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// IGNEUM_PROGRAM_SUBVERSION and program.json "sub_version".
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b.extend_from_slice(b"sub/");
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b.extend_from_slice(&PROGRAM_SUBVERSION_V4.to_le_bytes());
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}
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fnv1a64(&b)
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}
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/// The sub-version of class v4's program stream, in every generator-4 program id and pack (AP-F8-1: 1 = the
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/// load-source rule of `candidate_from_words_class`; 0 was the stream of 6 October 2026, never stamped).
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pub const PROGRAM_SUBVERSION_V4: u16 = 1;
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/// Domain tag of the program id of a read-width class (never collides with [`PROGRAM_ID_TAG`]).
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pub const PROGRAM_ID_TAG_RW: &[u8] = b"igneum-program-rw/";
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@ -1178,7 +1191,14 @@ pub fn candidate_from_words_class(
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is_hot[slot as usize] = true;
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}
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// (2) The instructions. `fresh[r]`: r was written by an earlier instruction and no load has read it since.
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// Class v4's chain draw (AP-F8-1, 7 October 2026, `docs/analysis/ca3-v4-uniform.md`): a load's source is drawn
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// only from registers whose last writer injects or is a rotate (`entropy_kept[r]`), never from one last written
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// by `or`, `mul` or `mulhi` (an `or`-written source is all-ones with probability (3/4)^32 per read and made the
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// 153x item of the finding). Keyed on the era-composed V4_CLASS so the generator-2 ladder packs keep their stream;
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// v2 and v3 take no part. The draw order and the stream are otherwise the same, draw for draw.
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let source_rule_v4 = ProgramClass::of_load_class(&class) == Some(ProgramClass::V4) && class.era.is_some();
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let mut fresh = [false; 8];
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let mut entropy_kept = [false; 8];
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let mut instrs = Vec::with_capacity(INSTR_COUNT);
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for k in 0..INSTR_COUNT {
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let mut roll = rng.below(75);
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@ -1204,7 +1224,7 @@ pub fn candidate_from_words_class(
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let mut eligible = [0u64; 8];
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let mut n = 0usize;
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for r in 0..8u64 {
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if r != dst && fresh[r as usize] {
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if r != dst && fresh[r as usize] && (!source_rule_v4 || entropy_kept[r as usize]) {
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eligible[n] = r;
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n += 1;
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}
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@ -1252,6 +1272,7 @@ pub fn candidate_from_words_class(
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fresh[src as usize] = false;
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}
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fresh[dst as usize] = true;
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entropy_kept[dst as usize] = op.injects() || matches!(op, Op::Rotl | Op::Rotr);
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instrs.push(Instr { op, dst: dst as u8, src: src as u8, src2: b as u8, imm, imm2, rot, bit: bit as u8, mask, width, win, off });
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}
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// (3) The latency-shadow block (Counter ASIC 3.0 item 8): drawn after the base program from the same stream, so
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@ -195,6 +195,15 @@ pub fn verify_pack_texts_chain(
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let shadow = define_u32(program_h, "IGNEUM_SHADOW_INSTRS").unwrap_or(0);
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match (class, shadow > 0) {
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(ProgramClass::V4, false) => return Err(PackFault::Disagree("IGNEUM_GENERATOR 4 (class v4) without IGNEUM_SHADOW_INSTRS: not a class v4 pack".into())),
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// the class v4 stream sub-version (AP-F8-1 amendment, 7 October 2026): a generator 4 pack from before the
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// load-source rule carries no IGNEUM_PROGRAM_SUBVERSION and its program id is another stream's; refused
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(ProgramClass::V4, true) if define_u32(program_h, "IGNEUM_PROGRAM_SUBVERSION") != Some(u32::from(crate::generator::PROGRAM_SUBVERSION_V4)) => {
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return Err(PackFault::Disagree(format!(
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"IGNEUM_GENERATOR 4 (class v4) with IGNEUM_PROGRAM_SUBVERSION {}: this software runs sub-version {} (a class v4 pack from before the load-source rule, or after another amendment)",
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define_u32(program_h, "IGNEUM_PROGRAM_SUBVERSION").map(|v| v.to_string()).unwrap_or_else(|| "absent".into()),
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crate::generator::PROGRAM_SUBVERSION_V4
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)))
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}
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(ProgramClass::V3, true) => {
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return Err(PackFault::Disagree(format!("IGNEUM_GENERATOR 3 (class v3) with a shadow block (IGNEUM_SHADOW_INSTRS {shadow}): a class v4 program is generator 4 (export the pack as class v4)")))
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}
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@ -92,8 +92,21 @@ fn contract(p: &Program, seed: &str, class: LoadClass, era: Option<[u8; 32]>) {
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assert_eq!((i.width, i.win, i.off), (1, 0, 0), "shadow #{k}: no load fields");
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}
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let base = program_of(seed, LoadClass { shadow: None, ..class }, era);
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assert_eq!(p.instrs, base.instrs, "{seed}: the base program is the class's without the shadow");
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assert_eq!(p.attempt, base.attempt);
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if p.generator == GENERATOR_VERSION_V4 {
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// the amended class v4 (AP-F8-1): the chain draw takes a load's source only from registers whose
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// last writer injects or rotates, so its base program is its own stream, not class v3's; what holds
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// is the rule itself, checked here on every load site in draw order
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let mut kept = [false; 8];
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for (k, i) in p.instrs.iter().enumerate() {
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if i.op.is_load() {
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assert!(kept[i.src as usize], "{seed}: load #{k} reads r{} whose last writer does not keep entropy", i.src);
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}
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kept[i.dst as usize] = i.op.injects() || matches!(i.op, Op::Rotl | Op::Rotr);
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}
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} else {
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assert_eq!(p.instrs, base.instrs, "{seed}: the base program is the class's without the shadow");
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assert_eq!(p.attempt, base.attempt);
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}
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if era.is_none() || p.generator == GENERATOR_VERSION_V4 {
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// a generator-2 program carries the shadow in its id bytes; a class v4 program is generator 4
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// (ca3-v4-node 7c22d0d), so its id differs from the generator-3 id of the same seeds
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@ -132,6 +132,9 @@ fn program_ids_differ_between_class_v3_and_class_v4_of_one_seed() {
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let v3 = load("packs-ca2-mixer/mx8-devnet-epoch0", ProgramClass::V3);
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let v4 = load("packs-ca3-v4/v4-devnet-epoch0", ProgramClass::V4);
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assert_eq!(v3.reference.program.program_id(), 0x73bc_bfe8_ccf9_88f1, "the v3 control's id as pinned");
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assert_eq!(v4.reference.program.program_id(), 0xc120_d796_3abd_cd96, "the v4 candidate's id as pinned");
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// the amended class v4 (AP-F8-1, sub-version 1): the id of 6 October 2026, c120d7963abdcd96, is the must-differ
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// vector (a binary from before the load-source rule), the pinned id below the must-equal one
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assert_ne!(v4.reference.program.program_id(), 0xc120_d796_3abd_cd96, "the pre-amendment v4 id must differ");
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assert_eq!(v4.reference.program.program_id(), 0x1a42_3069_9a6b_9c60, "the amended v4 candidate's id as pinned");
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assert_ne!(v3.reference.program.program_id(), v4.reference.program.program_id());
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}
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@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
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r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
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r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
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r5 = r5 * r4; // 12 mul
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r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r7 = r7 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
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{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
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r2 = r2 | r7; // 16 or
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@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
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r7 = rotr_var(r7, r0); // 26 rotr
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r4 = r5 * r7 + r4; // 27 mad
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r3 = r2 * r4 + r3; // 28 mad
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
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r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
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r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
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r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
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@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
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r7 = r7 - r0; // 41 sub
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r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
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r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r0 = r0 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
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r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r3 = r3 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r4 = mul_hi(r4, r2); // 48 mulhi
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r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
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r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
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r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r6 = rotl_imm(r6, 12u); // 53 rotl
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r3 = rotl_imm(r3, 12u); // 54 rotl
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r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r5 = r5 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
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r3 = mul_hi(r3, r2); // 60 mulhi
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r6 = r6 | r4; // 61 or
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{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
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r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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r3 = r3 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
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for (uint sh = 0u; sh < 27u; ++sh) {
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r7 = r7 * r3; // s0 mul
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@ -71,7 +71,7 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
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r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
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r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
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r5 = r5 * r4; // 12 mul
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r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r7 = r7 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
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r2 = r2 | r7; // 16 or
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@ -87,9 +87,9 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
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r7 = rotr_var(r7, r0); // 26 rotr
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r4 = r5 * r7 + r4; // 27 mad
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r3 = r2 * r4 + r3; // 28 mad
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -102,26 +102,26 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
@ -577,7 +577,7 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -593,9 +593,9 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -608,26 +608,26 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -64,9 +64,9 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -79,26 +79,26 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
#define IGNEUM_GENERATOR 4
|
||||
#define IGNEUM_PROGRAM_ATTEMPT 0
|
||||
#define IGNEUM_PROGRAM_ID 0xc120d7963abdcd96ull
|
||||
#define IGNEUM_PROGRAM_ID 0x1a4230699a6b9c60ull
|
||||
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY0 0xceed56d7u
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
// latency-shadow block (IGNEUM_SHADOW_INSTRS x IGNEUM_SHADOW_REPS per iteration); a worker that runs another class
|
||||
// refuses this pack, and a job line names the class it wants (class=v4 era=<hex>).
|
||||
#define IGNEUM_PROGRAM_CLASS "v4"
|
||||
#define IGNEUM_PROGRAM_SUBVERSION 1
|
||||
#define IGNEUM_ERA_SEED_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
|
||||
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
"format": "igneum-program-pack-3",
|
||||
"generator": 4,
|
||||
"attempt": 0,
|
||||
"program_id": "0xc120d7963abdcd96",
|
||||
"program_id": "0x1a4230699a6b9c60",
|
||||
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
|
||||
"dataset_mode": "memory-hard",
|
||||
"seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000",
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
"instruction_count": 64,
|
||||
"loads_per_hash": 128,
|
||||
"program_class": "v4",
|
||||
"sub_version": 1,
|
||||
"era_seed_bytes": "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07",
|
||||
"load_class": "mx8-erad810f22d+sh256x27",
|
||||
"mixer_mult": 8,
|
||||
|
|
@ -350,7 +351,7 @@
|
|||
{"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -366,9 +367,9 @@
|
|||
{"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 6, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 4, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -381,25 +382,25 @@
|
|||
{"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 2, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 0, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 4, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 7, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 2, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -67,9 +67,9 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -82,26 +82,26 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -69,9 +69,9 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -84,26 +84,26 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x9ad30d99u, 29u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x9ad30d99u, 29u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@
|
|||
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
|
||||
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
|
||||
{ // base nonce 0
|
||||
0xcefc114b62c2013bull, 0x82df54bee88f1fa9ull, 0x94ed24d32cecf436ull, 0x8a9bd67e3fed0c5bull, 0x7c1a21514ebe42b7ull, 0x0edd5b084c5815edull, 0x077927721192da87ull, 0x28e26e3eb72cd8c4ull,
|
||||
0xbc7f3f9fd6f31019ull, 0x9760c30962c54b67ull, 0x1d3973217b0f60e9ull, 0xb9dce5f8dbc47f84ull, 0xf48230bc1c38a8a6ull, 0xab2be58a952ee580ull, 0x063033462d39b5faull, 0x63ca56a0425cd505ull,
|
||||
0xc8c1e7342452a6d5ull, 0xe936506b6f9c5859ull, 0xbe73aaebab23a47dull, 0x185855356357c704ull, 0x8e4d10d9f929e4c6ull, 0x8162627beec866c7ull, 0x5bfae763cdba41f4ull, 0xbd133821e099c624ull,
|
||||
0x11a8f07f88a424aaull, 0x9f872faaa642d022ull, 0xe02e4e5a55e161bbull, 0xec4674b8e19443a3ull, 0xcb09ce61d2a7a482ull, 0x246fc454a58d9623ull, 0xe4e9d962e94f9d44ull, 0xea8f7e5f79b3cd6cull
|
||||
0x837032e82d96966eull, 0xe400757e57712a79ull, 0x7afb27f5eff8d4a9ull, 0x690f90c80f28d5aaull, 0x60351a57093c2f5dull, 0xd546a50ab88c2c20ull, 0x1d41c04480f2929dull, 0xce52b5688638299bull,
|
||||
0x950bce60d327a06eull, 0xe36c974f18915af7ull, 0xfee59c8e8282e192ull, 0x2695391e5f751be0ull, 0xab6f0a8ef7e26d64ull, 0xe798d2429e3e407full, 0x5642d72903cc92c6ull, 0xb32014567a8e89aeull,
|
||||
0x24755f41b337f39full, 0xf5bdea70c8f0cd68ull, 0xdce45b09663303a1ull, 0x6305fe683263beb6ull, 0xc147804cd12811deull, 0xda9489cee95ea55dull, 0x2b4da4c979259f4eull, 0x9265d4dfd994d505ull,
|
||||
0x430a9a3cc8b4e9f9ull, 0xe6a4aae26704d9e3ull, 0x85f97c529602e55cull, 0xd7fc2ee9fc4e9bb9ull, 0x05ca6ed316003925ull, 0x9d5b430772de1152ull, 0xc3ce9fccd2e85d2full, 0x46060d971ee45f28ull
|
||||
},
|
||||
{ // base nonce 4096
|
||||
0x72369740c7e914faull, 0x4e26670191e736b1ull, 0xfd0539ebd2476ba2ull, 0xbe026940c9b9b0cfull, 0x173cb4ffa35536dbull, 0x7a8c9f39fee473c8ull, 0xf1edbc92d4cf8fa7ull, 0x94cafcf8fe4d3484ull,
|
||||
0xaf52574e663f35d4ull, 0x3bfb83843cd530d1ull, 0x2276280eeb130699ull, 0x15363890a20c32c8ull, 0xfef7c4da969248c5ull, 0x53a0e23bb0180cbbull, 0x282baa859711bdcfull, 0x6b4175f6beb71cddull,
|
||||
0xa4e2f89843daa5b2ull, 0x9869cfcd682cb892ull, 0x8cb61b6583116468ull, 0x6a229c5101f56038ull, 0x16879e17e3a67e45ull, 0x0bfd173dfec23e7dull, 0x163009720a7cbe26ull, 0xc981a122be3e093eull,
|
||||
0xc8b10d937fd4fd68ull, 0x046db9ec4d476d23ull, 0x24d7d036955fc12aull, 0x6d4a7f64498eb506ull, 0x4bc021381be82d8dull, 0x8b53fe60b02ff39eull, 0x4f4aa55e80356ed4ull, 0xb87adc5371e0d7f3ull
|
||||
0x159824e1eeb921d2ull, 0x084629fc02b9d0deull, 0x22b9febf128a349cull, 0x090f3f649ac2ae79ull, 0x0d528956fb08ddc3ull, 0x99ac0576f36f43b8ull, 0x54610fcd8c439558ull, 0x6807c21b6e22727full,
|
||||
0xbd400a465ea10758ull, 0x6013d747c402d1eaull, 0x0c67d5e8760e32b9ull, 0x6d8ea819e938e96eull, 0xb61bbd97c43c615bull, 0xecf0b98e5d994f71ull, 0xd4891674382ab27eull, 0xd6a03a6e264d7bb9ull,
|
||||
0xe07185cd8828eac4ull, 0x11542c89f6340637ull, 0xda33d26e75cf619bull, 0xe6978aae3c70e560ull, 0xb4db0f0a6a047345ull, 0x5cc439b113cf73e4ull, 0x1296de8959046d5full, 0x131bfa7fc911b7ecull,
|
||||
0x7b9f4b82a5aa30a6ull, 0x24a302d88719d9f3ull, 0x952e426ba403805dull, 0x4f367471bb100c89ull, 0xbf2766e605a78bf3ull, 0x93c8bd18dc344accull, 0x331281075a9a6c50ull, 0x47f36d248de951bbull
|
||||
},
|
||||
{ // base nonce 1000000
|
||||
0xed8dab53b5e8e8edull, 0xa9094d1bb25a004eull, 0x26ec1cf0f7dbc177ull, 0x27a48a41c3b4e0d4ull, 0x56e048da75af2d13ull, 0xfedf9d48b3ed20d4ull, 0x68ab0258d0717aa6ull, 0x350a3144bf94e1c1ull,
|
||||
0x001a69003600a82full, 0x14ad260948d3e939ull, 0x5e255b44fd3e47b7ull, 0x53b5103bdee253beull, 0xc8cf96e4e28c7827ull, 0x10714ce66ccdbf82ull, 0x970092db360dd3c8ull, 0x0910d973b2114663ull,
|
||||
0x5755d28da59e923full, 0x867d702953278b8eull, 0x24d34058189ed262ull, 0xa38e73420b9e0405ull, 0xfdb7f7ceb03ae23bull, 0xf0e19d50f68941fdull, 0x0745a1fbcd7c081bull, 0xf56202c4322ddc9full,
|
||||
0x7754d69c1e232baeull, 0x8f769e87329523f7ull, 0x72005edcdb8bbe99ull, 0x1cc4600ef8652eb6ull, 0x9edcc4a4a846dd5cull, 0x16d2ba401de9992cull, 0x41ea900971c6a4f4ull, 0xc06178510e3ce787ull
|
||||
0x5be98dadb4171fadull, 0x096a01476342df27ull, 0xeeb669c1de4abe93ull, 0x51a0347c77e6d2bfull, 0xab08f1d6b3869387ull, 0x1ca5db9504f59e6bull, 0x8af8e8a147e6b899ull, 0xaa24d17ade936730ull,
|
||||
0x282599079c4d7f67ull, 0x22ca5f2967fa11cbull, 0x02c666545cab030eull, 0xb780105ca9815792ull, 0xe1ad6ea2a5027b12ull, 0xc5af9bce86a8295bull, 0x1051ae97c227548cull, 0x9fa2aa166beaa9d5ull,
|
||||
0xe56fbb9c5e51d135ull, 0x33ae0e1f818b6cadull, 0x8d061e05986ddbafull, 0xc18ff71984aff2d4ull, 0xd4a9156a12f9b2f7ull, 0x03e1a178fb252186ull, 0xc521acdd97d2eacfull, 0x14c2a451696d092dull,
|
||||
0x9d4f0da649eff67cull, 0xef1e861bcf9c4304ull, 0x0b9fcc86fbe4578aull, 0xcf3edce409dc534bull, 0x1a1a196970baf6ebull, 0x2d4e02b51c9e03cdull, 0x851be67d4f7a99e7ull, 0x9c4d76d2a79f8d87ull
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,22 +8,22 @@
|
|||
"source": "igneum-pow (Rust) CPU interpreter, generator v4, memory-hard dataset",
|
||||
"warps": [
|
||||
{"base_nonce": 0, "expected": [
|
||||
"0xcefc114b62c2013b", "0x82df54bee88f1fa9", "0x94ed24d32cecf436", "0x8a9bd67e3fed0c5b", "0x7c1a21514ebe42b7", "0x0edd5b084c5815ed", "0x077927721192da87", "0x28e26e3eb72cd8c4",
|
||||
"0xbc7f3f9fd6f31019", "0x9760c30962c54b67", "0x1d3973217b0f60e9", "0xb9dce5f8dbc47f84", "0xf48230bc1c38a8a6", "0xab2be58a952ee580", "0x063033462d39b5fa", "0x63ca56a0425cd505",
|
||||
"0xc8c1e7342452a6d5", "0xe936506b6f9c5859", "0xbe73aaebab23a47d", "0x185855356357c704", "0x8e4d10d9f929e4c6", "0x8162627beec866c7", "0x5bfae763cdba41f4", "0xbd133821e099c624",
|
||||
"0x11a8f07f88a424aa", "0x9f872faaa642d022", "0xe02e4e5a55e161bb", "0xec4674b8e19443a3", "0xcb09ce61d2a7a482", "0x246fc454a58d9623", "0xe4e9d962e94f9d44", "0xea8f7e5f79b3cd6c"
|
||||
"0x837032e82d96966e", "0xe400757e57712a79", "0x7afb27f5eff8d4a9", "0x690f90c80f28d5aa", "0x60351a57093c2f5d", "0xd546a50ab88c2c20", "0x1d41c04480f2929d", "0xce52b5688638299b",
|
||||
"0x950bce60d327a06e", "0xe36c974f18915af7", "0xfee59c8e8282e192", "0x2695391e5f751be0", "0xab6f0a8ef7e26d64", "0xe798d2429e3e407f", "0x5642d72903cc92c6", "0xb32014567a8e89ae",
|
||||
"0x24755f41b337f39f", "0xf5bdea70c8f0cd68", "0xdce45b09663303a1", "0x6305fe683263beb6", "0xc147804cd12811de", "0xda9489cee95ea55d", "0x2b4da4c979259f4e", "0x9265d4dfd994d505",
|
||||
"0x430a9a3cc8b4e9f9", "0xe6a4aae26704d9e3", "0x85f97c529602e55c", "0xd7fc2ee9fc4e9bb9", "0x05ca6ed316003925", "0x9d5b430772de1152", "0xc3ce9fccd2e85d2f", "0x46060d971ee45f28"
|
||||
]},
|
||||
{"base_nonce": 4096, "expected": [
|
||||
"0x72369740c7e914fa", "0x4e26670191e736b1", "0xfd0539ebd2476ba2", "0xbe026940c9b9b0cf", "0x173cb4ffa35536db", "0x7a8c9f39fee473c8", "0xf1edbc92d4cf8fa7", "0x94cafcf8fe4d3484",
|
||||
"0xaf52574e663f35d4", "0x3bfb83843cd530d1", "0x2276280eeb130699", "0x15363890a20c32c8", "0xfef7c4da969248c5", "0x53a0e23bb0180cbb", "0x282baa859711bdcf", "0x6b4175f6beb71cdd",
|
||||
"0xa4e2f89843daa5b2", "0x9869cfcd682cb892", "0x8cb61b6583116468", "0x6a229c5101f56038", "0x16879e17e3a67e45", "0x0bfd173dfec23e7d", "0x163009720a7cbe26", "0xc981a122be3e093e",
|
||||
"0xc8b10d937fd4fd68", "0x046db9ec4d476d23", "0x24d7d036955fc12a", "0x6d4a7f64498eb506", "0x4bc021381be82d8d", "0x8b53fe60b02ff39e", "0x4f4aa55e80356ed4", "0xb87adc5371e0d7f3"
|
||||
"0x159824e1eeb921d2", "0x084629fc02b9d0de", "0x22b9febf128a349c", "0x090f3f649ac2ae79", "0x0d528956fb08ddc3", "0x99ac0576f36f43b8", "0x54610fcd8c439558", "0x6807c21b6e22727f",
|
||||
"0xbd400a465ea10758", "0x6013d747c402d1ea", "0x0c67d5e8760e32b9", "0x6d8ea819e938e96e", "0xb61bbd97c43c615b", "0xecf0b98e5d994f71", "0xd4891674382ab27e", "0xd6a03a6e264d7bb9",
|
||||
"0xe07185cd8828eac4", "0x11542c89f6340637", "0xda33d26e75cf619b", "0xe6978aae3c70e560", "0xb4db0f0a6a047345", "0x5cc439b113cf73e4", "0x1296de8959046d5f", "0x131bfa7fc911b7ec",
|
||||
"0x7b9f4b82a5aa30a6", "0x24a302d88719d9f3", "0x952e426ba403805d", "0x4f367471bb100c89", "0xbf2766e605a78bf3", "0x93c8bd18dc344acc", "0x331281075a9a6c50", "0x47f36d248de951bb"
|
||||
]},
|
||||
{"base_nonce": 1000000, "expected": [
|
||||
"0xed8dab53b5e8e8ed", "0xa9094d1bb25a004e", "0x26ec1cf0f7dbc177", "0x27a48a41c3b4e0d4", "0x56e048da75af2d13", "0xfedf9d48b3ed20d4", "0x68ab0258d0717aa6", "0x350a3144bf94e1c1",
|
||||
"0x001a69003600a82f", "0x14ad260948d3e939", "0x5e255b44fd3e47b7", "0x53b5103bdee253be", "0xc8cf96e4e28c7827", "0x10714ce66ccdbf82", "0x970092db360dd3c8", "0x0910d973b2114663",
|
||||
"0x5755d28da59e923f", "0x867d702953278b8e", "0x24d34058189ed262", "0xa38e73420b9e0405", "0xfdb7f7ceb03ae23b", "0xf0e19d50f68941fd", "0x0745a1fbcd7c081b", "0xf56202c4322ddc9f",
|
||||
"0x7754d69c1e232bae", "0x8f769e87329523f7", "0x72005edcdb8bbe99", "0x1cc4600ef8652eb6", "0x9edcc4a4a846dd5c", "0x16d2ba401de9992c", "0x41ea900971c6a4f4", "0xc06178510e3ce787"
|
||||
"0x5be98dadb4171fad", "0x096a01476342df27", "0xeeb669c1de4abe93", "0x51a0347c77e6d2bf", "0xab08f1d6b3869387", "0x1ca5db9504f59e6b", "0x8af8e8a147e6b899", "0xaa24d17ade936730",
|
||||
"0x282599079c4d7f67", "0x22ca5f2967fa11cb", "0x02c666545cab030e", "0xb780105ca9815792", "0xe1ad6ea2a5027b12", "0xc5af9bce86a8295b", "0x1051ae97c227548c", "0x9fa2aa166beaa9d5",
|
||||
"0xe56fbb9c5e51d135", "0x33ae0e1f818b6cad", "0x8d061e05986ddbaf", "0xc18ff71984aff2d4", "0xd4a9156a12f9b2f7", "0x03e1a178fb252186", "0xc521acdd97d2eacf", "0x14c2a451696d092d",
|
||||
"0x9d4f0da649eff67c", "0xef1e861bcf9c4304", "0x0b9fcc86fbe4578a", "0xcf3edce409dc534b", "0x1a1a196970baf6eb", "0x2d4e02b51c9e03cd", "0x851be67d4f7a99e7", "0x9c4d76d2a79f8d87"
|
||||
]}
|
||||
],
|
||||
"dataset_head": ["0x19c6837f", "0xdf3adfb8", "0xbd3f6aed", "0xb8bede0d", "0xc5f0629f", "0x03e38ae8", "0xc435a60e", "0xfadee916", "0x827e59af", "0x8cf592f5", "0x60286061", "0x5d9abc1c", "0xa85d0c39", "0x4247a100", "0xd41a5b0d", "0x3f33dc64"],
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -87,9 +87,9 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -102,26 +102,26 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
@ -577,7 +577,7 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -593,9 +593,9 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -608,26 +608,26 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -64,9 +64,9 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -79,26 +79,26 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
#define IGNEUM_GENERATOR 4
|
||||
#define IGNEUM_PROGRAM_ATTEMPT 0
|
||||
#define IGNEUM_PROGRAM_ID 0xc120d7963abdcd96ull
|
||||
#define IGNEUM_PROGRAM_ID 0x1a4230699a6b9c60ull
|
||||
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY0 0xceed56d7u
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
// latency-shadow block (IGNEUM_SHADOW_INSTRS x IGNEUM_SHADOW_REPS per iteration); a worker that runs another class
|
||||
// refuses this pack, and a job line names the class it wants (class=v4 era=<hex>).
|
||||
#define IGNEUM_PROGRAM_CLASS "v4"
|
||||
#define IGNEUM_PROGRAM_SUBVERSION 1
|
||||
#define IGNEUM_ERA_SEED_HEX "8bffdd3366b9c3ffe89c1231e91538d531cfa717307df5c48ccba43096e17212"
|
||||
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
|
||||
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
"format": "igneum-program-pack-3",
|
||||
"generator": 4,
|
||||
"attempt": 0,
|
||||
"program_id": "0xc120d7963abdcd96",
|
||||
"program_id": "0x1a4230699a6b9c60",
|
||||
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
|
||||
"dataset_mode": "memory-hard",
|
||||
"seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000",
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
"instruction_count": 64,
|
||||
"loads_per_hash": 128,
|
||||
"program_class": "v4",
|
||||
"sub_version": 1,
|
||||
"era_seed_bytes": "8bffdd3366b9c3ffe89c1231e91538d531cfa717307df5c48ccba43096e17212",
|
||||
"load_class": "mx8-erab2ed8a89+sh256x27",
|
||||
"mixer_mult": 8,
|
||||
|
|
@ -350,7 +351,7 @@
|
|||
{"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -366,9 +367,9 @@
|
|||
{"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 6, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 4, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -381,25 +382,25 @@
|
|||
{"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 2, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 0, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 4, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 7, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 2, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -67,9 +67,9 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -82,26 +82,26 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -69,9 +69,9 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -84,26 +84,26 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@
|
|||
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
|
||||
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
|
||||
{ // base nonce 0
|
||||
0xc6ac65d8c667c94bull, 0x423ba68373b366fbull, 0x21eb7c55ad8be449ull, 0x241e717cf2ab882aull, 0xa615906f3f9be2ceull, 0xce309393aa36b7efull, 0x6243ddb51a337304ull, 0xe0495ce514ee4267ull,
|
||||
0xf479942a15b82d19ull, 0x3484f32ff6dcf936ull, 0x3d485cd36298b5daull, 0xcdb8c5017040e9edull, 0xed23ab1ee79266d1ull, 0x1a56ee16d69ad2a3ull, 0x0646e3397a174f83ull, 0x98ea781f02a5071aull,
|
||||
0x8c77f5c840d7762full, 0x4720419c079f4b89ull, 0xa9b0e2c3c07d9885ull, 0x612ecd1ff4ecd3c5ull, 0x254f3b36ad521004ull, 0x46d1f55d10cac72dull, 0xd7a5ba62b5d9315dull, 0xeac91757fb066b5full,
|
||||
0x84f6904c2da56898ull, 0x06efd77b90561e3cull, 0x9e152e00cd51627bull, 0x708c82cc2f545ca5ull, 0x7fb90cbb65b09681ull, 0x1a170cf306c6b81cull, 0x3d5fa555658bc6bfull, 0xb1dbc3e905378746ull
|
||||
0x3dd0c5d231aa501eull, 0xd6fac2cabd2d6f6dull, 0x94dd1d52f3cbde69ull, 0x382eecd03346f247ull, 0xce02ff223174b2d5ull, 0x86133c87300c6004ull, 0xdeff000d067516a7ull, 0x132937b3de51eaa5ull,
|
||||
0xee969d32009c357dull, 0x26c96fe5ece24f40ull, 0x5a6731206c31015cull, 0x52485bb69394bd45ull, 0x84a3d088549fb18cull, 0x73490ad1812a5787ull, 0xb8a899ed79de5745ull, 0xf5942bba1013aae3ull,
|
||||
0x9904fc45e408f9c8ull, 0x461cc234f82e6148ull, 0x89efc3ae79151634ull, 0x1da4085d6534f05dull, 0xcfca19af8c07e328ull, 0xdce057431e0745d1ull, 0x995257cf023bcdd8ull, 0x557647f1a9f4a9dfull,
|
||||
0xdeeff4ed4e9c7d77ull, 0xb88c4f6a98a7ea79ull, 0x3305dfd9d4330bdbull, 0xc0c9d98a57213bedull, 0x53a31b13526a2ac9ull, 0x66573ca57c48cd25ull, 0x4da452bb061408b0ull, 0x460bb36b6fd504d8ull
|
||||
},
|
||||
{ // base nonce 4096
|
||||
0x3be623a0f075d1f3ull, 0x2552e70de3533e93ull, 0x4c58e7fac79e754dull, 0x4c6ce1acd35693f6ull, 0x9c356bcd5f1d4639ull, 0x29361be2e3fa88efull, 0x8a1878dfba4b4637ull, 0x9289b157d1a01a8cull,
|
||||
0x70a4b5646d471b8eull, 0xcf1595ab96209aa0ull, 0xe83503a00680799aull, 0x7c1179b26025fcb4ull, 0x5a7aa05cd428f182ull, 0x02466e4a89473e34ull, 0xbd379fafb5889deeull, 0x914679b7d4a92eceull,
|
||||
0x71b1611d70b03bd4ull, 0x9b6ec7ca5afd24dbull, 0x955f2305b288ef17ull, 0x456aeb62e25e0a8cull, 0x40724ed4d6c72cc7ull, 0xf520227cecca4067ull, 0x92146b6c5d82408full, 0xbacdfeaa3693bba5ull,
|
||||
0xb50a632febcaff29ull, 0x60bfffcb8b540752ull, 0x3eb9dbc42fc7b9d9ull, 0x73fd73c129763cd9ull, 0x701a9ec7130c5833ull, 0x02845e3260dbb636ull, 0x3b15ad42edfd3e74ull, 0x531d777ef600ee58ull
|
||||
0x039cc30b8c031a48ull, 0xf9bfd6b480657c03ull, 0xaf13478481593783ull, 0x872ea5b7d73b8925ull, 0x889bfedd51045247ull, 0xe1ab81c6dcd69ff3ull, 0x2507dd502da1b9daull, 0x7567a01889f83134ull,
|
||||
0xde7d8f2cac60920eull, 0x0e0a63d966799441ull, 0x9d98775713c4a0e4ull, 0x47209fdd7ae001b7ull, 0x05c0d79abf0af16dull, 0xb94aa6292dd13bbcull, 0x63cb6d147242c41dull, 0x2ea7910c292d7444ull,
|
||||
0xdd482ea897c1996eull, 0xe84344303344b919ull, 0xe82c94a23d2bfba5ull, 0xe9d885013e70dcecull, 0xc4bb99afe28e20a5ull, 0x3f176b1b1ec2d0fcull, 0xd192d3f4b4198535ull, 0x7efd10fb18a3aed8ull,
|
||||
0x2aae74311fd49683ull, 0x84d188bc8cf911abull, 0x692d0a7500eed484ull, 0x227b6a6a62221e2cull, 0x6e7d05153c894e6full, 0x33e8b228c6751367ull, 0xbaa37d348728a2e8ull, 0x518f7da3478e7e74ull
|
||||
},
|
||||
{ // base nonce 1000000
|
||||
0xde8458bcb18fb637ull, 0x0206b58b1f067ff0ull, 0xe107cdd0e87d28aeull, 0x49fef7f22bc586d4ull, 0xff64163d017070ccull, 0x968adfe921ccec1bull, 0xe9560f8a3fa830daull, 0x5d6f239c97224957ull,
|
||||
0xcc2f980c31f7c7e5ull, 0x4d7cd09c7b731241ull, 0x5b1841dcfa517b45ull, 0xabd19c355dd4723full, 0x316eaf5ba7e30331ull, 0xec8156a374468b8dull, 0x0e3505a1ec9fe2a1ull, 0x5f1f5a94a69a1178ull,
|
||||
0xd4e6f7fda43c5056ull, 0x5ce560511eddb335ull, 0x88180b5ce94621cfull, 0xb1095ce2dc071b55ull, 0xded0110936b4cf80ull, 0x43d2bbff72e231bcull, 0xdd2bae28dbc4a9feull, 0x1c5055680fc7bca6ull,
|
||||
0x1917e8e4e79db0adull, 0xb4f64af4d8f8a7c2ull, 0xd6df5b0607279b60ull, 0x3da81ec2899f8314ull, 0x384c998c46ab8b80ull, 0x7c8ada8b7ca44cd5ull, 0x1346a6394b7e4e05ull, 0x4e9868001eb79a14ull
|
||||
0xff3704a4b4a39d74ull, 0x67ce2a95ff7f485eull, 0x0bc692d8d7c4b47bull, 0x91713025b7bfdad7ull, 0x01e28c92dacef958ull, 0xbe8d553dd7e4c987ull, 0x34ce4c7529ec9b1aull, 0xe2b3cbde7b2ff12eull,
|
||||
0xe05d9ff4895ab93eull, 0x09654827998a3e1aull, 0xd12e8d8776c76dadull, 0x96b916349effd9cfull, 0x6bf979214e05b755ull, 0x3082bfd6379b2b4dull, 0x283bec328ba13c9dull, 0x9f1b34dd7d719254ull,
|
||||
0x62429fc39f085fa0ull, 0x8e0e3bf0a74eab65ull, 0x12c89e7a7f7e27a3ull, 0xf4685da8ff6d84a6ull, 0xd2ac7b54e4f6ec1aull, 0x8bdf7f5fa3c211b1ull, 0x2cf20f105f8fd9f4ull, 0xd838f3668d715762ull,
|
||||
0x3cecb064b01bb2d6ull, 0x07a6fb3335e1f1aaull, 0x3d46b9036720b74aull, 0xeb6a68cdbc2a4efcull, 0xab1b29e32b4b9c37ull, 0x8023aae06ffaa42bull, 0x1a9eb7b38f4aa48eull, 0x21ee84e150b406a8ull
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,22 +8,22 @@
|
|||
"source": "igneum-pow (Rust) CPU interpreter, generator v4, memory-hard dataset",
|
||||
"warps": [
|
||||
{"base_nonce": 0, "expected": [
|
||||
"0xc6ac65d8c667c94b", "0x423ba68373b366fb", "0x21eb7c55ad8be449", "0x241e717cf2ab882a", "0xa615906f3f9be2ce", "0xce309393aa36b7ef", "0x6243ddb51a337304", "0xe0495ce514ee4267",
|
||||
"0xf479942a15b82d19", "0x3484f32ff6dcf936", "0x3d485cd36298b5da", "0xcdb8c5017040e9ed", "0xed23ab1ee79266d1", "0x1a56ee16d69ad2a3", "0x0646e3397a174f83", "0x98ea781f02a5071a",
|
||||
"0x8c77f5c840d7762f", "0x4720419c079f4b89", "0xa9b0e2c3c07d9885", "0x612ecd1ff4ecd3c5", "0x254f3b36ad521004", "0x46d1f55d10cac72d", "0xd7a5ba62b5d9315d", "0xeac91757fb066b5f",
|
||||
"0x84f6904c2da56898", "0x06efd77b90561e3c", "0x9e152e00cd51627b", "0x708c82cc2f545ca5", "0x7fb90cbb65b09681", "0x1a170cf306c6b81c", "0x3d5fa555658bc6bf", "0xb1dbc3e905378746"
|
||||
"0x3dd0c5d231aa501e", "0xd6fac2cabd2d6f6d", "0x94dd1d52f3cbde69", "0x382eecd03346f247", "0xce02ff223174b2d5", "0x86133c87300c6004", "0xdeff000d067516a7", "0x132937b3de51eaa5",
|
||||
"0xee969d32009c357d", "0x26c96fe5ece24f40", "0x5a6731206c31015c", "0x52485bb69394bd45", "0x84a3d088549fb18c", "0x73490ad1812a5787", "0xb8a899ed79de5745", "0xf5942bba1013aae3",
|
||||
"0x9904fc45e408f9c8", "0x461cc234f82e6148", "0x89efc3ae79151634", "0x1da4085d6534f05d", "0xcfca19af8c07e328", "0xdce057431e0745d1", "0x995257cf023bcdd8", "0x557647f1a9f4a9df",
|
||||
"0xdeeff4ed4e9c7d77", "0xb88c4f6a98a7ea79", "0x3305dfd9d4330bdb", "0xc0c9d98a57213bed", "0x53a31b13526a2ac9", "0x66573ca57c48cd25", "0x4da452bb061408b0", "0x460bb36b6fd504d8"
|
||||
]},
|
||||
{"base_nonce": 4096, "expected": [
|
||||
"0x3be623a0f075d1f3", "0x2552e70de3533e93", "0x4c58e7fac79e754d", "0x4c6ce1acd35693f6", "0x9c356bcd5f1d4639", "0x29361be2e3fa88ef", "0x8a1878dfba4b4637", "0x9289b157d1a01a8c",
|
||||
"0x70a4b5646d471b8e", "0xcf1595ab96209aa0", "0xe83503a00680799a", "0x7c1179b26025fcb4", "0x5a7aa05cd428f182", "0x02466e4a89473e34", "0xbd379fafb5889dee", "0x914679b7d4a92ece",
|
||||
"0x71b1611d70b03bd4", "0x9b6ec7ca5afd24db", "0x955f2305b288ef17", "0x456aeb62e25e0a8c", "0x40724ed4d6c72cc7", "0xf520227cecca4067", "0x92146b6c5d82408f", "0xbacdfeaa3693bba5",
|
||||
"0xb50a632febcaff29", "0x60bfffcb8b540752", "0x3eb9dbc42fc7b9d9", "0x73fd73c129763cd9", "0x701a9ec7130c5833", "0x02845e3260dbb636", "0x3b15ad42edfd3e74", "0x531d777ef600ee58"
|
||||
"0x039cc30b8c031a48", "0xf9bfd6b480657c03", "0xaf13478481593783", "0x872ea5b7d73b8925", "0x889bfedd51045247", "0xe1ab81c6dcd69ff3", "0x2507dd502da1b9da", "0x7567a01889f83134",
|
||||
"0xde7d8f2cac60920e", "0x0e0a63d966799441", "0x9d98775713c4a0e4", "0x47209fdd7ae001b7", "0x05c0d79abf0af16d", "0xb94aa6292dd13bbc", "0x63cb6d147242c41d", "0x2ea7910c292d7444",
|
||||
"0xdd482ea897c1996e", "0xe84344303344b919", "0xe82c94a23d2bfba5", "0xe9d885013e70dcec", "0xc4bb99afe28e20a5", "0x3f176b1b1ec2d0fc", "0xd192d3f4b4198535", "0x7efd10fb18a3aed8",
|
||||
"0x2aae74311fd49683", "0x84d188bc8cf911ab", "0x692d0a7500eed484", "0x227b6a6a62221e2c", "0x6e7d05153c894e6f", "0x33e8b228c6751367", "0xbaa37d348728a2e8", "0x518f7da3478e7e74"
|
||||
]},
|
||||
{"base_nonce": 1000000, "expected": [
|
||||
"0xde8458bcb18fb637", "0x0206b58b1f067ff0", "0xe107cdd0e87d28ae", "0x49fef7f22bc586d4", "0xff64163d017070cc", "0x968adfe921ccec1b", "0xe9560f8a3fa830da", "0x5d6f239c97224957",
|
||||
"0xcc2f980c31f7c7e5", "0x4d7cd09c7b731241", "0x5b1841dcfa517b45", "0xabd19c355dd4723f", "0x316eaf5ba7e30331", "0xec8156a374468b8d", "0x0e3505a1ec9fe2a1", "0x5f1f5a94a69a1178",
|
||||
"0xd4e6f7fda43c5056", "0x5ce560511eddb335", "0x88180b5ce94621cf", "0xb1095ce2dc071b55", "0xded0110936b4cf80", "0x43d2bbff72e231bc", "0xdd2bae28dbc4a9fe", "0x1c5055680fc7bca6",
|
||||
"0x1917e8e4e79db0ad", "0xb4f64af4d8f8a7c2", "0xd6df5b0607279b60", "0x3da81ec2899f8314", "0x384c998c46ab8b80", "0x7c8ada8b7ca44cd5", "0x1346a6394b7e4e05", "0x4e9868001eb79a14"
|
||||
"0xff3704a4b4a39d74", "0x67ce2a95ff7f485e", "0x0bc692d8d7c4b47b", "0x91713025b7bfdad7", "0x01e28c92dacef958", "0xbe8d553dd7e4c987", "0x34ce4c7529ec9b1a", "0xe2b3cbde7b2ff12e",
|
||||
"0xe05d9ff4895ab93e", "0x09654827998a3e1a", "0xd12e8d8776c76dad", "0x96b916349effd9cf", "0x6bf979214e05b755", "0x3082bfd6379b2b4d", "0x283bec328ba13c9d", "0x9f1b34dd7d719254",
|
||||
"0x62429fc39f085fa0", "0x8e0e3bf0a74eab65", "0x12c89e7a7f7e27a3", "0xf4685da8ff6d84a6", "0xd2ac7b54e4f6ec1a", "0x8bdf7f5fa3c211b1", "0x2cf20f105f8fd9f4", "0xd838f3668d715762",
|
||||
"0x3cecb064b01bb2d6", "0x07a6fb3335e1f1aa", "0x3d46b9036720b74a", "0xeb6a68cdbc2a4efc", "0xab1b29e32b4b9c37", "0x8023aae06ffaa42b", "0x1a9eb7b38f4aa48e", "0x21ee84e150b406a8"
|
||||
]}
|
||||
],
|
||||
"dataset_head": ["0x19c6837f", "0xdf3adfb8", "0xbd3f6aed", "0xb8bede0d", "0xc5f0629f", "0x03e38ae8", "0xc435a60e", "0xfadee916", "0x827e59af", "0x8cf592f5", "0x60286061", "0x5d9abc1c", "0xa85d0c39", "0x4247a100", "0xd41a5b0d", "0x3f33dc64"],
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -87,9 +87,9 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -102,26 +102,26 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
@ -577,7 +577,7 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -593,9 +593,9 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -608,26 +608,26 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -64,9 +64,9 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -79,26 +79,26 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
#define IGNEUM_GENERATOR 4
|
||||
#define IGNEUM_PROGRAM_ATTEMPT 0
|
||||
#define IGNEUM_PROGRAM_ID 0xc120d7963abdcd96ull
|
||||
#define IGNEUM_PROGRAM_ID 0x1a4230699a6b9c60ull
|
||||
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY0 0xceed56d7u
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
// latency-shadow block (IGNEUM_SHADOW_INSTRS x IGNEUM_SHADOW_REPS per iteration); a worker that runs another class
|
||||
// refuses this pack, and a job line names the class it wants (class=v4 era=<hex>).
|
||||
#define IGNEUM_PROGRAM_CLASS "v4"
|
||||
#define IGNEUM_PROGRAM_SUBVERSION 1
|
||||
#define IGNEUM_ERA_SEED_HEX "ff87ad96a1b53f367a95d5ca123bab64211bd9aa57fc7ad3c5e2d496c20138d4"
|
||||
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
|
||||
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
"format": "igneum-program-pack-3",
|
||||
"generator": 4,
|
||||
"attempt": 0,
|
||||
"program_id": "0xc120d7963abdcd96",
|
||||
"program_id": "0x1a4230699a6b9c60",
|
||||
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
|
||||
"dataset_mode": "memory-hard",
|
||||
"seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000",
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
"instruction_count": 64,
|
||||
"loads_per_hash": 128,
|
||||
"program_class": "v4",
|
||||
"sub_version": 1,
|
||||
"era_seed_bytes": "ff87ad96a1b53f367a95d5ca123bab64211bd9aa57fc7ad3c5e2d496c20138d4",
|
||||
"load_class": "mx8-era676a17fc+sh256x27",
|
||||
"mixer_mult": 8,
|
||||
|
|
@ -350,7 +351,7 @@
|
|||
{"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -366,9 +367,9 @@
|
|||
{"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 6, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 4, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -381,25 +382,25 @@
|
|||
{"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 2, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 0, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 4, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 7, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 2, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -67,9 +67,9 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -82,26 +82,26 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -69,9 +69,9 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -84,26 +84,26 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0xb2a9d70du, 6u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0xb2a9d70du, 6u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@
|
|||
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
|
||||
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
|
||||
{ // base nonce 0
|
||||
0xbd25be585e9f483aull, 0x42415dc1008bc167ull, 0x808b481a2ba0ee31ull, 0x9482f0d11a102aacull, 0xc8782e4fbd38f71dull, 0xbef02f6193c78dfeull, 0xf790061d0baf0ee2ull, 0x8df707bfebbb5266ull,
|
||||
0xd47ebe3648c32aa3ull, 0x8e337e0d74000f5full, 0xa2c1dfcf9bfd9b2bull, 0xbdc82bdf98d937e5ull, 0x6d8c6d41b0556cf1ull, 0x170c6a842bd29f8cull, 0x7cbb60763f8211e9ull, 0x091ae60c8df77ff1ull,
|
||||
0x85a309968b859efaull, 0xf917cf6f7e727926ull, 0xfa93a9f444db6381ull, 0x7ce089b8173f1af8ull, 0xdd4a1af297ec79f9ull, 0x3a1b907f25b76559ull, 0x5961a512eae86334ull, 0xf424423457ea3765ull,
|
||||
0x29c91de1b47e5cc1ull, 0x42dbeea9049ee394ull, 0xf1e5b7db42c969fcull, 0x05bd552362270025ull, 0xcc9d52e46c34e222ull, 0xea7a8dd12d9b5215ull, 0xb3767e4e3995df68ull, 0xe8ef919d038d88c5ull
|
||||
0xd71a9c938925ffc5ull, 0xe2068ed9973175b1ull, 0x53bf04769201d336ull, 0x692097e2c3a02e1aull, 0x4acc97ef5dd45cf2ull, 0x7aacd03e92bbd42bull, 0xcccef5441db823eeull, 0xa72fe9be1bf16bd1ull,
|
||||
0xdc1f90c1e2b4c1e0ull, 0x1225647be8a9ebe9ull, 0x13b68a6a501bbc8eull, 0xdf37aa95d989e077ull, 0x564bd0cc60c1f480ull, 0x2f550067c5c93d85ull, 0x13967e860eac50a2ull, 0xec28d64f290f0469ull,
|
||||
0x5e82470b3e5c1382ull, 0xeb810b7c8ba35882ull, 0x02dcbd3398745ef5ull, 0x42f89421a1bc4315ull, 0x8759dd657c5fa7aaull, 0x732f1eb6bbcc89dcull, 0xd603786d926cf2e5ull, 0xd3dbea210ef741b0ull,
|
||||
0x5acb31140b361861ull, 0x443866341fdb192dull, 0x3ad20321f5fc9739ull, 0x4c80c5b3d7ccf241ull, 0x31a80291eb23d585ull, 0xcab09df2c82b4800ull, 0x1f0b11eee15db929ull, 0x9dffa7b7c2cd0ddfull
|
||||
},
|
||||
{ // base nonce 4096
|
||||
0x3f56bb1287c456ceull, 0x82ea484e42cdc735ull, 0xf23918f44eb4b16bull, 0x35fa0e1461907922ull, 0x8f5ce24039e15677ull, 0xacd1c99175c3d7ecull, 0xd178a7b614ed8146ull, 0x47f918cfd5054696ull,
|
||||
0xc563739e8a6f80edull, 0x9e60aeeb9ca06c4eull, 0x857d4b51b3d98e10ull, 0xfaf2d0a4f79095ebull, 0x0b71b8fc789ac2ecull, 0x43a232348714b127ull, 0x285acfdac594da71ull, 0x3a7b88c3ce2b8072ull,
|
||||
0xa42762355d7a0a94ull, 0x12a5093c741ccfabull, 0x1c9132a046e1ca9full, 0xe88f10a778a1aabeull, 0xb54049c213699dc2ull, 0x3bb616b0bffda6b0ull, 0x2d2f0a25b94ecb3eull, 0x38c41e74a75e5921ull,
|
||||
0x631515adfa1edd4full, 0x80a01b3952ea1c95ull, 0x00afd63a2d4afcc2ull, 0x00fa1532253d3ea2ull, 0x76a824e91f58ad63ull, 0x15f3aa3ce283008bull, 0x8c4593b01e90cf5bull, 0x9b772227f63f5c1dull
|
||||
0xfc3d10a85cc5ce73ull, 0xd257f42d9fffc2a7ull, 0xb0b0065f25077172ull, 0x18b19b153e1e4240ull, 0x73bed5b1d3a47f4eull, 0x53ba261c0bfb9e5full, 0xedce185f5aaa1ec9ull, 0x9682fe851d8a7a1cull,
|
||||
0x594f71d3527835ecull, 0xb89b599b249bb490ull, 0xfca03d106efbf8bbull, 0xdbaba87c5269d5a3ull, 0x71f07379c3c2cf84ull, 0xb1605dc3784fac57ull, 0xfe5279a927fcbaa9ull, 0xa432c36395ae21e3ull,
|
||||
0x96760abd985c2a8dull, 0xafdb18def7e83f04ull, 0xf8b684dd887be464ull, 0x0409eb13a8c9b719ull, 0x3596c63a5bc1e647ull, 0x968e62e10bd4edc2ull, 0xf114d327832cdb98ull, 0xcf3f82e413c86937ull,
|
||||
0xd03e55ac5b486972ull, 0x8a89b8420ef05ca0ull, 0x789fd563db56779dull, 0x6d421d92c32f5817ull, 0x50f1c0278d793854ull, 0xac0e75d4e1d570a4ull, 0x183ef024ef55febcull, 0x7c43d95124150b23ull
|
||||
},
|
||||
{ // base nonce 1000000
|
||||
0xffc8d9c97d88e620ull, 0x1d7ee1acd496f181ull, 0xdff243b4a319c51aull, 0x1fd170c09f160fe3ull, 0xf67e0b69767852b0ull, 0x472912b4be99cdcdull, 0x5fad91fd832b3b61ull, 0xa5c9c1359d6aa74eull,
|
||||
0x6954523bb04ee9afull, 0xb048141f79726eb7ull, 0xe0c3182a16efb402ull, 0x39a09b038893b946ull, 0x2755e09f37d5efe2ull, 0x1e3338adcbbbaa5eull, 0x9036ec64d8816dbeull, 0xb6f6ffa4a73b774eull,
|
||||
0x514532b888255135ull, 0xc201f3dad4148ea0ull, 0x48cbcb6a4c9ba357ull, 0xf199b90384342df7ull, 0x9657e131356782d8ull, 0x5aa6f64a15b174f9ull, 0x6442f6fc30cd2f6cull, 0xdbd16862aff1b9b5ull,
|
||||
0xf62576ff01a1e6d6ull, 0xc3f654831ee4d08full, 0xbbe065fb2695bdffull, 0x1b9851d988309c48ull, 0x8474d21940bcc812ull, 0xa90030c199ad1c6bull, 0xb0752b8985cb7723ull, 0x2e5049d028c84c43ull
|
||||
0x0c0fd4bf3ba9ebd8ull, 0xa3c8d78474ec5dcfull, 0x28333f922209fad1ull, 0x0e15b3e0995e2ca9ull, 0xb0967681c36eb5deull, 0xbbc1e57ae64565a2ull, 0x6a91b4a3a6edcbb9ull, 0x3509e92f541acba2ull,
|
||||
0x5fadee87d1501340ull, 0x35e27ab61631cb03ull, 0x22022df945199137ull, 0x71b5c4d85fe4ee45ull, 0xf24af5e76a9b1bb9ull, 0xf6990011b3789453ull, 0xe6baa4d5afe8eeb3ull, 0xe04f6cee293a3f16ull,
|
||||
0x2becc5d55390595dull, 0x3f20d8bc7d2be74cull, 0xf37637a3a86909ffull, 0x399ff1a872b187eaull, 0x53d02cfc83562378ull, 0x0bf3ca7e0407b8daull, 0x5f8604b7f2c64f82ull, 0xd28865d9c1680184ull,
|
||||
0x88b8d07d2efd810cull, 0xa5f681e6857afe09ull, 0x3cb93a309b4885c6ull, 0x924ff9a6c6cecc50ull, 0x74fe2925e0abee88ull, 0x434871c5b84af89dull, 0x6ecf62d69b8eb98full, 0xdb4cdab409bc66ecull
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,22 +8,22 @@
|
|||
"source": "igneum-pow (Rust) CPU interpreter, generator v4, memory-hard dataset",
|
||||
"warps": [
|
||||
{"base_nonce": 0, "expected": [
|
||||
"0xbd25be585e9f483a", "0x42415dc1008bc167", "0x808b481a2ba0ee31", "0x9482f0d11a102aac", "0xc8782e4fbd38f71d", "0xbef02f6193c78dfe", "0xf790061d0baf0ee2", "0x8df707bfebbb5266",
|
||||
"0xd47ebe3648c32aa3", "0x8e337e0d74000f5f", "0xa2c1dfcf9bfd9b2b", "0xbdc82bdf98d937e5", "0x6d8c6d41b0556cf1", "0x170c6a842bd29f8c", "0x7cbb60763f8211e9", "0x091ae60c8df77ff1",
|
||||
"0x85a309968b859efa", "0xf917cf6f7e727926", "0xfa93a9f444db6381", "0x7ce089b8173f1af8", "0xdd4a1af297ec79f9", "0x3a1b907f25b76559", "0x5961a512eae86334", "0xf424423457ea3765",
|
||||
"0x29c91de1b47e5cc1", "0x42dbeea9049ee394", "0xf1e5b7db42c969fc", "0x05bd552362270025", "0xcc9d52e46c34e222", "0xea7a8dd12d9b5215", "0xb3767e4e3995df68", "0xe8ef919d038d88c5"
|
||||
"0xd71a9c938925ffc5", "0xe2068ed9973175b1", "0x53bf04769201d336", "0x692097e2c3a02e1a", "0x4acc97ef5dd45cf2", "0x7aacd03e92bbd42b", "0xcccef5441db823ee", "0xa72fe9be1bf16bd1",
|
||||
"0xdc1f90c1e2b4c1e0", "0x1225647be8a9ebe9", "0x13b68a6a501bbc8e", "0xdf37aa95d989e077", "0x564bd0cc60c1f480", "0x2f550067c5c93d85", "0x13967e860eac50a2", "0xec28d64f290f0469",
|
||||
"0x5e82470b3e5c1382", "0xeb810b7c8ba35882", "0x02dcbd3398745ef5", "0x42f89421a1bc4315", "0x8759dd657c5fa7aa", "0x732f1eb6bbcc89dc", "0xd603786d926cf2e5", "0xd3dbea210ef741b0",
|
||||
"0x5acb31140b361861", "0x443866341fdb192d", "0x3ad20321f5fc9739", "0x4c80c5b3d7ccf241", "0x31a80291eb23d585", "0xcab09df2c82b4800", "0x1f0b11eee15db929", "0x9dffa7b7c2cd0ddf"
|
||||
]},
|
||||
{"base_nonce": 4096, "expected": [
|
||||
"0x3f56bb1287c456ce", "0x82ea484e42cdc735", "0xf23918f44eb4b16b", "0x35fa0e1461907922", "0x8f5ce24039e15677", "0xacd1c99175c3d7ec", "0xd178a7b614ed8146", "0x47f918cfd5054696",
|
||||
"0xc563739e8a6f80ed", "0x9e60aeeb9ca06c4e", "0x857d4b51b3d98e10", "0xfaf2d0a4f79095eb", "0x0b71b8fc789ac2ec", "0x43a232348714b127", "0x285acfdac594da71", "0x3a7b88c3ce2b8072",
|
||||
"0xa42762355d7a0a94", "0x12a5093c741ccfab", "0x1c9132a046e1ca9f", "0xe88f10a778a1aabe", "0xb54049c213699dc2", "0x3bb616b0bffda6b0", "0x2d2f0a25b94ecb3e", "0x38c41e74a75e5921",
|
||||
"0x631515adfa1edd4f", "0x80a01b3952ea1c95", "0x00afd63a2d4afcc2", "0x00fa1532253d3ea2", "0x76a824e91f58ad63", "0x15f3aa3ce283008b", "0x8c4593b01e90cf5b", "0x9b772227f63f5c1d"
|
||||
"0xfc3d10a85cc5ce73", "0xd257f42d9fffc2a7", "0xb0b0065f25077172", "0x18b19b153e1e4240", "0x73bed5b1d3a47f4e", "0x53ba261c0bfb9e5f", "0xedce185f5aaa1ec9", "0x9682fe851d8a7a1c",
|
||||
"0x594f71d3527835ec", "0xb89b599b249bb490", "0xfca03d106efbf8bb", "0xdbaba87c5269d5a3", "0x71f07379c3c2cf84", "0xb1605dc3784fac57", "0xfe5279a927fcbaa9", "0xa432c36395ae21e3",
|
||||
"0x96760abd985c2a8d", "0xafdb18def7e83f04", "0xf8b684dd887be464", "0x0409eb13a8c9b719", "0x3596c63a5bc1e647", "0x968e62e10bd4edc2", "0xf114d327832cdb98", "0xcf3f82e413c86937",
|
||||
"0xd03e55ac5b486972", "0x8a89b8420ef05ca0", "0x789fd563db56779d", "0x6d421d92c32f5817", "0x50f1c0278d793854", "0xac0e75d4e1d570a4", "0x183ef024ef55febc", "0x7c43d95124150b23"
|
||||
]},
|
||||
{"base_nonce": 1000000, "expected": [
|
||||
"0xffc8d9c97d88e620", "0x1d7ee1acd496f181", "0xdff243b4a319c51a", "0x1fd170c09f160fe3", "0xf67e0b69767852b0", "0x472912b4be99cdcd", "0x5fad91fd832b3b61", "0xa5c9c1359d6aa74e",
|
||||
"0x6954523bb04ee9af", "0xb048141f79726eb7", "0xe0c3182a16efb402", "0x39a09b038893b946", "0x2755e09f37d5efe2", "0x1e3338adcbbbaa5e", "0x9036ec64d8816dbe", "0xb6f6ffa4a73b774e",
|
||||
"0x514532b888255135", "0xc201f3dad4148ea0", "0x48cbcb6a4c9ba357", "0xf199b90384342df7", "0x9657e131356782d8", "0x5aa6f64a15b174f9", "0x6442f6fc30cd2f6c", "0xdbd16862aff1b9b5",
|
||||
"0xf62576ff01a1e6d6", "0xc3f654831ee4d08f", "0xbbe065fb2695bdff", "0x1b9851d988309c48", "0x8474d21940bcc812", "0xa90030c199ad1c6b", "0xb0752b8985cb7723", "0x2e5049d028c84c43"
|
||||
"0x0c0fd4bf3ba9ebd8", "0xa3c8d78474ec5dcf", "0x28333f922209fad1", "0x0e15b3e0995e2ca9", "0xb0967681c36eb5de", "0xbbc1e57ae64565a2", "0x6a91b4a3a6edcbb9", "0x3509e92f541acba2",
|
||||
"0x5fadee87d1501340", "0x35e27ab61631cb03", "0x22022df945199137", "0x71b5c4d85fe4ee45", "0xf24af5e76a9b1bb9", "0xf6990011b3789453", "0xe6baa4d5afe8eeb3", "0xe04f6cee293a3f16",
|
||||
"0x2becc5d55390595d", "0x3f20d8bc7d2be74c", "0xf37637a3a86909ff", "0x399ff1a872b187ea", "0x53d02cfc83562378", "0x0bf3ca7e0407b8da", "0x5f8604b7f2c64f82", "0xd28865d9c1680184",
|
||||
"0x88b8d07d2efd810c", "0xa5f681e6857afe09", "0x3cb93a309b4885c6", "0x924ff9a6c6cecc50", "0x74fe2925e0abee88", "0x434871c5b84af89d", "0x6ecf62d69b8eb98f", "0xdb4cdab409bc66ec"
|
||||
]}
|
||||
],
|
||||
"dataset_head": ["0x19c6837f", "0xbd3f6aed", "0xdf3adfb8", "0xb8bede0d", "0x827e59af", "0x60286061", "0x8cf592f5", "0x5d9abc1c", "0xc5f0629f", "0xc435a60e", "0x03e38ae8", "0xfadee916", "0xa85d0c39", "0xd41a5b0d", "0x4247a100", "0x3f33dc64"],
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -87,9 +87,9 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -102,26 +102,26 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
@ -577,7 +577,7 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -593,9 +593,9 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -608,26 +608,26 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -64,9 +64,9 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -79,26 +79,26 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
#define IGNEUM_GENERATOR 4
|
||||
#define IGNEUM_PROGRAM_ATTEMPT 0
|
||||
#define IGNEUM_PROGRAM_ID 0xc120d7963abdcd96ull
|
||||
#define IGNEUM_PROGRAM_ID 0x1a4230699a6b9c60ull
|
||||
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY0 0xceed56d7u
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
// latency-shadow block (IGNEUM_SHADOW_INSTRS x IGNEUM_SHADOW_REPS per iteration); a worker that runs another class
|
||||
// refuses this pack, and a job line names the class it wants (class=v4 era=<hex>).
|
||||
#define IGNEUM_PROGRAM_CLASS "v4"
|
||||
#define IGNEUM_PROGRAM_SUBVERSION 1
|
||||
#define IGNEUM_ERA_SEED_HEX "df57136f2ad5f410e6145023090eea148c1342ccef5a5f541afa590be7e44745"
|
||||
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
|
||||
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
"format": "igneum-program-pack-3",
|
||||
"generator": 4,
|
||||
"attempt": 0,
|
||||
"program_id": "0xc120d7963abdcd96",
|
||||
"program_id": "0x1a4230699a6b9c60",
|
||||
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
|
||||
"dataset_mode": "memory-hard",
|
||||
"seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000",
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
"instruction_count": 64,
|
||||
"loads_per_hash": 128,
|
||||
"program_class": "v4",
|
||||
"sub_version": 1,
|
||||
"era_seed_bytes": "df57136f2ad5f410e6145023090eea148c1342ccef5a5f541afa590be7e44745",
|
||||
"load_class": "mx8-era843155d7+sh256x27",
|
||||
"mixer_mult": 8,
|
||||
|
|
@ -350,7 +351,7 @@
|
|||
{"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -366,9 +367,9 @@
|
|||
{"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 6, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 4, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -381,25 +382,25 @@
|
|||
{"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 2, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 0, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 4, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 7, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 2, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -67,9 +67,9 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -82,26 +82,26 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -69,9 +69,9 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -84,26 +84,26 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x2b4a5b97u, 28u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x2b4a5b97u, 28u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@
|
|||
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
|
||||
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
|
||||
{ // base nonce 0
|
||||
0xd15f7638ecab0638ull, 0xf71dc04ca33f9049ull, 0xdda27e825b83045full, 0x0babd54b6eb42cb6ull, 0x22b4cafe1d3a82d7ull, 0x1ded091e583999c8ull, 0x9445769b44b82cbdull, 0xbd850d3ec7937586ull,
|
||||
0xd503809c85e89628ull, 0xe1c06157f7c30353ull, 0xd60623d3d7eea552ull, 0x7d893fab4009c4d4ull, 0xa153fbc5e57b66a5ull, 0xd60055d442ad5f10ull, 0xd68537a9835ef4d5ull, 0xf904817a6a8188d3ull,
|
||||
0x024eef8355667005ull, 0x498b0d273a1f70d3ull, 0x04719bd1c8633f5bull, 0x153f8f65912540caull, 0x5d19c2cb32a9be86ull, 0x68a1791304d4c616ull, 0x65cee64ecdd50cf8ull, 0xd14b2d91df1e6c36ull,
|
||||
0x0a9f67bd86a20bcaull, 0x99068e67d3d9da10ull, 0x84c845b2f4a99b52ull, 0xb2d622100c4cb3c9ull, 0x312854dbc455f269ull, 0x6bfd7d56844bd049ull, 0x654be06144c8aaabull, 0xb97c033d13ff45b9ull
|
||||
0xa50fd84e469c0299ull, 0x956a02cc6e55e39bull, 0xcff98bd1ba125752ull, 0xfd349e2bf2f95bf0ull, 0xa23ab74a855d48aeull, 0x458cfd86913fe839ull, 0x4fc6bead2a788db4ull, 0x41f36429a69d0572ull,
|
||||
0x7db8bc5d0c153350ull, 0xf2e335084a646321ull, 0x14051b39d8eff830ull, 0x55605759b5fd1407ull, 0x833a24b656a37de7ull, 0xc7c10530d9b2771eull, 0xd52124942abf9662ull, 0x0832ecb41cb3f419ull,
|
||||
0x1b5b65afb35e979cull, 0x3fe3dc64a66f0c98ull, 0x8b0593a03d879943ull, 0x4d07ac8898ea5099ull, 0x0e1e7e456d0bde69ull, 0x07169a25e5e94c3dull, 0x0dbdec2f9a6271f0ull, 0x0fad105f526a4113ull,
|
||||
0x25476fe23461e7eaull, 0xd5cdecbab3c48dfeull, 0xff63fa1aa4ed8e17ull, 0x5e514d66699dcafdull, 0xd0e26e96e4906d4eull, 0xf65f5cd6b3c031cdull, 0x704eeffeff76efceull, 0xb55b9666e0e0ba2eull
|
||||
},
|
||||
{ // base nonce 4096
|
||||
0xca511aa94bb7de28ull, 0xf50562fbd930d7cbull, 0x90d1d21d286f4526ull, 0xf7dd004498042c76ull, 0x4015a3dedf539b30ull, 0xbf188aa13bf0d0b0ull, 0x3562a5190ceb5c0eull, 0x6d8fc479c085e14bull,
|
||||
0x0c028bae78f97b7aull, 0x83438623fdef4ab5ull, 0x12d046bb02e00e62ull, 0x70ec066026f7e35aull, 0x593aa049f2d1a94aull, 0x8ca00d8f621627adull, 0x6e1ca47c67a11a4aull, 0x44b0e6fba37093ceull,
|
||||
0x26557f61f6b46af6ull, 0xa8fb8acbd4f447f9ull, 0x8b5d5d8fea192771ull, 0x05319f2d2a379723ull, 0xea48c6831e5c4e09ull, 0x77dc8af07fbffad6ull, 0xf73f12c67ee72439ull, 0xbd6ca871de1f5a15ull,
|
||||
0xfa023ce22a449fcdull, 0x4d10b2e249f230c7ull, 0x8eb20cbc44bb4cd3ull, 0x0f6a25ef75994a9cull, 0xf3e2b830c7268634ull, 0xbb9b9d9cb45a3ba7ull, 0xe1a7cfda15d5d859ull, 0x469597ce101451dcull
|
||||
0x78d57bbfd2640ee5ull, 0xcd26544ec614acc0ull, 0x9a930f1faa1c820bull, 0x5bfeb2782647ac97ull, 0x8ef56bc0d1957fc3ull, 0x51b67fce32055b2cull, 0xa7958e73431bc372ull, 0x20a0384a77190463ull,
|
||||
0xdbc235471dc95936ull, 0x257d434ad4569f03ull, 0xe0e8b08d3c1f8cbdull, 0x2c1a7374af2fe448ull, 0x182975ab5388ca07ull, 0xe28f02e67a3a6322ull, 0x22a5af1129deb478ull, 0x8ada05248b23a133ull,
|
||||
0x9f8b35c661edb718ull, 0x971c5ffc24662e31ull, 0xb08be1b74e69b848ull, 0xa9e0f65de4cbfa1bull, 0x284c3612c569233aull, 0xb7fa4ffbdb36a5bcull, 0xba5c01642ad7e8e1ull, 0x7f1bf5cd0e5cb632ull,
|
||||
0x90a29a6014616cacull, 0x0b0205b1dbbe18c2ull, 0x0d264313d0921abfull, 0xc94597b61719f39full, 0x91890e2a6ff436d7ull, 0xe13596e45c56318dull, 0x750df0b43006dba1ull, 0x470bcdde541c43e1ull
|
||||
},
|
||||
{ // base nonce 1000000
|
||||
0x1b69d837d0e478f9ull, 0x7f4ea76a066e3abfull, 0x877d6e73bc9d55eeull, 0x2ce7115def57d121ull, 0xbaa9996f8db3a59full, 0xaf8f831594ef4cfbull, 0x7e15598c87bd4319ull, 0x5dbf2e8fe7d65335ull,
|
||||
0x69de5134b0e4260eull, 0x48f3865c27bdf852ull, 0xe470c56ea8799783ull, 0x3d99bbf38de6d92full, 0x16355adc8947980full, 0xeaf478e9b3c281e9ull, 0x64ad42cd95af5cb0ull, 0x8f3042a5ae75653full,
|
||||
0x5bd477dc9ace031bull, 0xe49671e0b12b9c88ull, 0xc2af87b389841379ull, 0x5f24587ff2b07510ull, 0xec5862ebad445432ull, 0x53a1995450693ed4ull, 0x62dacf7f2f8020cdull, 0x30cb5459c52a6779ull,
|
||||
0x616ba82cf713a033ull, 0x2ab4f3fc72d72c9eull, 0xd095040ca4fd494dull, 0x9cbf315db4bee964ull, 0xb3288c63109bd0d5ull, 0x7a8122aca003c5c5ull, 0x5e7054016621ab58ull, 0x116981c856dd2a2dull
|
||||
0xb763a5e3ff117e76ull, 0x3908a3516a0c716dull, 0xa126e19fe2d95edcull, 0x396a194582db520cull, 0x8dc2b83423861f29ull, 0xfd6c8913ee257ff5ull, 0xfdebf75bfd35e456ull, 0x44d41b818c660f54ull,
|
||||
0x7f9a83b8e543d325ull, 0xe81f73cc9c1ea9c3ull, 0x5f2cf4556e5f8426ull, 0x600c60bf03182500ull, 0x1d344ca28ebef75cull, 0xc68ba93ff35c8feaull, 0x73cfc027eeb5538cull, 0x5e8a88ffd4b73153ull,
|
||||
0x1ed548903f93eac5ull, 0x27085af02aaa8062ull, 0x92b54202359248c5ull, 0xda425e78da758280ull, 0x125471a0bc0b61ceull, 0x26efb3377cec9defull, 0x6bdb7cf1a5da7220ull, 0x0070ecdf0e84c654ull,
|
||||
0xd1b226f4e2eee520ull, 0xb7b13401ffb86790ull, 0x4e2671612852437eull, 0xac55e4a97dad8599ull, 0x269a53ab8606b40eull, 0x42100137c8e7cc3dull, 0x3e8a12ada77f5dfaull, 0x94306761f26d1768ull
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,22 +8,22 @@
|
|||
"source": "igneum-pow (Rust) CPU interpreter, generator v4, memory-hard dataset",
|
||||
"warps": [
|
||||
{"base_nonce": 0, "expected": [
|
||||
"0xd15f7638ecab0638", "0xf71dc04ca33f9049", "0xdda27e825b83045f", "0x0babd54b6eb42cb6", "0x22b4cafe1d3a82d7", "0x1ded091e583999c8", "0x9445769b44b82cbd", "0xbd850d3ec7937586",
|
||||
"0xd503809c85e89628", "0xe1c06157f7c30353", "0xd60623d3d7eea552", "0x7d893fab4009c4d4", "0xa153fbc5e57b66a5", "0xd60055d442ad5f10", "0xd68537a9835ef4d5", "0xf904817a6a8188d3",
|
||||
"0x024eef8355667005", "0x498b0d273a1f70d3", "0x04719bd1c8633f5b", "0x153f8f65912540ca", "0x5d19c2cb32a9be86", "0x68a1791304d4c616", "0x65cee64ecdd50cf8", "0xd14b2d91df1e6c36",
|
||||
"0x0a9f67bd86a20bca", "0x99068e67d3d9da10", "0x84c845b2f4a99b52", "0xb2d622100c4cb3c9", "0x312854dbc455f269", "0x6bfd7d56844bd049", "0x654be06144c8aaab", "0xb97c033d13ff45b9"
|
||||
"0xa50fd84e469c0299", "0x956a02cc6e55e39b", "0xcff98bd1ba125752", "0xfd349e2bf2f95bf0", "0xa23ab74a855d48ae", "0x458cfd86913fe839", "0x4fc6bead2a788db4", "0x41f36429a69d0572",
|
||||
"0x7db8bc5d0c153350", "0xf2e335084a646321", "0x14051b39d8eff830", "0x55605759b5fd1407", "0x833a24b656a37de7", "0xc7c10530d9b2771e", "0xd52124942abf9662", "0x0832ecb41cb3f419",
|
||||
"0x1b5b65afb35e979c", "0x3fe3dc64a66f0c98", "0x8b0593a03d879943", "0x4d07ac8898ea5099", "0x0e1e7e456d0bde69", "0x07169a25e5e94c3d", "0x0dbdec2f9a6271f0", "0x0fad105f526a4113",
|
||||
"0x25476fe23461e7ea", "0xd5cdecbab3c48dfe", "0xff63fa1aa4ed8e17", "0x5e514d66699dcafd", "0xd0e26e96e4906d4e", "0xf65f5cd6b3c031cd", "0x704eeffeff76efce", "0xb55b9666e0e0ba2e"
|
||||
]},
|
||||
{"base_nonce": 4096, "expected": [
|
||||
"0xca511aa94bb7de28", "0xf50562fbd930d7cb", "0x90d1d21d286f4526", "0xf7dd004498042c76", "0x4015a3dedf539b30", "0xbf188aa13bf0d0b0", "0x3562a5190ceb5c0e", "0x6d8fc479c085e14b",
|
||||
"0x0c028bae78f97b7a", "0x83438623fdef4ab5", "0x12d046bb02e00e62", "0x70ec066026f7e35a", "0x593aa049f2d1a94a", "0x8ca00d8f621627ad", "0x6e1ca47c67a11a4a", "0x44b0e6fba37093ce",
|
||||
"0x26557f61f6b46af6", "0xa8fb8acbd4f447f9", "0x8b5d5d8fea192771", "0x05319f2d2a379723", "0xea48c6831e5c4e09", "0x77dc8af07fbffad6", "0xf73f12c67ee72439", "0xbd6ca871de1f5a15",
|
||||
"0xfa023ce22a449fcd", "0x4d10b2e249f230c7", "0x8eb20cbc44bb4cd3", "0x0f6a25ef75994a9c", "0xf3e2b830c7268634", "0xbb9b9d9cb45a3ba7", "0xe1a7cfda15d5d859", "0x469597ce101451dc"
|
||||
"0x78d57bbfd2640ee5", "0xcd26544ec614acc0", "0x9a930f1faa1c820b", "0x5bfeb2782647ac97", "0x8ef56bc0d1957fc3", "0x51b67fce32055b2c", "0xa7958e73431bc372", "0x20a0384a77190463",
|
||||
"0xdbc235471dc95936", "0x257d434ad4569f03", "0xe0e8b08d3c1f8cbd", "0x2c1a7374af2fe448", "0x182975ab5388ca07", "0xe28f02e67a3a6322", "0x22a5af1129deb478", "0x8ada05248b23a133",
|
||||
"0x9f8b35c661edb718", "0x971c5ffc24662e31", "0xb08be1b74e69b848", "0xa9e0f65de4cbfa1b", "0x284c3612c569233a", "0xb7fa4ffbdb36a5bc", "0xba5c01642ad7e8e1", "0x7f1bf5cd0e5cb632",
|
||||
"0x90a29a6014616cac", "0x0b0205b1dbbe18c2", "0x0d264313d0921abf", "0xc94597b61719f39f", "0x91890e2a6ff436d7", "0xe13596e45c56318d", "0x750df0b43006dba1", "0x470bcdde541c43e1"
|
||||
]},
|
||||
{"base_nonce": 1000000, "expected": [
|
||||
"0x1b69d837d0e478f9", "0x7f4ea76a066e3abf", "0x877d6e73bc9d55ee", "0x2ce7115def57d121", "0xbaa9996f8db3a59f", "0xaf8f831594ef4cfb", "0x7e15598c87bd4319", "0x5dbf2e8fe7d65335",
|
||||
"0x69de5134b0e4260e", "0x48f3865c27bdf852", "0xe470c56ea8799783", "0x3d99bbf38de6d92f", "0x16355adc8947980f", "0xeaf478e9b3c281e9", "0x64ad42cd95af5cb0", "0x8f3042a5ae75653f",
|
||||
"0x5bd477dc9ace031b", "0xe49671e0b12b9c88", "0xc2af87b389841379", "0x5f24587ff2b07510", "0xec5862ebad445432", "0x53a1995450693ed4", "0x62dacf7f2f8020cd", "0x30cb5459c52a6779",
|
||||
"0x616ba82cf713a033", "0x2ab4f3fc72d72c9e", "0xd095040ca4fd494d", "0x9cbf315db4bee964", "0xb3288c63109bd0d5", "0x7a8122aca003c5c5", "0x5e7054016621ab58", "0x116981c856dd2a2d"
|
||||
"0xb763a5e3ff117e76", "0x3908a3516a0c716d", "0xa126e19fe2d95edc", "0x396a194582db520c", "0x8dc2b83423861f29", "0xfd6c8913ee257ff5", "0xfdebf75bfd35e456", "0x44d41b818c660f54",
|
||||
"0x7f9a83b8e543d325", "0xe81f73cc9c1ea9c3", "0x5f2cf4556e5f8426", "0x600c60bf03182500", "0x1d344ca28ebef75c", "0xc68ba93ff35c8fea", "0x73cfc027eeb5538c", "0x5e8a88ffd4b73153",
|
||||
"0x1ed548903f93eac5", "0x27085af02aaa8062", "0x92b54202359248c5", "0xda425e78da758280", "0x125471a0bc0b61ce", "0x26efb3377cec9def", "0x6bdb7cf1a5da7220", "0x0070ecdf0e84c654",
|
||||
"0xd1b226f4e2eee520", "0xb7b13401ffb86790", "0x4e2671612852437e", "0xac55e4a97dad8599", "0x269a53ab8606b40e", "0x42100137c8e7cc3d", "0x3e8a12ada77f5dfa", "0x94306761f26d1768"
|
||||
]}
|
||||
],
|
||||
"dataset_head": ["0x19c6837f", "0xbd3f6aed", "0xdf3adfb8", "0xb8bede0d", "0x827e59af", "0x60286061", "0x8cf592f5", "0x5d9abc1c", "0xc5f0629f", "0xc435a60e", "0x03e38ae8", "0xfadee916", "0xa85d0c39", "0xd41a5b0d", "0x4247a100", "0x3f33dc64"],
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -87,9 +87,9 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -102,26 +102,26 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
@ -577,7 +577,7 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -593,9 +593,9 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -608,26 +608,26 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -64,9 +64,9 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -79,26 +79,26 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
#define IGNEUM_GENERATOR 4
|
||||
#define IGNEUM_PROGRAM_ATTEMPT 0
|
||||
#define IGNEUM_PROGRAM_ID 0xc120d7963abdcd96ull
|
||||
#define IGNEUM_PROGRAM_ID 0x1a4230699a6b9c60ull
|
||||
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY0 0xceed56d7u
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
// latency-shadow block (IGNEUM_SHADOW_INSTRS x IGNEUM_SHADOW_REPS per iteration); a worker that runs another class
|
||||
// refuses this pack, and a job line names the class it wants (class=v4 era=<hex>).
|
||||
#define IGNEUM_PROGRAM_CLASS "v4"
|
||||
#define IGNEUM_PROGRAM_SUBVERSION 1
|
||||
#define IGNEUM_ERA_SEED_HEX "e593fc1d48475c88e456632f6aa0a752a5fdbca3c33022afe37680e44b7dfd11"
|
||||
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
|
||||
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
"format": "igneum-program-pack-3",
|
||||
"generator": 4,
|
||||
"attempt": 0,
|
||||
"program_id": "0xc120d7963abdcd96",
|
||||
"program_id": "0x1a4230699a6b9c60",
|
||||
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
|
||||
"dataset_mode": "memory-hard",
|
||||
"seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000",
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
"instruction_count": 64,
|
||||
"loads_per_hash": 128,
|
||||
"program_class": "v4",
|
||||
"sub_version": 1,
|
||||
"era_seed_bytes": "e593fc1d48475c88e456632f6aa0a752a5fdbca3c33022afe37680e44b7dfd11",
|
||||
"load_class": "mx8-erad6367bfe+sh256x27",
|
||||
"mixer_mult": 8,
|
||||
|
|
@ -350,7 +351,7 @@
|
|||
{"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -366,9 +367,9 @@
|
|||
{"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 6, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 4, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -381,25 +382,25 @@
|
|||
{"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 2, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 0, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 4, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 7, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 2, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -67,9 +67,9 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -82,26 +82,26 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -69,9 +69,9 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -84,26 +84,26 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x27ea7effu, 30u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x27ea7effu, 30u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@
|
|||
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
|
||||
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
|
||||
{ // base nonce 0
|
||||
0x40b750d1c8a8070full, 0x0eabee774c28ab59ull, 0xcc13c43e53c39432ull, 0x6a9c15036cd8ea3eull, 0x33632873969d8edeull, 0x598d17a33791fdc9ull, 0x2eff1230b4254f1eull, 0xe94dd51fbd984bceull,
|
||||
0xb99fbeb7ee79e111ull, 0xf96bf58191e27007ull, 0x0d0eeb157f2fb140ull, 0xc63153f0272b9855ull, 0x73805af5544b3db0ull, 0x79c1b5a74c8560e9ull, 0x0ea9cca3277890e5ull, 0x1d176fab1cd2973aull,
|
||||
0x119ab8f645bf8a2dull, 0xf1c9b6889298e177ull, 0x46f901ebdb35452aull, 0x383a4d749d1ad0e8ull, 0xf4353dc68a21fac5ull, 0xa6c45db77d51deb9ull, 0x82603eb8e3a8df60ull, 0xf8245dd6e5b8de09ull,
|
||||
0x3c5ad35824c49228ull, 0xc2ea030a6104da05ull, 0x6059173f71a28844ull, 0x42356c03e7c14337ull, 0xe707beb14ff8afa9ull, 0x0d572180b81363b2ull, 0xbd4479364aaac437ull, 0x3e6fd0864a730c42ull
|
||||
0x37153bb806168fe2ull, 0x60f5c68f3450d761ull, 0xe58773158354763aull, 0xc982ec329d077c1bull, 0x9941a2b9c89196bdull, 0xd2b9fe1c2d2708b0ull, 0x1548e3bc5054162aull, 0x6c90433d112dc47dull,
|
||||
0x7103d3c3b6c356f0ull, 0x6d214d6bed92ea3bull, 0x68a576c3858eac19ull, 0x86c71bdb16dfc63dull, 0x75fbfb8841591f6aull, 0x62d2f7be3688f885ull, 0xb973b904cc383437ull, 0x30a6b60a33e5f513ull,
|
||||
0xf0cb3dbea6f9880cull, 0x8e3350ee3d5cf5efull, 0x280b6e74cf6f728dull, 0x7534c2cabcbd1a74ull, 0x4b1583c09489e3a3ull, 0x3664deb8ab165897ull, 0x129192db3d976bdfull, 0x903a6fe916f06f59ull,
|
||||
0x4bc03753c1d0f1ddull, 0xcbc8e21dcf41320dull, 0x5be555c4779de21full, 0x64edc870ef6605c3ull, 0x268a25f14b989ec3ull, 0xa27ab228fc882951ull, 0x668ab91ab515077bull, 0x6e5af942a42cca56ull
|
||||
},
|
||||
{ // base nonce 4096
|
||||
0x0db15f7c616f2d25ull, 0x17b04f540b4846d6ull, 0xcddd5a8ee8a5efe0ull, 0x0cf0cf62d997c83eull, 0xbd5b7795b4dbd26cull, 0x2d7b8aa0a985480full, 0x10d7689b878233c2ull, 0xbeed4790abb65517ull,
|
||||
0x22c14a4e0a10eeaeull, 0xcdfa941f2e7960f9ull, 0x879bf9554455ec49ull, 0x5cec926ae13470fdull, 0xad086583b0bccd24ull, 0xa76fa9afc7d6d9f8ull, 0x4dc4e1184adb00c8ull, 0x5410c5c88a875d85ull,
|
||||
0x6ba2aed6fc622330ull, 0x4664d893aac13b54ull, 0x94bca09b542c77b6ull, 0x7ac3a74d54d15c2eull, 0x8fd7503272ef64b9ull, 0xd9ffc122880e7432ull, 0xd232c638aba55395ull, 0xf25659961199829cull,
|
||||
0xe87691a335d4d5b4ull, 0xc24e26d570d76954ull, 0xc2bf85ff359b2121ull, 0xa4195d2eec65f9c8ull, 0x260b4f6b0a9b6138ull, 0x6b7082ed96379d93ull, 0x7a4d1e4f9cd0276bull, 0x90afe3c042fed6e2ull
|
||||
0x15aa64176be3d2b7ull, 0x796085991cf0bc36ull, 0x4159555ce699c553ull, 0x41b7db70937ebff1ull, 0xb7aa5d515f39e98aull, 0xbf65a44a7f9d28fbull, 0xcbe8a4ff4bc229a7ull, 0xb896d2ef4595ef45ull,
|
||||
0x4d95f8c4d3682289ull, 0x0e9238d0398c51a5ull, 0xc0071c186ac50324ull, 0x1677c4c8b8143a40ull, 0x7c468c9e658fbd7aull, 0x06f20ab8ff3145b5ull, 0x493dd3161e781c21ull, 0x183408bb838cc8dfull,
|
||||
0x9685a6f441083252ull, 0x6e67cbfa06e3e94full, 0x625e299810c789d9ull, 0x0ef9be59f2c83740ull, 0xcc9f24f893fbc87full, 0x2d92a13784beee93ull, 0xced96a43f0c3aec2ull, 0xd381e745a95e0106ull,
|
||||
0xe91284aab02ea04dull, 0x1600dcb649b27a02ull, 0x6fcee68b9137f52dull, 0x685bfbdaa2b30404ull, 0xd329c9bbda12bf0eull, 0xffdb6ba911480017ull, 0x8fe5930d6114ae5eull, 0x25c6e5a41abf3065ull
|
||||
},
|
||||
{ // base nonce 1000000
|
||||
0x06897e48ecfdf30dull, 0xc2407e8c2e0a6df7ull, 0xfc7b70f2531fc0efull, 0x747fb0709c82c21bull, 0x2c1b6c10825e53edull, 0x4fc0e3d09485cbc3ull, 0x36a8e3d8a83dcb87ull, 0xa9b04c51829184f8ull,
|
||||
0x16c05be25080fcbeull, 0x488eec7576d2a293ull, 0xab03139ccbf27fa0ull, 0x85246c99a37d87d0ull, 0x09b2c5ae915b6eafull, 0x8e0a34f2ec25ba0cull, 0xa5313b7d8a58e010ull, 0x8cb897eb47b626a6ull,
|
||||
0x3c06e7453858ef65ull, 0xcee4fc69243cbf1bull, 0xfe2f0b3329d6ef34ull, 0x3a19eccb6a374b0aull, 0xa8848523eb449ec3ull, 0xc84ea452644c79caull, 0x23f77955e2b1c1d8ull, 0x1ec75c6675ca3245ull,
|
||||
0xbe1c597e1dc237a3ull, 0x524841798abd82bcull, 0x21c1b17d075c9356ull, 0xbeea164bb5aed2faull, 0x7e8db3ca049cde0eull, 0x1a6f526d31708af9ull, 0x06096e878273cab7ull, 0x707399fc4e364b01ull
|
||||
0x4527f5599e3ef95full, 0x669c823cf598aa10ull, 0x0e0752b32f1a3b6cull, 0xbc1d131573a47fe6ull, 0x6016efeaccc5ad4eull, 0x73bde6a8fa03bb96ull, 0x9a0f79f0b5511922ull, 0x9058423b04f21c72ull,
|
||||
0x63d699605a596e8full, 0x34fc6307fc5f0721ull, 0x29b3da70e584df80ull, 0x665f23d76ec4525full, 0x5b6457bc4262bc99ull, 0x26dbbfb8288b09baull, 0x33364c2c16437b3aull, 0xb92c3bc1a472ac47ull,
|
||||
0xf7aa712b71bd56cdull, 0x049d31aef9d2570dull, 0x98dedb6bd48ff170ull, 0x2eb13790ac614f36ull, 0x600a76d6a6172203ull, 0x13d40013ed68f645ull, 0x68768385cfa4db7eull, 0x6a653712f829585full,
|
||||
0x0655fe0286a831b1ull, 0x21f1af4f5b206aaeull, 0xa17d5a7179884645ull, 0x282ac93600858673ull, 0x5198a93cc4deb1b0ull, 0xeed984bfe1c8fa33ull, 0x5b29ecf0552c2f4eull, 0xaee0fa0c181b9a4aull
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,22 +8,22 @@
|
|||
"source": "igneum-pow (Rust) CPU interpreter, generator v4, memory-hard dataset",
|
||||
"warps": [
|
||||
{"base_nonce": 0, "expected": [
|
||||
"0x40b750d1c8a8070f", "0x0eabee774c28ab59", "0xcc13c43e53c39432", "0x6a9c15036cd8ea3e", "0x33632873969d8ede", "0x598d17a33791fdc9", "0x2eff1230b4254f1e", "0xe94dd51fbd984bce",
|
||||
"0xb99fbeb7ee79e111", "0xf96bf58191e27007", "0x0d0eeb157f2fb140", "0xc63153f0272b9855", "0x73805af5544b3db0", "0x79c1b5a74c8560e9", "0x0ea9cca3277890e5", "0x1d176fab1cd2973a",
|
||||
"0x119ab8f645bf8a2d", "0xf1c9b6889298e177", "0x46f901ebdb35452a", "0x383a4d749d1ad0e8", "0xf4353dc68a21fac5", "0xa6c45db77d51deb9", "0x82603eb8e3a8df60", "0xf8245dd6e5b8de09",
|
||||
"0x3c5ad35824c49228", "0xc2ea030a6104da05", "0x6059173f71a28844", "0x42356c03e7c14337", "0xe707beb14ff8afa9", "0x0d572180b81363b2", "0xbd4479364aaac437", "0x3e6fd0864a730c42"
|
||||
"0x37153bb806168fe2", "0x60f5c68f3450d761", "0xe58773158354763a", "0xc982ec329d077c1b", "0x9941a2b9c89196bd", "0xd2b9fe1c2d2708b0", "0x1548e3bc5054162a", "0x6c90433d112dc47d",
|
||||
"0x7103d3c3b6c356f0", "0x6d214d6bed92ea3b", "0x68a576c3858eac19", "0x86c71bdb16dfc63d", "0x75fbfb8841591f6a", "0x62d2f7be3688f885", "0xb973b904cc383437", "0x30a6b60a33e5f513",
|
||||
"0xf0cb3dbea6f9880c", "0x8e3350ee3d5cf5ef", "0x280b6e74cf6f728d", "0x7534c2cabcbd1a74", "0x4b1583c09489e3a3", "0x3664deb8ab165897", "0x129192db3d976bdf", "0x903a6fe916f06f59",
|
||||
"0x4bc03753c1d0f1dd", "0xcbc8e21dcf41320d", "0x5be555c4779de21f", "0x64edc870ef6605c3", "0x268a25f14b989ec3", "0xa27ab228fc882951", "0x668ab91ab515077b", "0x6e5af942a42cca56"
|
||||
]},
|
||||
{"base_nonce": 4096, "expected": [
|
||||
"0x0db15f7c616f2d25", "0x17b04f540b4846d6", "0xcddd5a8ee8a5efe0", "0x0cf0cf62d997c83e", "0xbd5b7795b4dbd26c", "0x2d7b8aa0a985480f", "0x10d7689b878233c2", "0xbeed4790abb65517",
|
||||
"0x22c14a4e0a10eeae", "0xcdfa941f2e7960f9", "0x879bf9554455ec49", "0x5cec926ae13470fd", "0xad086583b0bccd24", "0xa76fa9afc7d6d9f8", "0x4dc4e1184adb00c8", "0x5410c5c88a875d85",
|
||||
"0x6ba2aed6fc622330", "0x4664d893aac13b54", "0x94bca09b542c77b6", "0x7ac3a74d54d15c2e", "0x8fd7503272ef64b9", "0xd9ffc122880e7432", "0xd232c638aba55395", "0xf25659961199829c",
|
||||
"0xe87691a335d4d5b4", "0xc24e26d570d76954", "0xc2bf85ff359b2121", "0xa4195d2eec65f9c8", "0x260b4f6b0a9b6138", "0x6b7082ed96379d93", "0x7a4d1e4f9cd0276b", "0x90afe3c042fed6e2"
|
||||
"0x15aa64176be3d2b7", "0x796085991cf0bc36", "0x4159555ce699c553", "0x41b7db70937ebff1", "0xb7aa5d515f39e98a", "0xbf65a44a7f9d28fb", "0xcbe8a4ff4bc229a7", "0xb896d2ef4595ef45",
|
||||
"0x4d95f8c4d3682289", "0x0e9238d0398c51a5", "0xc0071c186ac50324", "0x1677c4c8b8143a40", "0x7c468c9e658fbd7a", "0x06f20ab8ff3145b5", "0x493dd3161e781c21", "0x183408bb838cc8df",
|
||||
"0x9685a6f441083252", "0x6e67cbfa06e3e94f", "0x625e299810c789d9", "0x0ef9be59f2c83740", "0xcc9f24f893fbc87f", "0x2d92a13784beee93", "0xced96a43f0c3aec2", "0xd381e745a95e0106",
|
||||
"0xe91284aab02ea04d", "0x1600dcb649b27a02", "0x6fcee68b9137f52d", "0x685bfbdaa2b30404", "0xd329c9bbda12bf0e", "0xffdb6ba911480017", "0x8fe5930d6114ae5e", "0x25c6e5a41abf3065"
|
||||
]},
|
||||
{"base_nonce": 1000000, "expected": [
|
||||
"0x06897e48ecfdf30d", "0xc2407e8c2e0a6df7", "0xfc7b70f2531fc0ef", "0x747fb0709c82c21b", "0x2c1b6c10825e53ed", "0x4fc0e3d09485cbc3", "0x36a8e3d8a83dcb87", "0xa9b04c51829184f8",
|
||||
"0x16c05be25080fcbe", "0x488eec7576d2a293", "0xab03139ccbf27fa0", "0x85246c99a37d87d0", "0x09b2c5ae915b6eaf", "0x8e0a34f2ec25ba0c", "0xa5313b7d8a58e010", "0x8cb897eb47b626a6",
|
||||
"0x3c06e7453858ef65", "0xcee4fc69243cbf1b", "0xfe2f0b3329d6ef34", "0x3a19eccb6a374b0a", "0xa8848523eb449ec3", "0xc84ea452644c79ca", "0x23f77955e2b1c1d8", "0x1ec75c6675ca3245",
|
||||
"0xbe1c597e1dc237a3", "0x524841798abd82bc", "0x21c1b17d075c9356", "0xbeea164bb5aed2fa", "0x7e8db3ca049cde0e", "0x1a6f526d31708af9", "0x06096e878273cab7", "0x707399fc4e364b01"
|
||||
"0x4527f5599e3ef95f", "0x669c823cf598aa10", "0x0e0752b32f1a3b6c", "0xbc1d131573a47fe6", "0x6016efeaccc5ad4e", "0x73bde6a8fa03bb96", "0x9a0f79f0b5511922", "0x9058423b04f21c72",
|
||||
"0x63d699605a596e8f", "0x34fc6307fc5f0721", "0x29b3da70e584df80", "0x665f23d76ec4525f", "0x5b6457bc4262bc99", "0x26dbbfb8288b09ba", "0x33364c2c16437b3a", "0xb92c3bc1a472ac47",
|
||||
"0xf7aa712b71bd56cd", "0x049d31aef9d2570d", "0x98dedb6bd48ff170", "0x2eb13790ac614f36", "0x600a76d6a6172203", "0x13d40013ed68f645", "0x68768385cfa4db7e", "0x6a653712f829585f",
|
||||
"0x0655fe0286a831b1", "0x21f1af4f5b206aae", "0xa17d5a7179884645", "0x282ac93600858673", "0x5198a93cc4deb1b0", "0xeed984bfe1c8fa33", "0x5b29ecf0552c2f4e", "0xaee0fa0c181b9a4a"
|
||||
]}
|
||||
],
|
||||
"dataset_head": ["0x19c6837f", "0xbd3f6aed", "0x827e59af", "0x60286061", "0xdf3adfb8", "0xb8bede0d", "0x8cf592f5", "0x5d9abc1c", "0xc5f0629f", "0xc435a60e", "0xa85d0c39", "0xd41a5b0d", "0x03e38ae8", "0xfadee916", "0x4247a100", "0x3f33dc64"],
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
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r7 = r7 - r0; // 41 sub
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r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
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r0 = r0 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r0 = r0 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
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r3 = r3 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r3 = r3 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r4 = mul_hi(r4, r2); // 48 mulhi
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r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
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r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
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r5 = r5 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r6 = rotl_imm(r6, 12u); // 53 rotl
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r3 = rotl_imm(r3, 12u); // 54 rotl
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r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r5 = r5 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
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r3 = mul_hi(r3, r2); // 60 mulhi
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r6 = r6 | r4; // 61 or
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{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
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r3 = r3 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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r3 = r3 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
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for (uint sh = 0u; sh < 27u; ++sh) {
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r7 = r7 * r3; // s0 mul
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@ -71,7 +71,7 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
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r7 = r7 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
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r7 = r7 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
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r5 = r5 * r4; // 12 mul
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r7 = r7 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r7 = r7 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
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r2 = r2 | r7; // 16 or
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@ -87,9 +87,9 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
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r7 = rotr_var(r7, r0); // 26 rotr
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r4 = r5 * r7 + r4; // 27 mad
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r3 = r2 * r4 + r3; // 28 mad
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r2 = r2 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
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r1 = r1 ^ ds[((rotl_imm(r5 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
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r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
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r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
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@ -102,26 +102,26 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
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r7 = r7 - r0; // 41 sub
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r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
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r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
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r0 = r0 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r0 = r0 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
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r3 = r3 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r3 = r3 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r4 = __umulhi(r4, r2); // 48 mulhi
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r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
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r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
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r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
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r5 = r5 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r6 = rotl_imm(r6, 12u); // 53 rotl
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r3 = rotl_imm(r3, 12u); // 54 rotl
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r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r5 = r5 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
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r3 = __umulhi(r3, r2); // 60 mulhi
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r6 = r6 | r4; // 61 or
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r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
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r3 = r3 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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r3 = r3 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
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for (uint32_t sh = 0u; sh < 27u; ++sh) {
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r7 = r7 * r3; // s0 mul
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@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
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r7 = r7 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
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r7 = r7 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
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r5 = r5 * r4; // 12 mul
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r7 = r7 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r7 = r7 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
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{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
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r2 = r2 | r7; // 16 or
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@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
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r7 = rotr_var(r7, r0); // 26 rotr
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r4 = r5 * r7 + r4; // 27 mad
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r3 = r2 * r4 + r3; // 28 mad
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r2 = r2 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
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r1 = r1 ^ ds[((rotl_imm(r5 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
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r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
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r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
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@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
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r7 = r7 - r0; // 41 sub
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r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
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r0 = r0 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r0 = r0 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
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r3 = r3 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r3 = r3 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r4 = mul_hi(r4, r2); // 48 mulhi
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r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
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r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
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r5 = r5 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r6 = rotl_imm(r6, 12u); // 53 rotl
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r3 = rotl_imm(r3, 12u); // 54 rotl
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r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r5 = r5 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
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r3 = mul_hi(r3, r2); // 60 mulhi
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r6 = r6 | r4; // 61 or
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{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
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r3 = r3 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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r3 = r3 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
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for (uint sh = 0u; sh < 27u; ++sh) {
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r7 = r7 * r3; // s0 mul
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@ -577,7 +577,7 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
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r7 = r7 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
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r7 = r7 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
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r5 = r5 * r4; // 12 mul
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r7 = r7 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r7 = r7 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
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{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
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r2 = r2 | r7; // 16 or
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@ -593,9 +593,9 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
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r7 = rotr_var(r7, r0); // 26 rotr
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r4 = r5 * r7 + r4; // 27 mad
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r3 = r2 * r4 + r3; // 28 mad
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r2 = r2 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
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r1 = r1 ^ ds[((rotl_imm(r5 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
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r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
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@ -608,26 +608,26 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
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r7 = r7 - r0; // 41 sub
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r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
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r0 = r0 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r0 = r0 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
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||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -64,9 +64,9 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -79,26 +79,26 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
#define IGNEUM_GENERATOR 4
|
||||
#define IGNEUM_PROGRAM_ATTEMPT 0
|
||||
#define IGNEUM_PROGRAM_ID 0xc120d7963abdcd96ull
|
||||
#define IGNEUM_PROGRAM_ID 0x1a4230699a6b9c60ull
|
||||
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY0 0xceed56d7u
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
// latency-shadow block (IGNEUM_SHADOW_INSTRS x IGNEUM_SHADOW_REPS per iteration); a worker that runs another class
|
||||
// refuses this pack, and a job line names the class it wants (class=v4 era=<hex>).
|
||||
#define IGNEUM_PROGRAM_CLASS "v4"
|
||||
#define IGNEUM_PROGRAM_SUBVERSION 1
|
||||
#define IGNEUM_ERA_SEED_HEX "5e0587f455a86e91e4990f5c481a34cca0044d3f3ae519adcae58ddc82885d31"
|
||||
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
|
||||
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
"format": "igneum-program-pack-3",
|
||||
"generator": 4,
|
||||
"attempt": 0,
|
||||
"program_id": "0xc120d7963abdcd96",
|
||||
"program_id": "0x1a4230699a6b9c60",
|
||||
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
|
||||
"dataset_mode": "memory-hard",
|
||||
"seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000",
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
"instruction_count": 64,
|
||||
"loads_per_hash": 128,
|
||||
"program_class": "v4",
|
||||
"sub_version": 1,
|
||||
"era_seed_bytes": "5e0587f455a86e91e4990f5c481a34cca0044d3f3ae519adcae58ddc82885d31",
|
||||
"load_class": "mx8-era4488f3ed+sh256x27",
|
||||
"mixer_mult": 8,
|
||||
|
|
@ -350,7 +351,7 @@
|
|||
{"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -366,9 +367,9 @@
|
|||
{"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 6, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 4, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -381,25 +382,25 @@
|
|||
{"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 2, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 0, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 4, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 7, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 2, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -67,9 +67,9 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -82,26 +82,26 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -69,9 +69,9 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -84,26 +84,26 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x4d38603du, 10u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x4d38603du, 10u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@
|
|||
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
|
||||
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
|
||||
{ // base nonce 0
|
||||
0x32d75a818461b0feull, 0xfb58b5a9a0749f1aull, 0x7f1ef1c14a39acb7ull, 0x241bbf0d64ef82daull, 0xa91a888a98e1a327ull, 0x85236aa911aee1ccull, 0x2b621fc52bd4de06ull, 0xccb36c7b29b9f7eeull,
|
||||
0x81d5f71dddc9d99eull, 0x77e66510f1716ed8ull, 0x1dfc423f41cc325eull, 0xe4b7dc733eca22b9ull, 0x252e914ee1a1b811ull, 0xd60b7bb383400268ull, 0x68c45f316313a46eull, 0xb44e1d40659b5c0full,
|
||||
0x3317b1e961fa97caull, 0x048195572a542bd0ull, 0xbfc8c57f13ac1c9cull, 0x90b11f960392b615ull, 0x833c4d8bf2b4e7a3ull, 0x85e8a998130d39adull, 0x46989748ffc3f693ull, 0xbd9b68036b5db585ull,
|
||||
0x2a7b248a138b7764ull, 0xa808e45213e9e428ull, 0x1cd401d2d14d73caull, 0xf380476406eaa703ull, 0x61c78feb89981977ull, 0xf9f0d9a7a6a3bff5ull, 0x8e862238e6607e1bull, 0x81bb469c84523c38ull
|
||||
0x5e30f6e147847baaull, 0xd4a986fd412d5f58ull, 0x8fb8c6a3fd892bb6ull, 0x76fecdea24ce5c27ull, 0xa7a1e3ab7a0c8bf3ull, 0x6afcdc1109045dd6ull, 0x8db1733bfd1a60c1ull, 0xd8279191817ddadbull,
|
||||
0x455df586b88e2a27ull, 0x47e130d6d8dc7599ull, 0x011de4e7546a6aabull, 0x8019147975c644d9ull, 0xc6f45c4e3d1ad902ull, 0xad9f46665d838fdbull, 0xfde1bd6f79071a1dull, 0x15051235c0b8af20ull,
|
||||
0x80f2fc894a693840ull, 0xfb8b4aef39bb3fb2ull, 0xbc058211df33655cull, 0x8cc6b365ca25adecull, 0x944bd3b38dcd80ebull, 0xfed3b46304bb6b07ull, 0x8263c6bb59184d56ull, 0x0e925c43879fc3acull,
|
||||
0x188164779c652017ull, 0x2e81b531f96f89b2ull, 0x4dfde759744a0e2dull, 0xa341233a2985439aull, 0x2744e2772ef40647ull, 0xf3c112a8d85edd72ull, 0x96188dd19db1fe35ull, 0x8092a188e3b3d421ull
|
||||
},
|
||||
{ // base nonce 4096
|
||||
0x16a13c6b8953521full, 0xb6fc3248eab8ad1bull, 0xd7636da2cadffb33ull, 0x0e4b29dbfbc26c03ull, 0xdc3628881ff4d880ull, 0xd7b5b538a83fa397ull, 0xd628f6e4c1faea5cull, 0x1b7271fe675ac8d2ull,
|
||||
0xc2e58dc8651838edull, 0xeceb83b391908d90ull, 0x4d2ced55dd770a57ull, 0x8476f19f2dced0beull, 0x7943efb7511ec325ull, 0x39517e839ac5cad6ull, 0xa93a24a60552fef4ull, 0xd06f827bfad0666full,
|
||||
0x8ad225381fec0d20ull, 0xc533e53132f29515ull, 0xccf64b20e5996785ull, 0xca92afef337bf781ull, 0x0346c9056575b868ull, 0xbd579e3afcad5227ull, 0xebbb7866335220acull, 0xae3cdc60a6b6614aull,
|
||||
0xbb0d1a802ba23492ull, 0x694ff6fa089a8a70ull, 0xb56b49abd8dae21dull, 0x8c1fac2bf309ccecull, 0x79b9689a4b61c18cull, 0x3cb6c19bfbcce52eull, 0xe908bb28f2574c34ull, 0x35080bd5bf213879ull
|
||||
0xa82dad92a4844966ull, 0x86bc877ac1d7f8d9ull, 0x886a0f6ede139660ull, 0x3d043f1b08e7aa8full, 0x2a6226cfd2ec2a5cull, 0xad8d41e58871e974ull, 0x54ec878017940ad5ull, 0x592c5afe0dfbc72eull,
|
||||
0x4392a5e9b3658e57ull, 0x18960bb0d90a4ad2ull, 0x38f18a85bd7bd3e5ull, 0x12cb6327d5c18f6dull, 0x2f83a92640900bbbull, 0x77dec98d18eab7f7ull, 0xa5e4e850404d7d34ull, 0x47516a8342cb090aull,
|
||||
0xb1150af86382544dull, 0x733a534296240f82ull, 0x99307562e9afd07dull, 0x9e30fc63c43e8359ull, 0x663bdc575f7cb53eull, 0x1ae34599ee0a5a92ull, 0x066016af49d4e98eull, 0x0379d2b2a32d47d7ull,
|
||||
0xb042dc705b5471e2ull, 0x4a97a5ef5cecbdb1ull, 0x78d63a6205e725f3ull, 0xeec10012ce4c9990ull, 0x9db61a6f9db1cb69ull, 0xf84b77e21dcdcbafull, 0x66889a95d5269fdbull, 0x9d9f3e77aca6c08bull
|
||||
},
|
||||
{ // base nonce 1000000
|
||||
0x41302c423e89263bull, 0x5152c4fdb644c7ebull, 0xa9886ee87da41e91ull, 0x52a1e6209b2119baull, 0xce336b33dc0eea27ull, 0x59b61d9b32a49598ull, 0x9fcabf472fe74364ull, 0x5d0d09ce86a6ddbaull,
|
||||
0x884e7ebff4a1a28bull, 0xa39081f4965aac7dull, 0xdae88580d7337c0eull, 0xba0f4c8b0d79c15cull, 0x66392f1948e70a94ull, 0xa7f0aeab677fb0aaull, 0x0efa4e6ea43702e4ull, 0xc2944100f48711f1ull,
|
||||
0xe22bf44299adaf79ull, 0x1a6c099e2b3836caull, 0x7595a2366be1b0dfull, 0xa0dc4af86aec0108ull, 0xa0b96e19fea7aed8ull, 0x52ca60aeb1c3dfc6ull, 0xde7a719d2d766daaull, 0x477f9497ccbf9388ull,
|
||||
0x8ce858b1f1d19a94ull, 0xdeab496a568e6df5ull, 0x6eb8896aff7fc737ull, 0xa3ef1cbbc0084fb9ull, 0x8609281ee7caf702ull, 0x6a403ada59e40b68ull, 0x7ee1a0b4bafe9a8aull, 0x6a6017a19d0e6879ull
|
||||
0xbbf87e39249e556full, 0x2e7be83d02bb08f2ull, 0x9a537c58f37ddaabull, 0x9afb00cf31489e2bull, 0xa0d3d02f0027d744ull, 0xdf120e458e67366bull, 0xecdaa71fd4c3a70dull, 0x8bb9f646e2b5d5b6ull,
|
||||
0x034e7da0eafd1f35ull, 0xfe3b55dc8768445full, 0x64655b7a964f20c2ull, 0xadbf74ba32b3c89full, 0x100b92b978b97765ull, 0xff8533443a7c4e63ull, 0xa5fc6924addb2af2ull, 0x0b581cac03ea0795ull,
|
||||
0x6df3f94de517f7c7ull, 0xac03c73ec098613full, 0xc6b4458cdfa992b9ull, 0xc99165dba30c96a5ull, 0x9805654f34d19c45ull, 0x7f56df6ca7d15adfull, 0xc1614ccee9f557dfull, 0xafb2798b9acd19c6ull,
|
||||
0x7d595db677a8441full, 0x9d01cfa6ace20608ull, 0x5780b6be029f252full, 0x8a0c1d4d608f5a35ull, 0x82c3bdf675e67a55ull, 0x4dfea446387fc345ull, 0x184ee05378f8817eull, 0xf7ce3da4c735c97cull
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,22 +8,22 @@
|
|||
"source": "igneum-pow (Rust) CPU interpreter, generator v4, memory-hard dataset",
|
||||
"warps": [
|
||||
{"base_nonce": 0, "expected": [
|
||||
"0x32d75a818461b0fe", "0xfb58b5a9a0749f1a", "0x7f1ef1c14a39acb7", "0x241bbf0d64ef82da", "0xa91a888a98e1a327", "0x85236aa911aee1cc", "0x2b621fc52bd4de06", "0xccb36c7b29b9f7ee",
|
||||
"0x81d5f71dddc9d99e", "0x77e66510f1716ed8", "0x1dfc423f41cc325e", "0xe4b7dc733eca22b9", "0x252e914ee1a1b811", "0xd60b7bb383400268", "0x68c45f316313a46e", "0xb44e1d40659b5c0f",
|
||||
"0x3317b1e961fa97ca", "0x048195572a542bd0", "0xbfc8c57f13ac1c9c", "0x90b11f960392b615", "0x833c4d8bf2b4e7a3", "0x85e8a998130d39ad", "0x46989748ffc3f693", "0xbd9b68036b5db585",
|
||||
"0x2a7b248a138b7764", "0xa808e45213e9e428", "0x1cd401d2d14d73ca", "0xf380476406eaa703", "0x61c78feb89981977", "0xf9f0d9a7a6a3bff5", "0x8e862238e6607e1b", "0x81bb469c84523c38"
|
||||
"0x5e30f6e147847baa", "0xd4a986fd412d5f58", "0x8fb8c6a3fd892bb6", "0x76fecdea24ce5c27", "0xa7a1e3ab7a0c8bf3", "0x6afcdc1109045dd6", "0x8db1733bfd1a60c1", "0xd8279191817ddadb",
|
||||
"0x455df586b88e2a27", "0x47e130d6d8dc7599", "0x011de4e7546a6aab", "0x8019147975c644d9", "0xc6f45c4e3d1ad902", "0xad9f46665d838fdb", "0xfde1bd6f79071a1d", "0x15051235c0b8af20",
|
||||
"0x80f2fc894a693840", "0xfb8b4aef39bb3fb2", "0xbc058211df33655c", "0x8cc6b365ca25adec", "0x944bd3b38dcd80eb", "0xfed3b46304bb6b07", "0x8263c6bb59184d56", "0x0e925c43879fc3ac",
|
||||
"0x188164779c652017", "0x2e81b531f96f89b2", "0x4dfde759744a0e2d", "0xa341233a2985439a", "0x2744e2772ef40647", "0xf3c112a8d85edd72", "0x96188dd19db1fe35", "0x8092a188e3b3d421"
|
||||
]},
|
||||
{"base_nonce": 4096, "expected": [
|
||||
"0x16a13c6b8953521f", "0xb6fc3248eab8ad1b", "0xd7636da2cadffb33", "0x0e4b29dbfbc26c03", "0xdc3628881ff4d880", "0xd7b5b538a83fa397", "0xd628f6e4c1faea5c", "0x1b7271fe675ac8d2",
|
||||
"0xc2e58dc8651838ed", "0xeceb83b391908d90", "0x4d2ced55dd770a57", "0x8476f19f2dced0be", "0x7943efb7511ec325", "0x39517e839ac5cad6", "0xa93a24a60552fef4", "0xd06f827bfad0666f",
|
||||
"0x8ad225381fec0d20", "0xc533e53132f29515", "0xccf64b20e5996785", "0xca92afef337bf781", "0x0346c9056575b868", "0xbd579e3afcad5227", "0xebbb7866335220ac", "0xae3cdc60a6b6614a",
|
||||
"0xbb0d1a802ba23492", "0x694ff6fa089a8a70", "0xb56b49abd8dae21d", "0x8c1fac2bf309ccec", "0x79b9689a4b61c18c", "0x3cb6c19bfbcce52e", "0xe908bb28f2574c34", "0x35080bd5bf213879"
|
||||
"0xa82dad92a4844966", "0x86bc877ac1d7f8d9", "0x886a0f6ede139660", "0x3d043f1b08e7aa8f", "0x2a6226cfd2ec2a5c", "0xad8d41e58871e974", "0x54ec878017940ad5", "0x592c5afe0dfbc72e",
|
||||
"0x4392a5e9b3658e57", "0x18960bb0d90a4ad2", "0x38f18a85bd7bd3e5", "0x12cb6327d5c18f6d", "0x2f83a92640900bbb", "0x77dec98d18eab7f7", "0xa5e4e850404d7d34", "0x47516a8342cb090a",
|
||||
"0xb1150af86382544d", "0x733a534296240f82", "0x99307562e9afd07d", "0x9e30fc63c43e8359", "0x663bdc575f7cb53e", "0x1ae34599ee0a5a92", "0x066016af49d4e98e", "0x0379d2b2a32d47d7",
|
||||
"0xb042dc705b5471e2", "0x4a97a5ef5cecbdb1", "0x78d63a6205e725f3", "0xeec10012ce4c9990", "0x9db61a6f9db1cb69", "0xf84b77e21dcdcbaf", "0x66889a95d5269fdb", "0x9d9f3e77aca6c08b"
|
||||
]},
|
||||
{"base_nonce": 1000000, "expected": [
|
||||
"0x41302c423e89263b", "0x5152c4fdb644c7eb", "0xa9886ee87da41e91", "0x52a1e6209b2119ba", "0xce336b33dc0eea27", "0x59b61d9b32a49598", "0x9fcabf472fe74364", "0x5d0d09ce86a6ddba",
|
||||
"0x884e7ebff4a1a28b", "0xa39081f4965aac7d", "0xdae88580d7337c0e", "0xba0f4c8b0d79c15c", "0x66392f1948e70a94", "0xa7f0aeab677fb0aa", "0x0efa4e6ea43702e4", "0xc2944100f48711f1",
|
||||
"0xe22bf44299adaf79", "0x1a6c099e2b3836ca", "0x7595a2366be1b0df", "0xa0dc4af86aec0108", "0xa0b96e19fea7aed8", "0x52ca60aeb1c3dfc6", "0xde7a719d2d766daa", "0x477f9497ccbf9388",
|
||||
"0x8ce858b1f1d19a94", "0xdeab496a568e6df5", "0x6eb8896aff7fc737", "0xa3ef1cbbc0084fb9", "0x8609281ee7caf702", "0x6a403ada59e40b68", "0x7ee1a0b4bafe9a8a", "0x6a6017a19d0e6879"
|
||||
"0xbbf87e39249e556f", "0x2e7be83d02bb08f2", "0x9a537c58f37ddaab", "0x9afb00cf31489e2b", "0xa0d3d02f0027d744", "0xdf120e458e67366b", "0xecdaa71fd4c3a70d", "0x8bb9f646e2b5d5b6",
|
||||
"0x034e7da0eafd1f35", "0xfe3b55dc8768445f", "0x64655b7a964f20c2", "0xadbf74ba32b3c89f", "0x100b92b978b97765", "0xff8533443a7c4e63", "0xa5fc6924addb2af2", "0x0b581cac03ea0795",
|
||||
"0x6df3f94de517f7c7", "0xac03c73ec098613f", "0xc6b4458cdfa992b9", "0xc99165dba30c96a5", "0x9805654f34d19c45", "0x7f56df6ca7d15adf", "0xc1614ccee9f557df", "0xafb2798b9acd19c6",
|
||||
"0x7d595db677a8441f", "0x9d01cfa6ace20608", "0x5780b6be029f252f", "0x8a0c1d4d608f5a35", "0x82c3bdf675e67a55", "0x4dfea446387fc345", "0x184ee05378f8817e", "0xf7ce3da4c735c97c"
|
||||
]}
|
||||
],
|
||||
"dataset_head": ["0x19c6837f", "0xbd3f6aed", "0x827e59af", "0x60286061", "0xdf3adfb8", "0xb8bede0d", "0x8cf592f5", "0x5d9abc1c", "0x680c3063", "0x64552beb", "0x43376a1c", "0x84d86df8", "0x15623a58", "0x50d157a7", "0x9d970ef9", "0x02b7d1e4"],
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -87,9 +87,9 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -102,26 +102,26 @@ __global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonc
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -231,9 +231,9 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -246,26 +246,26 @@ IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
@ -577,7 +577,7 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r6 = r6 ^ t_; } // 14 shfl
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r3 = r3 ^ t_; } // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -593,9 +593,9 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -608,26 +608,26 @@ IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulon
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = mul_hi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r0 = r0 ^ t_; } // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = mul_hi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r5 = r5 ^ t_; } // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
|
||||
r5 = r5 * r4; // 12 mul
|
||||
r7 = r7 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r7 = r7 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
|
||||
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
|
||||
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
|
||||
r2 = r2 | r7; // 16 or
|
||||
|
|
@ -64,9 +64,9 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = rotr_var(r7, r0); // 26 rotr
|
||||
r4 = r5 * r7 + r4; // 27 mad
|
||||
r3 = r2 * r4 + r3; // 28 mad
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
|
||||
r2 = r2 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r5 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
|
||||
r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
|
||||
r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
|
||||
r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
|
||||
|
|
@ -79,26 +79,26 @@ __global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t ba
|
|||
r7 = r7 - r0; // 41 sub
|
||||
r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
|
||||
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
|
||||
r0 = r0 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r0 = r0 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
|
||||
r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
|
||||
r3 = r3 ^ ds[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
|
||||
r6 = r6 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
|
||||
r4 = __umulhi(r4, r2); // 48 mulhi
|
||||
r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
|
||||
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
|
||||
r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
|
||||
r6 = rotl_imm(r6, 12u); // 53 rotl
|
||||
r3 = rotl_imm(r3, 12u); // 54 rotl
|
||||
r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
|
||||
r1 = r1 ^ ds[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r1 = r1 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
|
||||
r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
|
||||
r5 = r5 ^ ds[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r5 = r5 ^ ds[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
|
||||
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
|
||||
r3 = __umulhi(r3, r2); // 60 mulhi
|
||||
r6 = r6 | r4; // 61 or
|
||||
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
|
||||
r3 = r3 ^ ds[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
r3 = r3 ^ ds[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint32_t sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
#define IGNEUM_SEED_BYTES_HEX "edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07"
|
||||
#define IGNEUM_GENERATOR 4
|
||||
#define IGNEUM_PROGRAM_ATTEMPT 0
|
||||
#define IGNEUM_PROGRAM_ID 0xc120d7963abdcd96ull
|
||||
#define IGNEUM_PROGRAM_ID 0x1a4230699a6b9c60ull
|
||||
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffa50000000000000"
|
||||
#define IGNEUM_DAY0 0xceed56d7u
|
||||
|
|
@ -32,6 +32,7 @@
|
|||
// latency-shadow block (IGNEUM_SHADOW_INSTRS x IGNEUM_SHADOW_REPS per iteration); a worker that runs another class
|
||||
// refuses this pack, and a job line names the class it wants (class=v4 era=<hex>).
|
||||
#define IGNEUM_PROGRAM_CLASS "v4"
|
||||
#define IGNEUM_PROGRAM_SUBVERSION 1
|
||||
#define IGNEUM_ERA_SEED_HEX "7f450623297a954f493ca08abcdfe7142bb753900abcee38256266007b4b48b7"
|
||||
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
|
||||
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
"format": "igneum-program-pack-3",
|
||||
"generator": 4,
|
||||
"attempt": 0,
|
||||
"program_id": "0xc120d7963abdcd96",
|
||||
"program_id": "0x1a4230699a6b9c60",
|
||||
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
|
||||
"dataset_mode": "memory-hard",
|
||||
"seed": "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000",
|
||||
|
|
@ -16,6 +16,7 @@
|
|||
"instruction_count": 64,
|
||||
"loads_per_hash": 128,
|
||||
"program_class": "v4",
|
||||
"sub_version": 1,
|
||||
"era_seed_bytes": "7f450623297a954f493ca08abcdfe7142bb753900abcee38256266007b4b48b7",
|
||||
"load_class": "mx8-eraf897c84e+sh256x27",
|
||||
"mixer_mult": 8,
|
||||
|
|
@ -350,7 +351,7 @@
|
|||
{"i": 10, "op": "load", "dst": 7, "src": 0, "src2": 2, "imm": "0xe075297c", "imm2": "0x5779c44c", "rot": 10, "bit": 22, "mask": 2, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 11, "op": "load", "dst": 7, "src": 1, "src2": 6, "imm": "0x65aa4311", "imm2": "0x4fe48ea9", "rot": 15, "bit": 9, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 12, "op": "mul", "dst": 5, "src": 4, "src2": 2, "imm": "0x1383d3ad", "imm2": "0xf3094b29", "rot": 8, "bit": 9, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 6, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 13, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0xed8a496f", "imm2": "0x3072c3c6", "rot": 28, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 14, "op": "shfl", "dst": 6, "src": 5, "src2": 0, "imm": "0x8b965b57", "imm2": "0xcfeca6c1", "rot": 12, "bit": 27, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 15, "op": "shfl", "dst": 3, "src": 5, "src2": 3, "imm": "0x877c7586", "imm2": "0xa9cb2a03", "rot": 2, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 16, "op": "or", "dst": 2, "src": 7, "src2": 3, "imm": "0xb740221a", "imm2": "0x89d38d6d", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -366,9 +367,9 @@
|
|||
{"i": 26, "op": "rotr", "dst": 7, "src": 0, "src2": 1, "imm": "0xd89ef484", "imm2": "0x20be3846", "rot": 12, "bit": 9, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 27, "op": "mad", "dst": 4, "src": 5, "src2": 7, "imm": "0xb48420ae", "imm2": "0x3d1f2485", "rot": 14, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 28, "op": "mad", "dst": 3, "src": 2, "src2": 4, "imm": "0xc5c46d76", "imm2": "0x700044b5", "rot": 22, "bit": 10, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 4, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 29, "op": "load", "dst": 1, "src": 6, "src2": 3, "imm": "0x0fbaf177", "imm2": "0xfff4f2ed", "rot": 20, "bit": 31, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 30, "op": "load", "dst": 2, "src": 3, "src2": 0, "imm": "0xe90eb2e5", "imm2": "0xb0f9eb79", "rot": 27, "bit": 14, "mask": 4, "width": 1, "win": 2, "off": 2},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 5, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 31, "op": "load", "dst": 1, "src": 4, "src2": 2, "imm": "0x97ba3fc3", "imm2": "0x7894e657", "rot": 3, "bit": 30, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 32, "op": "add", "dst": 7, "src": 2, "src2": 7, "imm": "0x070888a8", "imm2": "0xe403240e", "rot": 2, "bit": 16, "mask": 2, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 33, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xf2e46d55", "imm2": "0x29701828", "rot": 31, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 34, "op": "add", "dst": 2, "src": 3, "src2": 0, "imm": "0x58f75b87", "imm2": "0x343b7aee", "rot": 12, "bit": 14, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
|
|
@ -381,25 +382,25 @@
|
|||
{"i": 41, "op": "sub", "dst": 7, "src": 0, "src2": 2, "imm": "0x0daf96ea", "imm2": "0x36f37be1", "rot": 5, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 42, "op": "add", "dst": 4, "src": 3, "src2": 6, "imm": "0x6ced15b7", "imm2": "0x6df7aed4", "rot": 19, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 43, "op": "shfl", "dst": 7, "src": 3, "src2": 5, "imm": "0x8ace05f3", "imm2": "0xd378ec12", "rot": 23, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 7, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 44, "op": "load", "dst": 0, "src": 2, "src2": 4, "imm": "0xb0607786", "imm2": "0xc4acabbc", "rot": 13, "bit": 7, "mask": 16, "width": 1, "win": 1, "off": 1},
|
||||
{"i": 45, "op": "add", "dst": 1, "src": 6, "src2": 5, "imm": "0xe09f54e9", "imm2": "0x83e825bf", "rot": 23, "bit": 14, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 1, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 3, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 46, "op": "load", "dst": 3, "src": 0, "src2": 0, "imm": "0x63cc1e4e", "imm2": "0xa1be8118", "rot": 12, "bit": 6, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 47, "op": "load", "dst": 6, "src": 4, "src2": 7, "imm": "0x353f1d79", "imm2": "0x3b2e7456", "rot": 18, "bit": 18, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 48, "op": "mulhi", "dst": 4, "src": 2, "src2": 7, "imm": "0x00d8a3cd", "imm2": "0x231866d2", "rot": 21, "bit": 20, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 49, "op": "add", "dst": 5, "src": 0, "src2": 2, "imm": "0xa8bae6df", "imm2": "0xf572bdb9", "rot": 14, "bit": 7, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 50, "op": "shfl", "dst": 0, "src": 7, "src2": 7, "imm": "0x81ef22e1", "imm2": "0x74438fc5", "rot": 28, "bit": 18, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 51, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x383b9260", "imm2": "0x11e17c61", "rot": 12, "bit": 19, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 2, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 52, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0xfb84f451", "imm2": "0x11cd863e", "rot": 21, "bit": 20, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 53, "op": "rotl", "dst": 6, "src": 5, "src2": 4, "imm": "0xb1a7db6b", "imm2": "0x76686b9b", "rot": 12, "bit": 4, "mask": 16, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 54, "op": "rotl", "dst": 3, "src": 6, "src2": 3, "imm": "0x6f981f52", "imm2": "0xd99aeba2", "rot": 12, "bit": 27, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 55, "op": "add", "dst": 2, "src": 1, "src2": 2, "imm": "0xac6be8e3", "imm2": "0x18d67dbb", "rot": 26, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 4, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 56, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x7e7f6a00", "imm2": "0x6f0747da", "rot": 25, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 57, "op": "add", "dst": 5, "src": 0, "src2": 4, "imm": "0xf03673fe", "imm2": "0xa75cd60d", "rot": 16, "bit": 12, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 0, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 58, "op": "load", "dst": 5, "src": 7, "src2": 2, "imm": "0x227f94a6", "imm2": "0x0e8344f9", "rot": 20, "bit": 10, "mask": 2, "width": 1, "win": 2, "off": 0},
|
||||
{"i": 59, "op": "add", "dst": 1, "src": 4, "src2": 3, "imm": "0xdecd4794", "imm2": "0x8dfb96bb", "rot": 21, "bit": 7, "mask": 4, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 60, "op": "mulhi", "dst": 3, "src": 2, "src2": 2, "imm": "0x0dd268e0", "imm2": "0x53034ca9", "rot": 1, "bit": 8, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 61, "op": "or", "dst": 6, "src": 4, "src2": 7, "imm": "0x3a45a321", "imm2": "0x9bc59a5f", "rot": 25, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 62, "op": "shfl", "dst": 5, "src": 4, "src2": 2, "imm": "0x8f229cc1", "imm2": "0xcaac64a2", "rot": 17, "bit": 13, "mask": 8, "width": 1, "win": 0, "off": 0},
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 6, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
{"i": 63, "op": "load", "dst": 3, "src": 2, "src2": 6, "imm": "0xb2574178", "imm2": "0xcbcc798d", "rot": 28, "bit": 0, "mask": 16, "width": 1, "win": 1, "off": 1}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -67,9 +67,9 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -82,26 +82,26 @@ kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 10
|
||||
r7 = r7 ^ dataset[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 11
|
||||
r5 = r5 * r4; // 12
|
||||
r7 = r7 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 13
|
||||
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)16); // 14
|
||||
r3 = r3 ^ simd_shuffle_xor(r5, (ushort)1); // 15
|
||||
r2 = r2 | r7; // 16
|
||||
|
|
@ -69,9 +69,9 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = rotr_var(r7, r0); // 26
|
||||
r4 = r5 * r7 + r4; // 27
|
||||
r3 = r2 * r4 + r3; // 28
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 29
|
||||
r2 = r2 ^ dataset[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 30
|
||||
r1 = r1 ^ dataset[((rotl_imm(r5 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 31
|
||||
r7 = r7 + r2 + select(0x070888a8u, 0xe403240eu, ((sel >> 16u) & 1u) != 0u); // 32
|
||||
r2 = r2 + r0 + select(0xf2e46d55u, 0x29701828u, ((sel >> 28u) & 1u) != 0u); // 33
|
||||
r2 = r2 + r3 + select(0x58f75b87u, 0x343b7aeeu, ((sel >> 14u) & 1u) != 0u); // 34
|
||||
|
|
@ -84,26 +84,26 @@ kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
|
|||
r7 = r7 - r0; // 41
|
||||
r4 = r4 + r3 + select(0x6ced15b7u, 0x6df7aed4u, ((sel >> 4u) & 1u) != 0u); // 42
|
||||
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 43
|
||||
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r0 = r0 ^ dataset[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 44
|
||||
r1 = r1 + r6 + select(0xe09f54e9u, 0x83e825bfu, ((sel >> 14u) & 1u) != 0u); // 45
|
||||
r3 = r3 ^ dataset[((rotl_imm(r1 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 46
|
||||
r6 = r6 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 47
|
||||
r4 = mulhi(r4, r2); // 48
|
||||
r5 = r5 + r0 + select(0xa8bae6dfu, 0xf572bdb9u, ((sel >> 7u) & 1u) != 0u); // 49
|
||||
r0 = r0 ^ simd_shuffle_xor(r7, (ushort)4); // 50
|
||||
r6 = r6 + r0 + select(0x383b9260u, 0x11e17c61u, ((sel >> 19u) & 1u) != 0u); // 51
|
||||
r5 = r5 ^ dataset[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 52
|
||||
r6 = rotl_imm(r6, 12u); // 53
|
||||
r3 = rotl_imm(r3, 12u); // 54
|
||||
r2 = r2 + r1 + select(0xac6be8e3u, 0x18d67dbbu, ((sel >> 10u) & 1u) != 0u); // 55
|
||||
r1 = r1 ^ dataset[((rotl_imm(r4 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r1 = r1 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 56
|
||||
r5 = r5 + r0 + select(0xf03673feu, 0xa75cd60du, ((sel >> 12u) & 1u) != 0u); // 57
|
||||
r5 = r5 ^ dataset[((rotl_imm(r0 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x03ac37adu, 22u) & 0x03ffffffu) | 0x00000000u) & MASK]; // 58
|
||||
r1 = r1 + r4 + select(0xdecd4794u, 0x8dfb96bbu, ((sel >> 7u) & 1u) != 0u); // 59
|
||||
r3 = mulhi(r3, r2); // 60
|
||||
r6 = r6 | r4; // 61
|
||||
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)8); // 62
|
||||
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
r3 = r3 ^ dataset[((rotl_imm(r2 * 0x03ac37adu, 22u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 63
|
||||
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
|
||||
for (uint sh = 0u; sh < 27u; ++sh) {
|
||||
r7 = r7 * r3; // s0 mul
|
||||
|
|
|
|||
|
|
@ -11,22 +11,22 @@
|
|||
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
|
||||
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
|
||||
{ // base nonce 0
|
||||
0xbf945be0cc8d3f41ull, 0x34be8a9b058957efull, 0xa790f250cb3f84c2ull, 0xf348a3adcb120feeull, 0x84ffe7a18320fce6ull, 0xc3ca0cd342a7b5a0ull, 0xc661be2913cc0a16ull, 0x42a2613074355476ull,
|
||||
0x652f7593de7c1c6bull, 0x8b82eec6d8a4cdb5ull, 0x64a052482e4aa45aull, 0x945d11e95d050e91ull, 0x9922b0bf0a9b65afull, 0xa6a46d687a41eea8ull, 0x1cd22c7c5a116cadull, 0x3bb0fe59f1d68bb0ull,
|
||||
0x392c2e38402ce2ceull, 0xce206717bf858f7bull, 0x725267c1b0a569c1ull, 0xb1a10c27e394a06cull, 0x8694ba08f13dadcaull, 0x9f6e2f304e7f8410ull, 0xfca54880fe409efbull, 0x8ddf5d9f26f6651aull,
|
||||
0x7744b0375f6a5356ull, 0x2ec062f98cea9669ull, 0x1fc1df8a93493c01ull, 0xe58efdbe3b0fded0ull, 0xbc80f43278e4a3aeull, 0xc576991cd263499bull, 0x6a964020bdafa9caull, 0x23d6a9f3a43b088bull
|
||||
0x5fb133e6c14c3239ull, 0xb360d37aad99f76eull, 0x3da84fceefd06da5ull, 0xb2f803d8b83b07f3ull, 0xb19744c94a9744e4ull, 0x23c93b9aa7c68069ull, 0x912436b29f5fbcf3ull, 0xf6313962096b23d1ull,
|
||||
0xc82d75c830055863ull, 0x8933404595905aacull, 0x8edb7eab7c52d898ull, 0xe18afb092d408221ull, 0x00e2ff8b85b0f958ull, 0x138c26a6b2a01fa9ull, 0xf149c5571b8a011eull, 0x7b4e2cbed63486faull,
|
||||
0xb8aa812f44e45ed5ull, 0x61e2ceb11adede7bull, 0x86dda499d4f04da5ull, 0x9b97c751cc58b065ull, 0x8d4fdd8fa6de313full, 0xd01cbad514f3184full, 0x41313afa438ff648ull, 0x3d2e3f3816471876ull,
|
||||
0x465cc98a2fddec00ull, 0x268e1eb581c20a56ull, 0xb4cd4af84b66c5daull, 0x69ccaa63aab033eeull, 0x20b53d1e00c359e9ull, 0xd6a3c40b2e86712dull, 0x6bbb5a2bd570bb00ull, 0x2aa8b2436df218edull
|
||||
},
|
||||
{ // base nonce 4096
|
||||
0x39a9f8aba6a9c7abull, 0xf1daab939a9c3217ull, 0x5831fcce18c03b2full, 0xb8ff659519b96eedull, 0x88d08144f09ffb22ull, 0xa373485c22133291ull, 0xfc82bfd2743de9dbull, 0x19dffd993bf1a1a3ull,
|
||||
0xec61385b02ed1eecull, 0xe3a705fedd476c62ull, 0x012af0af0abd2f1bull, 0xacbfc40c16d1c409ull, 0x64e16756a429ee6aull, 0x9a8b8c542b85d64bull, 0x95b962ec795480c1ull, 0x11a35a7657f86c66ull,
|
||||
0x4ae11f4a8b22a8edull, 0x649bd0de4210bbb2ull, 0xd9e81d1e0c794619ull, 0x865a6073aeaad870ull, 0xcc691a4eb315ed94ull, 0x7bdf6b0662f171e6ull, 0xde979c126cd8b9a8ull, 0x801a11f95defd5baull,
|
||||
0xe0b160c42c39df59ull, 0x2319e68444cacb1bull, 0xd8beee32eb63a71eull, 0x272e524e202c58dbull, 0xeefad04ef941e833ull, 0x98b08bb5658177b1ull, 0xeb6833af292f958eull, 0xb6b358ffd3b2de03ull
|
||||
0xc3c344c2ff16bff0ull, 0x537b196cd4cdbb09ull, 0x65fca37074e405f4ull, 0x072f943a4caffb36ull, 0x662266cf8de82a8aull, 0xb860ab3d16ae86f7ull, 0x5f98e443ce34f1bbull, 0xce1c9ca2339c0e42ull,
|
||||
0xccd68b4df195bbc9ull, 0x2866b38d4a401168ull, 0x9786a1957c75e7adull, 0x3ec5fc87c207ce1aull, 0x1fce372f3838e249ull, 0x0dde9ad1dc8938a3ull, 0xed1579fda990b570ull, 0x66bcd22759864a63ull,
|
||||
0x414d18a7c2507713ull, 0x0baddd09cc36a520ull, 0x8cd11f2ce02057b2ull, 0x8d898aac85fd75aaull, 0xea1acc6c93538ab9ull, 0x5d05a096b6bb636eull, 0x87e90c4240907c75ull, 0x049242a31f44ee9aull,
|
||||
0x2d0f84f4dd7cbfa8ull, 0x87694b7df4a79af1ull, 0xaaaafbe9f79bc92dull, 0x300a667ee303c8d5ull, 0x2666fabf6267e27full, 0x198602472c92fcadull, 0xa59eeed45b81af4aull, 0x22d7d46002bc7e7full
|
||||
},
|
||||
{ // base nonce 1000000
|
||||
0xb4835ddebdbfbaebull, 0x05ececfd8ef508ccull, 0x4bc1315c1b1ce4c8ull, 0xe13eca621f2ff598ull, 0x6fffb12762010b6cull, 0x78139a212e0870eeull, 0xe9e197bebebbce63ull, 0xb485f4c5f50377bdull,
|
||||
0x1284446e016546c1ull, 0xa2e4a3aefd217a73ull, 0xa484b974f813abb7ull, 0xf9959eac63a1401cull, 0x77b081fd93294af8ull, 0x1fc7fc1eb3d9eaabull, 0x71c51d4214cb47f0ull, 0x52171833d8d341f0ull,
|
||||
0x5699e6eae25c5854ull, 0x34752dd16c6ce88full, 0x353dd3b0890ba109ull, 0x696b0afc8f6fe70eull, 0x2b30eaa48b77cd0cull, 0x6c600c3b87409c38ull, 0x26ead9ba20d15168ull, 0xc93e5f5a261bc786ull,
|
||||
0x8606f09c2c74c81cull, 0x1b3f9792e5247d66ull, 0xf8bb901d0dd87bfaull, 0xbc939e016a57b734ull, 0x7bbbffc2dbcbc12aull, 0x51beb5108f2ae2a4ull, 0x37b252067e6cc262ull, 0xf038a9ff99426f88ull
|
||||
0xfcb7fbc29dad03d4ull, 0x54b64718d6fdcc0dull, 0x9c938236394bba35ull, 0x7c9b920dd87181bbull, 0xe61f6268c5e7e8a0ull, 0xf7c2cfd988090e76ull, 0xaec2e24e7050a52aull, 0x37ffb04710cce394ull,
|
||||
0x03046fa86bf21b62ull, 0x00785f0d4ed2331aull, 0x321a6fa31bc9b391ull, 0xdf88e6417dec1c9eull, 0x1b6ec67bbcd424d6ull, 0xa247dc89c7f3cc6bull, 0x1475f9ac604490b1ull, 0x106637b278da24a8ull,
|
||||
0xa697188fec6bdb0aull, 0x7e4c0201314281a7ull, 0xa8c7742d814fc0d1ull, 0xb07431c74a4506e3ull, 0xa9d8974c47e028cbull, 0x42189e4fdd512dc5ull, 0xc6fe11a9e9153822ull, 0x4ea57f7253864742ull,
|
||||
0xaabc3663cf578aefull, 0xf28f68780e809bfeull, 0x2df16b27d9eb162eull, 0x0f8ccb24b6ab2297ull, 0x863b7048b78f5453ull, 0x63652a33014e3f00ull, 0xb107d73ffd8431ffull, 0xcd7d8e5f0bc30687ull
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,22 +8,22 @@
|
|||
"source": "igneum-pow (Rust) CPU interpreter, generator v4, memory-hard dataset",
|
||||
"warps": [
|
||||
{"base_nonce": 0, "expected": [
|
||||
"0xbf945be0cc8d3f41", "0x34be8a9b058957ef", "0xa790f250cb3f84c2", "0xf348a3adcb120fee", "0x84ffe7a18320fce6", "0xc3ca0cd342a7b5a0", "0xc661be2913cc0a16", "0x42a2613074355476",
|
||||
"0x652f7593de7c1c6b", "0x8b82eec6d8a4cdb5", "0x64a052482e4aa45a", "0x945d11e95d050e91", "0x9922b0bf0a9b65af", "0xa6a46d687a41eea8", "0x1cd22c7c5a116cad", "0x3bb0fe59f1d68bb0",
|
||||
"0x392c2e38402ce2ce", "0xce206717bf858f7b", "0x725267c1b0a569c1", "0xb1a10c27e394a06c", "0x8694ba08f13dadca", "0x9f6e2f304e7f8410", "0xfca54880fe409efb", "0x8ddf5d9f26f6651a",
|
||||
"0x7744b0375f6a5356", "0x2ec062f98cea9669", "0x1fc1df8a93493c01", "0xe58efdbe3b0fded0", "0xbc80f43278e4a3ae", "0xc576991cd263499b", "0x6a964020bdafa9ca", "0x23d6a9f3a43b088b"
|
||||
"0x5fb133e6c14c3239", "0xb360d37aad99f76e", "0x3da84fceefd06da5", "0xb2f803d8b83b07f3", "0xb19744c94a9744e4", "0x23c93b9aa7c68069", "0x912436b29f5fbcf3", "0xf6313962096b23d1",
|
||||
"0xc82d75c830055863", "0x8933404595905aac", "0x8edb7eab7c52d898", "0xe18afb092d408221", "0x00e2ff8b85b0f958", "0x138c26a6b2a01fa9", "0xf149c5571b8a011e", "0x7b4e2cbed63486fa",
|
||||
"0xb8aa812f44e45ed5", "0x61e2ceb11adede7b", "0x86dda499d4f04da5", "0x9b97c751cc58b065", "0x8d4fdd8fa6de313f", "0xd01cbad514f3184f", "0x41313afa438ff648", "0x3d2e3f3816471876",
|
||||
"0x465cc98a2fddec00", "0x268e1eb581c20a56", "0xb4cd4af84b66c5da", "0x69ccaa63aab033ee", "0x20b53d1e00c359e9", "0xd6a3c40b2e86712d", "0x6bbb5a2bd570bb00", "0x2aa8b2436df218ed"
|
||||
]},
|
||||
{"base_nonce": 4096, "expected": [
|
||||
"0x39a9f8aba6a9c7ab", "0xf1daab939a9c3217", "0x5831fcce18c03b2f", "0xb8ff659519b96eed", "0x88d08144f09ffb22", "0xa373485c22133291", "0xfc82bfd2743de9db", "0x19dffd993bf1a1a3",
|
||||
"0xec61385b02ed1eec", "0xe3a705fedd476c62", "0x012af0af0abd2f1b", "0xacbfc40c16d1c409", "0x64e16756a429ee6a", "0x9a8b8c542b85d64b", "0x95b962ec795480c1", "0x11a35a7657f86c66",
|
||||
"0x4ae11f4a8b22a8ed", "0x649bd0de4210bbb2", "0xd9e81d1e0c794619", "0x865a6073aeaad870", "0xcc691a4eb315ed94", "0x7bdf6b0662f171e6", "0xde979c126cd8b9a8", "0x801a11f95defd5ba",
|
||||
"0xe0b160c42c39df59", "0x2319e68444cacb1b", "0xd8beee32eb63a71e", "0x272e524e202c58db", "0xeefad04ef941e833", "0x98b08bb5658177b1", "0xeb6833af292f958e", "0xb6b358ffd3b2de03"
|
||||
"0xc3c344c2ff16bff0", "0x537b196cd4cdbb09", "0x65fca37074e405f4", "0x072f943a4caffb36", "0x662266cf8de82a8a", "0xb860ab3d16ae86f7", "0x5f98e443ce34f1bb", "0xce1c9ca2339c0e42",
|
||||
"0xccd68b4df195bbc9", "0x2866b38d4a401168", "0x9786a1957c75e7ad", "0x3ec5fc87c207ce1a", "0x1fce372f3838e249", "0x0dde9ad1dc8938a3", "0xed1579fda990b570", "0x66bcd22759864a63",
|
||||
"0x414d18a7c2507713", "0x0baddd09cc36a520", "0x8cd11f2ce02057b2", "0x8d898aac85fd75aa", "0xea1acc6c93538ab9", "0x5d05a096b6bb636e", "0x87e90c4240907c75", "0x049242a31f44ee9a",
|
||||
"0x2d0f84f4dd7cbfa8", "0x87694b7df4a79af1", "0xaaaafbe9f79bc92d", "0x300a667ee303c8d5", "0x2666fabf6267e27f", "0x198602472c92fcad", "0xa59eeed45b81af4a", "0x22d7d46002bc7e7f"
|
||||
]},
|
||||
{"base_nonce": 1000000, "expected": [
|
||||
"0xb4835ddebdbfbaeb", "0x05ececfd8ef508cc", "0x4bc1315c1b1ce4c8", "0xe13eca621f2ff598", "0x6fffb12762010b6c", "0x78139a212e0870ee", "0xe9e197bebebbce63", "0xb485f4c5f50377bd",
|
||||
"0x1284446e016546c1", "0xa2e4a3aefd217a73", "0xa484b974f813abb7", "0xf9959eac63a1401c", "0x77b081fd93294af8", "0x1fc7fc1eb3d9eaab", "0x71c51d4214cb47f0", "0x52171833d8d341f0",
|
||||
"0x5699e6eae25c5854", "0x34752dd16c6ce88f", "0x353dd3b0890ba109", "0x696b0afc8f6fe70e", "0x2b30eaa48b77cd0c", "0x6c600c3b87409c38", "0x26ead9ba20d15168", "0xc93e5f5a261bc786",
|
||||
"0x8606f09c2c74c81c", "0x1b3f9792e5247d66", "0xf8bb901d0dd87bfa", "0xbc939e016a57b734", "0x7bbbffc2dbcbc12a", "0x51beb5108f2ae2a4", "0x37b252067e6cc262", "0xf038a9ff99426f88"
|
||||
"0xfcb7fbc29dad03d4", "0x54b64718d6fdcc0d", "0x9c938236394bba35", "0x7c9b920dd87181bb", "0xe61f6268c5e7e8a0", "0xf7c2cfd988090e76", "0xaec2e24e7050a52a", "0x37ffb04710cce394",
|
||||
"0x03046fa86bf21b62", "0x00785f0d4ed2331a", "0x321a6fa31bc9b391", "0xdf88e6417dec1c9e", "0x1b6ec67bbcd424d6", "0xa247dc89c7f3cc6b", "0x1475f9ac604490b1", "0x106637b278da24a8",
|
||||
"0xa697188fec6bdb0a", "0x7e4c0201314281a7", "0xa8c7742d814fc0d1", "0xb07431c74a4506e3", "0xa9d8974c47e028cb", "0x42189e4fdd512dc5", "0xc6fe11a9e9153822", "0x4ea57f7253864742",
|
||||
"0xaabc3663cf578aef", "0xf28f68780e809bfe", "0x2df16b27d9eb162e", "0x0f8ccb24b6ab2297", "0x863b7048b78f5453", "0x63652a33014e3f00", "0xb107d73ffd8431ff", "0xcd7d8e5f0bc30687"
|
||||
]}
|
||||
],
|
||||
"dataset_head": ["0x19c6837f", "0xdf3adfb8", "0xbd3f6aed", "0xb8bede0d", "0xc5f0629f", "0x03e38ae8", "0xc435a60e", "0xfadee916", "0x827e59af", "0x8cf592f5", "0x60286061", "0x5d9abc1c", "0xa85d0c39", "0x4247a100", "0xd41a5b0d", "0x3f33dc64"],
|
||||
|
|
|
|||
Loading…
Reference in a new issue