ECO-05 reported as found beside the coexistence result (the standard's new-entry test FAIL on a frozen register, its labels and files) on the litepaper and the facts row

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

site/litepaper.html

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         <p>Three statements, kept separate. The baseline is the hash as it stands under the scoring rule; rotation is an optional improvement to that baseline, not the mechanism the claim rests on.</p>
         <div class="tbl"><table><thead><tr><th>Statement</th><th>What it says</th><th>Label and date</th></tr></thead><tbody>
           <tr><td>Energy resistance</td><td>Per machine against a locked RTX 5090, node for node and a node ahead: the DRAM board 1.5x to 1.6x (1.3x to 1.7x) and 1.8x; the board with SRAM holding the hottest half of the dataset 1.9x to 2.1x and 2.4x to 2.6x; the SRAM-store die 2.3x and 3.1x; across the adversary’s lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x, so about 2x on the same node stands at the bracket’s top; per dollar of hardware at list price 3x to 6x (modelled on the placed full 18-family core, routed 8 October 2026, and the 32-lane core’s synthesis). The honest tier moves to the next node with every GPU generation; a chip must tape out again. Whole machine per tier (synthesis with the SRAM band and node factors, claimed; placed rows to follow): the complete GDDR7 machine about 1.8x the RTX 5090 at its lock per joule node for node and 2.1x a node ahead; 1.6x and 1.9x the RTX 5080; 2.8x and 3.3x the Ada, Ampere and RX 9070 XT cohort; about 1.5x the Apple tier, reported, never headlined.</td><td>MODELLED: placed and routed core energies against the measured RTX 5090 lock row, 8 October 2026, no chip measured</td></tr>
-          <tr><td>Economic resistance</td><td>Whether a chip gets built depends on development cost, deployment economics and productive hardware lifetime. The first cut of the profitability surface: the price at which a project pays scales as the project cost over its share of the chain times its discounted life, and moves by under 5 percent with the per-joule edge; a fixed-lane chip under rotation needs 4x the price a programmable one needs. No threshold is the headline: the five-year coexistence model (Deliverable 4; its first run is <code>docs/analysis/class-v6/coexistence-model.md</code>, every row modelled) replaces any capex wall: the DRAM board passes six of its seven success conditions at a one to three year life; the SRAM die fails four conditions at its reconciled machine cost; the larger half of a chip's edge is capital cost per accepted hash, not joules. The result, as the model words it: A specialised supplier may earn a normal return; ordinary GPUs remain sufficiently close in total cost, widely obtainable and useful outside mining that new operators can still compete. On today's modelled rows that holds for the chip anyone can build, a stored-dataset board on commodity DRAM, at a productive life of one to three years: its cost per accepted unit of work sits within the range of the best GPU owner and entrant, it passes six of the seven conditions (a third of the network in boards now costs less than a year's revenue at the final hardware price), and a fleet of it holds a minority of the network with GPU entrants still setting the price. For the SRAM-store die the outcome turns on its hardware cost per unit of work, not its energy advantage: at the reconciled machine cost, set by the power train and the shadow core rather than the die, it fails the cost, hardware, fleet and margin conditions at every point of the band, a modest fleet holds about two fifths of a growing network and three fifths of a flat one on arrival and takes every flat or shrinking network within five years, and the only coexistence-shaped outcome is private supply in a growing network; what holds it is the investment decision, since its economics are project economics. A third design, a DRAM board with the hottest half of the dataset in on-board SRAM, sits between the two: it coexists only in a growing network at cheap GPU electricity and fails the cost conditions in a flat or shrinking one, and the dataset's size floor is a real lever on it where it was none on the SRAM die. What holds the die is the investment decision, not the hash; every chip figure here is modelled, not measured, and the chip's hardware cost per unit of work is approximate within 2x. The model holds under every market structure for the DRAM board (private supply, hardware sales, multiple suppliers, with no single supplier above a quarter of the network), and the SRAM die under none but private supply in a growing network; the thresholds live in the model's sensitivity workbook (<code>docs/analysis/class-v6/coexistence-workbook.md</code>), never on a page.</td><td>MODELLED, the coexistence model's first run, 8 October 2026</td></tr>
+          <tr><td>Economic resistance</td><td>Whether a chip gets built depends on development cost, deployment economics and productive hardware lifetime. The first cut of the profitability surface: the price at which a project pays scales as the project cost over its share of the chain times its discounted life, and moves by under 5 percent with the per-joule edge; a fixed-lane chip under rotation needs 4x the price a programmable one needs. No threshold is the headline: the five-year coexistence model (Deliverable 4; its first run is <code>docs/analysis/class-v6/coexistence-model.md</code>, every row modelled) replaces any capex wall: the DRAM board passes six of its seven success conditions at a one to three year life; the SRAM die fails four conditions at its reconciled machine cost; the larger half of a chip's edge is capital cost per accepted hash, not joules. The result, as the model words it: A specialised supplier may earn a normal return; ordinary GPUs remain sufficiently close in total cost, widely obtainable and useful outside mining that new operators can still compete. On today's modelled rows that holds for the chip anyone can build, a stored-dataset board on commodity DRAM, at a productive life of one to three years: its cost per accepted unit of work sits within the range of the best GPU owner and entrant, it passes six of the seven conditions (a third of the network in boards now costs less than a year's revenue at the final hardware price), and a fleet of it holds a minority of the network with GPU entrants still setting the price. For the SRAM-store die the outcome turns on its hardware cost per unit of work, not its energy advantage: at the reconciled machine cost, set by the power train and the shadow core rather than the die, it fails the cost, hardware, fleet and margin conditions at every point of the band, a modest fleet holds about two fifths of a growing network and three fifths of a flat one on arrival and takes every flat or shrinking network within five years, and the only coexistence-shaped outcome is private supply in a growing network; what holds it is the investment decision, since its economics are project economics. A third design, a DRAM board with the hottest half of the dataset in on-board SRAM, sits between the two: it coexists only in a growing network at cheap GPU electricity and fails the cost conditions in a flat or shrinking one, and the dataset's size floor is a real lever on it where it was none on the SRAM die. What holds the die is the investment decision, not the hash; every chip figure here is modelled, not measured, and the chip's hardware cost per unit of work is approximate within 2x. The model holds under every market structure for the DRAM board (private supply, hardware sales, multiple suppliers, with no single supplier above a quarter of the network), and the SRAM die under none but private supply in a growing network; the thresholds live in the model's sensitivity workbook (<code>docs/analysis/class-v6/coexistence-workbook.md</code>), never on a page. A failure, reported as found: Under the approved acceptance standard’s stricter new-entry test, run on a register frozen before any result, the chain fails as it stands: across vendors, sustained new entry on this hash exists only at the cheapest tariff and the largest revenue, because the measured AMD and Intel cards cost four to six times a Blackwell card per joule, and in the one sustainable world no specialised design sits inside the envelope against the whole cohort; the failure rests on those measured energies and the test’s cohort-wide median, not on a small network, token appreciation or any chip’s death, and it is reported as found. (ECO-05, RUN: FAIL against P12’s envelope, 8 October 2026: the register frozen at 18:37 UK, the cube modelled on measured card rows, two cohort rows BLOCKED, the RX 7600’s knee and the Arc’s watts; the results file docs/analysis/class-v6/eco-05-results.md.)</td><td>MODELLED, the coexistence model's first run, 8 October 2026</td></tr>
           <tr><td>Response capability</td><td>Rotation is an optional improvement, not the mechanism. A passed rotation boundary proves the rotation works, not that hardware dies. The schedule: a new program every hour, a parameter era every week, a family epoch every 180 days, an emergency vote when miners call one. Rotation costs a chip versatility, not life: the family bank is firmware plus about 43 percent of core cells, and no transition carries an obsolescence credit (modelled).</td><td>measured per boundary, 8 October 2026; the family-bank cost modelled, 8 October 2026</td></tr>
         </tbody></table></div>
         <p>What a miner sees from this. Class v4 costs a 5090 145 W more unlocked, 88 W more at a 1,400 MHz core lock and 82 W at the best operating points (class v4 at 1,200 MHz, class v3 at 1,300; the knee is 1,300 MHz on both), for 0.2 percent more rate (measured, 7 October 2026; the 80 W read on 6 October was at the app's tuned cap); an M5 Max 16 W more for 1.5 percent, an RX 9070 XT and an RTX 4070 nothing (measured, 6 October 2026). The ladder that sets how much work rides in the shadow starts at rung 0 at genesis and climbs by miner signal; its third rung is inadmissible today because a server core verifies it in 10.85 ms, over the gate (measured, 7 October 2026). The devnet runs class v4 from its first block. Classes rotate on findings and at least yearly; a class change is a release activated by block height. Class v5 is built to cross by height; its dataset keyed by the chain's own state is under evaluation (Deliverable 3) and is not counted as a defence until justified. Class v6 is the design in progress (opened 8 October 2026), with four layers as its spine: per-era draws of the parameters a release now fixes, a dataset whose size tracks the chain state (under evaluation, Deliverable 3), scheduled family epochs by height, and the acceptance floor generalised to every era’s draw. The next test of the model is an internal adversarial pass, not an independent review: three lanes that have never worked on the hash code attack the mixer, the chained cache and the acceptance rule with only what an outsider has (the public kit, the frozen object, the spec, the harnesses) and publish the break or the bound they reach. No outside review has run yet.</p>