From 3c0f80d835fd8606461fad9b6bd73329d423ee73 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:20:52 +0000 Subject: [PATCH 01/11] Class v6 invention lane: first cut of docs/analysis/class-v6/invention.md (every candidate layer beyond the four with its paragraph, known-failed harness run and chip row; the sound per-load shadow measured today: 0.927 rejection per candidate on 256 seeds, verifier 8.3 to 8.8 ms loaded, two packs exported; the per-load prototype's era-window instrument fault found; the ranked list: per-load placement, register width, warp-uniform block selection, the reserve's order), the census script and its two TSVs Co-Authored-By: Claude Fable 5.1 --- docs/analysis/class-v6/invention.md | 256 ++ docs/analysis/class-v6/logs/census-era.tsv | 2817 +++++++++++++++++++ docs/analysis/class-v6/logs/census-none.tsv | 2817 +++++++++++++++++++ tools/attack/v6-invention/v6inv-census.sh | 29 + 4 files changed, 5919 insertions(+) create mode 100644 docs/analysis/class-v6/invention.md create mode 100644 docs/analysis/class-v6/logs/census-era.tsv create mode 100644 docs/analysis/class-v6/logs/census-none.tsv create mode 100644 tools/attack/v6-invention/v6inv-census.sh diff --git a/docs/analysis/class-v6/invention.md b/docs/analysis/class-v6/invention.md new file mode 100644 index 000000000..a46c2669f --- /dev/null +++ b/docs/analysis/class-v6/invention.md @@ -0,0 +1,256 @@ +# Class v6 invention lane: layers beyond the four, each priced against the chip that stores the dataset + +8 October 2026, first cut 11:1x to 13:xx UK (BST, the Mac's clock; the boxes print CEST, one hour ahead, and nothing below is stated in box time), branch `class-v6-invention` from the mirror's master at 17d61d52, research lane C under the Counter ASIC coordinator. The founder's word of 11:1x UK: class v6 is declared with four layers as its spine (per-era draws of the released parameters; the state-derived dataset's size tracking chain state with a floor; scheduled family epochs every 180 days with no release; the acceptance floor and the F8-form uniformity test generalised to each era's draw), and deep research opens: "see if anything can be optimised, added or invented". This file is the invention lane's answer: every candidate layer beyond the four as one paragraph, one known-failed test stated as a harness run, and one chip-model row, then the ranked list of what v6 should add. The synthesis is the research lane's `docs/design/class-v6-rotating-family.md` (branch `counter-asic-4`), which reads this file. + +Status: a research document and a gate plan. No consensus code this week; nothing here touches the devnet, the testnet object, the spec or any served page. Every number carries a label: **measured** (a run on a named box or card, the log named), **modelled** (arithmetic on the chip model's cited figures, `docs/analysis/chip-model-v3.md` section 5), **claimed** (a vendor's or an author's figure, URL and date), **approximate** (from memory or a scaling). The rule every candidate is held to: **reject what costs GPUs more than it costs chips, and say so with the number; keep what raises a chip's k or capex or shortens its useful life more than it raises every GPU tier's cost.** + +## 0. One page + +The frame is last night's identity (`docs/analysis/counter-asic-4-research.md` section 2): against the chip anyone builds, a GPU's memory system without the GPU (chip-model-v3 section 5.5, the `f = 1` chip), the per-joule edge is `(E_card + F) / (E_mem + k F)`, with `F` the premium per hash the card pays for forced work and `k` the chip core's energy per forced op over the card's. Zero premium is zero forcing. No hash-side design reaches a chip edge of about 2x at zero premium; the premium-free floor is the card's own whole-card energy over the chip's memory energy, 3.6x on a 5090 at its knee (measured card, modelled chip), and the class v4 shadow buys 2.1x at `k = 1` for 82 to 90 W on a 5090. The four layers of v6 render a fixed-function chip useless on its release day and move nothing in the identity for the GPU-like chip. So an invented layer can do one of four things, and only four: raise `k` (nothing on measured rows reads `k` above 1, section 15.1a of the research file); raise the chip's capex or project cost (the one lever the identity does not see); shorten the chip's useful life (layers 1 and 3 already do this for fixed silicon); or cost the honest cards less at the same `F`. Every candidate below was read against those four. + +What was measured today (all on igneum-build-1, the counter-asic-4 crate at 5984ffab, logs under `/srv/builds/v6-invention/`): + +| Reading | Number | Label | +|---|---|---| +| The sound per-load shadow (one pass of a 256-instruction sub-block after every load, `mx8+shl4096x1`), the form 20.2a-close named and never drew | 234 of 256 seeds accepted within the 32-attempt cap, 0.927 rejection per candidate, mean accepted attempt 9.7; the iterated 16 x 27 form on the same seeds 76 of 256, 0.989 per candidate | measured (section 3.1) | +| The same at class v4's instruction count (`mx8+shl2304x3`: 16 sub-blocks of 144, three passes, 55,296 shadow instructions per hash) | 224 of 256 seeds, 0.935 per candidate | measured | +| The verifier on the sound forms, cold warp on core 40 with core 88 loaded (the ladder's method) | shl4096x1 8.28 to 8.55 ms; shl2304x3 8.44 to 8.82; class v4's shape 8.33 to 8.63 on the same core in the same minutes; all under the 10 ms gate | measured (section 3.2) | +| The per-load prototype's acceptance under a drawn era | 0 of 256 seeds on every per-load form: 5,536 of 7,862 bias rejections name index bit 26 or 27 "set in 0 or 16,384 of 16,384", the era WINDOW's fixed top bits, an instrument fault; so 20.2a-close's "1.4 percent accepted, 42 of 64 seeds exhaust" (run across drawn eras) measured the instrument, not the construction | measured; a correction for the research file (section 3.3) | +| The two packs for the card row | `mx8_shl4096x1` (id 75ca9547da21b200) and `mx8_shl2304x3` (id bbfdfc1dcdda0b46), OVERALL PASS, in the hash lane's PC 1 job after the AMD grid (about 12:45 UK) | exported; the card row owed | + +**The ranked list of what v6 should add beyond the four** (section 4 has every column): + +| Rank | Layer | What it does to the chip | What it costs the cards (5090 / 5070 Ti / M5 Max) | Status | +|---|---|---|---|---| +| 1 | **Layer 5: the shadow placed per load, one pass of a long sub-block** (the capex lever: the chip's core must sit inside every read's dependency, so controller, lanes and PHY share one N5-class die or an interposer) | energy edge unchanged (`k` is `k` whichever die the core sits on); project cost about USD 30 M to about 60 M, the break-even market cap about USD 100 M to about 200 M (the mission lane's model, modelled); capex per MH/s 3.0 to 4.3 USD (modelled) | 5090: the 16 x 27 form measured 13 to 14 W UNDER the whole block at the same instruction count (448 against 462 W unlocked; 283 against 296 at the 1,300 lock), rate within 1.2 percent; the 256 x 1 form's row in today's PC 1 job / no row, the 4070's 30 W premium at its tune point as the proxy / the 16 x 27 form -0.5 percent of rate measured; the 256 x 1 form's Metal footprint OWED | acceptance measured today (0.927 per candidate, P(exhaust at 256) about 4 x 10^-9); the sub-version 3 dataflow rule in execution order is the fix that brings it toward v4's 0.68 (gate plan, section 2.1) | +| 2 | **Layer 6: register-file width drawn per era (8 to 32 registers per lane)**, the link tax on layer 5 | with layer 5, the lane state crossing the controller twice per read grows from 64 B to 128 to 256 B: 2.2 to 9 TB/s of die-to-die traffic at the 5090's read rate, past any one-stack interposer, which closes the "or an interposer" branch and forces the single N5 die (modelled); alone, nothing | 0 rate on every card while latency-bound (a GPU lane holds up to 255 registers; 7,262 lanes x 256 B is 1.9 MB against the 5090's 43 MB of register file, approximate); the verifier's register-major arrays 4x (unmeasured, under 0.1 ms by the op law); no pack form today (the register count is a generator constant) | modelled; the pack form is a generator change with its own census (gate plan) | +| 3 | **Layer 7: warp-uniform data-dependent block selection** (which of B shadow sub-blocks runs next is chosen by a warp-reduced register value, uniform across the 32 lanes, so no divergence) | nothing for the GPU-like chip (a sequencer already); an FPGA overlay or a fixed pipeline must hold all B blocks for one block's throughput: B x the shadow's LUT area (approximate); shortens a per-epoch bitstream's worth | one uniform indirect branch per iteration: about 0 (the `sel` register already does this for the immediates); verifier 0 | modelled; a generator change behind a pack (gate plan); rank 3 because it moves the FPGA lane only | +| 4 | **The reserve ordered by hardware orthogonality** (layer 3 as it stands, with the order fixed: shuffle-crossbar families, then byte-permute, then popcount and priority encoder, the int8 tile last) | a chip pre-wires every family for about USD 4 of N5 (modelled); the order makes the first unlocks the ones a 12-op datapath lacks most | 0 at 4 points (measured step costs under 1 percent of ALU time on every vendor) | an ordering rule inside layer 3, not a new layer; the history's addition 6 | + +Rejected with the number, each in section 2: per-lane data-dependent branches (divergence costs the card, a chip nothing); reads tied to the shard proof per block (a refresh per block is 0.3 to 1 W on a chip, 1.3 percent of a 4090's hash time); randomised memory topology (a chip's address decoder permutes its lines for nothing; the stride and interleave are already drawn); the VRAM-size ratchet as a lever (a chip buys 24 to 32 GB that the 8, 12 and 16 GB tiers cannot: it retires cards first); proof-carrying hashes sampled by the pool (the chip holds everything the witness proves); prover-gated eligibility (proving is 1.6 kW network-wide at any hash rate, 0.7 percent of the hash's energy at 100 GH/s); time-locked parameter commitments beyond the era VDF (the drawn band is firmware; the 2-hour lead already denies the fixed chip 180 days); a fraction of reads derived from the cache (the 5090 loses about 30 percent of rate, the chip 7 percent of energy); row-straddling reads (the w64 regime, 47 percent of the 5090's rate); a refresh per block (dead by arithmetic, the research file's row 7). + +Per tier, in one line each: a home miner on any card sees no change from anything here today (nothing ships; the devnet pays nothing); the 5090 tier's one number is that the per-load placement costs it LESS than class v4's whole block at the same work (13 to 14 W measured on the 16 x 27 form, the 256 x 1 form's row due about 12:45 UK); the 5070 Ti has no measured row in this lane (the 4070's rows are the proxy, approximate); the Apple tier's open question is the inline footprint of a 4,096-line block per iteration (the 1,024-line block cost the M5 Max 17 percent on 6 October, measured), which decides whether rank 1 needs a block-shape cap for Apple; a pool user sees nothing; a node verifies the per-load forms in the same 8.3 to 8.8 ms as class v4 (measured); a chip maker sees its project forced onto one advanced die by rank 1 and its interposer escape closed by rank 2. + +## 1. The frame, and what a candidate must do + +| Term | Value, 5090 at the 1,300 MHz knee | Label | Source | +|---|---|---|---| +| `E_card`, class v3 | 1.67 microjoules (127.3 MH/s at 213.0 W; 134.6 at 223.3 on the efficiency pass) | measured | research file 20.3 and the status file's efficiency pass | +| `E_mem`, the `f = 1` GDDR7 chip | 0.466 microjoules (16 devices, 166 MH/s at 78 W); one HBM3 stack 0.321 | modelled | chip-model-v3 5.4 | +| `F`, the class v4 shadow's premium | 0.652 microjoules (82.8 W over 126.9 M hashes x 102,100 ops: 6.4 pJ per counted op) | measured | research file 20.3 | +| The edge at zero premium | 3.6x (GDDR7), 5.2x (one HBM3 stack) | measured card, modelled chip | section 2 of the research file | +| The edge with the shadow | 2.1x at `k = 1`, 2.9x at `k = 0.5`, 3.5x at `k = 0.3`; the honest `k` band for an ALU-shaped core 0.3 to 0.8 | modelled on measured rows | 20.4 | +| The chip's capex | USD 470 of memory, controller and board per 166 MH/s: 2.8 USD per MH/s; plus the shadow core USD 25 to 40 (3.0 to 3.1); plus an interposer USD 200 (4.3); a 5090 at MSRP 14.7, at the 2026 street price about 29 | modelled; the card price measured | 16.1 | +| The project cost and the break-even cap | a 28 nm controller USD 5 M (cap about 17 M); plus an N5 shadow core USD 30 M (cap about 100 M); the core forced onto the controller's die or an interposer USD 60 M (cap about 200 M) | modelled (the mission lane's model, s = 0.30) | 16.2 | + +The four doors, and the one each candidate must walk through: + +1. **Raise `k`.** Measured on the 5090 (15.1a): the int32 ALU op 6.2 to 11.3 pJ against a 5 nm SIMD array's 2 to 5 (k 0.3 to 0.8); the shuffle 29 to 56 pJ against a crossbar's about 20 (k 0.4 to 0.7, and the card pays 5x the add per op); the int8 tile 0.8 to 4 pJ per MAC against an array's 0.04 to 0.4 (k 0.03 to 0.3); an L2 hit 1.4 to 2.4 nJ against on-die SRAM's 0.2 to 0.5 (k 0.1 to 0.3). Nothing reads above 1. A candidate that claims to raise `k` must name the block and the measured GPU cost per op it rests on. +2. **Raise the capex or the project.** The hash's dataset is a card's worth of DRAM and its work a fraction of a card's logic, so per-unit capex cannot pass about 4.3 USD per MH/s (16.1); the project cost is the lever that moves the break-even cap, and the only mechanism found for it is forcing the shadow core into every read's dependency (16.2). A candidate here is priced by which die it forces. +3. **Shorten the useful life.** Layers 1 and 3 kill fixed silicon at the first draw outside its wired value; a GPU-like chip's life is its memory's and its node's. A candidate here must move the GPU-like chip, or it is layer 1 again. +4. **Lower the honest card's cost at the same `F`.** The operating point (the knee lock) is the miner's lever, not the protocol's; a protocol lever here is a shape that runs cheaper per instruction on the card (the 16-instruction block effect, 13 to 14 W measured) at the same chip cost. + +## 2. The candidates + +Each: the paragraph, the known-failed test as a harness run, the chip row, the verdict. The harness names: `v6inv-census.sh` is `/srv/builds/v6-invention-census.sh` on build-1 (a copy sits in this lane's scratch and lands under `tools/attack/v6-invention/` with the 09:00 report), the counter-asic-4 crate's `igneum-pow accept --class
` over seeds `igneum-v6inv/`; the F8 census is `tools/attack/f8-uniform` (`attack-f8 warps`, master); the chip row is the model's arithmetic with the GPU side measured where a pack ran. + +### 2.1 Layer 5: the shadow placed per load, one pass of a long sub-block (KEEP, rank 1) + +The class v4 shadow runs 256 instructions 27 times after instruction 63 of every iteration, where the next iteration's 64 base instructions and 16 loads stand between the block and every load, and a chip may run it on a second die with 64 B of lane state crossing once per iteration (140 GB/s at the 5090's read rate, a PCB link; 16.2). Placed inside every read's dependency the same work makes the lane state cross twice per read, 2.2 TB/s, an interposer-class link or one N5 die carrying controller, lanes and PHY, which the mission lane's model prices at a project of about USD 60 M against 30 M and a break-even cap of about 200 M against 100 M. The 16 x 27 form (16 sub-blocks of 16, each iterated 27 times) was built on 7 October and closed the same night: 27 passes of a 16-instruction map right before a load collapses or biases the load's address register before any base instruction can re-randomise it, and the acceptance rule in execution order refused it. The sound form named there and never drawn is one pass of a long segment per load: 16 sub-blocks of 432 instructions, each run once, the same 6,912 instructions per iteration. The experimental class caps the per-load block at 4,096 instructions, so today's census takes the two forms inside the cap that bracket it: `mx8+shl4096x1` (16 x 256, one pass, 59 percent of class v4's work per hash) and `mx8+shl2304x3` (16 x 144, three passes, class v4's exact count), and the constant-work ladder between them (16 x 256 x 1, 32 x 128 x 2 ... 16 x 16 x 16) that reads how the acceptance rate depends on the sub-block length against the pass count. The 432 x 1 form itself needs the cap raised, a one-line change in a research-only parser, which this lane does not make this week; its number is bracketed by the 256 x 1 and 144 x 3 rows and the ladder's flatness between them. + +Known-failed test, as a harness run: `ERA=none SEEDS=256 /srv/builds/v6-invention-census.sh` on build-1 under `lease pool 48`. Fail: a form whose per-candidate rejection is 0.98 or above (P(exhaust) at the 256-attempt cap above 0.5 percent, an epoch without a program every few months). The 16 x 27 form reads 0.989 and fails (section 3.1). Pass: a form under 0.95 (P(exhaust) under 2 x 10^-6). The 256 x 1 form reads 0.927 and passes; so does every form with a sub-block of 36 instructions or longer (0.927 to 0.949). The second known-failed case is the instrument's own: `ERA=era` on the same seeds reads 0 of 256 accepted on every per-load form, with the window's fixed top bits named as biased index bits (section 3.3); the fixed instrument (bits at or above `28 - k_off_s` excluded from the value-level test) must accept per-load forms under drawn eras at the no-era rate within the binomial band, and still refuse the per-load record of 7 October (candidate 0 of the first export, 1,482 duplicate lanes). + +Chip row: + +| Column | Value | Label | +|---|---|---| +| A fixed-function chip's `k` | unchanged (the work is the same ALU mix); its capex: the controller cannot be a 28 nm part with the core elsewhere, so the project moves from USD 5 M (no core) or 30 M (a core on its own die) to about 60 M (one N5-class die or a 2.5D package); break-even cap about USD 200 M in years 1 to 2 (s = 0.30) against about 100 M | modelled (16.2, the mission lane's N3 single-die row; a GDDR7 PHY on N5 is unpriced) | +| A GPU-like chip's per-joule edge | unchanged: 2.1x at `k = 1`, 3.5x at `k = 0.3` at the knee; its capex per MH/s 3.0 to 4.3 USD against 2.8 | modelled | +| RTX 5090 | the 16 x 27 v2 export: 135.90 MH/s at 448.3 W unlocked against the whole block's 137.51 at 462.2 (the premium 137 against 151 W, -14 W); at the 1,300 lock 126.04 at 282.9 against 126.93 at 295.8 (-13 W); the 256 x 1 and 144 x 3 forms in today's PC 1 job (the hash lane, after the AMD grid, about 12:45 UK) | measured (research file 20.3); the sound forms' rows owed | +| RTX 5070 Ti | no row (no card in this lane); the 4070's class v4 premium at its tune point, 30 W for no rate, less the block effect, is the proxy | approximate | +| Apple M5 Max | the 16 x 27 v2 export 26.88 MH/s against 27.01 (-0.5 percent, Metal packbench, 7 October); the 256 x 1 form's inline text is 4,096 shadow lines per iteration where the 1,024-line block cost the M5 Max 17 percent (6 October, measured), so its footprint is the open Apple number: OWED (a Mac measurement under the measure lock, which this lane does not run; the hash lane's or the shipper's Metal row) | measured for 16 x 27; the sound form's row owed | +| The verifier | 8.28 to 8.55 ms cold with the sibling loaded (256 x 1), 8.44 to 8.82 (144 x 3), against class v4's 8.33 to 8.63 on the same core in the same minutes; the acceptance's dynamic test 35 ms per candidate (1,111 ms for 32), 13.7 candidates per seed on average: about 0.5 s of one core per epoch | measured (section 3.2) | +| The acceptance | 0.927 per candidate (256 x 1), P(256 consecutive rejections) 0.927^256 about 4 x 10^-9 per seed; class v4 sub-version 3 reads 0.681 and 2 x 10^-43; the gap is the missing dataflow rule (the per-load class is not the class v4 shape, so (a'), (c') and (c'') do not run on it; the value-level bias test catches the same population: 1,563 of 2,329 bias rejections name index bit 0 at a one-count near 4,096 or 12,288 of 16,384, the product's low-bit law) | measured (section 3.1) | + +Verdict: KEEP as layer 5, the first thing v6 adds beyond the four, because it is the only mechanism found that moves the project cost, it costs the 5090 less than class v4's own block (measured on the 16 x 27 form; the sound form's row today), and its acceptance is now a measured 0.927 with a named fix (the sub-version 3 dataflow fixpoint run over the real execution order, base and sub-blocks interleaved, as the generator's draw rule) that the research file's 20.2 already asked for. What it does not do: move the energy identity by one joule. The founder's "useless as soon as it dropped" is layer 1's and 3's sentence; layer 5's sentence is "the chip that can be built costs twice as much to start". + +### 2.2 Layer 6: the register-file width drawn per era, the link tax on layer 5 (KEEP, rank 2) + +The hash runs on 8 registers per lane, a prototype value to be fixed at gate 1 (spec 1.4). The lane state a chip must carry is those 8 words plus the nonce and counter, 64 B, which is why the chip's 1,172 lanes are 73 KB of SRAM and why, under layer 5, the per-read crossing is 128 B at 17.5 G reads per second, 2.2 TB/s: an interposer carries that (a one-stack HBM package moves about 0.8 to 1.2 TB/s of memory traffic and a die-to-die link of a few TB/s is a 2.5D product; approximate, from memory), so the chip has an escape at USD 200 of package instead of one die. Draw the register count per era from {8, 16, 32} (the acceptance rule's part (b) over every register; the program length scaled so that every register is written, or registers above 8 initialised and read by the shadow alone) and the crossing is 128 to 256 B per lane per read: 4.5 to 9 TB/s, past the interposer class, so the single die is forced and the project's USD 60 M row has no cheaper branch. A GPU pays nothing in rate while latency-bound: a CUDA lane holds up to 255 registers, the 5090's 7,262 lanes in flight at 256 B are 1.9 MB against about 43 MB of register file (170 SMs x 256 KB; approximate), and occupancy at 32 live registers plus the kernel's temporaries fits the 64K-register SM at full residency (approximate, unmeasured). The verifier's register-major arrays grow 4x (4 KB per warp) and the interpreter's cost per op does not move. + +Known-failed test, as a harness run: the generator with `REGISTERS` as a class field (a research-only change behind a pack name, `mx8+r32`), then `v6inv-census.sh` over the per-load forms at 8, 16 and 32 registers. Fail: the 32-register form's per-candidate rejection above the 8-register form's by more than the binomial band (more registers, more cold registers, more (b) rejections unless the program length scales). Pass: rejection at or under the 8-register form's; the F8 census at 2^24 on 64 seeds within 1.2x of the window model (the top 0.1 percent of items); the cold verify on core 40 with core 88 loaded under 10 ms. Then the card: one pack per register count on the 5090, rate within 1 percent of the 8-register pack at both states (the occupancy claim measured, not argued). + +Chip row: + +| Column | Value | Label | +|---|---|---| +| A fixed-function chip | with layer 5: the lane state per read 128 to 256 B, 4.5 to 9 TB/s of die-to-die traffic at the 5090's read rate; the interposer branch (USD 200 of package) closed, the single N5-class die forced; the project about USD 60 M either way, but with no cheaper escape; alone (without layer 5): nothing, the state crosses once per iteration | modelled, the link figures approximate | +| A GPU-like chip's per-joule edge | unchanged; its lane SRAM 73 KB to 300 KB (nothing) | modelled | +| RTX 5090 / 5070 Ti / M5 Max | 0 rate while latency-bound (approximate: the occupancy arithmetic above; a measurement is the pack); watts: the same `F` (the same ops) | approximate until the pack runs | +| The verifier | 4x the register arrays per warp (4 KB); cost per op unchanged (0.1 ns per lane-instruction, the shadow's law) | modelled | +| The acceptance | part (b) over 16 or 32 registers needs the base program to write every register: at 64 instructions over 32 registers about 13 percent of registers are never written (approximate, e^(-64 x 0.75 / 32)), so either the base length scales with the register count (the verifier's 10 ms gate holds to about 330,000 ops) or the extra registers belong to the shadow alone and part (b) reads the base's 8 | modelled; the census decides | + +Verdict: KEEP as layer 6, conditional on layer 5 (alone it moves nothing). Its value is one sentence in the chip's project plan: no interposer saves the second die. + +### 2.3 Layer 7: warp-uniform data-dependent block selection (KEEP, rank 3, small) + +A program whose control flow depends on the data it reads is the brief's first candidate. Per-lane branches are dead on arrival: a divergent branch costs a GPU warp both paths and a chip with per-lane sequencers nothing (the history's "placed nowhere" table; RandomX's one predictable branch targets speculative CPUs, which Igneum does not have). The form that survives is warp-uniform: at the end of each iteration a value reduced across the 32 lanes by shuffles (xor-fold of `r0`, say, which costs 5 shuffles) selects which of B drawn sub-blocks runs next, the same block for every lane of the warp, so the GPU takes one uniform indirect branch per iteration (as `sel` already takes one per iteration for the immediates) and the FPGA overlay or the fixed pipeline must hold all B blocks and pay B times the shadow's area for one block's throughput. For the GPU-like chip, a sequencer that already runs the hour's program, it is one more jump. What it buys: the per-epoch bitstream (the FPGA lane, history addition 5) holds B blocks instead of one, so a mid-size part's compile (42 to 160 minutes, PRflow, claimed in spec 1.13.1) carries B times the logic; at B = 4 a part that fitted one block does not fit, and at B = 8 the overlay must time-multiplex. Nothing in the energy identity moves. The acceptance must run every reachable path (B blocks per iteration, each judged by (a') in its own order) and the uniformity census must read the selection's bias (a selection that favours one block is a block that runs more). + +Known-failed test, as a harness run: a research-only class `mx8+sh256x27+sel` (the generator draws B blocks, the interpreter selects per iteration from the warp-folded `r0`), then `igneum-pow accept` over 256 seeds with every path judged, and `attack-f8 warps` at 2^24 on 64 seeds. Fail: the block-selection histogram over the 2^24 nonces outside 6 sigma of uniform (a plant: select from lane 0's `r0` bit 0 alone, which the fold is meant to prevent), or any path's (a') verdict differing from the whole-program verdict. Pass: within the band, 60 of 64 seeds under 1.2x on the hot-set test, as class v4 reads. + +Chip row: + +| Column | Value | Label | +|---|---|---| +| A fixed-function chip or an FPGA overlay | B x the shadow's logic for one block's throughput, or time-multiplexing at 1/B the rate; a bitstream compiled per epoch carries B blocks | approximate (LUT area scales with the straight-line block; no FPGA row exists in the repo) | +| A GPU-like chip | nothing: one jump per iteration on a sequencer | modelled | +| RTX 5090 / 5070 Ti / M5 Max | about 0: one uniform branch per iteration, 5 shuffles per iteration for the fold (5 x 8 = 40 shuffles per hash at 29 to 56 pJ: 0.002 microjoules, 0.3 percent of `F`); the compile-ahead carries B x 256 instructions of text (B = 4: the 1,024-line footprint that cost the M5 Max 17 percent on 6 October) | modelled on measured per-op costs; the Apple footprint is the cap on B | +| The verifier | B x the acceptance's dynamic test per candidate (every path); the hash's cost unchanged | modelled | + +Verdict: KEEP, rank 3, with B capped by the Apple footprint (B = 2 or 4 at the 256-instruction block, or B = 4 at 64-instruction blocks, which the 6 October measurement says run 2.5 to 3.5 percent faster anyway). It is the only candidate that moves the FPGA lane, which the history ranks as the first adversary of a per-hour program (Lyra2REv2, X16R) and which no measured row in the repo has priced (the HBM FPGA row is 0.30x to 0.39x of a 5090 per watt, chip-model-v3 5.3, the soft-overlay case unmeasured). + +### 2.4 The reserve ordered by hardware orthogonality (KEEP as an ordering rule inside layer 3) + +Layer 3 unlocks reserve families by height and rotates after exhaustion. The order is Open in spec 1.13.2 except R1. The history's addition 6 said: families that force a full 32-bit datapath per lane first, the int8 tile last. Today's measured rows (research file 15.1a; the research lane's layer 3 table) sharpen it: a shuffle crossbar is the one block where the GPU's cost per op is highest (29 to 56 pJ) and a chip's is near it (about 20 pJ, approximate), so `shfla` (lane plus delta, a second crossbar form) is the family a 12-op chip lacks most and gains least on; byte permute and popcount next (small adders a chip adds for 0.1 pJ, but a datapath without them loses 4 points of the mix); the int8 tile last (k 0.03 to 0.3: a chip's MAC array is cheaper than the GPU's tensor core, so the tile is kept for datapath diversity and never for joules). The chip row is layer 3's: about USD 4 of N5 pre-wires all eight. Cost to the cards at 4 points: under 1 percent of ALU time on every vendor (measured step costs: shfla 1.91x on Apple, 1.53x NVIDIA, 0.75 to 0.84 AMD). Known-failed test: the layer 3 gate's own (a kernel built without the live family refused at packcheck; the fast-time harness crossing one family epoch with a stale miner, 0 accepted blocks after it). Verdict: not a new layer; an ordering rule, stated so the synthesis fixes it at genesis. + +### 2.5 Data-dependent program graphs, per-lane (REJECT) + +The brief's form: the program's control flow drawn from the data it reads, per lane. A GPU warp executes a divergent branch as both paths with lanes masked, so a branch taken by half the lanes doubles the ALU work of that span; a chip with a sequencer per lane pays the taken path only. Number: a shadow of 55,296 instructions per hash with one two-way branch per 64 instructions at 50 percent divergence costs the card up to 2x the shadow's premium (165 W instead of 83 at the knee on the 5090, modelled on the measured 6.4 pJ per op) for a chip cost of 1x; `k` on the branched work falls to 0.15 to 0.4. Costs GPUs more than chips. The warp-uniform form (2.3) is what survives. + +### 2.6 Latency-bound reads tied to the shard proof (REJECT) + +The hash's reads sampled from the state the miner is proving: class v5 already keys every item to a leaf of the execution state at the epoch's cut and refreshes per epoch (spec 1.8.6; proof of following). Tying the reads to the segment being proved means a refresh per block (every second) from the touched leaves. The research file's row 7 priced the refresh as a cost: a 1 GiB rebuild is 157 G ops, 13.4 ms on a 5090 and 32 ms on a 4090 (measured), 0.16 to 0.5 J on a chip core (1 to 3 pJ per op, approximate); per block that is 0.3 to 1 W against 78 W of chip hashing (0.4 to 1.3 percent) and 1.3 to 3.2 percent of a GPU's hash time (the rebuild stalls the hash on the card; the chip's rebuild runs on its core beside the memory). A delta refresh (only the touched leaves, a few KB) costs both sides nothing. Either way the GPU pays more or equal. What the tie would buy is liveness (a chip must follow the chain per block, not per epoch), which class v5's per-epoch refresh already gives at the WAN line of 2a.2. Number: GPU 1.3 to 3.2 percent of rate against a chip's 0.4 to 1.3 percent of energy. Rejected. + +### 2.7 Randomised memory topology per era (REJECT) + +The dataset's address map and stride family drawn per era: class v3 draws the stride multiplier `M`, the rotation `R` and the interleave `pos` per era already (spec 1.13.1, Counter ASIC 2.0 layers 4 and 8, decided IN at a six-era hash-rate spread of 1.3 percent on the 5090, 3.2 on the 9070 XT, 0.8 on the M5 Max, measured). The plan said then what still holds: a chip whose address decoder can permute its address lines pays nothing. Drawing a richer family (a per-era permutation polynomial over bank and row bits, a drawn item size, a drawn line interleave across devices) costs the chip's decoder a few hundred gates and costs the honest card whatever the mapping does to its own DRAM's bank parallelism: a mapping that concentrates consecutive dependent reads into one bank group hurts the side with fewer lanes in flight, which is the chip (1,172 against 7,262), but the chip adds lanes at 64 B each (lane state is free, chip-model-v3 5.5), so the asymmetry closes at no cost. The one topology lever that would have moved the chip, the hot region above the window model, was read by adv-cache-2 as the diffuse era-stride excess (a product's low bits placed at address bit `R`; 8 of 27 drawn-era programs over 1.2x), which is a FAULT the next class's value-level test removes, not a lever to keep. Number: 0 to the chip, 0 to 3.2 percent to the cards. Rejected; the existing draws stand. + +### 2.8 VRAM-size ratchet (REJECT as a lever; layer 2's floor stands) + +A floor that rises with chain state by rule is layer 2. The ratchet form (the floor tracking the modal miner's VRAM minus the prover footprint, or rising on a calendar faster than the schedule) was read against the card-lifetime table (`docs/analysis/card-lifetime-2026-10-05.md`, option (b) steps): the 4 GB tier ends at the 4 GiB step, 8 GB at 8 GiB, 12 and 16 GB at the 16 GiB step; a chip holds 24 GB (one HBM3 stack, about USD 200, modelled) or 32 GB (the 5090's own 16 devices, USD 320), so every step retires a card tier before it touches the chip, and at 32 GiB and beyond the chip adds devices and its activate-bound rate RISES with the bank count (chip-model-v3 5.7, row "dataset size": "not a lever against this chip"). Number: at the 16 GiB step the 8, 12 and 16 GB tiers are out (3 of 6 card tiers) and the chip's energy per hash moves 0. Rejected as a lever; layer 2's rule (the schedule as the floor, the state above it, a ceiling at the next cache doubling) is kept exactly as the synthesis writes it, with its honest line that it retires cards before chips. + +### 2.9 Proof-carrying hashes sampled by the pool (REJECT) + +A fraction of hashes carries a verifiable execution witness. Three witness forms were read. (i) The hash's own 128 item values: the stored-dataset chip has every item; the recompute chip derives them; cost 0 to both, 512 B per share on the wire. (ii) A Merkle witness of the state leaves under the window's root: the chip's node has it (one node serves a farm, class-v5 2a.2); cost 0 to both. (iii) A witness that the item was DERIVED (a transcript of the 8 dependent cache reads and the mixer's 72 applications): a stored-dataset chip cannot produce it without the cache and the mixer core, so this form forces the `f = 0` chip's silicon (the 256 MiB SRAM mirror, USD 46 of die and an N5 project) onto the `f = 1` chip for the sampled fraction `g`; but the honest GPU must produce the same transcript, and deriving an item on the card is 8 dependent 64-byte cache reads at the mixer's 9,360 ops (the inline kernel measured 4.8x slower than the honest kernel on the M5 Max, spec 1.8.5), so at `g = 1/128` (one item per hash) the card pays about 4 percent of its rate and at `g = 1/16` about 30 percent; the chip derives on an SRAM-resident cache at 6.3 nJ per item (modelled) for 7 percent of its energy at `g = 1/16`. Number: GPU 4 to 30 percent of rate against the chip's 1 to 7 percent of energy. Rejected on form (iii); forms (i) and (ii) force nothing. + +### 2.10 Prover-gated eligibility (REJECT) + +The block's eligibility tied to the miner's proving (a key must have proved its share of segments in the last window to claim a block), so a chip farm must carry provers. The bound is the gas bound the research file's section 7 found: the chain needs 2 shards per block at the v1 budget, about 1.6 kW of 5090 proving network-wide at 1 block per second (measured prover rows), independent of the hash rate. Against the hash: at 1 GH/s the hash draws 2.4 kW (2.4 microjoules per hash, measured), so proving is 67 percent of it; at 100 GH/s 0.7 percent; at 10 TH/s 0.007 percent. A chip farm at share `s` must prove share `s` of 1.6 kW: six 5090s per farm at any scale, which is the node it already runs. Redundant proving (each segment proved by `m` provers) raises the forcing `m` times and is the useful-work gaming the history records (Aleo, Boundless). Number: at mainnet scale the forcing is under 0.01 percent of the chip's energy; the honest card already proves. Rejected; the 80/20 split stands. + +### 2.11 Time-locked parameter commitments (REJECT beyond the era VDF) + +An era's parameters committed under a VDF so a chip cannot be built ahead: the era VDF of 7 October (`docs/analysis/era-vdf-2026-10-07.md`) already makes the era draw's input unknowable for 517 s on the fastest prover measured (chiavdf's GMP path, 208,800 squarings per second, against the production T of 108 million) and the era lead is 2 hours (`pow_era_lead`), so a chip taped out against era `n` knows era `n + 1`'s draw 2 hours before it runs, against a 5-month (Bitmain) to 13-month (a startup) design cycle (the history's lesson 5, Vorick). Lengthening the delay or the commitment changes nothing a chip can use: the GPU-like chip holds the whole drawn band as firmware (the synthesis's section 7), and the fixed-function chip is dead at the first draw outside its wired value whether it learns the draw 2 hours or 2 days ahead. The one party for whom 2 hours matters is the FPGA fleet (a bitstream compiles in 42 to 160 minutes on a mid-size part, claimed), and layer 7 (2.3) and the epoch length (spec 1.13.1, the 600 s floor) are the levers for it, not the lock. Cost of a longer lock: one honest node core for the VDF's hour per era (today) rising linearly with T; the 2019-class verify gate already missed by 2.2x (26 ms against 10, measured, proxy). Number: 0 to the chip at any delay above 2 hours; the honest node's core-hours rise with T. Rejected. + +### 2.12 A fraction of reads derived from the cache in the hash (REJECT) + +The brief's spirit of "tie the hash to what the chip must hold": a fraction `g` of the 128 reads per hash derived on the fly from the 256 MiB cache (8 dependent cache reads and 72 mixer applications) instead of read from the dataset, so the stored-dataset chip must carry the recompute chip's cache and core for that fraction. This is 2.9 form (iii) without the witness and the same arithmetic: the card's derived read is 8 dependent DRAM reads (the cache does not fit L2 at 256 MiB, and the cache doubling keeps it so), so at `g = 1/16` the card's dependent-read count per hash rises from 128 to 184 and its rate falls about 30 percent (modelled on the latency-bound rule; the inline kernel's 4.8x at `g = 1` is the measured anchor); the chip with the cache on die derives at 6.3 nJ per item (4.0 nJ of SRAM reads, 2.3 of mixer; modelled) for 0.466 to 0.50 microjoules per hash (+7 percent) and buys the USD 46 mirror and the N5 project it already needs for the shadow core. Number: GPU -30 percent of rate at `g = 1/16`, chip +7 percent of energy and +USD 46 of die. Rejected. + +### 2.13 Row-straddling and double-activation reads (REJECT) + +The chip and the card share the DRAM's physics (the research file's section 5: the same tRC, the same activate window, the same 32-byte atom). A read that opens two rows (an item straddling a row boundary, or two independent 32-byte sectors per read) costs the chip's memory +0.9 nJ per read (a second 909 pJ activation; modelled) and the card +1 sector of traffic, which at 128 reads per hash is the w64 regime (64 B per read): the 5090 fell to 71.9 MH/s, bandwidth-bound, 47 percent of its rate (measured, read-width). Number: chip +45 percent of `E_mem` (0.466 to 0.58), card -47 percent of rate and about +9 percent of energy per hash on the memory side alone. The edge moves from 3.6x to about 3.1x at the knee (modelled) at the price of half the card's rate. Rejected. + +### 2.14 Per-era lane-state and scratch draws (REJECT) + +Per-lane live state across the hash (a scratch with read-modify-write) was measured out in Counter ASIC 2.0 (layer 3: the recompute chip's gain at every share 2.4x, the cards -12 to -48 percent) and bounded in `docs/analysis/scratch-soundness.md` (the live state sits in a chip's SRAM at under 5 percent of its mirror). A drawn scratch size per era draws from a dead family. Number: the cards -12 to -48 percent of rate (measured), the chip +picojoules per access. Rejected. (The register-file width of 2.2 is the live form of this idea: state that costs the GPU nothing because its register file is already there, and costs the chip a link, not an SRAM.) + +### 2.15 A refresh per block (REJECT; the research file's row 7) + +Dead by arithmetic: a 1 GiB rebuild is 0.16 to 0.5 J on a chip core and 13 to 32 ms of a card's hash time; per block that is 0.4 to 1.3 percent of the chip's energy and 1.3 to 3.2 percent of the card's rate. The refresh cadence is a liveness tool (class v5's proof of following), not an energy lever. + +## 3. The measured rows (igneum-build-1, 8 October 2026, 11:0x to 11:2x UK) + +The crate: `igneum-pow` of branch `counter-asic-4` at 5984ffab, built on build-1 through `tools/build-remote.sh --no-fetch --box 1` from the detached worktree `igneum-wt-v6-inv-ca4` (RESULT rc=0, 11 s, sccache); the binary `/srv/builds/igneum-wt-v6-inv-ca4/igneum-pow/target/release/igneum-pow`. Every run under `/srv/builds/_bin/lease` (pool 48 at class measure for the censuses, `cores 40,88` for the benches), owner `class-v6-invention`; the box at load 15 to 24 on 96 threads from other lanes throughout; logs under `/srv/builds/v6-invention/` (`census-none.tsv`, `census-era.tsv`, `logs/--.log`, `census-run-*.log`), copied into `docs/analysis/class-v6/logs/` with the 09:00 report. + +### 3.1 The acceptance census (`v6inv-census.sh`, 256 seeds `igneum-v6inv/0..255`, every candidate's verdict through `igneum-pow accept --class `, the class's own 32-attempt cap) + +No era (`ERA=none`; 2,816 rows in 80 s on 48 cores): + +| Form (sub-blocks x length x passes) | Shadow instructions per iteration | Seeds accepted of 256 | Seeds exhausting 32 attempts | Candidates | Rejection per candidate | Mean accepted attempt | First failing part, the top four | +|---|---|---|---|---|---|---|---| +| `mx8+sh256x27` (class v4's shape, the whole block after instruction 63) | 6,912 | 256 | 0 | 268 | 0.045 | 0.05 | (a) 6, (b) 5, (c) 1 (the v2/v3 rule only: the crate's `accept` does not take the class v4 parts on this spelling, so the row is the control's shape, not sub-version 3's 0.681) | +| `mx8+shl256x27` (16 x 16 x 27, the 7 October form) | 6,912 | 76 | 180 | 7,043 | 0.989 | 15.9 | per-load bias 6,081; (c) 545; (b) 212; (a) 129 | +| `mx8+shl256x16` (16 x 16 x 16) | 4,096 | 69 | 187 | 7,117 | 0.990 | 15.4 | bias 6,294; (c) 406; (b) 215; (a) 133 | +| `mx8+shl576x12` (16 x 36 x 12) | 6,912 | 215 | 41 | 3,815 | 0.944 | 10.6 | bias 3,367; (b) 98; (a) 72; (c) 63 | +| `mx8+shl512x8` (16 x 32 x 8) | 4,096 | 209 | 47 | 4,120 | 0.949 | 11.5 | bias 3,686; (b) 106; (a) 82; (c) 37 | +| `mx8+shl1152x6` (16 x 72 x 6) | 6,912 | 226 | 30 | 3,428 | 0.934 | 9.9 | bias 3,036; (b) 97; (a) 62; (c) 7 | +| `mx8+shl1024x4` (16 x 64 x 4) | 4,096 | 231 | 25 | 3,487 | 0.934 | 10.6 | bias 3,097; (b) 81; (a) 73; (c) 5 | +| `mx8+shl2304x3` (16 x 144 x 3, class v4's count) | 6,912 | 224 | 32 | 3,457 | 0.935 | 9.9 | bias 3,076; (b) 89; (a) 67; (c) 1 | +| `mx8+shl2048x2` (16 x 128 x 2) | 4,096 | 228 | 28 | 3,423 | 0.933 | 10.1 | bias 3,041; (b) 83; (a) 65; (c) 6 | +| **`mx8+shl4096x1` (16 x 256 x 1, the sound form inside the cap)** | 4,096 | **234** | **22** | 3,217 | **0.927** | 9.7 | bias 2,823; (b) 94; (a) 64; (c) 2 | +| `mx8+shl4096x2` (16 x 256 x 2) | 8,192 | 233 | 23 | 3,273 | 0.929 | 9.9 | bias 2,875; (b) 95; (a) 67; (c) 3 | + +What the ladder says: the iterated 16-instruction map is the fault (0.989 to 0.990 whatever its pass count), and from a 36-instruction sub-block up the rejection is flat at 0.927 to 0.949 whatever the pass count or the work per hash (4,096 or 6,912 or 8,192 instructions per iteration). The remaining 0.93 is not the placement: the `(c)` lane-constant and distinct rejections fall to 1 to 7 per form (they were 406 to 545 on the 16-instruction forms), and the bias rejections are the product's low-bit law at the load's source, which under class v4 the sub-version 3 dataflow rule (a') removes at the draw and which the per-load class, not being the class v4 shape, never applies. The value-level reading of the 256 x 1 form's 2,329 bias rejections: index bit 0 in 1,563 (one-counts clustered at 3,584 to 4,608 of 16,384, the 1/4 law, 680 of them; and at 11,776 to 12,288, the 3/4 complement, 212), bits 26 and 27 in 502 (one-counts 7,168 to 7,680: a mild low bias of the top address bits just outside the 6-sigma band of 384, the high bits of small products through `mulhi`, unattributed), the other 26 bits 264 in all; by site, site 0 takes 788 of 2,329 (its source is written last by the previous iteration's sub-block 15 and by the base instructions before instruction 1, where the draw's redraw covers the sub-block's last writer of the next load's source and not a product rotated into place by a later `rotl`). The named fix is one rule, the research file's own ask of 20.2: the sub-version 3 freshness fixpoint and the shared-operand rule run over the real execution order (base instruction, the load, its sub-block, the next base instructions), and a load whose source is not fresh at that point refused at the draw, which class v4 pays at 0.568 of candidates and which should bring the per-load forms from 0.93 toward 0.68. + +The acceptance's own cost: 35 ms per per-load candidate on one box core (1,111 ms for 32 candidates; the control's v2/v3 rule 2.8 ms), so an epoch's draw at 13.7 candidates is about 0.5 s of one core; the (c'') ratio at 2^20 would add class v4's 2.8 s per chosen candidate. + +### 3.2 The verifier (core 40 of the EPYC 9454P at nice 19, core 88 its SMT sibling held busy by a 100,000-warp class v4 bench for the whole run, killed by its pid at the end; the ladder's method; `igneum-pow bench --seed igneum-genesis --day 2026-10-03 --class --warps 50`) + +| Form | Cold, sibling loaded, warp base 0 / 4,096 / 1,000,000 (ms) | Avg of 50, loaded (ms) | Cold, core alone, earlier in the same minutes (ms) | Label | +|---|---|---|---|---| +| `mx8+sh256x27` (class v4's shape) | 8.63 / 8.33 / 8.33 | 8.29 | 5.90 / 6.34 / 5.24 | measured; the ladder's run 2 read 8.77 / 5.14 at load 25 on 6 October | +| `mx8+shl4096x1` | 8.55 / 8.28 / 8.28 | 8.24 | 5.44 / 5.21 / 5.17 | measured | +| `mx8+shl2304x3` | 8.82 / 8.54 / 8.44 | 8.43 | 5.31 / 5.13 / 5.09 | measured | +| `mx8+shl4096x2` | not run loaded | | 5.97 / 5.33 / 5.29 | measured, alone only | + +The per-load forms verify in class v4's time within the run's noise (the same instruction count, the same items derived, 4,096 per warp on every row). A first pass of the loaded column was discarded: its sibling run (300 warps) ended before the measured warps began, the ladder script's own known-failed case, and read the quiet-core figures; the second pass held the sibling for the whole run. + +### 3.3 The instrument fault under drawn eras, and the correction it forces + +The same 2,816 rows with `--era igneum-era-test/` (`ERA=era`): every per-load form 0 of 256 seeds accepted, 8,192 candidates per form, rejection 1.000; the class v4 shape 256 of 256. Of the 256 x 1 form's 7,862 bias rejections, 5,536 name index bit 26 or 27 "set in 0 of 16,384" or "set in 16,384 of 16,384" at a load site, which is the era's working-set window (spec 1.13.1: `k_off = below(3)` per site puts the site on the whole dataset, a half or a quarter by fixing the top `k` bits of the index to the drawn offset `o`); the prototype's `BiasedIndexBit` test loops bits 0 to 27 and does not exclude bits at or above `28 - k_off_s`, so under any era it refuses every program with a half- or quarter-window site, which is nearly every program. The research file's 20.2a-close ("the 16 x 27 per-load class accepts 22 of 1,621 candidates over 64 seeds, 1.4 percent; 42 of 64 seeds exhaust the chain's 32 attempts") was read across drawn eras and therefore measured the instrument on most of its rows; the no-era census above is the construction's own figure (the 16 x 27 form 0.989 per candidate, 76 of 256 seeds accepted, which still fails the test of 2.1 and keeps that form dead). Owed to the research file (the Counter ASIC coordinator): the instrument fix (skip the window bits per site) and the 20.2a-close figures re-read with it; neither is made this week by this lane, which changes no code in the crate. + +### 3.4 The packs + +`igneum-pow export --seed igneum-genesis --day 2026-10-03 --class --out ` on build-1: `mx8_shl4096x1` (attempt 7, id 75ca9547da21b200, OVERALL PASS, kernel.cu 245,267 bytes, 4,308 lines) and `mx8_shl2304x3` (attempt 8, id bbfdfc1dcdda0b46, OVERALL PASS, kernel.cu 142,010 bytes, 2,516 lines), under `/srv/builds/v6-invention/packs/`, tarred as `v6inv-perload-packs.tgz` (sha256 ca1986b7fc5fab20a643fc37151a55e01f91edbfacc6f1a22a7384ae87cc11bc). Handed to the hash lane at 11:1x UK, taken into its v6 PC 1 job (the 5090 alone, the packs beside today's class v3 x8 and x16, the two re-weighted shadow packs, and the controls `mx8-genesis` and `mx8_sh256x27`; self-test, the 2^24 fingerprint, MH/s and W unlocked and at the 1,300 MHz lock), queued after the AMD grid, publish about 12:00 UK, close about 12:45 UK. Nothing of the packs' output goes to a served page or the spec. + +## 4. The ranked list, every column + +| Rank | Layer | Door (section 1) | Chip: fixed-function `k` / capex | Chip: GPU-like per-joule edge | Cost: RTX 5090 | Cost: RTX 5070 Ti | Cost: Apple M5 Max | Verifier | Harness state | +|---|---|---|---|---|---|---|---|---|---| +| 1 | Layer 5: the shadow per load, one pass of a long sub-block | capex and project (door 2) | `k` unchanged; project about USD 60 M against 30 M, cap about 200 M against 100 M (modelled); capex 3.0 to 4.3 USD per MH/s | unchanged (2.1x at `k = 1`) | -13 to -14 W against class v4's block at the same work (16 x 27 form, measured); the sound forms' rows in today's PC 1 job | no row; the 4070's 30 W premium as the proxy (approximate) | -0.5 percent (16 x 27 form, measured); the 4,096-line footprint OWED | 8.28 to 8.82 ms loaded (measured) | acceptance 0.927 measured; the dataflow rule in execution order is the fix (gate plan) | +| 2 | Layer 6: the register-file width drawn per era | capex (door 2), with layer 5 | closes the interposer branch: 4.5 to 9 TB/s of die-to-die traffic (modelled, approximate link figures) | unchanged | about 0 rate (occupancy arithmetic, approximate; the pack measures it) | the same | the same | 4x the register arrays, cost per op unchanged (modelled) | no pack form; a generator constant (gate plan) | +| 3 | Layer 7: warp-uniform block selection | life of a bitstream (door 3, the FPGA lane) | B x the shadow's area for a fixed pipeline or an overlay (approximate) | unchanged | about 0 (one uniform branch and 40 shuffles per hash: 0.3 percent of `F`) | the same | the compile footprint caps B (the 1,024-line block cost 17 percent, measured) | B x the dynamic test per candidate | no pack form (gate plan) | +| 4 | The reserve's order | life of fixed silicon (door 3) | USD 4 pre-wired | unchanged | under 1 percent at 4 points (measured steps) | the same | the same | 0 | layer 3's gate | + +What the list does not contain, and why it is honest to say so: no candidate moves the per-joule identity. The chip that stores the dataset keeps 3.6x at zero premium and 2.1x at `k = 1` under every layer here, as under the four. What the list adds is the project cost (rank 1 doubles it on the mission lane's model, rank 2 removes its cheaper branch), the FPGA lane's cost (rank 3), and the order of the reserve (rank 4). The founder's line "render an ASIC useless as soon as it dropped" is true of the fixed-function chip under layers 1 and 3 and stays false of the GPU-like chip under everything; the honest public sentence is the research file's: the price per joule of the honest card's operating point and the shadow's premium are what hold the general chip, and the layers decide which chip can be built and what it costs to start. + +## 5. Consequences per tier (the standing rule of 5 October 2026) + +| Tier | What this file means today | What is being done | +|---|---|---| +| A home miner, one 8, 12 or 16 GB card, any vendor, any OS | nothing changes: no layer here ships this week, no class moves, the devnet pays nothing; if rank 1 lands in v6 the card runs the same shadow work in a different place at the same or lower watts (the 16 x 27 form's measured 13 to 14 W under the whole block on a 5090; a 4070-class card's premium at its tune point is 30 W today, measured) | the sound forms' 5090 rows today; a small-card row (the 4070) by job when the hash lane's queue allows | +| One 24 or 32 GB card (5090 class) | the measured rows of section 3; the per-load placement is cheaper for this card than class v4's block at the same work | the PC 1 job, about 12:45 UK | +| RTX 5070 Ti | no card in the project; every row is the 4070's or the 5090's scaled, approximate; the hash lane's default (the stock pair plus the 5090's lock slope) stands | stated as approximate wherever it appears | +| Apple (M-series) | the one open number: the inline footprint of a 4,096-line per-load block (the 1,024-line block cost 17 percent on 6 October); if it costs rate, rank 1 takes a block-shape cap for the Apple tier (144 x 3 at 2,516 lines, or a 64-instruction sub-block form) and the synthesis says so | a Metal packbench row under the measure lock by the lane that runs the Mac (not this one) | +| A rig | watts per card as the 5090 row; a rig's bill under rank 1 is at or under class v4's | the same rows | +| A pool user | nothing: no share, payout or template changes in any candidate kept; the rejected 2.9 (pool-sampled witnesses) is the only one that would have touched the pool protocol | nothing | +| A node operator (the verifier) | the per-load forms verify in class v4's time (8.3 to 8.8 ms loaded, measured); layer 7 at B blocks multiplies the acceptance's dynamic test per candidate, not the hash | the 2019-class core measurement (O-1.14) decides rung and block caps as before | +| A chip maker | under rank 1 the controller and the shadow core share one advanced die or an interposer (project about USD 60 M, modelled); under rank 2 the interposer no longer suffices; under rank 3 a per-epoch bitstream carries B blocks; the per-joule edge is unchanged | the gate plan of section 6 | +| The public claim | nothing moves; the chip texts rest on the research file's close (2.1x at `k = 1` for 82 to 90 W on a 5090 at the knee, measured four times) | the Counter lane's texts | + +## 6. The gate plan (hours, never weeks; nothing this week) + +| Gate | What runs | Pass line | Known-failed case | +|---|---|---|---| +| G5-draw (layer 5) | the generator's dataflow fixpoint and shared-operand rule over the real per-load order; the 4,096 cap raised so 16 x 432 x 1 draws; `v6inv-census.sh` at 256 seeds, no era and drawn eras (with the instrument's window bits excluded) | rejection per candidate at or under 0.75 on every sound form, 0 exhaustions, drawn-era rate equal to the no-era rate within the binomial band; the F8 census at 2^24 on 64 seeds: 60 of 64 under 1.2x, the four tail seeds' sites read against their own windows | the 7 October per-load record (candidate 0 of 854050a4293f0615) refused; the 16 x 27 form at 0.989 refused by the line | +| G5-card (layer 5) | one pack per sound form on the 5090 (today), the 4070 and the 9070 XT by job, Metal packbench on the M5 Max | rate within 1 percent of class v4's shape at both states on NVIDIA and AMD; watts at or under class v4's; the Apple footprint within 5 percent or the block-shape cap set | a pack whose fingerprint differs from the Rust verifier's on any vendor | +| G6 (layer 6) | the register count as a class field; the census at 8, 16, 32; the card packs | 2.2's pass line | 2.2's fail line | +| G7 (layer 7) | the selection class; every path judged; the selection histogram at 2^24 | 2.3's pass line | the lane-0 plant | +| G-order (the reserve) | layer 3's gate with the order fixed | layer 3's line | layer 3's case | + +Hours: the dataflow rule in execution order 2 to 3 (the research file's own estimate) plus the re-export and census 1; the register class 3 to 4; the selection class 4 to 6; the card jobs are queue time. Nothing is coded this week; the first code is the founder's call after the synthesis. + +## 7. Unverified and owed + +- The sound forms' card rows (the 5090 today through the hash lane; the 4070 and the 9070 XT later; the M5 Max footprint by the lane that runs the Mac). +- The 16 x 432 x 1 form itself: bracketed by the 256 x 1 and 144 x 3 rows (0.927 and 0.935) and the flat ladder between 36 and 256; not drawn (the cap). +- The instrument fix (the window bits) and the re-read of 20.2a-close: owed to the research file's owner, not made here. +- The bits 26 and 27 mild bias (502 rejections at one-counts 7,168 to 7,680 of 16,384): unattributed; a trace of the site's source writers is the next read. +- The register-width and block-selection classes: modelled only; no pack exists. +- Every chip figure is the model's (chip-model-v3 section 5 and the research file's sections 2, 15.1a, 16 and 20.4); the die-to-die link figures of 2.2 are approximate, from memory, uncited; no chip has been measured. +- The web search budget of this session was exhausted before this lane's reading; every external figure here is one already cited in the repo's files, with its URL and date there (the research file's section 14, the history's section 6, chip-model-v3 5.1). + +## 8. Sources + +Internal: `docs/spec/01-lottery-hash.md` (1.4.3 to 1.4.7, 1.8.5, 1.8.6 on branch class-v5, 1.13); `docs/analysis/chip-model-v3.md` (sections 1 to 3, 5.1 to 5.11, 6); `docs/analysis/counter-asic-4-research.md` on branch counter-asic-4 (sections 0, 2, 4, 7, 9, 15.1a, 15.1b, 16, 17, 20.2 to 20.4); `docs/plans/cryptanalysis/in-house-pass.md` (sections 12 to 14); `docs/plans/counter-asic-3-status.md` section 7c; `docs/analysis/asic-resistance-history.md` (sections 1.2, 2.4 to 2.6, 3, 4.3); `docs/analysis/era-vdf-2026-10-07.md`; `docs/design/class-v5-stored-state.md` on branch class-v5 (2a, 3); `docs/design/latency-ladder.md` on branch ladder (2 to 5); `docs/analysis/card-lifetime-2026-10-05.md`; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/analysis/scratch-soundness.md`; `docs/design/class-v6-rotating-family.md` on branch counter-asic-4 (the synthesis's outline at 5984ffab); the harness runs of section 3 (logs on build-1 under `/srv/builds/v6-invention/`). + +External, as cited in those files (read there on the dates they state): O'Connor et al., Fine-Grained DRAM, MICRO 2017; Li, Reddy, Jacob, MEMSYS 2018; Folded Banks, ISCA 2025; Horowitz, ISSCC 2014; Dally, Hot Chips 2023; the mlsysbook energy table citing Horowitz and Dally; the RandomX design document; the ProgPoW audits (Least Authority and Rao, 2019); Condrey, PoSME, arXiv 2604.15751 (April 2026); the Ethash, RandomX, Equihash and Cuckatoo chip rows of the history; the GDDR7 price rows (TrendForce, September 2026). diff --git a/docs/analysis/class-v6/logs/census-era.tsv b/docs/analysis/class-v6/logs/census-era.tsv new file mode 100644 index 000000000..e6e87ba27 --- /dev/null +++ b/docs/analysis/class-v6/logs/census-era.tsv @@ -0,0 +1,2817 @@ +mx8+sh256x27 3 1 1 0 +mx8+sh256x27 1 1 1 0 +mx8+sh256x27 4 1 1 0 +mx8+sh256x27 5 1 1 0 +mx8+sh256x27 6 1 1 0 +mx8+sh256x27 8 1 1 0 +mx8+sh256x27 0 1 1 0 +mx8+sh256x27 7 1 1 0 +mx8+sh256x27 13 1 1 0 +mx8+sh256x27 10 1 1 0 +mx8+sh256x27 11 1 1 0 +mx8+sh256x27 16 1 1 0 +mx8+sh256x27 12 1 1 0 +mx8+sh256x27 14 1 1 0 +mx8+sh256x27 15 1 1 0 +mx8+sh256x27 18 1 1 0 +mx8+sh256x27 20 1 1 0 +mx8+sh256x27 22 1 1 0 +mx8+sh256x27 17 1 1 0 +mx8+sh256x27 21 1 1 0 +mx8+sh256x27 19 1 1 0 +mx8+sh256x27 23 1 1 0 +mx8+sh256x27 2 1 1 0 +mx8+sh256x27 27 1 1 0 +mx8+sh256x27 28 1 1 0 +mx8+sh256x27 9 1 1 0 +mx8+sh256x27 31 1 1 0 +mx8+sh256x27 29 1 1 0 +mx8+sh256x27 24 1 1 0 +mx8+sh256x27 32 1 1 0 +mx8+sh256x27 33 1 1 0 +mx8+sh256x27 36 1 1 0 +mx8+sh256x27 26 1 1 0 +mx8+sh256x27 30 1 1 0 +mx8+sh256x27 35 1 1 0 +mx8+sh256x27 25 1 1 0 +mx8+sh256x27 38 1 1 0 +mx8+sh256x27 34 1 1 0 +mx8+sh256x27 37 1 1 0 +mx8+sh256x27 42 1 1 0 +mx8+sh256x27 39 1 1 0 +mx8+sh256x27 44 1 1 0 +mx8+sh256x27 40 1 1 0 +mx8+sh256x27 41 1 1 0 +mx8+sh256x27 43 1 1 0 +mx8+sh256x27 48 1 1 0 +mx8+sh256x27 49 1 1 0 +mx8+sh256x27 46 1 1 0 +mx8+sh256x27 47 1 1 0 +mx8+sh256x27 45 1 1 0 +mx8+sh256x27 50 1 1 0 +mx8+sh256x27 54 1 1 0 +mx8+sh256x27 53 1 1 0 +mx8+sh256x27 51 1 1 0 +mx8+sh256x27 56 1 1 0 +mx8+sh256x27 55 2 1 1 (b)=1; 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+mx8+sh256x27 221 1 1 0 +mx8+sh256x27 223 1 1 0 +mx8+sh256x27 220 1 1 0 +mx8+sh256x27 224 1 1 0 +mx8+sh256x27 225 1 1 0 +mx8+sh256x27 226 1 1 0 +mx8+sh256x27 229 1 1 0 +mx8+sh256x27 230 1 1 0 +mx8+sh256x27 228 1 1 0 +mx8+sh256x27 227 1 1 0 +mx8+sh256x27 234 1 1 0 +mx8+sh256x27 232 1 1 0 +mx8+sh256x27 235 1 1 0 +mx8+sh256x27 231 1 1 0 +mx8+sh256x27 236 1 1 0 +mx8+sh256x27 237 1 1 0 +mx8+sh256x27 239 1 1 0 +mx8+sh256x27 238 1 1 0 +mx8+sh256x27 233 2 1 1 (b)=1; +mx8+sh256x27 240 1 1 0 +mx8+sh256x27 242 1 1 0 +mx8+sh256x27 241 1 1 0 +mx8+sh256x27 243 1 1 0 +mx8+sh256x27 244 1 1 0 +mx8+sh256x27 247 1 1 0 +mx8+sh256x27 245 1 1 0 +mx8+sh256x27 248 1 1 0 +mx8+sh256x27 249 1 1 0 +mx8+sh256x27 246 2 1 1 (b)=1; +mx8+sh256x27 250 1 1 0 +mx8+sh256x27 251 1 1 0 +mx8+sh256x27 254 1 1 0 +mx8+sh256x27 252 1 1 0 +mx8+sh256x27 253 1 1 0 +mx8+sh256x27 255 1 1 0 +mx8+shl256x27 14 32 0 none (c,=23;(c)=4;(b)=4;(a)=1; +mx8+shl256x27 44 32 0 none (c,=24;(c)=5;(b)=3; +mx8+shl256x27 7 32 0 none (c,=26;(c)=5;(a)=1; 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+mx8+shl256x27 11 32 0 none (c,=29;(c)=3; +mx8+shl256x27 17 32 0 none (c,=30;(c)=2; +mx8+shl256x27 13 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 24 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 27 32 0 none (c,=30;(a)=2; +mx8+shl256x27 42 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 31 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 18 32 0 none (c,=31;(c)=1; +mx8+shl256x27 8 32 0 none (c,=29;(c)=3; +mx8+shl256x27 34 32 0 none (c,=29;(c)=3; +mx8+shl256x27 26 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 29 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 33 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 23 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 9 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 15 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 46 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 32 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl256x27 47 32 0 none (c,=31;(c)=1; +mx8+shl256x27 5 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 37 32 0 none (c,=30;(c)=2; +mx8+shl256x27 12 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 20 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 48 32 0 none (c,=26;(c)=5;(b)=1; +mx8+shl256x27 50 32 0 none (c,=30;(c)=2; +mx8+shl256x27 66 32 0 none (c,=23;(c)=4;(a)=3;(b)=2; +mx8+shl256x27 64 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x27 51 32 0 none (c,=27;(b)=3;(c)=1;(a)=1; +mx8+shl256x27 77 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x27 49 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 52 32 0 none (c,=29;(c)=3; +mx8+shl256x27 72 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 62 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 56 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 54 32 0 none (c,=31;(b)=1; +mx8+shl256x27 68 32 0 none (c,=28;(c)=4; +mx8+shl256x27 81 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 53 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x27 79 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x27 57 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 60 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x27 94 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x27 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x27 65 32 0 none (c,=31;(c)=1; +mx8+shl256x27 63 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 73 32 0 none (c,=27;(c)=3;(b)=1;(a)=1; +mx8+shl256x27 61 32 0 none (c,=30;(c)=2; +mx8+shl256x27 74 32 0 none (c,=30;(c)=2; +mx8+shl256x27 55 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 71 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 59 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x27 76 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 86 32 0 none (c,=31;(b)=1; +mx8+shl256x27 83 32 0 none (c,=31;(c)=1; +mx8+shl256x27 69 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 89 32 0 none (c,=31;(c)=1; +mx8+shl256x27 90 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 58 32 0 none (c,=31;(c)=1; +mx8+shl256x27 87 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 84 32 0 none (c,=32; +mx8+shl256x27 70 32 0 none (c,=31;(c)=1; +mx8+shl256x27 75 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 85 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 91 32 0 none (c,=32; +mx8+shl256x27 82 32 0 none (c,=31;(c)=1; +mx8+shl256x27 88 32 0 none (c,=32; +mx8+shl256x27 93 32 0 none (c,=31;(c)=1; +mx8+shl256x27 80 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl256x27 67 32 0 none (c,=31;(c)=1; +mx8+shl256x27 95 32 0 none (c,=30;(b)=2; +mx8+shl256x27 92 32 0 none (c,=31;(c)=1; +mx8+shl256x27 105 32 0 none (c,=27;(c)=3;(b)=1;(a)=1; +mx8+shl256x27 97 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 102 32 0 none (c,=29;(c)=3; +mx8+shl256x27 104 32 0 none (c,=26;(c)=5;(a)=1; +mx8+shl256x27 96 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 98 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x27 99 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 107 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 118 32 0 none (c,=27;(c)=5; +mx8+shl256x27 114 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 103 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 113 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x27 112 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 100 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 116 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 109 32 0 none (c,=28;(c)=2;(a)=2; +mx8+shl256x27 115 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x27 122 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 134 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 125 32 0 none (c,=26;(c)=5;(b)=1; +mx8+shl256x27 101 32 0 none (c,=31;(a)=1; +mx8+shl256x27 106 32 0 none (c,=29;(c)=3; +mx8+shl256x27 117 32 0 none (c,=28;(c)=2;(a)=2; +mx8+shl256x27 108 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 128 32 0 none (c,=26;(c)=3;(b)=3; +mx8+shl256x27 129 32 0 none (c,=28;(c)=4; +mx8+shl256x27 131 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 121 32 0 none (c,=27;(c)=5; +mx8+shl256x27 123 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x27 130 32 0 none (c,=27;(c)=3;(b)=1;(a)=1; +mx8+shl256x27 126 32 0 none (c,=31;(c)=1; +mx8+shl256x27 127 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 138 32 0 none (c,=27;(c)=3;(a)=2; +mx8+shl256x27 135 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x27 141 32 0 none (c,=27;(c)=5; +mx8+shl256x27 111 32 0 none (c,=30;(c)=2; +mx8+shl256x27 139 32 0 none (c,=29;(b)=3; +mx8+shl256x27 110 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 124 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 120 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 144 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 146 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x27 136 32 0 none (c,=31;(b)=1; +mx8+shl256x27 137 32 0 none (c,=30;(b)=2; +mx8+shl256x27 142 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 143 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x27 133 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x27 140 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 132 32 0 none (c,=31;(c)=1; +mx8+shl256x27 119 32 0 none (c,=32; +mx8+shl256x27 147 32 0 none (c,=28;(c)=4; +mx8+shl256x27 148 32 0 none (c,=28;(c)=4; +mx8+shl256x27 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl256x27 149 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 150 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 153 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 154 32 0 none (c,=26;(b)=3;(c)=2;(a)=1; +mx8+shl256x27 159 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 151 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 173 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 174 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 158 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x27 169 32 0 none (c,=24;(c)=6;(b)=2; +mx8+shl256x27 161 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 156 32 0 none (c,=31;(c)=1; +mx8+shl256x27 160 32 0 none (c,=30;(b)=2; +mx8+shl256x27 157 32 0 none (c,=32; +mx8+shl256x27 155 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl256x27 164 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x27 175 32 0 none (c,=31;(b)=1; +mx8+shl256x27 171 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 165 32 0 none (c,=30;(c)=2; +mx8+shl256x27 168 32 0 none (c,=32; +mx8+shl256x27 179 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 163 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 167 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 166 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 176 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x27 170 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 152 32 0 none (c,=31;(c)=1; +mx8+shl256x27 182 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 180 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x27 172 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 162 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 181 32 0 none (c,=31;(c)=1; +mx8+shl256x27 178 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 187 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 191 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 177 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 188 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl256x27 184 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 190 32 0 none (c,=30;(a)=2; +mx8+shl256x27 183 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 189 32 0 none (c,=31;(c)=1; +mx8+shl256x27 192 32 0 none (c,=29;(c)=3; +mx8+shl256x27 193 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 194 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x27 185 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x27 195 32 0 none (c,=32; +mx8+shl256x27 198 32 0 none (c,=27;(a)=3;(c)=2; +mx8+shl256x27 186 32 0 none (c,=31;(c)=1; +mx8+shl256x27 201 32 0 none (c,=29;(c)=3; +mx8+shl256x27 196 32 0 none (c,=31;(c)=1; +mx8+shl256x27 204 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 214 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 206 32 0 none (c,=31;(b)=1; +mx8+shl256x27 203 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 197 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 213 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 209 32 0 none (c,=30;(b)=2; +mx8+shl256x27 207 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 208 32 0 none (c,=29;(c)=3; +mx8+shl256x27 210 32 0 none (c,=26;(c)=2;(b)=2;(a)=2; +mx8+shl256x27 211 32 0 none (c,=30;(c)=2; +mx8+shl256x27 212 32 0 none (c,=27;(b)=3;(c)=1;(a)=1; +mx8+shl256x27 216 32 0 none (c,=28;(c)=4; +mx8+shl256x27 220 32 0 none (c,=26;(c)=3;(a)=2;(b)=1; +mx8+shl256x27 229 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 205 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 226 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 218 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x27 200 32 0 none (c,=32; +mx8+shl256x27 199 32 0 none (c,=31;(c)=1; +mx8+shl256x27 202 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 223 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 222 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 215 32 0 none (c,=31;(c)=1; +mx8+shl256x27 228 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 225 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x27 219 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 227 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 230 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 221 32 0 none (c,=29;(c)=3; +mx8+shl256x27 234 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 217 32 0 none (c,=30;(b)=2; +mx8+shl256x27 235 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 231 32 0 none (c,=31;(c)=1; +mx8+shl256x27 233 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x27 224 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl256x27 236 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 232 32 0 none (c,=32; +mx8+shl256x27 237 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x27 238 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 246 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 240 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 253 32 0 none (c,=23;(c)=7;(b)=1;(a)=1; +mx8+shl256x27 250 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 243 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x27 251 32 0 none (c,=28;(c)=4; +mx8+shl256x27 241 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x27 247 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 249 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 245 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 242 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x27 252 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 255 32 0 none (c,=27;(c)=3;(b)=1;(a)=1; +mx8+shl256x27 239 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 244 32 0 none (c,=32; +mx8+shl256x27 254 32 0 none (c,=30;(c)=2; +mx8+shl256x27 248 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl576x12 3 32 0 none (c,=29;(b)=3; +mx8+shl576x12 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 4 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 0 32 0 none (c,=31;(a)=1; +mx8+shl576x12 2 32 0 none (c,=31;(c)=1; +mx8+shl576x12 7 32 0 none (c,=31;(a)=1; +mx8+shl576x12 9 32 0 none (c,=31;(b)=1; +mx8+shl576x12 15 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 14 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl576x12 5 32 0 none (c,=31;(b)=1; +mx8+shl576x12 11 32 0 none (c,=32; +mx8+shl576x12 10 32 0 none (c,=30;(b)=2; +mx8+shl576x12 6 32 0 none (c,=31;(b)=1; +mx8+shl576x12 13 32 0 none (c,=31;(b)=1; +mx8+shl576x12 8 32 0 none (c,=32; +mx8+shl576x12 12 32 0 none (c,=31;(b)=1; +mx8+shl576x12 19 32 0 none (c,=32; +mx8+shl576x12 21 32 0 none (c,=31;(c)=1; +mx8+shl576x12 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl576x12 17 32 0 none (c,=32; +mx8+shl576x12 16 32 0 none (c,=32; +mx8+shl576x12 20 32 0 none (c,=31;(b)=1; +mx8+shl576x12 18 32 0 none (c,=32; +mx8+shl576x12 24 32 0 none (c,=30;(b)=2; +mx8+shl576x12 23 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 27 32 0 none (c,=30;(a)=2; +mx8+shl576x12 26 32 0 none (c,=31;(a)=1; +mx8+shl576x12 31 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl576x12 25 32 0 none (c,=31;(b)=1; +mx8+shl576x12 28 32 0 none (c,=28;(b)=4; +mx8+shl576x12 34 32 0 none (c,=31;(c)=1; +mx8+shl576x12 29 32 0 none (c,=31;(a)=1; +mx8+shl576x12 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl576x12 38 32 0 none (c,=31;(c)=1; +mx8+shl576x12 41 32 0 none (c,=30;(b)=2; +mx8+shl576x12 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 30 32 0 none (c,=30;(b)=2; +mx8+shl576x12 39 32 0 none (c,=32; +mx8+shl576x12 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 36 32 0 none (c,=30;(b)=2; +mx8+shl576x12 44 32 0 none (c,=29;(b)=3; +mx8+shl576x12 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 37 32 0 none (c,=32; +mx8+shl576x12 42 32 0 none (c,=31;(a)=1; +mx8+shl576x12 47 32 0 none (c,=32; +mx8+shl576x12 33 32 0 none (c,=31;(b)=1; +mx8+shl576x12 45 32 0 none (c,=31;(a)=1; +mx8+shl576x12 46 32 0 none (c,=31;(a)=1; +mx8+shl576x12 48 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl576x12 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl576x12 49 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl576x12 50 32 0 none (c,=32; +mx8+shl576x12 54 32 0 none (c,=31;(b)=1; +mx8+shl576x12 56 32 0 none (c,=31;(a)=1; +mx8+shl576x12 55 32 0 none (c,=31;(b)=1; +mx8+shl576x12 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 59 32 0 none (c,=30;(b)=2; +mx8+shl576x12 60 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl576x12 64 32 0 none (c,=30;(b)=2; +mx8+shl576x12 52 32 0 none (c,=31;(c)=1; +mx8+shl576x12 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 53 32 0 none (c,=30;(b)=2; +mx8+shl576x12 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl576x12 58 32 0 none (c,=32; +mx8+shl576x12 61 32 0 none (c,=32; +mx8+shl576x12 69 32 0 none (c,=31;(b)=1; +mx8+shl576x12 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 75 32 0 none (c,=31;(b)=1; +mx8+shl576x12 67 32 0 none (c,=32; +mx8+shl576x12 71 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl576x12 62 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl576x12 79 32 0 none (c,=30;(b)=2; +mx8+shl576x12 76 32 0 none (c,=31;(b)=1; +mx8+shl576x12 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 68 32 0 none (c,=32; +mx8+shl576x12 65 32 0 none (c,=32; +mx8+shl576x12 83 32 0 none (c,=32; +mx8+shl576x12 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 81 32 0 none (c,=31;(a)=1; +mx8+shl576x12 77 32 0 none (c,=30;(a)=2; +mx8+shl576x12 70 32 0 none (c,=32; +mx8+shl576x12 87 32 0 none (c,=31;(b)=1; +mx8+shl576x12 89 32 0 none (c,=32; +mx8+shl576x12 88 32 0 none (c,=32; +mx8+shl576x12 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 86 32 0 none (c,=31;(b)=1; +mx8+shl576x12 74 32 0 none (c,=32; +mx8+shl576x12 92 32 0 none (c,=31;(c)=1; +mx8+shl576x12 93 32 0 none (c,=31;(c)=1; +mx8+shl576x12 96 32 0 none (c,=31;(b)=1; +mx8+shl576x12 95 32 0 none (c,=30;(b)=2; +mx8+shl576x12 85 32 0 none (c,=31;(b)=1; +mx8+shl576x12 91 32 0 none (c,=32; +mx8+shl576x12 84 32 0 none (c,=32; +mx8+shl576x12 97 32 0 none (c,=31;(b)=1; +mx8+shl576x12 90 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl576x12 82 32 0 none (c,=32; +mx8+shl576x12 98 32 0 none (c,=30;(b)=2; +mx8+shl576x12 101 32 0 none (c,=31;(a)=1; +mx8+shl576x12 100 32 0 none (c,=31;(a)=1; +mx8+shl576x12 102 32 0 none (c,=32; +mx8+shl576x12 104 32 0 none (c,=31;(a)=1; +mx8+shl576x12 94 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl576x12 106 32 0 none (c,=32; +mx8+shl576x12 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 118 32 0 none (c,=31;(c)=1; +mx8+shl576x12 109 32 0 none (c,=30;(a)=2; +mx8+shl576x12 111 32 0 none (c,=30;(c)=2; +mx8+shl576x12 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 112 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl576x12 115 32 0 none (c,=30;(a)=2; +mx8+shl576x12 103 32 0 none (c,=31;(b)=1; +mx8+shl576x12 114 32 0 none (c,=31;(a)=1; +mx8+shl576x12 113 32 0 none (c,=29;(b)=3; +mx8+shl576x12 119 32 0 none (c,=32; +mx8+shl576x12 99 32 0 none (c,=31;(b)=1; +mx8+shl576x12 117 32 0 none (c,=30;(a)=2; +mx8+shl576x12 116 32 0 none (c,=31;(a)=1; +mx8+shl576x12 127 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 108 32 0 none (c,=31;(a)=1; +mx8+shl576x12 123 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl576x12 124 32 0 none (c,=31;(b)=1; +mx8+shl576x12 121 32 0 none (c,=32; +mx8+shl576x12 120 32 0 none (c,=31;(b)=1; +mx8+shl576x12 130 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 128 32 0 none (c,=29;(b)=3; +mx8+shl576x12 138 32 0 none (c,=30;(a)=2; +mx8+shl576x12 125 32 0 none (c,=31;(b)=1; +mx8+shl576x12 139 32 0 none (c,=29;(b)=3; +mx8+shl576x12 135 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl576x12 122 32 0 none (c,=31;(b)=1; +mx8+shl576x12 133 32 0 none (c,=30;(b)=2; +mx8+shl576x12 132 32 0 none (c,=32; +mx8+shl576x12 143 32 0 none (c,=29;(a)=3; +mx8+shl576x12 137 32 0 none (c,=30;(b)=2; +mx8+shl576x12 140 32 0 none (c,=31;(b)=1; +mx8+shl576x12 142 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl576x12 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 144 32 0 none (c,=31;(b)=1; +mx8+shl576x12 131 32 0 none (c,=31;(b)=1; +mx8+shl576x12 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 146 32 0 none (c,=30;(b)=2; +mx8+shl576x12 126 32 0 none (c,=32; +mx8+shl576x12 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 136 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl576x12 129 32 0 none (c,=32; +mx8+shl576x12 151 32 0 none (c,=31;(a)=1; +mx8+shl576x12 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl576x12 147 32 0 none (c,=32; +mx8+shl576x12 158 32 0 none (c,=30;(b)=2; +mx8+shl576x12 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 161 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl576x12 152 32 0 none (c,=32; +mx8+shl576x12 148 32 0 none (c,=32; +mx8+shl576x12 149 32 0 none (c,=31;(a)=1; +mx8+shl576x12 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl576x12 162 32 0 none (c,=31;(a)=1; +mx8+shl576x12 153 32 0 none (c,=31;(a)=1; +mx8+shl576x12 141 32 0 none (c,=32; +mx8+shl576x12 157 32 0 none (c,=32; +mx8+shl576x12 160 32 0 none (c,=30;(b)=2; +mx8+shl576x12 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 167 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 156 32 0 none (c,=32; +mx8+shl576x12 168 32 0 none (c,=32; +mx8+shl576x12 159 32 0 none (c,=31;(b)=1; +mx8+shl576x12 166 32 0 none (c,=31;(b)=1; +mx8+shl576x12 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 173 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 169 32 0 none (c,=30;(b)=2; +mx8+shl576x12 171 32 0 none (c,=31;(b)=1; +mx8+shl576x12 177 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl576x12 172 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 180 32 0 none (c,=30;(b)=2; +mx8+shl576x12 183 32 0 none (c,=31;(a)=1; +mx8+shl576x12 184 32 0 none (c,=31;(b)=1; +mx8+shl576x12 170 32 0 none (c,=31;(a)=1; +mx8+shl576x12 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 179 32 0 none (c,=31;(a)=1; +mx8+shl576x12 165 32 0 none (c,=32; +mx8+shl576x12 185 32 0 none (c,=30;(a)=2; +mx8+shl576x12 175 32 0 none (c,=31;(b)=1; +mx8+shl576x12 188 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 178 32 0 none (c,=31;(b)=1; +mx8+shl576x12 181 32 0 none (c,=32; +mx8+shl576x12 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 191 32 0 none (c,=31;(b)=1; +mx8+shl576x12 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 194 32 0 none (c,=29;(b)=3; +mx8+shl576x12 186 32 0 none (c,=32; +mx8+shl576x12 190 32 0 none (c,=30;(a)=2; +mx8+shl576x12 209 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl576x12 196 32 0 none (c,=32; +mx8+shl576x12 207 32 0 none (c,=31;(a)=1; +mx8+shl576x12 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl576x12 195 32 0 none (c,=32; +mx8+shl576x12 197 32 0 none (c,=31;(b)=1; +mx8+shl576x12 200 32 0 none (c,=31;(c)=1; +mx8+shl576x12 201 32 0 none (c,=32; +mx8+shl576x12 202 32 0 none (c,=30;(b)=2; +mx8+shl576x12 203 32 0 none (c,=31;(a)=1; +mx8+shl576x12 204 32 0 none (c,=31;(b)=1; +mx8+shl576x12 189 32 0 none (c,=32; +mx8+shl576x12 199 32 0 none (c,=32; +mx8+shl576x12 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl576x12 206 32 0 none (c,=31;(b)=1; +mx8+shl576x12 218 32 0 none (c,=29;(a)=3; +mx8+shl576x12 193 32 0 none (c,=31;(b)=1; +mx8+shl576x12 205 32 0 none (c,=31;(b)=1; +mx8+shl576x12 192 32 0 none (c,=32; +mx8+shl576x12 208 32 0 none (c,=32; +mx8+shl576x12 216 32 0 none (c,=31;(c)=1; +mx8+shl576x12 198 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl576x12 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 217 32 0 none (c,=30;(b)=2; +mx8+shl576x12 221 32 0 none (c,=32; +mx8+shl576x12 211 32 0 none (c,=30;(c)=2; +mx8+shl576x12 213 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl576x12 225 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl576x12 220 32 0 none (c,=27;(c)=2;(a)=2;(b)=1; +mx8+shl576x12 215 32 0 none (c,=32; +mx8+shl576x12 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl576x12 222 32 0 none (c,=31;(b)=1; +mx8+shl576x12 233 32 0 none (c,=29;(b)=3; +mx8+shl576x12 229 32 0 none (c,=31;(b)=1; +mx8+shl576x12 226 32 0 none (c,=31;(a)=1; +mx8+shl576x12 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 231 32 0 none (c,=32; +mx8+shl576x12 228 32 0 none (c,=31;(a)=1; +mx8+shl576x12 219 32 0 none (c,=31;(b)=1; +mx8+shl576x12 237 32 0 none (c,=28;(c)=2;(a)=2; +mx8+shl576x12 230 32 0 none (c,=31;(b)=1; +mx8+shl576x12 227 32 0 none (c,=31;(a)=1; +mx8+shl576x12 235 32 0 none (c,=31;(b)=1; +mx8+shl576x12 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 238 32 0 none (c,=31;(b)=1; +mx8+shl576x12 240 32 0 none (c,=31;(b)=1; +mx8+shl576x12 232 32 0 none (c,=31;(c)=1; +mx8+shl576x12 243 32 0 none (c,=30;(b)=2; +mx8+shl576x12 239 32 0 none (c,=31;(a)=1; +mx8+shl576x12 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 244 32 0 none (c,=32; +mx8+shl576x12 249 32 0 none (c,=31;(b)=1; +mx8+shl576x12 248 32 0 none (c,=31;(b)=1; +mx8+shl576x12 247 32 0 none (c,=31;(b)=1; +mx8+shl576x12 250 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl576x12 241 32 0 none (c,=29;(b)=3; +mx8+shl576x12 245 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl1152x6 2 32 0 none (c,=32; +mx8+shl576x12 253 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl1152x6 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 246 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 3 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 4 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 254 32 0 none (c,=32; +mx8+shl1152x6 7 32 0 none (c,=31;(a)=1; +mx8+shl576x12 252 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 0 32 0 none (c,=31;(a)=1; +mx8+shl576x12 242 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 5 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 10 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 6 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 14 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl1152x6 11 32 0 none (c,=32; +mx8+shl1152x6 17 32 0 none (c,=32; +mx8+shl576x12 251 32 0 none (c,=32; +mx8+shl1152x6 8 32 0 none (c,=32; +mx8+shl1152x6 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 12 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 13 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1152x6 18 32 0 none (c,=32; +mx8+shl1152x6 21 32 0 none (c,=32; +mx8+shl1152x6 27 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 9 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 23 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 25 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 19 32 0 none (c,=32; +mx8+shl1152x6 16 32 0 none (c,=32; +mx8+shl1152x6 20 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 26 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 28 32 0 none (c,=28;(b)=4; +mx8+shl1152x6 30 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 24 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1152x6 29 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 36 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 33 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 34 32 0 none (c,=32; +mx8+shl1152x6 39 32 0 none (c,=32; +mx8+shl1152x6 38 32 0 none (c,=32; +mx8+shl1152x6 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1152x6 41 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 48 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 49 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 44 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 46 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 47 32 0 none (c,=32; +mx8+shl1152x6 54 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 52 32 0 none (c,=32; +mx8+shl1152x6 31 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 50 32 0 none (c,=32; +mx8+shl1152x6 55 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 60 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 42 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 56 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 45 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 58 32 0 none (c,=32; +mx8+shl1152x6 61 32 0 none (c,=32; +mx8+shl1152x6 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 62 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 64 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl1152x6 65 32 0 none (c,=32; +mx8+shl1152x6 37 32 0 none (c,=32; +mx8+shl1152x6 71 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 53 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 67 32 0 none (c,=32; +mx8+shl1152x6 69 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 70 32 0 none (c,=32; +mx8+shl1152x6 68 32 0 none (c,=32; +mx8+shl1152x6 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 74 32 0 none (c,=32; +mx8+shl1152x6 59 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 77 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 79 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 75 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 76 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 81 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 86 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 84 32 0 none (c,=32; +mx8+shl1152x6 83 32 0 none (c,=32; +mx8+shl1152x6 85 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 82 32 0 none (c,=32; +mx8+shl1152x6 88 32 0 none (c,=32; +mx8+shl1152x6 96 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 91 32 0 none (c,=32; +mx8+shl1152x6 89 32 0 none (c,=32; +mx8+shl1152x6 87 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 93 32 0 none (c,=32; +mx8+shl1152x6 101 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 97 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 90 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 95 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 94 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 92 32 0 none (c,=32; +mx8+shl1152x6 100 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 102 32 0 none (c,=32; +mx8+shl1152x6 99 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 106 32 0 none (c,=32; +mx8+shl1152x6 113 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 111 32 0 none (c,=32; +mx8+shl1152x6 104 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 115 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 114 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 109 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 112 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 108 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 118 32 0 none (c,=32; +mx8+shl1152x6 98 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 128 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 103 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 122 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 123 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 120 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 121 32 0 none (c,=32; +mx8+shl1152x6 119 32 0 none (c,=32; +mx8+shl1152x6 127 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 124 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 116 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 125 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 126 32 0 none (c,=32; +mx8+shl1152x6 130 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 131 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 129 32 0 none (c,=32; +mx8+shl1152x6 133 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 138 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 117 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 136 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 140 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 146 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 143 32 0 none (c,=29;(a)=3; +mx8+shl1152x6 132 32 0 none (c,=32; +mx8+shl1152x6 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 141 32 0 none (c,=32; +mx8+shl1152x6 137 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 142 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 144 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 152 32 0 none (c,=32; +mx8+shl1152x6 147 32 0 none (c,=32; +mx8+shl1152x6 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1152x6 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1152x6 139 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 153 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 151 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 149 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 158 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 135 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 157 32 0 none (c,=32; +mx8+shl1152x6 148 32 0 none (c,=32; +mx8+shl1152x6 159 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 160 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 156 32 0 none (c,=32; +mx8+shl1152x6 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 161 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 168 32 0 none (c,=32; +mx8+shl1152x6 166 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 169 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 172 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 170 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 173 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 165 32 0 none (c,=32; +mx8+shl1152x6 167 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 177 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 175 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 171 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 162 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 179 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 183 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 185 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 184 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 180 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 178 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 181 32 0 none (c,=32; +mx8+shl1152x6 188 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 191 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 189 32 0 none (c,=32; +mx8+shl1152x6 195 32 0 none (c,=32; +mx8+shl1152x6 190 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 194 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 192 32 0 none (c,=32; +mx8+shl1152x6 197 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 198 32 0 none (c,=29;(a)=3; +mx8+shl1152x6 193 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 196 32 0 none (c,=32; +mx8+shl1152x6 207 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 201 32 0 none (c,=32; +mx8+shl1152x6 199 32 0 none (c,=32; +mx8+shl1152x6 206 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 204 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 205 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 200 32 0 none (c,=32; +mx8+shl1152x6 186 32 0 none (c,=32; +mx8+shl1152x6 209 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 203 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl1152x6 208 32 0 none (c,=32; +mx8+shl1152x6 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 213 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 211 32 0 none (c,=32; +mx8+shl1152x6 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 215 32 0 none (c,=32; +mx8+shl1152x6 202 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 220 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1152x6 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1152x6 219 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 217 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 221 32 0 none (c,=32; +mx8+shl1152x6 225 32 0 none (c,=29;(a)=3; +mx8+shl1152x6 218 32 0 none (c,=29;(a)=3; +mx8+shl1152x6 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 216 32 0 none (c,=32; +mx8+shl1152x6 227 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 228 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1152x6 229 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 222 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 232 32 0 none (c,=32; +mx8+shl1152x6 231 32 0 none (c,=32; +mx8+shl1152x6 230 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 233 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 235 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 239 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 238 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 242 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 237 32 0 none (c,=30;(a)=2; +mx8+shl1152x6 241 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 226 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 240 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 243 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 244 32 0 none (c,=32; +mx8+shl1152x6 249 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 248 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 250 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 247 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 251 32 0 none (c,=32; +mx8+shl1152x6 252 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 245 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 246 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 3 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 0 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 254 32 0 none (c,=32; +mx8+shl2304x3 4 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 6 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 14 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl1152x6 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 11 32 0 none (c,=32; +mx8+shl2304x3 12 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 253 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 2 32 0 none (c,=32; +mx8+shl2304x3 10 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 7 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 9 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 13 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 19 32 0 none (c,=32; +mx8+shl2304x3 5 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 28 32 0 none (c,=28;(b)=4; +mx8+shl2304x3 16 32 0 none (c,=32; +mx8+shl2304x3 8 32 0 none (c,=32; +mx8+shl2304x3 17 32 0 none (c,=32; +mx8+shl2304x3 18 32 0 none (c,=32; +mx8+shl2304x3 20 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 27 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 23 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 26 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 21 32 0 none (c,=32; +mx8+shl2304x3 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2304x3 31 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 24 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 33 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2304x3 25 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 29 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 34 32 0 none (c,=32; +mx8+shl2304x3 36 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 37 32 0 none (c,=32; +mx8+shl2304x3 30 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 41 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2304x3 38 32 0 none (c,=32; +mx8+shl2304x3 44 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 45 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 42 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 46 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 47 32 0 none (c,=32; +mx8+shl2304x3 48 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2304x3 49 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 53 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 39 32 0 none (c,=32; +mx8+shl2304x3 54 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 50 32 0 none (c,=32; +mx8+shl2304x3 60 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2304x3 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 56 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 58 32 0 none (c,=32; +mx8+shl2304x3 52 32 0 none (c,=32; +mx8+shl2304x3 55 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 59 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl2304x3 64 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 61 32 0 none (c,=32; +mx8+shl2304x3 65 32 0 none (c,=32; +mx8+shl2304x3 62 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 69 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 67 32 0 none (c,=32; +mx8+shl2304x3 68 32 0 none (c,=32; +mx8+shl2304x3 75 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 77 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 70 32 0 none (c,=32; +mx8+shl2304x3 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2304x3 79 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 76 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 81 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 87 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 82 32 0 none (c,=32; +mx8+shl2304x3 86 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 84 32 0 none (c,=32; +mx8+shl2304x3 85 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 71 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 74 32 0 none (c,=32; +mx8+shl2304x3 91 32 0 none (c,=32; +mx8+shl2304x3 93 32 0 none (c,=32; +mx8+shl2304x3 83 32 0 none (c,=32; +mx8+shl2304x3 88 32 0 none (c,=32; +mx8+shl2304x3 94 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 90 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 96 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 102 32 0 none (c,=32; +mx8+shl2304x3 92 32 0 none (c,=32; +mx8+shl2304x3 95 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 98 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 99 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 89 32 0 none (c,=32; +mx8+shl2304x3 100 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 97 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 113 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 106 32 0 none (c,=32; +mx8+shl2304x3 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 101 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 103 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 108 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 109 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 115 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 116 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 114 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 104 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 118 32 0 none (c,=32; +mx8+shl2304x3 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 111 32 0 none (c,=32; +mx8+shl2304x3 112 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 127 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 117 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 120 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 125 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 121 32 0 none (c,=32; +mx8+shl2304x3 119 32 0 none (c,=32; +mx8+shl2304x3 128 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 122 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 124 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 130 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 123 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 131 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 139 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 135 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 132 32 0 none (c,=32; +mx8+shl2304x3 143 32 0 none (c,=29;(a)=3; +mx8+shl2304x3 126 32 0 none (c,=32; +mx8+shl2304x3 136 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 138 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2304x3 133 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 142 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 129 32 0 none (c,=32; +mx8+shl2304x3 144 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 141 32 0 none (c,=32; +mx8+shl2304x3 146 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2304x3 148 32 0 none (c,=32; +mx8+shl2304x3 147 32 0 none (c,=32; +mx8+shl2304x3 153 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 149 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 158 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2304x3 151 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 157 32 0 none (c,=32; +mx8+shl2304x3 137 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 140 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 161 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 156 32 0 none (c,=32; +mx8+shl2304x3 152 32 0 none (c,=32; +mx8+shl2304x3 162 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 159 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 160 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2304x3 166 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 171 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 169 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 165 32 0 none (c,=32; +mx8+shl2304x3 167 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 172 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 173 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 168 32 0 none (c,=32; +mx8+shl2304x3 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2304x3 178 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 177 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 170 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 179 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 181 32 0 none (c,=32; +mx8+shl2304x3 185 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 180 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 175 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 198 32 0 none (c,=29;(a)=3; +mx8+shl2304x3 191 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 186 32 0 none (c,=32; +mx8+shl2304x3 190 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 183 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 189 32 0 none (c,=32; +mx8+shl2304x3 184 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 201 32 0 none (c,=32; +mx8+shl2304x3 194 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 196 32 0 none (c,=32; +mx8+shl2304x3 193 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 195 32 0 none (c,=32; +mx8+shl2304x3 207 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 197 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 199 32 0 none (c,=32; +mx8+shl2304x3 202 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 209 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 205 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 188 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2304x3 192 32 0 none (c,=32; +mx8+shl2304x3 203 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2304x3 211 32 0 none (c,=32; +mx8+shl2304x3 206 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl2304x3 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 208 32 0 none (c,=32; +mx8+shl2304x3 204 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 200 32 0 none (c,=32; +mx8+shl2304x3 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2304x3 225 32 0 none (c,=29;(a)=3; +mx8+shl2304x3 218 32 0 none (c,=29;(a)=3; +mx8+shl2304x3 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 215 32 0 none (c,=32; +mx8+shl2304x3 213 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 222 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 220 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2304x3 216 32 0 none (c,=32; +mx8+shl256x16 2 32 0 none (c,=32; +mx8+shl2304x3 221 32 0 none (c,=32; +mx8+shl2304x3 219 32 0 none (c,=31;(b)=1; +mx8+shl256x16 3 32 0 none (c,=26;(c)=3;(b)=3; +mx8+shl2304x3 217 32 0 none (c,=30;(b)=2; +mx8+shl256x16 1 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 0 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl2304x3 226 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 230 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 227 32 0 none (c,=31;(a)=1; +mx8+shl256x16 4 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl2304x3 228 32 0 none (c,=31;(a)=1; +mx8+shl256x16 5 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 7 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x16 14 32 0 none (c,=24;(b)=4;(c)=3;(a)=1; +mx8+shl2304x3 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 6 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl2304x3 235 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 231 32 0 none (c,=32; +mx8+shl256x16 16 32 0 none (c,=31;(c)=1; +mx8+shl2304x3 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 10 32 0 none (c,=30;(b)=2; +mx8+shl256x16 21 32 0 none (c,=30;(c)=2; +mx8+shl256x16 19 32 0 none (c,=28;(c)=4; +mx8+shl256x16 11 32 0 none (c,=29;(c)=3; +mx8+shl256x16 18 32 0 none (c,=31;(c)=1; +mx8+shl2304x3 229 32 0 none (c,=31;(b)=1; +mx8+shl256x16 17 32 0 none (c,=31;(c)=1; +mx8+shl256x16 13 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 12 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl2304x3 238 32 0 none (c,=31;(b)=1; +mx8+shl256x16 9 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl2304x3 240 32 0 none (c,=31;(b)=1; +mx8+shl256x16 8 32 0 none (c,=30;(c)=2; +mx8+shl2304x3 232 32 0 none (c,=32; +mx8+shl2304x3 237 32 0 none (c,=30;(a)=2; +mx8+shl2304x3 239 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 250 32 0 none (c,=31;(a)=1; +mx8+shl256x16 23 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x16 22 32 0 none (c,=26;(c)=3;(a)=2;(b)=1; +mx8+shl256x16 20 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 25 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 248 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 247 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 242 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 241 32 0 none (c,=29;(b)=3; +mx8+shl256x16 24 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 26 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 246 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 244 32 0 none (c,=32; +mx8+shl2304x3 252 32 0 none (c,=31;(a)=1; +mx8+shl256x16 28 32 0 none (c,=27;(b)=4;(c)=1; +mx8+shl2304x3 253 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 30 32 0 none (c,=25;(c)=5;(b)=2; +mx8+shl2304x3 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 39 32 0 none (c,=26;(c)=6; +mx8+shl2304x3 233 32 0 none (c,=29;(b)=3; +mx8+shl256x16 27 32 0 none (c,=30;(a)=2; +mx8+shl256x16 44 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x16 29 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x16 35 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 38 32 0 none (c,=31;(c)=1; +mx8+shl256x16 32 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl256x16 40 32 0 none (c,=27;(b)=3;(c)=1;(a)=1; +mx8+shl256x16 43 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl2304x3 243 32 0 none (c,=30;(b)=2; +mx8+shl256x16 31 32 0 none (c,=31;(a)=1; +mx8+shl256x16 36 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 42 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl2304x3 251 32 0 none (c,=32; +mx8+shl2304x3 249 32 0 none (c,=31;(b)=1; +mx8+shl256x16 34 32 0 none (c,=30;(c)=2; +mx8+shl2304x3 245 32 0 none (c,=31;(a)=1; +mx8+shl256x16 33 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 45 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x16 41 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 254 32 0 none (c,=32; +mx8+shl256x16 51 32 0 none (c,=25;(c)=3;(b)=3;(a)=1; +mx8+shl256x16 37 32 0 none (c,=30;(c)=2; +mx8+shl256x16 54 32 0 none (c,=31;(b)=1; +mx8+shl256x16 46 32 0 none (c,=31;(a)=1; +mx8+shl256x16 50 32 0 none (c,=31;(c)=1; +mx8+shl256x16 53 32 0 none (c,=30;(b)=2; +mx8+shl256x16 48 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 52 32 0 none (c,=28;(c)=4; +mx8+shl256x16 60 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 47 32 0 none (c,=30;(c)=2; +mx8+shl256x16 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 66 32 0 none (c,=25;(a)=3;(c)=2;(b)=2; +mx8+shl256x16 64 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 56 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x16 68 32 0 none (c,=29;(c)=3; +mx8+shl256x16 59 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 61 32 0 none (c,=32; +mx8+shl256x16 49 32 0 none (c,=31;(a)=1; +mx8+shl256x16 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 62 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 72 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 77 32 0 none (c,=30;(a)=2; +mx8+shl256x16 55 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 65 32 0 none (c,=32; +mx8+shl256x16 73 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 74 32 0 none (c,=31;(c)=1; +mx8+shl256x16 71 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 81 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 69 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 67 32 0 none (c,=31;(c)=1; +mx8+shl256x16 58 32 0 none (c,=32; +mx8+shl256x16 76 32 0 none (c,=31;(b)=1; +mx8+shl256x16 79 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 75 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 94 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 89 32 0 none (c,=31;(c)=1; +mx8+shl256x16 84 32 0 none (c,=32; +mx8+shl256x16 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 87 32 0 none (c,=31;(b)=1; +mx8+shl256x16 97 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 86 32 0 none (c,=31;(b)=1; +mx8+shl256x16 70 32 0 none (c,=31;(c)=1; +mx8+shl256x16 90 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 85 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 88 32 0 none (c,=30;(c)=2; +mx8+shl256x16 83 32 0 none (c,=32; +mx8+shl256x16 80 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 82 32 0 none (c,=31;(c)=1; +mx8+shl256x16 91 32 0 none (c,=32; +mx8+shl256x16 93 32 0 none (c,=30;(c)=2; +mx8+shl256x16 105 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 95 32 0 none (c,=30;(b)=2; +mx8+shl256x16 104 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x16 102 32 0 none (c,=30;(c)=2; +mx8+shl256x16 99 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x16 92 32 0 none (c,=31;(c)=1; +mx8+shl256x16 100 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 118 32 0 none (c,=28;(c)=4; +mx8+shl256x16 106 32 0 none (c,=30;(c)=2; +mx8+shl256x16 112 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 103 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 113 32 0 none (c,=29;(b)=3; +mx8+shl256x16 101 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 109 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x16 114 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 107 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x16 110 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 98 32 0 none (c,=30;(b)=2; +mx8+shl256x16 108 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 116 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 117 32 0 none (c,=30;(a)=2; +mx8+shl256x16 111 32 0 none (c,=30;(c)=2; +mx8+shl256x16 129 32 0 none (c,=30;(c)=2; +mx8+shl256x16 127 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 122 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 96 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 121 32 0 none (c,=27;(c)=5; +mx8+shl256x16 128 32 0 none (c,=27;(b)=3;(c)=2; +mx8+shl256x16 125 32 0 none (c,=26;(c)=5;(b)=1; +mx8+shl256x16 115 32 0 none (c,=30;(a)=2; +mx8+shl256x16 120 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 131 32 0 none (c,=31;(b)=1; +mx8+shl256x16 130 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 141 32 0 none (c,=30;(c)=2; +mx8+shl256x16 135 32 0 none (c,=30;(a)=2; +mx8+shl256x16 126 32 0 none (c,=31;(c)=1; +mx8+shl256x16 138 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x16 123 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x16 148 32 0 none (c,=29;(c)=3; +mx8+shl256x16 146 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x16 143 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x16 142 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 134 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 136 32 0 none (c,=31;(b)=1; +mx8+shl256x16 144 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 147 32 0 none (c,=29;(c)=3; +mx8+shl256x16 133 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 140 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 137 32 0 none (c,=30;(b)=2; +mx8+shl256x16 124 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 139 32 0 none (c,=29;(b)=3; +mx8+shl256x16 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl256x16 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl256x16 159 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 119 32 0 none (c,=32; +mx8+shl256x16 132 32 0 none (c,=30;(c)=2; +mx8+shl256x16 153 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 161 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 155 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl256x16 169 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 149 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x16 158 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 150 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 164 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 165 32 0 none (c,=31;(c)=1; +mx8+shl256x16 173 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 157 32 0 none (c,=31;(c)=1; +mx8+shl256x16 160 32 0 none (c,=30;(b)=2; +mx8+shl256x16 166 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 174 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 151 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 167 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 163 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 172 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 175 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 156 32 0 none (c,=31;(c)=1; +mx8+shl256x16 162 32 0 none (c,=31;(a)=1; +mx8+shl256x16 179 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 177 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 152 32 0 none (c,=32; +mx8+shl256x16 171 32 0 none (c,=31;(b)=1; +mx8+shl256x16 176 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 187 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 168 32 0 none (c,=32; +mx8+shl256x16 178 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 182 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 180 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 170 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 188 32 0 none (c,=26;(c)=3;(b)=2;(a)=1; +mx8+shl256x16 181 32 0 none (c,=31;(c)=1; +mx8+shl256x16 184 32 0 none (c,=31;(b)=1; +mx8+shl256x16 194 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x16 191 32 0 none (c,=31;(b)=1; +mx8+shl256x16 189 32 0 none (c,=32; +mx8+shl256x16 183 32 0 none (c,=31;(a)=1; +mx8+shl256x16 186 32 0 none (c,=32; +mx8+shl256x16 192 32 0 none (c,=29;(c)=3; +mx8+shl256x16 190 32 0 none (c,=30;(a)=2; +mx8+shl256x16 206 32 0 none (c,=31;(b)=1; +mx8+shl256x16 209 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 205 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 212 32 0 none (c,=27;(b)=3;(c)=1;(a)=1; +mx8+shl256x16 213 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 198 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x16 197 32 0 none (c,=31;(b)=1; +mx8+shl256x16 211 32 0 none (c,=31;(c)=1; +mx8+shl256x16 214 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 185 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x16 196 32 0 none (c,=29;(c)=3; +mx8+shl256x16 195 32 0 none (c,=32; +mx8+shl256x16 193 32 0 none (c,=31;(b)=1; +mx8+shl256x16 210 32 0 none (c,=26;(c)=2;(b)=2;(a)=2; +mx8+shl256x16 208 32 0 none (c,=29;(c)=3; +mx8+shl256x16 200 32 0 none (c,=32; +mx8+shl256x16 203 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 202 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 199 32 0 none (c,=31;(c)=1; +mx8+shl256x16 218 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x16 204 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 229 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 207 32 0 none (c,=31;(a)=1; +mx8+shl256x16 223 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 215 32 0 none (c,=32; +mx8+shl256x16 227 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x16 201 32 0 none (c,=30;(c)=2; +mx8+shl256x16 222 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 228 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 219 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 225 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x16 216 32 0 none (c,=28;(c)=4; +mx8+shl256x16 230 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 221 32 0 none (c,=29;(c)=3; +mx8+shl256x16 220 32 0 none (c,=27;(c)=2;(a)=2;(b)=1; +mx8+shl256x16 217 32 0 none (c,=30;(b)=2; +mx8+shl256x16 224 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl256x16 236 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 231 32 0 none (c,=30;(c)=2; +mx8+shl256x16 234 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 235 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 233 32 0 none (c,=29;(b)=3; +mx8+shl256x16 237 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x16 239 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 251 32 0 none (c,=31;(c)=1; +mx8+shl256x16 238 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 226 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x16 252 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 241 32 0 none (c,=29;(b)=3; +mx8+shl256x16 246 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 253 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x16 243 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 250 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 249 32 0 none (c,=31;(b)=1; +mx8+shl256x16 245 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 244 32 0 none (c,=32; +mx8+shl256x16 247 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 242 32 0 none (c,=29;(b)=3; +mx8+shl256x16 254 32 0 none (c,=31;(c)=1; +mx8+shl256x16 232 32 0 none (c,=32; +mx8+shl256x16 240 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 255 32 0 none (c,=27;(c)=3;(b)=1;(a)=1; +mx8+shl512x8 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 248 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 2 32 0 none (c,=31;(c)=1; +mx8+shl512x8 0 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl512x8 7 32 0 none (c,=31;(a)=1; +mx8+shl512x8 14 32 0 none (c,=26;(b)=4;(c)=1;(a)=1; +mx8+shl512x8 11 32 0 none (c,=32; +mx8+shl512x8 10 32 0 none (c,=30;(b)=2; +mx8+shl512x8 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 4 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 6 32 0 none (c,=31;(b)=1; +mx8+shl512x8 12 32 0 none (c,=31;(b)=1; +mx8+shl512x8 13 32 0 none (c,=31;(b)=1; +mx8+shl512x8 19 32 0 none (c,=32; +mx8+shl512x8 18 32 0 none (c,=31;(c)=1; +mx8+shl512x8 9 32 0 none (c,=31;(b)=1; +mx8+shl512x8 3 32 0 none (c,=29;(b)=3; +mx8+shl512x8 17 32 0 none (c,=32; +mx8+shl512x8 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 25 32 0 none (c,=31;(b)=1; +mx8+shl512x8 21 32 0 none (c,=32; +mx8+shl512x8 23 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl512x8 27 32 0 none (c,=30;(a)=2; +mx8+shl512x8 8 32 0 none (c,=31;(c)=1; +mx8+shl512x8 16 32 0 none (c,=32; +mx8+shl512x8 28 32 0 none (c,=28;(b)=4; +mx8+shl512x8 24 32 0 none (c,=30;(b)=2; +mx8+shl512x8 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 5 32 0 none (c,=31;(b)=1; +mx8+shl512x8 20 32 0 none (c,=31;(b)=1; +mx8+shl512x8 31 32 0 none (c,=31;(a)=1; +mx8+shl512x8 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl512x8 26 32 0 none (c,=31;(a)=1; +mx8+shl512x8 38 32 0 none (c,=32; +mx8+shl512x8 29 32 0 none (c,=31;(a)=1; +mx8+shl512x8 47 32 0 none (c,=32; +mx8+shl512x8 36 32 0 none (c,=30;(b)=2; +mx8+shl512x8 30 32 0 none (c,=30;(b)=2; +mx8+shl512x8 33 32 0 none (c,=31;(b)=1; +mx8+shl512x8 42 32 0 none (c,=31;(a)=1; +mx8+shl512x8 34 32 0 none (c,=32; +mx8+shl512x8 37 32 0 none (c,=32; +mx8+shl512x8 44 32 0 none (c,=29;(b)=3; +mx8+shl512x8 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl512x8 49 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl512x8 39 32 0 none (c,=32; +mx8+shl512x8 48 32 0 none (c,=31;(b)=1; +mx8+shl512x8 54 32 0 none (c,=31;(b)=1; +mx8+shl512x8 45 32 0 none (c,=31;(a)=1; +mx8+shl512x8 55 32 0 none (c,=31;(b)=1; +mx8+shl512x8 41 32 0 none (c,=30;(b)=2; +mx8+shl512x8 59 32 0 none (c,=30;(b)=2; +mx8+shl512x8 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 52 32 0 none (c,=32; +mx8+shl512x8 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 53 32 0 none (c,=30;(b)=2; +mx8+shl512x8 46 32 0 none (c,=31;(a)=1; +mx8+shl512x8 50 32 0 none (c,=32; +mx8+shl512x8 58 32 0 none (c,=31;(c)=1; +mx8+shl512x8 56 32 0 none (c,=31;(a)=1; +mx8+shl512x8 64 32 0 none (c,=30;(b)=2; +mx8+shl512x8 62 32 0 none (c,=31;(b)=1; +mx8+shl512x8 65 32 0 none (c,=31;(c)=1; +mx8+shl512x8 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 69 32 0 none (c,=31;(b)=1; +mx8+shl512x8 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl512x8 60 32 0 none (c,=30;(b)=2; +mx8+shl512x8 61 32 0 none (c,=32; +mx8+shl512x8 70 32 0 none (c,=32; +mx8+shl512x8 79 32 0 none (c,=30;(b)=2; +mx8+shl512x8 71 32 0 none (c,=31;(b)=1; +mx8+shl512x8 74 32 0 none (c,=32; +mx8+shl512x8 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 77 32 0 none (c,=30;(a)=2; +mx8+shl512x8 67 32 0 none (c,=32; +mx8+shl512x8 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 81 32 0 none (c,=31;(a)=1; +mx8+shl512x8 75 32 0 none (c,=31;(b)=1; +mx8+shl512x8 76 32 0 none (c,=31;(b)=1; +mx8+shl512x8 68 32 0 none (c,=32; +mx8+shl512x8 86 32 0 none (c,=31;(b)=1; +mx8+shl512x8 82 32 0 none (c,=32; +mx8+shl512x8 83 32 0 none (c,=32; +mx8+shl512x8 85 32 0 none (c,=31;(b)=1; +mx8+shl512x8 87 32 0 none (c,=31;(b)=1; +mx8+shl512x8 89 32 0 none (c,=32; +mx8+shl512x8 84 32 0 none (c,=32; +mx8+shl512x8 94 32 0 none (c,=30;(b)=2; +mx8+shl512x8 93 32 0 none (c,=32; +mx8+shl512x8 99 32 0 none (c,=31;(b)=1; +mx8+shl512x8 96 32 0 none (c,=31;(b)=1; +mx8+shl512x8 88 32 0 none (c,=32; +mx8+shl512x8 97 32 0 none (c,=31;(b)=1; +mx8+shl512x8 90 32 0 none (c,=31;(b)=1; +mx8+shl512x8 100 32 0 none (c,=31;(a)=1; +mx8+shl512x8 95 32 0 none (c,=30;(b)=2; +mx8+shl512x8 92 32 0 none (c,=32; +mx8+shl512x8 91 32 0 none (c,=32; +mx8+shl512x8 104 32 0 none (c,=31;(a)=1; +mx8+shl512x8 106 32 0 none (c,=32; +mx8+shl512x8 102 32 0 none (c,=32; +mx8+shl512x8 98 32 0 none (c,=30;(b)=2; +mx8+shl512x8 108 32 0 none (c,=31;(a)=1; +mx8+shl512x8 101 32 0 none (c,=31;(a)=1; +mx8+shl512x8 103 32 0 none (c,=31;(b)=1; +mx8+shl512x8 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 109 32 0 none (c,=30;(a)=2; +mx8+shl512x8 118 32 0 none (c,=32; +mx8+shl512x8 115 32 0 none (c,=30;(a)=2; +mx8+shl512x8 111 32 0 none (c,=32; +mx8+shl512x8 112 32 0 none (c,=31;(b)=1; +mx8+shl512x8 123 32 0 none (c,=30;(a)=2; +mx8+shl512x8 116 32 0 none (c,=31;(a)=1; +mx8+shl512x8 117 32 0 none (c,=30;(a)=2; +mx8+shl512x8 113 32 0 none (c,=29;(b)=3; +mx8+shl512x8 127 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 114 32 0 none (c,=31;(a)=1; +mx8+shl512x8 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 122 32 0 none (c,=31;(b)=1; +mx8+shl512x8 121 32 0 none (c,=32; +mx8+shl512x8 119 32 0 none (c,=32; +mx8+shl512x8 125 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 124 32 0 none (c,=31;(b)=1; +mx8+shl512x8 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 120 32 0 none (c,=31;(b)=1; +mx8+shl512x8 128 32 0 none (c,=29;(b)=3; +mx8+shl512x8 130 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 126 32 0 none (c,=32; +mx8+shl512x8 129 32 0 none (c,=32; +mx8+shl512x8 133 32 0 none (c,=30;(b)=2; +mx8+shl512x8 143 32 0 none (c,=29;(a)=3; +mx8+shl512x8 139 32 0 none (c,=29;(b)=3; +mx8+shl512x8 132 32 0 none (c,=32; +mx8+shl512x8 138 32 0 none (c,=30;(a)=2; +mx8+shl512x8 131 32 0 none (c,=31;(b)=1; +mx8+shl512x8 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 136 32 0 none (c,=31;(b)=1; +mx8+shl512x8 137 32 0 none (c,=30;(b)=2; +mx8+shl512x8 141 32 0 none (c,=32; +mx8+shl512x8 142 32 0 none (c,=30;(b)=2; +mx8+shl512x8 135 32 0 none (c,=30;(a)=2; +mx8+shl512x8 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl512x8 144 32 0 none (c,=31;(b)=1; +mx8+shl512x8 148 32 0 none (c,=32; +mx8+shl512x8 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 149 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl512x8 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 146 32 0 none (c,=30;(b)=2; +mx8+shl512x8 147 32 0 none (c,=32; +mx8+shl512x8 140 32 0 none (c,=31;(b)=1; +mx8+shl512x8 151 32 0 none (c,=31;(a)=1; +mx8+shl512x8 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 161 32 0 none (c,=31;(b)=1; +mx8+shl512x8 160 32 0 none (c,=30;(b)=2; +mx8+shl512x8 156 32 0 none (c,=32; +mx8+shl512x8 152 32 0 none (c,=32; +mx8+shl512x8 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 158 32 0 none (c,=30;(b)=2; +mx8+shl512x8 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 153 32 0 none (c,=31;(a)=1; +mx8+shl512x8 157 32 0 none (c,=32; +mx8+shl512x8 169 32 0 none (c,=30;(b)=2; +mx8+shl512x8 167 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl512x8 162 32 0 none (c,=31;(a)=1; +mx8+shl512x8 171 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 170 32 0 none (c,=31;(a)=1; +mx8+shl512x8 173 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 166 32 0 none (c,=31;(b)=1; +mx8+shl512x8 165 32 0 none (c,=31;(c)=1; +mx8+shl512x8 172 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 159 32 0 none (c,=31;(b)=1; +mx8+shl512x8 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 178 32 0 none (c,=31;(b)=1; +mx8+shl512x8 177 32 0 none (c,=31;(b)=1; +mx8+shl512x8 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 175 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 179 32 0 none (c,=31;(a)=1; +mx8+shl512x8 181 32 0 none (c,=30;(c)=2; +mx8+shl512x8 188 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl512x8 180 32 0 none (c,=30;(b)=2; +mx8+shl512x8 168 32 0 none (c,=32; +mx8+shl512x8 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 185 32 0 none (c,=30;(a)=2; +mx8+shl512x8 183 32 0 none (c,=31;(a)=1; +mx8+shl512x8 184 32 0 none (c,=31;(b)=1; +mx8+shl512x8 190 32 0 none (c,=30;(a)=2; +mx8+shl512x8 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 198 32 0 none (c,=29;(a)=3; +mx8+shl512x8 189 32 0 none (c,=32; +mx8+shl512x8 194 32 0 none (c,=29;(b)=3; +mx8+shl512x8 191 32 0 none (c,=31;(b)=1; +mx8+shl512x8 193 32 0 none (c,=31;(b)=1; +mx8+shl512x8 192 32 0 none (c,=32; +mx8+shl512x8 186 32 0 none (c,=32; +mx8+shl512x8 195 32 0 none (c,=32; +mx8+shl512x8 197 32 0 none (c,=31;(b)=1; +mx8+shl512x8 203 32 0 none (c,=31;(a)=1; +mx8+shl512x8 201 32 0 none (c,=32; +mx8+shl512x8 209 32 0 none (c,=30;(b)=2; +mx8+shl512x8 204 32 0 none (c,=31;(b)=1; +mx8+shl512x8 208 32 0 none (c,=32; +mx8+shl512x8 196 32 0 none (c,=32; +mx8+shl512x8 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl512x8 205 32 0 none (c,=31;(b)=1; +mx8+shl512x8 211 32 0 none (c,=32; +mx8+shl512x8 206 32 0 none (c,=31;(b)=1; +mx8+shl512x8 202 32 0 none (c,=30;(b)=2; +mx8+shl512x8 213 32 0 none (c,=31;(a)=1; +mx8+shl512x8 200 32 0 none (c,=32; +mx8+shl512x8 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl512x8 207 32 0 none (c,=31;(a)=1; +mx8+shl512x8 218 32 0 none (c,=29;(a)=3; +mx8+shl512x8 217 32 0 none (c,=30;(b)=2; +mx8+shl512x8 221 32 0 none (c,=32; +mx8+shl512x8 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 199 32 0 none (c,=32; +mx8+shl512x8 219 32 0 none (c,=31;(b)=1; +mx8+shl512x8 216 32 0 none (c,=31;(c)=1; +mx8+shl512x8 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 222 32 0 none (c,=31;(b)=1; +mx8+shl512x8 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 230 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 229 32 0 none (c,=31;(b)=1; +mx8+shl512x8 215 32 0 none (c,=32; +mx8+shl512x8 226 32 0 none (c,=31;(a)=1; +mx8+shl512x8 228 32 0 none (c,=31;(a)=1; +mx8+shl512x8 241 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl512x8 227 32 0 none (c,=31;(a)=1; +mx8+shl512x8 220 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 232 32 0 none (c,=32; +mx8+shl512x8 233 32 0 none (c,=29;(b)=3; +mx8+shl512x8 239 32 0 none (c,=31;(a)=1; +mx8+shl512x8 238 32 0 none (c,=31;(b)=1; +mx8+shl512x8 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 225 32 0 none (c,=29;(a)=3; +mx8+shl512x8 240 32 0 none (c,=31;(b)=1; +mx8+shl512x8 242 32 0 none (c,=29;(b)=3; +mx8+shl512x8 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 245 32 0 none (c,=31;(a)=1; +mx8+shl512x8 243 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl512x8 237 32 0 none (c,=30;(a)=2; +mx8+shl512x8 244 32 0 none (c,=32; +mx8+shl512x8 231 32 0 none (c,=31;(c)=1; +mx8+shl512x8 247 32 0 none (c,=31;(b)=1; +mx8+shl512x8 248 32 0 none (c,=31;(b)=1; +mx8+shl512x8 251 32 0 none (c,=32; +mx8+shl512x8 235 32 0 none (c,=31;(b)=1; +mx8+shl512x8 252 32 0 none (c,=31;(a)=1; +mx8+shl512x8 250 32 0 none (c,=31;(a)=1; +mx8+shl512x8 253 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 3 32 0 none (c,=29;(b)=3; +mx8+shl512x8 254 32 0 none (c,=32; +mx8+shl512x8 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 249 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 6 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 4 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 246 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 2 32 0 none (c,=32; +mx8+shl1024x4 0 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 14 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl1024x4 8 32 0 none (c,=32; +mx8+shl1024x4 5 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 10 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 11 32 0 none (c,=32; +mx8+shl1024x4 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 12 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 7 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1024x4 18 32 0 none (c,=32; +mx8+shl1024x4 21 32 0 none (c,=32; +mx8+shl1024x4 17 32 0 none (c,=32; +mx8+shl1024x4 19 32 0 none (c,=32; +mx8+shl1024x4 13 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 16 32 0 none (c,=32; +mx8+shl1024x4 29 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 25 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 28 32 0 none (c,=28;(b)=4; +mx8+shl1024x4 23 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 27 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 30 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 20 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 26 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 24 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1024x4 31 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 9 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 36 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 33 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 34 32 0 none (c,=32; +mx8+shl1024x4 41 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1024x4 39 32 0 none (c,=32; +mx8+shl1024x4 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1024x4 44 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 38 32 0 none (c,=32; +mx8+shl1024x4 37 32 0 none (c,=32; +mx8+shl1024x4 46 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 47 32 0 none (c,=32; +mx8+shl1024x4 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1024x4 45 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 49 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 48 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 54 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 60 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 52 32 0 none (c,=32; +mx8+shl1024x4 59 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 53 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 55 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 58 32 0 none (c,=32; +mx8+shl1024x4 42 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 64 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 62 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl1024x4 61 32 0 none (c,=32; +mx8+shl1024x4 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 65 32 0 none (c,=32; +mx8+shl1024x4 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 67 32 0 none (c,=32; +mx8+shl1024x4 69 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 71 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 70 32 0 none (c,=32; +mx8+shl1024x4 75 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 50 32 0 none (c,=32; +mx8+shl1024x4 79 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 74 32 0 none (c,=32; +mx8+shl1024x4 56 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1024x4 77 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 81 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 76 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 68 32 0 none (c,=32; +mx8+shl1024x4 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 85 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 82 32 0 none (c,=32; +mx8+shl1024x4 86 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 84 32 0 none (c,=32; +mx8+shl1024x4 90 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 89 32 0 none (c,=32; +mx8+shl1024x4 83 32 0 none (c,=32; +mx8+shl1024x4 87 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 88 32 0 none (c,=32; +mx8+shl1024x4 95 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 92 32 0 none (c,=32; +mx8+shl1024x4 94 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 99 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 91 32 0 none (c,=32; +mx8+shl1024x4 98 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 93 32 0 none (c,=32; +mx8+shl1024x4 96 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 97 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 100 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 109 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 101 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 102 32 0 none (c,=32; +mx8+shl1024x4 106 32 0 none (c,=32; +mx8+shl1024x4 103 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 111 32 0 none (c,=32; +mx8+shl1024x4 104 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 117 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 113 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 122 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 115 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 114 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 119 32 0 none (c,=32; +mx8+shl1024x4 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 108 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 116 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 120 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 123 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 127 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 126 32 0 none (c,=32; +mx8+shl1024x4 125 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 131 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 112 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 121 32 0 none (c,=32; +mx8+shl1024x4 128 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 124 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 118 32 0 none (c,=32; +mx8+shl1024x4 130 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 133 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 129 32 0 none (c,=32; +mx8+shl1024x4 132 32 0 none (c,=32; +mx8+shl1024x4 136 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 137 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 138 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 140 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1024x4 142 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 143 32 0 none (c,=29;(a)=3; +mx8+shl1024x4 141 32 0 none (c,=32; +mx8+shl1024x4 135 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 144 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 139 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1024x4 146 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1024x4 149 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 148 32 0 none (c,=32; +mx8+shl1024x4 147 32 0 none (c,=32; +mx8+shl1024x4 152 32 0 none (c,=32; +mx8+shl1024x4 159 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 161 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 153 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 156 32 0 none (c,=32; +mx8+shl1024x4 166 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1024x4 158 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 160 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 168 32 0 none (c,=32; +mx8+shl1024x4 167 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 171 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 178 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 162 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 169 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 165 32 0 none (c,=32; +mx8+shl1024x4 157 32 0 none (c,=32; +mx8+shl1024x4 175 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 170 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 177 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 173 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 172 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 151 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1024x4 179 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 180 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 183 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 181 32 0 none (c,=32; +mx8+shl1024x4 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 185 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 184 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 190 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 186 32 0 none (c,=32; +mx8+shl1024x4 188 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1024x4 191 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 189 32 0 none (c,=32; +mx8+shl1024x4 193 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 192 32 0 none (c,=32; +mx8+shl1024x4 198 32 0 none (c,=29;(a)=3; +mx8+shl1024x4 194 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 195 32 0 none (c,=32; +mx8+shl1024x4 199 32 0 none (c,=32; +mx8+shl1024x4 197 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 200 32 0 none (c,=32; +mx8+shl1024x4 196 32 0 none (c,=32; +mx8+shl1024x4 202 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 204 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 205 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 207 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 203 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 201 32 0 none (c,=32; +mx8+shl1024x4 218 32 0 none (c,=29;(a)=3; +mx8+shl1024x4 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl1024x4 206 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 208 32 0 none (c,=32; +mx8+shl1024x4 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl1024x4 220 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1024x4 213 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 211 32 0 none (c,=32; +mx8+shl1024x4 209 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 219 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 217 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 215 32 0 none (c,=32; +mx8+shl1024x4 221 32 0 none (c,=32; +mx8+shl1024x4 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1024x4 216 32 0 none (c,=32; +mx8+shl1024x4 226 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 225 32 0 none (c,=29;(a)=3; +mx8+shl1024x4 227 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 233 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 232 32 0 none (c,=32; +mx8+shl1024x4 238 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 231 32 0 none (c,=32; +mx8+shl1024x4 235 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 229 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 237 32 0 none (c,=30;(a)=2; +mx8+shl1024x4 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 239 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 240 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 230 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 242 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 222 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 241 32 0 none (c,=29;(b)=3; +mx8+shl1024x4 243 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 228 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 246 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 249 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 245 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 247 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 250 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 248 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 244 32 0 none (c,=32; +mx8+shl1024x4 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 251 32 0 none (c,=32; +mx8+shl1024x4 252 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 253 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 254 32 0 none (c,=32; +mx8+shl2048x2 3 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 4 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 0 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 6 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 9 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 10 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 11 32 0 none (c,=32; +mx8+shl2048x2 14 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl2048x2 12 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 2 32 0 none (c,=32; +mx8+shl2048x2 5 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 7 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 8 32 0 none (c,=32; +mx8+shl2048x2 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2048x2 28 32 0 none (c,=28;(b)=4; +mx8+shl2048x2 17 32 0 none (c,=32; +mx8+shl2048x2 16 32 0 none (c,=32; +mx8+shl2048x2 26 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 27 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 18 32 0 none (c,=32; +mx8+shl2048x2 23 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 19 32 0 none (c,=32; +mx8+shl2048x2 13 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 21 32 0 none (c,=32; +mx8+shl2048x2 34 32 0 none (c,=32; +mx8+shl2048x2 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2048x2 20 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 31 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 29 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 33 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 38 32 0 none (c,=32; +mx8+shl2048x2 30 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2048x2 24 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 36 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2048x2 42 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 25 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 41 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 44 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 37 32 0 none (c,=32; +mx8+shl2048x2 39 32 0 none (c,=32; +mx8+shl2048x2 46 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2048x2 45 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 47 32 0 none (c,=32; +mx8+shl2048x2 48 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 54 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 60 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 53 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 50 32 0 none (c,=32; +mx8+shl2048x2 59 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 49 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 56 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 55 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 58 32 0 none (c,=32; +mx8+shl2048x2 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 52 32 0 none (c,=32; +mx8+shl2048x2 61 32 0 none (c,=32; +mx8+shl2048x2 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 62 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 65 32 0 none (c,=32; +mx8+shl2048x2 70 32 0 none (c,=32; +mx8+shl2048x2 67 32 0 none (c,=32; +mx8+shl2048x2 69 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 77 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 64 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 68 32 0 none (c,=32; +mx8+shl2048x2 74 32 0 none (c,=32; +mx8+shl2048x2 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl2048x2 75 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 79 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 71 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 81 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 76 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2048x2 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 85 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 88 32 0 none (c,=32; +mx8+shl2048x2 82 32 0 none (c,=32; +mx8+shl2048x2 83 32 0 none (c,=32; +mx8+shl2048x2 87 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 86 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 91 32 0 none (c,=32; +mx8+shl2048x2 90 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 89 32 0 none (c,=32; +mx8+shl2048x2 94 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 84 32 0 none (c,=32; +mx8+shl2048x2 92 32 0 none (c,=32; +mx8+shl2048x2 93 32 0 none (c,=32; +mx8+shl2048x2 98 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 100 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 96 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 99 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 97 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 95 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 104 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 106 32 0 none (c,=32; +mx8+shl2048x2 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 101 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 102 32 0 none (c,=32; +mx8+shl2048x2 103 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 109 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 112 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 111 32 0 none (c,=32; +mx8+shl2048x2 108 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 113 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 115 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 114 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 117 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 122 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 116 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 125 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 120 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 123 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 121 32 0 none (c,=32; +mx8+shl2048x2 127 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 118 32 0 none (c,=32; +mx8+shl2048x2 119 32 0 none (c,=32; +mx8+shl2048x2 128 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 136 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 131 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 124 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 139 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 133 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 130 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 126 32 0 none (c,=32; +mx8+shl2048x2 143 32 0 none (c,=29;(a)=3; +mx8+shl2048x2 132 32 0 none (c,=32; +mx8+shl2048x2 129 32 0 none (c,=32; +mx8+shl2048x2 135 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 137 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 140 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 138 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2048x2 141 32 0 none (c,=32; +mx8+shl2048x2 142 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 144 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2048x2 148 32 0 none (c,=32; +mx8+shl2048x2 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2048x2 146 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 151 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 149 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 152 32 0 none (c,=32; +mx8+shl2048x2 153 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 147 32 0 none (c,=32; +mx8+shl2048x2 158 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 161 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 156 32 0 none (c,=32; +mx8+shl2048x2 159 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 157 32 0 none (c,=32; +mx8+shl2048x2 160 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2048x2 169 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 162 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 167 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 165 32 0 none (c,=32; +mx8+shl2048x2 166 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 171 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 170 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 168 32 0 none (c,=32; +mx8+shl2048x2 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2048x2 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 175 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 173 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 180 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 184 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 181 32 0 none (c,=32; +mx8+shl2048x2 177 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 179 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 188 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl2048x2 183 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 190 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 191 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 185 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 189 32 0 none (c,=32; +mx8+shl2048x2 178 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 186 32 0 none (c,=32; +mx8+shl2048x2 172 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 194 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 193 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 192 32 0 none (c,=32; +mx8+shl2048x2 198 32 0 none (c,=29;(a)=3; +mx8+shl2048x2 197 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 195 32 0 none (c,=32; +mx8+shl2048x2 196 32 0 none (c,=32; +mx8+shl2048x2 199 32 0 none (c,=32; +mx8+shl2048x2 209 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl2048x2 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl2048x2 202 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 201 32 0 none (c,=32; +mx8+shl2048x2 211 32 0 none (c,=32; +mx8+shl2048x2 203 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 205 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 200 32 0 none (c,=32; +mx8+shl2048x2 207 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 206 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 208 32 0 none (c,=32; +mx8+shl2048x2 204 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 215 32 0 none (c,=32; +mx8+shl2048x2 218 32 0 none (c,=29;(a)=3; +mx8+shl2048x2 220 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2048x2 225 32 0 none (c,=29;(a)=3; +mx8+shl2048x2 217 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 216 32 0 none (c,=32; +mx8+shl2048x2 221 32 0 none (c,=32; +mx8+shl2048x2 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2048x2 230 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 226 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 228 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 219 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 222 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 233 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 231 32 0 none (c,=32; +mx8+shl2048x2 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 232 32 0 none (c,=32; +mx8+shl2048x2 229 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 227 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 213 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 238 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 242 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 239 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 235 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 237 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 243 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 240 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 241 32 0 none (c,=29;(b)=3; +mx8+shl2048x2 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 246 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 245 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 249 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 250 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 247 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 252 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 251 32 0 none (c,=32; +mx8+shl2048x2 244 32 0 none (c,=32; +mx8+shl2048x2 253 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 248 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 254 32 0 none (c,=32; +mx8+shl4096x1 3 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 0 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 2 32 0 none (c,=32; +mx8+shl4096x1 5 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 11 32 0 none (c,=32; +mx8+shl4096x1 4 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 7 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 9 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 14 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl4096x1 8 32 0 none (c,=32; +mx8+shl4096x1 10 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 6 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 12 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 19 32 0 none (c,=32; +mx8+shl4096x1 13 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 17 32 0 none (c,=32; +mx8+shl4096x1 28 32 0 none (c,=28;(b)=4; +mx8+shl4096x1 23 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 18 32 0 none (c,=32; +mx8+shl4096x1 16 32 0 none (c,=32; +mx8+shl4096x1 21 32 0 none (c,=32; +mx8+shl4096x1 26 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 25 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 20 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 27 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 24 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 30 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 31 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 29 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 33 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 34 32 0 none (c,=32; +mx8+shl4096x1 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 42 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 38 32 0 none (c,=32; +mx8+shl4096x1 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x1 41 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 46 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 39 32 0 none (c,=32; +mx8+shl4096x1 37 32 0 none (c,=32; +mx8+shl4096x1 36 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x1 44 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 47 32 0 none (c,=32; +mx8+shl4096x1 45 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x1 48 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 49 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 50 32 0 none (c,=32; +mx8+shl4096x1 53 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 59 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 55 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 56 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 60 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 52 32 0 none (c,=32; +mx8+shl4096x1 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 54 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 58 32 0 none (c,=32; +mx8+shl4096x1 61 32 0 none (c,=32; +mx8+shl4096x1 67 32 0 none (c,=32; +mx8+shl4096x1 75 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 64 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 71 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 62 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 70 32 0 none (c,=32; +mx8+shl4096x1 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl4096x1 79 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 65 32 0 none (c,=32; +mx8+shl4096x1 77 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 68 32 0 none (c,=32; +mx8+shl4096x1 69 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 74 32 0 none (c,=32; +mx8+shl4096x1 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 81 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 76 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 82 32 0 none (c,=32; +mx8+shl4096x1 84 32 0 none (c,=32; +mx8+shl4096x1 86 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 85 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 87 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 89 32 0 none (c,=32; +mx8+shl4096x1 88 32 0 none (c,=32; +mx8+shl4096x1 90 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 94 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 93 32 0 none (c,=32; +mx8+shl4096x1 92 32 0 none (c,=32; +mx8+shl4096x1 91 32 0 none (c,=32; +mx8+shl4096x1 95 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 96 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 83 32 0 none (c,=32; +mx8+shl4096x1 98 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 97 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 100 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 101 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 102 32 0 none (c,=32; +mx8+shl4096x1 99 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 104 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 106 32 0 none (c,=32; +mx8+shl4096x1 103 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 109 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 111 32 0 none (c,=32; +mx8+shl4096x1 108 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 115 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 117 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 112 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 118 32 0 none (c,=32; +mx8+shl4096x1 114 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 116 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 122 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 123 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 127 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 128 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 120 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 121 32 0 none (c,=32; +mx8+shl4096x1 124 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 125 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 119 32 0 none (c,=32; +mx8+shl4096x1 113 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 129 32 0 none (c,=32; +mx8+shl4096x1 126 32 0 none (c,=32; +mx8+shl4096x1 132 32 0 none (c,=32; +mx8+shl4096x1 131 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 133 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 130 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 139 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 138 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 136 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 137 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 141 32 0 none (c,=32; +mx8+shl4096x1 143 32 0 none (c,=29;(a)=3; +mx8+shl4096x1 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 140 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 142 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 135 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 147 32 0 none (c,=32; +mx8+shl4096x1 144 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 151 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 149 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x1 146 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 153 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 152 32 0 none (c,=32; +mx8+shl4096x1 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x1 148 32 0 none (c,=32; +mx8+shl4096x1 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 160 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 158 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 157 32 0 none (c,=32; +mx8+shl4096x1 159 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 169 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 156 32 0 none (c,=32; +mx8+shl4096x1 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 161 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 166 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 170 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 167 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 162 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 165 32 0 none (c,=32; +mx8+shl4096x1 168 32 0 none (c,=32; +mx8+shl4096x1 171 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 173 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 172 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 175 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 177 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 178 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 180 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 181 32 0 none (c,=32; +mx8+shl4096x1 179 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 184 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 183 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 186 32 0 none (c,=32; +mx8+shl4096x1 191 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 185 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 188 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 189 32 0 none (c,=32; +mx8+shl4096x1 194 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 190 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 197 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 193 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 198 32 0 none (c,=29;(a)=3; +mx8+shl4096x1 196 32 0 none (c,=32; +mx8+shl4096x1 192 32 0 none (c,=32; +mx8+shl4096x1 202 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x1 209 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 195 32 0 none (c,=32; +mx8+shl4096x1 201 32 0 none (c,=32; +mx8+shl4096x1 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl4096x1 205 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 204 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 203 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 200 32 0 none (c,=32; +mx8+shl4096x1 208 32 0 none (c,=32; +mx8+shl4096x1 206 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 213 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 217 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 220 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x1 207 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 199 32 0 none (c,=32; +mx8+shl4096x1 215 32 0 none (c,=32; +mx8+shl4096x1 218 32 0 none (c,=29;(a)=3; +mx8+shl4096x1 216 32 0 none (c,=32; +mx8+shl4096x1 219 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 222 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 211 32 0 none (c,=32; +mx8+shl4096x1 221 32 0 none (c,=32; +mx8+shl4096x1 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x1 225 32 0 none (c,=29;(a)=3; +mx8+shl4096x1 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 227 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 226 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 228 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 229 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 233 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 231 32 0 none (c,=32; +mx8+shl4096x1 235 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 232 32 0 none (c,=32; +mx8+shl4096x1 239 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 237 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 238 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 230 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 240 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 241 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 243 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 242 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 247 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 246 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 244 32 0 none (c,=32; +mx8+shl4096x1 248 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 245 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 251 32 0 none (c,=32; +mx8+shl4096x1 254 32 0 none (c,=32; +mx8+shl4096x1 250 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 249 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 252 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 253 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 1 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 3 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 0 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 14 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl4096x2 2 32 0 none (c,=32; +mx8+shl4096x2 11 32 0 none (c,=32; +mx8+shl4096x2 4 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 9 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 7 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 12 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 8 32 0 none (c,=32; +mx8+shl4096x2 5 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 15 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 10 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 18 32 0 none (c,=32; +mx8+shl4096x2 22 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x2 13 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 24 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 6 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 20 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 26 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 23 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 19 32 0 none (c,=32; +mx8+shl4096x2 21 32 0 none (c,=32; +mx8+shl4096x2 16 32 0 none (c,=32; +mx8+shl4096x2 35 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 29 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 17 32 0 none (c,=32; +mx8+shl4096x2 31 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 30 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 32 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 27 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 34 32 0 none (c,=32; +mx8+shl4096x2 25 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 43 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 33 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 28 32 0 none (c,=28;(b)=4; +mx8+shl4096x2 36 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 38 32 0 none (c,=32; +mx8+shl4096x2 41 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 40 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x2 44 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 37 32 0 none (c,=32; +mx8+shl4096x2 39 32 0 none (c,=32; +mx8+shl4096x2 42 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 46 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 47 32 0 none (c,=32; +mx8+shl4096x2 45 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 49 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 51 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x2 48 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 54 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 55 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 57 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 59 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 53 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 50 32 0 none (c,=32; +mx8+shl4096x2 60 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 52 32 0 none (c,=32; +mx8+shl4096x2 66 32 0 none (c,=27;(a)=3;(b)=2; +mx8+shl4096x2 56 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 62 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 73 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 58 32 0 none (c,=32; +mx8+shl4096x2 67 32 0 none (c,=32; +mx8+shl4096x2 70 32 0 none (c,=32; +mx8+shl4096x2 65 32 0 none (c,=32; +mx8+shl4096x2 64 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 81 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 69 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 61 32 0 none (c,=32; +mx8+shl4096x2 68 32 0 none (c,=32; +mx8+shl4096x2 80 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 72 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 74 32 0 none (c,=32; +mx8+shl4096x2 71 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 77 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 76 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 83 32 0 none (c,=32; +mx8+shl4096x2 78 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 79 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 86 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 82 32 0 none (c,=32; +mx8+shl4096x2 87 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 85 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 89 32 0 none (c,=32; +mx8+shl4096x2 75 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 84 32 0 none (c,=32; +mx8+shl4096x2 88 32 0 none (c,=32; +mx8+shl4096x2 91 32 0 none (c,=32; +mx8+shl4096x2 90 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 95 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 94 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 93 32 0 none (c,=32; +mx8+shl4096x2 92 32 0 none (c,=32; +mx8+shl4096x2 98 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 96 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 99 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 100 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 97 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 105 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 102 32 0 none (c,=32; +mx8+shl4096x2 101 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 103 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 104 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 107 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 110 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 106 32 0 none (c,=32; +mx8+shl4096x2 108 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 113 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 114 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 109 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 118 32 0 none (c,=32; +mx8+shl4096x2 112 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 123 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 115 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 127 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 111 32 0 none (c,=32; +mx8+shl4096x2 126 32 0 none (c,=32; +mx8+shl4096x2 120 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 116 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 122 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 119 32 0 none (c,=32; +mx8+shl4096x2 125 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 128 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 130 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 117 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 133 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 121 32 0 none (c,=32; +mx8+shl4096x2 134 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 131 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 129 32 0 none (c,=32; +mx8+shl4096x2 135 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 139 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 137 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 132 32 0 none (c,=32; +mx8+shl4096x2 136 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 138 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 124 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 141 32 0 none (c,=32; +mx8+shl4096x2 140 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 142 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 145 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 143 32 0 none (c,=29;(a)=3; +mx8+shl4096x2 144 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 150 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 154 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x2 147 32 0 none (c,=32; +mx8+shl4096x2 146 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 149 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 148 32 0 none (c,=32; +mx8+shl4096x2 151 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 153 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 155 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x2 161 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 169 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 164 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 158 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 159 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 152 32 0 none (c,=32; +mx8+shl4096x2 156 32 0 none (c,=32; +mx8+shl4096x2 163 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 157 32 0 none (c,=32; +mx8+shl4096x2 166 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 170 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 162 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 167 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 176 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 171 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 179 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 175 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 160 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 172 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 165 32 0 none (c,=32; +mx8+shl4096x2 174 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 178 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 180 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 168 32 0 none (c,=32; +mx8+shl4096x2 177 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 173 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 182 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 181 32 0 none (c,=32; +mx8+shl4096x2 184 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 188 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 185 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 186 32 0 none (c,=32; +mx8+shl4096x2 183 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 191 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 190 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 189 32 0 none (c,=32; +mx8+shl4096x2 192 32 0 none (c,=32; +mx8+shl4096x2 198 32 0 none (c,=29;(a)=3; +mx8+shl4096x2 194 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 197 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 196 32 0 none (c,=32; +mx8+shl4096x2 193 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 195 32 0 none (c,=32; +mx8+shl4096x2 203 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 199 32 0 none (c,=32; +mx8+shl4096x2 201 32 0 none (c,=32; +mx8+shl4096x2 209 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 200 32 0 none (c,=32; +mx8+shl4096x2 210 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl4096x2 202 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 207 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 206 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 204 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 212 32 0 none (c,=28;(b)=3;(a)=1; +mx8+shl4096x2 208 32 0 none (c,=32; +mx8+shl4096x2 205 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 214 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 211 32 0 none (c,=32; +mx8+shl4096x2 219 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 220 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x2 213 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 215 32 0 none (c,=32; +mx8+shl4096x2 230 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 222 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 223 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 225 32 0 none (c,=29;(a)=3; +mx8+shl4096x2 217 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 228 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 221 32 0 none (c,=32; +mx8+shl4096x2 216 32 0 none (c,=32; +mx8+shl4096x2 224 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x2 218 32 0 none (c,=29;(a)=3; +mx8+shl4096x2 226 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 233 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 229 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 227 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 232 32 0 none (c,=32; +mx8+shl4096x2 231 32 0 none (c,=32; +mx8+shl4096x2 236 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 237 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 234 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 238 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 239 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 235 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 240 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 243 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 245 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 242 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 241 32 0 none (c,=29;(b)=3; +mx8+shl4096x2 247 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 244 32 0 none (c,=32; +mx8+shl4096x2 253 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 246 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 248 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 255 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 249 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 254 32 0 none (c,=32; +mx8+shl4096x2 250 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 252 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 251 32 0 none (c,=32; +DONE 2026-10-08T10:10:01Z rows=2816 diff --git a/docs/analysis/class-v6/logs/census-none.tsv b/docs/analysis/class-v6/logs/census-none.tsv new file mode 100644 index 000000000..590f5b1fe --- /dev/null +++ b/docs/analysis/class-v6/logs/census-none.tsv @@ -0,0 +1,2817 @@ +mx8+sh256x27 0 1 1 0 +mx8+sh256x27 2 1 1 0 +mx8+sh256x27 5 1 1 0 +mx8+sh256x27 3 1 1 0 +mx8+sh256x27 1 1 1 0 +mx8+sh256x27 4 1 1 0 +mx8+sh256x27 8 1 1 0 +mx8+sh256x27 9 1 1 0 +mx8+sh256x27 7 1 1 0 +mx8+sh256x27 6 1 1 0 +mx8+sh256x27 12 1 1 0 +mx8+sh256x27 10 1 1 0 +mx8+sh256x27 14 1 1 0 +mx8+sh256x27 23 1 1 0 +mx8+sh256x27 13 1 1 0 +mx8+sh256x27 21 1 1 0 +mx8+sh256x27 24 1 1 0 +mx8+sh256x27 19 1 1 0 +mx8+sh256x27 26 1 1 0 +mx8+sh256x27 15 1 1 0 +mx8+sh256x27 11 1 1 0 +mx8+sh256x27 28 1 1 0 +mx8+sh256x27 22 1 1 0 +mx8+sh256x27 20 1 1 0 +mx8+sh256x27 17 1 1 0 +mx8+sh256x27 16 1 1 0 +mx8+sh256x27 18 1 1 0 +mx8+sh256x27 25 1 1 0 +mx8+sh256x27 27 1 1 0 +mx8+sh256x27 32 1 1 0 +mx8+sh256x27 29 1 1 0 +mx8+sh256x27 30 1 1 0 +mx8+sh256x27 37 1 1 0 +mx8+sh256x27 36 1 1 0 +mx8+sh256x27 34 1 1 0 +mx8+sh256x27 39 1 1 0 +mx8+sh256x27 33 1 1 0 +mx8+sh256x27 38 1 1 0 +mx8+sh256x27 35 1 1 0 +mx8+sh256x27 31 1 1 0 +mx8+sh256x27 42 1 1 0 +mx8+sh256x27 40 1 1 0 +mx8+sh256x27 41 2 1 1 (a)=1; +mx8+sh256x27 47 1 1 0 +mx8+sh256x27 44 1 1 0 +mx8+sh256x27 45 1 1 0 +mx8+sh256x27 48 1 1 0 +mx8+sh256x27 43 1 1 0 +mx8+sh256x27 46 1 1 0 +mx8+sh256x27 50 1 1 0 +mx8+sh256x27 49 1 1 0 +mx8+sh256x27 51 1 1 0 +mx8+sh256x27 53 1 1 0 +mx8+sh256x27 52 1 1 0 +mx8+sh256x27 58 1 1 0 +mx8+sh256x27 54 1 1 0 +mx8+sh256x27 55 1 1 0 +mx8+sh256x27 57 1 1 0 +mx8+sh256x27 56 1 1 0 +mx8+sh256x27 63 1 1 0 +mx8+sh256x27 61 2 1 1 (a)=1; +mx8+sh256x27 62 1 1 0 +mx8+sh256x27 69 1 1 0 +mx8+sh256x27 64 1 1 0 +mx8+sh256x27 67 1 1 0 +mx8+sh256x27 65 1 1 0 +mx8+sh256x27 60 2 1 1 (b)=1; +mx8+sh256x27 68 1 1 0 +mx8+sh256x27 59 1 1 0 +mx8+sh256x27 70 1 1 0 +mx8+sh256x27 66 1 1 0 +mx8+sh256x27 71 1 1 0 +mx8+sh256x27 73 1 1 0 +mx8+sh256x27 74 1 1 0 +mx8+sh256x27 72 1 1 0 +mx8+sh256x27 78 1 1 0 +mx8+sh256x27 76 1 1 0 +mx8+sh256x27 77 1 1 0 +mx8+sh256x27 75 1 1 0 +mx8+sh256x27 80 1 1 0 +mx8+sh256x27 84 2 1 1 (a)=1; +mx8+sh256x27 81 1 1 0 +mx8+sh256x27 82 1 1 0 +mx8+sh256x27 83 2 1 1 (b)=1; +mx8+sh256x27 79 1 1 0 +mx8+sh256x27 85 1 1 0 +mx8+sh256x27 86 1 1 0 +mx8+sh256x27 88 1 1 0 +mx8+sh256x27 87 1 1 0 +mx8+sh256x27 89 2 1 1 (a)=1; +mx8+sh256x27 90 1 1 0 +mx8+sh256x27 92 1 1 0 +mx8+sh256x27 93 1 1 0 +mx8+sh256x27 91 1 1 0 +mx8+sh256x27 96 1 1 0 +mx8+sh256x27 95 1 1 0 +mx8+sh256x27 99 1 1 0 +mx8+sh256x27 98 1 1 0 +mx8+sh256x27 94 1 1 0 +mx8+sh256x27 97 1 1 0 +mx8+sh256x27 100 1 1 0 +mx8+sh256x27 101 1 1 0 +mx8+sh256x27 103 1 1 0 +mx8+sh256x27 102 1 1 0 +mx8+sh256x27 106 1 1 0 +mx8+sh256x27 110 1 1 0 +mx8+sh256x27 108 1 1 0 +mx8+sh256x27 104 1 1 0 +mx8+sh256x27 109 1 1 0 +mx8+sh256x27 107 1 1 0 +mx8+sh256x27 105 1 1 0 +mx8+sh256x27 111 1 1 0 +mx8+sh256x27 116 1 1 0 +mx8+sh256x27 115 1 1 0 +mx8+sh256x27 118 1 1 0 +mx8+sh256x27 112 1 1 0 +mx8+sh256x27 117 1 1 0 +mx8+sh256x27 113 1 1 0 +mx8+sh256x27 114 1 1 0 +mx8+sh256x27 121 1 1 0 +mx8+sh256x27 120 1 1 0 +mx8+sh256x27 119 1 1 0 +mx8+sh256x27 126 1 1 0 +mx8+sh256x27 123 1 1 0 +mx8+sh256x27 124 1 1 0 +mx8+sh256x27 122 1 1 0 +mx8+sh256x27 125 1 1 0 +mx8+sh256x27 129 1 1 0 +mx8+sh256x27 128 1 1 0 +mx8+sh256x27 127 1 1 0 +mx8+sh256x27 131 1 1 0 +mx8+sh256x27 130 1 1 0 +mx8+sh256x27 132 1 1 0 +mx8+sh256x27 133 1 1 0 +mx8+sh256x27 134 1 1 0 +mx8+sh256x27 138 1 1 0 +mx8+sh256x27 135 1 1 0 +mx8+sh256x27 136 1 1 0 +mx8+sh256x27 141 1 1 0 +mx8+sh256x27 140 1 1 0 +mx8+sh256x27 144 1 1 0 +mx8+sh256x27 137 1 1 0 +mx8+sh256x27 139 1 1 0 +mx8+sh256x27 145 1 1 0 +mx8+sh256x27 142 1 1 0 +mx8+sh256x27 146 1 1 0 +mx8+sh256x27 149 1 1 0 +mx8+sh256x27 147 1 1 0 +mx8+sh256x27 143 1 1 0 +mx8+sh256x27 150 1 1 0 +mx8+sh256x27 155 1 1 0 +mx8+sh256x27 148 1 1 0 +mx8+sh256x27 156 1 1 0 +mx8+sh256x27 152 2 1 1 (b)=1; +mx8+sh256x27 153 2 1 1 (a)=1; +mx8+sh256x27 154 1 1 0 +mx8+sh256x27 157 1 1 0 +mx8+sh256x27 159 1 1 0 +mx8+sh256x27 158 1 1 0 +mx8+sh256x27 160 1 1 0 +mx8+sh256x27 151 1 1 0 +mx8+sh256x27 164 1 1 0 +mx8+sh256x27 162 1 1 0 +mx8+sh256x27 161 1 1 0 +mx8+sh256x27 172 1 1 0 +mx8+sh256x27 166 1 1 0 +mx8+sh256x27 171 1 1 0 +mx8+sh256x27 169 1 1 0 +mx8+sh256x27 174 1 1 0 +mx8+sh256x27 167 1 1 0 +mx8+sh256x27 163 1 1 0 +mx8+sh256x27 178 1 1 0 +mx8+sh256x27 176 1 1 0 +mx8+sh256x27 170 1 1 0 +mx8+sh256x27 173 1 1 0 +mx8+sh256x27 165 1 1 0 +mx8+sh256x27 168 1 1 0 +mx8+sh256x27 177 1 1 0 +mx8+sh256x27 175 1 1 0 +mx8+sh256x27 181 1 1 0 +mx8+sh256x27 179 1 1 0 +mx8+sh256x27 180 1 1 0 +mx8+sh256x27 184 1 1 0 +mx8+sh256x27 185 1 1 0 +mx8+sh256x27 182 1 1 0 +mx8+sh256x27 186 1 1 0 +mx8+sh256x27 183 1 1 0 +mx8+sh256x27 188 1 1 0 +mx8+sh256x27 187 1 1 0 +mx8+sh256x27 190 1 1 0 +mx8+sh256x27 189 1 1 0 +mx8+sh256x27 192 1 1 0 +mx8+sh256x27 194 1 1 0 +mx8+sh256x27 191 1 1 0 +mx8+sh256x27 197 1 1 0 +mx8+sh256x27 195 1 1 0 +mx8+sh256x27 196 1 1 0 +mx8+sh256x27 193 2 1 1 (c)=1; +mx8+sh256x27 203 1 1 0 +mx8+sh256x27 200 1 1 0 +mx8+sh256x27 198 1 1 0 +mx8+sh256x27 202 1 1 0 +mx8+sh256x27 201 1 1 0 +mx8+sh256x27 199 1 1 0 +mx8+sh256x27 205 1 1 0 +mx8+sh256x27 206 1 1 0 +mx8+sh256x27 204 1 1 0 +mx8+sh256x27 209 1 1 0 +mx8+sh256x27 207 1 1 0 +mx8+sh256x27 208 1 1 0 +mx8+sh256x27 210 1 1 0 +mx8+sh256x27 212 1 1 0 +mx8+sh256x27 211 1 1 0 +mx8+sh256x27 215 1 1 0 +mx8+sh256x27 216 1 1 0 +mx8+sh256x27 213 1 1 0 +mx8+sh256x27 214 1 1 0 +mx8+sh256x27 217 1 1 0 +mx8+sh256x27 218 1 1 0 +mx8+sh256x27 222 2 1 1 (a)=1; +mx8+sh256x27 219 1 1 0 +mx8+sh256x27 220 1 1 0 +mx8+sh256x27 221 1 1 0 +mx8+sh256x27 225 1 1 0 +mx8+sh256x27 223 1 1 0 +mx8+sh256x27 224 1 1 0 +mx8+sh256x27 227 1 1 0 +mx8+sh256x27 226 1 1 0 +mx8+sh256x27 229 1 1 0 +mx8+sh256x27 230 1 1 0 +mx8+sh256x27 228 1 1 0 +mx8+sh256x27 233 1 1 0 +mx8+sh256x27 231 1 1 0 +mx8+sh256x27 232 1 1 0 +mx8+sh256x27 234 1 1 0 +mx8+sh256x27 235 1 1 0 +mx8+sh256x27 236 1 1 0 +mx8+sh256x27 239 1 1 0 +mx8+sh256x27 241 1 1 0 +mx8+sh256x27 237 1 1 0 +mx8+sh256x27 238 1 1 0 +mx8+sh256x27 240 1 1 0 +mx8+sh256x27 242 1 1 0 +mx8+sh256x27 247 1 1 0 +mx8+sh256x27 246 1 1 0 +mx8+sh256x27 244 1 1 0 +mx8+sh256x27 245 2 1 1 (b)=1; +mx8+sh256x27 243 1 1 0 +mx8+sh256x27 249 2 1 1 (b)=1; +mx8+sh256x27 248 1 1 0 +mx8+sh256x27 252 1 1 0 +mx8+sh256x27 250 1 1 0 +mx8+sh256x27 251 1 1 0 +mx8+sh256x27 253 1 1 0 +mx8+sh256x27 254 1 1 0 +mx8+sh256x27 255 1 1 0 +mx8+shl256x27 14 1 1 0 +mx8+shl256x27 41 5 1 4 (c,=2;(c)=1;(a)=1; +mx8+shl256x27 25 7 1 6 (c,=4;(c)=1;(b)=1; +mx8+shl256x27 4 12 1 11 (c,=8;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 34 6 1 5 (c,=4;(c)=1; +mx8+shl256x27 26 12 1 11 (c,=10;(c)=1; +mx8+shl256x27 16 17 1 16 (c,=14;(c)=1;(a)=1; +mx8+shl256x27 18 22 1 21 (c,=19;(c)=2; +mx8+shl256x27 53 3 1 2 (c,=1;(c)=1; +mx8+shl256x27 52 6 1 5 (c,=4;(c)=1; +mx8+shl256x27 11 15 1 14 (c,=11;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 19 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 17 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 36 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 12 32 0 none (c,=24;(c)=6;(b)=1;(a)=1; +mx8+shl256x27 23 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 1 32 0 none (c,=31;(c)=1; +mx8+shl256x27 24 32 0 none (c,=29;(c)=3; +mx8+shl256x27 33 26 1 25 (c,=22;(c)=2;(b)=1; +mx8+shl256x27 15 32 0 none (c,=26;(c)=5;(b)=1; +mx8+shl256x27 48 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 46 32 0 none (c,=25;(c)=4;(b)=2;(a)=1; +mx8+shl256x27 21 32 0 none (c,=26;(c)=2;(b)=2;(a)=2; +mx8+shl256x27 43 32 0 none (c,=23;(c)=5;(b)=2;(a)=2; +mx8+shl256x27 6 32 0 none (c,=26;(b)=3;(c)=2;(a)=1; +mx8+shl256x27 28 32 0 none (c,=21;(c)=5;(b)=4;(a)=2; +mx8+shl256x27 32 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 30 32 0 none (c,=27;(c)=5; +mx8+shl256x27 7 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 40 32 0 none (c,=26;(c)=6; +mx8+shl256x27 8 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl256x27 39 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x27 42 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 13 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 38 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x27 44 29 1 28 (c,=21;(b)=5;(c)=2; +mx8+shl256x27 50 32 0 none (c,=25;(c)=4;(a)=2;(b)=1; +mx8+shl256x27 20 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 58 5 1 4 (c,=4; +mx8+shl256x27 56 14 1 13 (c,=10;(b)=2;(a)=1; +mx8+shl256x27 5 32 0 none (c,=30;(c)=2; +mx8+shl256x27 47 32 0 none (c,=31;(a)=1; +mx8+shl256x27 22 32 0 none (c,=29;(c)=3; +mx8+shl256x27 65 8 1 7 (c,=4;(c)=2;(a)=1; +mx8+shl256x27 2 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x27 61 13 1 12 (c,=9;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 10 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 37 28 1 27 (c,=24;(c)=2;(b)=1; +mx8+shl256x27 35 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 29 27 1 26 (c,=23;(c)=3; +mx8+shl256x27 31 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl256x27 9 32 0 none (c,=29;(c)=3; +mx8+shl256x27 27 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 89 3 1 2 (c)=1;(a)=1; +mx8+shl256x27 49 32 0 none (c,=27;(c)=5; +mx8+shl256x27 51 32 0 none (c,=26;(c)=5;(a)=1; +mx8+shl256x27 45 32 0 none (c,=31;(a)=1; +mx8+shl256x27 0 32 0 none (c,=31;(c)=1; +mx8+shl256x27 3 32 0 none (c,=28;(c)=2;(a)=2; +mx8+shl256x27 73 8 1 7 (c,=6;(c)=1; +mx8+shl256x27 86 12 1 11 (c,=8;(c)=2;(a)=1; +mx8+shl256x27 59 20 1 19 (c,=15;(c)=3;(b)=1; +mx8+shl256x27 98 8 1 7 (c,=6;(c)=1; +mx8+shl256x27 60 22 1 21 (c,=17;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 54 31 1 30 (c,=25;(c)=3;(b)=2; +mx8+shl256x27 70 18 1 17 (c,=14;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 67 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x27 81 27 1 26 (c,=20;(b)=3;(c)=2;(a)=1; +mx8+shl256x27 63 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 68 32 0 none (c,=26;(c)=3;(b)=3; +mx8+shl256x27 84 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x27 64 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 57 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 72 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 76 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 55 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x27 71 32 0 none (c,=26;(c)=3;(b)=3; +mx8+shl256x27 77 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 75 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 94 19 1 18 (c,=17;(c)=1; +mx8+shl256x27 69 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 116 1 1 0 +mx8+shl256x27 93 32 0 none (c,=30;(c)=2; +mx8+shl256x27 91 32 0 none (c,=25;(c)=3;(b)=2;(a)=2; +mx8+shl256x27 88 32 0 none (c,=25;(c)=4;(b)=2;(a)=1; +mx8+shl256x27 85 28 1 27 (c,=24;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 95 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 80 28 1 27 (c,=22;(c)=4;(b)=1; +mx8+shl256x27 66 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 78 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 62 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 87 32 0 none (c,=31;(c)=1; +mx8+shl256x27 79 32 0 none (c,=30;(c)=2; +mx8+shl256x27 90 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x27 99 22 1 21 (c,=18;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 110 20 1 19 (c,=18;(c)=1; +mx8+shl256x27 92 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 74 32 0 none (c,=29;(c)=3; +mx8+shl256x27 105 32 0 none (c,=26;(c)=3;(b)=2;(a)=1; +mx8+shl256x27 101 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x27 82 30 1 29 (c,=26;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 107 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x27 100 32 1 31 (c,=24;(c)=6;(a)=1; +mx8+shl256x27 103 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x27 97 32 0 none (c,=26;(c)=3;(b)=3; +mx8+shl256x27 83 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 96 32 0 none (c,=30;(c)=2; +mx8+shl256x27 117 22 1 21 (c,=17;(b)=2;(c)=1;(a)=1; +mx8+shl256x27 130 15 1 14 (c,=12;(c)=2; +mx8+shl256x27 109 28 1 27 (c,=22;(c)=3;(b)=1;(a)=1; +mx8+shl256x27 112 24 1 23 (c,=21;(c)=2; +mx8+shl256x27 133 27 1 26 (c,=20;(c)=4;(b)=2; +mx8+shl256x27 124 17 1 16 (c,=14;(c)=1;(b)=1; +mx8+shl256x27 104 32 0 none (c,=30;(c)=2; +mx8+shl256x27 127 11 1 10 (c,=10; +mx8+shl256x27 108 32 0 none (c,=30;(c)=2; +mx8+shl256x27 141 8 1 7 (c,=4;(c)=3; +mx8+shl256x27 106 32 0 none (c,=31;(b)=1; +mx8+shl256x27 118 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 120 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 102 32 0 none (c,=30;(c)=2; +mx8+shl256x27 129 17 1 16 (c,=15;(c)=1; +mx8+shl256x27 121 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x27 155 6 1 5 (c,=4;(c)=1; +mx8+shl256x27 119 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl256x27 154 11 1 10 (c,=8;(c)=2; +mx8+shl256x27 115 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 111 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl256x27 132 29 1 28 (c,=22;(c)=3;(b)=2;(a)=1; +mx8+shl256x27 131 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x27 125 26 1 25 (c,=21;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 113 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 126 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 136 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 122 32 0 none (c,=23;(c)=5;(b)=2;(a)=2; +mx8+shl256x27 176 2 1 1 (c,=1; +mx8+shl256x27 137 23 1 22 (c,=22; +mx8+shl256x27 135 32 0 none (c,=26;(c)=6; +mx8+shl256x27 128 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 173 12 1 11 (c,=10;(c)=1; +mx8+shl256x27 139 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 123 32 0 none (c,=31;(c)=1; +mx8+shl256x27 138 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 144 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 114 32 0 none (c,=30;(c)=2; +mx8+shl256x27 134 32 0 none (c,=30;(c)=2; +mx8+shl256x27 147 32 0 none (c,=26;(c)=4;(b)=2; +mx8+shl256x27 143 32 0 none (c,=30;(b)=2; +mx8+shl256x27 148 32 0 none (c,=26;(c)=3;(a)=2;(b)=1; +mx8+shl256x27 140 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 146 32 0 none (c,=30;(a)=2; +mx8+shl256x27 142 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 153 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 149 32 0 none (c,=31;(c)=1; +mx8+shl256x27 150 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 145 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 185 4 1 3 (c,=3; +mx8+shl256x27 163 26 1 25 (c,=19;(c)=3;(b)=2;(a)=1; +mx8+shl256x27 156 32 0 none (c,=26;(c)=2;(b)=2;(a)=2; +mx8+shl256x27 191 3 1 2 (c,=2; +mx8+shl256x27 152 32 0 none (c,=25;(c)=4;(b)=3; +mx8+shl256x27 151 32 0 none (c,=26;(b)=3;(c)=2;(a)=1; +mx8+shl256x27 160 32 0 none (c,=24;(c)=5;(b)=3; +mx8+shl256x27 159 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x27 157 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 164 32 0 none (c,=27;(c)=3;(b)=1;(a)=1; +mx8+shl256x27 162 32 0 none (c,=27;(b)=3;(c)=2; +mx8+shl256x27 168 24 1 23 (c,=21;(c)=1;(b)=1; +mx8+shl256x27 190 10 1 9 (c,=8;(c)=1; +mx8+shl256x27 167 32 0 none (c,=30;(c)=2; +mx8+shl256x27 165 32 0 none (c,=32; +mx8+shl256x27 161 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 169 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x27 158 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 200 11 1 10 (c,=8;(c)=1;(a)=1; +mx8+shl256x27 166 32 0 none (c,=27;(c)=5; +mx8+shl256x27 170 32 0 none (c,=27;(c)=2;(a)=2;(b)=1; +mx8+shl256x27 180 32 0 none (c,=26;(c)=3;(b)=2;(a)=1; +mx8+shl256x27 179 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl256x27 177 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x27 171 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 174 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x27 218 5 1 4 (c,=4; +mx8+shl256x27 187 27 1 26 (c,=21;(c)=3;(b)=1;(a)=1; +mx8+shl256x27 181 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 172 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 178 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 184 24 1 23 (c,=19;(c)=2;(a)=2; +mx8+shl256x27 182 32 0 none (c,=27;(c)=3;(a)=2; +mx8+shl256x27 189 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 175 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x27 186 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x27 209 21 1 20 (c,=18;(c)=2; +mx8+shl256x27 203 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 222 14 1 13 (c,=10;(c)=2;(a)=1; +mx8+shl256x27 197 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 230 6 1 5 (c,=5; +mx8+shl256x27 192 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x27 193 32 0 none (c,=28;(c)=4; +mx8+shl256x27 199 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x27 198 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 219 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 195 28 1 27 (c,=24;(b)=2;(c)=1; +mx8+shl256x27 234 7 1 6 (c,=4;(c)=2; +mx8+shl256x27 188 32 0 none (c,=29;(a)=3; +mx8+shl256x27 183 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x27 194 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 229 16 1 15 (c,=14;(b)=1; +mx8+shl256x27 204 32 0 none (c,=30;(c)=2; +mx8+shl256x27 215 23 1 22 (c,=21;(a)=1; +mx8+shl256x27 196 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 210 32 0 none (c,=30;(c)=2; +mx8+shl256x27 208 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x27 206 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 217 23 1 22 (c,=20;(c)=2; +mx8+shl256x27 212 32 1 31 (c,=27;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 250 2 1 1 (c,=1; +mx8+shl256x27 216 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 201 32 1 31 (c,=27;(c)=4; +mx8+shl256x27 207 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x27 202 32 0 none (c,=30;(c)=2; +mx8+shl256x27 231 16 1 15 (c,=14;(b)=1; +mx8+shl256x27 205 32 0 none (c,=25;(c)=6;(a)=1; +mx8+shl256x27 220 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x27 211 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x27 235 19 1 18 (c,=16;(c)=2; +mx8+shl576x12 7 1 1 0 +mx8+shl256x27 225 32 0 none (c,=27;(c)=5; +mx8+shl576x12 6 2 1 1 (c,=1; +mx8+shl256x27 213 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 214 32 0 none (c,=28;(c)=4; +mx8+shl576x12 2 6 1 5 (c,=4;(b)=1; +mx8+shl256x27 243 16 1 15 (c,=13;(b)=2; +mx8+shl576x12 12 4 1 3 (c,=3; +mx8+shl576x12 18 3 1 2 (c,=2; +mx8+shl256x27 233 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl576x12 11 7 1 6 (c,=5;(b)=1; +mx8+shl256x27 238 32 0 none (c,=25;(b)=4;(a)=2;(c)=1; +mx8+shl576x12 16 3 1 2 (c,=2; +mx8+shl256x27 226 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x27 237 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x27 245 32 0 none (c,=24;(c)=4;(b)=2;(a)=2; +mx8+shl256x27 241 32 0 none (c,=26;(c)=4;(a)=2; +mx8+shl256x27 224 32 0 none (c,=29;(c)=3; +mx8+shl256x27 227 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl576x12 9 8 1 7 (c,=7; +mx8+shl576x12 4 12 1 11 (c,=9;(b)=1;(a)=1; +mx8+shl256x27 239 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl576x12 1 10 1 9 (c,=9; +mx8+shl576x12 30 1 1 0 +mx8+shl576x12 24 3 1 2 (c,=2; +mx8+shl256x27 228 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x27 223 32 0 none (c,=30;(b)=2; +mx8+shl576x12 23 7 1 6 (c,=5;(a)=1; +mx8+shl256x27 249 32 0 none (c,=23;(c)=7;(b)=1;(a)=1; +mx8+shl576x12 5 12 1 11 (c,=11; +mx8+shl576x12 34 2 1 1 (c,=1; +mx8+shl256x27 221 32 0 none (c,=30;(c)=2; +mx8+shl576x12 25 6 1 5 (c,=3;(c)=1;(b)=1; +mx8+shl256x27 236 32 0 none (c,=29;(c)=3; +mx8+shl576x12 33 3 1 2 (c,=2; +mx8+shl576x12 22 8 1 7 (c,=7; +mx8+shl576x12 27 6 1 5 (c,=5; +mx8+shl576x12 38 2 1 1 (c,=1; +mx8+shl576x12 20 10 1 9 (c,=9; +mx8+shl576x12 15 11 1 10 (c,=10; +mx8+shl576x12 48 2 1 1 (c,=1; +mx8+shl256x27 240 31 1 30 (c,=27;(c)=3; +mx8+shl256x27 247 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 251 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 232 32 0 none (c,=31;(c)=1; +mx8+shl576x12 39 5 1 4 (c,=4; +mx8+shl256x27 244 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl576x12 28 7 1 6 (c,=6; +mx8+shl256x27 252 32 0 none (c,=30;(c)=2; +mx8+shl256x27 248 32 0 none (c,=31;(c)=1; +mx8+shl576x12 47 4 1 3 (c,=3; +mx8+shl576x12 60 2 1 1 (b)=1; +mx8+shl256x27 254 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x27 246 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl576x12 42 5 1 4 (c,=4; +mx8+shl576x12 51 4 1 3 (c,=3; +mx8+shl576x12 53 3 1 2 (c,=2; +mx8+shl576x12 55 3 1 2 (c,=2; +mx8+shl576x12 0 22 1 21 (c,=21; +mx8+shl576x12 44 6 1 5 (c,=4;(b)=1; +mx8+shl576x12 52 4 1 3 (c,=3; +mx8+shl256x27 242 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl576x12 17 18 1 17 (c,=16;(b)=1; +mx8+shl256x27 253 32 0 none (c,=30;(c)=2; +mx8+shl576x12 31 12 1 11 (c,=10;(b)=1; +mx8+shl576x12 10 20 1 19 (c,=19; +mx8+shl256x27 255 32 0 none (c,=30;(c)=2; +mx8+shl576x12 21 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl576x12 41 14 1 13 (c,=12;(a)=1; +mx8+shl576x12 62 4 1 3 (c,=2;(a)=1; +mx8+shl576x12 56 10 1 9 (c,=6;(b)=2;(a)=1; +mx8+shl576x12 68 3 1 2 (c,=2; +mx8+shl576x12 69 2 1 1 (c,=1; +mx8+shl576x12 26 14 1 13 (c,=12;(c)=1; +mx8+shl576x12 72 2 1 1 (c,=1; +mx8+shl576x12 71 3 1 2 (c,=2; +mx8+shl576x12 76 2 1 1 (c,=1; +mx8+shl576x12 14 23 1 22 (c,=20;(c)=1;(b)=1; +mx8+shl576x12 37 13 1 12 (c,=12; +mx8+shl576x12 50 11 1 10 (c,=9;(a)=1; +mx8+shl576x12 8 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl576x12 3 32 0 none (c,=30;(a)=2; +mx8+shl576x12 78 5 1 4 (c,=4; +mx8+shl576x12 43 13 1 12 (c,=12; +mx8+shl576x12 93 2 1 1 (c,=1; +mx8+shl576x12 89 3 1 2 (c,=1;(a)=1; +mx8+shl576x12 95 1 1 0 +mx8+shl576x12 83 5 1 4 (c,=3;(b)=1; +mx8+shl576x12 13 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl576x12 49 17 1 16 (c,=16; +mx8+shl576x12 46 19 1 18 (c,=14;(b)=2;(c)=1;(a)=1; +mx8+shl576x12 88 7 1 6 (c,=6; +mx8+shl576x12 61 13 1 12 (c,=10;(b)=1;(a)=1; +mx8+shl576x12 90 4 1 3 (c,=2;(b)=1; +mx8+shl576x12 36 20 1 19 (c,=18;(b)=1; +mx8+shl576x12 29 19 1 18 (c,=18; +mx8+shl576x12 87 8 1 7 (c,=7; +mx8+shl576x12 80 9 1 8 (c,=7;(c)=1; +mx8+shl576x12 91 6 1 5 (c,=5; +mx8+shl576x12 107 1 1 0 +mx8+shl576x12 45 17 1 16 (c,=15;(c)=1; +mx8+shl576x12 19 32 0 none (c,=30;(b)=2; +mx8+shl576x12 84 11 1 10 (c,=9;(a)=1; +mx8+shl576x12 67 15 1 14 (c,=14; +mx8+shl576x12 75 12 1 11 (c,=10;(b)=1; +mx8+shl576x12 94 9 1 8 (c,=7;(c)=1; +mx8+shl576x12 101 7 1 6 (c,=6; +mx8+shl576x12 64 20 1 19 (c,=17;(c)=1;(b)=1; +mx8+shl576x12 100 5 1 4 (c,=4; +mx8+shl576x12 102 8 1 7 (c,=7; +mx8+shl576x12 32 27 1 26 (c,=25;(b)=1; +mx8+shl576x12 54 22 1 21 (c,=20;(b)=1; +mx8+shl576x12 113 4 1 3 (c,=3; +mx8+shl576x12 103 7 1 6 (c,=5;(b)=1; +mx8+shl576x12 57 14 1 13 (c,=13; +mx8+shl576x12 59 23 1 22 (c,=21;(b)=1; +mx8+shl576x12 118 3 1 2 (c,=2; +mx8+shl576x12 66 18 1 17 (c,=16;(a)=1; +mx8+shl576x12 65 20 1 19 (c,=18;(a)=1; +mx8+shl576x12 98 9 1 8 (c,=8; +mx8+shl576x12 74 20 1 19 (c,=18;(c)=1; +mx8+shl576x12 70 21 1 20 (c,=18;(b)=1;(a)=1; +mx8+shl576x12 97 12 1 11 (c,=9;(b)=2; +mx8+shl576x12 130 1 1 0 +mx8+shl576x12 111 8 1 7 (c,=6;(a)=1; +mx8+shl576x12 92 14 1 13 (c,=13; +mx8+shl576x12 105 15 1 14 (c,=13;(b)=1; +mx8+shl576x12 126 4 1 3 (c,=2;(a)=1; +mx8+shl576x12 117 10 1 9 (c,=7;(b)=1;(a)=1; +mx8+shl576x12 35 30 1 29 (c,=27;(b)=2; +mx8+shl576x12 40 32 0 none (c,=32; +mx8+shl576x12 120 6 1 5 (c,=5; +mx8+shl576x12 125 6 1 5 (c,=4;(a)=1; +mx8+shl576x12 127 4 1 3 (c,=3; +mx8+shl576x12 81 26 1 25 (c,=20;(b)=3;(c)=1;(a)=1; +mx8+shl576x12 108 10 1 9 (c,=9; +mx8+shl576x12 121 9 1 8 (c,=8; +mx8+shl576x12 142 3 1 2 (c,=2; +mx8+shl576x12 149 1 1 0 +mx8+shl576x12 145 2 1 1 (c,=1; +mx8+shl576x12 77 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 140 5 1 4 (c,=4; +mx8+shl576x12 99 18 1 17 (c,=16;(a)=1; +mx8+shl576x12 136 7 1 6 (c,=4;(c)=1;(a)=1; +mx8+shl576x12 110 14 1 13 (c,=13; +mx8+shl576x12 122 12 1 11 (c,=10;(b)=1; +mx8+shl576x12 82 25 1 24 (c,=21;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 85 25 1 24 (c,=21;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 123 12 1 11 (c,=10;(c)=1; +mx8+shl576x12 135 7 1 6 (c,=5;(c)=1; +mx8+shl576x12 138 7 1 6 (c,=4;(c)=2; +mx8+shl576x12 104 17 1 16 (c,=16; +mx8+shl576x12 114 16 1 15 (c,=14;(c)=1; +mx8+shl576x12 128 10 1 9 (c,=9; +mx8+shl576x12 148 6 1 5 (c,=5; +mx8+shl576x12 139 9 1 8 (c,=8; +mx8+shl576x12 106 20 1 19 (c,=19; +mx8+shl576x12 58 30 1 29 (c,=27;(c)=1;(b)=1; +mx8+shl576x12 73 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl576x12 124 16 1 15 (c,=14;(b)=1; +mx8+shl576x12 141 8 1 7 (c,=7; +mx8+shl576x12 63 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl576x12 159 4 1 3 (c,=3; +mx8+shl576x12 164 3 1 2 (c,=1;(b)=1; +mx8+shl576x12 133 16 1 15 (c,=14;(b)=1; +mx8+shl576x12 79 32 0 none (c,=30;(c)=2; +mx8+shl576x12 134 12 1 11 (c,=11; +mx8+shl576x12 170 3 1 2 (c,=2; +mx8+shl576x12 155 6 1 5 (c,=5; +mx8+shl576x12 86 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl576x12 151 11 1 10 (c,=9;(b)=1; +mx8+shl576x12 158 8 1 7 (c,=7; +mx8+shl576x12 144 11 1 10 (c,=10; +mx8+shl576x12 176 2 1 1 (c)=1; +mx8+shl576x12 131 16 1 15 (c,=15; +mx8+shl576x12 152 13 1 12 (c,=11;(b)=1; +mx8+shl576x12 180 5 1 4 (c,=4; +mx8+shl576x12 157 10 1 9 (c,=9; +mx8+shl576x12 96 32 0 none (c,=29;(c)=3; +mx8+shl576x12 150 14 1 13 (c,=13; +mx8+shl576x12 179 6 1 5 (c,=3;(c)=1;(b)=1; +mx8+shl576x12 185 4 1 3 (c,=3; +mx8+shl576x12 116 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl576x12 129 22 1 21 (c,=20;(a)=1; +mx8+shl576x12 109 28 1 27 (c,=25;(b)=1;(a)=1; +mx8+shl576x12 112 32 0 none (c,=32; +mx8+shl576x12 169 11 1 10 (c,=9;(a)=1; +mx8+shl576x12 165 10 1 9 (c,=9; +mx8+shl576x12 163 16 1 15 (c,=13;(b)=1;(a)=1; +mx8+shl576x12 192 6 1 5 (c,=5; +mx8+shl576x12 119 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl576x12 167 14 1 13 (c,=13; +mx8+shl576x12 115 30 1 29 (c,=28;(b)=1; +mx8+shl576x12 198 2 1 1 (c,=1; +mx8+shl576x12 156 19 1 18 (c,=14;(b)=2;(c)=1;(a)=1; +mx8+shl576x12 200 3 1 2 (c,=2; +mx8+shl576x12 205 1 1 0 +mx8+shl576x12 194 6 1 5 (c,=5; +mx8+shl576x12 177 14 1 13 (c,=13; +mx8+shl576x12 160 17 1 16 (c,=15;(b)=1; +mx8+shl576x12 184 17 1 16 (c,=14;(a)=2; +mx8+shl576x12 209 1 1 0 +mx8+shl576x12 146 32 0 none (c,=29;(a)=2;(c)=1; +mx8+shl576x12 171 18 1 17 (c,=17; +mx8+shl576x12 193 10 1 9 (c,=9; +mx8+shl576x12 132 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl576x12 195 14 1 13 (c,=12;(b)=1; +mx8+shl576x12 143 29 1 28 (c,=26;(b)=2; +mx8+shl576x12 186 17 1 16 (c,=13;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 218 2 1 1 (c,=1; +mx8+shl576x12 182 21 1 20 (c,=18;(a)=2; +mx8+shl576x12 187 16 1 15 (c,=13;(b)=1;(a)=1; +mx8+shl576x12 183 18 1 17 (c,=16;(b)=1; +mx8+shl576x12 137 32 0 none (c,=31;(c)=1; +mx8+shl576x12 172 21 1 20 (c,=18;(c)=1;(a)=1; +mx8+shl576x12 162 25 1 24 (c,=22;(b)=2; +mx8+shl576x12 223 3 1 2 (c,=2; +mx8+shl576x12 168 23 1 22 (c,=21;(b)=1; +mx8+shl576x12 153 29 1 28 (c,=27;(a)=1; +mx8+shl576x12 147 32 0 none (c,=30;(b)=2; +mx8+shl576x12 214 8 1 7 (c,=7; +mx8+shl576x12 196 15 1 14 (c,=13;(c)=1; +mx8+shl576x12 216 12 1 11 (c,=10;(a)=1; +mx8+shl576x12 231 2 1 1 (c,=1; +mx8+shl576x12 161 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl576x12 174 28 1 27 (c,=23;(b)=2;(c)=1;(a)=1; +mx8+shl576x12 234 2 1 1 (c,=1; +mx8+shl576x12 222 10 1 9 (c,=8;(a)=1; +mx8+shl576x12 230 6 1 5 (c,=4;(c)=1; +mx8+shl576x12 175 32 0 none (c,=31;(a)=1; +mx8+shl576x12 154 31 1 30 (c,=30; +mx8+shl576x12 213 15 1 14 (c,=11;(c)=1;(b)=1;(a)=1; +mx8+shl576x12 221 11 1 10 (c,=10; +mx8+shl576x12 240 2 1 1 (c,=1; +mx8+shl576x12 211 17 1 16 (c,=15;(b)=1; +mx8+shl576x12 197 21 1 20 (c,=17;(c)=2;(a)=1; +mx8+shl576x12 166 32 0 none (c,=32; +mx8+shl576x12 219 16 1 15 (c,=14;(a)=1; +mx8+shl576x12 181 32 0 none (c,=31;(b)=1; +mx8+shl576x12 238 5 1 4 (c,=4; +mx8+shl576x12 178 32 0 none (c,=31;(b)=1; +mx8+shl576x12 188 32 0 none (c,=27;(a)=3;(c)=2; +mx8+shl576x12 173 32 1 31 (c,=29;(b)=1;(a)=1; +mx8+shl576x12 239 7 1 6 (c,=5;(b)=1; +mx8+shl576x12 232 9 1 8 (c,=8; +mx8+shl576x12 207 18 1 17 (c,=17; +mx8+shl576x12 236 8 1 7 (c,=7; +mx8+shl576x12 250 2 1 1 (c,=1; +mx8+shl1152x6 0 1 1 0 +mx8+shl576x12 242 6 1 5 (c,=5; +mx8+shl576x12 227 13 1 12 (c,=12; +mx8+shl576x12 233 11 1 10 (c,=10; +mx8+shl576x12 217 23 1 22 (c,=21;(c)=1; +mx8+shl1152x6 6 2 1 1 (c,=1; +mx8+shl576x12 254 6 1 5 (c,=4;(b)=1; +mx8+shl576x12 190 32 0 none (c,=32; +mx8+shl576x12 189 32 0 none (c,=31;(b)=1; +mx8+shl576x12 199 30 1 29 (c,=26;(c)=1;(b)=1;(a)=1; +mx8+shl1152x6 3 5 1 4 (c,=3;(a)=1; +mx8+shl576x12 201 32 0 none (c,=31;(c)=1; +mx8+shl576x12 246 9 1 8 (c,=8; +mx8+shl576x12 244 12 1 11 (c,=11; +mx8+shl576x12 235 15 1 14 (c,=14; +mx8+shl576x12 229 16 1 15 (c,=14;(b)=1; +mx8+shl576x12 220 24 1 23 (c,=21;(c)=1;(a)=1; +mx8+shl1152x6 14 1 1 0 +mx8+shl576x12 204 32 0 none (c,=32; +mx8+shl576x12 202 32 0 none (c,=30;(c)=2; +mx8+shl576x12 206 32 0 none (c,=31;(a)=1; +mx8+shl576x12 243 16 1 15 (c,=13;(b)=2; +mx8+shl1152x6 12 4 1 3 (c,=3; +mx8+shl1152x6 25 1 1 0 +mx8+shl1152x6 22 1 1 0 +mx8+shl1152x6 17 3 1 2 (c,=2; +mx8+shl576x12 247 12 1 11 (c,=11; +mx8+shl1152x6 16 3 1 2 (c,=2; +mx8+shl576x12 215 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl1152x6 1 7 1 6 (c,=6; +mx8+shl1152x6 19 3 1 2 (c,=2; +mx8+shl576x12 191 32 0 none (c,=31;(c)=1; +mx8+shl576x12 212 32 1 31 (c,=29;(b)=1;(a)=1; +mx8+shl1152x6 11 7 1 6 (c,=5;(b)=1; +mx8+shl1152x6 7 7 1 6 (c,=6; +mx8+shl576x12 226 32 0 none (c,=30;(b)=2; +mx8+shl576x12 210 32 0 none (c,=32; +mx8+shl576x12 251 12 1 11 (c,=11; +mx8+shl1152x6 24 3 1 2 (c,=2; +mx8+shl576x12 228 23 1 22 (c,=21;(c)=1; +mx8+shl1152x6 36 2 1 1 (c,=1; +mx8+shl1152x6 4 12 1 11 (c,=9;(b)=1;(a)=1; +mx8+shl576x12 208 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 34 2 1 1 (c,=1; +mx8+shl1152x6 10 9 1 8 (c,=8; +mx8+shl576x12 237 28 1 27 (c,=26;(b)=1; +mx8+shl1152x6 41 5 1 4 (c,=3;(a)=1; +mx8+shl1152x6 23 7 1 6 (c,=5;(a)=1; +mx8+shl576x12 248 20 1 19 (c,=19; +mx8+shl576x12 203 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl576x12 255 18 1 17 (c,=17; +mx8+shl1152x6 15 11 1 10 (c,=10; +mx8+shl1152x6 38 7 1 6 (c,=5;(b)=1; +mx8+shl576x12 224 32 0 none (c,=30;(c)=2; +mx8+shl1152x6 47 4 1 3 (c,=3; +mx8+shl1152x6 37 5 1 4 (c,=4; +mx8+shl1152x6 51 4 1 3 (c,=3; +mx8+shl1152x6 20 10 1 9 (c,=9; +mx8+shl1152x6 28 7 1 6 (c,=6; +mx8+shl1152x6 50 3 1 2 (c,=2; +mx8+shl1152x6 13 12 1 11 (c,=11; +mx8+shl1152x6 55 1 1 0 +mx8+shl1152x6 32 8 1 7 (c,=6;(b)=1; +mx8+shl1152x6 57 1 1 0 +mx8+shl1152x6 60 2 1 1 (b)=1; +mx8+shl1152x6 42 5 1 4 (c,=4; +mx8+shl1152x6 26 12 1 11 (c,=10;(c)=1; +mx8+shl576x12 241 28 1 27 (c,=25;(a)=2; +mx8+shl576x12 225 32 0 none (c,=31;(c)=1; +mx8+shl1152x6 52 4 1 3 (c,=3; +mx8+shl1152x6 46 8 1 7 (c,=6;(b)=1; +mx8+shl1152x6 31 12 1 11 (c,=10;(b)=1; +mx8+shl1152x6 62 4 1 3 (c,=2;(a)=1; +mx8+shl576x12 245 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl1152x6 72 2 1 1 (c,=1; +mx8+shl1152x6 21 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl1152x6 8 24 1 23 (c,=22;(a)=1; +mx8+shl1152x6 65 4 1 3 (c,=3; +mx8+shl1152x6 58 7 1 6 (c,=6; +mx8+shl1152x6 76 2 1 1 (c,=1; +mx8+shl1152x6 5 23 1 22 (c,=22; +mx8+shl1152x6 33 16 1 15 (c,=15; +mx8+shl1152x6 43 13 1 12 (c,=12; +mx8+shl1152x6 18 19 1 18 (c,=18; +mx8+shl1152x6 2 28 1 27 (c,=25;(b)=2; +mx8+shl576x12 252 32 0 none (c,=32; +mx8+shl1152x6 71 8 1 7 (c,=6;(b)=1; +mx8+shl1152x6 75 5 1 4 (c,=4; +mx8+shl1152x6 9 24 1 23 (c,=23; +mx8+shl1152x6 59 10 1 9 (c,=9; +mx8+shl1152x6 73 8 1 7 (c,=7; +mx8+shl1152x6 78 5 1 4 (c,=4; +mx8+shl1152x6 40 15 1 14 (c,=14; +mx8+shl1152x6 61 13 1 12 (c,=10;(b)=1;(a)=1; +mx8+shl1152x6 90 1 1 0 +mx8+shl1152x6 80 5 1 4 (c,=4; +mx8+shl1152x6 89 3 1 2 (c,=1;(a)=1; +mx8+shl1152x6 39 19 1 18 (c,=17;(b)=1; +mx8+shl1152x6 83 5 1 4 (c,=3;(b)=1; +mx8+shl1152x6 70 11 1 10 (c,=8;(b)=1;(a)=1; +mx8+shl576x12 249 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 95 1 1 0 +mx8+shl1152x6 63 11 1 10 (c,=10; +mx8+shl1152x6 93 2 1 1 (c,=1; +mx8+shl1152x6 30 19 1 18 (c,=18; +mx8+shl1152x6 103 2 1 1 (c,=1; +mx8+shl1152x6 91 4 1 3 (c,=3; +mx8+shl576x12 253 32 1 31 (c,=31; +mx8+shl1152x6 27 24 1 23 (c,=23; +mx8+shl1152x6 97 7 1 6 (c,=4;(b)=2; +mx8+shl1152x6 82 11 1 10 (c,=8;(b)=1;(a)=1; +mx8+shl1152x6 100 5 1 4 (c,=4; +mx8+shl1152x6 56 25 1 24 (c,=20;(b)=3;(a)=1; +mx8+shl1152x6 84 11 1 10 (c,=9;(a)=1; +mx8+shl1152x6 104 3 1 2 (c,=2; +mx8+shl1152x6 67 15 1 14 (c,=14; +mx8+shl1152x6 44 29 1 28 (c,=23;(b)=5; +mx8+shl1152x6 86 12 1 11 (c,=10;(a)=1; +mx8+shl1152x6 66 16 1 15 (c,=14;(a)=1; +mx8+shl1152x6 107 5 1 4 (c,=3;(c)=1; +mx8+shl1152x6 116 1 1 0 +mx8+shl1152x6 64 20 1 19 (c,=18;(b)=1; +mx8+shl1152x6 102 8 1 7 (c,=7; +mx8+shl1152x6 88 17 1 16 (c,=14;(b)=2; +mx8+shl1152x6 98 8 1 7 (c,=7; +mx8+shl1152x6 94 9 1 8 (c,=8; +mx8+shl1152x6 118 3 1 2 (c,=2; +mx8+shl1152x6 106 7 1 6 (c,=6; +mx8+shl1152x6 85 16 1 15 (c,=14;(b)=1; +mx8+shl1152x6 68 22 1 21 (c,=19;(b)=2; +mx8+shl1152x6 29 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 130 1 1 0 +mx8+shl1152x6 128 3 1 2 (c,=2; +mx8+shl1152x6 48 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 74 20 1 19 (c,=19; +mx8+shl1152x6 126 4 1 3 (c,=2;(a)=1; +mx8+shl1152x6 125 5 1 4 (c,=3;(a)=1; +mx8+shl1152x6 133 2 1 1 (c,=1; +mx8+shl1152x6 105 15 1 14 (c,=13;(b)=1; +mx8+shl1152x6 141 1 1 0 +mx8+shl1152x6 137 2 1 1 (c,=1; +mx8+shl1152x6 108 10 1 9 (c,=9; +mx8+shl1152x6 49 29 1 28 (c,=28; +mx8+shl1152x6 113 10 1 9 (c,=8;(a)=1; +mx8+shl1152x6 122 6 1 5 (c,=5; +mx8+shl1152x6 121 6 1 5 (c,=5; +mx8+shl1152x6 35 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 127 6 1 5 (c,=5; +mx8+shl1152x6 54 22 1 21 (c,=20;(b)=1; +mx8+shl1152x6 136 4 1 3 (c,=2;(a)=1; +mx8+shl1152x6 114 10 1 9 (c,=9; +mx8+shl1152x6 96 14 1 13 (c,=13; +mx8+shl1152x6 135 4 1 3 (c,=3; +mx8+shl1152x6 146 1 1 0 +mx8+shl1152x6 45 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 142 3 1 2 (c,=2; +mx8+shl1152x6 145 2 1 1 (c,=1; +mx8+shl1152x6 110 14 1 13 (c,=13; +mx8+shl1152x6 99 18 1 17 (c,=16;(a)=1; +mx8+shl1152x6 109 16 1 15 (c,=13;(b)=1;(a)=1; +mx8+shl1152x6 87 20 1 19 (c,=19; +mx8+shl1152x6 140 5 1 4 (c,=4; +mx8+shl1152x6 124 11 1 10 (c,=9;(b)=1; +mx8+shl1152x6 138 6 1 5 (c,=5; +mx8+shl1152x6 53 32 0 none (c,=32; +mx8+shl1152x6 115 14 1 13 (c,=12;(b)=1; +mx8+shl1152x6 148 6 1 5 (c,=5; +mx8+shl1152x6 112 17 1 16 (c,=16; +mx8+shl1152x6 163 3 1 2 (c,=2; +mx8+shl1152x6 123 12 1 11 (c,=11; +mx8+shl1152x6 158 5 1 4 (c,=4; +mx8+shl1152x6 81 30 1 29 (c,=25;(b)=3;(a)=1; +mx8+shl1152x6 153 6 1 5 (c,=4;(a)=1; +mx8+shl1152x6 77 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 144 8 1 7 (c,=7; +mx8+shl1152x6 174 2 1 1 (c,=1; +mx8+shl1152x6 176 1 1 0 +mx8+shl1152x6 69 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 151 11 1 10 (c,=9;(b)=1; +mx8+shl1152x6 155 9 1 8 (c,=7;(c)=1; +mx8+shl1152x6 111 24 1 23 (c,=20;(b)=2;(a)=1; +mx8+shl1152x6 117 22 1 21 (c,=18;(b)=2;(a)=1; +mx8+shl1152x6 79 32 0 none (c,=32; +mx8+shl1152x6 154 11 1 10 (c,=10; +mx8+shl1152x6 173 6 1 5 (c,=5; +mx8+shl1152x6 101 32 0 none (c,=29;(b)=3; +mx8+shl1152x6 150 14 1 13 (c,=13; +mx8+shl1152x6 152 13 1 12 (c,=11;(b)=1; +mx8+shl1152x6 92 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 164 11 1 10 (c,=9;(b)=1; +mx8+shl1152x6 169 11 1 10 (c,=9;(a)=1; +mx8+shl1152x6 149 13 1 12 (c,=12; +mx8+shl1152x6 131 21 1 20 (c,=20; +mx8+shl1152x6 165 10 1 9 (c,=9; +mx8+shl1152x6 170 11 1 10 (c,=10; +mx8+shl1152x6 191 3 1 2 (c,=2; +mx8+shl1152x6 156 19 1 18 (c,=15;(b)=2;(a)=1; +mx8+shl1152x6 139 20 1 19 (c,=19; +mx8+shl1152x6 180 8 1 7 (c,=7; +mx8+shl1152x6 189 4 1 3 (c,=3; +mx8+shl1152x6 129 26 1 25 (c,=24;(a)=1; +mx8+shl1152x6 161 16 1 15 (c,=14;(a)=1; +mx8+shl1152x6 192 6 1 5 (c,=5; +mx8+shl1152x6 178 12 1 11 (c,=10;(b)=1; +mx8+shl1152x6 119 29 1 28 (c,=25;(a)=2;(b)=1; +mx8+shl1152x6 200 3 1 2 (c,=2; +mx8+shl1152x6 181 10 1 9 (c,=9; +mx8+shl1152x6 168 17 1 16 (c,=15;(b)=1; +mx8+shl1152x6 205 2 1 1 (c,=1; +mx8+shl1152x6 120 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 203 4 1 3 (c,=3; +mx8+shl1152x6 209 2 1 1 (c,=1; +mx8+shl1152x6 194 8 1 7 (c,=7; +mx8+shl1152x6 199 8 1 7 (c,=7; +mx8+shl1152x6 160 21 1 20 (c,=19;(b)=1; +mx8+shl1152x6 206 4 1 3 (c,=3; +mx8+shl1152x6 132 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl1152x6 212 3 1 2 (c,=2; +mx8+shl1152x6 218 2 1 1 (c,=1; +mx8+shl1152x6 213 3 1 2 (c,=2; +mx8+shl1152x6 157 22 1 21 (c,=20;(b)=1; +mx8+shl1152x6 159 22 1 21 (c,=19;(b)=2; +mx8+shl1152x6 219 4 1 3 (c,=2;(a)=1; +mx8+shl1152x6 198 9 1 8 (c,=7;(b)=1; +mx8+shl1152x6 190 13 1 12 (c,=12; +mx8+shl1152x6 182 21 1 20 (c,=18;(a)=2; +mx8+shl1152x6 224 1 1 0 +mx8+shl1152x6 134 31 1 30 (c,=30; +mx8+shl1152x6 147 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 223 3 1 2 (c,=2; +mx8+shl1152x6 162 25 1 24 (c,=22;(b)=2; +mx8+shl1152x6 196 13 1 12 (c,=12; +mx8+shl1152x6 143 32 0 none (c,=30;(b)=2; +mx8+shl1152x6 185 24 1 23 (c,=22;(b)=1; +mx8+shl1152x6 171 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 214 10 1 9 (c,=8;(c)=1; +mx8+shl1152x6 240 2 1 1 (c,=1; +mx8+shl1152x6 172 31 1 30 (c,=28;(b)=1;(a)=1; +mx8+shl1152x6 175 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 238 5 1 4 (c,=4; +mx8+shl1152x6 179 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl1152x6 221 11 1 10 (c,=10; +mx8+shl1152x6 187 27 1 26 (c,=24;(b)=1;(a)=1; +mx8+shl1152x6 167 32 0 none (c,=32; +mx8+shl1152x6 184 24 1 23 (c,=21;(a)=2; +mx8+shl1152x6 177 32 0 none (c,=31;(a)=1; +mx8+shl1152x6 242 3 1 2 (c,=2; +mx8+shl1152x6 234 7 1 6 (c,=6; +mx8+shl1152x6 225 9 1 8 (c,=8; +mx8+shl1152x6 166 32 0 none (c,=32; +mx8+shl1152x6 211 17 1 16 (c,=15;(b)=1; +mx8+shl1152x6 197 21 1 20 (c,=19;(a)=1; +mx8+shl1152x6 243 3 1 2 (c,=2; +mx8+shl1152x6 230 10 1 9 (c,=9; +mx8+shl1152x6 250 2 1 1 (c,=1; +mx8+shl1152x6 233 11 1 10 (c,=10; +mx8+shl2304x3 2 1 1 0 +mx8+shl1152x6 195 28 1 27 (c,=25;(b)=2; +mx8+shl1152x6 228 15 1 14 (c,=14; +mx8+shl1152x6 186 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1152x6 215 18 1 17 (c,=16;(a)=1; +mx8+shl1152x6 183 32 0 none (c,=31;(b)=1; +mx8+shl1152x6 227 13 1 12 (c,=12; +mx8+shl1152x6 207 20 1 19 (c,=19; +mx8+shl1152x6 248 4 1 3 (c,=3; +mx8+shl1152x6 255 3 1 2 (c,=2; +mx8+shl1152x6 201 24 1 23 (c,=22;(c)=1; +mx8+shl1152x6 239 11 1 10 (c,=9;(b)=1; +mx8+shl2304x3 6 2 1 1 (c,=1; +mx8+shl1152x6 188 32 0 none (c,=29;(a)=3; +mx8+shl1152x6 220 21 1 20 (c,=19;(a)=1; +mx8+shl1152x6 241 13 1 12 (c,=11;(a)=1; +mx8+shl1152x6 231 16 1 15 (c,=14;(b)=1; +mx8+shl2304x3 14 1 1 0 +mx8+shl1152x6 216 21 1 20 (c,=19;(a)=1; +mx8+shl1152x6 217 23 1 22 (c,=22; +mx8+shl1152x6 253 7 1 6 (c,=6; +mx8+shl1152x6 251 8 1 7 (c,=7; +mx8+shl1152x6 222 22 1 21 (c,=20;(a)=1; +mx8+shl1152x6 229 18 1 17 (c,=16;(b)=1; +mx8+shl2304x3 17 3 1 2 (c,=2; +mx8+shl1152x6 193 32 0 none (c,=32; +mx8+shl1152x6 246 9 1 8 (c,=8; +mx8+shl1152x6 244 12 1 11 (c,=11; +mx8+shl1152x6 226 25 1 24 (c,=23;(b)=1; +mx8+shl2304x3 25 1 1 0 +mx8+shl2304x3 20 3 1 2 (c,=2; +mx8+shl1152x6 210 24 1 23 (c,=23; +mx8+shl1152x6 235 19 1 18 (c,=17;(c)=1; +mx8+shl2304x3 7 7 1 6 (c,=6; +mx8+shl1152x6 247 12 1 11 (c,=11; +mx8+shl1152x6 208 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 24 3 1 2 (c,=2; +mx8+shl1152x6 202 32 0 none (c,=32; +mx8+shl2304x3 22 4 1 3 (c,=3; +mx8+shl2304x3 34 2 1 1 (c,=1; +mx8+shl2304x3 36 2 1 1 (c,=1; +mx8+shl2304x3 10 9 1 8 (c,=8; +mx8+shl1152x6 204 32 0 none (c,=32; +mx8+shl2304x3 23 7 1 6 (c,=5;(a)=1; +mx8+shl2304x3 38 2 1 1 (c,=1; +mx8+shl2304x3 44 1 1 0 +mx8+shl2304x3 11 9 1 8 (c,=7;(b)=1; +mx8+shl2304x3 46 1 1 0 +mx8+shl2304x3 5 12 1 11 (c,=11; +mx8+shl2304x3 28 7 1 6 (c,=6; +mx8+shl2304x3 4 12 1 11 (c,=9;(b)=1;(a)=1; +mx8+shl2304x3 26 8 1 7 (c,=7; +mx8+shl2304x3 32 8 1 7 (c,=6;(b)=1; +mx8+shl2304x3 48 2 1 1 (c,=1; +mx8+shl2304x3 13 12 1 11 (c,=11; +mx8+shl2304x3 12 9 1 8 (c,=8; +mx8+shl2304x3 19 11 1 10 (c,=9;(b)=1; +mx8+shl1152x6 237 30 1 29 (c,=26;(c)=1;(b)=1;(a)=1; +mx8+shl2304x3 57 1 1 0 +mx8+shl2304x3 59 1 1 0 +mx8+shl2304x3 16 15 1 14 (c,=13;(a)=1; +mx8+shl2304x3 42 5 1 4 (c,=4; +mx8+shl2304x3 30 9 1 8 (c,=8; +mx8+shl2304x3 15 13 1 12 (c,=12; +mx8+shl1152x6 236 27 1 26 (c,=26; +mx8+shl2304x3 50 3 1 2 (c,=2; +mx8+shl2304x3 52 4 1 3 (c,=3; +mx8+shl1152x6 252 21 1 20 (c,=20; +mx8+shl2304x3 47 7 1 6 (c,=6; +mx8+shl2304x3 41 10 1 9 (c,=8;(a)=1; +mx8+shl1152x6 232 32 0 none (c,=32; +mx8+shl2304x3 62 4 1 3 (c,=2;(a)=1; +mx8+shl2304x3 58 5 1 4 (c,=4; +mx8+shl2304x3 68 3 1 2 (c,=2; +mx8+shl2304x3 72 2 1 1 (c,=1; +mx8+shl2304x3 69 2 1 1 (c,=1; +mx8+shl2304x3 18 19 1 18 (c,=18; +mx8+shl2304x3 37 13 1 12 (c,=12; +mx8+shl2304x3 60 6 1 5 (c,=3;(c)=1;(b)=1; +mx8+shl2304x3 71 3 1 2 (c,=2; +mx8+shl1152x6 254 25 1 24 (c,=23;(b)=1; +mx8+shl2304x3 3 21 1 20 (c,=19;(a)=1; +mx8+shl2304x3 39 14 1 13 (c,=12;(b)=1; +mx8+shl2304x3 1 22 1 21 (c,=21; +mx8+shl2304x3 55 10 1 9 (c,=8;(b)=1; +mx8+shl1152x6 245 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl2304x3 53 9 1 8 (c,=8; +mx8+shl2304x3 8 21 1 20 (c,=19;(a)=1; +mx8+shl2304x3 78 5 1 4 (c,=4; +mx8+shl2304x3 65 8 1 7 (c,=6;(a)=1; +mx8+shl2304x3 76 5 1 4 (c,=4; +mx8+shl1152x6 249 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 63 8 1 7 (c,=7; +mx8+shl2304x3 75 5 1 4 (c,=4; +mx8+shl2304x3 80 5 1 4 (c,=4; +mx8+shl2304x3 90 1 1 0 +mx8+shl2304x3 89 3 1 2 (c,=1;(a)=1; +mx8+shl2304x3 88 2 1 1 (c,=1; +mx8+shl2304x3 95 1 1 0 +mx8+shl2304x3 61 13 1 12 (c,=10;(b)=1;(a)=1; +mx8+shl2304x3 29 19 1 18 (c,=18; +mx8+shl2304x3 97 2 1 1 (c,=1; +mx8+shl2304x3 45 15 1 14 (c,=14; +mx8+shl2304x3 79 7 1 6 (c,=6; +mx8+shl2304x3 103 2 1 1 (c,=1; +mx8+shl2304x3 21 26 1 25 (c,=23;(b)=1;(a)=1; +mx8+shl2304x3 70 11 1 10 (c,=8;(b)=1;(a)=1; +mx8+shl2304x3 105 3 1 2 (c,=2; +mx8+shl2304x3 107 2 1 1 (c,=1; +mx8+shl2304x3 83 6 1 5 (c,=4;(b)=1; +mx8+shl2304x3 91 6 1 5 (c,=5; +mx8+shl2304x3 87 8 1 7 (c,=7; +mx8+shl2304x3 100 5 1 4 (c,=4; +mx8+shl2304x3 27 24 1 23 (c,=23; +mx8+shl2304x3 66 16 1 15 (c,=14;(a)=1; +mx8+shl2304x3 0 32 1 31 (c,=31; +mx8+shl2304x3 40 22 1 21 (c,=21; +mx8+shl2304x3 31 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2304x3 116 1 1 0 +mx8+shl2304x3 64 20 1 19 (c,=18;(b)=1; +mx8+shl2304x3 33 26 1 25 (c,=24;(b)=1; +mx8+shl2304x3 51 19 1 18 (c,=17;(a)=1; +mx8+shl2304x3 113 4 1 3 (c,=3; +mx8+shl2304x3 9 32 0 none (c,=32; +mx8+shl2304x3 84 13 1 12 (c,=11;(a)=1; +mx8+shl2304x3 54 22 1 21 (c,=20;(b)=1; +mx8+shl2304x3 56 27 1 26 (c,=22;(b)=3;(a)=1; +mx8+shl2304x3 43 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl2304x3 93 13 1 12 (c,=12; +mx8+shl2304x3 126 4 1 3 (c,=2;(a)=1; +mx8+shl2304x3 114 6 1 5 (c,=5; +mx8+shl2304x3 128 3 1 2 (c,=2; +mx8+shl2304x3 131 2 1 1 (c,=1; +mx8+shl2304x3 125 5 1 4 (c,=3;(a)=1; +mx8+shl2304x3 127 4 1 3 (c,=3; +mx8+shl2304x3 108 10 1 9 (c,=9; +mx8+shl2304x3 120 6 1 5 (c,=5; +mx8+shl2304x3 74 19 1 18 (c,=18; +mx8+shl2304x3 122 6 1 5 (c,=5; +mx8+shl2304x3 123 6 1 5 (c,=5; +mx8+shl2304x3 86 18 1 17 (c,=16;(a)=1; +mx8+shl2304x3 99 13 1 12 (c,=11;(a)=1; +mx8+shl2304x3 85 16 1 15 (c,=14;(b)=1; +mx8+shl2304x3 124 7 1 6 (c,=6; +mx8+shl2304x3 112 11 1 10 (c,=10; +mx8+shl2304x3 92 14 1 13 (c,=13; +mx8+shl2304x3 134 2 1 1 (c,=1; +mx8+shl2304x3 35 30 1 29 (c,=27;(b)=2; +mx8+shl2304x3 133 2 1 1 (c,=1; +mx8+shl2304x3 49 28 1 27 (c,=27; +mx8+shl2304x3 137 2 1 1 (c,=1; +mx8+shl2304x3 94 17 1 16 (c,=16; +mx8+shl2304x3 149 1 1 0 +mx8+shl2304x3 110 14 1 13 (c,=13; +mx8+shl2304x3 136 4 1 3 (c,=2;(a)=1; +mx8+shl2304x3 130 7 1 6 (c,=6; +mx8+shl2304x3 142 3 1 2 (c,=2; +mx8+shl2304x3 135 4 1 3 (c,=3; +mx8+shl2304x3 81 26 1 25 (c,=21;(b)=3;(a)=1; +mx8+shl2304x3 109 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl2304x3 129 10 1 9 (c,=9; +mx8+shl2304x3 77 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 138 6 1 5 (c,=5; +mx8+shl2304x3 67 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 148 6 1 5 (c,=5; +mx8+shl2304x3 141 7 1 6 (c,=6; +mx8+shl2304x3 145 8 1 7 (c,=7; +mx8+shl2304x3 163 3 1 2 (c,=2; +mx8+shl2304x3 159 4 1 3 (c,=3; +mx8+shl2304x3 102 19 1 18 (c,=18; +mx8+shl2304x3 155 6 1 5 (c,=5; +mx8+shl2304x3 73 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 162 5 1 4 (c,=4; +mx8+shl2304x3 144 8 1 7 (c,=7; +mx8+shl2304x3 174 2 1 1 (c,=1; +mx8+shl2304x3 176 1 1 0 +mx8+shl2304x3 111 24 1 23 (c,=20;(b)=2;(a)=1; +mx8+shl2304x3 164 7 1 6 (c,=5;(b)=1; +mx8+shl2304x3 158 9 1 8 (c,=8; +mx8+shl2304x3 166 10 1 9 (c,=9; +mx8+shl2304x3 82 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 156 11 1 10 (c,=8;(b)=2; +mx8+shl2304x3 184 1 1 0 +mx8+shl2304x3 157 9 1 8 (c,=8; +mx8+shl2304x3 101 32 0 none (c,=29;(b)=3; +mx8+shl2304x3 98 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 151 12 1 11 (c,=10;(b)=1; +mx8+shl2304x3 173 6 1 5 (c,=5; +mx8+shl2304x3 179 6 1 5 (c,=4;(b)=1; +mx8+shl2304x3 152 14 1 13 (c,=12;(b)=1; +mx8+shl2304x3 187 5 1 4 (c,=3;(a)=1; +mx8+shl2304x3 185 4 1 3 (c,=3; +mx8+shl2304x3 121 27 1 26 (c,=23;(b)=2;(a)=1; +mx8+shl2304x3 150 14 1 13 (c,=13; +mx8+shl2304x3 117 26 1 25 (c,=22;(b)=2;(a)=1; +mx8+shl2304x3 96 32 0 none (c,=32; +mx8+shl2304x3 169 11 1 10 (c,=9;(a)=1; +mx8+shl2304x3 118 29 1 28 (c,=26;(b)=1;(a)=1; +mx8+shl2304x3 196 3 1 2 (c,=2; +mx8+shl2304x3 178 12 1 11 (c,=10;(b)=1; +mx8+shl2304x3 192 6 1 5 (c,=5; +mx8+shl2304x3 189 4 1 3 (c,=3; +mx8+shl2304x3 205 1 1 0 +mx8+shl2304x3 119 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2304x3 115 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 198 2 1 1 (c,=1; +mx8+shl2304x3 139 20 1 19 (c,=19; +mx8+shl2304x3 181 10 1 9 (c,=9; +mx8+shl2304x3 104 32 1 31 (c,=31; +mx8+shl2304x3 172 14 1 13 (c,=12;(a)=1; +mx8+shl2304x3 177 14 1 13 (c,=13; +mx8+shl2304x3 194 6 1 5 (c,=5; +mx8+shl2304x3 132 29 1 28 (c,=25;(b)=2;(a)=1; +mx8+shl2304x3 209 1 1 0 +mx8+shl2304x3 200 4 1 3 (c,=3; +mx8+shl2304x3 146 26 1 25 (c,=24;(a)=1; +mx8+shl2304x3 190 9 1 8 (c,=8; +mx8+shl2304x3 167 20 1 19 (c,=19; +mx8+shl2304x3 206 4 1 3 (c,=3; +mx8+shl2304x3 106 32 1 31 (c,=30;(b)=1; +mx8+shl2304x3 193 10 1 9 (c,=9; +mx8+shl2304x3 212 3 1 2 (c,=2; +mx8+shl2304x3 218 2 1 1 (c,=1; +mx8+shl2304x3 160 21 1 20 (c,=19;(b)=1; +mx8+shl2304x3 168 17 1 16 (c,=15;(b)=1; +mx8+shl2304x3 224 1 1 0 +mx8+shl2304x3 143 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 140 30 1 29 (c,=28;(a)=1; +mx8+shl2304x3 213 5 1 4 (c,=4; +mx8+shl2304x3 153 29 1 28 (c,=27;(a)=1; +mx8+shl2304x3 182 21 1 20 (c,=18;(a)=2; +mx8+shl2304x3 223 3 1 2 (c,=2; +mx8+shl2304x3 221 4 1 3 (c,=3; +mx8+shl2304x3 202 9 1 8 (c,=8; +mx8+shl2304x3 197 11 1 10 (c,=10; +mx8+shl2304x3 222 6 1 5 (c,=4;(a)=1; +mx8+shl2304x3 234 2 1 1 (c,=1; +mx8+shl2304x3 147 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 230 6 1 5 (c,=5; +mx8+shl2304x3 180 25 1 24 (c,=22;(b)=1;(a)=1; +mx8+shl2304x3 154 32 0 none (c,=32; +mx8+shl2304x3 229 8 1 7 (c,=6;(b)=1; +mx8+shl2304x3 216 12 1 11 (c,=10;(a)=1; +mx8+shl2304x3 233 7 1 6 (c,=6; +mx8+shl2304x3 238 5 1 4 (c,=4; +mx8+shl2304x3 161 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 225 9 1 8 (c,=8; +mx8+shl2304x3 170 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2304x3 186 23 1 22 (c,=20;(b)=1;(a)=1; +mx8+shl2304x3 240 6 1 5 (c,=5; +mx8+shl2304x3 165 32 0 none (c,=32; +mx8+shl2304x3 171 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 175 32 0 none (c,=31;(a)=1; +mx8+shl2304x3 235 7 1 6 (c,=6; +mx8+shl2304x3 232 9 1 8 (c,=8; +mx8+shl2304x3 211 17 1 16 (c,=15;(b)=1; +mx8+shl2304x3 247 7 1 6 (c,=6; +mx8+shl2304x3 231 13 1 12 (c,=11;(b)=1; +mx8+shl2304x3 203 25 1 24 (c,=22;(b)=2; +mx8+shl256x16 5 2 1 1 (c,=1; +mx8+shl2304x3 217 20 1 19 (c,=19; +mx8+shl2304x3 246 9 1 8 (c,=8; +mx8+shl2304x3 183 32 0 none (c,=31;(b)=1; +mx8+shl2304x3 227 15 1 14 (c,=14; +mx8+shl2304x3 249 6 1 5 (c,=4;(b)=1; +mx8+shl2304x3 242 10 1 9 (c,=9; +mx8+shl2304x3 255 4 1 3 (c,=3; +mx8+shl256x16 4 12 1 11 (c,=8;(c)=1;(b)=1;(a)=1; +mx8+shl2304x3 241 13 1 12 (c,=11;(a)=1; +mx8+shl2304x3 188 32 0 none (c,=29;(a)=3; +mx8+shl256x16 14 1 1 0 +mx8+shl2304x3 207 20 1 19 (c,=19; +mx8+shl2304x3 228 20 1 19 (c,=19; +mx8+shl2304x3 220 21 1 20 (c,=19;(a)=1; +mx8+shl2304x3 253 7 1 6 (c,=6; +mx8+shl2304x3 195 30 1 29 (c,=27;(b)=2; +mx8+shl2304x3 191 28 1 27 (c,=27; +mx8+shl2304x3 210 24 1 23 (c,=23; +mx8+shl2304x3 208 27 1 26 (c,=24;(b)=2; +mx8+shl256x16 11 15 1 14 (c,=11;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 3 32 0 none (c,=28;(c)=2;(a)=2; +mx8+shl2304x3 236 18 1 17 (c,=17; +mx8+shl256x16 16 17 1 16 (c,=15;(a)=1; +mx8+shl2304x3 244 18 1 17 (c,=16;(b)=1; +mx8+shl256x16 1 32 0 none (c,=31;(c)=1; +mx8+shl256x16 7 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl2304x3 199 30 1 29 (c,=27;(b)=1;(a)=1; +mx8+shl2304x3 251 12 1 11 (c,=11; +mx8+shl256x16 6 32 0 none (c,=27;(b)=3;(c)=1;(a)=1; +mx8+shl256x16 2 28 1 27 (c,=23;(c)=2;(b)=2; +mx8+shl256x16 8 32 0 none (c,=30;(a)=2; +mx8+shl256x16 0 32 0 none (c,=32; +mx8+shl256x16 18 22 1 21 (c,=20;(c)=1; +mx8+shl256x16 26 12 1 11 (c,=11; +mx8+shl256x16 19 32 0 none (c,=30;(b)=2; +mx8+shl2304x3 201 32 0 none (c,=32; +mx8+shl256x16 12 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl2304x3 204 32 0 none (c,=32; +mx8+shl2304x3 215 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl256x16 15 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl2304x3 219 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 17 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl2304x3 214 32 0 none (c,=32; +mx8+shl256x16 41 5 1 4 (c,=2;(c)=1;(a)=1; +mx8+shl256x16 13 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 23 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 10 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 24 32 0 none (c,=29;(c)=3; +mx8+shl256x16 21 32 0 none (c,=25;(c)=3;(b)=2;(a)=2; +mx8+shl2304x3 226 31 1 30 (c,=28;(b)=2; +mx8+shl2304x3 245 24 1 23 (c,=19;(b)=2;(a)=2; +mx8+shl256x16 9 32 0 none (c,=30;(c)=2; +mx8+shl256x16 20 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 22 32 0 none (c,=30;(c)=2; +mx8+shl256x16 36 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl2304x3 243 32 0 none (c,=30;(b)=2; +mx8+shl256x16 25 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 56 14 1 13 (c,=10;(b)=2;(a)=1; +mx8+shl256x16 30 30 1 29 (c,=28;(c)=1; +mx8+shl256x16 32 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 28 32 0 none (c,=24;(b)=4;(c)=2;(a)=2; +mx8+shl256x16 27 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl2304x3 239 32 0 none (c,=31;(b)=1; +mx8+shl256x16 31 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl2304x3 237 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 61 13 1 12 (c,=10;(b)=1;(a)=1; +mx8+shl256x16 50 32 0 none (c,=26;(c)=3;(a)=2;(b)=1; +mx8+shl256x16 38 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x16 42 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 51 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x16 33 26 1 25 (c,=22;(c)=2;(b)=1; +mx8+shl256x16 66 6 1 5 (c,=5; +mx8+shl256x16 48 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 39 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x16 40 32 0 none (c,=29;(c)=3; +mx8+shl256x16 44 32 0 none (c,=26;(b)=5;(c)=1; +mx8+shl256x16 29 27 1 26 (c,=24;(c)=2; +mx8+shl256x16 43 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl256x16 53 32 0 none (c,=30;(c)=2; +mx8+shl256x16 73 8 1 7 (c,=7; +mx8+shl256x16 34 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 37 28 1 27 (c,=25;(c)=1;(b)=1; +mx8+shl2304x3 254 25 1 24 (c,=23;(b)=1; +mx8+shl256x16 46 32 0 none (c,=25;(c)=4;(b)=2;(a)=1; +mx8+shl256x16 70 11 1 10 (c,=7;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 49 32 0 none (c,=28;(c)=4; +mx8+shl256x16 64 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 54 31 1 30 (c,=27;(b)=2;(c)=1; +mx8+shl256x16 35 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 45 32 0 none (c,=31;(a)=1; +mx8+shl256x16 65 32 0 none (c,=26;(c)=3;(b)=2;(a)=1; +mx8+shl2304x3 250 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 47 32 0 none (c,=31;(a)=1; +mx8+shl256x16 58 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x16 63 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 55 32 0 none (c,=27;(b)=3;(c)=2; +mx8+shl256x16 59 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x16 52 32 1 31 (c,=28;(c)=2;(a)=1; +mx8+shl256x16 86 12 1 11 (c,=8;(c)=2;(a)=1; +mx8+shl256x16 57 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x16 60 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 67 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2304x3 252 32 0 none (c,=32; +mx8+shl2304x3 248 32 1 31 (c,=31; +mx8+shl256x16 72 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 62 32 0 none (c,=31;(a)=1; +mx8+shl256x16 68 32 0 none (c,=27;(b)=3;(c)=2; +mx8+shl256x16 100 9 1 8 (c,=7;(c)=1; +mx8+shl256x16 74 19 1 18 (c,=18; +mx8+shl256x16 89 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 77 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 116 1 1 0 +mx8+shl256x16 69 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 75 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x16 106 6 1 5 (c,=5; +mx8+shl256x16 71 32 0 none (c,=26;(c)=3;(b)=3; +mx8+shl256x16 81 32 0 none (c,=26;(b)=4;(c)=1;(a)=1; +mx8+shl256x16 84 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x16 98 32 0 none (c,=27;(c)=3;(b)=2; +mx8+shl256x16 76 32 0 none (c,=31;(b)=1; +mx8+shl256x16 94 19 1 18 (c,=17;(c)=1; +mx8+shl256x16 80 28 1 27 (c,=23;(c)=3;(b)=1; +mx8+shl256x16 88 32 0 none (c,=25;(c)=4;(b)=2;(a)=1; +mx8+shl256x16 78 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 91 32 0 none (c,=25;(c)=3;(b)=2;(a)=2; +mx8+shl256x16 85 32 0 none (c,=27;(c)=3;(b)=1;(a)=1; +mx8+shl256x16 79 32 0 none (c,=31;(c)=1; +mx8+shl256x16 101 21 1 20 (c,=17;(b)=2;(c)=1; +mx8+shl256x16 92 32 0 none (c,=31;(b)=1; +mx8+shl256x16 87 32 0 none (c,=31;(c)=1; +mx8+shl256x16 95 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 82 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 90 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 93 32 0 none (c,=32; +mx8+shl256x16 99 22 1 21 (c,=18;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 141 1 1 0 +mx8+shl256x16 107 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 83 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 127 11 1 10 (c,=10; +mx8+shl256x16 110 20 1 19 (c,=18;(c)=1; +mx8+shl256x16 105 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl256x16 130 15 1 14 (c,=13;(c)=1; +mx8+shl256x16 97 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x16 103 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 117 22 1 21 (c,=17;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 96 32 0 none (c,=31;(c)=1; +mx8+shl256x16 109 28 1 27 (c,=24;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 102 32 0 none (c,=29;(c)=3; +mx8+shl256x16 112 32 0 none (c,=30;(c)=2; +mx8+shl256x16 121 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 108 32 0 none (c,=30;(c)=2; +mx8+shl256x16 115 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 118 32 0 none (c,=26;(c)=4;(b)=1;(a)=1; +mx8+shl256x16 104 32 0 none (c,=30;(c)=2; +mx8+shl256x16 133 27 1 26 (c,=21;(c)=3;(b)=2; +mx8+shl256x16 129 17 1 16 (c,=15;(c)=1; +mx8+shl256x16 134 16 1 15 (c,=14;(c)=1; +mx8+shl256x16 120 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 122 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl256x16 159 4 1 3 (c,=3; +mx8+shl256x16 125 26 1 25 (c,=21;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 154 11 1 10 (c,=9;(c)=1; +mx8+shl256x16 111 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl256x16 131 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 155 6 1 5 (c,=4;(c)=1; +mx8+shl256x16 119 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl256x16 132 29 1 28 (c,=24;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 126 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 113 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 114 32 0 none (c,=30;(c)=2; +mx8+shl256x16 158 12 1 11 (c,=10;(c)=1; +mx8+shl256x16 128 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 176 2 1 1 (c,=1; +mx8+shl256x16 123 32 0 none (c,=31;(c)=1; +mx8+shl256x16 124 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 135 32 0 none (c,=27;(c)=5; +mx8+shl256x16 139 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 138 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 147 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 144 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 150 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x16 137 32 0 none (c,=32; +mx8+shl256x16 136 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 145 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x16 185 4 1 3 (c,=3; +mx8+shl256x16 143 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 140 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 156 25 1 24 (c,=18;(c)=2;(b)=2;(a)=2; +mx8+shl256x16 142 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 146 32 0 none (c,=30;(a)=2; +mx8+shl256x16 149 32 0 none (c,=31;(c)=1; +mx8+shl256x16 148 32 0 none (c,=27;(c)=2;(a)=2;(b)=1; +mx8+shl256x16 191 3 1 2 (c,=2; +mx8+shl256x16 173 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 186 17 1 16 (c,=14;(b)=1;(a)=1; +mx8+shl256x16 151 32 0 none (c,=27;(b)=3;(c)=1;(a)=1; +mx8+shl256x16 168 24 1 23 (c,=22;(b)=1; +mx8+shl256x16 169 17 1 16 (c,=15;(a)=1; +mx8+shl256x16 190 10 1 9 (c,=8;(c)=1; +mx8+shl256x16 157 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 152 32 0 none (c,=25;(c)=4;(b)=3; +mx8+shl256x16 153 32 0 none (c,=28;(c)=3;(a)=1; +mx8+shl256x16 160 32 0 none (c,=25;(c)=4;(b)=3; +mx8+shl256x16 161 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 163 26 1 25 (c,=19;(c)=3;(b)=2;(a)=1; +mx8+shl256x16 172 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 167 32 0 none (c,=31;(c)=1; +mx8+shl256x16 166 32 0 none (c,=27;(c)=5; +mx8+shl256x16 194 10 1 9 (c,=9; +mx8+shl256x16 179 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl256x16 162 32 0 none (c,=28;(b)=3;(c)=1; +mx8+shl256x16 164 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 184 24 1 23 (c,=19;(c)=2;(a)=2; +mx8+shl256x16 187 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 200 11 1 10 (c,=9;(a)=1; +mx8+shl256x16 181 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 170 32 0 none (c,=26;(c)=3;(a)=2;(b)=1; +mx8+shl256x16 171 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 180 32 0 none (c,=26;(c)=3;(b)=2;(a)=1; +mx8+shl256x16 175 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 165 32 0 none (c,=32; +mx8+shl256x16 178 32 0 none (c,=28;(c)=3;(b)=1; +mx8+shl256x16 177 32 0 none (c,=27;(c)=4;(a)=1; +mx8+shl256x16 182 32 0 none (c,=28;(c)=2;(a)=2; +mx8+shl256x16 174 32 0 none (c,=28;(b)=2;(c)=1;(a)=1; +mx8+shl256x16 203 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 189 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 183 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 197 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 192 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 230 6 1 5 (c,=5; +mx8+shl256x16 222 14 1 13 (c,=10;(c)=2;(a)=1; +mx8+shl256x16 234 7 1 6 (c,=5;(c)=1; +mx8+shl256x16 219 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 188 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl256x16 195 30 1 29 (c,=26;(b)=2;(c)=1; +mx8+shl256x16 198 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x16 229 16 1 15 (c,=14;(b)=1; +mx8+shl256x16 205 32 0 none (c,=25;(c)=6;(a)=1; +mx8+shl256x16 199 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl256x16 196 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 193 32 0 none (c,=30;(c)=2; +mx8+shl256x16 212 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 204 32 0 none (c,=30;(c)=2; +mx8+shl256x16 209 32 0 none (c,=31;(c)=1; +mx8+shl256x16 208 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl256x16 210 32 0 none (c,=30;(c)=2; +mx8+shl256x16 235 19 1 18 (c,=16;(c)=2; +mx8+shl256x16 201 32 1 31 (c,=27;(c)=4; +mx8+shl256x16 207 32 0 none (c,=27;(c)=4;(b)=1; +mx8+shl256x16 206 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl256x16 250 2 1 1 (c,=1; +mx8+shl256x16 217 23 1 22 (c,=22; +mx8+shl256x16 225 26 1 25 (c,=23;(c)=2; +mx8+shl256x16 216 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl256x16 211 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 218 32 0 none (c,=27;(c)=3;(a)=2; +mx8+shl256x16 214 32 0 none (c,=30;(c)=2; +mx8+shl512x8 3 5 1 4 (c,=3;(a)=1; +mx8+shl256x16 215 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 2 1 1 0 +mx8+shl512x8 6 2 1 1 (c,=1; +mx8+shl512x8 7 1 1 0 +mx8+shl256x16 213 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl256x16 231 16 1 15 (c,=14;(b)=1; +mx8+shl256x16 202 32 0 none (c,=30;(c)=2; +mx8+shl256x16 220 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl512x8 14 1 1 0 +mx8+shl256x16 238 32 0 none (c,=24;(b)=4;(c)=2;(a)=2; +mx8+shl256x16 227 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 1 10 1 9 (c,=8;(c)=1; +mx8+shl256x16 221 32 0 none (c,=32; +mx8+shl256x16 245 32 0 none (c,=26;(c)=2;(b)=2;(a)=2; +mx8+shl256x16 224 32 0 none (c,=28;(c)=4; +mx8+shl256x16 226 32 0 none (c,=28;(c)=2;(b)=2; +mx8+shl256x16 243 16 1 15 (c,=13;(b)=2; +mx8+shl512x8 9 8 1 7 (c,=7; +mx8+shl512x8 4 12 1 11 (c,=9;(b)=1;(a)=1; +mx8+shl512x8 12 4 1 3 (c,=3; +mx8+shl256x16 228 32 0 none (c,=31;(a)=1; +mx8+shl512x8 20 3 1 2 (c,=2; +mx8+shl256x16 239 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 232 32 0 none (c,=30;(c)=2; +mx8+shl256x16 241 32 0 none (c,=27;(c)=3;(a)=2; +mx8+shl512x8 30 1 1 0 +mx8+shl512x8 5 12 1 11 (c,=11; +mx8+shl512x8 25 6 1 5 (c,=4;(b)=1; +mx8+shl256x16 249 32 0 none (c,=24;(c)=6;(b)=1;(a)=1; +mx8+shl256x16 251 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 233 32 0 none (c,=27;(c)=2;(b)=2;(a)=1; +mx8+shl512x8 36 2 1 1 (c,=1; +mx8+shl256x16 244 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl512x8 24 8 1 7 (c,=7; +mx8+shl512x8 22 10 1 9 (c,=8;(c)=1; +mx8+shl256x16 248 32 0 none (c,=31;(c)=1; +mx8+shl256x16 240 31 1 30 (c,=28;(c)=2; +mx8+shl512x8 38 2 1 1 (c,=1; +mx8+shl512x8 44 1 1 0 +mx8+shl256x16 223 32 0 none (c,=30;(b)=2; +mx8+shl256x16 237 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl256x16 236 32 0 none (c,=31;(c)=1; +mx8+shl512x8 35 8 1 7 (c,=6;(b)=1; +mx8+shl512x8 41 5 1 4 (c,=3;(a)=1; +mx8+shl256x16 247 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl512x8 34 6 1 5 (c,=5; +mx8+shl512x8 48 2 1 1 (c,=1; +mx8+shl256x16 242 32 0 none (c,=29;(c)=2;(b)=1; +mx8+shl256x16 254 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl256x16 253 32 0 none (c,=30;(c)=2; +mx8+shl512x8 55 1 1 0 +mx8+shl256x16 255 32 0 none (c,=31;(c)=1; +mx8+shl512x8 17 18 1 17 (c,=16;(b)=1; +mx8+shl512x8 8 24 1 23 (c,=22;(a)=1; +mx8+shl512x8 15 13 1 12 (c,=11;(c)=1; +mx8+shl512x8 47 7 1 6 (c,=6; +mx8+shl512x8 26 12 1 11 (c,=11; +mx8+shl256x16 246 32 0 none (c,=29;(c)=2;(a)=1; +mx8+shl512x8 10 20 1 19 (c,=19; +mx8+shl512x8 31 12 1 11 (c,=10;(b)=1; +mx8+shl512x8 58 5 1 4 (c,=4; +mx8+shl512x8 28 23 1 22 (c,=17;(b)=3;(a)=2; +mx8+shl512x8 39 14 1 13 (c,=12;(b)=1; +mx8+shl512x8 60 6 1 5 (c,=4;(b)=1; +mx8+shl256x16 252 32 0 none (c,=31;(c)=1; +mx8+shl512x8 68 3 1 2 (c,=2; +mx8+shl512x8 46 13 1 12 (c,=10;(b)=1;(a)=1; +mx8+shl512x8 42 11 1 10 (c,=9;(b)=1; +mx8+shl512x8 43 13 1 12 (c,=12; +mx8+shl512x8 65 4 1 3 (c,=3; +mx8+shl512x8 59 10 1 9 (c,=8;(c)=1; +mx8+shl512x8 16 32 0 none (c,=28;(c)=2;(b)=1;(a)=1; +mx8+shl512x8 62 9 1 8 (c,=7;(a)=1; +mx8+shl512x8 51 17 1 16 (c,=15;(a)=1; +mx8+shl512x8 80 5 1 4 (c,=4; +mx8+shl512x8 57 14 1 13 (c,=13; +mx8+shl512x8 0 32 1 31 (c,=31; +mx8+shl512x8 78 5 1 4 (c,=4; +mx8+shl512x8 21 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl512x8 63 11 1 10 (c,=10; +mx8+shl512x8 73 8 1 7 (c,=7; +mx8+shl512x8 11 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 89 3 1 2 (c,=1;(a)=1; +mx8+shl512x8 40 22 1 21 (c,=21; +mx8+shl512x8 83 6 1 5 (c,=4;(b)=1; +mx8+shl512x8 18 31 1 30 (c,=30; +mx8+shl512x8 13 32 0 none (c,=31;(b)=1; +mx8+shl512x8 49 19 1 18 (c,=18; +mx8+shl512x8 27 32 0 none (c,=30;(c)=1;(a)=1; +mx8+shl512x8 37 24 1 23 (c,=22;(b)=1; +mx8+shl512x8 93 2 1 1 (c,=1; +mx8+shl512x8 33 32 0 none (c,=28;(a)=2;(c)=1;(b)=1; +mx8+shl512x8 69 14 1 13 (c,=12;(a)=1; +mx8+shl512x8 23 28 1 27 (c,=26;(a)=1; +mx8+shl512x8 29 27 1 26 (c,=26; +mx8+shl512x8 56 26 1 25 (c,=21;(b)=3;(a)=1; +mx8+shl512x8 32 32 0 none (c,=31;(b)=1; +mx8+shl512x8 52 32 0 none (c,=31;(a)=1; +mx8+shl512x8 19 32 0 none (c,=30;(b)=2; +mx8+shl512x8 99 3 1 2 (c,=2; +mx8+shl512x8 61 21 1 20 (c,=17;(b)=2;(a)=1; +mx8+shl512x8 86 12 1 11 (c,=10;(a)=1; +mx8+shl512x8 87 8 1 7 (c,=7; +mx8+shl512x8 107 2 1 1 (c,=1; +mx8+shl512x8 97 7 1 6 (c,=4;(b)=2; +mx8+shl512x8 50 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 104 3 1 2 (c,=2; +mx8+shl512x8 100 7 1 6 (c,=6; +mx8+shl512x8 70 18 1 17 (c,=15;(b)=1;(a)=1; +mx8+shl512x8 117 1 1 0 +mx8+shl512x8 105 3 1 2 (c,=2; +mx8+shl512x8 98 5 1 4 (c,=4; +mx8+shl512x8 88 17 1 16 (c,=14;(b)=2; +mx8+shl512x8 85 16 1 15 (c,=13;(c)=1;(b)=1; +mx8+shl512x8 101 7 1 6 (c,=6; +mx8+shl512x8 116 4 1 3 (c,=2;(c)=1; +mx8+shl512x8 103 7 1 6 (c,=4;(c)=1;(b)=1; +mx8+shl512x8 94 9 1 8 (c,=8; +mx8+shl512x8 53 32 0 none (c,=32; +mx8+shl512x8 106 7 1 6 (c,=6; +mx8+shl512x8 45 32 0 none (c,=31;(a)=1; +mx8+shl512x8 111 8 1 7 (c,=6;(a)=1; +mx8+shl512x8 108 8 1 7 (c,=7; +mx8+shl512x8 54 32 0 none (c,=30;(b)=2; +mx8+shl512x8 81 27 1 26 (c,=21;(b)=3;(c)=1;(a)=1; +mx8+shl512x8 118 6 1 5 (c,=5; +mx8+shl512x8 126 4 1 3 (c,=2;(a)=1; +mx8+shl512x8 131 2 1 1 (c,=1; +mx8+shl512x8 95 17 1 16 (c,=16; +mx8+shl512x8 72 26 1 25 (c,=22;(c)=2;(b)=1; +mx8+shl512x8 67 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 128 3 1 2 (c,=2; +mx8+shl512x8 64 32 1 31 (c,=30;(b)=1; +mx8+shl512x8 136 3 1 2 (c,=1;(a)=1; +mx8+shl512x8 137 2 1 1 (c,=1; +mx8+shl512x8 120 6 1 5 (c,=5; +mx8+shl512x8 71 32 0 none (c,=29;(b)=3; +mx8+shl512x8 74 29 1 28 (c,=27;(c)=1; +mx8+shl512x8 90 15 1 14 (c,=13;(b)=1; +mx8+shl512x8 114 10 1 9 (c,=9; +mx8+shl512x8 112 11 1 10 (c,=10; +mx8+shl512x8 84 27 1 26 (c,=24;(a)=2; +mx8+shl512x8 79 32 0 none (c,=32; +mx8+shl512x8 127 5 1 4 (c,=4; +mx8+shl512x8 130 7 1 6 (c,=6; +mx8+shl512x8 124 11 1 10 (c,=9;(b)=1; +mx8+shl512x8 149 1 1 0 +mx8+shl512x8 77 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 75 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 91 24 1 23 (c,=20;(a)=2;(b)=1; +mx8+shl512x8 125 8 1 7 (c,=6;(a)=1; +mx8+shl512x8 66 32 0 none (c,=31;(a)=1; +mx8+shl512x8 146 6 1 5 (c,=4;(a)=1; +mx8+shl512x8 153 3 1 2 (c,=1;(a)=1; +mx8+shl512x8 82 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl512x8 148 7 1 6 (c,=6; +mx8+shl512x8 159 4 1 3 (c,=3; +mx8+shl512x8 163 3 1 2 (c,=2; +mx8+shl512x8 139 9 1 8 (c,=8; +mx8+shl512x8 110 16 1 15 (c,=15; +mx8+shl512x8 162 5 1 4 (c,=4; +mx8+shl512x8 144 8 1 7 (c,=7; +mx8+shl512x8 157 9 1 8 (c,=8; +mx8+shl512x8 145 8 1 7 (c,=7; +mx8+shl512x8 92 32 0 none (c,=31;(b)=1; +mx8+shl512x8 76 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl512x8 129 17 1 16 (c,=16; +mx8+shl512x8 151 11 1 10 (c,=9;(b)=1; +mx8+shl512x8 113 20 1 19 (c,=18;(a)=1; +mx8+shl512x8 156 11 1 10 (c,=8;(b)=2; +mx8+shl512x8 141 14 1 13 (c,=13; +mx8+shl512x8 158 10 1 9 (c,=9; +mx8+shl512x8 134 16 1 15 (c,=15; +mx8+shl512x8 115 29 1 28 (c,=27;(b)=1; +mx8+shl512x8 176 2 1 1 (c,=1; +mx8+shl512x8 178 3 1 2 (c,=2; +mx8+shl512x8 140 13 1 12 (c,=12; +mx8+shl512x8 152 13 1 12 (c,=11;(b)=1; +mx8+shl512x8 96 32 0 none (c,=31;(c)=1; +mx8+shl512x8 160 13 1 12 (c,=12; +mx8+shl512x8 119 29 1 28 (c,=25;(a)=2;(b)=1; +mx8+shl512x8 168 9 1 8 (c,=8; +mx8+shl512x8 185 1 1 0 +mx8+shl512x8 150 13 1 12 (c,=12; +mx8+shl512x8 123 22 1 21 (c,=21; +mx8+shl512x8 179 6 1 5 (c,=4;(b)=1; +mx8+shl512x8 164 11 1 10 (c,=9;(b)=1; +mx8+shl512x8 109 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl512x8 121 27 1 26 (c,=23;(b)=2;(a)=1; +mx8+shl512x8 170 11 1 10 (c,=10; +mx8+shl512x8 102 32 1 31 (c,=31; +mx8+shl512x8 161 16 1 15 (c,=14;(a)=1; +mx8+shl512x8 167 14 1 13 (c,=13; +mx8+shl512x8 184 6 1 5 (c,=4;(a)=1; +mx8+shl512x8 187 5 1 4 (c,=3;(a)=1; +mx8+shl512x8 198 2 1 1 (c,=1; +mx8+shl512x8 169 11 1 10 (c,=9;(a)=1; +mx8+shl512x8 122 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl512x8 186 6 1 5 (c,=4;(b)=1; +mx8+shl512x8 196 3 1 2 (c,=2; +mx8+shl512x8 155 19 1 18 (c,=18; +mx8+shl512x8 189 4 1 3 (c,=3; +mx8+shl512x8 192 6 1 5 (c,=5; +mx8+shl512x8 180 8 1 7 (c,=7; +mx8+shl512x8 133 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 181 10 1 9 (c,=9; +mx8+shl512x8 209 1 1 0 +mx8+shl512x8 132 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl512x8 177 14 1 13 (c,=13; +mx8+shl512x8 190 9 1 8 (c,=8; +mx8+shl512x8 200 8 1 7 (c,=6;(a)=1; +mx8+shl512x8 194 8 1 7 (c,=6;(c)=1; +mx8+shl512x8 174 21 1 20 (c,=16;(b)=2;(c)=1;(a)=1; +mx8+shl512x8 213 3 1 2 (c,=2; +mx8+shl512x8 147 32 0 none (c,=30;(b)=2; +mx8+shl512x8 143 29 1 28 (c,=26;(b)=2; +mx8+shl512x8 135 25 1 24 (c,=24; +mx8+shl512x8 171 18 1 17 (c,=17; +mx8+shl512x8 223 3 1 2 (c,=2; +mx8+shl512x8 228 3 1 2 (c,=2; +mx8+shl512x8 193 11 1 10 (c,=10; +mx8+shl512x8 142 32 1 31 (c,=29;(c)=1;(b)=1; +mx8+shl512x8 138 31 1 30 (c,=29;(a)=1; +mx8+shl512x8 206 15 1 14 (c,=14; +mx8+shl512x8 216 12 1 11 (c,=10;(a)=1; +mx8+shl512x8 205 16 1 15 (c,=14;(a)=1; +mx8+shl512x8 154 32 0 none (c,=32; +mx8+shl512x8 219 16 1 15 (c,=14;(a)=1; +mx8+shl512x8 197 16 1 15 (c,=13;(c)=1;(a)=1; +mx8+shl512x8 165 32 0 none (c,=32; +mx8+shl512x8 218 11 1 10 (c,=10; +mx8+shl512x8 172 31 1 30 (c,=28;(b)=1;(a)=1; +mx8+shl512x8 182 30 1 29 (c,=27;(a)=2; +mx8+shl512x8 207 18 1 17 (c,=17; +mx8+shl512x8 233 7 1 6 (c,=6; +mx8+shl512x8 173 32 1 31 (c,=28;(c)=1;(b)=1;(a)=1; +mx8+shl512x8 238 5 1 4 (c,=4; +mx8+shl512x8 201 24 1 23 (c,=23; +mx8+shl512x8 175 32 0 none (c,=31;(a)=1; +mx8+shl512x8 211 19 1 18 (c,=17;(b)=1; +mx8+shl512x8 227 9 1 8 (c,=8; +mx8+shl512x8 203 25 1 24 (c,=22;(b)=2; +mx8+shl512x8 221 11 1 10 (c,=10; +mx8+shl512x8 232 9 1 8 (c,=8; +mx8+shl512x8 217 19 1 18 (c,=18; +mx8+shl512x8 229 18 1 17 (c,=16;(b)=1; +mx8+shl512x8 250 2 1 1 (c,=1; +mx8+shl512x8 183 32 0 none (c,=31;(b)=1; +mx8+shl512x8 210 24 1 23 (c,=23; +mx8+shl512x8 188 32 0 none (c,=28;(a)=3;(c)=1; +mx8+shl512x8 204 32 0 none (c,=31;(c)=1; +mx8+shl512x8 247 7 1 6 (c,=6; +mx8+shl512x8 195 28 1 27 (c,=24;(b)=2;(c)=1; +mx8+shl512x8 249 6 1 5 (c,=4;(b)=1; +mx8+shl512x8 202 30 1 29 (c,=27;(c)=2; +mx8+shl512x8 254 6 1 5 (c,=4;(b)=1; +mx8+shl1024x4 6 2 1 1 (c,=1; +mx8+shl512x8 235 18 1 17 (c,=17; +mx8+shl512x8 166 32 0 none (c,=32; +mx8+shl1024x4 2 6 1 5 (c,=4;(b)=1; +mx8+shl512x8 230 19 1 18 (c,=18; +mx8+shl512x8 243 13 1 12 (c,=11;(b)=1; +mx8+shl512x8 225 20 1 19 (c,=19; +mx8+shl512x8 222 22 1 21 (c,=19;(c)=1;(a)=1; +mx8+shl1024x4 7 1 1 0 +mx8+shl512x8 220 25 1 24 (c,=23;(a)=1; +mx8+shl512x8 215 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl512x8 231 20 1 19 (c,=18;(b)=1; +mx8+shl512x8 208 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 1 7 1 6 (c,=6; +mx8+shl1024x4 18 3 1 2 (c,=2; +mx8+shl1024x4 14 1 1 0 +mx8+shl512x8 191 32 0 none (c,=31;(c)=1; +mx8+shl512x8 251 8 1 7 (c,=7; +mx8+shl512x8 212 32 1 31 (c,=29;(b)=1;(a)=1; +mx8+shl512x8 236 18 1 17 (c,=17; +mx8+shl1024x4 19 3 1 2 (c,=2; +mx8+shl512x8 234 26 1 25 (c,=24;(c)=1; +mx8+shl1024x4 4 12 1 11 (c,=9;(b)=1;(a)=1; +mx8+shl1024x4 10 9 1 8 (c,=8; +mx8+shl1024x4 30 1 1 0 +mx8+shl512x8 252 16 1 15 (c,=15; +mx8+shl512x8 199 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 12 4 1 3 (c,=3; +mx8+shl512x8 241 21 1 20 (c,=18;(a)=2; +mx8+shl512x8 224 32 0 none (c,=32; +mx8+shl512x8 244 16 1 15 (c,=14;(b)=1; +mx8+shl512x8 226 32 0 none (c,=30;(b)=2; +mx8+shl512x8 248 20 1 19 (c,=17;(c)=2; +mx8+shl1024x4 13 12 1 11 (c,=11; +mx8+shl512x8 255 15 1 14 (c,=14; +mx8+shl1024x4 36 2 1 1 (c,=1; +mx8+shl1024x4 38 2 1 1 (c,=1; +mx8+shl1024x4 44 1 1 0 +mx8+shl1024x4 23 7 1 6 (c,=5;(a)=1; +mx8+shl512x8 237 28 1 27 (c,=26;(b)=1; +mx8+shl512x8 240 25 1 24 (c,=24; +mx8+shl1024x4 11 14 1 13 (c,=11;(b)=1;(a)=1; +mx8+shl1024x4 16 9 1 8 (c,=8; +mx8+shl512x8 214 32 0 none (c,=32; +mx8+shl1024x4 22 8 1 7 (c,=7; +mx8+shl1024x4 26 8 1 7 (c,=7; +mx8+shl1024x4 46 1 1 0 +mx8+shl1024x4 48 2 1 1 (c,=1; +mx8+shl1024x4 5 12 1 11 (c,=11; +mx8+shl512x8 239 32 0 none (c,=30;(c)=1;(b)=1; +mx8+shl1024x4 24 8 1 7 (c,=7; +mx8+shl512x8 245 32 0 none (c,=27;(b)=2;(a)=2;(c)=1; +mx8+shl1024x4 55 1 1 0 +mx8+shl1024x4 15 11 1 10 (c,=10; +mx8+shl1024x4 35 8 1 7 (c,=6;(b)=1; +mx8+shl1024x4 60 2 1 1 (b)=1; +mx8+shl1024x4 50 3 1 2 (c,=2; +mx8+shl1024x4 52 4 1 3 (c,=3; +mx8+shl1024x4 37 5 1 4 (c,=4; +mx8+shl512x8 242 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 0 22 1 21 (c,=21; +mx8+shl1024x4 21 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl1024x4 62 4 1 3 (c,=2;(a)=1; +mx8+shl1024x4 8 21 1 20 (c,=19;(a)=1; +mx8+shl1024x4 51 4 1 3 (c,=3; +mx8+shl1024x4 39 14 1 13 (c,=12;(b)=1; +mx8+shl1024x4 3 32 0 none (c,=30;(a)=2; +mx8+shl512x8 246 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 58 5 1 4 (c,=4; +mx8+shl1024x4 34 11 1 10 (c,=10; +mx8+shl1024x4 65 4 1 3 (c,=3; +mx8+shl1024x4 53 9 1 8 (c,=8; +mx8+shl1024x4 76 2 1 1 (c,=1; +mx8+shl1024x4 61 9 1 8 (c,=7;(a)=1; +mx8+shl512x8 253 32 0 none (c,=32; +mx8+shl1024x4 40 15 1 14 (c,=14; +mx8+shl1024x4 72 5 1 4 (c,=4; +mx8+shl1024x4 71 4 1 3 (c,=3; +mx8+shl1024x4 79 3 1 2 (c,=2; +mx8+shl1024x4 45 15 1 14 (c,=14; +mx8+shl1024x4 75 5 1 4 (c,=4; +mx8+shl1024x4 80 5 1 4 (c,=4; +mx8+shl1024x4 33 16 1 15 (c,=14;(c)=1; +mx8+shl1024x4 9 25 1 24 (c,=24; +mx8+shl1024x4 27 24 1 23 (c,=23; +mx8+shl1024x4 83 5 1 4 (c,=3;(b)=1; +mx8+shl1024x4 90 1 1 0 +mx8+shl1024x4 28 28 1 27 (c,=22;(b)=3;(a)=2; +mx8+shl1024x4 88 2 1 1 (c,=1; +mx8+shl1024x4 95 1 1 0 +mx8+shl1024x4 17 27 1 26 (c,=25;(b)=1; +mx8+shl1024x4 63 11 1 10 (c,=10; +mx8+shl1024x4 25 27 1 26 (c,=25;(b)=1; +mx8+shl1024x4 78 9 1 8 (c,=8; +mx8+shl1024x4 47 16 1 15 (c,=15; +mx8+shl1024x4 57 14 1 13 (c,=13; +mx8+shl1024x4 97 2 1 1 (c,=1; +mx8+shl1024x4 99 3 1 2 (c,=2; +mx8+shl1024x4 68 12 1 11 (c,=10;(b)=1; +mx8+shl1024x4 82 11 1 10 (c,=8;(b)=1;(a)=1; +mx8+shl1024x4 87 8 1 7 (c,=7; +mx8+shl1024x4 105 3 1 2 (c,=2; +mx8+shl1024x4 84 11 1 10 (c,=9;(a)=1; +mx8+shl1024x4 107 2 1 1 (c,=1; +mx8+shl1024x4 91 6 1 5 (c,=5; +mx8+shl1024x4 20 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 54 22 1 21 (c,=20;(b)=1; +mx8+shl1024x4 101 7 1 6 (c,=6; +mx8+shl1024x4 29 27 1 26 (c,=26; +mx8+shl1024x4 43 30 1 29 (c,=25;(b)=2;(a)=2; +mx8+shl1024x4 66 18 1 17 (c,=16;(a)=1; +mx8+shl1024x4 31 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl1024x4 98 8 1 7 (c,=7; +mx8+shl1024x4 112 5 1 4 (c,=4; +mx8+shl1024x4 100 7 1 6 (c,=6; +mx8+shl1024x4 106 6 1 5 (c,=5; +mx8+shl1024x4 113 5 1 4 (c,=4; +mx8+shl1024x4 114 6 1 5 (c,=5; +mx8+shl1024x4 89 15 1 14 (c,=13;(a)=1; +mx8+shl1024x4 124 1 1 0 +mx8+shl1024x4 59 27 1 26 (c,=25;(b)=1; +mx8+shl1024x4 41 26 1 25 (c,=24;(a)=1; +mx8+shl1024x4 86 16 1 15 (c,=14;(a)=1; +mx8+shl1024x4 85 18 1 17 (c,=15;(b)=1;(a)=1; +mx8+shl1024x4 111 8 1 7 (c,=6;(a)=1; +mx8+shl1024x4 56 32 0 none (c,=27;(b)=4;(a)=1; +mx8+shl1024x4 81 26 1 25 (c,=21;(b)=3;(a)=1; +mx8+shl1024x4 108 8 1 7 (c,=7; +mx8+shl1024x4 93 13 1 12 (c,=12; +mx8+shl1024x4 42 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 130 1 1 0 +mx8+shl1024x4 131 2 1 1 (c,=1; +mx8+shl1024x4 67 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 104 14 1 13 (c,=13; +mx8+shl1024x4 128 3 1 2 (c,=2; +mx8+shl1024x4 133 2 1 1 (c,=1; +mx8+shl1024x4 134 2 1 1 (c,=1; +mx8+shl1024x4 32 27 1 26 (c,=25;(b)=1; +mx8+shl1024x4 127 5 1 4 (c,=4; +mx8+shl1024x4 49 28 1 27 (c,=27; +mx8+shl1024x4 74 20 1 19 (c,=19; +mx8+shl1024x4 69 30 1 29 (c,=28;(a)=1; +mx8+shl1024x4 137 2 1 1 (c,=1; +mx8+shl1024x4 145 2 1 1 (c,=1; +mx8+shl1024x4 121 9 1 8 (c,=8; +mx8+shl1024x4 135 4 1 3 (c,=3; +mx8+shl1024x4 117 15 1 14 (c,=12;(b)=1;(a)=1; +mx8+shl1024x4 77 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 64 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 110 14 1 13 (c,=13; +mx8+shl1024x4 136 8 1 7 (c,=6;(a)=1; +mx8+shl1024x4 115 14 1 13 (c,=12;(b)=1; +mx8+shl1024x4 70 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl1024x4 144 4 1 3 (c,=3; +mx8+shl1024x4 146 6 1 5 (c,=4;(a)=1; +mx8+shl1024x4 152 8 1 7 (c,=6;(b)=1; +mx8+shl1024x4 94 19 1 18 (c,=18; +mx8+shl1024x4 142 8 1 7 (c,=6;(c)=1; +mx8+shl1024x4 129 10 1 9 (c,=9; +mx8+shl1024x4 116 17 1 16 (c,=16; +mx8+shl1024x4 73 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 138 7 1 6 (c,=6; +mx8+shl1024x4 141 7 1 6 (c,=6; +mx8+shl1024x4 102 21 1 20 (c,=20; +mx8+shl1024x4 125 15 1 14 (c,=12;(b)=1;(a)=1; +mx8+shl1024x4 123 14 1 13 (c,=13; +mx8+shl1024x4 158 5 1 4 (c,=4; +mx8+shl1024x4 119 13 1 12 (c,=11;(a)=1; +mx8+shl1024x4 159 4 1 3 (c,=3; +mx8+shl1024x4 155 6 1 5 (c,=5; +mx8+shl1024x4 176 1 1 0 +mx8+shl1024x4 92 25 1 24 (c,=24; +mx8+shl1024x4 174 2 1 1 (c,=1; +mx8+shl1024x4 157 9 1 8 (c,=8; +mx8+shl1024x4 179 1 1 0 +mx8+shl1024x4 178 2 1 1 (c,=1; +mx8+shl1024x4 151 11 1 10 (c,=9;(b)=1; +mx8+shl1024x4 156 11 1 10 (c,=8;(b)=2; +mx8+shl1024x4 185 1 1 0 +mx8+shl1024x4 177 5 1 4 (c,=4; +mx8+shl1024x4 96 32 0 none (c,=32; +mx8+shl1024x4 190 1 1 0 +mx8+shl1024x4 184 2 1 1 (c,=1; +mx8+shl1024x4 173 6 1 5 (c,=5; +mx8+shl1024x4 172 7 1 6 (c,=5;(a)=1; +mx8+shl1024x4 103 30 1 29 (c,=26;(b)=2;(a)=1; +mx8+shl1024x4 166 10 1 9 (c,=9; +mx8+shl1024x4 160 13 1 12 (c,=12; +mx8+shl1024x4 180 5 1 4 (c,=4; +mx8+shl1024x4 120 21 1 20 (c,=19;(b)=1; +mx8+shl1024x4 187 5 1 4 (c,=3;(a)=1; +mx8+shl1024x4 150 15 1 14 (c,=14; +mx8+shl1024x4 132 16 1 15 (c,=14;(b)=1; +mx8+shl1024x4 169 11 1 10 (c,=9;(a)=1; +mx8+shl1024x4 181 9 1 8 (c,=8; +mx8+shl1024x4 139 20 1 19 (c,=19; +mx8+shl1024x4 186 6 1 5 (c,=4;(b)=1; +mx8+shl1024x4 189 4 1 3 (c,=3; +mx8+shl1024x4 161 16 1 15 (c,=14;(a)=1; +mx8+shl1024x4 165 10 1 9 (c,=9; +mx8+shl1024x4 122 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl1024x4 163 16 1 15 (c,=13;(b)=1;(a)=1; +mx8+shl1024x4 196 4 1 3 (c,=3; +mx8+shl1024x4 109 28 1 27 (c,=25;(b)=1;(a)=1; +mx8+shl1024x4 170 12 1 11 (c,=11; +mx8+shl1024x4 154 17 1 16 (c,=16; +mx8+shl1024x4 126 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 203 4 1 3 (c,=3; +mx8+shl1024x4 194 8 1 7 (c,=7; +mx8+shl1024x4 200 3 1 2 (c,=2; +mx8+shl1024x4 209 3 1 2 (c,=2; +mx8+shl1024x4 167 14 1 13 (c,=13; +mx8+shl1024x4 213 3 1 2 (c,=2; +mx8+shl1024x4 164 18 1 17 (c,=16;(b)=1; +mx8+shl1024x4 210 5 1 4 (c,=4; +mx8+shl1024x4 171 18 1 17 (c,=17; +mx8+shl1024x4 148 27 1 26 (c,=22;(a)=2;(c)=1;(b)=1; +mx8+shl1024x4 143 29 1 28 (c,=26;(b)=2; +mx8+shl1024x4 223 3 1 2 (c,=2; +mx8+shl1024x4 140 30 1 29 (c,=28;(a)=1; +mx8+shl1024x4 168 17 1 16 (c,=15;(b)=1; +mx8+shl1024x4 118 32 0 none (c,=29;(c)=1;(b)=1;(a)=1; +mx8+shl1024x4 162 25 1 24 (c,=22;(b)=2; +mx8+shl1024x4 182 21 1 20 (c,=17;(a)=2;(c)=1; +mx8+shl1024x4 195 14 1 13 (c,=12;(b)=1; +mx8+shl1024x4 149 26 1 25 (c,=25; +mx8+shl1024x4 214 8 1 7 (c,=7; +mx8+shl1024x4 153 29 1 28 (c,=27;(a)=1; +mx8+shl1024x4 147 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 197 16 1 15 (c,=14;(a)=1; +mx8+shl1024x4 234 2 1 1 (c,=1; +mx8+shl1024x4 192 19 1 18 (c,=17;(a)=1; +mx8+shl1024x4 239 2 1 1 (c,=1; +mx8+shl1024x4 216 12 1 11 (c,=10;(a)=1; +mx8+shl1024x4 221 11 1 10 (c,=10; +mx8+shl1024x4 225 9 1 8 (c,=8; +mx8+shl1024x4 218 11 1 10 (c,=10; +mx8+shl1024x4 236 4 1 3 (c,=3; +mx8+shl1024x4 242 3 1 2 (c,=2; +mx8+shl1024x4 230 10 1 9 (c,=9; +mx8+shl1024x4 219 16 1 15 (c,=14;(a)=1; +mx8+shl1024x4 175 32 0 none (c,=31;(a)=1; +mx8+shl1024x4 238 5 1 4 (c,=4; +mx8+shl1024x4 222 14 1 13 (c,=12;(a)=1; +mx8+shl1024x4 199 23 1 22 (c,=20;(b)=1;(a)=1; +mx8+shl1024x4 205 16 1 15 (c,=14;(a)=1; +mx8+shl1024x4 252 1 1 0 +mx8+shl1024x4 232 9 1 8 (c,=8; +mx8+shl1024x4 250 2 1 1 (c,=1; +mx8+shl1024x4 193 21 1 20 (c,=20; +mx8+shl1024x4 215 18 1 17 (c,=16;(a)=1; +mx8+shl1024x4 240 6 1 5 (c,=5; +mx8+shl1024x4 207 18 1 17 (c,=17; +mx8+shl1024x4 226 17 1 16 (c,=15;(b)=1; +mx8+shl1024x4 231 13 1 12 (c,=11;(b)=1; +mx8+shl1024x4 220 18 1 17 (c,=16;(a)=1; +mx8+shl2048x2 2 1 1 0 +mx8+shl1024x4 255 3 1 2 (c,=2; +mx8+shl1024x4 247 7 1 6 (c,=6; +mx8+shl1024x4 233 11 1 10 (c,=10; +mx8+shl1024x4 198 27 1 26 (c,=25;(b)=1; +mx8+shl2048x2 5 2 1 1 (c,=1; +mx8+shl1024x4 254 6 1 5 (c,=4;(b)=1; +mx8+shl2048x2 6 2 1 1 (c,=1; +mx8+shl1024x4 191 32 0 none (c,=32; +mx8+shl1024x4 188 32 0 none (c,=29;(a)=3; +mx8+shl1024x4 217 23 1 22 (c,=22; +mx8+shl1024x4 246 9 1 8 (c,=8; +mx8+shl1024x4 212 32 1 31 (c,=29;(b)=1;(a)=1; +mx8+shl1024x4 243 16 1 15 (c,=13;(b)=2; +mx8+shl1024x4 229 18 1 17 (c,=16;(b)=1; +mx8+shl2048x2 3 5 1 4 (c,=3;(a)=1; +mx8+shl2048x2 25 1 1 0 +mx8+shl1024x4 244 16 1 15 (c,=14;(b)=1; +mx8+shl2048x2 12 4 1 3 (c,=3; +mx8+shl1024x4 206 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 11 7 1 6 (c,=5;(b)=1; +mx8+shl1024x4 204 32 0 none (c,=32; +mx8+shl2048x2 20 3 1 2 (c,=2; +mx8+shl1024x4 235 19 1 18 (c,=18; +mx8+shl1024x4 227 21 1 20 (c,=20; +mx8+shl1024x4 228 22 1 21 (c,=21; +mx8+shl1024x4 183 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 211 32 0 none (c,=31;(b)=1; +mx8+shl1024x4 202 30 1 29 (c,=29; +mx8+shl2048x2 7 7 1 6 (c,=6; +mx8+shl2048x2 22 4 1 3 (c,=3; +mx8+shl2048x2 30 2 1 1 (c,=1; +mx8+shl1024x4 208 32 0 none (c,=30;(b)=2; +mx8+shl1024x4 201 32 0 none (c,=32; +mx8+shl2048x2 1 7 1 6 (c,=6; +mx8+shl2048x2 23 7 1 6 (c,=5;(a)=1; +mx8+shl2048x2 38 2 1 1 (c,=1; +mx8+shl1024x4 237 30 1 29 (c,=27;(b)=1;(a)=1; +mx8+shl2048x2 34 2 1 1 (c,=1; +mx8+shl2048x2 16 9 1 8 (c,=8; +mx8+shl2048x2 14 12 1 11 (c,=11; +mx8+shl2048x2 28 7 1 6 (c,=6; +mx8+shl2048x2 41 5 1 4 (c,=3;(a)=1; +mx8+shl2048x2 26 8 1 7 (c,=7; +mx8+shl2048x2 24 8 1 7 (c,=7; +mx8+shl2048x2 4 12 1 11 (c,=9;(b)=1;(a)=1; +mx8+shl1024x4 224 31 1 30 (c,=30; +mx8+shl2048x2 13 12 1 11 (c,=11; +mx8+shl1024x4 248 27 1 26 (c,=26; +mx8+shl2048x2 37 5 1 4 (c,=4; +mx8+shl2048x2 55 1 1 0 +mx8+shl2048x2 50 3 1 2 (c,=2; +mx8+shl2048x2 35 8 1 7 (c,=6;(b)=1; +mx8+shl2048x2 15 11 1 10 (c,=10; +mx8+shl2048x2 51 4 1 3 (c,=3; +mx8+shl2048x2 47 4 1 3 (c,=3; +mx8+shl2048x2 42 5 1 4 (c,=4; +mx8+shl1024x4 251 26 1 25 (c,=24;(b)=1; +mx8+shl2048x2 57 1 1 0 +mx8+shl2048x2 60 2 1 1 (b)=1; +mx8+shl1024x4 245 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl2048x2 68 3 1 2 (c,=2; +mx8+shl1024x4 241 28 1 27 (c,=25;(a)=2; +mx8+shl2048x2 71 1 1 0 +mx8+shl2048x2 62 4 1 3 (c,=2;(a)=1; +mx8+shl2048x2 44 10 1 9 (c,=8;(b)=1; +mx8+shl2048x2 21 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl2048x2 65 4 1 3 (c,=3; +mx8+shl2048x2 49 6 1 5 (c,=5; +mx8+shl2048x2 72 2 1 1 (c,=1; +mx8+shl2048x2 10 23 1 22 (c,=21;(c)=1; +mx8+shl2048x2 76 3 1 2 (c,=2; +mx8+shl2048x2 39 14 1 13 (c,=12;(b)=1; +mx8+shl2048x2 33 16 1 15 (c,=15; +mx8+shl2048x2 40 15 1 14 (c,=14; +mx8+shl2048x2 17 24 1 23 (c,=22;(b)=1; +mx8+shl2048x2 66 6 1 5 (c,=5; +mx8+shl2048x2 63 8 1 7 (c,=7; +mx8+shl2048x2 81 6 1 5 (c,=4;(b)=1; +mx8+shl2048x2 90 1 1 0 +mx8+shl2048x2 43 13 1 12 (c,=12; +mx8+shl1024x4 253 32 1 31 (c,=31; +mx8+shl1024x4 249 26 1 25 (c,=23;(b)=1;(a)=1; +mx8+shl2048x2 83 5 1 4 (c,=3;(b)=1; +mx8+shl2048x2 8 32 0 none (c,=30;(a)=2; +mx8+shl2048x2 9 24 1 23 (c,=22;(c)=1; +mx8+shl2048x2 61 13 1 12 (c,=10;(b)=1;(a)=1; +mx8+shl2048x2 48 15 1 14 (c,=13;(a)=1; +mx8+shl2048x2 93 2 1 1 (c,=1; +mx8+shl2048x2 89 3 1 2 (c,=1;(a)=1; +mx8+shl2048x2 36 20 1 19 (c,=18;(b)=1; +mx8+shl2048x2 18 19 1 18 (c,=18; +mx8+shl2048x2 73 8 1 7 (c,=7; +mx8+shl2048x2 88 2 1 1 (c,=1; +mx8+shl2048x2 95 1 1 0 +mx8+shl2048x2 92 3 1 2 (c,=2; +mx8+shl2048x2 19 32 0 none (c,=29;(b)=2;(c)=1; +mx8+shl2048x2 56 14 1 13 (c,=10;(b)=2;(a)=1; +mx8+shl2048x2 91 4 1 3 (c,=3; +mx8+shl2048x2 0 32 1 31 (c,=31; +mx8+shl2048x2 70 11 1 10 (c,=8;(b)=1;(a)=1; +mx8+shl2048x2 97 2 1 1 (c,=1; +mx8+shl2048x2 80 9 1 8 (c,=8; +mx8+shl2048x2 84 7 1 6 (c,=5;(a)=1; +mx8+shl2048x2 103 2 1 1 (c,=1; +mx8+shl2048x2 27 24 1 23 (c,=23; +mx8+shl2048x2 54 16 1 15 (c,=15; +mx8+shl2048x2 31 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl2048x2 69 14 1 13 (c,=12;(a)=1; +mx8+shl2048x2 105 3 1 2 (c,=2; +mx8+shl2048x2 117 1 1 0 +mx8+shl2048x2 116 1 1 0 +mx8+shl2048x2 98 5 1 4 (c,=4; +mx8+shl2048x2 75 12 1 11 (c,=10;(b)=1; +mx8+shl2048x2 87 9 1 8 (c,=8; +mx8+shl2048x2 100 5 1 4 (c,=4; +mx8+shl2048x2 113 4 1 3 (c,=3; +mx8+shl2048x2 118 3 1 2 (c,=2; +mx8+shl2048x2 29 27 1 26 (c,=26; +mx8+shl2048x2 112 5 1 4 (c,=4; +mx8+shl2048x2 130 1 1 0 +mx8+shl2048x2 102 8 1 7 (c,=7; +mx8+shl2048x2 126 2 1 1 (c,=1; +mx8+shl2048x2 52 23 1 22 (c,=21;(a)=1; +mx8+shl2048x2 107 5 1 4 (c,=4; +mx8+shl2048x2 32 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 108 8 1 7 (c,=7; +mx8+shl2048x2 127 4 1 3 (c,=3; +mx8+shl2048x2 128 3 1 2 (c,=2; +mx8+shl2048x2 125 5 1 4 (c,=3;(a)=1; +mx8+shl2048x2 59 23 1 22 (c,=21;(b)=1; +mx8+shl2048x2 45 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 96 12 1 11 (c,=11; +mx8+shl2048x2 122 6 1 5 (c,=5; +mx8+shl2048x2 134 2 1 1 (c,=1; +mx8+shl2048x2 124 7 1 6 (c,=6; +mx8+shl2048x2 133 2 1 1 (c,=1; +mx8+shl2048x2 85 18 1 17 (c,=15;(b)=1;(a)=1; +mx8+shl2048x2 86 18 1 17 (c,=16;(a)=1; +mx8+shl2048x2 74 23 1 22 (c,=22; +mx8+shl2048x2 53 32 0 none (c,=32; +mx8+shl2048x2 104 14 1 13 (c,=13; +mx8+shl2048x2 99 13 1 12 (c,=11;(a)=1; +mx8+shl2048x2 149 1 1 0 +mx8+shl2048x2 142 3 1 2 (c,=2; +mx8+shl2048x2 46 28 1 27 (c,=24;(b)=2;(a)=1; +mx8+shl2048x2 110 14 1 13 (c,=13; +mx8+shl2048x2 151 2 1 1 (c,=1; +mx8+shl2048x2 140 5 1 4 (c,=4; +mx8+shl2048x2 58 30 1 29 (c,=28;(b)=1; +mx8+shl2048x2 138 6 1 5 (c,=5; +mx8+shl2048x2 94 17 1 16 (c,=16; +mx8+shl2048x2 109 16 1 15 (c,=13;(b)=1;(a)=1; +mx8+shl2048x2 136 8 1 7 (c,=6;(a)=1; +mx8+shl2048x2 77 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 106 12 1 11 (c,=11; +mx8+shl2048x2 144 4 1 3 (c,=3; +mx8+shl2048x2 146 6 1 5 (c,=4;(a)=1; +mx8+shl2048x2 101 21 1 20 (c,=17;(b)=2;(c)=1; +mx8+shl2048x2 137 4 1 3 (c,=3; +mx8+shl2048x2 141 7 1 6 (c,=6; +mx8+shl2048x2 123 12 1 11 (c,=11; +mx8+shl2048x2 67 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 148 6 1 5 (c,=5; +mx8+shl2048x2 139 9 1 8 (c,=8; +mx8+shl2048x2 162 5 1 4 (c,=4; +mx8+shl2048x2 163 3 1 2 (c,=2; +mx8+shl2048x2 153 6 1 5 (c,=4;(a)=1; +mx8+shl2048x2 129 17 1 16 (c,=16; +mx8+shl2048x2 176 1 1 0 +mx8+shl2048x2 179 1 1 0 +mx8+shl2048x2 64 32 1 31 (c,=30;(b)=1; +mx8+shl2048x2 78 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 158 8 1 7 (c,=7; +mx8+shl2048x2 155 9 1 8 (c,=8; +mx8+shl2048x2 174 2 1 1 (c,=1; +mx8+shl2048x2 82 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 156 11 1 10 (c,=8;(b)=2; +mx8+shl2048x2 172 7 1 6 (c,=5;(a)=1; +mx8+shl2048x2 180 5 1 4 (c,=4; +mx8+shl2048x2 135 13 1 12 (c,=12; +mx8+shl2048x2 111 27 1 26 (c,=23;(b)=2;(a)=1; +mx8+shl2048x2 121 27 1 26 (c,=23;(b)=2;(a)=1; +mx8+shl2048x2 131 16 1 15 (c,=15; +mx8+shl2048x2 79 32 1 31 (c,=31; +mx8+shl2048x2 164 11 1 10 (c,=9;(b)=1; +mx8+shl2048x2 119 29 1 28 (c,=25;(a)=2;(b)=1; +mx8+shl2048x2 173 6 1 5 (c,=5; +mx8+shl2048x2 114 25 1 24 (c,=24; +mx8+shl2048x2 169 11 1 10 (c,=9;(a)=1; +mx8+shl2048x2 186 6 1 5 (c,=4;(b)=1; +mx8+shl2048x2 165 10 1 9 (c,=9; +mx8+shl2048x2 150 15 1 14 (c,=14; +mx8+shl2048x2 181 10 1 9 (c,=9; +mx8+shl2048x2 160 13 1 12 (c,=12; +mx8+shl2048x2 192 6 1 5 (c,=5; +mx8+shl2048x2 170 11 1 10 (c,=10; +mx8+shl2048x2 152 14 1 13 (c,=12;(b)=1; +mx8+shl2048x2 154 17 1 16 (c,=16; +mx8+shl2048x2 177 14 1 13 (c,=13; +mx8+shl2048x2 205 1 1 0 +mx8+shl2048x2 209 1 1 0 +mx8+shl2048x2 161 16 1 15 (c,=14;(a)=1; +mx8+shl2048x2 196 4 1 3 (c,=2;(c)=1; +mx8+shl2048x2 200 3 1 2 (c,=2; +mx8+shl2048x2 132 29 1 28 (c,=25;(b)=2;(a)=1; +mx8+shl2048x2 157 17 1 16 (c,=16; +mx8+shl2048x2 194 6 1 5 (c,=5; +mx8+shl2048x2 193 7 1 6 (c,=6; +mx8+shl2048x2 159 22 1 21 (c,=19;(b)=2; +mx8+shl2048x2 206 5 1 4 (c,=4; +mx8+shl2048x2 211 3 1 2 (c,=2; +mx8+shl2048x2 120 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 115 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 210 5 1 4 (c,=4; +mx8+shl2048x2 183 18 1 17 (c,=16;(b)=1; +mx8+shl2048x2 184 17 1 16 (c,=14;(a)=2; +mx8+shl2048x2 182 16 1 15 (c,=14;(a)=1; +mx8+shl2048x2 143 29 1 28 (c,=26;(b)=2; +mx8+shl2048x2 167 20 1 19 (c,=19; +mx8+shl2048x2 224 1 1 0 +mx8+shl2048x2 168 23 1 22 (c,=21;(b)=1; +mx8+shl2048x2 218 5 1 4 (c,=4; +mx8+shl2048x2 223 3 1 2 (c,=2; +mx8+shl2048x2 147 32 0 none (c,=30;(b)=2; +mx8+shl2048x2 197 11 1 10 (c,=10; +mx8+shl2048x2 202 9 1 8 (c,=8; +mx8+shl2048x2 199 11 1 10 (c,=9;(b)=1; +mx8+shl2048x2 145 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 195 14 1 13 (c,=12;(b)=1; +mx8+shl2048x2 221 4 1 3 (c,=3; +mx8+shl2048x2 190 17 1 16 (c,=16; +mx8+shl2048x2 214 8 1 7 (c,=7; +mx8+shl2048x2 242 3 1 2 (c,=2; +mx8+shl2048x2 191 21 1 20 (c,=20; +mx8+shl2048x2 216 12 1 11 (c,=10;(a)=1; +mx8+shl2048x2 230 6 1 5 (c,=5; +mx8+shl2048x2 243 3 1 2 (c,=2; +mx8+shl2048x2 236 8 1 7 (c,=6;(c)=1; +mx8+shl2048x2 234 7 1 6 (c,=6; +mx8+shl2048x2 171 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 239 7 1 6 (c,=5;(b)=1; +mx8+shl2048x2 238 5 1 4 (c,=4; +mx8+shl2048x2 175 32 0 none (c,=31;(a)=1; +mx8+shl2048x2 240 6 1 5 (c,=5; +mx8+shl2048x2 232 9 1 8 (c,=8; +mx8+shl2048x2 185 24 1 23 (c,=22;(b)=1; +mx8+shl2048x2 189 25 1 24 (c,=23;(b)=1; +mx8+shl2048x2 219 16 1 15 (c,=14;(a)=1; +mx8+shl2048x2 207 18 1 17 (c,=17; +mx8+shl2048x2 233 11 1 10 (c,=10; +mx8+shl2048x2 231 13 1 12 (c,=11;(b)=1; +mx8+shl2048x2 217 20 1 19 (c,=19; +mx8+shl4096x1 6 2 1 1 (c,=1; +mx8+shl4096x1 2 1 1 0 +mx8+shl2048x2 166 31 1 30 (c,=30; +mx8+shl2048x2 246 9 1 8 (c,=8; +mx8+shl2048x2 187 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 178 31 1 30 (c,=29;(b)=1; +mx8+shl2048x2 203 26 1 25 (c,=23;(b)=2; +mx8+shl2048x2 229 18 1 17 (c,=16;(b)=1; +mx8+shl4096x1 14 1 1 0 +mx8+shl2048x2 254 6 1 5 (c,=4;(b)=1; +mx8+shl4096x1 7 4 1 3 (c,=3; +mx8+shl2048x2 188 32 0 none (c,=29;(a)=3; +mx8+shl2048x2 247 12 1 11 (c,=11; +mx8+shl2048x2 227 15 1 14 (c,=14; +mx8+shl2048x2 244 16 1 15 (c,=14;(b)=1; +mx8+shl4096x1 12 4 1 3 (c,=3; +mx8+shl2048x2 225 20 1 19 (c,=19; +mx8+shl2048x2 198 32 0 none (c,=31;(b)=1; +mx8+shl2048x2 222 22 1 21 (c,=20;(a)=1; +mx8+shl4096x1 11 7 1 6 (c,=5;(b)=1; +mx8+shl2048x2 241 21 1 20 (c,=18;(a)=2; +mx8+shl2048x2 201 32 1 31 (c,=31; +mx8+shl4096x1 19 3 1 2 (c,=2; +mx8+shl4096x1 17 3 1 2 (c,=2; +mx8+shl4096x1 16 3 1 2 (c,=2; +mx8+shl4096x1 25 1 1 0 +mx8+shl2048x2 204 32 0 none (c,=32; +mx8+shl2048x2 215 32 1 31 (c,=28;(a)=2;(b)=1; +mx8+shl4096x1 10 9 1 8 (c,=8; +mx8+shl2048x2 212 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 220 24 1 23 (c,=22;(a)=1; +mx8+shl2048x2 208 27 1 26 (c,=24;(b)=2; +mx8+shl4096x1 29 1 1 0 +mx8+shl4096x1 24 3 1 2 (c,=2; +mx8+shl4096x1 22 4 1 3 (c,=3; +mx8+shl4096x1 1 10 1 9 (c,=9; +mx8+shl4096x1 9 8 1 7 (c,=7; +mx8+shl2048x2 213 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 248 20 1 19 (c,=19; +mx8+shl4096x1 38 2 1 1 (c,=1; +mx8+shl4096x1 36 2 1 1 (c,=1; +mx8+shl4096x1 15 11 1 10 (c,=10; +mx8+shl4096x1 33 3 1 2 (c,=2; +mx8+shl4096x1 44 1 1 0 +mx8+shl4096x1 46 1 1 0 +mx8+shl2048x2 255 18 1 17 (c,=17; +mx8+shl2048x2 245 24 1 23 (c,=19;(b)=2;(a)=2; +mx8+shl2048x2 226 31 1 30 (c,=28;(b)=2; +mx8+shl2048x2 249 23 1 22 (c,=20;(b)=1;(a)=1; +mx8+shl2048x2 237 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl2048x2 235 32 0 none (c,=32; +mx8+shl4096x1 34 6 1 5 (c,=5; +mx8+shl4096x1 23 9 1 8 (c,=7;(a)=1; +mx8+shl4096x1 32 8 1 7 (c,=6;(b)=1; +mx8+shl4096x1 39 5 1 4 (c,=4; +mx8+shl4096x1 13 12 1 11 (c,=11; +mx8+shl4096x1 55 1 1 0 +mx8+shl4096x1 50 3 1 2 (c,=2; +mx8+shl4096x1 37 5 1 4 (c,=4; +mx8+shl4096x1 51 4 1 3 (c,=3; +mx8+shl4096x1 47 4 1 3 (c,=3; +mx8+shl4096x1 57 1 1 0 +mx8+shl4096x1 26 9 1 8 (c,=8; +mx8+shl4096x1 42 5 1 4 (c,=4; +mx8+shl4096x1 60 2 1 1 (b)=1; +mx8+shl4096x1 28 10 1 9 (c,=8;(b)=1; +mx8+shl4096x1 35 8 1 7 (c,=6;(b)=1; +mx8+shl4096x1 0 22 1 21 (c,=21; +mx8+shl2048x2 251 26 1 25 (c,=24;(b)=1; +mx8+shl4096x1 69 1 1 0 +mx8+shl2048x2 228 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 49 6 1 5 (c,=5; +mx8+shl4096x1 4 22 1 21 (c,=17;(b)=2;(a)=2; +mx8+shl4096x1 20 13 1 12 (c,=12; +mx8+shl4096x1 62 4 1 3 (c,=2;(a)=1; +mx8+shl4096x1 72 2 1 1 (c,=1; +mx8+shl4096x1 8 21 1 20 (c,=19;(a)=1; +mx8+shl2048x2 250 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 65 4 1 3 (c,=3; +mx8+shl4096x1 71 3 1 2 (c,=2; +mx8+shl4096x1 58 7 1 6 (c,=6; +mx8+shl2048x2 253 32 0 none (c,=32; +mx8+shl4096x1 90 1 1 0 +mx8+shl4096x1 21 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl4096x1 78 5 1 4 (c,=4; +mx8+shl4096x1 18 19 1 18 (c,=18; +mx8+shl2048x2 252 32 0 none (c,=32; +mx8+shl4096x1 75 5 1 4 (c,=4; +mx8+shl4096x1 93 2 1 1 (c,=1; +mx8+shl4096x1 83 6 1 5 (c,=4;(b)=1; +mx8+shl4096x1 80 5 1 4 (c,=4; +mx8+shl4096x1 95 1 1 0 +mx8+shl4096x1 79 7 1 6 (c,=6; +mx8+shl4096x1 43 13 1 12 (c,=12; +mx8+shl4096x1 40 15 1 14 (c,=14; +mx8+shl4096x1 73 8 1 7 (c,=7; +mx8+shl4096x1 68 12 1 11 (c,=10;(b)=1; +mx8+shl4096x1 48 15 1 14 (c,=13;(a)=1; +mx8+shl4096x1 52 17 1 16 (c,=15;(a)=1; +mx8+shl4096x1 30 20 1 19 (c,=19; +mx8+shl4096x1 97 2 1 1 (c,=1; +mx8+shl4096x1 63 11 1 10 (c,=10; +mx8+shl4096x1 76 10 1 9 (c,=8;(b)=1; +mx8+shl4096x1 3 32 0 none (c,=30;(a)=2; +mx8+shl4096x1 27 24 1 23 (c,=23; +mx8+shl4096x1 45 17 1 16 (c,=16; +mx8+shl4096x1 89 10 1 9 (c,=8;(a)=1; +mx8+shl4096x1 103 5 1 4 (c,=3;(b)=1; +mx8+shl4096x1 100 7 1 6 (c,=6; +mx8+shl4096x1 31 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x1 116 1 1 0 +mx8+shl4096x1 107 5 1 4 (c,=4; +mx8+shl4096x1 5 31 1 30 (c,=30; +mx8+shl4096x1 98 8 1 7 (c,=7; +mx8+shl4096x1 102 8 1 7 (c,=7; +mx8+shl4096x1 117 1 1 0 +mx8+shl4096x1 112 4 1 3 (c,=3; +mx8+shl4096x1 118 3 1 2 (c,=2; +mx8+shl4096x1 106 6 1 5 (c,=5; +mx8+shl4096x1 113 5 1 4 (c,=4; +mx8+shl4096x1 56 26 1 25 (c,=21;(b)=3;(a)=1; +mx8+shl4096x1 94 9 1 8 (c,=8; +mx8+shl4096x1 41 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 114 6 1 5 (c,=5; +mx8+shl4096x1 84 18 1 17 (c,=16;(a)=1; +mx8+shl4096x1 64 20 1 19 (c,=18;(b)=1; +mx8+shl4096x1 96 12 1 11 (c,=11; +mx8+shl4096x1 54 22 1 21 (c,=20;(b)=1; +mx8+shl4096x1 92 14 1 13 (c,=13; +mx8+shl4096x1 130 1 1 0 +mx8+shl4096x1 74 19 1 18 (c,=18; +mx8+shl4096x1 91 18 1 17 (c,=14;(a)=2;(b)=1; +mx8+shl4096x1 88 19 1 18 (c,=16;(b)=2; +mx8+shl4096x1 86 18 1 17 (c,=16;(a)=1; +mx8+shl4096x1 120 6 1 5 (c,=5; +mx8+shl4096x1 111 8 1 7 (c,=6;(a)=1; +mx8+shl4096x1 99 13 1 12 (c,=11;(a)=1; +mx8+shl4096x1 131 2 1 1 (c,=1; +mx8+shl4096x1 134 2 1 1 (c,=1; +mx8+shl4096x1 104 14 1 13 (c,=13; +mx8+shl4096x1 141 1 1 0 +mx8+shl4096x1 125 5 1 4 (c,=3;(a)=1; +mx8+shl4096x1 127 5 1 4 (c,=4; +mx8+shl4096x1 146 1 1 0 +mx8+shl4096x1 124 7 1 6 (c,=6; +mx8+shl4096x1 145 2 1 1 (c,=1; +mx8+shl4096x1 53 32 0 none (c,=32; +mx8+shl4096x1 82 25 1 24 (c,=22;(b)=1;(a)=1; +mx8+shl4096x1 67 26 1 25 (c,=25; +mx8+shl4096x1 135 4 1 3 (c,=3; +mx8+shl4096x1 149 1 1 0 +mx8+shl4096x1 105 18 1 17 (c,=15;(b)=1;(a)=1; +mx8+shl4096x1 61 31 1 30 (c,=26;(b)=3;(a)=1; +mx8+shl4096x1 137 4 1 3 (c,=3; +mx8+shl4096x1 81 26 1 25 (c,=21;(b)=3;(a)=1; +mx8+shl4096x1 59 27 1 26 (c,=25;(b)=1; +mx8+shl4096x1 110 16 1 15 (c,=15; +mx8+shl4096x1 128 8 1 7 (c,=7; +mx8+shl4096x1 85 28 1 27 (c,=25;(b)=1;(a)=1; +mx8+shl4096x1 144 4 1 3 (c,=3; +mx8+shl4096x1 129 10 1 9 (c,=9; +mx8+shl4096x1 140 5 1 4 (c,=4; +mx8+shl4096x1 119 13 1 12 (c,=11;(a)=1; +mx8+shl4096x1 148 6 1 5 (c,=5; +mx8+shl4096x1 109 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl4096x1 77 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 142 8 1 7 (c,=7; +mx8+shl4096x1 123 12 1 11 (c,=11; +mx8+shl4096x1 138 7 1 6 (c,=6; +mx8+shl4096x1 153 6 1 5 (c,=4;(a)=1; +mx8+shl4096x1 87 26 1 25 (c,=25; +mx8+shl4096x1 101 32 0 none (c,=29;(b)=3; +mx8+shl4096x1 176 1 1 0 +mx8+shl4096x1 155 6 1 5 (c,=5; +mx8+shl4096x1 70 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x1 156 11 1 10 (c,=8;(b)=2; +mx8+shl4096x1 162 5 1 4 (c,=4; +mx8+shl4096x1 184 1 1 0 +mx8+shl4096x1 185 1 1 0 +mx8+shl4096x1 151 11 1 10 (c,=9;(b)=1; +mx8+shl4096x1 136 17 1 16 (c,=15;(a)=1; +mx8+shl4096x1 157 9 1 8 (c,=8; +mx8+shl4096x1 158 9 1 8 (c,=7;(c)=1; +mx8+shl4096x1 66 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 182 3 1 2 (c,=2; +mx8+shl4096x1 190 1 1 0 +mx8+shl4096x1 165 10 1 9 (c,=9; +mx8+shl4096x1 108 27 1 26 (c,=26; +mx8+shl4096x1 150 13 1 12 (c,=12; +mx8+shl4096x1 172 7 1 6 (c,=5;(a)=1; +mx8+shl4096x1 115 23 1 22 (c,=21;(b)=1; +mx8+shl4096x1 164 11 1 10 (c,=9;(b)=1; +mx8+shl4096x1 152 14 1 13 (c,=12;(b)=1; +mx8+shl4096x1 175 9 1 8 (c,=8; +mx8+shl4096x1 186 6 1 5 (c,=4;(b)=1; +mx8+shl4096x1 169 11 1 10 (c,=9;(a)=1; +mx8+shl4096x1 154 17 1 16 (c,=16; +mx8+shl4096x1 170 11 1 10 (c,=10; +mx8+shl4096x1 205 1 1 0 +mx8+shl4096x1 173 12 1 11 (c,=11; +mx8+shl4096x1 178 12 1 11 (c,=10;(b)=1; +mx8+shl4096x1 187 10 1 9 (c,=7;(b)=1;(a)=1; +mx8+shl4096x1 181 9 1 8 (c,=8; +mx8+shl4096x1 160 13 1 12 (c,=12; +mx8+shl4096x1 177 14 1 13 (c,=13; +mx8+shl4096x1 209 1 1 0 +mx8+shl4096x1 121 32 1 31 (c,=28;(b)=2;(a)=1; +mx8+shl4096x1 200 3 1 2 (c,=2; +mx8+shl4096x1 161 16 1 15 (c,=14;(a)=1; +mx8+shl4096x1 132 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 122 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl4096x1 206 4 1 3 (c,=3; +mx8+shl4096x1 212 3 1 2 (c,=2; +mx8+shl4096x1 194 8 1 7 (c,=7; +mx8+shl4096x1 133 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x1 159 22 1 21 (c,=19;(b)=2; +mx8+shl4096x1 211 3 1 2 (c,=2; +mx8+shl4096x1 210 5 1 4 (c,=4; +mx8+shl4096x1 171 18 1 17 (c,=17; +mx8+shl4096x1 126 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 217 4 1 3 (c,=3; +mx8+shl4096x1 139 26 1 25 (c,=24;(a)=1; +mx8+shl4096x1 180 16 1 15 (c,=14;(b)=1; +mx8+shl4096x1 174 24 1 23 (c,=20;(b)=2;(a)=1; +mx8+shl4096x1 193 11 1 10 (c,=9;(c)=1; +mx8+shl4096x1 192 12 1 11 (c,=11; +mx8+shl4096x1 167 20 1 19 (c,=19; +mx8+shl4096x1 213 5 1 4 (c,=4; +mx8+shl4096x1 199 11 1 10 (c,=9;(b)=1; +mx8+shl4096x1 223 3 1 2 (c,=2; +mx8+shl4096x1 147 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 196 13 1 12 (c,=12; +mx8+shl4096x1 198 9 1 8 (c,=7;(b)=1; +mx8+shl4096x1 202 9 1 8 (c,=8; +mx8+shl4096x1 197 16 1 15 (c,=14;(a)=1; +mx8+shl4096x1 234 2 1 1 (c,=1; +mx8+shl4096x1 143 32 0 none (c,=30;(b)=2; +mx8+shl4096x1 163 26 1 25 (c,=22;(b)=2;(a)=1; +mx8+shl4096x1 240 2 1 1 (c,=1; +mx8+shl4096x1 224 6 1 5 (c,=5; +mx8+shl4096x1 168 27 1 26 (c,=25;(b)=1; +mx8+shl4096x1 191 21 1 20 (c,=20; +mx8+shl4096x1 222 10 1 9 (c,=8;(a)=1; +mx8+shl4096x1 230 6 1 5 (c,=5; +mx8+shl4096x1 249 2 1 1 (b)=1; +mx8+shl4096x1 242 3 1 2 (c,=2; +mx8+shl4096x1 218 11 1 10 (c,=10; +mx8+shl4096x1 221 11 1 10 (c,=10; +mx8+shl4096x1 235 7 1 6 (c,=6; +mx8+shl4096x1 250 2 1 1 (c,=1; +mx8+shl4096x1 225 9 1 8 (c,=8; +mx8+shl4096x1 248 4 1 3 (c,=3; +mx8+shl4096x1 239 9 1 8 (c,=7;(b)=1; +mx8+shl4096x1 233 11 1 10 (c,=10; +mx8+shl4096x2 2 1 1 0 +mx8+shl4096x1 179 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl4096x1 166 31 1 30 (c,=30; +mx8+shl4096x1 255 3 1 2 (c,=2; +mx8+shl4096x1 247 7 1 6 (c,=6; +mx8+shl4096x1 232 11 1 10 (c,=10; +mx8+shl4096x1 215 18 1 17 (c,=16;(a)=1; +mx8+shl4096x1 183 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 189 25 1 24 (c,=23;(b)=1; +mx8+shl4096x2 6 2 1 1 (c,=1; +mx8+shl4096x2 7 1 1 0 +mx8+shl4096x1 195 28 1 27 (c,=25;(b)=2; +mx8+shl4096x1 219 20 1 19 (c,=18;(a)=1; +mx8+shl4096x1 227 13 1 12 (c,=12; +mx8+shl4096x1 201 24 1 23 (c,=23; +mx8+shl4096x1 229 16 1 15 (c,=14;(b)=1; +mx8+shl4096x1 216 21 1 20 (c,=19;(a)=1; +mx8+shl4096x1 188 32 0 none (c,=29;(a)=3; +mx8+shl4096x1 203 25 1 24 (c,=22;(b)=2; +mx8+shl4096x1 244 12 1 11 (c,=11; +mx8+shl4096x1 208 27 1 26 (c,=24;(b)=2; +mx8+shl4096x1 251 8 1 7 (c,=7; +mx8+shl4096x1 226 17 1 16 (c,=15;(b)=1; +mx8+shl4096x1 241 13 1 12 (c,=11;(a)=1; +mx8+shl4096x1 231 16 1 15 (c,=14;(b)=1; +mx8+shl4096x2 14 1 1 0 +mx8+shl4096x1 243 16 1 15 (c,=13;(b)=2; +mx8+shl4096x2 25 1 1 0 +mx8+shl4096x2 17 3 1 2 (c,=2; +mx8+shl4096x1 245 24 1 23 (c,=19;(b)=2;(a)=2; +mx8+shl4096x1 236 18 1 17 (c,=17; +mx8+shl4096x1 220 24 1 23 (c,=22;(a)=1; +mx8+shl4096x2 12 4 1 3 (c,=3; +mx8+shl4096x2 20 3 1 2 (c,=2; +mx8+shl4096x2 19 3 1 2 (c,=2; +mx8+shl4096x2 16 3 1 2 (c,=2; +mx8+shl4096x2 11 7 1 6 (c,=5;(b)=1; +mx8+shl4096x2 24 3 1 2 (c,=2; +mx8+shl4096x2 33 3 1 2 (c,=2; +mx8+shl4096x1 252 16 1 15 (c,=15; +mx8+shl4096x2 22 4 1 3 (c,=3; +mx8+shl4096x2 36 2 1 1 (c,=1; +mx8+shl4096x1 207 32 0 none (c,=31;(b)=1; +mx8+shl4096x1 204 32 0 none (c,=32; +mx8+shl4096x2 44 1 1 0 +mx8+shl4096x2 38 2 1 1 (c,=1; +mx8+shl4096x2 46 1 1 0 +mx8+shl4096x1 238 32 0 none (c,=26;(b)=4;(a)=2; +mx8+shl4096x2 9 8 1 7 (c,=7; +mx8+shl4096x1 228 22 1 21 (c,=21; +mx8+shl4096x2 1 10 1 9 (c,=9; +mx8+shl4096x2 32 8 1 7 (c,=6;(b)=1; +mx8+shl4096x2 39 5 1 4 (c,=4; +mx8+shl4096x1 237 28 1 27 (c,=26;(b)=1; +mx8+shl4096x2 10 9 1 8 (c,=8; +mx8+shl4096x2 28 10 1 9 (c,=8;(b)=1; +mx8+shl4096x2 23 9 1 8 (c,=7;(a)=1; +mx8+shl4096x2 37 5 1 4 (c,=4; +mx8+shl4096x2 50 3 1 2 (c,=2; +mx8+shl4096x2 55 1 1 0 +mx8+shl4096x2 57 1 1 0 +mx8+shl4096x2 26 9 1 8 (c,=8; +mx8+shl4096x2 47 4 1 3 (c,=3; +mx8+shl4096x2 34 6 1 5 (c,=5; +mx8+shl4096x2 51 4 1 3 (c,=3; +mx8+shl4096x2 35 8 1 7 (c,=6;(b)=1; +mx8+shl4096x2 15 11 1 10 (c,=10; +mx8+shl4096x2 60 2 1 1 (b)=1; +mx8+shl4096x1 214 30 1 29 (c,=29; +mx8+shl4096x1 246 32 0 none (c,=31;(a)=1; +mx8+shl4096x1 254 25 1 24 (c,=23;(b)=1; +mx8+shl4096x2 62 4 1 3 (c,=2;(a)=1; +mx8+shl4096x2 69 1 1 0 +mx8+shl4096x2 49 6 1 5 (c,=5; +mx8+shl4096x2 72 2 1 1 (c,=1; +mx8+shl4096x2 71 3 1 2 (c,=2; +mx8+shl4096x2 42 11 1 10 (c,=9;(b)=1; +mx8+shl4096x2 65 4 1 3 (c,=3; +mx8+shl4096x2 8 21 1 20 (c,=19;(a)=1; +mx8+shl4096x2 13 18 1 17 (c,=17; +mx8+shl4096x1 253 32 0 none (c,=32; +mx8+shl4096x2 78 5 1 4 (c,=4; +mx8+shl4096x2 58 7 1 6 (c,=6; +mx8+shl4096x2 0 22 1 21 (c,=21; +mx8+shl4096x2 4 22 1 21 (c,=17;(b)=2;(a)=2; +mx8+shl4096x2 75 5 1 4 (c,=4; +mx8+shl4096x2 90 1 1 0 +mx8+shl4096x2 21 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl4096x2 43 13 1 12 (c,=12; +mx8+shl4096x2 40 15 1 14 (c,=14; +mx8+shl4096x2 48 15 1 14 (c,=13;(a)=1; +mx8+shl4096x2 18 19 1 18 (c,=18; +mx8+shl4096x2 95 1 1 0 +mx8+shl4096x2 80 5 1 4 (c,=4; +mx8+shl4096x2 83 6 1 5 (c,=4;(b)=1; +mx8+shl4096x2 93 2 1 1 (c,=1; +mx8+shl4096x2 97 2 1 1 (c,=1; +mx8+shl4096x2 76 10 1 9 (c,=8;(b)=1; +mx8+shl4096x2 79 7 1 6 (c,=6; +mx8+shl4096x2 30 20 1 19 (c,=19; +mx8+shl4096x2 27 24 1 23 (c,=23; +mx8+shl4096x2 5 23 1 22 (c,=22; +mx8+shl4096x2 68 12 1 11 (c,=10;(b)=1; +mx8+shl4096x2 45 17 1 16 (c,=16; +mx8+shl4096x2 52 17 1 16 (c,=15;(a)=1; +mx8+shl4096x2 3 32 0 none (c,=30;(a)=2; +mx8+shl4096x2 63 11 1 10 (c,=10; +mx8+shl4096x2 103 5 1 4 (c,=3;(b)=1; +mx8+shl4096x2 89 10 1 9 (c,=8;(a)=1; +mx8+shl4096x2 31 32 0 none (c,=29;(a)=2;(b)=1; +mx8+shl4096x2 100 7 1 6 (c,=6; +mx8+shl4096x2 116 1 1 0 +mx8+shl4096x2 98 8 1 7 (c,=7; +mx8+shl4096x2 117 1 1 0 +mx8+shl4096x2 107 5 1 4 (c,=4; +mx8+shl4096x2 94 9 1 8 (c,=8; +mx8+shl4096x2 102 8 1 7 (c,=7; +mx8+shl4096x2 106 6 1 5 (c,=5; +mx8+shl4096x2 112 4 1 3 (c,=3; +mx8+shl4096x2 64 20 1 19 (c,=18;(b)=1; +mx8+shl4096x2 56 26 1 25 (c,=21;(b)=3;(a)=1; +mx8+shl4096x2 111 8 1 7 (c,=6;(a)=1; +mx8+shl4096x2 114 6 1 5 (c,=5; +mx8+shl4096x2 130 1 1 0 +mx8+shl4096x2 84 18 1 17 (c,=16;(a)=1; +mx8+shl4096x2 96 12 1 11 (c,=11; +mx8+shl4096x2 74 19 1 18 (c,=18; +mx8+shl4096x2 92 14 1 13 (c,=13; +mx8+shl4096x2 118 6 1 5 (c,=5; +mx8+shl4096x2 124 7 1 6 (c,=6; +mx8+shl4096x2 29 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 131 2 1 1 (c,=1; +mx8+shl4096x2 113 10 1 9 (c,=8;(a)=1; +mx8+shl4096x2 41 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 125 5 1 4 (c,=3;(a)=1; +mx8+shl4096x2 61 31 1 30 (c,=26;(b)=3;(a)=1; +mx8+shl4096x2 91 18 1 17 (c,=14;(a)=2;(b)=1; +mx8+shl4096x2 99 13 1 12 (c,=11;(a)=1; +mx8+shl4096x2 104 14 1 13 (c,=13; +mx8+shl4096x2 120 6 1 5 (c,=5; +mx8+shl4096x2 54 22 1 21 (c,=20;(b)=1; +mx8+shl4096x2 86 18 1 17 (c,=16;(a)=1; +mx8+shl4096x2 127 5 1 4 (c,=4; +mx8+shl4096x2 134 2 1 1 (c,=1; +mx8+shl4096x2 137 2 1 1 (c,=1; +mx8+shl4096x2 81 26 1 25 (c,=21;(b)=3;(a)=1; +mx8+shl4096x2 141 1 1 0 +mx8+shl4096x2 110 16 1 15 (c,=15; +mx8+shl4096x2 88 19 1 18 (c,=16;(b)=2; +mx8+shl4096x2 146 1 1 0 +mx8+shl4096x2 105 18 1 17 (c,=15;(b)=1;(a)=1; +mx8+shl4096x2 67 26 1 25 (c,=25; +mx8+shl4096x2 149 1 1 0 +mx8+shl4096x2 82 25 1 24 (c,=22;(b)=1;(a)=1; +mx8+shl4096x2 135 4 1 3 (c,=3; +mx8+shl4096x2 101 21 1 20 (c,=18;(b)=2; +mx8+shl4096x2 145 2 1 1 (c,=1; +mx8+shl4096x2 128 8 1 7 (c,=7; +mx8+shl4096x2 53 32 0 none (c,=32; +mx8+shl4096x2 144 4 1 3 (c,=3; +mx8+shl4096x2 129 10 1 9 (c,=9; +mx8+shl4096x2 77 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 148 6 1 5 (c,=5; +mx8+shl4096x2 140 5 1 4 (c,=4; +mx8+shl4096x2 119 13 1 12 (c,=11;(a)=1; +mx8+shl4096x2 142 8 1 7 (c,=7; +mx8+shl4096x2 85 28 1 27 (c,=25;(b)=1;(a)=1; +mx8+shl4096x2 138 7 1 6 (c,=6; +mx8+shl4096x2 59 27 1 26 (c,=25;(b)=1; +mx8+shl4096x2 66 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 109 19 1 18 (c,=16;(b)=1;(a)=1; +mx8+shl4096x2 73 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 155 6 1 5 (c,=5; +mx8+shl4096x2 123 12 1 11 (c,=11; +mx8+shl4096x2 70 32 0 none (c,=30;(b)=1;(a)=1; +mx8+shl4096x2 153 6 1 5 (c,=4;(a)=1; +mx8+shl4096x2 87 26 1 25 (c,=25; +mx8+shl4096x2 176 1 1 0 +mx8+shl4096x2 162 5 1 4 (c,=4; +mx8+shl4096x2 164 7 1 6 (c,=5;(b)=1; +mx8+shl4096x2 115 23 1 22 (c,=21;(b)=1; +mx8+shl4096x2 184 1 1 0 +mx8+shl4096x2 151 11 1 10 (c,=9;(b)=1; +mx8+shl4096x2 156 11 1 10 (c,=8;(b)=2; +mx8+shl4096x2 185 1 1 0 +mx8+shl4096x2 190 1 1 0 +mx8+shl4096x2 157 9 1 8 (c,=8; +mx8+shl4096x2 182 3 1 2 (c,=2; +mx8+shl4096x2 158 9 1 8 (c,=7;(c)=1; +mx8+shl4096x2 168 9 1 8 (c,=8; +mx8+shl4096x2 108 27 1 26 (c,=26; +mx8+shl4096x2 152 14 1 13 (c,=12;(b)=1; +mx8+shl4096x2 165 10 1 9 (c,=9; +mx8+shl4096x2 136 17 1 16 (c,=15;(a)=1; +mx8+shl4096x2 150 15 1 14 (c,=14; +mx8+shl4096x2 169 11 1 10 (c,=9;(a)=1; +mx8+shl4096x2 175 9 1 8 (c,=8; +mx8+shl4096x2 205 1 1 0 +mx8+shl4096x2 187 10 1 9 (c,=7;(b)=1;(a)=1; +mx8+shl4096x2 160 13 1 12 (c,=12; +mx8+shl4096x2 200 3 1 2 (c,=2; +mx8+shl4096x2 177 14 1 13 (c,=13; +mx8+shl4096x2 181 9 1 8 (c,=8; +mx8+shl4096x2 178 12 1 11 (c,=10;(b)=1; +mx8+shl4096x2 173 12 1 11 (c,=11; +mx8+shl4096x2 170 11 1 10 (c,=10; +mx8+shl4096x2 172 14 1 13 (c,=12;(a)=1; +mx8+shl4096x2 161 16 1 15 (c,=14;(a)=1; +mx8+shl4096x2 209 1 1 0 +mx8+shl4096x2 122 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl4096x2 154 17 1 16 (c,=16; +mx8+shl4096x2 206 4 1 3 (c,=3; +mx8+shl4096x2 211 3 1 2 (c,=2; +mx8+shl4096x2 212 3 1 2 (c,=2; +mx8+shl4096x2 171 18 1 17 (c,=17; +mx8+shl4096x2 121 32 1 31 (c,=28;(b)=2;(a)=1; +mx8+shl4096x2 159 22 1 21 (c,=19;(b)=2; +mx8+shl4096x2 199 11 1 10 (c,=9;(b)=1; +mx8+shl4096x2 132 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 180 16 1 15 (c,=14;(b)=1; +mx8+shl4096x2 186 17 1 16 (c,=14;(b)=1;(a)=1; +mx8+shl4096x2 198 9 1 8 (c,=7;(b)=1; +mx8+shl4096x2 192 12 1 11 (c,=11; +mx8+shl4096x2 210 5 1 4 (c,=4; +mx8+shl4096x2 194 8 1 7 (c,=7; +mx8+shl4096x2 167 20 1 19 (c,=19; +mx8+shl4096x2 193 11 1 10 (c,=9;(c)=1; +mx8+shl4096x2 126 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 202 9 1 8 (c,=8; +mx8+shl4096x2 217 4 1 3 (c,=3; +mx8+shl4096x2 213 5 1 4 (c,=4; +mx8+shl4096x2 133 32 0 none (c,=29;(b)=2;(a)=1; +mx8+shl4096x2 139 26 1 25 (c,=24;(a)=1; +mx8+shl4096x2 196 13 1 12 (c,=12; +mx8+shl4096x2 223 3 1 2 (c,=2; +mx8+shl4096x2 183 18 1 17 (c,=16;(b)=1; +mx8+shl4096x2 234 2 1 1 (c,=1; +mx8+shl4096x2 163 26 1 25 (c,=22;(b)=2;(a)=1; +mx8+shl4096x2 197 16 1 15 (c,=14;(a)=1; +mx8+shl4096x2 240 2 1 1 (c,=1; +mx8+shl4096x2 174 24 1 23 (c,=20;(b)=2;(a)=1; +mx8+shl4096x2 147 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 224 6 1 5 (c,=5; +mx8+shl4096x2 242 3 1 2 (c,=2; +mx8+shl4096x2 230 6 1 5 (c,=5; +mx8+shl4096x2 143 32 0 none (c,=30;(b)=2; +mx8+shl4096x2 249 2 1 1 (b)=1; +mx8+shl4096x2 189 25 1 24 (c,=23;(b)=1; +mx8+shl4096x2 222 10 1 9 (c,=8;(a)=1; +mx8+shl4096x2 250 2 1 1 (c,=1; +mx8+shl4096x2 248 4 1 3 (c,=3; +mx8+shl4096x2 247 7 1 6 (c,=6; +mx8+shl4096x2 218 11 1 10 (c,=10; +mx8+shl4096x2 225 9 1 8 (c,=8; +mx8+shl4096x2 239 9 1 8 (c,=7;(b)=1; +mx8+shl4096x2 255 3 1 2 (c,=2; +mx8+shl4096x2 235 7 1 6 (c,=6; +mx8+shl4096x2 191 21 1 20 (c,=20; +mx8+shl4096x2 221 11 1 10 (c,=10; +mx8+shl4096x2 233 11 1 10 (c,=10; +mx8+shl4096x2 166 31 1 30 (c,=30; +mx8+shl4096x2 232 11 1 10 (c,=10; +mx8+shl4096x2 179 32 0 none (c,=28;(b)=2;(a)=2; +mx8+shl4096x2 215 18 1 17 (c,=16;(a)=1; +mx8+shl4096x2 244 12 1 11 (c,=11; +mx8+shl4096x2 251 8 1 7 (c,=7; +mx8+shl4096x2 241 13 1 12 (c,=11;(a)=1; +mx8+shl4096x2 188 32 0 none (c,=29;(a)=3; +mx8+shl4096x2 203 25 1 24 (c,=22;(b)=2; +mx8+shl4096x2 227 13 1 12 (c,=12; +mx8+shl4096x2 243 16 1 15 (c,=13;(b)=2; +mx8+shl4096x2 229 16 1 15 (c,=14;(b)=1; +mx8+shl4096x2 231 16 1 15 (c,=14;(b)=1; +mx8+shl4096x2 219 20 1 19 (c,=18;(a)=1; +mx8+shl4096x2 216 21 1 20 (c,=19;(a)=1; +mx8+shl4096x2 195 28 1 27 (c,=25;(b)=2; +mx8+shl4096x2 245 24 1 23 (c,=19;(b)=2;(a)=2; +mx8+shl4096x2 208 27 1 26 (c,=24;(b)=2; +mx8+shl4096x2 252 16 1 15 (c,=15; +mx8+shl4096x2 220 24 1 23 (c,=22;(a)=1; +mx8+shl4096x2 228 22 1 21 (c,=21; +mx8+shl4096x2 204 32 0 none (c,=32; +mx8+shl4096x2 214 30 1 29 (c,=29; +mx8+shl4096x2 207 32 0 none (c,=31;(b)=1; +mx8+shl4096x2 236 27 1 26 (c,=25;(c)=1; +mx8+shl4096x2 201 32 0 none (c,=32; +mx8+shl4096x2 238 32 0 none (c,=26;(b)=4;(a)=2; +mx8+shl4096x2 237 28 1 27 (c,=26;(b)=1; +mx8+shl4096x2 226 31 1 30 (c,=28;(b)=2; +mx8+shl4096x2 254 25 1 24 (c,=23;(b)=1; +mx8+shl4096x2 246 32 0 none (c,=31;(a)=1; +mx8+shl4096x2 253 32 0 none (c,=32; +DONE 2026-10-08T10:09:03Z rows=2816 diff --git a/tools/attack/v6-invention/v6inv-census.sh b/tools/attack/v6-invention/v6inv-census.sh new file mode 100644 index 000000000..ffea9cec9 --- /dev/null +++ b/tools/attack/v6-invention/v6inv-census.sh @@ -0,0 +1,29 @@ +#!/usr/bin/env bash +# Class v6 invention lane: acceptance census of the per-load shadow forms (Counter ASIC 4.0 research 20.2a-close named the +# sound form, one pass of a longer sub-block per load, and never drew it). Each form keeps class v4's work per hash as near as +# the 4,096-instruction cap of the experimental class allows. 64 seeds, each under a drawn era (igneum-era-test/), +# every candidate's verdict through `igneum-pow accept` of the counter-asic-4 crate. Output: one TSV row per (form, seed). +set -u +BIN=${BIN:-/srv/builds/igneum-wt-v6-inv-ca4/igneum-pow/target/release/igneum-pow} +OUT=${OUT:-/srv/builds/v6-invention} +THREADS=${THREADS:-32} +FORMS=${FORMS:-"mx8+sh256x27 mx8+shl256x27 mx8+shl576x12 mx8+shl1152x6 mx8+shl2304x3 mx8+shl256x16 mx8+shl512x8 mx8+shl1024x4 mx8+shl2048x2 mx8+shl4096x1 mx8+shl4096x2"} +SEEDS=${SEEDS:-256} +ERA=${ERA:-none} +if [ "$ERA" = none ]; then ERA_ARG=""; else ERA_ARG="--era igneum-era-test/\$((i % 16))"; fi +mkdir -p "$OUT/logs" +one() { + form=$1; i=$2 + log="$OUT/logs/$ERA-$(echo "$form" | tr '+' '_')-$i.log" + if [ "$ERA" = none ]; then "$BIN" accept --seed "igneum-v6inv/$i" --class "$form"; else "$BIN" accept --seed "igneum-v6inv/$i" --class "$form" --era "igneum-era-test/$((i % 16))"; fi > "$log" 2>&1 + n=$(grep -c '^attempt' "$log") + acc=$(grep -ci 'accepted' "$log") + first=$(grep -im1 'accepted' "$log" | sed 's/:.*//; s/attempt //') + reasons=$(grep 'rejected' "$log" | sed 's/.*rejected, //; s/ .*//' | sort | uniq -c | sort -rn | awk '{printf "%s=%s;", $2, $1}') + printf '%s\t%s\t%s\t%s\t%s\t%s\n' "$form" "$i" "$n" "$acc" "${first:-none}" "$reasons" +} +export -f one; export BIN OUT ERA +for form in $FORMS; do + for i in $(seq 0 $((SEEDS - 1))); do echo "$form $i"; done +done | xargs -P "$THREADS" -n 2 bash -c 'one "$0" "$1"' > "$OUT/census-$ERA.tsv" +echo "DONE $(date -u +%FT%TZ) rows=$(wc -l < "$OUT/census-$ERA.tsv")" >> "$OUT/census-$ERA.tsv" From cb2b8a257800f860bd31c690f92e5d4ce45f6517 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:24:07 +0000 Subject: [PATCH 02/11] Builder programme (8 October 2026): /build, /grants, the Devnet 3 faucet on build-1, docs/build as the source - site/build.html and site/grants.html rendered by site/build.mjs from docs/build/build.md and docs/build/grants.md (the gate's site-only copy keeps the committed pages, as for /bench); site-relative links in the markdown renderer - the nav's fourth group, Build (/build, /faucet, /grants), in the partial, the sheet, the footer, the sitemap and tools/ci/site-nav-check.mjs; the faucet leaves the Mine panel - site/faucet.html is the Devnet 3 faucet: 10 IGN per address per day, 500 a day, chain id 4463, no value, resets without notice; the page posts to https://faucet.igneum.network/api/faucet and shows the balance - infra/build-server/faucet: faucet.mjs (zero dependencies, signs with site/lib/eth.mjs, limiter self-test known-failed first, 100 IGN cap on the amount), the unit, faucet.sh install/status; live on build-1 behind Caddy since 10:16Z, funded 2,000 IGN by the fleet's funder at 10:01Z; first drip 0x8620e9d8 at 10:17Z - docs/build: README, first-contract.md with its test script and the PASS line (24 s end to end through the public RPC and faucet, Foundry 1.8.5, Counter deployed at block 27055), rpc.md read from the node (75 methods probed, served and not served), faucet.md, verify-a-block.md, grants.md - .forgejo/issue_template/grant.md: the grant application template on git.igneum.network Co-Authored-By: Claude Fable 5.1 --- .forgejo/issue_template/grant.md | 26 ++ docs/build/README.md | 16 + docs/build/build.md | 88 +++++ docs/build/faucet.md | 36 ++ docs/build/first-contract-test.sh | 49 +++ docs/build/first-contract.md | 91 +++++ docs/build/grants.md | 46 +++ docs/build/rpc.md | 79 ++++ docs/build/verify-a-block.md | 34 ++ infra/build-server/faucet/faucet.mjs | 171 +++++++++ infra/build-server/faucet/faucet.sh | 62 +++ .../build-server/faucet/igneum-faucet.service | 22 ++ site/404.html | 19 +- site/address.html | 19 +- site/app.html | 19 +- site/bench.html | 41 +- site/block.html | 19 +- site/build.html | 356 ++++++++++++++++++ site/build.mjs | 16 + site/claims.html | 19 +- site/dev-fee.html | 19 +- site/download.html | 27 +- site/evidence.html | 19 +- site/explorer.html | 19 +- site/faucet.html | 68 ++-- site/grants.html | 333 ++++++++++++++++ site/income.html | 19 +- site/index.html | 19 +- site/journey.html | 29 +- site/journey.json | 22 +- site/ledger.html | 25 +- site/litepaper.html | 19 +- site/live.html | 19 +- site/metamask.html | 19 +- site/miner.html | 25 +- site/miners.html | 19 +- site/partials/footer.html | 4 +- site/partials/nav.html | 15 +- site/provenance.html | 19 +- site/randomx.html | 19 +- site/scenes.html | 19 +- site/sitemap.xml | 4 +- site/wallet.html | 19 +- tools/ci/site-nav-check.mjs | 7 +- 44 files changed, 1904 insertions(+), 130 deletions(-) create mode 100644 .forgejo/issue_template/grant.md create mode 100644 docs/build/README.md create mode 100644 docs/build/build.md create mode 100644 docs/build/faucet.md create mode 100755 docs/build/first-contract-test.sh create mode 100644 docs/build/first-contract.md create mode 100644 docs/build/grants.md create mode 100644 docs/build/rpc.md create mode 100644 docs/build/verify-a-block.md create mode 100644 infra/build-server/faucet/faucet.mjs create mode 100755 infra/build-server/faucet/faucet.sh create mode 100644 infra/build-server/faucet/igneum-faucet.service create mode 100644 site/build.html create mode 100644 site/grants.html diff --git a/.forgejo/issue_template/grant.md b/.forgejo/issue_template/grant.md new file mode 100644 index 000000000..59ae0a533 --- /dev/null +++ b/.forgejo/issue_template/grant.md @@ -0,0 +1,26 @@ +--- +name: Grant application +about: Apply for an Igneum grant: tooling, a reference app, infrastructure or research, paid in IGN on delivery +title: "Grant: " +labels: grant +--- + + + +## What you will build + + + +## What done looks like + + + +## Your public work + + + +## How to reach you + + + + diff --git a/docs/build/README.md b/docs/build/README.md new file mode 100644 index 000000000..da070f7a1 --- /dev/null +++ b/docs/build/README.md @@ -0,0 +1,16 @@ +# docs/build: the builder programme + +8 October 2026. These files are the source of the developer pages on igneum.network; `site/build.mjs` renders two of them as pages and the rest are read here. + +| File | Serves | +|---|---| +| `build.md` | [igneum.network/build](https://igneum.network/build): what is different, the chain ids and endpoints, the wallet, the explorer, the faucet, the five-minute contract, the browser verifier | +| `grants.md` | [igneum.network/grants](https://igneum.network/grants): the tiers, what a grant is, how to apply, the review, the honest lines | +| `first-contract.md`, `first-contract-test.sh` | the walkthrough and the script that runs it end to end on Devnet 3 from a build box; the PASS line is the test record | +| `rpc.md` | the JSON-RPC method list as the node serves it, read from a Devnet 3 node, with the probe | +| `faucet.md` | the Devnet 3 faucet: rules, where it runs, how it is funded | +| `verify-a-block.md` | the in-browser checkpoint verifier, twelve lines | + +The faucet service is `infra/build-server/faucet/`. The grant application template is `.forgejo/issue_template/grant.md`. + +Served-text rules (the site audit reads every page before it lands): no em dashes, short sentences, one to three points per block, nothing that reads as an offer, a price or a promise of value; devnet and testnet coins have no value; no amount, price or date is promised. diff --git a/docs/build/build.md b/docs/build/build.md new file mode 100644 index 000000000..5e9e7fd7a --- /dev/null +++ b/docs/build/build.md @@ -0,0 +1,88 @@ +# Build on Igneum + +This file is the source of [igneum.network/build](https://igneum.network/build). The site build renders it as the page. The other files in this directory are the walkthrough, the RPC list, the faucet, the verifier and the grants. + +## What is different + +**Every block is proven.** A chain block carries a zero-knowledge proof of its execution. The miners are the provers: the same cards that find blocks prove them, in shards, and the proof follows the tip by tens of seconds. Your contract runs on a chain whose state is proven, not assumed. + +**A lock in minutes, not an hour of confirmations.** Miners sign a checkpoint every 30 seconds. When two thirds of the mining weight of the last 30 days have signed, the checkpoint is locked. Weight is blocks mined, nothing else. The lock lands in about two minutes. The [litepaper](/litepaper) has the rule. + +**Nothing to stake.** No validator set, no delegation, no slashing, no bonded class above the miners. Finality comes from mining weight alone. Nobody holds a key that the chain depends on. + +**The EVM you already know.** Solidity deploys unchanged. Standard JSON-RPC, EIP-1559 transactions, the chain id in the signature, `cancun` as the EVM version. Gas has two dimensions on Igneum, execution and proving, and the node folds the second into the price it quotes, so `eth_estimateGas` and `eth_gasPrice` work as they do on Ethereum. + +## Networks + +| | Devnet 3 | Testnet | Mainnet | +|---|---|---|---| +| Chain id | 4463 (`0x116f`) | 4462 (`0x116e`) | 4461 (`0x116d`) | +| Network id | `igneum-devnet-3` | `igneum-testnet-1` | not started | +| RPC | `https://rpc.devnet.igneum.network` (a node you run serves `http://127.0.0.1:26790`) | `https://rpc.testnet.igneum.network` (answers; nothing mines there yet, so a transaction waits) | none | +| Coins | no value, resets without notice | no value, resets with notice | not started | +| Symbol, decimals | IGN, 18 | IGN, 18 | IGN, 18 | + +Devnet 3 is where you build today. It is a developer network: it resets without notice and its coins have no value. Its public RPC takes the read methods, `eth_sendRawTransaction` and a wRPC websocket at `/ws`, at 20 requests a second per address. The public testnet exists, its RPC answers, and no blocks are being produced on it until it opens. Mainnet has no date. Devnet 3 answers chain id 4463 until its class v5 floor, then 4464. + +## Endpoints and tools + +- **Wallet.** Any Ethereum wallet. [Add Igneum to MetaMask](/metamask) with one click, or the [Igneum wallet](/wallet). +- **Faucet.** [10 IGN of Devnet 3 coin](/faucet) per address per day. No account. +- **Explorer.** [The explorer](/explorer) shows blocks, the DAG, miners and addresses. The EVM views, transactions and contracts, are being built and link from the same page as they land. +- **Swap.** A swap on Devnet 3 is being built. This page links it when it serves. +- **Source.** [git.igneum.network/igneum-network/igneum](https://git.igneum.network/igneum-network/igneum): the node, the miner, the site, and these pages under `docs/build/`. + +## Your first contract in five minutes + +With [Foundry](https://getfoundry.sh). Tested end to end on Devnet 3 on a build box; the full walkthrough with the expected output is [docs/build/first-contract.md](https://git.igneum.network/igneum-network/igneum/src/branch/master/docs/build/first-contract.md). + +``` +curl -L https://foundry.paradigm.xyz | bash && foundryup +export RPC=https://rpc.devnet.igneum.network +cast wallet new # an address and a private key, for the devnet only +``` + +Paste the address into [the faucet](/faucet). Then: + +``` +export PK=0x... # the private key cast printed +cast balance $(cast wallet address $PK) --rpc-url $RPC --ether +forge init counter && cd counter +forge create src/Counter.sol:Counter --rpc-url $RPC --private-key $PK --broadcast +``` + +`forge create` prints `Deployed to: 0x...`. Call it: + +``` +cast send 0xDEPLOYED "increment()" --rpc-url $RPC --private-key $PK +cast call 0xDEPLOYED "number()(uint256)" --rpc-url $RPC +``` + +The call answers `1`. Paste the transaction hash into [the explorer](/explorer). Hardhat, ethers and viem work the same way: chain id 4463, the RPC above. + +## The RPC the node serves + +Read from a Devnet 3 node, not from a spec. `web3_clientVersion` answers `igneumd/2.1.0/execution-layer-v3`. The full list, served and not served, with the probe that produced it: [docs/build/rpc.md](https://git.igneum.network/igneum-network/igneum/src/branch/master/docs/build/rpc.md). + +- **Served.** `eth_chainId`, `eth_blockNumber`, `eth_getBalance`, `eth_getTransactionCount`, `eth_getCode`, `eth_getStorageAt`, `eth_getBlockByNumber`, `eth_getBlockByHash`, `eth_getTransactionByHash`, `eth_getTransactionReceipt`, `eth_getBlockReceipts`, `eth_getLogs`, `eth_call`, `eth_estimateGas`, `eth_gasPrice`, `eth_maxPriorityFeePerGas`, `eth_feeHistory`, `eth_sendRawTransaction`, `eth_syncing`, `eth_accounts`, `net_version`, `net_peerCount`, `net_listening`, `web3_clientVersion`. +- **Igneum's own.** `igneum_getExecStatus`, `igneum_getProvingStatus`, `igneum_getShardPlan`, `igneum_getProofRecords`, `igneum_getTransactionStatus`, `igneum_estimateGas`, `igneum_getBudgets` and the segment and proof calls. `igneum_estimateGas` returns both gas dimensions and whether a call exceeds the proving limit. +- **Not served.** Filters and subscriptions (`eth_newFilter`, `eth_subscribe`), `txpool_*`, `debug_*`, `trace_*`, `eth_sendTransaction`, `eth_sign`, `eth_getProof`, the uncle calls. Poll `eth_blockNumber` and `eth_getLogs`. Sign on your side. + +## Verify a block in your browser + +The site ships a light client. Your browser fetches the latest certified checkpoint from `/api/checkpoint` and verifies the BLS aggregate signature, the voter weights and the header chain itself, in the tab. Nothing is trusted from the server but the data. The example, in twelve lines, is [docs/build/verify-a-block.md](https://git.igneum.network/igneum-network/igneum/src/branch/master/docs/build/verify-a-block.md); the live run is [verify/test.html](/verify/test.html), genuine and tampered cases side by side. + +``` +import { fetchCheckpoint, verify } from 'https://igneum.network/verify/verify.js'; +const data = await fetchCheckpoint('https://igneum.network/api/checkpoint'); +const r = verify(data); +console.log(r.verified, r.signers, 'of', r.voters, 'voters', r.ms, 'ms'); +``` + +## Where to ask + +- An issue on [the repository](https://git.igneum.network/igneum-network/igneum/issues). +- [Discord](https://discord.gg/igneum), the builders channel. +- [Grants](/grants) for tooling, reference apps, infrastructure and research. + +Devnet and testnet coins have no value. Nothing on this page is an offer to sell anything. diff --git a/docs/build/faucet.md b/docs/build/faucet.md new file mode 100644 index 000000000..0d0120718 --- /dev/null +++ b/docs/build/faucet.md @@ -0,0 +1,36 @@ +# The Devnet 3 faucet + +[igneum.network/faucet](https://igneum.network/faucet) sends 10 IGN of Devnet 3 coin to an address. Once per address per day, once per connection per day. No account. + +## What it is + +- A small Node service on a build box, `infra/build-server/faucet/faucet.mjs`, behind Caddy at `faucet.igneum.network`. The page on igneum.network posts to it. +- It signs a plain transfer with its own key and sends it to the Devnet 3 node on the same box by address (`FAUCET_RPC`), never chosen by chain id: Devnet 3 answers the same chain id as the shared devnet. +- The key lives only in the service's environment file on that box. It is not in the repository and not on the site. + +## The rules, as the code enforces them + +| Rule | Value | +|---|---| +| Amount | 10 IGN per send; the code refuses to start with an amount over the 100 IGN cap | +| Per address | one send per 24 hours | +| Per connection | one send per 24 hours | +| Per day, in total | 500 sends, then "come back tomorrow" | +| What is stored | the address, the connection's IP, the transaction hash and the time, in a file on the box, for the 24-hour window | + +The faucet's balance is refilled from the devnet's funder as it runs down. When it is empty the page says so and sends nothing. + +## Devnet 3 coin + +No value. Not for sale, not redeemable, not a claim on anything. The chain resets without notice and balances do not carry over. Mainnet starts from an empty genesis. + +## Running it + +``` +infra/build-server/faucet/faucet.sh install # dry run: what would be copied and started +infra/build-server/faucet/faucet.sh install --go # copy the service, the unit and the Caddy block; start it +infra/build-server/faucet/faucet.sh status # the unit, the balance, the sends in the last 24 hours +node infra/build-server/faucet/faucet.mjs --self-test # the limiter: known-failed cases first +``` + +The public testnet faucet is a separate thing: `site/api/faucet.mjs` is prepared for it and answers "not open yet" until the testnet starts. diff --git a/docs/build/first-contract-test.sh b/docs/build/first-contract-test.sh new file mode 100755 index 000000000..ee529e092 --- /dev/null +++ b/docs/build/first-contract-test.sh @@ -0,0 +1,49 @@ +#!/usr/bin/env bash +# The five-minute walkthrough (docs/build/first-contract.md), run end to end on a build box against a Devnet 3 node, so the +# page is tested and not described. Runs where Foundry is installed (~/.foundry/bin); asks the faucet for the coins exactly +# as a reader would, deploys Foundry's Counter, calls it, reads the receipt, prints one PASS line with the numbers. +# RPC=http://127.0.0.1:27810 FAUCET=http://127.0.0.1:8790/api/faucet bash docs/build/first-contract-test.sh +# Known-failed first: with RPC pointed at a closed port the script must print FAIL and exit 1 (--self-test). +set -uo pipefail +export PATH="$HOME/.foundry/bin:$PATH" +RPC="${RPC:-https://rpc.devnet.igneum.network}" +FAUCET="${FAUCET:-https://faucet.igneum.network/api/faucet}" +t0=$(date +%s); now() { date -u +%H:%M:%SZ; } +fail() { echo "FAIL $(now): $*"; exit 1; } +if [ "${1:-}" = --self-test ]; then + out=$(RPC=http://127.0.0.1:9 FAUCET=http://127.0.0.1:9/x bash "$0" 2>&1); rc=$? + [ "$rc" = 1 ] && case "$out" in *FAIL*) echo "self-test passed: a closed RPC port reads FAIL, exit 1"; exit 0 ;; esac + echo "self-test failed: rc=$rc out=$out"; exit 1 +fi +command -v forge >/dev/null || fail "forge is not installed" +cid=$(cast chain-id --rpc-url "$RPC" 2>/dev/null) || fail "no chain id from $RPC" +[ "$cid" = 4463 ] || [ "$cid" = 4464 ] || fail "chain id $cid is not Devnet 3" +work=$(mktemp -d); cd "$work" || fail "no scratch dir" +# step 1: a key for the devnet only (never printed) +w=$(cast wallet new 2>&1 | sed 's/\x1b\[[0-9;]*m//g') || fail "cast wallet new" +PK=$(printf '%s\n' "$w" | sed -n 's/^Private key: *//p' | head -1); ME=$(printf '%s\n' "$w" | sed -n 's/^Address: *//p' | head -1) +[ -n "$PK" ] && [ -n "$ME" ] || fail "cast wallet new printed no key" +# step 2: the faucet, as a reader would +f=$(curl -s -m 60 -X POST -H 'content-type: application/json' --data "{\"address\":\"$ME\"}" "$FAUCET") || fail "the faucet did not answer" +case "$f" in *'"ok":true'*) ;; *) fail "the faucet refused: $f" ;; esac +drip=$(printf '%s' "$f" | sed -n 's/.*"tx":"\(0x[0-9a-f]*\)".*/\1/p') +for i in $(seq 1 60); do bal=$(cast balance "$ME" --rpc-url "$RPC" --ether 2>/dev/null); case "$bal" in 10.*|9.*) break ;; esac; sleep 1; done +case "$bal" in 10.*|9.*) ;; *) fail "balance after the faucet: ${bal:-none}" ;; esac +# step 3: deploy Foundry's template counter +forge init counter --no-git >/dev/null 2>&1 || forge init counter >/dev/null 2>&1 || fail "forge init" +cd counter || fail "no counter dir" +out=$(forge create src/Counter.sol:Counter --rpc-url "$RPC" --private-key "$PK" --broadcast 2>&1) || fail "forge create: $(printf '%s' "$out" | tail -3)" +C=$(printf '%s\n' "$out" | sed -n 's/^Deployed to: *//p' | head -1); deployTx=$(printf '%s\n' "$out" | sed -n 's/^Transaction hash: *//p' | head -1) +[ -n "$C" ] || fail "no Deployed to line: $out" +# step 4: call it +cast send "$C" "increment()" --rpc-url "$RPC" --private-key "$PK" >/dev/null 2>&1 || fail "cast send increment" +n=$(cast call "$C" "number()(uint256)" --rpc-url "$RPC" 2>/dev/null); [ "$n" = 1 ] || fail "number() after increment: $n" +sendOut=$(cast send "$C" "setNumber(uint256)" 41 --rpc-url "$RPC" --private-key "$PK" 2>&1) || fail "cast send setNumber" +txh=$(printf '%s\n' "$sendOut" | sed -n 's/^transactionHash *//p' | head -1) +n=$(cast call "$C" "number()(uint256)" --rpc-url "$RPC" 2>/dev/null); [ "$n" = 41 ] || fail "number() after setNumber: $n" +# step 5: the receipt +st=$(cast receipt "${txh:-$deployTx}" --rpc-url "$RPC" 2>/dev/null | sed -n 's/^status *//p' | head -1) +case "$st" in 1*|*success*) ;; *) fail "receipt status: $st" ;; esac +blk=$(cast block-number --rpc-url "$RPC" 2>/dev/null) +echo "PASS $(now): Devnet 3 chain id $cid, faucet drip $drip, deployed Counter at $C (tx $deployTx), increment then setNumber(41) read back 41, receipt status $st, block $blk, $(( $(date +%s) - t0 )) s end to end, Foundry $(forge --version 2>/dev/null | sed -n 's/^forge Version: *//p' | head -1)" +cd / && rm -rf "$work" diff --git a/docs/build/first-contract.md b/docs/build/first-contract.md new file mode 100644 index 000000000..66322567c --- /dev/null +++ b/docs/build/first-contract.md @@ -0,0 +1,91 @@ +# Your first contract on Devnet 3, in five minutes + +With Foundry. Tested end to end on Devnet 3 from a build box on 8 October 2026; the pass line and the exact output are at the end. Hardhat, ethers and viem work the same way: chain id 4463 and the RPC below. + +## 0. What you need + +- Foundry: `curl -L https://foundry.paradigm.xyz | bash && foundryup`. About a minute. +- The RPC. Devnet 3's public endpoint is `https://rpc.devnet.igneum.network`. A node you run yourself serves `http://127.0.0.1:26790`. +- Nothing else. No account, no sign-up. + +``` +export RPC=https://rpc.devnet.igneum.network +cast chain-id --rpc-url $RPC # 4463 +``` + +## 1. A key, for the devnet only + +``` +cast wallet new +``` + +It prints an address and a private key. Keep the key for this walkthrough and nothing else: devnet coins have no value and the chain resets without notice. + +``` +export PK=0x... # the private key cast printed +export ME=$(cast wallet address $PK) +``` + +## 2. Coins from the faucet + +Paste `$ME` into [igneum.network/faucet](https://igneum.network/faucet). It sends 10 IGN and shows the transaction hash. Once per address per day. + +``` +cast balance $ME --rpc-url $RPC --ether # 10.000000000000000000 +``` + +## 3. Deploy + +Foundry's template is a counter. Initialise it and deploy it as it is. + +``` +forge init counter && cd counter +forge create src/Counter.sol:Counter --rpc-url $RPC --private-key $PK --broadcast +``` + +Expected: + +``` +Deployer: 0x... +Deployed to: 0x... +Transaction hash: 0x... +``` + +``` +export C=0x... # the Deployed to address +``` + +## 4. Call it + +``` +cast send $C "increment()" --rpc-url $RPC --private-key $PK +cast call $C "number()(uint256)" --rpc-url $RPC # 1 +cast send $C "setNumber(uint256)" 41 --rpc-url $RPC --private-key $PK +cast call $C "number()(uint256)" --rpc-url $RPC # 41 +``` + +`cast send` waits for the receipt. A block takes about a second. + +## 5. See it + +Paste the transaction hash into [igneum.network/explorer](https://igneum.network/explorer). The receipt is also one call away: + +``` +cast receipt 0xTXHASH --rpc-url $RPC +``` + +## What is different under the hood + +- Gas has two dimensions, execution and proving. The node folds the second into the price it quotes, so `forge` and `cast` estimate and pay as on Ethereum. `igneum_estimateGas` shows both numbers and whether a call exceeds the proving limit. +- Your transaction is in a block within about a second, proven tens of seconds later, and locked by miner signatures in about two minutes. `igneum_getTransactionStatus` reports each stage. +- A transaction signed for another chain id is refused. EIP-155, EIP-1559 and legacy envelopes are accepted. + +## The test record + +Run on a build box against its own Devnet 3 node (the box that also fronts the public RPC and runs the faucet), with Foundry 1.8.5 and a fresh key, through `docs/build/first-contract-test.sh`. The pass line is appended below by the run. + +``` +PASS 10:17:23Z: Devnet 3 chain id 4463, faucet drip 0x8620e9d894484e824e4ac33002946a00e2f75823ea6db0da0ad29f1af142e8f2, deployed Counter at 0x6345265C6Db0b3713eb6645d795d0B52FE0a4201 (tx 0xcf77b4822d51f3c60ecdf6d7dbbe67524d42071f06c76e1cf9b0511d64783574), increment then setNumber(41) read back 41, receipt status 1 (success), block 27055, 24 s end to end, Foundry 1.8.5 +``` + +Through the public endpoints, `https://rpc.devnet.igneum.network` and `https://faucet.igneum.network`, from the box: the first faucet drip and the first reader-path deploy on Devnet 3. diff --git a/docs/build/grants.md b/docs/build/grants.md new file mode 100644 index 000000000..de138be38 --- /dev/null +++ b/docs/build/grants.md @@ -0,0 +1,46 @@ +# Grants + +This file is the source of [igneum.network/grants](https://igneum.network/grants). + +## What a grant is + +Work paid in IGN on delivery. You propose a piece of work, it is accepted with a written definition of done, you build it, it runs on the public testnet, and it is paid when it does. Not a salary, not an advance, not an investment. + +The money is the dev fee fund: the IGN that the Ember dev fee collects. Ember, the official miner, takes an optional 1% of a miner's rewards, in full view and off with one flag; that fee goes to Igneum Labs, the company that ships the software. The protocol itself carries no fee, no fund and no allocation, and no grant is paid from emission. [The dev fee](/dev-fee) has the mechanism. + +## The tiers + +| Tier | What fits | +|---|---| +| Tooling | SDK bindings, indexers, a Hardhat or Foundry plugin for the two gas dimensions, verification tooling, a light client in another language | +| Reference apps | A token, a swap, a registry, a wallet integration, an app that uses `igneum_getTransactionStatus` and the lock the way it is meant to be used | +| Infrastructure | RPC providers, archive nodes, seed nodes in new regions, pool software, an explorer back end | +| Research | The lottery hash, the finality rule, the proving layer, the fee model; attacks on the public test vectors; measurements the project does not have | + +A grant is sized by the work in front of it, not by a table. Two grants in the same tier can differ. + +## How to apply + +Open an issue on [git.igneum.network/igneum-network/igneum](https://git.igneum.network/igneum-network/igneum/issues/new?template=.forgejo%2Fissue_template%2Fgrant.md) and pick the Grant template. It asks for: + +1. What you will build, in a paragraph, and which tier it is. +2. What done looks like: what runs where, what a reviewer can click or call to see it working on the public testnet. +3. Your public work: a repository, a package, a paper, a deployed thing. +4. How you want to be reached. + +A short issue is fine. The definition of done is the part that matters. + +## The review + +- Every Friday. Each open application gets one of three answers inside seven days: accepted with a definition of done, questions, or no with the reason. +- Accepted work is tracked in its issue. The reviewer and the builder agree the definition of done there before any work starts. +- Delivery is reviewed on the public testnet first. Payment follows the review, in the issue, in the open. + +## The honest lines + +- Devnet and testnet coins have no value. A grant delivered before mainnet is paid when mainnet IGN exists, not in devnet or testnet coin. +- No amount, price or date is promised. The fund is what the dev fee collects, and it is zero until there is mining with value. +- A grant is for work delivered, never for a user count, a listing, a post or a referral. +- Igneum Labs may decline any application and may close the programme; what has been accepted and delivered is still paid. + +Not legal advice. diff --git a/docs/build/rpc.md b/docs/build/rpc.md new file mode 100644 index 000000000..8f46d1ef1 --- /dev/null +++ b/docs/build/rpc.md @@ -0,0 +1,79 @@ +# The JSON-RPC a Devnet 3 node serves + +Read from the node, not from a spec: every method below was sent to a Devnet 3 node on 8 October 2026 (`web3_clientVersion` answered `igneumd/2.1.0/execution-layer-v3`, `eth_chainId` `0x116f`, block 26,666) and sorted by what came back. A method the node does not know answers JSON-RPC error `-32601`. The probe is at the end; run it against your own node to refresh this file. + +Transport: HTTP POST, JSON-RPC 2.0, one request per call, no batches tested. The public endpoint is `https://rpc.devnet.igneum.network`; a node you run serves `http://127.0.0.1:26790`. The DAG side of the node (blocks, the mempool, the vote table) speaks the Kaspa-style gRPC and wRPC on their own ports; the explorer and the observer use those, a contract developer needs only what is here. + +## Served: the Ethereum set + +| Method | Note | +|---|---| +| `web3_clientVersion` | `igneumd//execution-layer-v3` | +| `net_version` | the chain id as a decimal string, `"4463"` | +| `net_listening`, `net_peerCount` | | +| `eth_chainId` | `0x116f` (4463) on Devnet 3; `0x1170` after its class v5 floor | +| `eth_blockNumber` | the executed chain tip | +| `eth_syncing` | `false` when the executor is at the tip | +| `eth_mining` | `false` from the RPC's point of view: mining is the miner's, not the node's | +| `eth_accounts` | always `[]`: the node holds no keys | +| `eth_protocolVersion` | `0x41` | +| `eth_gasPrice`, `eth_maxPriorityFeePerGas`, `eth_feeHistory` | EIP-1559 pricing; the proving dimension is folded into the quoted price | +| `eth_getBalance`, `eth_getTransactionCount`, `eth_getCode`, `eth_getStorageAt` | by block tag or number | +| `eth_getBlockByNumber`, `eth_getBlockByHash` | the EVM view of a chain block; `null` for an unknown hash | +| `eth_getBlockTransactionCountByNumber` | | +| `eth_getTransactionByHash`, `eth_getTransactionByBlockNumberAndIndex` | | +| `eth_getTransactionReceipt`, `eth_getBlockReceipts` | | +| `eth_getLogs` | by block range, address and topics | +| `eth_call`, `eth_estimateGas` | as on Ethereum | +| `eth_sendRawTransaction` | a signed EIP-155, EIP-1559 or legacy envelope; the chain id must match | + +## Served: Igneum's own + +| Method | What the answer carries (from the probe) | +|---|---| +| `igneum_getExecStatus` | the executed tip, a continuity break if any, what the executor is blocked on | +| `igneum_getProvingStatus` | whether proving is active, its activation height, assignees per shard, the dust rule | +| `igneum_getShardPlan` | a block's shard plan: the DAA score, eligible keys, the epoch seed, the assignments | +| `igneum_getProofRecords` | the proof records a block carries and claims | +| `igneum_getTransactionStatus` | per transaction: in the mempool, included in, executed, locked | +| `igneum_estimateGas` | both gas dimensions, the base fee, and `exceedsProvingLimit` | +| `igneum_getBudgets` | the proving budgets: backlog depth, the base fee, chain blocks | +| `igneum_getAssignedShards` | the shards assigned to this node's prover | +| `igneum_getSegment`, `igneum_getSegmentRecords`, `igneum_getSegmentStatement` | a segment's executed blocks, records and statement | +| `igneum_getSegmentProofBytes`, `igneum_getProofBytes` | the proof bytes for a key hash (`keyHash` is required) | +| `igneum_exportSegments` | a range of segments with their accounts | +| `igneum_exportExecSnapshot` | writes a snapshot to a path on the node's own disk | +| `igneum_submitProofRecord`, `igneum_submitSegmentRecord` | the prover's submissions; a record is required | + +## Not served + +Each of these answered `-32601` on 8 October 2026. Where a tool wants one, the note says what to do instead. + +| Method | Instead | +|---|---| +| `eth_newFilter`, `eth_newBlockFilter`, `eth_newPendingTransactionFilter`, `eth_getFilterChanges`, `eth_getFilterLogs`, `eth_uninstallFilter` | poll `eth_blockNumber` and `eth_getLogs` | +| `eth_subscribe`, `eth_unsubscribe` | no WebSocket subscriptions; poll | +| `eth_sendTransaction`, `eth_sign`, `eth_signTransaction` | the node holds no keys; sign on your side and use `eth_sendRawTransaction` | +| `eth_getProof` | not yet | +| `eth_getTransactionByBlockHashAndIndex`, `eth_getBlockTransactionCountByHash` | use the by-number forms | +| `eth_getUncleByBlockHashAndIndex`, `eth_getUncleByBlockNumberAndIndex`, `eth_getUncleCountByBlockHash`, `eth_getUncleCountByBlockNumber` | there are no uncles; the DAG's merged blocks are not EVM blocks | +| `eth_createAccessList`, `eth_simulateV1`, `eth_blobBaseFee` | not yet; no blobs | +| `eth_coinbase`, `eth_hashrate` | the miner's, not the node's | +| `txpool_content`, `txpool_status` | `igneum_getTransactionStatus` for one transaction | +| `debug_traceTransaction`, `debug_traceBlockByNumber`, `trace_block` | no tracing yet | +| `web3_sha3` | hash on your side | + +## The probe + +Every method with a harmless argument; the verdict is `served`, `not-found` (`-32601`) or `error` (the node knows the method and refused the argument, which counts as served). + +``` +URL=http://127.0.0.1:26790 +call() { curl -s -X POST -H 'content-type: application/json' \ + --data "{\"jsonrpc\":\"2.0\",\"id\":1,\"method\":\"$1\",\"params\":${2:-[]}}" "$URL"; } +for m in web3_clientVersion eth_chainId eth_blockNumber eth_newFilter eth_subscribe; do + printf '%-32s %s\n' "$m" "$(call $m | cut -c1-80)" +done +``` + +Devnet 3 resets without notice and its coins have no value. diff --git a/docs/build/verify-a-block.md b/docs/build/verify-a-block.md new file mode 100644 index 000000000..fcb1ac997 --- /dev/null +++ b/docs/build/verify-a-block.md @@ -0,0 +1,34 @@ +# Verify a block in your browser + +Igneum's finality is a certificate: miners sign a checkpoint every 30 seconds, and when two thirds of the 30-day mining weight have signed, it is locked. A browser can check that certificate by itself. The site ships the verifier: `site/verify/core.js` does the work, `site/verify/verify.js` fetches the data and calls it. + +## Twelve lines + +``` + +``` + +## What is checked, in the tab + +1. The header chain from the previous locked checkpoint to this one: each header's hash is recomputed and each links to its parent. +2. The voter table: each voter's key hash, and the weights the bitmap selects. +3. The BLS aggregate signature over the checkpoint message, against the aggregated public keys of the signers, and that the signed weight reaches two thirds of the total. + +Nothing is trusted from the server but the data itself. Change one bit of the signature, drop one signer from the bitmap, alter a header's nonce, and `verify` says `false` with the reason. The live run of exactly those cases is [igneum.network/verify/test.html](https://igneum.network/verify/test.html). + +## The data + +`GET /api/checkpoint` returns the latest certified checkpoint: the certificate as carried in a block, the voter list with public keys and weights, and the selected-chain headers from the previous lock. `?source=test` returns the finality test network's instead. Libraries, pinned: BLAKE2b from `@noble/hashes` 2.4.0 and BLS12-381 from `@noble/curves` 2.4.0, pure JavaScript. + +## From a node + +The same certificate is in the block that carries it, and `igneum_getProofRecords` returns a block's records. A light client that reads blocks from a node instead of the site's API verifies the same way; `core.js` has no dependency on the site. diff --git a/infra/build-server/faucet/faucet.mjs b/infra/build-server/faucet/faucet.mjs new file mode 100644 index 000000000..332f84393 --- /dev/null +++ b/infra/build-server/faucet/faucet.mjs @@ -0,0 +1,171 @@ +// The Devnet 3 faucet (the builder programme, 8 October 2026). A Node service behind Caddy at faucet.igneum.network on a build box: +// POST /api/faucet {address} sends AMOUNT_IGN of Devnet 3 coin to the address and answers {ok, tx, amount, chainId, to} +// GET /api/faucet the state: network, chain id, amount, the faucet's balance in IGN, sends in the last 24 hours +// Rules, enforced here and nowhere else: one send per address per WINDOW_HOURS, one per connection (IP) per WINDOW_HOURS, +// DAILY_MAX sends per WINDOW_HOURS in total, and AMOUNT_IGN under the HARD_CAP_IGN the fleet lane set on the faucet's own sends +// (the service refuses to start otherwise). Sends are serialised so the nonce is read once per send. The record of sends is an +// append-only JSONL file next to the service (FAUCET_STATE, default ./grants.jsonl); the window is read from it at start. +// Environment (EnvironmentFile=/srv/faucet/env on the box, mode 600; the key is nowhere else): FAUCET_KEY (0x + 64 hex), +// FAUCET_RPC (the Devnet 3 node by address, never chosen by chain id: Devnet 3 answers the same id as the shared devnet), +// FAUCET_CHAIN_ID (4463), FAUCET_PORT (8790), FAUCET_ORIGIN (the page's origin for CORS, https://igneum.network). +// Signing: site/lib/eth.mjs, copied next to this file by faucet.sh (zero dependencies). +// node faucet.mjs the service +// node faucet.mjs --self-test the limiter and the handler against a fake node: known-failed cases first +import { createServer } from 'node:http'; +import { readFileSync, appendFileSync, existsSync } from 'node:fs'; +import { dirname, join } from 'node:path'; +import { fileURLToPath } from 'node:url'; + +const here = dirname(fileURLToPath(import.meta.url)); +const { signTransaction, addressOf, isAddress, toWei } = await import(join(here, 'eth.mjs')); + +export const AMOUNT_IGN = 10; +export const HARD_CAP_IGN = 100; // the fleet lane's cap on the faucet's own sends (main's rule, 8 October 2026) +export const WINDOW_HOURS = 24; +export const DAILY_MAX = 500; +const WINDOW_MS = WINDOW_HOURS * 3600 * 1000; + +export function limiter(now = () => Date.now()) { + // in memory, fed from the JSONL at start; each row {t, address, ip, tx} + const rows = []; + const prune = () => { const cut = now() - WINDOW_MS; while (rows.length && rows[0].t < cut) rows.shift(); }; + return { + load(row) { rows.push(row); }, + check(address, ip) { + prune(); + if (rows.some(r => r.address === address)) return `This address had its ${AMOUNT_IGN} IGN in the last ${WINDOW_HOURS} hours. Come back tomorrow.`; + if (rows.some(r => r.ip === ip)) return `This connection had its ${AMOUNT_IGN} IGN in the last ${WINDOW_HOURS} hours. Come back tomorrow.`; + if (rows.length >= DAILY_MAX) return `The faucet has sent its ${DAILY_MAX} for today. Come back tomorrow.`; + return null; + }, + add(row) { rows.push(row); }, + drop(row) { const i = rows.indexOf(row); if (i >= 0) rows.splice(i, 1); }, + count() { prune(); return rows.length; }, + }; +} + +export function rpcClient(url, fetchImpl = fetch) { + let id = 0; + return async (method, params = []) => { + const r = await fetchImpl(url, { method: 'POST', headers: { 'Content-Type': 'application/json' }, body: JSON.stringify({ jsonrpc: '2.0', id: ++id, method, params }) }); + const j = await r.json(); + if (j.error) throw new Error(`${method}: ${j.error.message || JSON.stringify(j.error)}`); + return j.result; + }; +} + +const ignOf = wei => (Number(BigInt(wei) / 10n ** 12n) / 1e6).toFixed(6); + +export function createHandler({ env = process.env, rpc, lim, record = () => {}, now = () => Date.now() } = {}) { + const key = env.FAUCET_KEY || '', rpcUrl = env.FAUCET_RPC || ''; + const chainId = Number(env.FAUCET_CHAIN_ID || 4463); + const origin = env.FAUCET_ORIGIN || 'https://igneum.network'; + if (AMOUNT_IGN > HARD_CAP_IGN) throw new Error(`AMOUNT_IGN ${AMOUNT_IGN} is over the ${HARD_CAP_IGN} IGN cap`); + if (!/^0x[0-9a-fA-F]{64}$/.test(key) || !rpcUrl) throw new Error('FAUCET_KEY (0x + 64 hex) and FAUCET_RPC are required'); + const from = addressOf(key); + rpc = rpc || rpcClient(rpcUrl); + lim = lim || limiter(now); + let chain = Promise.resolve(); // sends one after another: one nonce read per send + const json = (res, status, body) => { res.writeHead(status, { 'Content-Type': 'application/json', 'Cache-Control': 'no-store' }); res.end(JSON.stringify(body)); }; + const cors = (req, res) => { + const o = req.headers.origin || ''; + const allowed = o === origin || /^http:\/\/(127\.0\.0\.1|localhost):\d+$/.test(o); + res.setHeader('Access-Control-Allow-Origin', allowed ? o : origin); + res.setHeader('Vary', 'Origin'); + res.setHeader('Access-Control-Allow-Methods', 'GET, POST, OPTIONS'); + res.setHeader('Access-Control-Allow-Headers', 'Content-Type'); + }; + const clientIp = req => { const fwd = req.headers['x-forwarded-for']; const first = (Array.isArray(fwd) ? fwd[0] : fwd || '').split(',')[0].trim(); return first || String(req.headers['x-real-ip'] || req.socket?.remoteAddress || '').trim() || 'unknown'; }; + const readBody = req => new Promise((resolve, reject) => { const c = []; let n = 0; req.on('data', d => { n += d.length; if (n > 4096) { reject(new Error('too large')); req.destroy(); } else c.push(d); }); req.on('end', () => { try { resolve(JSON.parse(Buffer.concat(c).toString('utf8') || '{}')); } catch (e) { reject(e); } }); req.on('error', reject); }); + return async function handler(req, res) { + cors(req, res); + const path = (req.url || '/').split('?')[0]; + if (req.method === 'OPTIONS') { res.writeHead(204); return res.end(); } + if (path !== '/api/faucet' && path !== '/api/faucet/') return json(res, 404, { ok: false, error: 'not found' }); + if (req.method === 'GET') { + let balance = null; + try { balance = ignOf(await rpc('eth_getBalance', [from, 'latest'])); } catch { /* the node is the status */ } + return json(res, 200, { ok: true, network: 'igneum-devnet-3', chainId, amount: String(AMOUNT_IGN), window_hours: WINDOW_HOURS, daily_max: DAILY_MAX, address: from, balance_ign: balance, sends_24h: lim.count(), funded: balance !== null && Number(balance) >= AMOUNT_IGN }); + } + if (req.method !== 'POST') { res.setHeader('Allow', 'GET, POST, OPTIONS'); return json(res, 405, { ok: false, error: 'method not allowed' }); } + let body; + try { body = await readBody(req); } catch { return json(res, 400, { ok: false, error: 'bad json' }); } + const address = String(body.address || '').trim(); + if (!isAddress(address)) return json(res, 400, { ok: false, error: 'That is not an address. It is 0x followed by 40 hex characters.' }); + const to = address.toLowerCase(), ip = clientIp(req); + const refused = lim.check(to, ip); + if (refused) return json(res, 429, { ok: false, error: refused }); + const row = { t: now(), address: to, ip, tx: null }; + lim.add(row); // reserved before the send, so two asks in the same second cannot both pass + const result = chain.then(async () => { + const [nonceHex, block, tipHex, balHex] = await Promise.all([ + rpc('eth_getTransactionCount', [from, 'pending']), + rpc('eth_getBlockByNumber', ['latest', false]), + rpc('eth_maxPriorityFeePerGas').catch(() => '0x3b9aca00'), + rpc('eth_getBalance', [from, 'latest']), + ]); + const value = toWei(AMOUNT_IGN); + if (BigInt(balHex) < value * 2n) throw Object.assign(new Error('The faucet is empty right now. It is being refilled; try again in an hour.'), { status: 503 }); + const baseFee = BigInt(block?.baseFeePerGas || '0x3b9aca00'), tip = BigInt(tipHex || '0x3b9aca00'); + let gas = 21000n; + try { gas = BigInt(await rpc('eth_estimateGas', [{ from, to, value: '0x' + value.toString(16) }])); } catch { /* the plain-transfer default */ } + const tx = { chainId, nonce: BigInt(nonceHex), maxPriorityFeePerGas: tip, maxFeePerGas: baseFee * 2n + tip, gas, to, value, data: '0x' }; + const signed = signTransaction(tx, key); + return rpc('eth_sendRawTransaction', [signed.raw]); + }); + chain = result.catch(() => {}); + try { + const hash = await result; + row.tx = hash; record(row); + return json(res, 200, { ok: true, tx: hash, amount: String(AMOUNT_IGN), chainId, to }); + } catch (e) { + lim.drop(row); + return json(res, e.status || 502, { ok: false, error: e.status ? e.message : `The node did not take the transaction: ${String(e.message || e).slice(0, 200)}` }); + } + }; +} + +if (process.argv.includes('--self-test')) { + // known-failed first: a fake node that answers every read and refuses every send must leave the limiter empty and answer 502 + let t = 1_000_000; const now = () => t; + const fakeNode = (sendOk = true) => async (m, p) => ({ + eth_getTransactionCount: '0x1', eth_getBlockByNumber: { baseFeePerGas: '0x174876e800' }, eth_maxPriorityFeePerGas: '0x3b9aca00', + eth_getBalance: '0x' + (10n ** 21n).toString(16), eth_estimateGas: '0x5208', + eth_sendRawTransaction: sendOk ? '0x' + 'ab'.repeat(32) : (() => { throw new Error('refused'); })(), + })[m]; + const call = async (h, method, body, ip = '1.1.1.1') => new Promise(resolve => { + const chunks = body === undefined ? [] : [Buffer.from(JSON.stringify(body))]; + const req = { method, url: '/api/faucet', headers: { 'x-forwarded-for': ip, origin: 'https://igneum.network' }, socket: {}, on(ev, cb) { if (ev === 'data') for (const c of chunks) cb(c); if (ev === 'end') cb(); return this; } }; + const res = { h: {}, setHeader(k, v) { this.h[k] = v; }, writeHead(s, hh) { this.status = s; Object.assign(this.h, hh || {}); }, end(b) { resolve({ status: this.status, body: b ? JSON.parse(b) : null }); } }; + h(req, res); + }); + const env = { FAUCET_KEY: '0x' + '11'.repeat(32), FAUCET_RPC: 'http://fake', FAUCET_CHAIN_ID: '4463' }; + const A = '0x' + 'a1'.repeat(20), B = '0x' + 'b2'.repeat(20); + let fails = 0; const expect = (c, msg) => { if (!c) { console.error('self-test failed: ' + msg); fails++; } }; + { const lim = limiter(now); const h = createHandler({ env, rpc: fakeNode(false), lim, now }); const r = await call(h, 'POST', { address: A }); expect(r.status === 502 && lim.count() === 0, `a refused send must answer 502 and reserve nothing (got ${r.status}, ${lim.count()})`); } + { const lim = limiter(now); const h = createHandler({ env, rpc: fakeNode(), lim, now }); const r = await call(h, 'POST', { address: 'not-an-address' }); expect(r.status === 400, 'a bad address must answer 400'); } + { const lim = limiter(now); const recorded = []; const h = createHandler({ env, rpc: fakeNode(), lim, record: r => recorded.push(r), now }); + const r1 = await call(h, 'POST', { address: A }); expect(r1.status === 200 && r1.body.ok && r1.body.tx.startsWith('0x'), 'the first ask sends'); + expect(recorded.length === 1 && recorded[0].tx === r1.body.tx, 'the send is recorded with its hash'); + const r2 = await call(h, 'POST', { address: A }); expect(r2.status === 429 && /address/.test(r2.body.error), 'the same address inside the window is refused'); + const r3 = await call(h, 'POST', { address: B }); expect(r3.status === 429 && /connection/.test(r3.body.error), 'the same connection inside the window is refused'); + const r4 = await call(h, 'POST', { address: B }, '2.2.2.2'); expect(r4.status === 200, 'another address from another connection sends'); + t += WINDOW_MS + 1; const r5 = await call(h, 'POST', { address: A }); expect(r5.status === 200, 'after the window the address sends again'); + const s = await call(h, 'GET'); expect(s.status === 200 && s.body.network === 'igneum-devnet-3' && s.body.sends_24h === 1 && s.body.funded === true, `the status carries the network and the window count (got ${JSON.stringify(s.body)})`); + for (let i = 0; i < DAILY_MAX - 1; i++) lim.add({ t: now(), address: '0x' + String(i).padStart(40, '0'), ip: 'x' + i, tx: '0x' }); + const r6 = await call(h, 'POST', { address: '0x' + 'c3'.repeat(20) }, '3.3.3.3'); expect(r6.status === 429 && /today/.test(r6.body.error), 'the daily total refuses the next ask'); } + { let threw = false; try { createHandler({ env: { ...env, FAUCET_KEY: 'bad' }, rpc: fakeNode(), now }); } catch { threw = true; } expect(threw, 'a bad key must refuse to start'); } + expect(AMOUNT_IGN <= HARD_CAP_IGN, 'the amount is under the cap'); + if (fails) process.exit(1); + console.log(`self-test passed: a refused send reserves nothing (502), a bad address 400, the same address and the same connection are refused inside ${WINDOW_HOURS} h (429), another pair sends, the window expires, the status counts, the ${DAILY_MAX}-a-day total refuses, a bad key refuses to start, ${AMOUNT_IGN} IGN is under the ${HARD_CAP_IGN} IGN cap`); + process.exit(0); +} + +if (process.argv[1] && fileURLToPath(import.meta.url) === process.argv[1] && !process.argv.includes('--self-test')) { + const STATE = process.env.FAUCET_STATE || join(here, 'grants.jsonl'); + const lim = limiter(); + if (existsSync(STATE)) { const cut = Date.now() - WINDOW_MS; for (const l of readFileSync(STATE, 'utf8').split('\n')) { if (!l) continue; try { const r = JSON.parse(l); if (r.t >= cut && r.tx) lim.load(r); } catch { /* a torn line */ } } } + const handler = createHandler({ lim, record: row => appendFileSync(STATE, JSON.stringify(row) + '\n') }); + const port = Number(process.env.FAUCET_PORT || 8790); + createServer((req, res) => { handler(req, res).catch(e => { try { res.writeHead(500, { 'Content-Type': 'application/json' }); res.end(JSON.stringify({ ok: false, error: String(e.message || e).slice(0, 200) })); } catch { /* closed */ } }); }).listen(port, '127.0.0.1', () => console.log(`${new Date().toISOString()} faucet on 127.0.0.1:${port}, ${AMOUNT_IGN} IGN per send, ${lim.count()} sends in the window, from ${addressOf(process.env.FAUCET_KEY)}`)); +} diff --git a/infra/build-server/faucet/faucet.sh b/infra/build-server/faucet/faucet.sh new file mode 100755 index 000000000..bd162e6bc --- /dev/null +++ b/infra/build-server/faucet/faucet.sh @@ -0,0 +1,62 @@ +#!/usr/bin/env bash +# The Devnet 3 faucet on a build box (the builder programme, 8 October 2026). Dry run by default, --go executes. +# infra/build-server/faucet/faucet.sh install [--go] copy faucet.mjs and site/lib/eth.mjs to /srv/faucet (the build user's), the unit +# to /etc/systemd/system, the Caddy block for faucet.igneum.network (validate, reload), +# enable and start the unit, read back GET /api/faucet through the loopback +# infra/build-server/faucet/faucet.sh status the unit, the loopback status (balance, sends in the window), the Caddy host +# infra/build-server/faucet/faucet.sh self-test node faucet.mjs --self-test on the box +# /srv/faucet/env (mode 600, the build user's) is written by hand on the box and never by this script: FAUCET_KEY, FAUCET_RPC +# (the Devnet 3 node by address), FAUCET_CHAIN_ID, FAUCET_PORT, FAUCET_ORIGIN. The key is nowhere else. +set -euo pipefail +HERE=$(cd "$(dirname "$0")" && pwd); ROOT=$(cd "$HERE/../../.." && pwd) +KEY="${IGNEUM_BUILD_KEY:-$HOME/.ssh/igneum_ed25519}"; HOST=$(head -1 "${IGNEUM_BUILD_HOST_FILE:-$HOME/.config/igneum/build-server}" | tr -d '[:space:]') +IP="${HOST#*@}" +SSHB=(ssh -i "$KEY" -o BatchMode=yes -o ConnectTimeout=15 "$HOST") +SSHR=(ssh -i "$KEY" -o BatchMode=yes -o ConnectTimeout=15 "root@$IP") +say() { echo "$(TZ=UTC date '+%H:%M:%SZ') faucet: $*" >&2; } +mode="${1:-}"; shift || true; GO=0; [ "${1:-}" = --go ] && GO=1 +FAUCET_HOST="${FAUCET_HOST:-faucet.igneum.network}"; PORT="${FAUCET_PORT:-8790}" +caddy_block() { cat < $HOST:/srv/faucet/; igneum-faucet.service -> root@$IP:/etc/systemd/system/; append to /etc/caddy/Caddyfile unless $FAUCET_HOST is there:"; caddy_block; say "DRY: systemctl daemon-reload, enable --now igneum-faucet; curl 127.0.0.1:$PORT/api/faucet"; exit 0 + fi + "${SSHB[@]}" 'test -s /srv/faucet/env' || { say "/srv/faucet/env is missing on the box: write it by hand first (FAUCET_KEY, FAUCET_RPC, FAUCET_CHAIN_ID, FAUCET_PORT, FAUCET_ORIGIN)"; exit 1; } + scp -q -i "$KEY" "$HERE/faucet.mjs" "$ROOT/site/lib/eth.mjs" "$HOST:/srv/faucet/" + "${SSHB[@]}" 'cd /srv/faucet && node faucet.mjs --self-test' || { say "the self-test failed on the box; nothing started"; exit 1; } + scp -q -i "$KEY" "$HERE/igneum-faucet.service" "root@$IP:/etc/systemd/system/igneum-faucet.service" + "${SSHR[@]}" bash -s -- "$FAUCET_HOST" "$(caddy_block | base64 | tr -d '\n')" <<'REMOTE' +set -euo pipefail; host="$1"; block="$(printf '%s' "$2" | base64 -d)" +if ! grep -q "^$host {" /etc/caddy/Caddyfile; then + cp /etc/caddy/Caddyfile "/etc/caddy/Caddyfile.bak-$(date -u +%Y%m%d%H%M%S)" + printf '%s\n' "$block" >> /etc/caddy/Caddyfile + caddy validate --config /etc/caddy/Caddyfile --adapter caddyfile >/dev/null + systemctl reload caddy; echo "caddy: $host block appended and reloaded" +else echo "caddy: $host block already present"; fi +systemctl daemon-reload; systemctl enable igneum-faucet >/dev/null 2>&1; systemctl restart igneum-faucet; sleep 3; systemctl is-active igneum-faucet; journalctl -u igneum-faucet --since "-30 s" --no-pager | tail -2 | cut -c1-160 +REMOTE + "${SSHB[@]}" "curl -s -m 10 http://127.0.0.1:$PORT/api/faucet; echo" + ;; + status) + "${SSHR[@]}" "systemctl is-active igneum-faucet; journalctl -u igneum-faucet --since '-10 min' --no-pager | tail -5 | cut -c1-160; grep -c '^$FAUCET_HOST {' /etc/caddy/Caddyfile" + "${SSHB[@]}" "curl -s -m 10 http://127.0.0.1:$PORT/api/faucet; echo; wc -l /srv/faucet/grants.jsonl 2>/dev/null || echo 'no sends yet'" + ;; + self-test) "${SSHB[@]}" 'cd /srv/faucet && node faucet.mjs --self-test' ;; + *) sed -n '2,10p' "$0" | sed 's/^# \{0,1\}//'; exit 2 ;; +esac diff --git a/infra/build-server/faucet/igneum-faucet.service b/infra/build-server/faucet/igneum-faucet.service new file mode 100644 index 000000000..c7adf50b8 --- /dev/null +++ b/infra/build-server/faucet/igneum-faucet.service @@ -0,0 +1,22 @@ +[Unit] +Description=Igneum Devnet 3 faucet (infra/build-server/faucet/faucet.mjs), 127.0.0.1:8790 behind Caddy at faucet.igneum.network +After=network-online.target +Wants=network-online.target + +[Service] +User=build +Group=build +WorkingDirectory=/srv/faucet +EnvironmentFile=/srv/faucet/env +Environment=FAUCET_STATE=/srv/faucet/grants.jsonl +ExecStart=/usr/local/bin/node /srv/faucet/faucet.mjs +Restart=always +RestartSec=5 +Nice=5 +NoNewPrivileges=true +ProtectSystem=strict +ReadWritePaths=/srv/faucet +PrivateTmp=true + +[Install] +WantedBy=multi-user.target diff --git a/site/404.html b/site/404.html index 4020c5c81..6cb434aff 100644 --- a/site/404.html +++ b/site/404.html @@ -60,6 +60,7 @@ main{flex:1}
+
@@ -77,7 +78,6 @@ main{flex:1} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -100,6 +100,13 @@ main{flex:1} Built on the shouldersEvery borrowed part, credited. +
Network
@@ -129,6 +135,11 @@ main{flex:1} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -218,7 +229,7 @@ main{flex:1} The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -233,6 +244,8 @@ main{flex:1}

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/address.html b/site/address.html index 1b21eab43..c2f48532e 100644 --- a/site/address.html +++ b/site/address.html @@ -108,6 +108,7 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin
+
@@ -125,7 +126,6 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -148,6 +148,13 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -177,6 +183,11 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -273,7 +284,7 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -288,6 +299,8 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/app.html b/site/app.html index 143257d2b..66b1de0ea 100644 --- a/site/app.html +++ b/site/app.html @@ -82,6 +82,7 @@
+
@@ -99,7 +100,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -122,6 +122,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -151,6 +157,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -470,7 +481,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -485,6 +496,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/bench.html b/site/bench.html index 3559f6c31..67ea3ade2 100644 --- a/site/bench.html +++ b/site/bench.html @@ -87,6 +87,7 @@ table{min-width:560px}
+
@@ -104,7 +105,6 @@ table{min-width:560px} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -127,6 +127,13 @@ table{min-width:560px} Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -156,6 +162,11 @@ table{min-width:560px} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -213,7 +224,7 @@ table{min-width:560px}
Igneum/Engineering log
-
96 entries, newest at the bottom
+
98 entries, newest at the bottom

Engineering log

Every measurement the project has made, newest at the bottom, written by the people and agents who ran it, with the commands and hardware. Prototype numbers are not mining numbers and say so.

@@ -221,7 +232,7 @@ table{min-width:560px}
- +

Igneum bench log

Append-only. Every number here was measured on the machine named, on the date given.

@@ -962,7 +973,23 @@ table{min-width:560px}

Rented Vast instance 54613164, Intel Core i7-9700K at 4,170 MHz as read, one core, the box-built Linux igneum-pow (sha256 6d286783...), bench --seed igneum-genesis --day 2026-10-03 --warps 50. Ms per warp, cold max / average of 50: v2 1.582 / 1.280; mx8 5.394 / 5.267; mx8+sh256x27 (class v4) 6.334 / 6.006; dr368 5.540 / 5.426; dr736 10.290 / 10.042 (fails the 10 ms gate, the known-fail). Cache fill 276 ms. Log docs/analysis/attack-pass/o114-i7-9700K-2026-10-07.log; record docs/analysis/attack-pass-2026-10.md row F6. Class v4 passes a real 2019-class core with 3.7 ms to spare; the half-core proxy (8.23 ms) stays the standing pessimistic rule for the ladder's ceiling.

F6: the verifier's worst case over 10^5 class v4 programs (attack pass, 7 October 2026, 13:5x UTC)

-

igneum-build-1, cores 40 (one-core proxy) and 88 (the half-core proxy, both SMT siblings busy) under the per-core lease, core 40 at a median 3,799.9 MHz. 100,000 programs ranked by exact op counts; 50,000 timed cold on core 40 (min / median / p99 / max 4.610 / 4.948 / 5.606 / 6.194 ms per warp); the worst 200 re-timed at 10 cold reps on both proxies and the worst 1,000 on the half-core at 2 reps, the worst 10 at 20: worst half-core cold max 8.708 ms (attack-f6/87142), then 8.629 (attack-f6/88521), 8.414 (attack-f6/15781); the genesis program 8.624. Gate 10 ms: PASS by 1.29 ms. Record docs/analysis/attack-pass/f6-verifier.md; logs /srv/builds/igneum-wt-attack/target-attack-f6/phase2b.log, phase2c.log.

+

igneum-build-1, cores 40 (one-core proxy) and 88 (the half-core proxy, both SMT siblings busy) under the per-core lease, core 40 at a median 3,799.9 MHz. 100,000 programs ranked by exact op counts; 50,000 timed cold on core 40 (min / median / p99 / max 4.610 / 4.948 / 5.606 / 6.194 ms per warp); the worst 200 re-timed at 10 cold reps on both proxies and the worst 1,000 on the half-core at 2 reps, the worst 10 at 20: worst half-core cold max 8.708 ms (attack-f6/87142), then 8.629 (attack-f6/88521), 8.414 (attack-f6/15781); the genesis program 8.624. Gate 10 ms: PASS by 1.29 ms. Record docs/analysis/attack-pass/f6-verifier.md; logs /srv/builds/igneum-wt-attack/target-attack-f6/phase2b.log, phase2c.log.

+
+

7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080 (branch ca3-v4-amend, the hash lane)

+

Main's question of 7 October ("profitable mining is all about efficiency, is there a solution?"): the latency-shadow work hides in the memory wait, so the core clock, and the voltage along the driver's V/F curve, can drop until the work just fits the wait, with no rate loss and the class v4 premium coming back. Measured on the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) (machine ae432dc7, driver 617.14, app 0.3.20) with tools/ca3-v4-amend/pc1-v4-efficiency.ps1: the installed CUDA worker's --bench on the class v4 pack v4-devnet-epoch0 (id a785001687d8688a) and the class v3 control mx8-devnet-epoch0 of the same seed (the two differ by the shadow block alone), the card alone through the runner's card switch, 60 s per step (the batch count sized from a 5-batch probe), the clock lock through the installed app's Power Helper task (nvidia-smi -lgc 0,<MHz>, a cap; no prompt), nvidia-smi at 1 Hz with the mean from 8 s in (power.draw, power.draw.instant and power.draw.average agree within 0.2 W on every row on 617.14), the 2^24 fingerprint at base 0 checked against the Apple M5 Max on every step (every step matched), the clocks reset and read back at the end. Jobs: run-ca3-pc1-v4-eff-5090-20261007-b (18:40 to 19:16 UTC, 2,850 to 1,400 MHz), run-ca3-pc1-v4-eff-5090-floor-20261007 (20:21 to 20:41 UTC, 1,400 to 1,100; the steps below were lost to the helper's sequence rule, see the fud ledger), run-ca3-pc1-v4-eff-5080-20261007-d (8 October, 00:45 to 01:54 UTC, unlocked to 1,000 MHz plus 900 on v4; the 75 min budget ended it there). The memory clock stayed at the driver's default throughout (13,801 MHz on the 5090, 14,801 on the 5080).

+

RTX 5090 (lock MHz: class v4 MH/s / W / MH/W ; class v3 MH/s / W / MH/W; the SM clock read):

+
lockv4 MH/sv4 Wv4 MH/Wv3 MH/sv3 Wv3 MH/Wsm MHz
unlocked136.84475.50.288136.59330.20.4142,838 / 2,850
2850136.89478.90.286136.61330.30.4142,833 / 2,842
2781136.87457.60.299136.62317.90.4302,767
2700136.85443.20.309136.54312.40.4372,692
2550136.77402.90.339136.43288.50.4732,542
2472136.62391.20.349136.38276.00.4942,460
2400136.67382.80.357136.29269.80.5052,392
2250136.43366.50.372136.07255.00.5342,242
2163136.33361.30.377136.11252.40.5392,152
2100136.25359.30.379136.04251.40.5412,092
1950135.99350.10.388135.78244.60.5551,942
1854135.85341.40.398135.56239.60.5661,845
1800135.75337.10.403135.48237.40.5711,792
1650135.37328.10.413135.10235.10.5751,642
1500135.22320.50.422134.90232.10.5811,492
1400134.98316.30.427134.68228.00.5911,387
1300134.76312.50.431134.62223.30.6031,290
1200133.80305.10.439129.54215.70.6011,192
1100122.43287.30.426118.70209.40.5671,087
+

Reading (5090): the rate is memory-bound on the whole grid and holds within 1.5 percent of unlocked down to 1,300 MHz on both classes; it falls past 5 percent at 1,200 on class v3 and past 10 percent at 1,100 on class v4, so the knee is 1,300 MHz (42 percent of the 3,090 MHz maximum). Best MH per watt: class v4 at 1,200 MHz (133.80 MH/s at 305.1 W, 0.439 MH/W; 168.6 W recovered for 2.2 percent rate), class v3 at 1,300 MHz (134.62 at 223.3 W, 0.603; 106.6 W for 1.4 percent). The class v4 premium over class v3 is 145.3 W at the unlocked clock and 81.8 W at the best points: 63 W of the premium is the clock and comes back with the lock, 82 W is the shadow's ALU work and stays. The throttle reason reads the power governor (0x400) from unlocked to 2,163 and the clock lock itself (0x4) below. Consequence per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate (MH per watt up 49 to 52 percent).

+

RTX 5080 (the same shape; 8 October 2026, 00:45 to 01:54 UTC):

+
lockv4 MH/sv4 Wv4 MH/Wv3 MH/sv3 Wv3 MH/Wsm MHz
unlocked71.41253.10.28271.28169.70.4202,963 / 2,977
285071.41229.50.31171.29155.30.4592,842
278171.41223.90.31971.29150.10.4752,767
270071.41209.60.34171.29149.20.4782,692
255071.41193.00.37071.29134.40.5312,542
247271.41182.20.39271.28133.70.5332,460
240071.41176.00.40671.29128.70.5542,392
225071.41165.60.43171.28117.30.6082,242
216371.39161.50.44271.28114.10.6252,147 / 2,152
210071.38157.70.45371.28112.30.6352,085
195071.37154.00.46371.26111.60.6391,942
185471.37153.00.46771.25111.40.6401,845
180071.35150.30.47571.24113.40.6281,777 / 1,785
165071.33151.40.47171.22109.70.6491,635 / 1,642
150071.30149.20.47871.19110.60.6441,492
140071.27149.60.47671.16107.00.6651,387
130071.24147.90.48271.14107.70.6611,275 / 1,282
120071.20149.40.47771.12104.40.6811,192
110071.20146.60.48671.11105.60.6731,087
100071.19149.00.47871.11103.70.686990
90067.66137.80.491not taken (the budget)893
+

Reading (5080): the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes and falls 5.2 percent at 900 MHz on class v4, so the knee is between 1,000 and 900 MHz, a third of the 2,963 MHz boost and lower than the 5090's (the 5080's 84 SMs have more compute headroom per unit of its memory bandwidth, so the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: class v4 at 1,100 MHz (71.20 MH/s at 146.6 W, 0.486 MH/W; 106.5 W recovered for 0.29 percent rate), class v3 at 1,000 MHz (71.11 at 103.7 W, 0.686; 66.0 W for 0.25 percent). The class v4 premium is 83.4 W unlocked and 41 W at the best points (146.6 W against 105.6 W at 1,100). The draw floors from 1,500 MHz down (about 147 W on v4, 104 W on v3) with the power governor as the only throttle reason say the clock lever is spent by 1,500 MHz on this card. Consequence per tier: a 5080 owner on class v4 locked near 1,100 MHz pays 147 W instead of 253 for 0.3 percent less rate (MH per watt up 72 percent).

+

What the lever is and is not: nvidia-smi exposes no voltage offset (that is NVAPI's); the clock lock walks the driver's V/F curve, which is where the watts come from; the Apple M5 Max has no lever (no clock cap on Apple silicon); AMD has the ADLX tune line through igneum-gpu-telemetry or nothing. The knob goes into Ember Tune for 0.3.24 (src/ember.rs: the clock ladder continues below 45 percent of the maximum in 100 MHz steps to a 20 percent floor, the search stops at the first row more than the tolerance under the cap point's rate or on a faulted row, the best MH per watt within tolerance is the point, the fingerprint checked on every step, the result stored per card as the lock_* fields). The 5080 stock rows against the rented 5080 of 7 October (71.16 MH/s at 145 W on driver 580): the rate agrees to 0.4 percent, the watts do not (253 W here); the three-card Windows rig's three power fields agree, so the difference sits with the rented card's sampler or its cap, the fleet lane's re-measure owed.

+
+

8 October 2026, the hot-table packs on the RTX 5090: ld.global.cs against the plain load, unlocked and at the 1,300 MHz lock (branch ca3-v4-amend, the hash lane, job run-ca4-pc1-hot-ldcs-5090-20261008b)

+

the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT), RTX 5090 (170 SMs, driver 13.4, NVRTC 12.8), igneum-worker-cuda 1.0 (4 October 2026). The eight 5 October hot-table packs (proto-cuda/packs-ca2-hot) and the mx8-genesis control (proto-cuda/packs-ca2-mixer), each run twice per state: variant base (plain loads) and variant ldcs (ld.global.cs on the hot-table loads). 16,777,216 nonces per run, nvidia-smi 1 Hz sampler (power.draw; instant and average agreed within 0.5 W on every row), 19 to 30 samples per row. Every one of the 36 rows PASS on its pinned fingerprint. Unlocked 06:34 to 06:45 UTC at 2,865 MHz; lock1300 06:45 to 06:56 UTC at 1,290 MHz through the helper; clocks reset (rgc) at the end. The 5090 was switched off in the app by the runner for the job and back on after.

+
packunlocked base MH/sunlocked base Wunlocked ldcs MH/slock1300 base MH/slock1300 base Wlock1300 base MH/Wlock1300 ldcs MH/slock1300 ldcs MH/W
mx8-genesis (control)137.7312.0137.7127.3211.40.602127.30.603
hot32k4147.4318.9147.4144.4215.30.671144.40.672
hot32k4a118.9320.1118.9116.6214.90.542116.60.542
hot64k2137.7318.1137.7135.0214.30.630135.00.630
hot64k4141.0318.8141.0138.2214.40.645138.20.644
hot64k4a115.7319.6115.8113.4214.80.528113.40.528
hot64k8164.2326.4164.2160.9219.20.734160.80.733
hot96k4139.0318.3139.0136.2214.50.635136.30.635
hot96k4a114.6318.8114.5112.3214.80.523112.30.523
+

What the rows say.

+
  1. The ldcs variant changes nothing: every pack reads the same rate and the same watts as its base run within 0.1 MH/s and 1 W, both states. The streaming hint on the hot-table loads is dead as a lever; the table's cache behaviour is already what the hardware gives. No further ldcs rows are owed.
  2. The hot packs hold their rate under the lock far better than mx8: the 1,300 MHz lock costs mx8 7.5 percent of rate (137.7 to 127.3) and costs the hot packs 2 percent (hot32k4 147.4 to 144.4, hot64k8 164.2 to 160.9). The hot packs are bound by the table's latency, not by the core; the lock takes a third of the watts off every pack (319 to 215 W) and the hot packs pay almost no rate for it.
  3. Per watt at the lock the hot family runs 0.52 to 0.73 MH/W against the control's 0.60: hot64k8 is 22 percent cheaper per hash than mx8 on this card, hot32k4 11 percent cheaper, the "a" packs 10 to 13 percent dearer. Whether a cheaper hash on the GPU is a gain or a loss for resistance is the research lane's call: it is a gain only if the saving comes from the memory path an ASIC would have to buy too.
  4. The 5090's locked class v4 reading from the efficiency pass (1,300 MHz: 134.6 MH/s at 223 W, 0.60 MH/W) sits level with the mx8 control here (0.602), so the two passes agree on the control and the hot rows are comparable to the v4 grid.

Generated from the repository at build time. Times are UTC. Machine names are model names.

@@ -989,7 +1016,7 @@ table{min-width:560px} The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -1004,6 +1031,8 @@ table{min-width:560px}

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/block.html b/site/block.html index 1b1d4e62e..1da684c9b 100644 --- a/site/block.html +++ b/site/block.html @@ -108,6 +108,7 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin
+
@@ -125,7 +126,6 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -148,6 +148,13 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -177,6 +183,11 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -274,7 +285,7 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -289,6 +300,8 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/build.html b/site/build.html new file mode 100644 index 000000000..f476ffb48 --- /dev/null +++ b/site/build.html @@ -0,0 +1,356 @@ + + + + + +Build on Igneum: chain ids, RPC, a contract in five minutes + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
Igneum/Build on Igneum
+
Developers
+

Build on Igneum

+

Every block proven. A lock in minutes. Nothing to stake. The EVM you already know: Solidity deploys unchanged. Here are the chain ids, the endpoints and a contract in five minutes.

+
+
+
+ +
+ +

Build on Igneum

+

This file is the source of igneum.network/build. The site build renders it as the page. The other files in this directory are the walkthrough, the RPC list, the faucet, the verifier and the grants.

+
+

What is different

+

Every block is proven. A chain block carries a zero-knowledge proof of its execution. The miners are the provers: the same cards that find blocks prove them, in shards, and the proof follows the tip by tens of seconds. Your contract runs on a chain whose state is proven, not assumed.

+

A lock in minutes, not an hour of confirmations. Miners sign a checkpoint every 30 seconds. When two thirds of the mining weight of the last 30 days have signed, the checkpoint is locked. Weight is blocks mined, nothing else. The lock lands in about two minutes. The litepaper has the rule.

+

Nothing to stake. No validator set, no delegation, no slashing, no bonded class above the miners. Finality comes from mining weight alone. Nobody holds a key that the chain depends on.

+

The EVM you already know. Solidity deploys unchanged. Standard JSON-RPC, EIP-1559 transactions, the chain id in the signature, cancun as the EVM version. Gas has two dimensions on Igneum, execution and proving, and the node folds the second into the price it quotes, so eth_estimateGas and eth_gasPrice work as they do on Ethereum.

+
+

Networks

+
Devnet 3TestnetMainnet
Chain id4463 (0x116f)4462 (0x116e)4461 (0x116d)
Network idigneum-devnet-3igneum-testnet-1not started
RPChttps://rpc.devnet.igneum.network (a node you run serves http://127.0.0.1:26790)https://rpc.testnet.igneum.network (answers; nothing mines there yet, so a transaction waits)none
Coinsno value, resets without noticeno value, resets with noticenot started
Symbol, decimalsIGN, 18IGN, 18IGN, 18
+

Devnet 3 is where you build today. It is a developer network: it resets without notice and its coins have no value. Its public RPC takes the read methods, eth_sendRawTransaction and a wRPC websocket at /ws, at 20 requests a second per address. The public testnet exists, its RPC answers, and no blocks are being produced on it until it opens. Mainnet has no date. Devnet 3 answers chain id 4463 until its class v5 floor, then 4464.

+
+

Endpoints and tools

+ +
+

Your first contract in five minutes

+

With Foundry. Tested end to end on Devnet 3 on a build box; the full walkthrough with the expected output is docs/build/first-contract.md.

+
curl -L https://foundry.paradigm.xyz | bash && foundryup
+export RPC=https://rpc.devnet.igneum.network
+cast wallet new                      # an address and a private key, for the devnet only
+

Paste the address into the faucet. Then:

+
export PK=0x...                      # the private key cast printed
+cast balance $(cast wallet address $PK) --rpc-url $RPC --ether
+forge init counter && cd counter
+forge create src/Counter.sol:Counter --rpc-url $RPC --private-key $PK --broadcast
+

forge create prints Deployed to: 0x.... Call it:

+
cast send 0xDEPLOYED "increment()" --rpc-url $RPC --private-key $PK
+cast call 0xDEPLOYED "number()(uint256)" --rpc-url $RPC
+

The call answers 1. Paste the transaction hash into the explorer. Hardhat, ethers and viem work the same way: chain id 4463, the RPC above.

+
+

The RPC the node serves

+

Read from a Devnet 3 node, not from a spec. web3_clientVersion answers igneumd/2.1.0/execution-layer-v3. The full list, served and not served, with the probe that produced it: docs/build/rpc.md.

+
  • Served. eth_chainId, eth_blockNumber, eth_getBalance, eth_getTransactionCount, eth_getCode, eth_getStorageAt, eth_getBlockByNumber, eth_getBlockByHash, eth_getTransactionByHash, eth_getTransactionReceipt, eth_getBlockReceipts, eth_getLogs, eth_call, eth_estimateGas, eth_gasPrice, eth_maxPriorityFeePerGas, eth_feeHistory, eth_sendRawTransaction, eth_syncing, eth_accounts, net_version, net_peerCount, net_listening, web3_clientVersion.
  • Igneum's own. igneum_getExecStatus, igneum_getProvingStatus, igneum_getShardPlan, igneum_getProofRecords, igneum_getTransactionStatus, igneum_estimateGas, igneum_getBudgets and the segment and proof calls. igneum_estimateGas returns both gas dimensions and whether a call exceeds the proving limit.
  • Not served. Filters and subscriptions (eth_newFilter, eth_subscribe), txpool_*, debug_*, trace_*, eth_sendTransaction, eth_sign, eth_getProof, the uncle calls. Poll eth_blockNumber and eth_getLogs. Sign on your side.
+
+

Verify a block in your browser

+

The site ships a light client. Your browser fetches the latest certified checkpoint from /api/checkpoint and verifies the BLS aggregate signature, the voter weights and the header chain itself, in the tab. Nothing is trusted from the server but the data. The example, in twelve lines, is docs/build/verify-a-block.md; the live run is verify/test.html, genuine and tampered cases side by side.

+
import { fetchCheckpoint, verify } from 'https://igneum.network/verify/verify.js';
+const data = await fetchCheckpoint('https://igneum.network/api/checkpoint');
+const r = verify(data);
+console.log(r.verified, r.signers, 'of', r.voters, 'voters', r.ms, 'ms');
+
+

Where to ask

+ +

Devnet and testnet coins have no value. Nothing on this page is an offer to sell anything.

+
+

Generated from docs/build/build.md in the repository at build time. Times are UTC.

+
+
+ + + + + + + + \ No newline at end of file diff --git a/site/build.mjs b/site/build.mjs index ccd3f4571..f9343f2e6 100644 --- a/site/build.mjs +++ b/site/build.mjs @@ -19,6 +19,7 @@ function inline(s) { s = s.replace(/`([^`]+)`/g, '$1'); s = s.replace(/\*\*([^*]+)\*\*/g, '$1'); s = s.replace(/\[([^\]]+)\]\((https?:[^)]+)\)/g, '$1'); + s = s.replace(/\[([^\]]+)\]\((\/[^)\s]*)\)/g, '$1'); // a site-relative link (the builder pages, 8 October 2026) return s; } function md(src) { @@ -278,6 +279,21 @@ if (existsSync(join(docs, 'bench-log.md'))) { built.push('journey.json (' + j.log.length + ' entries)'); } +// The builder programme (8 October 2026): /build and /grants are rendered from docs/build/build.md and docs/build/grants.md +// through the same generated-page shell as /bench, so the markdown is the source and the served page follows it. The other +// files of docs/build/ (the walkthrough, the RPC list, the faucet, the verifier) are linked from /build on the git host. +for (const [src, file, title, desc, heading, lead, eyebrow] of [ + ['build.md', 'build.html', 'Build on Igneum: chain ids, RPC, a contract in five minutes', 'The developer entry page for Igneum: what is different, the chain ids and RPC endpoints, the wallet, the explorer, the faucet, a five-minute contract deploy and a block you verify in your browser.', 'Build on Igneum', 'Every block proven. A lock in minutes. Nothing to stake. The EVM you already know: Solidity deploys unchanged. Here are the chain ids, the endpoints and a contract in five minutes.', 'Developers'], + ['grants.md', 'grants.html', 'Igneum grants: tooling, reference apps, infrastructure, research', 'The Igneum grants programme: four tiers, what a grant is, how to apply with an issue on the git host, the weekly review, and the lines that stay honest about value, amounts and dates.', 'Grants', 'Work paid in IGN on delivery, on the public testnet first. Four tiers. One issue to apply. A weekly review.', 'The programme'], +]) { + const mdp = join(docs, 'build', src); + if (!existsSync(mdp)) continue; // the gate builds a copy of site/ alone: the committed page stands, as for /bench + const { html, toc } = md(readFileSync(mdp, 'utf8')); + const path = '/' + file.replace(/\.html$/, ''); + writeFileSync(join(here, file), page(title, desc, html, toc, lead, { path, heading, crumb: heading, eyebrow, filter: false }).replace('

Generated from the repository at build time. Times are UTC. Machine names are model names.

', `

Generated from docs/build/${src} in the repository at build time. Times are UTC.

`)); + built.push(file); +} + // The hand-written pages: shared head, nav (with the active link marked) and footer injected in place; the homepage also // gets journey.json inlined so the phases and the log render without a fetch and without a layout shift. const journey = JSON.parse(readFileSync(join(here, 'journey.json'), 'utf8')); diff --git a/site/claims.html b/site/claims.html index f86f4de02..eebcc8bae 100644 --- a/site/claims.html +++ b/site/claims.html @@ -86,6 +86,7 @@
+
@@ -103,7 +104,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -126,6 +126,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -155,6 +161,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -262,7 +273,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -277,6 +288,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/dev-fee.html b/site/dev-fee.html index dc749c60b..f6812dc1b 100644 --- a/site/dev-fee.html +++ b/site/dev-fee.html @@ -86,6 +86,7 @@
+
@@ -103,7 +104,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -126,6 +126,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -155,6 +161,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -270,7 +281,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -285,6 +296,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/download.html b/site/download.html index 7c6872ad9..63fbf554f 100644 --- a/site/download.html +++ b/site/download.html @@ -76,6 +76,7 @@
+
@@ -93,7 +94,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -116,6 +116,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -145,6 +151,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -235,16 +246,16 @@

Ember for Linux

one tarball, the miner and the node inside

Unpack it, run igneum with your payout address. The same signed manifest as the desktop apps. NVIDIA through CUDA, AMD through OpenCL.

- Download the tarball v0.3.23 · 28.8 MB -
sha256 0d716ed92560b6b2eccb63ca1bd7a4d9eb64c9b334e8370e1263f0344cee294e
+ Download the tarball v0.3.22 · 28.8 MB +
sha256 8ad6dcef9edc57dcd33e8d5a97cbef5cdda0e384a6e56d3f62f8903029c4c764

Ember on HiveOS

for the rig people, the same tarball
-
Flight Sheet. Miner: Custom. Installation URL: https://dl.igneum.network/dl/public/igneum-hive-0.3.23.tar.gz. Miner name igneum, wallet and worker 0x<your 40-hex payout address>.%WORKER_NAME%. Hive itself is untested on our side: tell us what breaks.
- Download the tarball v0.3.23 · 28.8 MB +
Flight Sheet. Miner: Custom. Installation URL: https://dl.igneum.network/dl/public/igneum-hive-0.3.22.tar.gz. Miner name igneum, wallet and worker 0x<your 40-hex payout address>.%WORKER_NAME%. Hive itself is untested on our side: tell us what breaks.
+ Download the tarball v0.3.22 · 28.8 MB
@@ -308,7 +319,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -323,6 +334,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/evidence.html b/site/evidence.html index 391c2479c..949c11b25 100644 --- a/site/evidence.html +++ b/site/evidence.html @@ -97,6 +97,7 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v
+
@@ -114,7 +115,6 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -137,6 +137,13 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -166,6 +172,11 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -303,7 +314,7 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -318,6 +329,8 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/explorer.html b/site/explorer.html index 4dcc62e34..42f072c74 100644 --- a/site/explorer.html +++ b/site/explorer.html @@ -107,6 +107,7 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin
+
@@ -124,7 +125,6 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -147,6 +147,13 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -176,6 +182,11 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -295,7 +306,7 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -310,6 +321,8 @@ main{padding-bottom:100px}.card{background:var(--row);border:1px solid var(--lin

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/faucet.html b/site/faucet.html index d571e217e..96f5566d2 100644 --- a/site/faucet.html +++ b/site/faucet.html @@ -3,22 +3,22 @@ -Igneum testnet faucet. 10 IGN a day for testing - +Igneum Devnet 3 faucet. 10 IGN a day for building + - - + + - - + + @@ -86,9 +86,10 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo devnet
@@ -106,7 +107,6 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -129,6 +129,13 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -158,6 +164,11 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -213,16 +224,16 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo
-
Igneum/Testnet faucet
-
Testnet faucet
-

10 IGN a day, for testing.

-

Paste an address. The faucet sends 10 testnet IGN and shows you the transaction hash. Once per address per day, once per connection per day. No account, no sign-in, nothing to install.

-

Public testnet: not yet open. The faucet is prepared on the devnet and answers "not open yet" until the testnet starts.

+
Igneum/Devnet 3 faucet
+
Devnet 3 faucet
+

10 IGN a day, for building.

+

Paste an address. The faucet sends 10 IGN of Devnet 3 coin and shows you the transaction hash. Once per address per day, once per connection per day. No account, no sign-in, nothing to install.

+

Devnet 3, chain id 4463. The coins have no value and the chain resets without notice.

Ask for 10 IGN

-

An Ethereum-style address: 0x and 40 hex characters. The one the miner made for you, or any wallet you have pointed at the Igneum testnet.

+

An Ethereum-style address: 0x and 40 hex characters. The one cast wallet new printed, the one the miner made for you, or any wallet you have pointed at Devnet 3.

@@ -233,15 +244,17 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo
@@ -268,7 +281,7 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -283,6 +296,8 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord @@ -315,17 +330,20 @@ dt{color:var(--ash)}dd{margin:0;font-family:var(--f-mono);font-size:14px;overflo + + + + + + + + + +
+
+
+
Igneum/Grants
+
The programme
+

Grants

+

Work paid in IGN on delivery, on the public testnet first. Four tiers. One issue to apply. A weekly review.

+
+
+
+ +
+ +

Grants

+

This file is the source of igneum.network/grants.

+
+

What a grant is

+

Work paid in IGN on delivery. You propose a piece of work, it is accepted with a written definition of done, you build it, it runs on the public testnet, and it is paid when it does. Not a salary, not an advance, not an investment.

+

The money is the dev fee fund: the IGN that the Ember dev fee collects. Ember, the official miner, takes an optional 1% of a miner's rewards, in full view and off with one flag; that fee goes to Igneum Labs, the company that ships the software. The protocol itself carries no fee, no fund and no allocation, and no grant is paid from emission. The dev fee has the mechanism.

+
+

The tiers

+
TierWhat fits
ToolingSDK bindings, indexers, a Hardhat or Foundry plugin for the two gas dimensions, verification tooling, a light client in another language
Reference appsA token, a swap, a registry, a wallet integration, an app that uses igneum_getTransactionStatus and the lock the way it is meant to be used
InfrastructureRPC providers, archive nodes, seed nodes in new regions, pool software, an explorer back end
ResearchThe lottery hash, the finality rule, the proving layer, the fee model; attacks on the public test vectors; measurements the project does not have
+

A grant is sized by the work in front of it, not by a table. Two grants in the same tier can differ.

+
+

How to apply

+

Open an issue on git.igneum.network/igneum-network/igneum and pick the Grant template. It asks for:

+
  1. What you will build, in a paragraph, and which tier it is.
  2. What done looks like: what runs where, what a reviewer can click or call to see it working on the public testnet.
  3. Your public work: a repository, a package, a paper, a deployed thing.
  4. How you want to be reached.
+

A short issue is fine. The definition of done is the part that matters.

+
+

The review

+
  • Every Friday. Each open application gets one of three answers inside seven days: accepted with a definition of done, questions, or no with the reason.
  • Accepted work is tracked in its issue. The reviewer and the builder agree the definition of done there before any work starts.
  • Delivery is reviewed on the public testnet first. Payment follows the review, in the issue, in the open.
+
+

The honest lines

+
  • Devnet and testnet coins have no value. A grant delivered before mainnet is paid when mainnet IGN exists, not in devnet or testnet coin.
  • No amount, price or date is promised. The fund is what the dev fee collects, and it is zero until there is mining with value.
  • A grant is for work delivered, never for a user count, a listing, a post or a referral.
  • Igneum Labs may decline any application and may close the programme; what has been accepted and delivered is still paid.
+

Not legal advice.

+
+

Generated from docs/build/grants.md in the repository at build time. Times are UTC.

+
+
+ + + + + + + + \ No newline at end of file diff --git a/site/income.html b/site/income.html index 5f73c7dbf..fce08f63b 100644 --- a/site/income.html +++ b/site/income.html @@ -46,6 +46,7 @@
+
@@ -63,7 +64,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -86,6 +86,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -115,6 +121,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -236,7 +247,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -251,6 +262,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/index.html b/site/index.html index 716624fbb..792b1fa37 100644 --- a/site/index.html +++ b/site/index.html @@ -78,6 +78,7 @@
+
@@ -95,7 +96,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -118,6 +118,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -147,6 +153,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -277,7 +288,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -292,6 +303,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/journey.html b/site/journey.html index a613273f6..97ad9030d 100644 --- a/site/journey.html +++ b/site/journey.html @@ -86,6 +86,7 @@
+
@@ -103,7 +104,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -126,6 +126,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -155,6 +161,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -212,7 +223,7 @@
Igneum/The journey
-
Six phases · updated 7 Oct 2026
+
Six phases · updated 8 Oct 2026

The journey.

Six phases from the specification to a fair launch. Each closes at its gate, a measurement published whether it passes or fails, so there is no date to slip. Below the phases, the latest entries of the engineering log.

@@ -226,7 +237,8 @@
The log, newest first

Lately, in the log.

-
log

The first 16 GB card

The first 16 GB card: an RTX 5060 Ti in a Thunderbolt enclosure on the RTX 5090 Windows rig

+
log

The hot-table packs on the RTX 5090

The hot-table packs on the RTX 5090: ld.global.cs against the plain load, unlocked and at the 1,300 MHz lock

+
log

The first 16 GB card

The first 16 GB card: an RTX 5060 Ti in a Thunderbolt enclosure on the RTX 5090 Windows rig

log

Counter ASIC 3.0

Counter ASIC 3.0: the class v4 rehearsal

log

16:01Z: Ember run 6 on the three-card Windows rig

log

Counter ASIC 3.0 item 2

Counter ASIC 3.0 item 2: the per-day derivation

@@ -259,13 +271,12 @@
log

Live devnet: real transactions, the first non-empty shard proven and…

Live devnet: real transactions, the first non-empty shard proven and paid, and the exporter's block structure fixed

log

The program id split

The program id split: why the Apple M5 Max rejected the RTX 5090 Windows rig's proofs, and the verifier at 114 s

log

Live devnet: the first shards proven, verified and paid

+
log

Devnet v4 live: generator v2, two-thirds floor, fresh chain

Devnet v4 cut-over: generator v2, 2/3 floor, three nodes and a seed on a fresh chain

log

One-click Windows workers

One-click Windows workers: what the Apple M5 Max could measure

log

First live hourly swap: no pause on Mac, NVIDIA or AMD

First hourly program swap on the live devnet: compile-ahead, no pause, two cards

log

Proving: devnet v4 shards on the Apple M5 Max CPU, loaded machine

log

First live finality lock: 77.4% of weight, 17 voters

First finality lock on the live devnet: checkpoint 242 at 77.4% of all weight, two hours after genesis

-
log

The gfx1036 worker fault and what the Apple M5 Max could and could…

The gfx1036 worker fault and what the Apple M5 Max could and could not reproduce

-
log

A node 60 s behind the clock is silently dead

-
log

First machine on the one-click app: a 5090 at 118 MH/s

First machine on the Igneum Miner app: the RTX 5090 Windows rig's RTX 5090 at 118 MH/s, via Setup.exe

+
log

The gfx1036 worker fault and what the Apple M5 Max could and could…

The gfx1036 worker fault and what the Apple M5 Max could and could not reproduce

Every entry is a dated heading of the engineering log, where the commands and the hardware are. The phases and their gates are the litepaper’s roadmap.

The engineering logEvery claim and its statusThe live devnet
@@ -294,7 +305,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -309,6 +320,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/journey.json b/site/journey.json index 331b53d72..40e99d2b7 100644 --- a/site/journey.json +++ b/site/journey.json @@ -1,5 +1,5 @@ { - "updated": "2026-10-07", + "updated": "2026-10-08", "stage": "phase-3", "phases": [ { @@ -50,6 +50,11 @@ } ], "log": [ + { + "date": "2026-10-08", + "text": "The hot-table packs on the RTX 5090: ld.global.cs against the plain load, unlocked and at the 1,300 MHz lock", + "short": "The hot-table packs on the RTX 5090" + }, { "date": "2026-10-07", "text": "The first 16 GB card: an RTX 5060 Ti in a Thunderbolt enclosure on the RTX 5090 Windows rig", @@ -215,6 +220,11 @@ "text": "Live devnet: the first shards proven, verified and paid", "short": "Live devnet: the first shards proven, verified and paid" }, + { + "date": "2026-10-04", + "text": "Devnet v4 cut-over: generator v2, 2/3 floor, three nodes and a seed on a fresh chain", + "short": "Devnet v4 live: generator v2, two-thirds floor, fresh chain" + }, { "date": "2026-10-04", "text": "One-click Windows workers: what the Apple M5 Max could measure", @@ -239,16 +249,6 @@ "date": "2026-10-04", "text": "The gfx1036 worker fault and what the Apple M5 Max could and could not reproduce", "short": "The gfx1036 worker fault and what the Apple M5 Max could and could…" - }, - { - "date": "2026-10-04", - "text": "A node 60 s behind the clock is silently dead", - "short": "A node 60 s behind the clock is silently dead" - }, - { - "date": "2026-10-04", - "text": "First machine on the Igneum Miner app: the RTX 5090 Windows rig's RTX 5090 at 118 MH/s, via Setup.exe", - "short": "First machine on the one-click app: a 5090 at 118 MH/s" } ] } diff --git a/site/ledger.html b/site/ledger.html index f896139f2..cfdab4980 100644 --- a/site/ledger.html +++ b/site/ledger.html @@ -89,7 +89,8 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
@@ -107,7 +108,6 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -130,6 +130,13 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -154,11 +160,16 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
Learn
LitepaperThe design, as published. Income per tierIGN a day per card at three network sizes, and the electricity. - LedgerEvery criticism, answered or conceded. + LedgerEvery criticism, answered or conceded. What Igneum does not claimThe limits, stated first. Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -1426,7 +1437,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
-
WindowsmacOSLinuxHiveOS
+
WindowsmacOSLinuxHiveOS
Specification and test vectors

Run

@@ -1436,7 +1447,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -1451,6 +1462,8 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/litepaper.html b/site/litepaper.html index defe6ddf3..2f00351a3 100644 --- a/site/litepaper.html +++ b/site/litepaper.html @@ -143,6 +143,7 @@ body.all .pager{display:none}
+
@@ -160,7 +161,6 @@ body.all .pager{display:none} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -183,6 +183,13 @@ body.all .pager{display:none} Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -212,6 +218,11 @@ body.all .pager{display:none} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -847,7 +858,7 @@ body.all .pager{display:none} The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -862,6 +873,8 @@ body.all .pager{display:none}

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/live.html b/site/live.html index 12c52735c..d716d7e9d 100644 --- a/site/live.html +++ b/site/live.html @@ -227,6 +227,7 @@ details.tablebar summary{display:flex;align-items:center}
+
@@ -244,7 +245,6 @@ details.tablebar summary{display:flex;align-items:center} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -267,6 +267,13 @@ details.tablebar summary{display:flex;align-items:center} Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -296,6 +302,11 @@ details.tablebar summary{display:flex;align-items:center} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -510,7 +521,7 @@ details.tablebar summary{display:flex;align-items:center} The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -525,6 +536,8 @@ details.tablebar summary{display:flex;align-items:center}

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/metamask.html b/site/metamask.html index 8f2ef399a..7b6b6e73e 100644 --- a/site/metamask.html +++ b/site/metamask.html @@ -88,6 +88,7 @@ ol{margin:0 0 14px;padding-left:22px}li{margin-bottom:6px}
+
@@ -105,7 +106,6 @@ ol{margin:0 0 14px;padding-left:22px}li{margin-bottom:6px} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -128,6 +128,13 @@ ol{margin:0 0 14px;padding-left:22px}li{margin-bottom:6px} Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -157,6 +163,11 @@ ol{margin:0 0 14px;padding-left:22px}li{margin-bottom:6px} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -301,7 +312,7 @@ ol{margin:0 0 14px;padding-left:22px}li{margin-bottom:6px} The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -316,6 +327,8 @@ ol{margin:0 0 14px;padding-left:22px}li{margin-bottom:6px}

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/miner.html b/site/miner.html index 1a34df3a7..32363b728 100644 --- a/site/miner.html +++ b/site/miner.html @@ -83,6 +83,7 @@ pre b{color:var(--molten-text);font-weight:500}
+
@@ -100,7 +101,6 @@ pre b{color:var(--molten-text);font-weight:500} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -123,6 +123,13 @@ pre b{color:var(--molten-text);font-weight:500} Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -152,6 +158,11 @@ pre b{color:var(--molten-text);font-weight:500} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -268,9 +279,9 @@ pre b{color:var(--molten-text);font-weight:500}
@@ -453,7 +464,7 @@ pre b{color:var(--molten-text);font-weight:500} The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -468,6 +479,8 @@ pre b{color:var(--molten-text);font-weight:500}

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/miners.html b/site/miners.html index 1973c1dca..1a52b7d8e 100644 --- a/site/miners.html +++ b/site/miners.html @@ -87,6 +87,7 @@ table{min-width:560px}
+
@@ -104,7 +105,6 @@ table{min-width:560px} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -127,6 +127,13 @@ table{min-width:560px} Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -156,6 +162,11 @@ table{min-width:560px} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
@@ -331,7 +342,7 @@ table.bench2 tr.detail .d{display:block;margin:0 0 4px}table.bench2 tr.detail b{ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -346,6 +357,8 @@ table.bench2 tr.detail .d{display:block;margin:0 0 4px}table.bench2 tr.detail b{

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/partials/footer.html b/site/partials/footer.html index 2dae4547e..1efe7f230 100644 --- a/site/partials/footer.html +++ b/site/partials/footer.html @@ -19,7 +19,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -34,6 +34,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/partials/nav.html b/site/partials/nav.html index 58fd4456a..76be0d56b 100644 --- a/site/partials/nav.html +++ b/site/partials/nav.html @@ -10,6 +10,7 @@
+
@@ -27,7 +28,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -50,6 +50,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -79,6 +85,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
DiscordSourceReddit
diff --git a/site/provenance.html b/site/provenance.html index c303deb48..91ccb4a13 100644 --- a/site/provenance.html +++ b/site/provenance.html @@ -87,6 +87,7 @@ table{min-width:560px}
+
@@ -104,7 +105,6 @@ table{min-width:560px} The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -127,6 +127,13 @@ table{min-width:560px} Built on the shouldersEvery borrowed part, credited. +
Network
@@ -156,6 +162,11 @@ table{min-width:560px} Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
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@@ -269,7 +280,7 @@ table{min-width:560px} The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -284,6 +295,8 @@ table{min-width:560px}

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/randomx.html b/site/randomx.html index ebc61f0a5..5ad16c920 100644 --- a/site/randomx.html +++ b/site/randomx.html @@ -86,6 +86,7 @@
+
@@ -103,7 +104,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -126,6 +126,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -155,6 +161,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
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@@ -260,7 +271,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -275,6 +286,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/scenes.html b/site/scenes.html index fd8804a07..080fdb2ef 100644 --- a/site/scenes.html +++ b/site/scenes.html @@ -64,6 +64,7 @@
+
@@ -81,7 +82,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -104,6 +104,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -133,6 +139,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
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@@ -247,7 +258,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

Read

@@ -262,6 +273,8 @@

Explore

Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/site/sitemap.xml b/site/sitemap.xml index 0307cfa6e..7608ca529 100644 --- a/site/sitemap.xml +++ b/site/sitemap.xml @@ -17,5 +17,7 @@ https://igneum.network/provenance2026-10-07monthly0.4 https://igneum.network/dev-fee2026-10-07monthly0.4 https://igneum.network/metamask2026-10-07monthly0.4 - https://igneum.network/faucet2026-10-07monthly0.4 + https://igneum.network/faucet2026-10-08monthly0.4 + https://igneum.network/build2026-10-08weekly0.8 + https://igneum.network/grants2026-10-08monthly0.6 diff --git a/site/wallet.html b/site/wallet.html index dc32d079b..363b40deb 100644 --- a/site/wallet.html +++ b/site/wallet.html @@ -96,6 +96,7 @@
+
@@ -113,7 +114,6 @@ The walletYour coins. Final means final. GPU bench tableMeasured rates, card by card. The dev feeThe optional one, in full view, off with one flag. - Testnet faucetTest coin for an address, once a day. Add to MetaMaskIgneum as a network in your wallet.
@@ -136,6 +136,13 @@ Built on the shouldersEvery borrowed part, credited.
+
Network
@@ -165,6 +171,11 @@ Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited.
+
Build
+ Build on IgneumChain ids, RPC, a contract in five minutes. + Devnet faucet10 IGN of devnet coin, once a day. + GrantsTooling, apps, infrastructure, research. +
Download
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@@ -395,7 +406,7 @@ The wallet GPU bench table The dev fee - Testnet faucet + Devnet faucet Add Igneum to MetaMask

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@@ -410,6 +421,8 @@

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Live devnet Explorer + Build on Igneum + Grants Journey Downloads: devnet build Community Discord diff --git a/tools/ci/site-nav-check.mjs b/tools/ci/site-nav-check.mjs index 05acee2e6..d4978563b 100644 --- a/tools/ci/site-nav-check.mjs +++ b/tools/ci/site-nav-check.mjs @@ -1,6 +1,6 @@ #!/usr/bin/env node // Every served page carries the slim bar (site-ui-5, the owner's rule of 7 October 2026: "easy access to all of our pages -// without a header that is crazy"): the mark and wordmark, the three groups (Mine, Network, Learn) as buttons with their +// without a header that is crazy"): the mark and wordmark, the four groups (Mine, Network, Learn, Build) as buttons with their // aria, the Download button, and every route of the site reachable from the group panels AND from the phone sheet, each with // its one-line description. A page with a shorter nav, a panel missing a route, or a route the panels do not name fails the // build and the gate. The route list below is the contract: a new page adds its line here and in site/partials/nav.html in @@ -13,9 +13,10 @@ import { tmpdir } from 'node:os'; import { fileURLToPath } from 'node:url'; const here = dirname(fileURLToPath(import.meta.url)); const GROUPS = { - mine: ['/miner', '/download', '/app', '/wallet', '/miners', '/dev-fee', '/faucet', '/metamask'], + mine: ['/miner', '/download', '/app', '/wallet', '/miners', '/dev-fee', '/metamask'], network: ['/live', '/explorer', '/journey', '/bench', '/evidence'], learn: ['/litepaper', '/income', '/ledger', '/claims', '/randomx', '/provenance'], + build: ['/build', '/faucet', '/grants'], // the builder programme (8 October 2026): the developer entry page, the Devnet 3 faucet, the grants }; const ROUTES = Object.values(GROUPS).flat(); // pages served without their own panel entry: the explorer's two rewrites, the 404 and the unlinked scenes lab @@ -74,5 +75,5 @@ if (args[0] === '--self-test') { const site = args[0] || join(here, '..', '..', 'site'); const { pages, bad } = check(site); if (bad.length) { console.error('site nav check: ' + bad.length + ' problems\n' + bad.join('\n')); process.exit(1); } - console.log(`site nav check: ${pages} pages carry the slim bar: the mark, three groups with ${ROUTES.length} routes in the panels and the sheet, Download, the burger`); + console.log(`site nav check: ${pages} pages carry the slim bar: the mark, four groups with ${ROUTES.length} routes in the panels and the sheet, Download, the burger`); } From 1dcb3882e12fc67b20a150c44f9b55066ccca0b7 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:25:17 +0000 Subject: [PATCH 03/11] Class v6 family gate (lane D), first cut: the parameter table with bands and margins, the sampling bound (rule of three, the union bound over the per-era tests' measured miss rates, the stratified corners), the three rings of per-era tests with known-failed shapes and clean-seed costs, the board over the testnet period and the proof-of-testing record format, the honest line; the harness running on the boxes and its first 16-era reading (the era-stride class at 130 to 511 sigma on one address bit in 7 of 16 drawn eras); docs/analysis/class-v6 excluded from the public export Co-Authored-By: Claude Fable 5.1 --- docs/analysis/class-v6/family-gate.md | 232 ++++++++++++++++++++++++++ tools/ci/export-exclude.txt | 2 + 2 files changed, 234 insertions(+) create mode 100644 docs/analysis/class-v6/family-gate.md diff --git a/docs/analysis/class-v6/family-gate.md b/docs/analysis/class-v6/family-gate.md new file mode 100644 index 000000000..9d30b65f8 --- /dev/null +++ b/docs/analysis/class-v6/family-gate.md @@ -0,0 +1,232 @@ +# Class v6, the family gate: how a parameter family is cryptanalysed as a family + +Research lane D of the class v6 rotating-family design, under the Counter ASIC coordinator. First cut 8 October 2026, 11:0x to 17:00 BST (the deliverable clock); the full report by 09:00 BST on 9 October. Branch `class-v6-family-gate` (this document) and the harness branch `family-gate-v5` (the class v5 crate at 8f481459 plus the census harness, never a chain path). Internal research, not an independent review; nothing here touches a served number, the devnet or the testnet object; no consensus code this week. Every figure carries its source: a lane report on the mirror, a log on a box, or an arithmetic step shown in the text. Figures from memory are labelled approximate. + +The question. Class v6 (the founder's word at 11:1x BST, 8 October 2026) draws per era the parameters a release used to fix (layer 1), lets the dataset track the chain state (layer 2), rotates instruction families by height (layer 3) and generalises the acceptance floor and the uniformity test to each era's draw with a redraw on failure (layer 4). A chip is then built against a FAMILY of hashes, not one hash. The in-house pass of 7 October and the attack board F1 to F10 bounded ONE member of the family (class v4 sub-version 3 at 017e7037 and class v5 at 1c420786). This document says how the family is bounded: what the space is, how many eras must be drawn to say anything about the worst era, which tests the chain runs itself on every era and epoch, what the offline board looks like over the testnet period, what a published proof of testing contains, and what the whole apparatus cannot see. + +## 0. One page + +| Item | The line | +|---|---| +| The space (section 1) | Seven drawn axes with a tested band each: the mixer multiplier `m` in {4, 8, 16} (8 and 4 measured on cards and the verifier; 16 the verifier's open row), the ten non-load op weights within B points of table 1.4.2 with shuffle and mulhi never raised (B = 2 proposed in spec 1.13.1, B = 4 the research lane's proposal), the read width in {1, 4} words (w16 measured 5 October, w64 excluded), the shadow block shape in {64, 128, 256} instructions at 6,912 per iteration (measured 6 October), the shadow placement fixed at the whole block after instruction 63 (the per-load placement is a known-failed corner: 1.4 percent acceptance, 42 of 64 seeds exhausting 32 attempts), the program length N by the ladder's signal inside rungs 0 to 2 (rung 3 inadmissible by F6), and the existing era draws (the stride `M`, the rotation `R` in 1..31, the interleave, the per-site windows). The day key (ROT, MUL, RC) is drawn daily under the AP-F4-1 redraw rule | +| Which tests depend on which axis (section 1.3) | The acceptance rule and every index statistic ((c''), (c'''), the bucket bound, the bit-bias read, the attempts census) run on the closed-form dataset and never see `m`: the mixer axis is bounded per family by adv-mixer-3's rows and F4, not per era. The width axis changes the index space of every site ((c'')'s expectation `E_s` must divide the window by the width, a spec change the harness carries). The shape and weight axes change the draw's stream and so every per-era statistic | +| The sampling bound (section 2) | With `n` eras drawn from the chain's own distribution and every one passing a per-era test, the fraction of eras that would fail it is under `3/n` at 95 percent confidence (the rule of three; Wilks 1941 for the order-statistic form): 190 eras bound the failing fraction at 1 in 64 (one era in 32 years of 180-day eras), 3,067 at 2^-10. The bound is on the TESTED property only; the union bound over the per-era tests' own false-pass rates gives the family's false-pass rate, and each test's false-pass rate is itself a rule-of-three number on its known-failed cases (the (c''') floor refused 9 of 9 live hot sets, so its miss rate on that class is under 0.33 at 95 percent: nine cases bound nothing tighter) | +| The per-era tests (section 3) | Three rings. Ring A, the chain runs per era at the cut, microseconds: the structural redraw rules (the band membership of every draw, the day-key cost rule, the product-bias rotation class recorded). Ring B, the chain runs per epoch, seconds: the acceptance rule generalised to the family's shape ((a) (b) (a') (c) (c') (c'') (c''') plus the two next-class tests, the per-site largest-256-item-bucket bound and the index-bit bias read, on the same 2^20 pass). Ring C, the gate runs offline per drawn era, box-hours: the F8-form census at 2^24 on 64 seeds, the attempts census, the exhaustion count. Each row carries its known-failed shape and its clean-seed cost so the redraw is priced | +| The board (section 4) | F1 to F10 and the nine lanes classified per-era, per-family or chain-run, with the harness taking the era draw as an input; the proof of testing is one JSON record per drawn era (the draw, the object, the binary, the seeds, every verdict with its statistic, threshold and log sha256, the core-seconds) and one family summary (eras per stratum, the worst era per test, the refuse rate per band, the bound's arithmetic) | +| The honest line (section 5) | The gate sees what its tests see. It does not see the diffuse era-stride class below the bit-bias read's resolution (a bias under 0.3 percent at 2^20), a mechanism that lives in a joint corner no stratum names, a mixer weakness below adv-mixer-3's bands, or an era whose draw sits in the untested 1 in 64. A GPU-like chip loses nothing on any era; what a corner buys it is a per-era hot set bounded at 1.002x (the floor) or 1.0024x (the diffuse class), or, at `m = 4`, a mixer with 2 applications of measured margin instead of 6 | +| Running now (section 6) | The harness `family_gate_era_census` on build-1 from 11:16 BST: one drawn era per seed, every family parameter from the era's own stream, the chain draw through the real rule keyed on the family's shape, one TSV row per era with the (c'') ratio, the bucket ratio, the bit bias and the attempts; the base control (`v5_attempts_census`, the shipped draw) beside it. The coverage table in section 6 is filled from the logs at 16:xx BST | + +## 1. The parameter space + +### 1.1 The axes, their bands and the margin each band was read from + +| Axis | Band proposed for the draw | What fixed the band (the measured rows) | The tested margin inside the band | Known-failed corner, named | +|---|---|---|---|---| +| Mixer multiplier `m` (applications per round, `LoadClass::mixer_mult`; 72 per item at `m = 8`, 8 between dependent reads) | {4, 8, 16}; the research lane's outline; this lane's reading: {8} plus {4} as a corner, {16} only after the verifier row | x4 and x8 measured (`docs/plans/mixer-x4.md` section 6.4: 1.92 and 2.79 ms per unit on a loaded M5 Max core; the daily build 42 ms at x8 on the 5090, measured); x16 estimated at about 3.7 ms per unit on the M5 Max core and 9 ms on a 2019-class core (chip-model-v3 section 3 item 1), against the 10 ms verifier gate | adv-mixer-3 (`report-mixer-3.md`, "The round margin, stated"): no statistic survives 2 of the 8 keyed applications between reads at bands 0.0015 (Q2, 2^24 states), 0.00026 (2^27), 0.00018 (Q2b, 2^28); SAT solved at k = 1 in 137 s and timed out at k = 2, 3, 4; two real days and eight random days agree. So at `m = 8` 6 of 8 applications are margin; at `m = 4` the same rows leave 2 of 4; at `m = 16` 14 of 16 | None measured. The corner is `m = 4` by margin and `m = 16` by the verifier; the all-ROT-equal day key is the day-level corner (rejected by the AP-F4-1 rule) | +| Op-mix weights (the ten non-load families, sum 75) | Each weight within B points of table 1.4.2 (add 12, xor 10, mul 8, mad 8, shfl 8, rotl 7, sub 6, mulhi 6, rotr 6, or 4), renormalised by largest remainder; shfl and mulhi never raised; B = 2 (spec 1.13.1, proposed) or B = 4 (the research lane) | The microbench (`counter-asic-4-research.md` 15.1a, the 5090 alone, 8 October): pJ per counted op at the stock clock and the 1,300 MHz lock: arx 11.3 / 6.2, mul 13.9 / 8.3, mulhi 39.6 / 21.0, prmt 22.3 / 11.5, lop3 24.1 / 13.0, shfl 55.8 / 29.4; the shuffle is 4.9x the add, so a draw that raises shfl raises the card's premium per instruction with no better `k` for a chip (15.1b). F7's era census: the op-weight corners (15 to 31 of 75) read 1.0x against the GPU, 0 memory effect | The acceptance's rejection rate moves with the lossy share: at the table 0.68 per candidate ((a') 83.5 percent of rejections; adv-accept row 90, 20,000 seeds); the F7 census at B = 2 read every corner clean for the chip; nothing was measured at B = 4 before today (section 6) | The lossy corner: or, mul and mulhi all at +B. It raises (a') rejections and so the attempts per seed; the exhaustion bound `r^256` is the number to read there (section 3, ring C) | +| Read width `W` (words per load) | {1, 4} | `docs/plans/read-width.md` (5 October): w16 within the rules (5090 139.8 against 136.1 MH/s, 9070 XT 17.90 against 18.15, M5 Max within 1 percent); w64 bandwidth-bound (5090 share 0.58, 71.9 MH/s): out; the per-load mixes out on the 5 percent spread rule | The acceptance runs unchanged on aligned addresses (read-width.md section 2), but (c'') and (c''') read a site's distinct ALIGNED indices against `E_s = N - N^2 / 2W_s`: at `W = 4` the index space is `W_s / 4`, so the expectation must follow or every width-4 program reads 0.976 at a quarter window and is refused by the 0.98 floor. The harness divides the window by the width (`site_window_words`); the spec line is owed | `W = 16` (w64): excluded by measurement, never in the band | +| Shadow block shape (instructions per block, passes per iteration) | {64 x 108, 128 x 54, 256 x 27}: 6,912 shadow instructions per iteration at rung 0 | 64-instruction blocks ran 2.5 to 3.5 percent faster than 256 on the 5090 and the M5 Max (6 October, measured); 1,024 cost the M5 Max 17 percent (out) | F1's shadow redundancy bound (3.0 percent of peephole-removable instructions, the v5 generator's `SHADOW_REMOVABLE_MAX_PERMILLE`) was set from F1's census at 256 instructions; the removable fraction per block is a property of the block's length, so the fraction must be re-read at 64 and 128 (a per-family row). The acceptance's (a') fixpoint and the shadow's execution in (c) take any length | The per-load placement (16 sub-blocks of 16 after each load): dead as a chain class (`counter-asic-4-research.md` 20.2a-close): 22 of 1,621 candidates accepted, 42 of 64 seeds exhaust 32 attempts, candidate 0 carries index bit 0 set in 40 of 1,024 addresses at site 0 (z 29.5). The placement axis therefore has ONE value in the band | +| Program length `N` (counted ops per hash) | Not drawn: the ladder's signal (rungs 0 to 2); the research lane's outline keeps it so | F6: the worst of 10^5 class v4 programs 8.708 ms on the half-core proxy, so N about 300,000 fits under 10 ms (rung 2 admissible, rung 3 not); the M5 Max loses 3.3 to 10 points across the band (measured ladder) | The verifier's worst case was censused at rung 0 only; a draw inside the ladder needs the 10^5-program worst case at the top rung (per-family row) | Rung 3 (inadmissible by F6) | +| Era stride and interleave (`M` odd, `R` in 1..31, `pos` four ascending bit positions, the fold rotations, the per-site windows `k_off`, `o`) | As spec 1.13.1 draws them today | F7's 2^24 era census (stride bijective, R, pos, M uniform, no class over 1.1x); adv-cache-2 section 2.3: the same 32 base programs read 2 of 32 with a site over 1.04x under `R = 29` and 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), because `rotl(x * M, R)` places a product's biased low bits (P(bit 0) = 1/4) at address bits R and up, inside the 28-bit index unless R is 29 or 30; at D = 29 only R = 30 and 31 cut bit 0 | The whole 64-seed F8 census is a census over drawn eras (each f8 seed carries its own era), so the per-era uniformity verdicts of sub-version 3 and class v5 (60 of 64 and 61 of 64 under 1.2x) already sample this axis; the devnet's clean reading at R = 29 is the accident, the drawn-era figure the chain's | R in 1..27 with a product as the last writer of a load's source (sub-class A); the warp-uniform mulhi source (sub-class B, 1 in 16,000 warps) | +| Dataset size `D` (layer 2) | 2^28 words today, 2^29 at the 2 GiB genesis step, growing on the 1.13.3 schedule with the state as a floor | The acceptance's closed form is pinned at D = 28 (`ACCEPT_DATASET_LOG2`); the live dataset is larger; the stand-in gap measured at 0.0004 under D = 28 (adv-accept Q2, 54 programs) | Unmeasured at D = 29: which R values hide the product bits changes with D, and the window cap `min(k_off, D - 26)` changes the per-site windows | D at a value where the acceptance's D = 28 windows and the live windows disagree: the stand-in gap row of ring C | +| Day key (ROT x 8, MUL x 16, RC x 16, drawn daily from the day seed) | As spec 1.8.4, under the AP-F4-1 redraw rule in class v5 (cost A at most 205 rejected, k >= 1, the eight ROT equal rejected) | F4 and adv-mixer-2: 0 of 2^24 days over 1.1x on both metrics with the rule (8ca66afa); 5.69e-4 of days over 1.1x on LUT area without it, 15 days a century, worst 28 April 2050 at 1.113x | The rule is per day and chain-run; it does not depend on `m` (the cost is per application) | Day 29,337 (redrawn under the rule); the planted mul1all and mulnaf days fire | + +### 1.2 The joint space and what a draw covers + +Counting the discrete axes alone: 3 (m) x 2 (W) x 3 (shape) x the weight perturbations ((2B + 1)^10 before the caps: about 9.8 million at B = 2, 3.5 billion at B = 4) x 31 (R) x 2^31 (M) x 1,820 (pos) x 31^6 (the fold rotations). The space is of order 2^80 before the per-site windows, which are per program. No census walks it. What a census can do is (i) draw eras from the chain's own distribution (the era stream over random `E_n`) and bound the fraction of eras that fail a test (section 2.1), and (ii) pin the axes that carry a KNOWN mechanism at their corner and draw the rest (section 2.3), so a mechanism that depends on one named axis is read at its worst value. A mechanism that depends on a joint corner nobody named is in the honest line (section 5). + +### 1.3 Which tests see which axis + +| Test | `m` | weights | `W` | shape | N | era stride, windows | D | day key | +|---|---|---|---|---|---|---|---|---| +| The acceptance rule and the index statistics ((c''), (c'''), bucket, bit bias), on the closed form | no (the mixer never runs) | yes (the stream) | yes (the index space) | yes (the stream, the shadow's execution) | yes (the shadow's passes) | yes (`load_index`) | no (D = 28 pinned) | no | +| The attempts census and the exhaustion bound | no | yes | yes | yes | yes | yes | no | no | +| The F8-form census at 2^24 on the live dataset | yes (the item words) | yes | yes | yes | yes | yes | yes | yes | +| adv-mixer-3's distinguisher rows, F2, F4, adv-mixer-2 | yes | no | no | no | no | no | no | yes | +| F6 verifier worst case | yes | yes | yes | yes | yes | no | yes (the fill) | no | +| F1 shadow redundancy | no | yes | no | yes | yes | no | no | no | +| F3, adv-cache, adv-cache-3 (the chained cache) | no (the cache fill is ChaCha12) | no | no | no | no | no | yes (the cache doublings) | yes | +| F7 era census | no | yes (the perturbation) | yes | no | no | yes | no | no | +| F5 chip model, F10 ladder | the band's top | the band's dearest mix | yes | no | the ladder | no | yes | no | + +Reading: the per-era statistical tests are blind to `m` by construction, so the mixer is a per-FAMILY axis with three values and is closed by re-running adv-mixer-3's ladder and F4 at `m = 4` and `m = 16` (section 4), not by drawing eras. The weights, the width and the shape are per-era axes and are what the drawn-era census of section 6 walks. + +## 2. The sampling bound + +### 2.1 Zero failures in `n` eras (the rule of three, Wilks) + +Let a per-era test have a fixed verdict per era and let `p` be the fraction of the family's eras (under the chain's own draw) that fail it. If `n` eras drawn independently from that draw all pass, then with confidence `1 - alpha`, `p <= eps` where `(1 - eps)^n = alpha`, that is `n >= ln(alpha) / ln(1 - eps)`, about `3 / eps` at 95 percent and `4.6 / eps` at 99 percent (Hanley and Lippman-Hand 1983; Wilks 1941 gives the same arithmetic as the one-sided nonparametric tolerance limit on the worst order statistic). The table, with the era length of layer 3 (180 days) turned into years: + +| `eps` (the failing fraction bounded) | One failing era expected every | `n` at 95 percent | `n` at 99 percent | +|---|---|---|---| +| 1/16 | 8 years | 45 | 70 | +| 1/64 | 32 years | 190 | 293 | +| 1/256 | 126 years | 766 | 1,177 | +| 2^-10 | 505 years | 3,067 | 4,713 | +| 2^-20 | the F4 and F7 gate's fraction | 3.1 million | 4.8 million | + +What this buys and does not. The F4 and F7 gates ask "no class with gain over 1.1x at a fraction over 2^-20" and reach it by censusing 2^24 draws of a CHEAP statistic (microseconds per day key or era seed). A per-era test that costs box-hours (the F8 census at 2^24) can be run on hundreds of eras, so it bounds the failing fraction at the 1/64 to 1/256 class, never 2^-20. That is why layer 4 puts the tests on the chain: a per-era test the chain runs on EVERY era (ring A) or every epoch (ring B) needs no sampling bound at all; the offline census (ring C) is then a check on the chain-run tests' calibration (their clean refuse rate and their known-failed firing per stratum), and a reading of the one statistic the chain cannot afford, the live-dataset census. + +### 2.2 The union bound over the per-era tests + +Let the chain run tests `T_1 .. T_k` on every era or epoch, and let `delta_i` be the probability that `T_i` passes an era (or program) that carries the failure class `T_i` exists for. The family's false-pass rate on the union of those classes is at most `sum delta_i`. Each `delta_i` is itself bounded by the rule of three on the test's known-failed cases: a test that fired on `f` of `f` known-failed cases has `delta_i <= 3 / f` at 95 percent. The numbers today: + +| Test | Known-failed cases it fired on | `delta` at 95 percent | Source | +|---|---|---|---| +| (c''') floor at 0.995 on the few-item hot-set class | 9 of 9 live hot sets refused (minimum sites 0.9809 to 0.9919), both single-item programs refused | under 0.33 | adv-accept, "the floor's final tally", 01:13 BST 8 October; class-v5 section 14 | +| (c'') floor at 0.98 on the low-entropy band | 5 of 5 (p23, p18, p19, p15, p56) | under 0.60 | attack-pass-2026-10.md, sub-version 3 | +| (a') freshness on the lineage-visible constant class | 11 of 11 (sub-version 1's eleven seeds under 1.2x on sub-version 3) | under 0.27 | attack-pass-2026-10.md, the sub-version 1 table | +| The bucket bound (in sigma of the bucket's expectation at 2^20) on the quarter-bit class | 4 of 4 would be caught (p4, p8, p10, p34: largest bucket 3.1x to 5.6x at narrow windows, +17 to +37 sigma), not yet wired as a rule | under 0.75 once wired; the clean spread is measured in section 6 | the hash lane's attribution, 09:46 BST 8 October | +| The index-bit bias read on the product class | 3 of 3 named sites (Devnet 3 site 0 at P(bit 0) = 0.25; era-drawn-28 site 15 at 0.778; the per-load candidate 0 at z 29.5), and 7 of 7 in the 16-era smoke run at 130 to 511 sigma | under 0.30 on ten cases; but the read is a record, not a refusal (section 3.2) | adv-cache-2 2.3; counter-asic-4-research.md 20.2a; section 6 | +| The day-key cost rule | the planted mul1all and mulnaf days, day 29,337 | 0 of 2^24 days over 1.1x after the rule (a census, not a case count) | f4-weakday.md, 8ca66afa | + +Reading: the per-test miss rates are bounded by HANDFULS of known cases, so the union bound today is a loose number (the sum exceeds 1). The way to tighten it is not more eras but more known-failed cases per test, which the adversarial sweeps supply cheaply: adv-accept's tail holds 22 programs beyond the 1.2x gate of 37 measured live, and the drawn-era census of adv-cache-2 holds 19 biased sites of 1,056. A test with 60 fired cases has `delta` under 0.05; with 300, under 0.01. The proof of testing (section 4.3) therefore carries, per test, the count of known-failed cases it fired on, and that count is the number a reader checks first. + +### 2.3 Stratified draws over the corners + +The axes with a known mechanism and their corner values: `m` in {4, 16} (margin, verifier), weights at the lossy cap (or, mul, mulhi at +B) and at the table, `W` in {1, 4}, shape in {64, 256}, R in {1..27} against {28..31} (the product-bias class visible or hidden; at D = 29 the hidden set is {30, 31}), the windows forced to quarter (`k_off = 2` at every site, the F8 tail class), D in {28, 29}. That is 2 x 2 x 2 x 2 x 2 x 2 x 2 = 128 corner cells for the per-era statistics (the mixer cells are per-family rows), plus the random stratum (every axis drawn). The plan: at least 8 eras per cell for the cheap ring-B statistics (1,024 eras, about 2 core-hours each at the (c''') cost, 2,000 core-hours, 64 box-hours of 32-core slots) and the random stratum at 3,000 eras (the 2^-10 line of 2.1 at 95 percent for the ring-B tests, 6,000 core-hours, 190 box-hours); the live-dataset census at 2^24 on 64 seeds for 24 corner representatives and 64 random eras (88 eras at 45 to 95 core-hours each, about 6,000 core-hours, 190 box-hours). About 450 box-hours in all, 2 to 3 days of both boxes at the 88-core pool, inside the testnet period by a wide margin. Section 6 records what has run. + +## 3. The per-era automatic tests (layer 4) + +The three rings. A test's ring says who runs it and what a failure costs. + +| Ring | Who runs it, when | Cost per run | What a failure does | +|---|---|---|---| +| A: structural, per era | every node at the era cut, on the drawn parameters | microseconds | the era stream's next block of draws is consumed (a redraw), up to a cap, then the base table (the class v4 values) as the last resort, so the draw is total and no consensus path panics (the AP-F8-2 shape) | +| B: the acceptance, per epoch | every node at the epoch draw, on each candidate | about 2.2 s per chosen candidate on one box core at 2^20 (the (c'') pass), plus 0.3 s for the 64-unit parts; the two next-class tests ride the same 2^20 pass | the next attempt, as today; the cap 256 and the last resort unchanged | +| C: offline, per drawn era | the family gate on the boxes, before the testnet and through it | box-hours | a finding against the family's band (a band narrowed, a rule added), never a chain event | + +### 3.1 Ring A: the structural rules the chain runs per era + +| Rule | Draw it reads | Known-failed shape | Clean refuse rate | Source | +|---|---|---|---|---| +| Band membership: `m` in the band, `W` in the allowed set, the shape in the set, every weight within B of the table with shfl and mulhi at or under their base, the sum 75 | the layer-1 draws | a draw outside the band (a unit test) | 0 by construction (the draw is bounded) | spec 1.13.1's form | +| The day-key cost rule (AP-F4-1, class v5) | ROT, MUL | mul1all, mulnaf, day 29,337 | 6.1e-4 per day | f4-weakday.md 6.7 to 8; 8ca66afa | +| The rotation class recorded: whether R leaves a product's low bits inside the index at the era's D | R, D | none (a record, not a refusal: restricting R to {29, 30} would cut the interleave's entropy from 31 to 2 values; the value-level test of ring B is the catch) | 0 | adv-cache-2 2.3 | +| The weights' lossy share bound: or + mul + mulhi at most the table's 18 plus B, so the exhaustion bound `r^256` stays under 1e-18 (r under 0.85) | weights | the lossy corner of section 6 if its `r` reads over 0.85 | 0 by construction | row 90 (r = 0.681 at the table) and section 6 | + +### 3.2 Ring B: the acceptance rule generalised to the family, per epoch + +| Part | Generalisation | Known-failed shape (fires today) | Clean refuse rate (the cost) | Per-candidate cost | +|---|---|---|---|---| +| (a) (b) | unchanged | the class v2 census vectors (22, 37, 51) | 11.6 and 3.0 percent of rejections | microseconds | +| (a') the freshness fixpoint over base then shadow | keyed on the family's shape (`is_family_shape`: shadow in {64, 128, 256} at 6,912 per iteration, `m` in {4, 8, 16}, the mix one-hot on the drawn width) in place of the one class v4 shape, in the draw's source rule and the acceptance alike | sub-version 1's eleven seeds | 83.5 percent of rejections (57.5 percent of candidates) | microseconds | +| (c) the dynamic test with the shadow executed | the interpreter already runs any block length, any pass count and any width (the fold) | p23 at attempt 1 (the shared-operand idiom) | 0.9 percent | about 3 ms (64 units) | +| (c') saturated sources | unchanged | the forced-saturation plant | 0.05 percent | in (c) | +| (c'') the distinct-index ratio at 0.98 | `E_s = N - N^2 / (2 W_s / W)`: the window divided by the width | p15, p18, p19, p56 | 1.1 percent | 2.2 s at 2^20 | +| (c''') the hot-item floor at 0.995 | the same `E_s`; the floor's clean spread re-read per stratum (section 6): a fixed 0.995 under a spread that moves with the shape or the width is either a liveness cost or a miss | seed 100767 (0.9919) and the nine live hot sets | 2.435 percent of accepted class v4 programs, +0.045 on the mean attempt | in the (c'') pass | +| The per-site largest-256-item-bucket bound (NEW, the F8 tail's catch) | the largest count over a site's 4,096-word buckets in its window against `N / (W_s / 4096)`, in SIGMA of the bucket's expectation (`(max - E) / sqrt(E)`), refused above a band set from the clean spread. The ratio alone cannot carry the bound: a clean full-window site's largest of 65,536 Poisson(16) buckets reads 2.1x at +4.4 sigma, a quarter-window site's largest of 16,384 Poisson(64) buckets 1.5x at +4 sigma (the 16-era smoke run read ratios 2.2 to 2.4 on clean sites); the four tail seeds' 3.1x to 5.6x at narrow windows are +17 to +37 sigma | p4, p8, p10, p34 | measured in section 6 (the columns `bucket_z_max`, `bucket_win`) | one linear pass over the (c'') indices | +| The index-bit bias read (NEW, adv-cache-2's value-level test) | per site, the one-count of each free index bit (bits above the width's alignment and below the window's cut) over the 2^20 evaluations, in sigma (`sigma = sqrt(N) / 2 = 512`); a 6-sigma band is a bias of 0.3 percent at 2^20 (the product law's bit 0 at 25 percent reads z about 512, bit 1 at 3/8 z 256, bit 3 at 3.1 percent z 64, bit 6 at 0.4 percent z 8, bit 7 at 0.2 percent z 4: passes). MEASURED on the first 16 drawn eras (11:21 BST, section 6): 7 of 16 accepted programs carry one site with a bias of 130 to 511 sigma at address bit R or R + 1 (the era's rotation), the era-stride class exactly, on programs (c''') passes at 0.9954 to 1.0000; the 9 others read under 3.8 sigma. So as a REFUSAL the read would redraw about 40 percent of epochs; its right use is as a record per era plus the structural lever (fold the product's low bits in `load_index` before the rotation, a next-class item), and the chip price is stated in section 5 | Devnet 3 site 0, era-drawn-28 site 15, the per-load candidate 0; and now the 7 of 16 | 7 of 16 at 6 sigma (a refusal is not the form); 0 of 16 at a 600-sigma band | one pass over the indices, 28 bit tests each | +| The cap and the last resort | unchanged at 256; the last resort's own verdict is adv-accept-3's finding 1 (9 percent of last-resort programs fail (a)); the family keeps the open fix (continue past 256 until one passes) | the reject-everything mirror | 0 reached in 1.02 x 10^6 seeds | n/a | + +### 3.3 Ring C: the offline tests per drawn era + +| Test | What it reads | Known-failed shape | Clean cost per era | Sample needed for its own verdict | +|---|---|---|---|---| +| The attempts census (row 90's form) | every candidate of each seed's chain draw through the real rule; `r` per candidate, the parts' shares, the attempt histogram, `P(exhaust) = r^256`, 0 at the cap | the forced-exhaust plant (hits the cap, prints the last resort); the per-load class (r about 0.98) | 1,000 seeds: 202 s on 23 threads at the table (1.3 core-hours); about 5 core-seconds per accepted program with (c''') | 1,000 seeds per stratum reads `r` to 0.01 | +| The F8-form uniformity census at 2^24 on the live dataset | the item histogram against the window model (the program's own 16 draws under the era's windows at the era's D), the top 0.1 percent within 1.2x, the hot-set test `X_f >= f`, the 6-sigma largest bucket, the per-site attribution | quarter-lines, half-lines, const-item (the plants); p31 (29.27x), p23 (4.82x) | 42 to 95 core-minutes per seed at 2^24 (the two halves of 32 on build-2 took 41 to 46 minutes at 30 to 32 cores; the 64 seeds of sub-version 3 took 69 minutes of the box); 64 seeds about 45 to 100 core-hours | 64 seeds per era bound the fraction of epochs over 1.2x at 3/64 (4.7 percent) at 95 percent: a calibration of ring B, not a hot-set hunt (adv-accept's sweep found 9 hot sets in 796,042 draws, 1e-5, every one refused by the floor) | +| The stand-in gap at the era's D | the (c'') and bucket statistics on the closed form at D = 28 against the live dataset at the era's D on the same programs | none yet (the gap read 0.0004 at D = 28; a D where the windows disagree is the plant to build) | one 2^24 run per program, about 1 core-hour; 54 programs per era class | per D value, not per era | +| The exhaustion count at scale | 10^4 to 10^5 chain-shaped seeds per stratum | the per-load class | 1.45 s per seed (F9's chain path): 4 core-hours per 10^4 | 10^5 per lossy corner reads the past-31 tail | + +## 4. The board over the testnet period + +### 4.1 F1 to F10 and the nine lanes, classified + +| Row | Harness input | Class | Per what | Cost per run | Note | +|---|---|---|---|---|---| +| F1 shadow redundancy | the shape (block length, passes) | per family | each of the three shapes | 10^4 programs at 5 core-seconds each (the (c''') draw): 14 core-hours; 10^5: 140 | the 3.0 percent `SHADOW_REMOVABLE_MAX_PERMILLE` re-read per shape | +| F2, adv-mixer, adv-mixer-3 (the round margin) | `m`, the day | per family | `m` in {4, 16} on 10 days each | index census 2^32 t about 7 core-hours per k per day; sac at 2^24 similar; SAT 1 core-hour per k | at `m = 4` the gate "no distinguisher beyond 2 of m" leaves 2 of 4 | +| F3, adv-cache, adv-cache-3 (the chained cache) | the cache log2 (layer 2's doublings) | per family | each cache size step | minutes (the closure search), the curve by arithmetic | the fill is not drawn | +| F4, adv-mixer-2 (the weak day) | `m`, the day key | per family and chain-run per day | 2^24 days per `m` | 379 s on 12 cores (1.3 core-hours) | the rule is chain-run; the census is its calibration | +| F5 chip model | the band's top (`m = 16`, the dearest mix, `W = 4`, rung 2) | per family | once per band | minutes | the premium row per corner | +| F6 verifier worst case | `m`, shape, `W`, N, the fill at D | per family | the top corner (`m = 16`, rung 2, `W = 4`) | 10^5 programs timed on the half-core proxy: about 100 core-hours | the x16 row decides whether 16 enters the band | +| F7 era census | the era draw with the layer-1 draws added | per family | 2^24 era seeds | minutes | stride bijective, R, pos, M, the weights' corners uniform | +| F8 uniformity | the era (every axis) | per era (ring C) and chain-run per epoch (ring B) | 64 seeds per drawn era | 45 to 100 core-hours | section 3.3 | +| F9 acceptance edges, grinding, exhaustion | the era | per era (the exhaustion count) and per family (the 5090 grinding row) | 10^4 seeds per stratum | 4 core-hours | the GPU row once per band | +| F10 ladder monotonicity | N | per family | once | the fast-time harness, minutes | unchanged by the draws | +| adv-cache-2 (hot set, era stride) | the era | per era | 32 drawn programs at 2^23 | 0.7 core-hours per program | the value-level read is ring B now | +| adv-accept, adv-accept-2, adv-accept-3 | the era | per era (the sweep and the attempts census) and per family (the A6000 header row) | as the attempts census | as above | the last-resort fix is the family's | + +### 4.2 The testnet period as the window + +Before the first miner: the per-family rows at the corners (F1 at three shapes, the mixer ladder at `m = 4` and 16, F4 per `m`, F6 at the top corner, F7 with the new draws), and the ring-C census on the corner cells and the random stratum of section 2.3. Through the period: every era the chain actually draws is a drawn era of the census (the chain's own eras are the best sample, the one the rule of three speaks about), so the F8-form census at 2^24 runs on each live era within its first day, and the attempts census on each; a live era that fails ring C is a finding against the band, filed and priced, never a chain event (the chain's ring-A and ring-B tests already passed it). The board's verdict at the end of the period: the count of live eras drawn and passed, the corner cells drawn and passed, the worst reading per test, the refuse rate per stratum, and the bound's arithmetic from those counts. + +### 4.3 The proof of testing (the published format) + +One JSON record per drawn era, in `docs/analysis/class-v6/gate-records///.json`, the shape of `docs/plans/counter-asic-3-gate/*.json`: + +``` +{ "family": { "id": "", "spec": "docs/spec/01-lottery-hash.md@", "object": "igneum-pow@" }, + "era": { "label": "igneum-family-gate/era/", "stratum": "random | lossy-cap | w4 | shape64 | ...", + "draw": { "m": 8, "weights": [12,10,8,8,8,7,6,6,6,4], "width_words": 1, "shape": [256, 27], "R": 17, "M": "0x9ad30d99", "pos": [0,2,12,13] } }, + "harness": { "binary": "", "box": "igneum-build-1", "lease": "", "started": "", "ended": "", "core_seconds": 7210 }, + "tests": [ { "name": "attempts-census", "seeds": "igneum-family-gate/program//epoch/0..999", "r": 0.681, "parts": {"a_prime": 0.835, ...}, "max_attempt": 28, "exhausted": 0, "verdict": "PASS", "log": "", "log_sha256": "" }, + { "name": "c3-floor", "floor": 0.995, "min_ratio": 0.9962, "min_site": 6, "verdict": "PASS", ... }, + { "name": "bucket-bound", "bound": 2.0, "max_ratio": 1.31, "verdict": "PASS", ... }, + { "name": "bit-bias", "band_sigma": 6, "max_z": 2.4, "verdict": "PASS", ... }, + { "name": "f8-census-2e24", "seeds": 64, "over_1.2x": 2, "worst": 1.38, "hot_sets": 0, "verdict": "PASS", "known_failed_fired": ["quarter-lines", "const-item"], ... } ], + "label": "internal research, not an independent review" } +``` + +And one family summary per board cut, `docs/analysis/class-v6/gate-records//summary.md`: eras drawn per stratum; per test the count passed, the worst reading, the refuse rate, the known-failed cases fired (the count that bounds `delta`); the rule-of-three line per test (`3 / n` at 95 percent); the union bound's sum; the box-hours; the list of corner cells not reached. A reader checks the record by re-running one era from its label with the pinned binary; every number in the summary is a count over the records. + +## 5. The honest line + +What the family gate cannot see, and how a chip would use it. + +| Blind spot | Why the gate misses it | What a chip gets from it | Bound today | +|---|---|---|---| +| The era-stride class, measured today at the bit level on 7 of 16 drawn eras (section 3.2): not diffuse, a 25 percent bias on ONE address bit (bit R, the product's bit 0 through `rotl(x * M, R)`) at one site, on programs every floor passes | the (c''') floor reads distinct counts, which a one-bit bias barely moves (0.9954 to 1.0000 on the seven); the bit read sees it at 130 to 511 sigma but refusing it would redraw about 40 percent of epochs; the class is structural (`load_index`'s form and the weights' products), so the catch is a next-class change to the address form, not a per-era floor | a store holding the favoured half of that site's window (128 MiB at D = 28) serves 75 percent of that site's reads instead of 50: 25 percent of 1/16 of a hash's reads, about 1.6 percent of reads at f = 1/2 from one site in about 40 percent of eras (arithmetic on the measured bias); the honest partial-store curve already costs 1.26x the ops at f = 1/2 (adv-cache-2 Q4), so the f = 1 verdict stands; the top-0.1-percent reading of the ledger (1.0024x) was the same class seen through the coarser instrument | the per-era record (ring A names the rotation class; ring B logs the bit read); the structural fix is the family's first owed item for the research lane | +| A joint corner no stratum names | the 128 cells pin the axes with a KNOWN mechanism; a mechanism that needs, say, a particular `M` with a particular weight table and a particular shape is reached only by the random stratum, which bounds its fraction at 3/n | one era (180 days) of whatever the corner is worth, at most once per occurrence | 1/64 to 1/256 of eras untested at 95 percent (section 2.1); the chain-run rings catch the known shapes on every era | +| The mixer below adv-mixer-3's bands | biases under 0.00018 (Q2b), correlations under 0.00073 with multi-bit masks, differentials under 2^-19, any structure a SAT model of 2 or more applications would expose; at `m = 4` the measured margin is 2 applications | a shortcut that saves applications against the 9,360 ops per item; none found at any k | the round margin, stated; `m = 4` is the corner that spends 4 of the 6 measured spare applications | +| The verifier at `m = 16` and rung 2 on a 2019-class core | unmeasured (an estimate of 9 ms against the 10 ms gate) | nothing for a chip; a node tier retired if the corner is drawn | the row is owed before 16 enters the band | +| The acceptance's stand-in at D = 28 against a live D = 29 | the windows cap `min(k_off, D - 26)` and the rotation's cut set move with D; the gap is measured at D = 28 only | a per-site concentration the closed form does not reproduce | 0.0004 at D = 28; unmeasured at 29 (ring C row) | +| The union bound's own looseness | the per-test miss rates rest on 3 to 11 known-failed cases each (section 2.2), so the family's false-pass rate is not yet a number under 1 | nothing new; the bound is on what the gate claims, not on the hash | fixed by cases, not eras: 60 fired cases per test for `delta` under 0.05 | +| The last-resort program | 9 percent of last-resort programs fail (a) and are handed out unchecked; a lossy-corner era that raised `r` toward 0.95 would reach it at 2e-6 per epoch | a program that re-reads one address in two loads of the same hash | ring A's lossy-share bound keeps `r` under 0.85 (`r^256` under 1e-18); the fix (continue past 256) is owed to the rule's owner | +| The era redraw's own grindability | a ring-A redraw consumes the stream's next block, so an adversary who could steer `E_n` could steer which block is used; the era VDF of F7 (517 s on the fastest prover, 259x the window) closes the steering of `E_n` itself | nothing beyond F7's bound | F7 (a) PASS with the VDF in the node | + +A GPU-like chip (the `f = 1` stored-dataset chip with a programmable core, chip-model-v3 section 5) loses nothing on any era of the family: every drawn parameter is firmware to it, and what the family costs it is the core sized for the band's top (the research lane's USD 30 to 60 per chip, modelled). The family gate's job is therefore not to defeat that chip (the identity of the research file's section 2 says the per-joule edge is the card's own idle, 2.1x at `k = 1`) but to make sure no drawn era hands ANY chip more than the one hash did: a per-era hot set, a per-era mixer shortcut, a per-era verifier miss. Everything in this document is a bound on that increment, and the increments found so far are 1.002x and 1.0024x. + +## 6. Running now, and the coverage measured + +Started 11:1x BST, 8 October 2026, on igneum-build-1 under `lease pool` (class measure, owner class-v6-family-gate), the scripts under `/srv/builds/_adv-family-gate/` (fg-setup.sh, fg-build.sh, fg-census.sh), every binary run from a pinned copy under `bin//` with its sha256 (AP-H2's rule), logs and TSV rows under `logs/`, copies of the finished logs land under `docs/analysis/class-v6/logs/` on this branch with the full report. + +| Run | What | Where | State | +|---|---|---|---| +| base | `v5_attempts_census` (the shipped class v5 draw: shape 256 x 27, `m = 8`, `W = 1`, the table weights) over f8-label seeds 1,000 to 11,000, each seed its own drawn era (M, R, pos, windows) | build-1, 24 cores, binary 4bec799c (8f481459 unmodified) | running from 11:16 BST | +| fg1 random | `family_gate_era_census` with every axis drawn (shape in {64, 128, 256}, `m` in {4, 8, 16} recorded, `W` over {1, 4}, weights at B = 4 with shfl and mulhi never raised) | build-1 | the harness built at 11:2x BST; the smoke run and the chunks follow | +| fg1 corners | the same harness pinned per cell: `IGNEUM_FG_LOSSY_CAP`, `IGNEUM_FG_WIDTH=4`, `IGNEUM_FG_SHAPE=64`, the combinations | build-1, build-3, build-4 as the pool frees | queued | + +The coverage table (filled from the TSV rows at 16:xx BST for the 17:00 cut; the full read at 09:00 BST tomorrow): + +| Stratum | Eras drawn | `r` per candidate | Mean attempt, max | Exhausted | min (c'') ratio (the worst era) | Under 0.995 (the (c''') refuse rate on the accepted draw) | Largest bucket ratio (worst era, site) | Largest bit bias in sigma (worst era, site, bit) | +|---|---|---|---|---|---|---|---|---| +| base (shipped draw) | pending | | | | | | | | +| random (every axis drawn) | pending | | | | | | | | +| lossy cap | pending | | | | | | | | +| W = 4 | pending | | | | | | | | +| shape 64 | pending | | | | | | | | + +## 7. Owed by 09:00 BST on 9 October (the full report) + +1. The coverage table of section 6 filled from the logs, with the per-stratum refuse rates and the union-bound arithmetic on the measured numbers, and the TSV rows and logs under `docs/analysis/class-v6/logs/`. +2. The clean spread of the bucket ratio and the bit bias per stratum, so the two new ring-B tests get a bound and a clean refuse rate (not a guess). +3. The lossy-corner `r` against the 0.85 line, and the exhaustion count at 10^4 seeds on that corner. +4. The width-4 reading of (c'') and (c''') with the divided expectation, and the spec line for 1.4.6.5. +5. The mixer rows at `m = 4` and 16 (adv-mixer-3's index and sac at k = 2 on two days; the SAT at k = 2) as the per-family corner rows, if the boxes have the cores after the other lanes' jobs arrive; else the plan with its hours. +6. The F8-form census at 2^24 on 64 seeds of one lossy-cap era and one width-4 era, the first ring-C rows on the family (about 2 box-hours each). +7. The gate-record JSON written for every era of the census from the TSV (the format of 4.3), and the summary. + +## 8. Sources + +In-tree (the mirror's master and lane branches at 8 October 2026, 11:00 BST): `docs/plans/cryptanalysis/in-house-pass.md` (sections 13 and 14, the nine lanes' close); `docs/analysis/attack-pass-2026-10.md` (F1 to F10; the sub-version 1, 2 and 3 re-gate tables; the tail attribution of 8 October, 09:40 to 09:46 BST); `docs/analysis/cryptanalysis/report-mixer-3.md` on branch adv-mixer-3 at 981bfff2 (the round margin); `docs/analysis/cryptanalysis/report-chained-cache-2.md` on adv-cache-2 at bfc3746c (section 2.3, the era-stride table); `docs/analysis/cryptanalysis/report-acceptance-rule-3.md` on adv-accept-3 at 7826d2b2 (Q1, Q1b); `docs/analysis/cryptanalysis/report-acceptance-rule.md` on adv-accept at 8f188e5a (row 90, the floor's tally, gap-deep); `docs/spec/01-lottery-hash.md` 1.4.6, 1.4.7, 1.8.4, 1.13; `docs/design/class-v5-stored-state.md` on class-v5 at 8f481459 (sections 11 and 14) and `docs/design/class-v5-harness/` (v5-attempts-census-1000.log, v5-census-4600-0.log); `docs/plans/counter-asic-3-status.md` section 7c; `docs/plans/read-width.md`; `docs/analysis/counter-asic-4-research.md` on counter-asic-4 at 7a133d76 (15.1a, 15.1b, 20.2a, 20.2b, 20.3); `docs/design/class-v6-rotating-family.md` on the same branch (the outline). + +Public, read 8 October 2026: + +- Hanley, J. A. and Lippman-Hand, A., "If nothing goes wrong, is everything all right? Interpreting zero numerators", JAMA 249(13), 1743 to 1745, 1983; the rule of three as a one-sided 95 percent bound 3/n on a binomial rate with zero events in n trials: https://en.wikipedia.org/wiki/Rule_of_three_(statistics) +- Wilks, S. S., "Determination of Sample Sizes for Setting Tolerance Limits", Annals of Mathematical Statistics 12(1), 91 to 96, 1941; the nonparametric tolerance limit on the extreme order statistic, the same arithmetic as 2.1: https://www.projecteuclid.org/euclid.aoms/1177700380 +- Böhme, M., "STADS: Software Testing as Species Discovery", ACM TOSEM 27(2), 2018; the Good-Turing estimate `f_1 / n` of the discovery probability as the residual-risk bound of a testing campaign with no finding (the fuzzing-coverage view of section 2): https://arxiv.org/abs/1803.02130 +- OSTIF, "Four audits of RandomX for Monero and Arweave have been completed: results" (2019; Trail of Bits, X41 D-SEC, Kudelski Security, Quarkslab; no critical finding; the one-round AES diffusion and the BLAKE2 rows): https://ostif.org/four-audits-of-randomx-for-monero-and-arweave-have-been-completed-results/ +- Quarkslab, "Security audit of Monero RandomX" (2019; the "alternative configurations" caveat: the audits bounded the shipped configuration, which is the single-member reading this document generalises): https://blog.quarkslab.com/security-audit-of-monero-randomx.html +- Least Authority, ProgPoW algorithm audit (final report 9 September 2019; the Ethereum Cat Herders, the Ethereum Foundation and Bitfly as clients): https://leastauthority.com/blog/2019/09/09/ +- The hardware audit of ProgPoW (Bob Rao, 2019; "works well against conventional ASIC strategies", the memory-intensive threat kept open), as reported: https://criptonoticias.com/mineria/desarrolladores-ethereum-presentan-resultados-auditoria-progpow diff --git a/tools/ci/export-exclude.txt b/tools/ci/export-exclude.txt index 76af5a1a3..a98631b4c 100644 --- a/tools/ci/export-exclude.txt +++ b/tools/ci/export-exclude.txt @@ -19,3 +19,5 @@ docs/analysis/mission # copied logs are research and operations documents, not public export; the public text is the served sentence main landed. docs/analysis/cryptanalysis docs/plans/cryptanalysis +# 8 October 2026: the class v6 family-gate research record and its census logs (lane records, box paths, the founder's words) +docs/analysis/class-v6 From 697fdd23a1f5fe460e9b9973f8d8cfbd42fc6700 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:29:17 +0000 Subject: [PATCH 04/11] Class v6 history lane, revision 2: the synthesis lane's reading of the six items folded in, lane B's hardware file cross-cited docs/analysis/class-v6/history.md: layer 2's open ceiling question replaced by the synthesis lane's resolution (the per-year ceiling as layer 2's first constant, the schedule's power-of-two step for the year; the state brings a step forward and never adds one), with the Ethereum-state figure kept as the reason the ceiling exists; the read-width rank reworded on the measured warrant (w16 latency-bound within 2.7 percent on the 5090 and the 9070 XT, within 1 percent on the M5 Max; the band is {4 B, 16 B}, nothing wider); the Jasminer X4 finding cross-cited to lane B's hybrid-bonded DRAM row (hardware-future.md 4.4, 13x to 17x modelled) as that row's shipped precedent at 5x on a planar node; the header records the 11:26 UK landing (eb71eaf3). No number changes. Co-Authored-By: Claude Fable 5.1 --- docs/analysis/class-v6/history.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/analysis/class-v6/history.md b/docs/analysis/class-v6/history.md index 1d7b524f4..0a2b802f1 100644 --- a/docs/analysis/class-v6/history.md +++ b/docs/analysis/class-v6/history.md @@ -2,7 +2,7 @@ 8 October 2026, branch `class-v6-history`, the Counter ASIC coordinator's history lane. The founder's word at 11:1x UK: class v6 is declared with four layers as its spine, and the research opens "see if anything can be optimised, added or invented". This file extends and corrects `docs/analysis/asic-resistance-history.md` (5 October 2026, the deep dive: 31 rows, 24 papers, ten lessons, seven ranked additions); it does not repeat that file's rows. What is new here: the exact MECHANISM of every chip (what it specialised: the memory, the hash core, the instruction mix, the parameter fixity), what each design missed, the timeline from announcement to chip to response, and for each one the mapping to class v6's four layers with "does v6 close it" in one sentence and one number. Every figure about another chain cites a URL with the date it was read, or is labelled approximate. Every Igneum figure names the repo file. Reading public research is in-house; nothing is paid or asked of anyone outside. -First cut landed before 15:00 UK on 8 October (the table, the mechanisms, the three lessons); the full report by 09:00 UK on 9 October. A line goes to the coordinator and to the synthesis lane at each landing. +First cut landed on the mirror's master at 11:26 UK on 8 October (merge 4c58ad65: the table, the mechanisms, the three lessons), ahead of the 15:00 clock; this revision folds in the synthesis lane's reading of the six items (`docs/design/class-v6-rotating-family.md` section 7b) and cross-cites lane B's hardware file; the full report by 09:00 UK on 9 October carries any row the other lanes move. A line goes to the coordinator and to the synthesis lane at each landing. ## 0. One page @@ -22,7 +22,7 @@ First cut landed before 15:00 UK on 8 October (the table, the mechanisms, the th 2. **Automatic change beats the human fork only where it costs the chip a redesign, and the one parameter that does is the memory.** Grin's six-monthly tweaks held because each was a new algorithm the lane was scheduled to retire; Monero's forks lost on the second lap; Ethash's DAG growth is the one scheduled change in the record that killed a shipped chip (the E3, when the DAG passed its 4 GB of DDR3). Layer 2 is that lesson made a rule, and its rate decides everything: at 2 GiB plus 0.5 GiB a year a 32 GB chip board outlives the chain, so layer 2 as declared ages out the honest 8 GB card before any chip unless the floor is set against DRAM cost per gigabyte, not against chain state. 3. **A steered or biased address pattern is always found after launch unless the test lives in the acceptance rule, and every new draw needs its own null.** ProgPoW's seed, MTP's blocks and class v4's lossy sources were the same attack three times; layer 4 puts the test where it must be, and its cost is one census per era draw on the node (2.2 s per candidate at 2^20 today) with the null re-derived for every drawn parameter, because the window model that defines "uniform" changes with the read width and the program length. -**What the history says to add** (section 5): the issuance clock and the share-pattern detector (unchanged from the 5 October ranking, still unbuilt); a layer 2 floor stated in DRAM dollars; the read width kept out of the era draw unless a width other than 4 bytes is measured latency-bound on every vendor; the reserve ordered by what a sequencer chip cannot fold into firmware. +**What the history says to add** (section 5): a layer 2 floor and a per-tier ceiling stated before its rate (the synthesis lane has since made the ceiling layer 2's first constant); the issuance clock and the share-pattern detector (unchanged from the 5 October ranking, still unbuilt); the read width's draw band stopped where the honest card stops being latency-bound ({4 B, 16 B} on the measured warrant, nothing wider); the op-mix band bounded by the per-vendor energy table; the reserve ordered by what a sequencer chip cannot fold into firmware. ## 1. The chips, one row per mechanism @@ -77,7 +77,7 @@ One section per proof of work. Each carries the mechanism, the miss, the timelin **The timeline.** Hash live July 2015; the E3 at 32 months (announced) and 36 (shipped); the first chip over 2x at 65 months (Linzhi, December 2020); 5x at 75 months (Jasminer, October 2021); the Merge at 86 (15 September 2022). The E3's death by DAG growth: Classic first, at epoch 328 (DAG about 3.56 GB, March 2020), then Ethereum, with a 30 March 2020 firmware stretching the DDR to about block 11.4 million (about October 2020): 20 to 27 months after shipping. Ethereum's responses: Zamfir's April 2018 poll (57 percent for an anti-chip fork); EIP-1057 created 2 May 2018, a 93 percent community vote in April 2019, audits delivered September 2019, "accepted" on 21 February 2020, EIP-2538's opposition on 25 February, then stagnant; the share claim in the EIP's own text: "as much as 40 percent of the Ethereum network may now be secured by ASICs" (undated inside a 2018 to 2020 document; no year-by-year series exists). After the Merge: Classic's hashrate went 64 to 183 TH/s in one day; today Classic reads 129.9 TH/s and ETHW 2.15; at USD 0.10 per kWh every Ethash chip in the table loses money (E9 Pro minus USD 5.28 a day), and a later wave (iPollo V1 3.6 GH/s at 3,100 W, June 2022; Jasminer X16-P 5.8 GH/s at 1,900 W, August 2023) holds Classic (https://hashrateindex.com/blog/how-much-ethereum-mining-hashrate-can-other-blockchains-absorb/ ; https://2miners.com/etc-network-hashrate ; read 8 October 2026). -**The mapping to v6.** Ethash is class C in full, and its chips are the f = 1 chip of `chip-model-v3.md` section 5 at three points on the packaging ladder: commodity DRAM on a board (E3, E9: 1x to 4x), memory sized and placed per chip (Linzhi: 2x), DRAM bonded to the logic (Jasminer: 5x, the model's HBM3 row). None of v6's four layers touches a chip of this class: the program, the mixer, the op mix, the family schedule and the acceptance floor are all firmware or configuration to a controller that stores the dataset; the only layer that reaches it is layer 2, and only when the dataset passes the chip's board, which at 2 GiB plus 0.5 GiB a year is year 60 for a 32 GB board (section 4.2). Does v6 close it: **no**. The number: 5.1x per joule on GDDR7 and 7.5x on one HBM3 stack at zero premium against the 5090 unlocked, 3.6x at the 5090's 1,300 MHz knee, 2.1x at the knee with the class v4 shadow at k = 1 (`counter-asic-4-research.md` section 0); the history's measured band for exactly this chip class is 1.0x (E3) to 5.1x (Jasminer), and Jasminer's number is the model's HBM-class row reached in 2021 on a 40 nm logic die. The one thing Igneum has that Ethash did not: the honest card is latency-bound at 4-byte reads, not bandwidth-bound at 128, so the chip's energy per read is the activate's 909 pJ plus a 32-byte atom (2.0 nJ on GDDR7 against the card's measured 8.7 to 10.9 nJ marginal), which is where the 5.1x comes from, and the shadow is the only term on the card's side of that ratio. +**The mapping to v6.** Ethash is class C in full, and its chips are the f = 1 chip of `chip-model-v3.md` section 5 at three points on the packaging ladder: commodity DRAM on a board (E3, E9: 1x to 4x), memory sized and placed per chip (Linzhi: 2x), DRAM bonded to the logic (Jasminer: 5x, the model's HBM3 row). None of v6's four layers touches a chip of this class: the program, the mixer, the op mix, the family schedule and the acceptance floor are all firmware or configuration to a controller that stores the dataset; the only layer that reaches it is layer 2, and only when the dataset passes the chip's board, which at 2 GiB plus 0.5 GiB a year is year 60 for a 32 GB board (section 4.2). Does v6 close it: **no**. The number: 5.1x per joule on GDDR7 and 7.5x on one HBM3 stack at zero premium against the 5090 unlocked, 3.6x at the 5090's 1,300 MHz knee, 2.1x at the knee with the class v4 shadow at k = 1 (`counter-asic-4-research.md` section 0); the history's measured band for exactly this chip class is 1.0x (E3) to 5.1x (Jasminer), and Jasminer's number is the model's HBM-class row reached in 2021 on a 40 nm logic die. The forward line of the same mechanism is lane B's (`docs/analysis/class-v6/hardware-future.md`, master 34f63b3c, section 4.4 and its table row for fine-grained hybrid-bonded DRAM on logic: 13x to 17x per joule at zero shadow, modelled, on the 2028 to 2030 roadmaps); the Jasminer X4 is that row's shipped precedent, five years early and at 5x on a planar node, which is the reason to read lane B's 13x to 17x as a ceiling a first product will not reach and a second one will approach. The one thing Igneum has that Ethash did not: the honest card is latency-bound at 4-byte reads, not bandwidth-bound at 128, so the chip's energy per read is the activate's 909 pJ plus a 32-byte atom (2.0 nJ on GDDR7 against the card's measured 8.7 to 10.9 nJ marginal), which is where the 5.1x comes from, and the shadow is the only term on the card's side of that ratio. ### 2.3 RandomX (Monero, 30 November 2019): the chips, RandomX v2, and the X9's withdrawal @@ -232,7 +232,7 @@ The arithmetic that binds. A chip's memory is bought by the board, and today's p | 24 GB | 44 | one HBM3 stack; the 4090 and the M5 Max class | | 32 GB | 60 | the f = 1 GDDR7 chip's board; the 5090 | -So layer 2 as a rate "tracking chain state" ages out fixed-memory silicon only if the dataset grows faster than a chip generation's memory headroom, and every rate that does that retires the honest small cards first by the same table. The E3 is the only case in the record where a growth rule beat a chip, and it beat a chip that had under-provisioned memory by a factor the card fleet also hit (4 GB). The rule that would hurt the f = 1 chip is one that keeps the dataset above what one board of commodity DRAM holds at the chip's price point, and that rule is unaffordable for the honest fleet. The honest reading: layer 2 is the right lever class (the memory is the one parameter a stored-dataset chip cannot read as firmware), and its value is set by the floor and the ceiling, not by the tracking: a floor keeps the dataset above every SRAM die (class B stays closed: 2 GiB is 1,000 mm^2 of SRAM even at N5), and a ceiling keeps it under the honest tiers' memory. Between those two lines the chip's board holds whatever the card holds, and the growth rate changes nothing for it. What "tracking chain state" adds over the fixed schedule is governance (no release decides the size) and the class v5 link (the dataset is built from the state, so the size follows the state's record count naturally); it is not an anti-chip rate. Open for the synthesis lane: if the chain's state grows the way Ethereum's did (approximate, from memory: Ethereum's account and storage state passed 100 GB in its eighth year), a dataset that tracks it literally outgrows every consumer card inside the chain's first decade, so the ceiling is the number to fix, in gigabytes per tier per year, before the rate. +So layer 2 as a rate "tracking chain state" ages out fixed-memory silicon only if the dataset grows faster than a chip generation's memory headroom, and every rate that does that retires the honest small cards first by the same table. The E3 is the only case in the record where a growth rule beat a chip, and it beat a chip that had under-provisioned memory by a factor the card fleet also hit (4 GB). The rule that would hurt the f = 1 chip is one that keeps the dataset above what one board of commodity DRAM holds at the chip's price point, and that rule is unaffordable for the honest fleet. The honest reading: layer 2 is the right lever class (the memory is the one parameter a stored-dataset chip cannot read as firmware), and its value is set by the floor and the ceiling, not by the tracking: a floor keeps the dataset above every SRAM die (class B stays closed: 2 GiB is 1,000 mm^2 of SRAM even at N5), and a ceiling keeps it under the honest tiers' memory. Between those two lines the chip's board holds whatever the card holds, and the growth rate changes nothing for it. What "tracking chain state" adds over the fixed schedule is governance (no release decides the size) and the class v5 link (the dataset is built from the state, so the size follows the state's record count naturally); it is not an anti-chip rate. Resolved by the synthesis lane (11:2x UK, `docs/design/class-v6-rotating-family.md` section 7b on `counter-asic-4`): layer 2's rule carries a per-year ceiling as its first constant, the fixed schedule's power-of-two step for that year, so the chain's state can bring a step forward and never add one; "retires cards before chips" is recorded as the reason the ceiling exists. Under that rule the table above is the ceiling's own schedule, and the honest 8 GB tier's year-12 line stands whatever the state does. What this file adds for the record: if the chain's state grew the way Ethereum's did (approximate, from memory: the account and storage state passed 100 GB in its eighth year), a dataset tracking it with no ceiling would have outgrown every consumer card inside the first decade; the ceiling is what makes layer 2 a governance rule and not a fleet-retirement rule. ### 4.3 Layer 3: scheduled family epochs by height, every 180 days, no release @@ -268,7 +268,7 @@ Reading. Layer 4 is the right answer to this class and the only one of the four |---|---|---|---|---| | 1 | **State layer 2's floor and ceiling in gigabytes per tier, before its rate.** The floor above every SRAM die (today's 2 GiB holds); the ceiling under the honest tiers' memory on a stated glide (the 8 GB tier's life is the first number) | the E3 is the only chip a growth rule ever killed and it was the chip with the fleet's own memory limit; Scrypt-N was abandoned because its growth was public and slow; Autolykos's growth is untested; a dataset that tracks chain state literally outgrows every card if the state grows the way Ethereum's did (approximate) | none at the floor; everything at the ceiling | genesis rule, with the card-lifetime table | | 2 | **The clock and the detector**, unchanged from the 5 October ranking and still unbuilt: the per-program rate spread and nonce pattern on the observer (the method that found Monero's chips at 85 percent), plus a share-by-key-and-template instrument (what found Qubic until it randomised), plus the issuance trigger at about USD 50 K a day | every chip in the record was on its chain before it was announced (Monero 2017, Zcash's three groups, SChernykh's 2021 reading of the X5) | none | before the public testnet | -| 3 | **Keep the read width out of the era draw** unless a width other than 4 bytes is measured latency-bound on all three vendors; a draw over {4 B, 16 B} is harmless and worthless (w16 moved the chip's cost not at all) | the Ethash chips' whole edge was the bandwidth lever Ren and Devadas name; w64 made the 5090 bandwidth-bound | a 47 percent loss on the 5090 at w64 | spec 1.13.1's allowed set stays {1} | +| 3 | **The read width's draw band stops where the honest card stops being latency-bound**: the synthesis lane keeps {4 B, 16 B} on the measured warrant (w16 latency-bound within 2.7 percent on the 5090 and the 9070 XT, within 1 percent on the M5 Max); w64 is out (the 5090 bandwidth-bound at 71.9 MH/s); the draw costs every chip nothing (the same 32-byte atom at either width) and is a governance value only | the Ethash chips' whole edge was the bandwidth lever Ren and Devadas name; a width that makes the card bandwidth-bound hands the chip that lever | within 2.7 percent at w16; 47 percent at w64 | the band {4 B, 16 B} in the class v6 spec; nothing wider without a per-vendor latency-bound measurement | | 4 | **Bound the op-mix draw by the per-vendor energy table, not only by the rate spread**: the 5090 pays 55.8 pJ per shuffle against 11.3 per add, so a shuffle-heavy era taxes the honest card up to 5x per instruction for no better k | X16R's drawn order cost the chip nothing and the fleet nothing; Igneum's draw can cost the fleet watts | up to 2x the premium per instruction at the band's edge | the band's definition in the class v6 spec | | 5 | **Order the reserve by what a sequencer cannot fold into firmware**, mm8 last; and name the random item-derivation program (the 5 October addition 2) as the one reserve item whose semantics are not knowable at genesis | the kHeavyHash chips and the 5090's own 1.4 to 4.1 pJ per int8 MAC; RandomX's SuperscalarHash is the one idea Igneum has not taken, and it acts on the f = 0 chip only | none at launch | reserve ordering, genesis | | 6 | **Generalise layer 4 with a null per drawn parameter**: the window model re-derived per era, the census per draw, and a stated ceiling for the shadow-written residue per shadow placement | lesson 3 | 2.2 s per candidate once an epoch on a node | the class v6 acceptance rule | From 6f8ef7f128e2841b282870991f531fd4c729b7c5 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:31:06 +0000 Subject: [PATCH 05/11] Builder pages: the site audit's four lines (8 October 2026) - /build: "built to be proven" with the Devnet 3 share-and-lag line and the full-node sentence, in place of a proven-chain claim (evidence row 15) - /grants: paid from the dev fee fund on delivery; before mainnet no IGN with value, payment when the fund holds IGN, nothing promised about when or whether; the fund is zero today Co-Authored-By: Claude Fable 5.1 --- docs/build/README.md | 2 +- docs/build/build.md | 2 +- docs/build/grants.md | 6 +++--- site/build.html | 4 ++-- site/build.mjs | 4 ++-- site/grants.html | 6 +++--- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/docs/build/README.md b/docs/build/README.md index da070f7a1..4789d31fa 100644 --- a/docs/build/README.md +++ b/docs/build/README.md @@ -4,7 +4,7 @@ | File | Serves | |---|---| -| `build.md` | [igneum.network/build](https://igneum.network/build): what is different, the chain ids and endpoints, the wallet, the explorer, the faucet, the five-minute contract, the browser verifier | +| `build.md` | [igneum.network/build](https://igneum.network/build): what is different (built to prove every block, a lock in minutes, nothing to stake, the EVM unchanged), the chain ids and endpoints, the wallet, the explorer, the faucet, the five-minute contract, the browser verifier | | `grants.md` | [igneum.network/grants](https://igneum.network/grants): the tiers, what a grant is, how to apply, the review, the honest lines | | `first-contract.md`, `first-contract-test.sh` | the walkthrough and the script that runs it end to end on Devnet 3 from a build box; the PASS line is the test record | | `rpc.md` | the JSON-RPC method list as the node serves it, read from a Devnet 3 node, with the probe | diff --git a/docs/build/build.md b/docs/build/build.md index 5e9e7fd7a..989341c1f 100644 --- a/docs/build/build.md +++ b/docs/build/build.md @@ -4,7 +4,7 @@ This file is the source of [igneum.network/build](https://igneum.network/build). ## What is different -**Every block is proven.** A chain block carries a zero-knowledge proof of its execution. The miners are the provers: the same cards that find blocks prove them, in shards, and the proof follows the tip by tens of seconds. Your contract runs on a chain whose state is proven, not assumed. +**Every block is built to be proven.** A chain block carries a zero-knowledge proof of its execution. The miners are the provers: the same cards that find blocks prove them, in shards. On Devnet 3 a share of blocks carries a proof today; the live page shows the share and the lag, and the design target at launch is under a minute. Full nodes execute every block themselves, so a bad proof is a light-client problem and never a chain split. **A lock in minutes, not an hour of confirmations.** Miners sign a checkpoint every 30 seconds. When two thirds of the mining weight of the last 30 days have signed, the checkpoint is locked. Weight is blocks mined, nothing else. The lock lands in about two minutes. The [litepaper](/litepaper) has the rule. diff --git a/docs/build/grants.md b/docs/build/grants.md index de138be38..a9d8c5865 100644 --- a/docs/build/grants.md +++ b/docs/build/grants.md @@ -4,7 +4,7 @@ This file is the source of [igneum.network/grants](https://igneum.network/grants ## What a grant is -Work paid in IGN on delivery. You propose a piece of work, it is accepted with a written definition of done, you build it, it runs on the public testnet, and it is paid when it does. Not a salary, not an advance, not an investment. +Grants are paid in IGN from the dev fee fund, on delivery. You propose a piece of work, it is accepted with a written definition of done, you build it, and it runs on the public testnet. Not a salary, not an advance, not an investment. The money is the dev fee fund: the IGN that the Ember dev fee collects. Ember, the official miner, takes an optional 1% of a miner's rewards, in full view and off with one flag; that fee goes to Igneum Labs, the company that ships the software. The protocol itself carries no fee, no fund and no allocation, and no grant is paid from emission. [The dev fee](/dev-fee) has the mechanism. @@ -38,8 +38,8 @@ A short issue is fine. The definition of done is the part that matters. ## The honest lines -- Devnet and testnet coins have no value. A grant delivered before mainnet is paid when mainnet IGN exists, not in devnet or testnet coin. -- No amount, price or date is promised. The fund is what the dev fee collects, and it is zero until there is mining with value. +- Devnet and testnet coins have no value. Before mainnet there is no IGN with value: a grant delivered on the testnet is recorded in its issue, and payment comes from the fund when the fund holds IGN. Nothing is promised about when, or whether, that is. +- No amount, price or date is promised. The fund is what the dev fee collects, and it is zero today. - A grant is for work delivered, never for a user count, a listing, a post or a referral. - Igneum Labs may decline any application and may close the programme; what has been accepted and delivered is still paid. diff --git a/site/build.html b/site/build.html index f476ffb48..b2eec0c88 100644 --- a/site/build.html +++ b/site/build.html @@ -226,7 +226,7 @@ table{min-width:560px}
Igneum/Build on Igneum
Developers

Build on Igneum

-

Every block proven. A lock in minutes. Nothing to stake. The EVM you already know: Solidity deploys unchanged. Here are the chain ids, the endpoints and a contract in five minutes.

+

Built to prove every block. A lock in minutes. Nothing to stake. The EVM you already know: Solidity deploys unchanged. Here are the chain ids, the endpoints and a contract in five minutes.

@@ -237,7 +237,7 @@ table{min-width:560px}

This file is the source of igneum.network/build. The site build renders it as the page. The other files in this directory are the walkthrough, the RPC list, the faucet, the verifier and the grants.

What is different

-

Every block is proven. A chain block carries a zero-knowledge proof of its execution. The miners are the provers: the same cards that find blocks prove them, in shards, and the proof follows the tip by tens of seconds. Your contract runs on a chain whose state is proven, not assumed.

+

Every block is built to be proven. A chain block carries a zero-knowledge proof of its execution. The miners are the provers: the same cards that find blocks prove them, in shards. On Devnet 3 a share of blocks carries a proof today; the live page shows the share and the lag, and the design target at launch is under a minute. Full nodes execute every block themselves, so a bad proof is a light-client problem and never a chain split.

A lock in minutes, not an hour of confirmations. Miners sign a checkpoint every 30 seconds. When two thirds of the mining weight of the last 30 days have signed, the checkpoint is locked. Weight is blocks mined, nothing else. The lock lands in about two minutes. The litepaper has the rule.

Nothing to stake. No validator set, no delegation, no slashing, no bonded class above the miners. Finality comes from mining weight alone. Nobody holds a key that the chain depends on.

The EVM you already know. Solidity deploys unchanged. Standard JSON-RPC, EIP-1559 transactions, the chain id in the signature, cancun as the EVM version. Gas has two dimensions on Igneum, execution and proving, and the node folds the second into the price it quotes, so eth_estimateGas and eth_gasPrice work as they do on Ethereum.

diff --git a/site/build.mjs b/site/build.mjs index f9343f2e6..5b5cdc348 100644 --- a/site/build.mjs +++ b/site/build.mjs @@ -283,8 +283,8 @@ if (existsSync(join(docs, 'bench-log.md'))) { // through the same generated-page shell as /bench, so the markdown is the source and the served page follows it. The other // files of docs/build/ (the walkthrough, the RPC list, the faucet, the verifier) are linked from /build on the git host. for (const [src, file, title, desc, heading, lead, eyebrow] of [ - ['build.md', 'build.html', 'Build on Igneum: chain ids, RPC, a contract in five minutes', 'The developer entry page for Igneum: what is different, the chain ids and RPC endpoints, the wallet, the explorer, the faucet, a five-minute contract deploy and a block you verify in your browser.', 'Build on Igneum', 'Every block proven. A lock in minutes. Nothing to stake. The EVM you already know: Solidity deploys unchanged. Here are the chain ids, the endpoints and a contract in five minutes.', 'Developers'], - ['grants.md', 'grants.html', 'Igneum grants: tooling, reference apps, infrastructure, research', 'The Igneum grants programme: four tiers, what a grant is, how to apply with an issue on the git host, the weekly review, and the lines that stay honest about value, amounts and dates.', 'Grants', 'Work paid in IGN on delivery, on the public testnet first. Four tiers. One issue to apply. A weekly review.', 'The programme'], + ['build.md', 'build.html', 'Build on Igneum: chain ids, RPC, a contract in five minutes', 'The developer entry page for Igneum: what is different, the chain ids and RPC endpoints, the wallet, the explorer, the faucet, a five-minute contract deploy and a block you verify in your browser.', 'Build on Igneum', 'Built to prove every block. A lock in minutes. Nothing to stake. The EVM you already know: Solidity deploys unchanged. Here are the chain ids, the endpoints and a contract in five minutes.', 'Developers'], + ['grants.md', 'grants.html', 'Igneum grants: tooling, reference apps, infrastructure, research', 'The Igneum grants programme: four tiers, what a grant is, how to apply with an issue on the git host, the weekly review, and the lines that stay honest about value, amounts and dates.', 'Grants', 'Paid in IGN from the dev fee fund, on delivery, on the public testnet first. Four tiers. One issue to apply. A weekly review.', 'The programme'], ]) { const mdp = join(docs, 'build', src); if (!existsSync(mdp)) continue; // the gate builds a copy of site/ alone: the committed page stands, as for /bench diff --git a/site/grants.html b/site/grants.html index 155b26bc5..089ec10ed 100644 --- a/site/grants.html +++ b/site/grants.html @@ -226,7 +226,7 @@ table{min-width:560px}
Igneum/Grants
The programme

Grants

-

Work paid in IGN on delivery, on the public testnet first. Four tiers. One issue to apply. A weekly review.

+

Paid in IGN from the dev fee fund, on delivery, on the public testnet first. Four tiers. One issue to apply. A weekly review.

@@ -237,7 +237,7 @@ table{min-width:560px}

This file is the source of igneum.network/grants.

What a grant is

-

Work paid in IGN on delivery. You propose a piece of work, it is accepted with a written definition of done, you build it, it runs on the public testnet, and it is paid when it does. Not a salary, not an advance, not an investment.

+

Grants are paid in IGN from the dev fee fund, on delivery. You propose a piece of work, it is accepted with a written definition of done, you build it, and it runs on the public testnet. Not a salary, not an advance, not an investment.

The money is the dev fee fund: the IGN that the Ember dev fee collects. Ember, the official miner, takes an optional 1% of a miner's rewards, in full view and off with one flag; that fee goes to Igneum Labs, the company that ships the software. The protocol itself carries no fee, no fund and no allocation, and no grant is paid from emission. The dev fee has the mechanism.

The tiers

@@ -253,7 +253,7 @@ table{min-width:560px}
  • Every Friday. Each open application gets one of three answers inside seven days: accepted with a definition of done, questions, or no with the reason.
  • Accepted work is tracked in its issue. The reviewer and the builder agree the definition of done there before any work starts.
  • Delivery is reviewed on the public testnet first. Payment follows the review, in the issue, in the open.

The honest lines

-
  • Devnet and testnet coins have no value. A grant delivered before mainnet is paid when mainnet IGN exists, not in devnet or testnet coin.
  • No amount, price or date is promised. The fund is what the dev fee collects, and it is zero until there is mining with value.
  • A grant is for work delivered, never for a user count, a listing, a post or a referral.
  • Igneum Labs may decline any application and may close the programme; what has been accepted and delivered is still paid.
+
  • Devnet and testnet coins have no value. Before mainnet there is no IGN with value: a grant delivered on the testnet is recorded in its issue, and payment comes from the fund when the fund holds IGN. Nothing is promised about when, or whether, that is.
  • No amount, price or date is promised. The fund is what the dev fee collects, and it is zero today.
  • A grant is for work delivered, never for a user count, a listing, a post or a referral.
  • Igneum Labs may decline any application and may close the programme; what has been accepted and delivered is still paid.

Not legal advice.

Generated from docs/build/grants.md in the repository at build time. Times are UTC.

From 5d1044ca258cb327bad7dfc6e87b40a8d51807d7 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:32:47 +0000 Subject: [PATCH 06/11] Litepaper (and /claims, /randomx from it): the RandomX record as lane A's history reads it (docs/analysis/class-v6/history.md 2.3, 8 October 2026): one chip shipped, Bitmain's Antminer X5 (September 2023) at 1.46x per joule over a desktop CPU on silicon believed mining privately from about 2021; RandomX v2 released 25 March 2026 with its mainnet activation pending; the X9 withdrawn in May 2026 with zero units (the X36 sentence stands); "no chip shipped" and "seven years without a shipped chip" gone from every served sentence; ledger X34 and C2 corrected, pins moved, the public ledger and the ledger page regenerated. Governance line beside the class v5 crossing sentence (main's wording): classes rotate on findings and at least yearly, a class change is a release activated by block height; class v6 named as the design in progress with its four layers, dated 8 October 2026 Co-Authored-By: Claude Fable 5.1 --- docs/fud-ledger.md | 4 ++-- site/claims.html | 2 +- site/ledger.html | 8 ++++---- site/litepaper.html | 12 ++++++------ site/randomx.html | 4 ++-- tools/ci/ledger-text-check.mjs | 4 ++-- 6 files changed, 17 insertions(+), 17 deletions(-) diff --git a/docs/fud-ledger.md b/docs/fud-ledger.md index 43c590710..1a1f78b09 100644 --- a/docs/fud-ledger.md +++ b/docs/fud-ledger.md @@ -706,7 +706,7 @@ Evidence: litepaper "For miners", hardware paragraph. Wording: overclaims list, ### C2. vs Monero: "no chip in seven years" is not proof "Absence of a public RandomX ASIC is not evidence one cannot exist. Monero is also a small prize." -Status: Conceded, stated; reopened as conceded (7 October 2026, morning, X36): the X9 never shipped, so Monero's record is again seven years without a shipped chip, and the concession stands as first written; the litepaper says so in the same sentences. +Status: Conceded, stated; corrected (8 October 2026, lane A's history): Monero's record is about seven years with one shipped chip, the Antminer X5 at 1.46x per joule over a desktop CPU, not seven years without one; the concession stands and the litepaper's sentences say so (`docs/analysis/class-v6/history.md` 2.3). Was: Conceded, stated; reopened as conceded (7 October 2026, morning, X36): the X9 never shipped, so Monero's record is again seven years without a shipped chip, and the concession stands as first written; the litepaper says so in the same sentences. Status: Conceded, stated (7 October 2026, morning): the one-screen home page is back on the owner's word, so this row is stated on `site/litepaper.html` only; the sentence there is unchanged and the text check lists it under the litepaper. @@ -2298,7 +2298,7 @@ Evidence: `site/litepaper.html`; `docs/plans/testnet-go.md`; X31, X32. ### X34. RandomX described as chip-free "The home page said the random program 'has kept chips off Monero since 2019', the litepaper said Monero ran on RandomX 'with no chip publicly shipped' and spoke of 'Monero's seven years without a public chip'. Bitmain's Antminer X9, a RandomX chip, ships from July 2026 (1 MH/s at 2,472 W, about USD 5,600; monero-project/monero issue 10270), and RandomX 2.0 shipped on 25 March 2026. Every sentence that said or implied RandomX is chip-free, or that Monero's approach has held, was wrong." -Status: Fixed, stated; corrected (7 October 2026, morning, X36): the X9 never shipped. Bitmain opened pre-orders on 26 December 2025 and withdrew the product in mid-May 2026 before any unit was delivered; every sentence below that had it shipping now states that, and RandomX stands as a technique no chip has yet shipped against. The sentences in this row are the history. +Status: Fixed, stated; corrected again (8 October 2026, lane A's history, `docs/analysis/class-v6/history.md` 2.3): one chip did ship against RandomX, Bitmain's Antminer X5 (announced 27 August 2023, shipped September 2023), a board of RISC-V chips at 1.46x per joule over a Ryzen 9 7950X, on silicon SChernykh believes mined privately from about 2021; RandomX v2 was released on 25 March 2026 with its mainnet activation pending (PR 10038); the X9 was withdrawn in mid-May 2026 with zero units. Every served sentence that said "no chip shipped" or "seven years without a shipped chip" now carries the X5 and the v2 release (litepaper precedents row, the chip-model paragraph, the vs RandomX section and its track-record row; /claims and /randomx follow from it); the X36 sentence on the X9 stands. Was: Fixed, stated; corrected (7 October 2026, morning, X36): the X9 never shipped. Bitmain opened pre-orders on 26 December 2025 and withdrew the product in mid-May 2026 before any unit was delivered; every sentence below that had it shipping now states that, and RandomX stands as a technique no chip has yet shipped against. The sentences in this row are the history. Status: Fixed, stated (7 October 2026, morning): the one-screen home page carries no RandomX sentence, so the corrected wording stands on `site/litepaper.html` (four sentences and the table row); the text check lists them there. diff --git a/site/claims.html b/site/claims.html index f86f4de02..4094a8379 100644 --- a/site/claims.html +++ b/site/claims.html @@ -222,7 +222,7 @@

Here are the limits, stated before anyone else states them.

  • A proof in seconds. Not at launch. Proving a full block today needs a cluster of 100 to 200 consumer GPUs, approximate, so Igneum launches with proofs within about a minute and tightens as hardware improves. Users still see their transaction land in one second.
    • -
  • A chip is impossible. No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane and 3.4x with one three times better, under class v4 from the first block: a memory-controller chip that stores the whole dataset and carries a GPU-class datapath beside its memory for the 100,000 ops per hash in the shadow, the range running from a chip core as costly per operation as a GPU lane (k = 1, modelled on the 5090’s measured watts at its knee, 7 October 2026) to a core three times better per operation (k about 0.33); the withdrawn Antminer X9’s claimed figure is a ratio against a CPU core, not a GPU lane, so it does not stand for a chip core against us; the ladder’s second rung takes that bracket to about 2.8x (modelled, 7 October 2026). Class v5 then makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The baseline the work started from, never the launch state: without class v4 the same stored-dataset chip would reach 1.2x per chip and 5x to 9x per joule in our model (6 October 2026); the Ethash chips of this class reached 2.1x to 4.8x (Linzhi Phoenix 2020, Jasminer X4 2021, Antminer E9 2022). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the chip model analysis (6 October 2026); the ASIC history’s Ethash rows; Counter ASIC 3.0 item 8 (the chip’s per-joule edge over the RTX 5090 falls from 5.6x to 2.1x on GDDR7 at k = 1 and to 3.4x at a core three times better, the 5090 at 0.2% less rate; gates G1 to G6 passed, 6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held for about seven years; the one chip announced against it, Bitmain’s Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core (k about 0.33) never measured. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.
    • +
  • A chip is impossible. No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane and 3.4x with one three times better, under class v4 from the first block: a memory-controller chip that stores the whole dataset and carries a GPU-class datapath beside its memory for the 100,000 ops per hash in the shadow, the range running from a chip core as costly per operation as a GPU lane (k = 1, modelled on the 5090’s measured watts at its knee, 7 October 2026) to a core three times better per operation (k about 0.33); the withdrawn Antminer X9’s claimed figure is a ratio against a CPU core, not a GPU lane, so it does not stand for a chip core against us; the ladder’s second rung takes that bracket to about 2.8x (modelled, 7 October 2026). Class v5 then makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The baseline the work started from, never the launch state: without class v4 the same stored-dataset chip would reach 1.2x per chip and 5x to 9x per joule in our model (6 October 2026); the Ethash chips of this class reached 2.1x to 4.8x (Linzhi Phoenix 2020, Jasminer X4 2021, Antminer E9 2022). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the chip model analysis (6 October 2026); the ASIC history’s Ethash rows; Counter ASIC 3.0 item 8 (the chip’s per-joule edge over the RTX 5090 falls from 5.6x to 2.1x on GDDR7 at k = 1 and to 3.4x at a core three times better, the 5090 at 0.2% less rate; gates G1 to G6 passed, 6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), at 1.46x per joule over a desktop CPU; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core (k about 0.33) never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.
  • A guaranteed income floor. No. External proving is a small market today. Igneum's miners' electricity cost in it is close to power, but the price they must charge is the subsidy they forgo, which falls as one over network hash: an edge at scale and nothing more.
  • A memory-hard prototype on every vendor. Not yet. The 256 MB cache closed the shortcut on Apple silicon (computing items runs 4.8x slower than loading them, measured 3 October 2026). The same ratio on NVIDIA and on a discrete AMD card is Open.
  • Finality in the first month. No. No checkpoint locks until the 30-day window has 30 days of history. The first month of mainnet is proof of work with a 12-hour depth, and the text above says so wherever a day count appears.
    • diff --git a/site/ledger.html b/site/ledger.html index f896139f2..acf7be50e 100644 --- a/site/ledger.html +++ b/site/ledger.html @@ -89,7 +89,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
    @@ -154,7 +154,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
    Learn
    LitepaperThe design, as published. Income per tierIGN a day per card at three network sizes, and the electricity. - LedgerEvery criticism, answered or conceded. + LedgerEvery criticism, answered or conceded. What Igneum does not claimThe limits, stated first. Igneum vs RandomXWhat was kept and what was rebuilt for GPUs. Built on the shouldersEvery borrowed part, credited. @@ -1395,7 +1395,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
    AP-F8-1

    A load whose source was last written by or, mul or mulhi makes a cross-hash hot set

    7 October 2026
    The item histogram of class v4 over 2^26 nonces is not uniform: the top 0.1 percent of items take 0.520 percent of reads against 0.115 for a uniform control (4.05x), one item takes 78,479 reads (153x the mean), and site 15 feeds 6.37 percent of its reads into that top 0.1 percent in every iteration." (attack-pass row F8, a repository file, 7 October 2026)
    -
    Fixed in part, finding bounded, stated 7 October 2026, night, the Counter ASIC lane's words): class v4 sub-version 3 (igneum-pow 017e7037, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under 1.2x with the four-seed tail accepted by the coordinator as the window model's unattributed residue (no chip consequence); the pass then attributed the class by value (eight live hot sets at 1.54x to 2.24x in the lowest 30 of 29,032 accepted programs, each about 1 MB of items at 0.3 percent of reads, 1.002x to a chip); class v5 (1c420786, frozen 21:53 UK) carries the fix as rule (c'''), the per-site distinct-index floor at 0.995 on the state flag (its census refuses 2.435 percent of accepted programs; seven of seven live hot sets refused at 0.9821 to 0.9919; the eighth's ratio owed tonight), with a named residual (three mild shadow-block-written concentrations at 0.9992 to 0.9997, about 1.0004x, a value-level test in the next class); the record is a repository file section 7c and the class v5 design's section 14. The eighth live hot set (seed 122960, id 4be7393ab6c84802, the deepest found: X_f +0.111 percent, 1.54x the window model, its hottest item at 475,616 reads from an all-ones source) reads minimum site 12 at 0.9824 at the acceptance's own 2^20 sample (live 0.9822), refused by class v5's (c''') floor at 0.995; so the floor refuses nine of nine live hot sets by X_f at or above f found in the tail of 269,250 accepted programs (minimum sites 0.9809 to 0.9919; the ninth, seed 228763 from a non-saturated source, at 0.9809 on 8 October 2026) against 0 hot sets in 20 random programs; what it misses stays the three mild shadow-block-written concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x to a chip, the value-level test in the next class (22:41 local time; the logs under a repository file/ on branch adv-accept; the v5 design's section 14). The public sentence (the coordinator's wording, 7 October 2026, night; the count moved to nine at 01:13 local time on 8 October when the ninth live hot set, seed 228763 from a non-saturated source, read 0.9809 and was refused): nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test. The reason, read by the in-house pass (adv-cache-2) and the class v5 lane together: the distinct-index count at 2^20 sees concentration on few word indices whatever their source, saturated or not (the hot sets put about 3 percent of a site's reads on 512 indices, so the ratio falls to 0.981 to 0.992; the final tally 9 of 9 live hot sets and both single-item programs refused, 7 clean-live programs refused among the 12 deepest, 3 mild residuals missed) and not a diffuse excess over the top 0.1 percent of items (16,384 items), which is what the era-stride low-bit law produces (13 of 27 drawn-era programs carry a site over 1.04x, 8 over 1.2x, worst 1.75x; 0 of 29 refused at the 2^20 sample, minimum sites 0.9965 to 1.0000); its chip value is about 1.0024x at the worst site read, under this row's bound by an order; the row for it is AP-F8-6. The RTX 5080 grid's knee is not in tonight; X37 keeps the 5080's stock premium only.
    +
    Fixed in part, finding bounded, stated 7 October 2026, night, the Counter ASIC lane's words): class v4 sub-version 3 (igneum-pow 017e7037, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under 1.2x with the four-seed tail accepted by the coordinator as the window model's unattributed residue (no chip consequence); the pass then attributed the class by value (eight live hot sets at 1.54x to 2.24x in the lowest 30 of 29,032 accepted programs, each about 1 MB of items at 0.3 percent of reads, 1.002x to a chip); class v5 (1c420786, frozen 21:53 UK) carries the fix as rule (c'''), the per-site distinct-index floor at 0.995 on the state flag (its census refuses 2.435 percent of accepted programs; seven of seven live hot sets refused at 0.9821 to 0.9919; the eighth's ratio owed tonight), with a named residual (three mild shadow-block-written concentrations at 0.9992 to 0.9997, about 1.0004x, a value-level test in the next class); the record is a repository file section 7c and the class v5 design's section 14. The eighth live hot set (seed 122960, id 4be7393ab6c84802, the deepest found: X_f +0.111 percent, 1.54x the window model, its hottest item at 475,616 reads from an all-ones source) reads minimum site 12 at 0.9824 at the acceptance's own 2^20 sample (live 0.9822), refused by class v5's (c''') floor at 0.995; so the floor refuses nine of nine live hot sets by X_f at or above f found in the tail of 269,250 accepted programs (minimum sites 0.9809 to 0.9919; the ninth, seed 228763 from a non-saturated source, at 0.9809 on 8 October 2026) against 0 hot sets in 20 random programs; what it misses stays the three mild shadow-block-written concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x to a chip, the value-level test in the next class (22:41 local time; the logs under a repository file/ on branch adv-accept; the v5 design's section 14). The public sentence (the coordinator's wording, 7 October 2026, night; the count moved to nine at 01:13 local time on 8 October when the ninth live hot set, seed 228763 from a non-saturated source, read 0.9809 and was refused): nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test. The reason, read by the in-house pass (adv-cache-2) and the class v5 lane together: the distinct-index count at 2^20 sees concentration on few word indices whatever their source, saturated or not (the hot sets put about 3 percent of a site's reads on 512 indices, so the ratio falls to 0.981 to 0.992; the final tally 9 of 9 live hot sets and both single-item programs refused, 7 clean-live programs refused among the 12 deepest, 3 mild residuals missed) and not a diffuse excess over the top 0.1 percent of items (16,384 items), which is what the era-stride low-bit law produces (13 of 27 drawn-era programs carry a site over 1.04x, 8 over 1.2x, worst 1.75x; 0 of 29 refused at the 2^20 sample, minimum sites 0.9965 to 1.0000); its chip value is about 1.0024x at the worst site read, under this row's bound by an order; the row for it is AP-F8-6. The RTX 5080 grid's knee is not in tonight; X37 keeps the 5080's stock premium only. The tail is attributed (8 October 2026, 09:46 UK, the hash lane): one narrow-window site per seed with a quarter-bit bucket concentration from a mad, xor or sub writer, no lossy source, no chip consequence beyond the window model; the per-site bucket bound that would refuse it is a morning item for the next class, not a change to 017e7037.
    The answer as first written

    Correct as a fault, wrong as a null. The window layer (spec 01 1.13.1 as proposed, a repository file 1.4) moves the uniform null from 0.115 to 0.160 percent at the top 0.1 percent (1.39x, not 4.05x) and explains every per-site row of F8's attribution except site 15. Site 15's source r6 was last written by or r6, r4 (instruction 61, the load at 63), a non-injective op whose output bits are 1 with probability 3/4, so the all-ones source recurs with probability (3/4)^32 per read; the era map sends it to item 0xca5b92, F8's hottest item exactly, and F8's next seven items are exactly the seven one-zero-bit sources whose zero survives the window mask. The popcount model at the measured bias (p = 0.7585) predicts 77,348 all-ones reads against 78,479, and the program's top-0.1-percent share at 0.58 against 0.52. The acceptance rule's part (a) takes any write as a fresh source and part (c) counts saturation on final register values only, so the class of fault passes it: of 1,024 chain-shaped class v4 programs 96.6 percent carry a load whose source's last writer is or, mul or mulhi, 48.5 percent an or-sourced one (0.30 percent of all reads per site), 4.9 percent an or-of-or chain (p3's class: 72 percent of that site's reads, 4.6 percent of all reads, on 0.1 percent of items). The ceiling under rule (c)'s 120-of-128 floor is one site repeating its item in all 8 iterations, 6.25 percent of reads, a chip edge of at most 1.067x in 64 bytes of SRAM; the public claim's 2x margin stands, and the public line says "bounded", not "uniform" (a repository file sections 1 to 4).

    @@ -1426,7 +1426,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
    -
    WindowsmacOSLinuxHiveOS
    +
    WindowsmacOSLinuxHiveOS
    Specification and test vectors

    Run

    diff --git a/site/litepaper.html b/site/litepaper.html index defe6ddf3..81ab61eb9 100644 --- a/site/litepaper.html +++ b/site/litepaper.html @@ -330,7 +330,7 @@ body.all .pager{display:none}
    - + @@ -449,14 +449,14 @@ body.all .pager{display:none}
    PieceClosest precedentWhat Igneum addsState, 7 Oct 2026
    A mining program that regenerates itself, for GPUsRandomX on Monero since 2019, for CPUs, a program per hash; the one chip announced against it, Bitmain’s Antminer X9, withdrawn in May 2026 before launch. ProgPoW, as KAWPOW on Ravencoin since 2020, changes the maths inside a fixed program shape every few blocks on GPUs (approximate)A whole kernel per hour compiled to native code, a daily dataset from a 256 MB cache, a verifiable delay before the seed, era draws from a genesis reserveMeasured: hourly swaps on Apple, NVIDIA and AMD cards on the live devnet, 4 October 2026
    A mining program that regenerates itself, for GPUsRandomX on Monero since 2019, for CPUs, a program per hash; one chip shipped against it, Bitmain’s Antminer X5 (September 2023), a board of RISC-V chips at 1.46x per joule over a desktop CPU, on silicon believed mining privately from about 2021; the X9 was withdrawn in May 2026 with zero units; RandomX v2 was released on 25 March 2026 with its activation pending. ProgPoW, as KAWPOW on Ravencoin since 2020, changes the maths inside a fixed program shape every few blocks on GPUs (approximate)A whole kernel per hour compiled to native code, a daily dataset from a 256 MB cache, a verifiable delay before the seed, era draws from a genesis reserveMeasured: hourly swaps on Apple, NVIDIA and AMD cards on the live devnet, 4 October 2026
    The mining card does paid, useful, verifiable workPrimecoin's prime chains in 2013 were not useful. Aleo ran proving as consensus and the fastest prover won (both approximate)Proving kept apart from the lottery; shards assigned by sortition, not by speedImplemented: proving v0 and v1 on Devnet 3 from block zero (7 October 2026), v0 on the first devnet since 5 October 2026. The job market for other chains is Designed
    A proof-of-work chain where every block is provenzkEVMs run as rollups on proof-of-stake Ethereum. Conflux has run GPU-mined EVM apps on a DAG since 2020, without proofs (approximate)Proven state on a proof-of-work base layer, produced by the miners themselvesImplemented in part: shards proven and paid on the devnet. The aggregated block proof checked in consensus is Designed
    Finality held by miners and not moved by hour-long rentalsDecred votes with stake. Horizen penalises hidden chains. Kaspa limits merge depth (approximate)Vote weight is 30 days of blocks per key. Hashrate that appeared today has no voteImplemented: rule v3 live on Devnet 3 from block zero, first lock 7 October 2026; rule v2 ran the first devnet from its first lock on 4 October 2026. External review is owed at gate 3
    When a stored-dataset chip pays for itselfat about USD 100 M of market cap in the first two years, not beforemodelled, 7 October 2026
    The baseline the work started from: the same chip under class v3, without the shadow (the Ethash class)5x to 9x (5.1x on GDDR7, 9.2x on eight HBM3 stacks; the Ethash chips of this class reached 2.1x to 4.8x)modelled, 6 October 2026; the precedent measured by others, 2020 to 2022; never the launch state
    -

    What a miner sees from this. Class v4 costs a 5090 145 W more unlocked, 88 W more at a 1,400 MHz core lock and 82 W at the best operating points (class v4 at 1,200 MHz, class v3 at 1,300; the knee is 1,300 MHz on both), for 0.2 percent more rate (measured, 7 October 2026; the 80 W read on 6 October was at the app's tuned cap); an M5 Max 16 W more for 1.5 percent, an RX 9070 XT and an RTX 4070 nothing (measured, 6 October 2026). The ladder that sets how much work rides in the shadow starts at rung 0 at genesis and climbs by miner signal; its third rung is inadmissible today because a server core verifies it in 10.85 ms, over the gate (measured, 7 October 2026). Devnet 3 runs class v4 from its first block (7 October 2026); the first devnet started on class v3 and reaches class v4 by miner signal at a published height. The next test of the model is an internal adversarial pass, not an independent review: three lanes that have never worked on the hash code attack the mixer, the chained cache and the acceptance rule with only what an outsider has (the public kit, the frozen object, the spec, the harnesses) and publish the break or the bound they reach. No outside review has run yet.

    -

    No hash has stayed free of chips forever. Igneum does not claim to. It states the gain its own model finds, the response takes a week, and both are measured. The model is public: the numbers; the claim is tested by the in-house adversarial pass and the public benchmark. Monero has run on RandomX since 2019 (approximate) with no chip shipped. Bitmain opened Antminer X9 pre-orders on 26 December 2025 for July 2026 delivery, then withdrew the product in mid-May 2026 and refunded buyers before any unit shipped; none has been independently benchmarked. A box with about a 2x per joule edge over the best CPUs, and about 3x over a desktop, was withdrawn rather than face a RandomX re-tune of 1.5x or more. That is the band Igneum’s class v4 model sits in (2.1x to 3.4x over an RTX 5090), and the defence that held was a maintained algorithm with a credible upgrade path, which is what the ladder is.

    +

    What a miner sees from this. Class v4 costs a 5090 145 W more unlocked, 88 W more at a 1,400 MHz core lock and 82 W at the best operating points (class v4 at 1,200 MHz, class v3 at 1,300; the knee is 1,300 MHz on both), for 0.2 percent more rate (measured, 7 October 2026; the 80 W read on 6 October was at the app's tuned cap); an M5 Max 16 W more for 1.5 percent, an RX 9070 XT and an RTX 4070 nothing (measured, 6 October 2026). The ladder that sets how much work rides in the shadow starts at rung 0 at genesis and climbs by miner signal; its third rung is inadmissible today because a server core verifies it in 10.85 ms, over the gate (measured, 7 October 2026). Devnet 3 runs class v4 from its first block (7 October 2026); the first devnet started on class v3 and reaches class v4 by miner signal at a published height. Classes rotate on findings and at least yearly; a class change is a release activated by block height. Class v5 crosses on Devnet 3 by height; class v6 is the design in progress (opened 8 October 2026), with four layers as its spine: per-era draws of the parameters a release now fixes, a dataset whose size tracks the chain state, scheduled family epochs by height, and the acceptance floor generalised to every era’s draw. The next test of the model is an internal adversarial pass, not an independent review: three lanes that have never worked on the hash code attack the mixer, the chained cache and the acceptance rule with only what an outsider has (the public kit, the frozen object, the spec, the harnesses) and publish the break or the bound they reach. No outside review has run yet.

    +

    No hash has stayed free of chips forever. Igneum does not claim to. It states the gain its own model finds, the response takes a week, and both are measured. The model is public: the numbers; the claim is tested by the in-house adversarial pass and the public benchmark. Monero has run on RandomX since November 2019; one chip shipped against it, Bitmain’s Antminer X5 (September 2023), a board of RISC-V chips at 1.46x per joule over a desktop CPU, on silicon believed mining privately from about 2021; RandomX v2 was released on 25 March 2026 with its mainnet activation pending. Bitmain opened Antminer X9 pre-orders on 26 December 2025 for July 2026 delivery, then withdrew the product in mid-May 2026 and refunded buyers before any unit shipped; none has been independently benchmarked. A box with about a 2x per joule edge over the best CPUs, and about 3x over a desktop, was withdrawn rather than face a RandomX re-tune of 1.5x or more. That is the band Igneum’s class v4 model sits in (2.1x to 3.4x over an RTX 5090), and the defence that held was a maintained algorithm with a credible upgrade path, which is what the ladder is.

    One thing takes a person, here and on every chain that exists: writing new code. A chain cannot safely write its own generator, and it cannot safely tell a chip from a wave of honest new cards by hashrate alone. If the design above ever failed, anyone could publish a new generator and miners would switch it on by signalling, as Monero's community can fork. Igneum is built to make that day unlikely, and does not depend on avoiding it.

    Monero's idea, finished for GPUs

    -

    RandomX has kept chips off Monero since 2019 (approximate) by making the mining program random, so the hardware that runs it well is the hardware everyone already owns. The one chip announced against it, Bitmain’s Antminer X9 (pre-orders from 26 December 2025 at 1 MH/s and 2,472 W, about USD 5,600), was withdrawn in mid-May 2026 before any unit shipped; RandomX 2.0 shipped on 25 March 2026 (monero-project/monero issue 10270). Igneum takes the same principle to graphics cards and adds what RandomX never had.

    +

    RandomX has kept Monero on commodity hardware since 2019 by making the mining program random, so the hardware that runs it well is close to the hardware everyone already owns: the one chip that shipped, Bitmain’s Antminer X5 (September 2023), is a board of RISC-V chips at 1.46x per joule over a desktop CPU. The one chip announced against it, Bitmain’s Antminer X9 (pre-orders from 26 December 2025 at 1 MH/s and 2,472 W, about USD 5,600), was withdrawn in mid-May 2026 before any unit shipped; RandomX 2.0 shipped on 25 March 2026 with its mainnet activation pending (monero-project/monero issue 10270). Igneum takes the same principle to graphics cards and adds what RandomX never had.

    @@ -467,7 +467,7 @@ body.all .pager{display:none} - +
    PropertyRandomX, MoneroIgneum
    Changes over timeNone. A fixed design, unchanged for seven yearsA new program every hour, its memory pattern with it; era draws and reserved families on a schedule fixed at genesis. Nobody touches it
    Seed grindingNot applicable, the program comes from the hash inputClosed by a verifiable delay between seed and program
    Useful workNone. Hashing onlyEvery NVIDIA card from 8 GB proves; 12 GB and up mine and prove; 24 GB on the stock server (eleven rented cards, RTX 3060 to RTX 5090, 6 October 2026); they sell proofs to other chains. AMD and Apple cards mine, and a prover for them lands when a zkVM ships one
    Track recordAbout seven years without a shipped chip; the one announced, Bitmain’s Antminer X9, was withdrawn in May 2026 before launchZero years. Every number above is measured and logged with the commands that produced it. The specification, reference hash, test vectors and simulators are public now (git.igneum.network/igneum-network/spec). The node, the miner and the wallet follow to the same host as the repository is published
    Track recordAbout seven years with one shipped chip, Bitmain’s Antminer X5 (September 2023), at 1.46x per joule over a desktop CPU; the one announced beyond it, Bitmain’s Antminer X9, was withdrawn in May 2026 with zero units; RandomX v2 released 25 March 2026, activation pendingZero years. Every number above is measured and logged with the commands that produced it. The specification, reference hash, test vectors and simulators are public now (git.igneum.network/igneum-network/spec). The node, the miner and the wallet follow to the same host as the repository is published

    Measured so far: the same hourly program, generated on an Apple M5 Max, compiled by Apple's Metal and NVIDIA's CUDA on an RTX 5090, produced identical hashes on both, 192 of 192 across two programs. On a 1 GB dataset the 5090 ran at about 228 million hashes a second and the Mac at about 45 million, both bound by random memory access rather than arithmetic. Those are prototype figures, not mining rates. The first prototype dataset was a closed-form function, and a miner could compute items instead of loading them: measured 111x faster that way on the Mac. The 256 MB cache construction replaced it on 3 October 2026. With the cache, computing items on the fly runs 4.8x slower than loading them, measured on the Mac, and the honest rate is unchanged on both vendors. Open: the same shortcut ratio on NVIDIA and on a discrete AMD card, and the time-memory trade-off between the two measured points. Inside the 5090's 96 MB cache the same program ran nearly six times faster, which is why the dataset starts at 2 GB and grows. On 4 October 2026 the live devnet crossed an hourly program change on all three vendors with no pause and no rejected block: a Mac at 26.7 million hashes a second, an RTX 5090 at 123 million and an integrated AMD chip at 2.7 million, every hash doing 128 distinct reads of the memory-hard dataset.

    @@ -806,7 +806,7 @@ body.all .pager{display:none}

    Here are the limits, stated before anyone else states them.

    • A proof in seconds. Not at launch. Proving a full block today needs a cluster of 100 to 200 consumer GPUs, approximate, so Igneum launches with proofs within about a minute and tightens as hardware improves. Users still see their transaction land in one second.
      • -
    • A chip is impossible. No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane and 3.4x with one three times better, under class v4 from the first block: a memory-controller chip that stores the whole dataset and carries a GPU-class datapath beside its memory for the 100,000 ops per hash in the shadow, the range running from a chip core as costly per operation as a GPU lane (k = 1, modelled on the 5090’s measured watts at its knee, 7 October 2026) to a core three times better per operation (k about 0.33); the withdrawn Antminer X9’s claimed figure is a ratio against a CPU core, not a GPU lane, so it does not stand for a chip core against us; the ladder’s second rung takes that bracket to about 2.8x (modelled, 7 October 2026). Class v5 then makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The baseline the work started from, never the launch state: without class v4 the same stored-dataset chip would reach 1.2x per chip and 5x to 9x per joule in our model (6 October 2026); the Ethash chips of this class reached 2.1x to 4.8x (Linzhi Phoenix 2020, Jasminer X4 2021, Antminer E9 2022). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the chip model analysis (6 October 2026); the ASIC history’s Ethash rows; Counter ASIC 3.0 item 8 (the chip’s per-joule edge over the RTX 5090 falls from 5.6x to 2.1x on GDDR7 at k = 1 and to 3.4x at a core three times better, the 5090 at 0.2% less rate; gates G1 to G6 passed, 6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held for about seven years; the one chip announced against it, Bitmain’s Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core (k about 0.33) never measured. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.
      • +
    • A chip is impossible. No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane and 3.4x with one three times better, under class v4 from the first block: a memory-controller chip that stores the whole dataset and carries a GPU-class datapath beside its memory for the 100,000 ops per hash in the shadow, the range running from a chip core as costly per operation as a GPU lane (k = 1, modelled on the 5090’s measured watts at its knee, 7 October 2026) to a core three times better per operation (k about 0.33); the withdrawn Antminer X9’s claimed figure is a ratio against a CPU core, not a GPU lane, so it does not stand for a chip core against us; the ladder’s second rung takes that bracket to about 2.8x (modelled, 7 October 2026). Class v5 then makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The baseline the work started from, never the launch state: without class v4 the same stored-dataset chip would reach 1.2x per chip and 5x to 9x per joule in our model (6 October 2026); the Ethash chips of this class reached 2.1x to 4.8x (Linzhi Phoenix 2020, Jasminer X4 2021, Antminer E9 2022). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the chip model analysis (6 October 2026); the ASIC history’s Ethash rows; Counter ASIC 3.0 item 8 (the chip’s per-joule edge over the RTX 5090 falls from 5.6x to 2.1x on GDDR7 at k = 1 and to 3.4x at a core three times better, the 5090 at 0.2% less rate; gates G1 to G6 passed, 6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), at 1.46x per joule over a desktop CPU; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core (k about 0.33) never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.
    • A guaranteed income floor. No. External proving is a small market today. Igneum's miners' electricity cost in it is close to power, but the price they must charge is the subsidy they forgo, which falls as one over network hash: an edge at scale and nothing more.
    • A memory-hard prototype on every vendor. Not yet. The 256 MB cache closed the shortcut on Apple silicon (computing items runs 4.8x slower than loading them, measured 3 October 2026). The same ratio on NVIDIA and on a discrete AMD card is Open.
    • Finality in the first month. No. No checkpoint locks until the 30-day window has 30 days of history. The first month of mainnet is proof of work with a 12-hour depth, and the text above says so wherever a day count appears.
      • diff --git a/site/randomx.html b/site/randomx.html index ebc61f0a5..7d02aa00f 100644 --- a/site/randomx.html +++ b/site/randomx.html @@ -219,7 +219,7 @@
    -

    RandomX has kept chips off Monero since 2019 (approximate) by making the mining program random, so the hardware that runs it well is the hardware everyone already owns. The one chip announced against it, Bitmain’s Antminer X9 (pre-orders from 26 December 2025 at 1 MH/s and 2,472 W, about USD 5,600), was withdrawn in mid-May 2026 before any unit shipped; RandomX 2.0 shipped on 25 March 2026 (monero-project/monero issue 10270). Igneum takes the same principle to graphics cards and adds what RandomX never had.

    +

    RandomX has kept Monero on commodity hardware since 2019 by making the mining program random, so the hardware that runs it well is close to the hardware everyone already owns: the one chip that shipped, Bitmain’s Antminer X5 (September 2023), is a board of RISC-V chips at 1.46x per joule over a desktop CPU. The one chip announced against it, Bitmain’s Antminer X9 (pre-orders from 26 December 2025 at 1 MH/s and 2,472 W, about USD 5,600), was withdrawn in mid-May 2026 before any unit shipped; RandomX 2.0 shipped on 25 March 2026 with its mainnet activation pending (monero-project/monero issue 10270). Igneum takes the same principle to graphics cards and adds what RandomX never had.

    @@ -230,7 +230,7 @@ - +
    PropertyRandomX, MoneroIgneum
    Changes over timeNone. A fixed design, unchanged for seven yearsA new program every hour, its memory pattern with it; era draws and reserved families on a schedule fixed at genesis. Nobody touches it
    Seed grindingNot applicable, the program comes from the hash inputClosed by a verifiable delay between seed and program
    Useful workNone. Hashing onlyEvery NVIDIA card from 8 GB proves; 12 GB and up mine and prove; 24 GB on the stock server (eleven rented cards, RTX 3060 to RTX 5090, 6 October 2026); they sell proofs to other chains. AMD and Apple cards mine, and a prover for them lands when a zkVM ships one
    Track recordAbout seven years without a shipped chip; the one announced, Bitmain’s Antminer X9, was withdrawn in May 2026 before launchZero years. Every number above is measured and logged with the commands that produced it. The specification, reference hash, test vectors and simulators are public now (git.igneum.network/igneum-network/spec). The node, the miner and the wallet follow to the same host as the repository is published
    Track recordAbout seven years with one shipped chip, Bitmain’s Antminer X5 (September 2023), at 1.46x per joule over a desktop CPU; the one announced beyond it, Bitmain’s Antminer X9, was withdrawn in May 2026 with zero units; RandomX v2 released 25 March 2026, activation pendingZero years. Every number above is measured and logged with the commands that produced it. The specification, reference hash, test vectors and simulators are public now (git.igneum.network/igneum-network/spec). The node, the miner and the wallet follow to the same host as the repository is published

    Measured so far: the same hourly program, generated on an Apple M5 Max, compiled by Apple's Metal and NVIDIA's CUDA on an RTX 5090, produced identical hashes on both, 192 of 192 across two programs. On a 1 GB dataset the 5090 ran at about 228 million hashes a second and the Mac at about 45 million, both bound by random memory access rather than arithmetic. Those are prototype figures, not mining rates. The first prototype dataset was a closed-form function, and a miner could compute items instead of loading them: measured 111x faster that way on the Mac. The 256 MB cache construction replaced it on 3 October 2026. With the cache, computing items on the fly runs 4.8x slower than loading them, measured on the Mac, and the honest rate is unchanged on both vendors. Open: the same shortcut ratio on NVIDIA and on a discrete AMD card, and the time-memory trade-off between the two measured points. Inside the 5090's 96 MB cache the same program ran nearly six times faster, which is why the dataset starts at 2 GB and grows. On 4 October 2026 the live devnet crossed an hourly program change on all three vendors with no pause and no rejected block: a Mac at 26.7 million hashes a second, an RTX 5090 at 123 million and an integrated AMD chip at 2.7 million, every hash doing 128 distinct reads of the memory-hard dataset.

    diff --git a/tools/ci/ledger-text-check.mjs b/tools/ci/ledger-text-check.mjs index 59094533e..7fca5f218 100644 --- a/tools/ci/ledger-text-check.mjs +++ b/tools/ci/ledger-text-check.mjs @@ -22,7 +22,7 @@ const REQUIRED = { ['G4', 'admin keys in consensus'], ['X8', 'No listing is arranged, promised or sought by the project'], ['X31', 'The public testnet is armed: three seed nodes and the public RPC are up, and it opens on the go word.'], - ['C2', '2019 (approximate)'], + ['C2', 'Monero has run on RandomX since November 2019'], ['X34', 'was withdrawn in mid-May 2026 before any unit shipped; RandomX 2.0 shipped on 25 March 2026'], ['X36', 'Bitmain opened Antminer X9 pre-orders on 26 December 2025 for July 2026 delivery, then withdrew the product in mid-May 2026 and refunded buyers before any unit shipped; none has been independently benchmarked.'], ['X35', 'so the launch number is the class v4 row'], @@ -61,7 +61,7 @@ const REQUIRED = { ['G3', 'there is no team page'], ['G4', 'no admin keys in consensus'], ['G6', 'Pools can be bypassed on transaction choice'], - ['X34', 'About seven years without a shipped chip; the one announced, Bitmain'], + ['X34', 'About seven years with one shipped chip, Bitmain'], ['C3', 'Chips arrived, as on Kaspa, whose hash was designed to welcome them'], ['C3', 'Kaspa has run in production since 2021 (approximate)'], ['C5', 'Inclusion is not confirmation on either chain'], From cf521c467d3ff8a67c93d15b8f456a1bb7f0d9e3 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:32:55 +0000 Subject: [PATCH 07/11] Counter ASIC 3.0 status: the whole 60x file (six keys) landed on both lines, the index fold as a class v6 design row, class v5 level with v4 at the 5090's knee (the knee stands, the note off, the A4000's loss a cap effect), lane B's SRAM-store and HBM4E readings and main's three orders on them, the shipper's three readings and the cut tip edf77203, lane A's cut and verdict (the stored-dataset chip closed by no layer; the floor and a per-tier ceiling the numbers) with main's schedule to price, the snapshot digest stamp and the genesis difference as a gate on the pin, main's words Co-Authored-By: Claude Fable 5.1 --- docs/plans/counter-asic-3-status.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 1bfc3cdb9..11d43ee45 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,7 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. THE FAST-TIME GATE ON THE RE-CUT: SUMMARY PASS (cross-0324-c9e385eb) at 22:49:32Z (23:49 BST) on the shipped 0.3.24 re-cut c9e385eb (igneumd 7a841b20..., igneum-miner 1e209b9e..., igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 22:36:25Z to 22:49:32Z, every check green: rung 1 by signal at epoch 6 (22:42:54Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (22:44:54Z, 4 of 4, 9,985 bps), 11 of 11 ids equal to the CPU verifier's, the stale node 86 of 86 refused with 0 accepted after the first refresh, the restart step across the boundary on a kept datadir resynced in 28.1 s with the catch-up done after 10 s and 0 of its own blocks during it, four sinks equal at 660, honest nodes 0 PoW rejections; record on v5-fasttime 76276be6, docs/design/class-v5-harness/fasttime/cross-0324-c9e385eb.json. The 0.3.24 move's gates left (the shipper's correction of this record): not F9 and F1's full 10^5 PASS (landing about 00:40 BST, too close to the 00:52 ceiling) but an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, max attempt 25), any non-zero holding the move, the full 10^5 the record line after; the minute named by the fleet on the last FETCHED plus ten once the build-server lane's c9e385eb pairs land. THE 61-ROW ERA READING (the v5 lane, box 2, 23:4x to 23:5x BST, docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log): 0 of 61 refused by the 0.995 floor at the table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), every class v5 draw on the class v4 attempt; era-drawn-28 (id 5e9eb01efbbf653e, attempt 6, R 15, the worst of adv-cache-2's census at 1.7451x) reads its biased site 15 at 0.9969, over the floor by 0.0019; era-drawn-25 (1.3571x, R 21) site 11 at 0.9994; the eight over 1.2x span 0.9965 to 0.9997 while the eight few-item hot sets sat 0.003 to 0.013 under the line. Main's sentence opens AP-F8-6 and section 14 verbatim with the two-instrument reading under it. THE CLASS V5 ATTEMPTS CENSUS for 1.4.7 (1,000 f8 seeds through the chain draw, v5-attempts-census-1000.log, the crypto lane's form): 3,219 candidates, 2,219 rejected, per-candidate rejection 0.6893 (sub-version 3: 0.68), accepted attempt mean 2.219, 0 exhaustions, P(256 consecutive) 4.4e-42; first failing part (a') 83.4 percent of rejections, (a) 10.7, (b) 3.0, (c'') 1.2, (c''') 1.0 (0.7 percent of candidates, one in 140: the floor's own share, 0.045 on the attempt mean), (c) 0.7 together, (c') none; the 5.14 percent of class v3 that 1.4.6 quotes is the audit lane's to replace. Both on class-v5 at 3b1dffd6 with main's sentence (891dd008), the mirror's master merged (e0471019: AP-F8-1's update and AP-F8-4 taken, the program-id recipe form with the state tag, no conflict), the design page's pre-public scrub (the founder's name six times, gone), M35's status word and the regenerated public ledger; the push waits on the full gate and the pinned-packs test on the merged tree (the proof that e5a4ac5978462156 and the other ids still derive under master's recipe form). THE 00:00 BST READINGS (the crypto lane; the verified roll-up of all nine lanes in section 13 of in-house-pass.md on crypto-engage, every branch tip read from the mirror and igneum-pow identical to 017e7037 on each). adv-accept, tip a7c49399 (about 5.5 box-hours, 0 pod-hours): 182,646 distinct accepted programs drawn (18 percent of the 10^6); eight pass every part of the frozen rule and flag the live hot-set test at 2^24 (X at 0.1 percent +0.102 to +0.221, 1.54x to 2.24x), all in the lowest 34 stand-in-ratio seeds against 0 in 20 random; each about 1 MB of items holding 0.26 to 0.41 percent of reads, 1.002x at the largest; the mechanism a near-saturated source at one site mapped by the era stride to one fixed item (plus two lesser shapes); the exemplar reads the same under the class v5 dataset. Against the class v5 floor: 8 of 8 refused; 3 mild residuals missed (adv-cache-2's rotation class, a load_index question not a floor question); 6 clean programs refused among the 9 deepest (the 2.4 percent). Q2 BOUND (54 programs plus 17 reads, 0 disagreements). Row 90: 0.6787 per candidate, (a') 83.3 percent, 0 exhaustions, P 8e-44. Partial named: 18 percent of seeds, 54 live rows, row 90 at half; a longer pass adds rows of the same shapes, not a different answer, unless a seed reads a hot set over 1 percent of reads, which 182,646 draws did not produce. THE PER-LOAD CLASS CLOSED (the research lane, for main; clock readings UTC): the per-load shadow fix held for distinctness and then met the value-level requirement from adv-cache-2, and the construction did not survive it; the per-load 16 x 27 class is dead as a chain class. 22:44 the attempt verdicts on four seeds (igneum-genesis 0 of 32 accepted); 22:47 the 64-seed census under the full rule (duplicate lanes at a load row plus the one-count of every index bit per site over the 64 units, 6-sigma band): 22 of 1,621 candidates accepted (1.4 percent), 42 of 64 seeds exhaust the chain's 32 attempts (an epoch without a program); the first failing test per candidate: biased index bit 775, duplicate lanes 643, the base rule 110, (b) 43, (a) 28; candidate 0 of the class carries index bit 0 set in 40 of 1,024 addresses (z 29.5); 22:52 the suite green (64 + 5 + 7 + 4 + 19 + 2 + 7); the acceptance rule with BiasedIndexBit for this class and the tests pushed as the record, the file's 20.2a closed. The structural reason: 27 passes of a 16-instruction map right before a load is an iterated small function and collapses or biases the load's address register before any base instruction re-randomises it; the class v4 shape has 64 base instructions and 16 loads between its block and every load. Both exports were accepted only because the rule did not model the placement; their PC 1 rows stay as an energy reading of the placement, labelled unsound. Rank 4 and the USD 200 M capex row rest on a construction not shown to exist (chip model 5.11's clause marked so in this landing); the sound form is one pass of a 432-instruction sub-block per load (a program segment, not an iterated map), a new class to draw, accept and measure, not tonight's. Replicated by a second instrument: the class v4 shape on this pre-amendment generator carries the adv-cache-2 product bit at address bit R exactly in 14 of 17 drawn eras (one-count 250 or 780 of 1,024, z 15 to 19), 0 duplicate pairs across the eras. What stands from the two prototypes: the tile block (bit-exact on the Metal reference, the AVX2 verifier at 0.047 us per tile, the Apple emulation cost 35 to 78 percent) awaiting its 5090 rows; the per-load placement closed. THE SPEC REWRITE ON MASTER (the site audit lane, 8b834634 at 23:56 BST; gate GREEN on 64e2a91b, 71 checks; the igneum-pow suite green on the box for that commit with derivation.rs and spec_readback.rs): spec 01 sections 1.4.3 and 1.4.6.1 to 1.4.6.6 rewritten to 017e7037 with the 20-row constants table (ACCEPT_TAG, the window-cap literal, MAX_SATURATED as the first refused count with the 163 message noted) and the 6-row pinned-ids table with Devnet 3's full genesis hex; the shadow block in 1.7; the ninth era draw in 1.13.1; tools/ci/spec-constants-check.mjs in the gate (known-failed first, every Constant | Value | Where table, pending rows skipped while absent); igneum-pow/tests/spec_readback.rs (ids derived through the crate, each class v4 row drawn to its attempt); ledger AP-F8-5 after AP-F8-4; the ledger-page fix (both heading forms, the pass as its own section, known-failed self-test in the gate; AP-F8-1, AP-F8-4 and AP-F8-5 render on /ledger); the fud-ledger's two prize clauses and "paid independent cryptanalysis" removed at the source so the regenerated page carries neither (commit 90424d5a, merge 64e2a91b). A HARDWARE FACT IN DISPUTE, for main: tonight's 5080 efficiency rows came from PC 1 jobs (run-ca3-pc1-v4-eff-5080-20261007-b and -c), the audit lane's record reads the RTX 5080 and the Arc B580 on PC 1, the hash lane's 22:09Z device list on PC 1 shows the 5090, the 9070 XT and the 4070 only, and main places the 5080 and the B580 on PC 2; identity-check.sh's "PC 2" substitution text names cards and is left card-free until the PC 2 job's own --list settles which cards sit where. THE IDENTITY CHECK'S PC 2 TEXT (the CI steward, 00:05 UK on 8 October): tools/ci/identity-check.sh rewrites "PC 2" card-free as "the second Windows rig" (commit 40f2be54, merge 0d2cf334, gate GREEN 71 checks, identity grep 0 hits over 306 export files and 52 served pages); line 69's PC 1 list untouched; the reason recorded in a bash comment above the perl call. THE 32,400 FLOOR LOST (the node lane, 00:0x UK on 8 October): dn3-g1's chain read DAA 25,126 at 23:52:03Z and 25,169 at 23:52:38Z, so the publish DAA passed 25,200 at about 23:53:09Z with no 0.3.24 move made (build-1's three Devnet 3 nodes last restarted about 21:31Z on the 0.3.23 move; the old seed holds 38 peers on ba75bf6f; no move minute was named). The next boundary is 36,000 (epoch 10), about 02:52Z on 8 October (03:52 BST) at 1.0 DAA/s, holding for a publish up to DAA 28,800 (about 00:53Z, 01:53 BST). Two routes put to the shipper and main: the same re-cut script on release-0.3.24-node (program_class_v5_activation_daa 36,000, nothing else, the same gate set, about 20 minutes to the pin line), or the fleet names its minute first and the floor is cut from it in one go (publish DAA plus 7,200 to the next 3,600) instead of a fourth chase; the pin c9e385eb stands meanwhile. THE FLOOR RE-CUT FROM A NAMED MINUTE (the shipper, 00:1x BST on 8 October, under the slip rule main set with the object commit): the floor re-cuts once more to 39,600 (epoch 11, about 04:52 BST) from a move minute the shipper named: 02:00 BST on 8 October, or the fleet's last FETCHED plus ten if later but before 02:53 BST (DAA 32,400, the ceiling); the node lane's pin line in about 20 minutes with the new Devnet 3 digest; the F9/F1 interim read at 01:55 BST; the publish minute equals the move minute (the apps' entries at or after it); the fast-time SUMMARY PASS reruns on the new pin as part of its gate set; the cause of the lost floor named: the c9e385eb pairs and the two PC jobs unreported for forty minutes, so the fleet had nothing to point its move file at. "slot closed" on PC 1 still waits on the host job's exit. THE 0.3.24 NODE PIN AT 39,600 (the node lane): dfbd1e10 on release-0.3.24-node (both mirrors, 23:54:13Z) = c9e385eb with program_class_v5_activation_daa 39,600 (epoch 11), nothing else; pairing igneum-pow 1c420786; every gate green at 00:01:52Z (build 23:56Z rc 0 at gate priority, igneumd 4870ccf2..., igneum-miner aa8c2978..., /srv/artefacts/0324-dfbd1e10/node-lane; pow 19, consensus 134, p2p-flows 38, exec 47, core 175, miner 28); the Devnet 3 canary set (23:56:33Z to 23:58:13Z): digest b1ba78229b069dc395fa666638a686a66615eb760d251798adfa6a654a415f82 on igneum-devnet-3 from ba75bf6f, object version 6 stamped (block version 1538), the override file refused, shutdown 2,015 ms, two empty nodes handshaking on it, the shared-devnet dialler rejected, a 2720d8d2 node refused on the digest both ways; the testnet canary b2e856ed unchanged (byte 7, a live old-object testnet node refused). The cut's read: dn3-g1 at DAA 25,169 at 23:52:38Z (1.0 DAA/s), the publish DAA at the named minute 01:00Z about 29,211, plus 7,200 = 36,411, the boundary 39,600 about 03:53:09Z on 8 October (04:53 BST), holding for a publish up to DAA 32,400 (about 01:53:09Z, 02:53 BST). The one gate running: the fast-time pair on dfbd1e10 (about 13 minutes from its start). c9e385eb is void as a pin; the F9/F1 interim read armed at 00:55Z. THE TWO PC QUEUES AT 01:03 BST (the hash lane): PC 1's "slot closed" has not come (the shipper's 0.3.24 host job, the build-server lane's, took the slot at 22:13Z for an expected two to three minutes; nothing reported in 110 minutes); nothing of the hash lane's has run on PC 1 since 22:09:25Z; the v5 kit fetch and the 9070 XT v5 bench are prepared and unpublished (tools/ca3-v4-amend/pc1-publish-20261007.sh, steps v5-kit and v5-amd), so no 9070 XT class v5 fingerprint exists yet; the lock protocol holds unless main says the lock-free pair goes ahead of the silent host job. PC 2's "clear" has not come either (the 0.3.23 take 3 smoke and the scheduler proof unreported by either lane); the Intel job is prepared and unpublished. THE HARDWARE FACT, read from tonight's PC 1 lines: nvidia-smi on PC 1 lists GPU 0 RTX 5090 (bus 01:00.0) and GPU 1 RTX 5080 (bus 0D:00.0); its OpenCL list carries the RX 9070 XT (gfx1201) and the integrated gfx1036 and no Intel platform; so the 5080 is on PC 1 (the audit lane's record right, the 22:09Z device-list summary short by one card) and the Arc B580 is not, which agrees with main's word that it is PC 2's eGPU; the kits row, the bench notes and identity-check's card-free PC 2 text stand on that. The locked PC 1 jobs stay parked (the 5080 full grid, the third 5090 pass, SM-sparse, the microbench and packs knee states, the two Ember tunes, the hot-table ldcs rows); the lock-free CA4 rows queue after the v5 bench on the same "slot closed". THE 00:00 BST READINGS, THE OTHER THREE (read by the crypto lane from each branch's report on the mirror at 01:03 BST; the roll-up section 13 of in-house-pass.md at crypto-engage c84ba51b with adv-accept's reading at 1b4e07ff; all nine branch tips read back from the mirror and igneum-pow IDENTICAL to 017e7037 on every one: adv-mixer d2ba3134, adv-mixer-2 2a632579, adv-mixer-3 4ebe2455, adv-cache 555c3e42, adv-cache-2 9384ee09, adv-cache-3 9452c0bf, adv-accept a7c49399, adv-accept-2 92168536, adv-accept-3 0c150e3c). adv-accept-3 (exhaustion or steering of the draw), tip 0c150e3c, every sweep ended 23:05 BST, about 3.3 box-hours, 0 pod-hours: Q1 exhaustion BOUND (per attempt accept 0.323, reject 0.677 ((a') 0.568, (a) 0.079, (b) 0.022, dynamic parts about 0.009), geometric histogram, P(exhaust) 0.677^256 = 4.6e-44, 0 of 16,337 seeds at the cap); Q1b the last resort FINDING (correctness; the mirror fired at cap 256 byte-identically; of 3,000 last-resort programs the real rule rejects 271, 9.0 percent: 251 by (a), 14 by (b), 6 by (c) distinct sum; handed out unchecked; unreachable; closed in class v5 by 8ca66afa, AP-F8-3); Q2 steering BOUND (45 of 48 planted rows fired, the real rule rejects every effective plant by (a'); 975 seeds at the first part, min ratio 0.998, 18 of 18 chain re-draws equal); Q2b the price of a seed property at 1 in 10^6 tries is a shadow block with 38 multiplies of 256 against a mean 74, about 2 to 3 percent of the f = 1 chip's energy per hash, the load critical path worth nothing at the memory activate ceiling; Q2c the 256-unit ratio is noise as a selector; Q3 program id FINDING (documentation: the "sub/" || 3_le16 suffix omitted from program.json and spec 1.4.6; a text-derived implementation computes 30956569d8f3d8d7 for Devnet 3 against the pack's fce15bf61030be57; 0 collisions over 10^7 pairs; fixed as AP-F8-4 at da2fc101); Q4 determinism DONE (the (c'') f64 compare never disagrees with the integer rule on any of the 2^20 + 1 values, margins 0.32 to 0.44 counts; a second interpretation agrees on 5,748 of 5,748 verdicts of 1,792 seeds); Q5 the era lever BOUND (400 eras, no stride under NAF weight 7, all 31 rotations, 354 distinct interleaves; epoch 0's accepted attempt is 3 under every era, so the era moves the address map, not the program). Partial named: the steering sweep at 975 of a planned 10^5 seeds (about 8 box-hours more at 32 cores). adv-cache-2 (the hot-set attack), tip 9384ee09 at 23:52 BST, about 2.2 box-hours by wall times threads over 96 (the boxes at load 400 to 600 for the first two hours), 0 pod-hours; two shards still queued at 00:00 (lines-2e30-s2c, warps-devnet-2e25-v2), named partial: Q1 the line index PASS (pooled 16 days; segments max +4.84 sigma against a control's +4.24, lines +5.61 against +5.35, chi2/dof 0.99937, top 0.1 and 1 percent of lines 1.0003x and 1.0002x of control; the 2^35 + 3 x 2^33 census all PASS; 0 mirror mismatches); Q2a the real programs PASS on the hot-set test (devnet at 2^26 1.0002x; Devnet 3 at 2^26 items 1.0071x, lines 1.0000x) with the FINDING at Devnet 3 site 0; Q2b all 64 programs done, every one clear on the hot-set test (items 0.9993x to 1.0075x of the windowed control) but the site class as recorded above (13 of 27 drawn-era over 1.04x, 8 over 1.2x, worst 1.7451x; the v5 floor refuses 0 of 61; AP-F8-6); Q3(1) steering by t PASS (worst cell 3.95 sigma in 2 x 2,112 cells); Q3(2) the weak-day scan PASS over 16,384 days (2^30 derivations in 707 s; worst per-day max bucket +8.13 sigma against the control's +7.78; the plant fired at +1,090); Q3(3) the window layer: the exact distribution matches the 4,096-program census to four digits (top quarter mean 0.3382, top half 0.5811), with a FINDING against the chip model's table: the f = 0.25 and f = 0.5 partial-store rows overstate the recompute share by up to 1.8x at f = 0.5, the full-store (f = 1) verdict unchanged (a correction owed in chip-model-v3's partial-store rows; no served number rests on f under 1); Q4 the prices: the only measured excess over f is the window layer's and the line reference multiplicity (a hottest-lines half store hits 57.8 percent instead of 50 at a higher miss cost than the stride). adv-mixer-3 (the statistical distinguisher and round margin), tip 4ebe2455 at 00:41 BST, still RUNNING at 01:03 (Q3 and Q4 at k = 8 on day 20729, queue 07 in the pool, the SAT ladder at k = 3 timed out; the total box-hours the lane's to give): Q1 the exhaustive round-0 line-index census over all 2^32 t PASS to k = 8 on days 20729 and 20733 and at k = 2, 3, 4, 8 on 20730 (z within 1.5); Q2 single-bit avalanche FINDING at k = 1 (354 and 266 holes, 130,000 cells beyond 6 sigma, the known one-application diffusion), PASS from k = 2 at 2^24 (0 holes, worst z under 5.3 through k = 8); Q2b the t-bit avalanche the same shape; Q3 differential multiplicity over 576 low-weight differences FINDING at k = 1 (695 and 537 deterministic output bits), PASS k = 2 through 7, k = 8 running; Q4 and Q4b linear correlations PASS from k = 1 (worst c 0.00046 to 0.00062, z under 5.1); Q5 rotational-XOR PASS from k = 1; Q6 SAT: k = 1 SATISFIABLE in 137 s (t = 0x49880000 verified through the real code), k = 2 and 3 TIMEOUT at the one-hour cap. The round margin as it stands: no statistic survives 2 of the 8 applications between reads; a chip gets nothing from the k = 1 findings because every read sits behind 8. The lanes' own lines go into section 13.1 as they arrive. THE LANES' OWN 00:00 LINES (adv-accept-3 and adv-mixer-3, 01:0x BST, in section 13.1 of in-house-pass.md): adv-accept-3's P(exhaust) refined to 1.0e-43 per epoch seed from 62,240 full-rule candidates plus 3.0e6 static candidates; Q2 steering BOUND over 19,975 full-rule and 1e6 static seeds, no property buying over about 1.03x at 1 in 1e6 tries; a second documentary FINDING: an implementation written from the spec text (not the code) at 017e7037's spec differs on 264 of 400 epoch programs, the same text-against-code gap as the id suffix (the audit lane's rewrite 8b834634 with spec_readback.rs is the fix; the proof that it closes this is a re-run of the text-derived implementation against the rewritten text, asked); a plant note: the floor-0.97 known-failed variant did not fire because the (c'') ratios are bimodal (accepted 0.989 to 0.999, rejected 0.814 to 0.966), replaced by a single-pass (a) variant that did; 3.3 box-hours, nothing running. adv-mixer-3: about 3.0 wall-hours of sweep plus 4 single-core CaDiCaL hours; the round margin stated as 6 of 8 applications between reads and 70 of 72 per item on every measured statistic, the k = 1 effects one mechanism (the lowest-set-bit trail through one application, dead once both addends carry a difference), nothing saving one application against 9,360 ops per item; still running at 4 cores on build-1 (2^27 and 2^28 avalanche rows, finish about 03:00 BST) and the day-20733 SAT ladder on build-2 (about 03:45 BST); not attempted: multi-bit linear masks and a MILP trail bound. adv-cache-2's own line still owed. ADV-CACHE-2'S OWN LINE (01:05 BST, tip 3f50d6c4; section 13 of in-house-pass.md now carries every lane's reading in its own words plus the verified roll-up): the drawn-era prevalence read on the SAME 32 base programs is 2 of 32 under the devnet era against 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), the mechanism carried by rotl(x times M, R) into the item index unless R is 29 or 30 (2 of 31 rotations), with a sub-class of warp-uniform sources once in 16,000 warps; the window layer's price restated: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the chip model's partial-store rows overstate the recompute share by up to 2.3x on these programs, the f = 1 verdict unchanged (the correction to chip-model-v3's partial-store rows is the coordinator's next commit); partial named (the drawn-era windows census of 4,096 and one line shard in the pool); the longer-pass line: the biased-site rate per era in closed form (the R in {29, 30} rate 2 in 31) and a 2^28 read of the worst site. Nothing of the pass stands between the pool and a higher-class job except two pre-emptable shards on box 2. THE SPEC-TEXT RE-DERIVATION ORDERED (01:06 BST): adv-accept-3 re-derives its 400 epoch programs from the rewritten spec text alone at master 8b834634 (1.4.3 to 1.4.6 grown from 79 to 198 lines with the constants and pinned-ids tables), lease pool 16 --min 8 class adv, row Q4c in its report; the expected reading 0 of 400, any non-zero naming the diverging sentence to the audit lane; the proof that AP-F8-5 closed the text-against-code gap. THE CHIP MODEL'S PARTIAL-STORE ROWS carry a second correction (section 5, 8 October 2026) from adv-cache-2's window-layer reading: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the uniform-store rows overstate the recompute share by up to 2.3x; the f = 1 row, the SRAM column and the full-store verdict unchanged, no served number on f under 1. THE CLASS V5 PACKS TEST ON THE MERGED TREE (the v5 lane, 01:0x UK): the job ran on box 2 the minute two adv-accept holders ended (65 cores; no lease fault, plain starvation before); 19 passed, 1 FAILED: v5_pack_is_the_v4_program_over_the_state_leaves (tests/packs.rs:977), the byte-for-byte compare of every pinned pack file with the crate's export. The ids are EQUAL (v4-genesis exports a217c7f698880830 as pinned; the state tag rides in master's recipe form unchanged); what differs is the program_id_derivation TEXT in program.json, which master's export (the hash lane's AP-F8-4 read-back form) now writes as "... || attempt_le32 || 'sub/' || sub_version_le16" for generator 4 while the pinned packs carry the pre-suffix wording. Disposition: the three pinned packs re-exported from the merged crate (text only; the ids, kernel texts, leaves and the fingerprint 82b19cbde8557ea5 must come out byte-identical, proved by the same test); the CLI rebuilding on build-1 from 51aa5bc4, the export from the box's IGSD1 streams, the packs test and the full suite on box 2 at 16 cores, then the push; readiness about 01:35 UK. The 0.3.24 kit zip (packs-ca3-v5-20261007T221001Z.zip) carries the old derivation text in its program.json files: a text field only, no id, kernel or fingerprint change, so the kit stands for 0.3.24 and the shipper is told; the re-exported packs go in the next kit. THE ONE 0.3.24 KIT, NAMED for the shipper (01:1x BST): packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 the pin pairs with; the fleet keeps placing it. The 23:11 zip packs-ca3-v5-20261007T221001Z.zip (sha256 4aaf9b9e..., /srv/artefacts/packs/ on build-1, from class-v5 7f58af97) carries the same packs, ids, kernels, leaves, fingerprint and derivation text and differs only in the merged kit host code and scripts beside the packs; it is the bench lanes' kit for the fingerprint jobs. The coordinator's earlier line naming 4aaf9b9e as the 0.3.24 kit was wrong and is corrected here. THE SPEC-TEXT READ-BACK RUNNING (adv-accept-3's Q4c, 01:11 BST on build-2, lease pool 16 --min 8 class adv): the same 400 epoch seeds re-derived from the spec text at master 8b834634 alone (1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7, 1.13.1; a fresh text interpretation), compared field for field with the chain draw; the count about 01:21. One sentence already named divergent before the count: 1.4.6 part (c) cites dataset_elem(idx, S[0], S[1]) "of verify.rs" without stating its six operations, so part (c) cannot be computed from the text alone and the derivation takes that one function from the crate; the audit lane is to state the closed form's six operations in the text or the constants table, else 1.4.6 stays code-dependent on that line. A NINTH LIVE HOT SET (adv-accept, 01:12 BST): seed 228763 (id 2c4be0f6dc44c423, stand-in 0.9820) at 2^24 (X at 0.1 percent +0.118, 1.82x the window model), its single hottest item 0xe2cc96 at 1,218,380 reads, 0.057 percent of ALL reads, the largest single item of the pass (40x 100767's), from a NON-saturated source r0 at site 9 (the sel register), saturated-source share 0.000: the third shape at scale, a value-level concentration neither (c') nor a saturation test can see by construction; its 2^20 ratio against the 0.995 floor lands in minutes and decides whether the floor's instrument reaches it (if missed, the exemplar for the next class's non-saturated case). 638990 reads 1.51x beyond the gate with one item at 0.027 percent (r0, no saturation), no hot set; 623492 clean. Tally: 9 hot sets in 37 tail seeds against 0 in 20 random, 269,250 programs drawn; the price unchanged at 1.002x (0.27 percent of reads on 1 MB; one item 64 bytes). The public sentence's "eight of eight" moves to "nine of nine" or gains the first miss when the ratio reads. THE FLOOR REACHES THE NON-SATURATED SHAPE (adv-accept gap-tail3, 01:13 BST): seed 228763 reads minimum site 9 at 0.9809 at the 2^20 sample, the lowest of the pass, REFUSED; 638990 site 2 at 0.9872, REFUSED; 623492 (clean live) site 0 at 0.9922, REFUSED, a seventh false refusal. Final tally over everything the lane read at 2^20: 9 of 9 live hot sets refused (0.9809 to 0.9919), both single-item programs refused, 7 clean-live programs refused and 1 passed among the 12 deepest 256-unit seeds, 3 mild residuals missed at about 1.0004x. The reading: the distinct-index ratio reads any few-item concentration whatever its source, saturated or not, and misses only the diffuse era-stride excess; the class v5 floor closes the hot-set class entire at the 2.4 percent clean-rejection cost; the next class's value-level test is for the diffuse class alone. The public sentence reads "nine of nine hot sets refused" from here (the v5 lane's follow-up cfce57ea rides its push; AP-F8-1 on master updates with the next record commit). THE FAST-TIME GATE ON dfbd1e10: SUMMARY PASS (cross-0324-dfbd1e10) at 00:12:57Z on 8 October (01:13 BST), the shipped re-cut's binaries (igneumd 4870ccf2..., igneum-miner aa8c2978..., igneum-pow 1c420786), build-1 under lease pool class v5, 23:58:56Z to 00:12:57Z, every check green: rung 1 by signal at epoch 6 (00:05:37Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (00:07:46Z, 4 of 4, 9,985 bps), 12 of 12 ids equal to the CPU verifier's, the stale node 95 of 95 refused, the restart step across the boundary on a kept datadir resynced in 36.2 s with the catch-up done after 11 s (4 IsInIBD refusals of its own miner during it, 0 of its blocks accepted), four sinks equal at 661, 0 PoW rejections on the honest nodes; record on v5-fasttime 0a09eb78, docs/design/class-v5-harness/fasttime/cross-0324-dfbd1e10.json. Every gate on the pin is green; the move waits on the pairs on the dl host, the last FETCHED plus ten, and the F9/F1 interim read. THE RE-EXPORT READ (the v5 lane, box 1 with the merged crate ac285733): the three pinned packs' only difference was program.json's program_id_derivation text (generator 4 now "|| 'sub/' || sub_version_le16", generator 5 the class recipe "igneum-program-rw/ ..."); ids, kernel texts, leaves.bin, vectors and the fingerprint 82b19cbde8557ea5 byte-identical; the pinned packs carry the merged text; the full gate and the full igneum-pow suite with the packs test and spec_readback running on that tree, the push and commit string about 01:45 UK; main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2 at class-v5 b5d6368d (nothing with eight of eight reached the mirror). AP-F8-1's two eight-of-eight lines on master move to nine in this record commit. THE MOVE'S SOURCE (the shipper's ruling at 01:05 BST, corrected to this record at 01:1x): the 02:00 BST move does not wait on the build-server lane's pairs; that lane is dark (nothing published since 23:05 BST, nothing answered since 00:17), so the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair at /srv/artefacts/0324-dfbd1e10/node-lane on build-1 (igneumd 4870ccf2, igneum-miner aa8c2978, the pair every gate ran on, native glibc 2.39 on every fleet box), the way dn3-g1 and g2 moved at 22:30; the fleet's puller fetches from build-1, not the dl host. The move waits on the fleet publishing the dfbd1e10 move file and naming the minute (asked 01:05) and the F9/F1 interim at 01:55. The hive and the Windows pairs are the dark lane's loss for tonight unless main gives the shipper the word to build them (asked 01:06); the Mac entry publishes at the minute regardless; if the fleet has not published the move file by 01:40 BST, main and the coordinator hear it with the clock. THE PC 1 LOCK VOID, THE V5 AMD BENCH PUBLISHED (the hash lane, 01:1x BST): the shipper's 0.3.24 host job was never published to the jobs file, so the slot was void (the shipper's "slot void" at 01:05 BST); the v5 kit fetch landed on both PCs at 00:12:06Z (919,273 bytes, sha256 ok); run-ca3-pc1-v5-amd-bench-20261007 published 00:14:19Z (the 9070 XT by name, about 3 minutes, lock-free), its start line printing app_version, so the 0.3.20 or 0.3.23 reading of PC 1's app comes with the fingerprint; PC 2's Arc job needs only the shipper's "PC 2 clear". PC 1's app had NOT taken the 0.3.23 kit as of the last reads (every job log through 21:46Z app_version 0.3.20; the install folder's exe igneum-app 0.3.20, mtime 12:24:42Z, sha256 0443ae17...). The update-return lane (a22d765a2e0355a9f) last spoke at 23:0x BST: the helper workaround for 0.3.20 scripts (truncate cmd.txt, restart the task, wait for helper.alive, then write; or four leading " dev " padding lines), the locked jobs held as they are, power-helper-24 b9a72b9b merged into release-0.3.24 (daa7427b: a silent change becomes a logged line, the helper writes its exit reason), install-close-23 4ad6c199 for 0.3.23's take 3, the re-probe job when PC 1's app has taken the 0.3.23 kit; nothing since. THE SPEC-TEXT READ-BACK PASS (adv-accept-3 Q4c, 01:11 to 01:15 BST on build-2 at 16 cores; report section 6.5 on build/adv-accept-3, log 983-textderive-8b834634.tsv, pushed): the spec text at master 8b834634, implemented fresh without the crate's generator or rule, reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences (every instruction, the chosen attempt, the id, the rejection sequence); the 264-of-400 divergence against the text at 017e7037 is closed, so AP-F8-5 reads fixed on a measurement. The one remaining gap: 1.4.6.4 names dataset_elem "of verify.rs" without its six operations, so parts (c), (c') and (c'') still take that function from the crate; the audit lane's one-sentence closed form (asked 01:1x) closes it, and the read-back re-runs on the new text. THE AMD CLASS V5 FINGERPRINT (PC 1's RX 9070 XT, gfx1201, beside the miners, lock-free): 82b19cbde8557ea5 at 01:16:14 BST, equal to the kit e6c088bb's on Metal, Apple OpenCL and CUDA, self-test PASS, the v4-genesis control 892b6d55a7ddcfcb PASS; the 0.3.24 kit stands on four platforms; Intel waits on PC 2 (held until main's word, since the 0.3.23 take 3 never ran there); PC 1's queue continues with the CA4 unlocked rows. The kits row reads: Metal, Apple OpenCL, CUDA, AMD equal; Intel not measured tonight. THE UPDATE-RETURN LANE'S THREE READINGS (01:17 BST, from the live manifest and the intake): (1) 0.3.23 take 3 (install-close-23 4ad6c199) never reported; the live manifest igneum-app-latest.json reads 0.3.23 published 20:37:44Z with platforms = {mac} only, NO Windows entry, so neither PC has anything to take through its update path; PC 2's app run is still take 1's relaunch from 21:08:43Z (997 uploads, last 00:16Z); (2) PC 1 will not take 0.3.23 unattended tonight for want of a Windows entry; its run win-ae432dc7-20261007-160110 (0.3.20) never restarted (2,376 uploads, last 00:16Z), mining 18.96 MH/s on the 9070 XT; when a Windows entry is published the 0.3.20 engine's OTA takes it with no hand; the 21:41:32Z helper.ps1 write was not the prompt path (0.3.20 writes that file unconditionally), so no screen is owed in the morning for it; (3) the re-probe job (relay/playbooks/pc1-helper-reprobe.ps1 on power-helper-24 69f3c733) waits only on PC 1's exe becoming 0.3.21 or later; the 0.3.20 workaround is cleared to run tonight as a lock-free job so the locked grids go ahead: per grid job, before the first command, empty sweep\cmd.txt, Stop-ScheduledTask and Start-ScheduledTask 'Igneum Power Helper', wait until helper.alive is within 4 s, then write the lines with climbing sequences (in 0.3.20 the skip is the line count at the helper's start, fixed for its life); the helper idle-exits 20 minutes after its last command and the next start must begin over an empty file again; never pad after a command. The coordinator's order to the hash lane on it: the locked grids proceed in the earlier order (the 5080 full grid, the third 5090 pass to the driver's floor, SM-sparse, the two Ember tunes, the hot-table ldcs rows), each with its restore step, under the no-prompt rule; a Start-ScheduledTask that reads the 0x800710E0 refusal again stops the job and reports, nothing escalates. THE LOCKED GRIDS UNDER THE WORKAROUND (the hash lane, 01:2x BST; commit 24f9858e on the mirror): the three lock scripts carry the cleared sequence (empty sweep\cmd.txt, Stop- then Start-ScheduledTask 'Igneum Power Helper', helper.alive within 4 s with a 60 s cap, then dev + command with climbing sequences; repeated before any write when helper.alive is older than 10 s; a refused start 0x800710E0 or no heartbeat stops the lock path with the text on RESULT lines, nothing escalates; no padding; each grid job ends with rgc through the same sequence and the applications clock read back). PC 1's app_version on the v5 bench's start line: 0.3.20 (no Windows 0.3.23 published, nothing to take). The CA4 SM-sparse job run-ca4-pc1-ca4sparse-5090-20261007 runs since 00:20:40Z on the earlier padded script (unlocked rows first, then its 1,300 knee attempt; about 25 to 50 minutes); then in order on the shipper's acks: the 5080 full grid as run-ca3-pc1-v4-eff-5080-20261007-d, the third 5090 pass (1,100 MHz down), the microbench and the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the 5080 grid's knee and best points to the site audit lane for row 17 as read. THE ATTEMPTS CENSUS COMPLETE (adv-accept row 90, 01:34 BST, 20,000 seeds, closing the partial named at 00:00): 42,711 rejected candidates; (a') 83.5 percent, (a) 11.6, (b) 3.0, (c'') 1.1 (459 candidates), constant bit 0.4, saturated 0.3, (c') 0.05, distinct 0.04, lane-constant and bias 0; per-candidate rejection 0.681, flat across attempts 0 to 3 (the halves agree to a tenth of a percent); accepted-attempt mean 2.136, max 28; 0 exhaustions; P(256 consecutive rejections) 2e-43 per seed. The number for spec 1.4.6: under sub-version 3 the per-candidate rejection is 68.1 percent and the expected attempt 2.1. adv-accept's shards run on in the pool's gaps under the mechanical yield; the box-hours cross 8 later tonight. CLASS-V5 LANDED ON BOTH MIRRORS (the v5 lane, 091a0758 at 01:40 UK): the full pre-push gate GREEN at 71 checks (stamp on 48d38493, the last code change); the igneum-pow suite on box 2 (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs byte-identical to the merged crate's export, so e5a4ac5978462156, 7c54302b487340a1, a217c7f698880830 and 82b19cbde8557ea5 hold under master's recipe form, recheck 2, scratch 7, spec_readback 2); spec-constants 28 rows agreeing; identity grep 0 hits. Carried since 61588347: main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2; the 61-row era reading and the class v5 attempts census on the spec, the page and the ledger; AP-F8-3; spec 1.4.7 and 1.8.6 with the constants and id tables; the AMD fingerprint row; the kits branch and master merged; two corrections the proofs found: master's program_id_derivation text lacked the class v5 rung-0 arm (the v5 packs' text named the class recipe while the id was the plain form; the arm added to the TEXT, re-exported, ids unchanged; a post-freeze change on the class-v5 line, so 0.3.25's pairing, never 1c420786's), and the public-export scrub (the founder's name six times on the page, the zone name in three files; gone). Incoming to the page: the Arc fingerprint, F9 and F1. THE MOVE FILE NOT PUBLISHED (the shipper, 01:41 BST): build-1's /fleet/move.json still names commit 2720d8d2 with the 22:30 BST minute; no FETCHED count, no named minute; the fleet lane (ac055d60427caab99) has answered nothing since its 22:4x report (asks at 01:05, 01:16 and 01:41; its task output last written 22:21 BST, its last action a hand read of dn3-g1's proven share), the second dark lane beside the build-server lane (last written 22:36 BST). So 02:00 BST cannot hold; the 02:53 BST ceiling (DAA 32,400) stands only if a signed move file lands at once and the 34 pullers fetch inside forty minutes; main has the clock line with the two options (wake or replace the fleet lane; or a fourth re-cut from a morning minute, the Mac entry standing down with it). The publish record's shape stands: the Mac entry at the minute (staged, DMG 1aa301cc, both folders, armed); the hive and the Windows pairs on main's word; the pairing 1c420786, 091a0758 0.3.25's. Every other gate on dfbd1e10 green and recorded. THE RUNG-0 ARM CONFIRMED (the v5 lane, 01:4x UK): 987e90e8 touches only Program::program_id_derivation, the text in program.json; Program::program_id untouched (the v5 rung-0 plain-form branch since the freeze); the crate at 091a0758 and 1b5684ec (master 35602b30 merged, pushed 01:41 UK) derives every pinned id byte for byte (packs 20 on box 2 comparing all three pinned packs' files including program_id and leaves.bin; spec_readback 2); the shipper told 091a0758 and 1b5684ec are 0.3.25's pairing, 0.3.24 on 1c420786. THE SM-SPARSE JOB (run-ca4-pc1-ca4sparse-5090-20261007, exit 0 at 00:41:53Z, 1,171 s, the 5090 alone, every fingerprint matched, the Power Helper answering every command on the padded write, the card left unlocked at 2,855 MHz): the SM-sparse reading does NOT exist; the research lane's worker ran its base kernel on every variant row (its race line "race 0 ms variant base" on all 48 rows, no NVRTC compile text), so --bench never honoured --variant sp-w32; the sparse rows equal base in rate and drift in watts with the card's heat only; the rerun waits on the research lane's exe honouring the flag. What stands: a repeat of the efficiency pass at two states, 32 s rows, the card alone: v4 unlocked 137.07 MH/s at 465.5 W (0.294 MH/W), at 1,300 MHz 134.26 at 309.9 W (0.433; 155.6 W back for 2.05 percent of rate); v3 unlocked 136.71 at 331.6 W (0.412), at 1,300 134.03 at 219.4 W (0.611; 112.2 W back for 1.97 percent); the v4 premium 133.9 W unlocked, 90.5 W at the knee; the three power fields agree within 0.2 W on every row (power.draw = instant = average on driver 617.14), which settles the field question on PC 1's side and leaves the 5080's 110 W gap to the fleet's rented card's sampler. Next on the shipper's ack: the 5080 full grid (-d) through the cleared helper sequence, the third 5090 pass, the microbench, the seven packs, the two tunes, the hot-table ldcs rows (kit and job at 292fcc75). THE --variant FAULT FIXED (the research lane, counter-asic-4, UTC clocks on 8 October): 00:44 the fix (a --bench with --variant runs the pinned race and installs the named kernel; the RESULT line carries variant=, sparse_blocks=, block_warps=; a served kernel other than the requested one prints variant_not_installed); 00:46 the known-failed test on build-1 against the real class v4 pack, no card (base: race off, 524,288 blocks of 32, "variant base"; sp43-w32: race on, 43 sparse blocks of 32 warps, the rewritten kernel with the nonces argument and the unit function, 43 blocks of 1,024; PASS; before the fix both read the base shape); 00:46 the Windows exe igneum-worker-cuda-ca4sparse3.exe sha256 0ba97edcd5c46a302a7ff5ddd1bbb1e493ca15f64d0757820ed645972df3bb56, mingw exit 0; the commit after 2d0013d1; the hash lane has the sha, the test's lines and the rerun's job shape (the same 48 rows, the race line per row); the op-mix re-weight stays behind the SM-sparse reading, the served 3.4x standing; the clean efficiency repeat in the file's 20.3a (6.6 pJ per counted op). THE SPEC'S LAST CRATE-DEPENDENT SENTENCE CLOSED (the site audit lane, master 56eebc0d at 01:49 BST, gate GREEN on c2c92eab, 71 checks; spec_readback now 3 tests): 1.4.6.4 states dataset_elem in full (the eight operations, the three constants, 32-bit wrapping) with two pinned vectors (dataset_elem(0x00000fed, 0x9E3779B9, 0x7F4A7C15) = 0x5c7dabd2; dataset_elem(0x0fffffff, 0, 0) = 0x7662c1ec) that spec_readback.rs reads from the text and checks against the crate, so part (c) computes from the text alone (34845c47); 1.4.6.5 names the class v2 figures as class v2's and carries the shipped rule's own census sentence (20,000 seeds, 68.1 percent rejected per candidate, the per-part shares, mean attempt 2.1, max 28, 0 exhaustions, 2e-43). The text-derived re-run on this text is the proof it is sufficient end to end (asked of adv-accept-3). THE MOVE FILE STAGED (the shipper, 01:5x BST): id mdfbd-1, commit dfbd1e10, want_digest b1ba7822, both pair slots on build-1's served tarball dfbd1e10-node-lane.tgz (e59ed0e6), at_epoch 0, signed with the fleet key on the Mac and verified against the fleet's public key in the puller's namespace; the read-back on placing it: the served file's id by curl and the first FETCHED on the relay intake; the 34 pullers fetch inside their one-minute timers (27 MB from build-1), the last FETCHED about five minutes after the file, the earliest minute ten after that. THE REAL LATEST-PUBLISH CLOCK: the file alone halts every miner on the restart, because each box's pack gate PAIR_MINER_SHA16 lacks aa8c2978 and the puller does not carry the file's miner sha into the restart environment; so route (A) also needs one ssh line on each of the 34 boxes before the minute with the fleet's tooling (the fleet lane's, or the shipper's on main's word). Absent main's word by 02:15 BST the shipper stands the Mac entry down under the ceiling rule (no app alone on b1ba7822) and 0.3.24 becomes a morning minute with a fourth re-cut. ROUTE (A) STAGED TO ONE COMMAND (the shipper, 01:5x BST): the gate script r0324/move/pair-gate-aa8c2978.py in its scratch (dry run by default, apply on the literal argument, the fleet's own Box helper and label list, nothing restarted); the dry run read 33 of 35 boxes, every one carrying the old gate list with fb147dd1 last and aa8c2978 absent, no env-last override; unreachable dn3-relay and p2-4090-1b (dead Vast proxies; they fall off at the move and rejoin by the pull); the apply about 90 s for the 33 with each gate read back and counted. THE F9/F1 INTERIM (the attack-pass lane, read at 01:5x BST): 71,292 seeds, 0 exhausted, 0 panics, max attempt 30; F1 0 failures at 2 h 23 min; the move's gate reads clear. On main's (A): apply 02:00, the file placed 02:02, the last FETCHED about 02:05, the minute 02:15 BST; main has the clock. Nothing applies before the word. THE SPEC TEXT SUFFICIENT END TO END (adv-accept-3 Q4d, 01:52 to 01:57 BST on build-2 at 16 cores; report section 6.6 on build/adv-accept-3, log 984-textderive-56eebc0d.tsv, every row equal to its Q4c row): the spec text at master 56eebc0d, implemented with nothing from the crate (text.rs: 0 igneum_pow imports; dataset_elem from 1.4.6.4, its two pinned vectors checked at start), reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences on every field; no sentence of the generator or acceptance sections needs the crate; the documentary finding (AP-F8-4, AP-F8-5) closed in full on two measurements; the lane at its end, 3.35 box-hours in all. F9 AND F1 AT 00:59Z (class v5 at 1c420786, pairing e5a4ac5978462156, build-1): F9 73,691 of 100,000 chain-shaped seeds written, 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; the attempt histogram 23,119 / 15,981 / 10,805 / 7,547 / 5,181 / 3,415 / 2,439 / 1,653 / 1,119 / 744 / 529 / 389 / 258 / 152 / 113 / 72 / 54 / 40 / 31 / 14 / 15 / 5 / 2 / 6 / 2 / 4 / 1 at 26 / 1 at 30, r about 0.69; the 10^5 about 01:30Z (02:30 BST). F1: the 10^5 redundancy census at 2 h 28 min under its lease with no end marker (18 minutes on an idle box; under tonight's load no minute named); its panic path live and empty, 0 failures the honest reading. Both land as record lines, then the board's close per item on sub-version 3 and class v5. AP-F8-5 ON TWO MEASUREMENTS (the site audit lane, commit 116e6055, master 5c77a7ac at 02:05 BST, gate GREEN 71 checks): the row carries Q4c (8b834634, 0 of 400 with one crate function, section 6.5, log 983) and Q4d (56eebc0d, 0 of 400 with no crate import, section 6.6, log 984); the public ledger and the ledger page regenerated; nothing open in the spec or the ledger on the audit lane's side. THE 5080 FULL GRID (run-ca3-pc1-v4-eff-5080-20261007-d, exit 0 at 01:54:00Z, 4,118 s; PC 1's dock card alone, driver 617.14, app 0.3.20, mem 14,801 MHz throughout; every lock through the cleared helper sequence, every command answered first time, every fingerprint matched, clocks reset and read back): the knee as a reading: the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes (v4 71.19 of 71.41 MH/s; v3 71.11 of 71.28) and falls 5.2 percent at 900 MHz on v4 (67.66), where the 75-minute budget ended the grid (v3's 900 and below not taken; the drift check skipped); so the 5080's knee sits between 1,000 and 900 MHz, a third of its 2,963 MHz boost, lower than the 5090's 1,300 (84 SMs at 2,960 MHz have more compute headroom per unit of its 960 GB/s than the 5090's 170 SMs per unit of 1,792 GB/s; the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: v4 at 1,100 MHz, 71.20 MH/s at 146.6 W (0.486 MH/W; 106.5 W recovered for 0.29 percent of rate); v3 at 1,000 MHz, 71.11 at 103.7 W (0.686; 66.0 W for 0.25 percent). The v4 premium 83.4 W unlocked (253.1 against 169.7), 41 W at the best points (146.6 against 105.6 at 1,100). Per tier: a 5080 owner on class v4 locked near 1,100 MHz draws 147 W instead of 253 for 0.3 percent less rate (MH/W up 72 percent) and the shadow's residual cost is 41 W. Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 71.41/253.1/0.282 ; 71.28/169.7/0.420 (sm 2,963/2,977); 2850 71.41/229.5/0.311 ; 71.29/155.3/0.459; 2700 71.41/209.6/0.341 ; 71.29/149.2/0.478; 2550 71.41/193.0/0.370 ; 71.29/134.4/0.531; 2400 71.41/176.0/0.406 ; 71.29/128.7/0.554; 2250 71.41/165.6/0.431 ; 71.28/117.3/0.608; 2100 71.38/157.7/0.453 ; 71.28/112.3/0.635; 1950 71.37/154.0/0.463 ; 71.26/111.6/0.639; 1800 71.35/150.3/0.475 ; 71.24/113.4/0.628; 1650 71.33/151.4/0.471 ; 71.22/109.7/0.649; 1500 71.30/149.2/0.478 ; 71.19/110.6/0.644; 1400 71.27/149.6/0.476 ; 71.16/107.0/0.665; 1300 71.24/147.9/0.482 ; 71.14/107.7/0.661; 1200 71.20/149.4/0.477 ; 71.12/104.4/0.681; 1100 71.20/146.6/0.486 ; 71.11/105.6/0.673; 1000 71.19/149.0/0.478 ; 71.11/103.7/0.686; 900 67.66/137.8/0.491 ; not taken. Throttle reason 0x400 (the power governor) on every row, never the clock lock, so the draw floor of about 147 W (v4) and 104 W (v3) from 1,500 MHz down is the memory system plus idle, not the SMs: the clock lever is spent by 1,500 MHz on this card. The three power fields agree within 0.2 W on every row. The site audit lane has the knee and best points for row 17; the bench table's 5080 row takes "71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", class v4 cost "+83 W unlocked, +41 W at the best points", hive core 1100 (the mem clock unchanged) once the fleet's rented-5080 sampler question is closed. Next on the shipper's ack: the third 5090 pass, the SM-sparse rerun on the fixed exe, the microbench, the packs, the two tunes, the hot table. THE NIGHT'S MOVE OUTCOME (the shipper, 02:58 BST): main's word on (A), (A') or (B) did not come (asked 01:41, 01:50, 01:53, 01:56 by the shipper and 01:42, 01:52, 01:5x, 02:00 by the coordinator); the gate script not applied (the dry run's 33 of 35 the only read); the move file not placed (build-1's /fleet/move.json serves m2720-1, 2720d8d2, the 22:30 minute, by curl at 02:56); no move minute; the stand-down under the ceiling rule holds from 02:15 (the shipper's stand-down line at 02:15 was not sent, its miss, the state unchanged); the Mac entry standing, not published (staged on DMG 1aa301cc in both folders, the live manifest at 0.3.23). A FINDING: build-1's Devnet 3 seed (the process on 26631 with JSON RPC 27632, the node lane's DAA reader) is DOWN (no such process; node1-dn3 26671 and the observer 26651 run on 2720d8d2; the node lane's 0.3.24 reader on 28690 runs but answers no DAA by the envelope tried), so the node lane's DAA reads since 25,169 at 00:52:38 BST may have stopped with it; at 1.0 DAA/s the DAA passed 32,400 at about 02:53 BST, the 39,600 floor is lost, and the fourth re-cut is from a morning minute main names (before 12:50 BST, or the three heights move with the floor). Every Devnet 3 node is on the 0.3.23 pin 2720d8d2, digest ba75bf6f (the 22:30 move; dn3-j1 behind its proxy unverified since); nothing of 0.3.24 is on any box or in any manifest. The night's 0.3.24: every gate green on dfbd1e10, the kit on four platforms, the move unmade for want of one word and two dark lanes. THE ATTACK-PASS BOARD'S CLOSE (lane (d), 01:58Z on 8 October; record docs/analysis/attack-pass-2026-10.md on the mirror's attack-pass; box-hours approximate: build-2 about 7 h, build-1 about 9 h plus about 6 h of F6 batches and F2 solvers earlier in the day). F9 so far: 89,301 of 100,000 chain-shaped seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 20: 20, 21: 6, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1; r about 0.69), three chunks on their cores to about 02:20Z; F1 the 10^5 redundancy census at 3 h 22 min on 17 threads, healthy, no end marker, 0 failures on its live panic path. The board: F1 shadow redundancy PASS on sub-version 3 (max 5.078 percent at honest-compiler parity; AP-F1-1 on the v5 list at 3.0 percent), running on v5; F2 mixer round margin PASS effort-bounded (no trail under weight 20 to 24 at 2 applications, 29 to 35 at 3, 39 to 47 at 4), not re-run on v5 (the mixer unchanged); F3 chained cache j+1 PASS, not re-run; F4 weak-day census PASS on v4 on the DSP-bound metric with AP-F4-1 reconciled with adv-mixer-2 (median 226, 15 days a century, worst 2050-04-28 at 1.113x), on v5 PASS at 8ca66afa (0 of 2^24 days over 1.1x on both metrics, AP-F4-1 FIXED-AND-PASSED); F5 chip-model sweep FIXED-AND-PASSED (the F2 hour skipped by decision), not re-run; F6 verifier worst case PASS (worst of 10^5 at 8.708 ms half-core; O-1.14 closed, i7-9700K 6.334 ms), not re-run; F7 era draw PASS on all three (0 of 6 re-rolls), not re-run; F8 uniformity FIXED-AND-PASSED on sub-version 3 (60 of 64 under 1.2x; AP-F8-1, 2, 3 closed), PASS on v5 (61 of 64, worst 1.50x, the residue p4, p8, p10; p34 under); F9 edges, hot set, grinding PASS on sub-version 3 (34 of 105,064 edges bounded; grinding +0.004 percent), the exhaustion count running on v5; F10 ladder signal PASS, not re-run (node rule). Findings of the pass, all in-house: AP-F1-1, AP-F4-1, AP-F5-1 (the X9), AP-F8-1, AP-F8-2, AP-F8-3; two operating hazards fixed (AP-H1 the box clean, AP-H2 the shared binary path). The open tail (p4, p8, p10, and p34 on sub-version 3) is named in the public report; no outside party holds it (the attack-pass lane's close wrote "disclosed to the firms", stale wording from before the in-house ruling; its record file is to say "named in the public report"). THE SEED'S DEATH AND THE DAA NOW (the node lane, 03:0x BST): build-1's Devnet 3 seed log /home/build/dn3seed.log ends at 01:09:05Z at DAA 29,732 mid-stream with no stop, shutdown or panic line, so it was killed abruptly (it ran under nohup from a shell, not a unit; no journal names the killer; the OOM record needs sudo the lane lacks); its datadir /home/build/dn3seed/igneum-devnet-3/datadir is intact (13 GB) and it stays down until the shipper says; the lane's reads 25,169 at 23:52:38Z and 28,906 at 00:55:09Z came from it while it lived. The DAA now from node1-dn3 on 28670: 32,659 at 01:57:50Z (the observer 32,660), both on 2720d8d2; the chain passed 32,400 at about 01:53Z, 39,600 lost. The fourth cut in one line: the script on release-0.3.24-node reads the DAA from 28670, sets the floor to the morning minute's publish DAA plus 7,200 rounded up to the next 3,600, commits, pushes both mirrors and dispatches the gate set (about 20 minutes to the pin line, then the fast-time pair about 14); the latest minute before the three heights move with the floor is about 11:50Z (12:50 BST), where the floor reaches 79,200; nothing is cut until main names the minute. A morning item for the box owner: a process on build-1 was killed at 01:09:05Z without a log line while the box carried a load of 400 to 600; the killer (OOM or a sweep's cleanup) is to be read from the journal with sudo before anything long-lived runs there again under nohup. THE BENCH LOG ENTRY (the hash lane): docs/bench-log.md "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080" (both cards' full tables, the knee per card, the best MH per watt points, the premiums at the lock, the lever's limits, the job ids and clocks, the rented-5080 watts note) on the mirror's master as merge 773b93a8 at 02:04:47Z (commit 11c698ad); the audit lane writes row 17's sentence from it. PC 1: the third 5090 pass run-ca3-pc1-v4-eff-5090-floor2-20261007 (1,100 MHz down to 300) since 01:57:03Z, about 28 minutes; then the SM-sparse rerun. ROW 17 AND THE 5080 BENCH ROW (the site audit lane, master 2c5c7f52 at 03:19 BST, gate GREEN on 6eb6fd9b, 71 checks): docs/evidence.md row 17 carries both cards' efficiency passes from the bench-log entry (the 5090's knee, best points and premium; the 5080's 71.41 MH/s at 253.1 W unlocked, 71.20 at 146.6 W at 1,100 MHz, v3 at 1,000 MHz 103.7 W, the premium 83.4 W to 41 W, the knee between 1,000 and 900 MHz, the per-tier reading, the Ember Tune lever), a what-moved table for 8 October, /evidence rebuilt (865a0a5e); site/miner-bench.json's RTX 5080 row states the team's pass as the card's figure ("71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", "+83 W unlocked, +41 W at the best points", hive core 1100 with the memory stock, driver 617.14, the bench-log entry as the source) and keeps the rented-fleet sampler reading with its 110 W gap as the open question; /miners rebuilt at 35 rows (6eb6fd9b); 0 identity hits; nothing deployed, the deploy the morning hand-off. The design pass on ca3-coord (015cc839) now sits behind this master and rebases onto it before its own landing on main's word. THE DESIGN PASS REBASED (the coordinator, 03:2x BST): ca3-coord rebased onto master 2c5c7f52 as the three site commits only (f5b7140c the design pass, 8cc4cbc6 the phone grid, 9ad3fdc9 the six-column row; the two commits already landed through the record branch skipped), site/miners.html rebuilt at each from the merged miner-bench.json so the page carries the 5080's new row ("71.4 stock (71.2 tuned)") under the design; the diff against master is build.mjs and miners.html only; pushed to the mirror (pre-push GREEN); it lands on main's word after the captures, one gate run. ADV-MIXER-3's LINE (read from its report at tip e02297ae, 03:18 BST): queue 17 finished on build-1 at 01:3x BST; Q2 single-bit avalanche at 2^27, k = 2 and 3 on day 20729: 0 holes, 0 cells beyond 6 sigma at band 0.00026, PASS (the k = 1 finding stands as the single-application diffusion); Q2b t-bit avalanche on day 20733 at 2^28: 0 cells beyond 6 sigma at band 0.00018, PASS (k = 2, 3, 4 on 20729 at 2^28 the same); Q3 at k = 8 NOT run (killed at 20:20 BST under the lease rule, not re-queued; k = 2 to 7 clean with 0 deterministic bits on both days), named partial; Q6 the day-20733 SAT ladder: k = 2 and 3 TIMEOUT at the one-hour cap, k = 4 on one build-2 core since 03:05 BST, its cap about 04:05; one pre-emption in its ledger (23:58 BST, 21 minutes of a 2^27 row lost, re-queued); box-hours about 3.0 wall-hours of sweep (build-1 1.9, build-2 1.1) plus about 4 single-core CaDiCaL hours, about 7 with the 20733 ladder. The pass's close with the per-lane table and totals at about 04:05 BST; section 13 on crypto-engage (docs only) merging the current master and going through the gate to the mirror's master so the record cites a master commit. Box 2 at 03:20: adv-accept 87 cores in four shards with three waiting, adv-mixer-3 one core; build-1 load 34, no adv lease. THE DESIGN PASS'S OVERLAP ON THE BOX (the CI steward, 03:33 BST): the 1440 and 390 dark captures of /miners from ca3-coord 9ad3fdc9 taken on build-2 under lease pool 4 (Playwright chromium 1194, the recorded feed; /srv/artefacts/captures/ca3-coord-9ad3fdc9/miners-1440-dark.png 1440 x 4280 and miners-390-dark.png 390 x 9779); the overlap sweep on the same checkout, 390 to 1600 px, light and dark: RED, 3 findings on the change itself: at 1280 px dark and 1600 px light and dark the date span in the lead cell's class v4 line is COVERED by the rate cell (4 of 5 sample points under td.big); 390 to 1024 pass. Cause: the branch's last gate ran on the Mac, which has no browser, so the sweep skipped and read GREEN; on the page the row rule's white-space:nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell from 1280 px up. FIXED at ca3-coord 2ca45001 (the lead cell's rule at the row rule's specificity, max-width 360 px, the class v4 line wrapping with overflow-wrap), rebuilt, pushed; the sweep and the captures re-run on the box before main's word. THE IN-HOUSE PASS'S PATH TO MASTER (the crypto lane, 03:2x BST): adv-accept's box-hours crossed 8 before 02:00 BST and sit near 10 (87 cores in four shards; it sweeps on under the mechanical yield, its reading unchanged); crypto-engage merged master 56eebc0d at 342b6730 (one conflict in funding.md, the pre-public scrub against the rewrite, resolved to the in-house pass with the scrub applied; the founder never named in in-house-pass.md or funding.md), the full gate running, merge-to-master on GREEN; section 13.3: master's igneum-pow moved after the freeze in four files (src/emit.rs and src/generator.rs, the derivation string and its recipe helpers, ids unchanged; tests/derivation.rs and tests/spec_readback.rs), none the hash, so the object the pass bounded is unchanged in every operation the hash performs. THE PASS IN ONE LINE (the crypto lane, 03:2x BST): eight of nine lanes closed, adv-mixer-3 on one SAT timeout (about 04:05 BST), adv-accept sweeping to its 16 box-hour line (9.2 now, the reading saturated at the 1.002x class), adv-cache-2 on one line shard; no break of class v4 sub-version 3; the acceptance's hot-set class closed by the class v5 floor (9 of 9) and its diffuse era-stride class routed to the next class; the weak-day FPGA tail reconciled and closed by a measured redraw rule; the attempts census complete; the spec text proven sufficient by two read-backs; one pod at USD 0.33 in the whole pass, none originated by the lane. THE THIRD 5090 PASS BELOW THE KNEE (run-ca3-pc1-v4-eff-5090-floor2-20261007, running at 02:34Z on its 500 MHz step; the steps lengthen as the rate falls since the batch count was sized from the unlocked rate, about 155 s at 500 against 60 at 1,100; the helper answering every command on the cleared sequence, every fingerprint matched, the 5090 alone). Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 137.09/456.7/0.300 ; 136.79/320.0/0.428 (sm 2,858/2,862); 1100 120.98/275.9/0.439 ; 117.32/198.6/0.591; 1000 110.03/254.9/0.432 ; 106.73/180.2/0.592; 900 97.43/232.7/0.419 ; 94.33/174.5/0.541; 800 86.00/216.3/0.398 ; 83.41/166.6/0.501; 700 75.98/202.7/0.375 ; 73.58/156.4/0.470; 600 65.30/178.2/0.366 ; 63.25/153.3/0.413; 500 53.03/166.5/0.319 ; v3 running. Reading: below the knee the rate falls about 10 percent per 100 MHz on both classes (compute-bound: the shadow and the base program no longer fit the memory wait) and MH per watt falls with it from 1,100 down, so the best point stays where the second pass put it (v4 at 1,200, v3 at 1,300); the driver took every lock down to 500 (the SM clock within 10 MHz), so the floor is below 500 MHz and is not where the optimum lives; the v4 premium below the knee 77 W at 1,100, 75 at 1,000, 58 at 900, 50 at 800, 46 at 700, 25 at 600 (the ALU work shrinking with the clock as the rate does). The exit line, the 400 and 300 rows, the drift check and the restore at its close; then the SM-sparse rerun on the fixed exe (each sparse row reading served= and sparse_blocks=, marked variant_row=FAILED if served as base). F9 AND F1 AT 02:34Z (class v5 at 1c420786, build-1): F9 98,945 of 100,000 seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 18: 39, 19: 19, 20: 24, 21: 8, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1); the last three chunks within minutes of their ends; F1 at 4 h 02 min under its lease, no end marker, 0 on its panic path. The pass record's wording fixed on the mirror's attack-pass at 9474cea8 ("named in the public report"; no "firm", "firms", "escrow", "prize", "paid review" or "Lot" line in the pass record or the ten row records; identity grep 0 hits); the section's merge to master after the two record lines, through the full gate in a detached worktree. THE SECOND SWEEP ON THE DESIGN PASS (the CI steward on 2ca45001, 03:38 BST): the desktop widths pass; RED at 390 px dark only, three findings on the lead cell (the card name and the class v4 line covered by the rate cell), the cause the new 360 px max-width on the phone grid; FIXED at ca3-coord 5158276c (the lead-cell width rule scoped to widths above 1,100 px, the phone grid's lead cell with no max-width), rebuilt, pushed; the sweep and captures re-run on it. F9 PASS ON CLASS V5 (the attack-pass lane, class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, the last chunk written 02:34:54Z): 100,000 of 100,000 seeds drawn through the chain path (era-composed class), 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; histogram 0: 31,454, 1: 21,460, 2: 14,660, 3: 10,263, 4: 7,047, 5: 4,701, 6: 3,297, 7: 2,256, 8: 1,532, 9: 1,027, 10: 702, 11: 509, 12: 365, 13: 216, 14: 153, 15: 103, 16: 80, 17: 56, 18: 39, 19: 20, 20: 24, 21: 9, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1 (first-draw acceptance 0.3145; the mean attempt index 2.185, so 3.185 draws per seed on average; 4,862 seeds, 4.86 percent, at index 8 or above and 255, 0.255 percent, at 16 or above; the 256-attempt cap and the deterministic last resort never reached; the lane's first line read 1.993, a slip it corrected); the exhaustion gate holds for the 0.3.24 move; record docs/analysis/attack-pass/f9-grind.md and the lane (d) section on the mirror's attack-pass. F1 still running (4 h 05 min, 16 cores, 0 on its panic path, no end marker). F9's record on the mirror's attack-pass at 2bcb7e08 (the lane (d) row and f9-grind.md section (d); feature gate GREEN); F1 the one open item before the lane (d) merge to master. THE DESIGN PASS GREEN ON THE BOX (the CI steward on ca3-coord 5158276c, 03:4x BST; build-2 under lease pool 4): the overlap sweep 390 to 1600 px, light and dark, GREEN, 0 findings (the known-failed fixture fired first); the 390 px capture byte-identical to 9ad3fdc9's (the phone shape that passed before), the desktop widths carrying the wrap at 4,640 px tall; the four dark whole-page captures on build-1 under /srv/artefacts/captures/ca3-coord-5158276c/: miners-390-dark.png (sha256 9eec8f27..., 509,158 bytes), miners-1280-dark.png (1b6e636d..., 438,541), miners-1440-dark.png (87387e14..., 445,402), miners-1600-dark.png (d53973cd..., 448,545); the run log /srv/builds/bs-ci-steward/cap-out/run-5158276c.log on build-2. The branch's gate record: a full gate on the Mac skips the sweep (no browser), so the box line is the sweep's verdict for 5158276c; the branch waits on main's word on the look and lands in one gate run. THE IN-HOUSE PASS'S RECORD ON MASTER (the crypto lane): crypto-engage dab0c89f (gate GREEN, 71 checks) landed through merge-to-master.sh --remote build at 03:50 BST as master 00b8cd1b: docs/plans/cryptanalysis/in-house-pass.md section 13 (the roll-up, every lane's reading, the frozen-object note) and funding.md's in-house row and brief, scrubbed under founder-strings-check.sh. AN EXCEPTION OWNED (03:39 to 03:50 BST): the lane's first merge call used the tool's default path, which reads CI on GitHub with gh run list; GitHub is suspended and the rule says never poll it; the tool polled 21 times (each 403, nothing pushed, nothing read); the run's process outlived the task stop and the lane ended it by its pid at 03:50 BST, then used --remote build; the breach is the tool's default against the rule and the lane's for not passing the switch; no state moved on GitHub's side. The coordinator's order on it: merge-to-master.sh's default remote must refuse GitHub while the suspension stands (the CI steward, a gate-side fix with a known-failed self-test), so the rule does not rest on every lane remembering the switch. THE THIRD 5090 PASS CLOSED BY ITS CAP (run-ca3-pc1-v4-eff-5090-floor2-20261007, ended by the 45-minute cap at 02:42:05Z during the 300 MHz step, exit -1, its own finally block never ran; every row taken matched its fingerprint, the 5090 alone): the 500 row's v3 side 51.37 MH/s at 136.4 W (0.377); 400: v4 42.62/152.5/0.280, v3 41.32/131.3/0.315 (sm 390); 300 not taken; no unlocked-end drift check; the driver took every lock down to 400 (the SM clock within 10 MHz), so the floor is at or below 400 MHz. The reading: below 1,300 the rate falls about 10 percent per 100 MHz on both classes and MH per watt falls from 1,100 down (v4 0.439 at 1,100 to 0.280 at 400; v3 0.592 at 1,000 to 0.315), so the optimum stays at the second pass's points (v4 1,200 MHz, v3 1,300) and nothing below 1,100 is worth the knob's time; the v4 premium below the knee shrinks with the clock (77 W at 1,100, 46 at 700, 21 at 400). AN EXCEPTION OWNED: the 5090 sat at the 400 lock (390 MHz, 127 W mining) for four minutes until run-ca3-pc1-clocks-restore-20261008 (02:45:20 to 02:46:30Z, exit 0) started the helper over an empty cmd.txt and sent rgc ("All done"), the card reading 2,880 MHz after; the cause the batch count per step sized from the unlocked rate, so the low steps ran 2.5x longer than planned; the fix in the scripts: the budget check ends the grid with the restore inside the cap, and a probe dev line answered in helper.log counts as the helper up when its heartbeat file stays stale (the restore answered at once with helper.alive stale past 60 s). THE SM-SPARSE RERUN: fetch-ca4-sparse3-exe-20261008 landed 02:49:57Z (sha256 0ba97edc...), run-ca4-pc1-ca4sparse-5090-20261008 published 02:51:15Z on the hash lane's own order (the shipper's acks were for the void host slot); each sparse row reads served= and sparse_blocks= and is marked variant_row=FAILED if served as base; the close about 03:15Z (04:15 BST). THE STEP-BUDGET FIX ON MASTER (the hash lane, merge 9fd8b1d8 at 03:02:03Z on 8 October, commit 0b00c42e, the full gate GREEN): the efficiency pass keeps four minutes of its cap for the restore (every step and lock guarded by the deadline minus four minutes) and sizes each step's batch count from the last rate read for the pack, so a 60 s step stays 60 s as the rate falls; a probe dev line answered in helper.log counts as the helper up when the heartbeat file stays stale (all four lock scripts); the gate check tools/ci/pc1-step-budget-check.sh with the known-failed case first (under the old rule a lengthening grid ends on the cap with no restore; under the new it ends with the restore at 1,500 s of 2,700), wired into pre-push.sh and checks.txt (74 checks). The 5080 Ember tune, the 9070 XT tune pass and the hot-table ldcs rows publish behind the SM-sparse rerun, the microbench and the packs. THE SM-SPARSE RERUN FAILS THE SAME WAY, NOW NAMED (run-ca4-pc1-ca4sparse-5090-20261008, the fixed exe ca4sparse3, started 02:52:48Z): every sparse row served=base sparse_blocks=0 variant_row=FAILED, the worker's own line "RESULT variant_not_installed requested=sp43-w32 served=base race=... variants 1 base only, no race (no other variant named)", no "compile:" text, so NVRTC never saw a rewritten kernel: the variant name is parsed into the request but never added to the race's variant table in this exe; the research lane's emulation test checked resolve and rewrite, not the race list the bench builds (a test of the wrong layer; the known-failed case must be the bench's own race line reading "variants 2"). The rows are base runs; no reading. The queue goes on: the microbench at the rerun's exit (about 03:15Z), the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the SM-sparse question's fourth row stays with the research lane, an exe whose card-free check shows "variants 2" in its race line getting the slot within the minute. CLASS-V5'S F9 ROW PUSHED (the v5 lane, class-v5 1d5e5d23 on both mirrors at 04:04 UK): the page's F9 row (100,000 seeds, 0 exhausted, max index 30, first-draw acceptance 0.3145, mean index 2.185, F9 PASS, the record file named), F1 stated as running with 0 failures (its own commit to follow), the Intel row not measured tonight; master merged twice (2c5c7f52 gated at 5f5e0a5c, full gate GREEN 71 checks at 03:45 UK; 9fd8b1d8 auto-merged and pushed on the hook's light gate, the full gate running on 1d5e5d23); the generated ledger files and the spec-constants check clean on the tree. THE THIRD --variant FIX (the research lane, 03:04Z on build-1 under lease, with the hash lane): the cause of the 02:52Z rows: the race's push looked the pinned name up in the empty order list through the variant lookup, whose on-demand sp path answers for any list, so the sparse variant was "found" and never pushed; the order is now a pure function with membership by name; --list-race prints, with no device, the race order the worker's own option handling builds and whether the rewrite applies: with the job's exact flags "variants=2 names=base,sp43-w32" and "sparse_blocks=43 block_warps=32 rewrite=applied bytes=22261 nonces_arg=1 unit_fn=1" (before the fix variants=1); exe igneum-worker-cuda-ca4sparse4.exe sha256 84846396559004a8df61881c15ecb42fa3fc1010ad99074e0c0b53e81bb1ca3b, the commit on the mirror after 7e9d52a6; the third rerun on the hash lane's queue at the next slot; the two failed runs stay the night's SM-sparse state, the op-mix re-weight held, the served 3.4x standing. THE GITHUB GUARD ON MASTER (the CI steward, tip 2f702735 at 04:05 UK; merges 53773860 and 2f702735, full gate GREEN 71 checks each): fa7e98fe adds the tracked marker tools/ci/github-suspended (suspended-since 2026-10-07T17:02:00Z, removed by main at the cut-over) and two refusals: merge-to-master.sh refuses a GitHub remote (origin by default, or any remote whose URL carries github.com) with one line naming the switch and exit 2 before any gh or git call; the pre-push hook refuses any push to a GitHub remote the same way (the hook reads the remote URL, so a bare git push origin is refused too); known-failed first in both self-tests; the live read on the Mac: merge-to-master.sh --remote origin exits 2, nothing contacted; two follow-ups (9484b988, a08423d4) fix the tool's own --self-test under the real marker. The rule no longer rests on any lane remembering the switch. F1 READ AT 03:05:58Z (the attack-pass lane; the census process itself, not the lease wrapper): state S with 17 threads, 15 cores busy over 45 s, 2 d 19 h of CPU banked over 4 h 30 min of wall, RSS 0.8 to 1.0 GB; computing, not hung. No rows can exist before the end: the harness collects every Report in memory under thread::scope and writes census.csv in one go at the end (no progress print), named as a harness gap in the record. Why fifteenfold against the v4 reference: under class v5 every candidate draw runs the (c''') distinct-index floor over 2^20 (about 1.8 core-s per candidate under the night's load, times 3.2 draws per program, about 5.8 core-s per program before the analysis), so 10^5 programs at 15 busy cores is about 10.7 h of wall, the end about 09:00Z (10:00 BST), nearer the early side as the load fell to 21. Ruling: not killed (a kill loses 4 h 30 min with nothing on disk); the lane (d) section merges to the mirror's master now with F9 and the F1 row reading "running, 03:06Z reading, projected end about 09:00Z", F1's record line in a second merge when it writes; the harness gains a progress line before its next 10^5 run. THE IN-HOUSE ADVERSARIAL PASS CLOSED (04:08 BST on 8 October; an internal adversarial pass, not an independent review; section 14 of in-house-pass.md at crypto-engage c099e818 landing on master through --remote build; every tip read from the mirror at 04:07 with igneum-pow identical to 017e7037 on all nine). Per lane (tip; box-hours; verdict; partial): adv-mixer d2ba3134, about 0.6 plus 1.8 single-core SAT hours, the algebraic structure BOUND, none; adv-mixer-2 2a632579, 0.31, BOUND for every chip, GPU and the verifier with the FPGA LUT-area FINDING (2^-10.8 of days, 15 a century, worst 2050-04-28 at 1.113x) closed by the measured redraw rule, none; adv-mixer-3 981bfff2, about 5.0 wall-hours plus 8 single-core SAT hours, Q1 BOUND (2^32 t uniform at k = 1 to 8, both days and 8 random days), Q2 and Q2b FINDING at k = 1 only and BOUND from 2 to 8 at 2^24 to 2^28, Q3 FINDING at k = 1 and BOUND 2 to 7, Q4 and Q5 BOUND from k = 1, Q6 SAT BOUND (k = 1 in 137 s, k = 2 to 4 timeout), the round margin 70 of 72 per item, partial Q3 at k = 8 not run, multi-bit masks and a MILP bound not attempted, GPU blocked; adv-cache 555c3e42, 0.55, the recompute shortcut BOUND on every row, none; adv-cache-2 91ca5ce1, about 2.25, the line census PASS at 2^35 + 3 x 2^33, the real programs PASS with the Devnet 3 site-0 FINDING, the diffuse era-stride class named (16 of 32 base programs biased under drawn eras against 2 of 32 under R = 29, 8 over 1.2x, worst 1.75x, under 0.1 percent of reads per site, 0 of 61 refused by the v5 floor, AP-F8-6), steering and the 16,384-day scan PASS, the window layer exact and the chip model's partial-store rows overstated up to 2.3x with the verdict unchanged, partial the line shard s2c waiting on build-1 since 23:09 BST; adv-cache-3 9452c0bf, 0.23, the chain-break or skip BOUND on every row with the pebbling optimum under the hold-every-k curve, none; adv-accept c8a98e46, about 9.2 at 03:25 BST running to its 16-hour line, the bypass FINDING confirmed and bounded (9 few-item hot sets in the tail of 408,067 accepted programs, 0 in 20 random, 1.002x at the largest; all 9 refused by the class v5 floor, 7 clean programs falsely refused among the 12 deepest, 3 mild residuals missed), the stand-in gap BOUND, distinguishers BOUND, the attempts census complete, partial the sweep at 408,067 of 10^6; adv-accept-2 92168536, about 9.0 core-hours and 0.3 pod-hours (the one pod), header grinding BOUND by card measurement (+0.09 percent on an A6000) and by tail (3e-7), one 0.1 percent repeat class for the rule's owners, none; adv-accept-3 7826d2b2, 3.3, exhaustion BOUND (P 1.0e-43), the last-resort path FINDING (correctness, unreachable; closed in class v5), steering BOUND (no property over 1.03x at 1 in 1e6 tries), the program id BOUND with the derivation-string FINDING (fixed on master and in the packs), determinism BOUND, the spec text proven sufficient by two read-backs, the era lever BOUND, partial the steering sweep at 975 of 10^5 full-rule seeds. Totals: about 30.4 box-hours of run across the nine lanes (lease waits excluded) plus about 9.8 single-core SAT hours; pod-hours 0.3 on one RunPod A6000, USD 0.33 in all, rented and destroyed by the fleet lane. The verdict: no lane broke the frozen object; the acceptance rule admits two residual classes of address concentration, both under 1.002x to a chip: the few-item hot sets, closed entire by the class v5 floor (9 of 9) at a 2.4 percent clean-rejection cost, and the diffuse era-stride excess the floor does not reach, routed to the next class with its lever; the weak-day FPGA tail reconciled and closed. Already changed by the pass: the derivation string in the shipped packs, spec 1.4.3 to 1.4.6 rewritten and proven text-sufficient, the chip model's partial-store and pebbling baselines corrected, the last-resort path flagged and closed in class v5. Still to come: adv-cache-2's s2c row and adv-accept's final count, appended when they land. CLASS-V5 GATED (the v5 lane): the full gate on 1d5e5d23 GREEN, 72 checks in 347 s (04:1x UK); class-v5 4a162aba on both mirrors at 04:12 UK with the page's F1 line stating the 04:06 reading (computing, not hung; census.csv only at its end; projected end about 10:00 UK); nothing of the lane's pending on a box or a watch. THE LANE (d) MERGE ON MASTER (the attack-pass lane, 399f8c4d at 03:16:35Z, 04:17 BST; attack-pass 4150f66d, full gate GREEN 45 checks on the branch): F9 PASS on 1c420786 (row and f9-grind.md section (d)), the F1 row as ruled (running, the 03:06Z reading, projected end about 09:00Z, 0 on its live panic path, the harness gap named), the in-house wording kept through a conflict with master's older copy, one founder-strings scrub the gate caught on the pass record (the attribution now "The founder's word"). The harness item: the progress line every 1,000 programs and the flushed partial census.csv (temp file and rename) committed on attack-v5-frozen at 18a9c04a, built on box 2, its known-failed test (a 4,000-program census killed by pid at the 2,000 line, 2,000 rows expected) running under lease pool class adv; the verdict and the push follow. THE SM-SPARSE QUESTION, THE THIRD RUN (run-ca4-pc1-ca4sparse-5090-20261008-b on ca4sparse4, 03:23:45 to 03:48:45Z, exit 0): the card-free check on the card's own exe listed the sparse variant (variants=2 names=base,sp43-w32, rewrite=applied), the race ran it, and NVRTC refused the rewritten kernel on every sparse row: "kernel_bound.cu(370): error: identifier "d" is undefined | igneum_hash_bound_unit(d, ou, baseNonc, mas, i, gid);" (the same for sp170, sp85, sp21, sp11), so the race installed base and every sparse row reads served=base variant_row=FAILED. The hash lane's reading to the research lane: the wrapper's call carries the kernel's parameter names cut by one character (d, ou, baseNonc, mas for ds, out, baseNonce, mask), which points at the rewrite's name capture against the PC's CRLF pack text (the Linux check reported a different byte count for the rewritten kernel): the first card test of the rewrite, the finding kept. The base rows a third repeat of the knee pass (v4 137.06 MH/s at 449.7 W unlocked, 134.23 at 301.4 W at 1,300; v3 136.79 at 329.8, 134.05 at 218.0), the card restored each time. The slot returns to the research lane on an exe whose card-free check compiles the rewritten text through nvrtc for sm_120 (on CRLF input). The queue: the microbench run-ca4-pc1-microbench-5090-20261007 since 03:52:14Z (20 probes of 60 s unlocked, then at the 1,300 lock; about 50 minutes), then the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. THE CLOSE'S MASTER COMMIT (the crypto lane, sent 04:55 BST for a 04:14 landing, the forty-minute gap its own): crypto-engage c099e818 (full gate GREEN, 71 checks) landed as the mirror's master 2882352c at 04:14:50 BST; the record cites the roll-up and every lane's reading at 00b8cd1b and the close (section 14) at 2882352c; further landings only for adv-accept's final count and adv-cache-2's s2c row. THE FOURTH --variant FIX (the research lane, 03:55Z on build-1 under lease): the cause was not the line endings: the rewrite's parameter capture wrote the substring length as end minus start where the last index needs plus one, so every argument lost its last character on any input; CRLF would have missed the anchors entirely; the rewrite now strips \r first (the same rewritten bytes from LF and CRLF, 22,266 on both) and the capture is right; the card-free check through NVRTC on LF and a CRLF copy, identical lines: variants=2 names=base,sp43-w32; rewrite=applied; call="igneum_hash_bound_unit(ds, out, baseNonce, mask, iw, gid)" params=6 args=6 names_match=1; nvrtc=libnvrtc.so.12 arch=sm_120 compiled=1 image_bytes=36256; the failed case the 03:23Z card line. Exe igneum-worker-cuda-ca4sparse5.exe sha256 a4550202b301faf22f5329c2ab4fa1c0aa6695dbdaf31c974f316dca2524d7d6, with the hash lane; the commit on the mirror after 3ac5d20a; the slot after the microbench and the packs. The three failures gave three repeats of the knee pass (the v4 premium 133.9 to 145.3 W unlocked, 90.5 W at 1,300 MHz) in the file's 20.3a. ADV-ACCEPT OFF BUILD-1 (04:5x BST, the coordinator's placement rule): adv-accept runs on to its 16-hour line (about 10:15 BST, 10.6 box-hours at 04:54, the reading saturated) in box 2's gaps under the mechanical yield, its build-1 shard ended at the frontier and its waiter withdrawn, so F1's census keeps build-1 (its 10:00 BST projection assumed load 21) until census.csv writes; adv-cache-2's four-minute s2c shard the one exception. Confirmed by lease status at 04:57 BST: build-1 holds F1 (release, 16 cores) and adv-cache-2's s2c (32 cores, its last shard) and nothing of adv-accept's; adv-accept's four holders and waiters on box 2, where the attack-pass lane's flush test waits at 1 free behind them (the same class, no yield case); the coordinator's placement rule: one adv-accept holder ends at its frontier for the flush test (a 4,000-program census, minutes), since adv-accept's reading is saturated and the harness fix gates the morning's F1 rerun class. Done at 04:59 BST: adv-accept's sweep-s05b ended at its frontier at 04:58:50 (46,460 rows kept) and the flush known-failed test took the 16 cores at 04:58:55; the shard re-queued behind it. ADV-CACHE-2 CLOSED (05:0x BST): its last shard s2c ran 04:56 to 04:59 on build-1 (PASS at 2^33 reads, control-level), so the line census totals 2^36 reads over 464 chain days with every statistic at the control's values; final box-hours 2.35 of run (0.08 a duplicate windows run by its build-1 drain, recorded), pod-hours 0; tip bfc3746c on build/adv-cache-2, igneum-pow identical to 017e7037; the biased-site class (AP-F8-6) and the window-layer pricing stand; section 14's row updated on crypto-engage, landing with adv-accept's final count. Eight of nine lanes at their end; adv-accept alone runs to its 16-hour line about 10:15 BST. THE CENSUS HARNESS'S PROGRESS LINE (the attack-pass lane, attack-v5-frozen 18a9c04a on the mirror): the attack-f1 census prints a progress line every 1,000 programs (count, elapsed, running failure count) and flushes a partial census.csv at the same cadence through a temp file and rename; the known-failed test on box 2 under lease pool class adv (binary 14180ef4...): a 4,000-program census killed by pid at the 2,000 line at 04:08:27Z (05:08 BST), census.csv holding exactly 2,000 rows, no tmp file, lease exit 143; PASS (the old harness's known fail zero rows); record f1-shadow.md section 12 on the mirror's attack-pass at c99f147f (riding the F1 record merge); a side reading: 1,000 programs per 286 s on 16 cores, about 4.6 core-s per program, confirming F1's build-1 projection of about 09:00Z (10:00 BST); the running 10^5 census stays on the old binary, every census after it on the new. F1 PASS ON CLASS V5 (the attack-pass lane; class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, 16 cores; census.csv written 04:20Z, 05:20 BST, after 20,774 s of census, 5 h 46 min, earlier than the 09:00Z projection as build-1 emptied): 100,000 of 100,000 programs through the string-seed draw with the (c''') floor; instructions saved min 0.000 percent, mean 0.623, max 4.688 (the worst seed attack-f1/95060: 6,912 to 6,588); chip-view ops saved mean 0.520, max 4.783; programs over 5 percent 0, over 10 percent 0; soundness: differential mismatches 0 of 100,000 (8 random states each), verifier mismatches 0 of 100,000; 0 panics; the histogram of saved in 0.5 percent bins from 0: 55,241, 20,597, 11,762, 9,851, 1,484, 656, 259, 133, 13, 4, 0, 0. Against the v4 10^5 (max 5.078, the AP-F1-1 letter miss): the v5 tip's worst program sits 0.39 points under the 5 percent letter and the top two bins are empty. F1 PASS on 1c420786 by the letter and at honest-compiler parity; the redundancy gate holds for the 0.3.24 move; AP-F1-1's v5 half FIXED-AND-PASSED at this count; record f1-shadow.md section 13 and the lane (d) row, merged to master next. The attack board on class v5 is complete: F4 PASS (8ca66afa), F8 PASS, F9 PASS, F1 PASS; the rest not re-run by rule. CLASS-V5'S F1 ROW (the v5 lane, class-v5 1095eaa8 on both mirrors at 05:24 UK): the page's attack row reads F8 PASS with the known residue, F4 PASS, F9 PASS, F1 PASS on the full 10^5, the rest not re-run by rule; the full gate running on 1095eaa8; nothing else of the lane's open tonight. THE CA4 PACKS ON THE 5090 (run-ca4-pc1-packs-5090-20261008-b, exit 0 at 04:22:54Z, 579 s; the 5090 alone through the installed worker, the lock and reset through the helper, every self-test PASS at both states): the int8 mma tile prototypes' inline PTX compiles under NVRTC 12.8 on sm_120 and matches the CPU reference (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1, mm1430 8e9b7066239d35d1), as do both per-load exports (404cad3b3399f9b3, ee5d7c71180e5ea7), sh256x27 (3d2e8245cc084d07) and the mx8-genesis control (7c28cfb06c5c65a9). Rows (MH/s / W / MH/W), unlocked then at the 1,300 lock: mx8-genesis 137.54/311.0/0.442 then 127.32/213.0/0.598; sh256x27 137.51/462.2/0.298 then 126.93/295.8/0.429; shl256x27 (unsound, an energy reading only) 158.62/472.8 then 145.65/299.4; shl256x27_v2 (unsound) 135.90/448.3 then 126.04/282.9; mm128 137.45/332.9/0.413 then 127.01/217.8/0.583; mm512 137.50/369.4/0.372 then 127.07/235.4/0.540; mm1430 137.45/457.7/0.300 then 126.87/284.5/0.446. Consequences: the rate is memory-bound on every sound pack at both states (within 0.5 percent of the control); the tile premium over mx8 is 21.9 / 58.4 / 146.7 W unlocked for 128 / 512 / 1,430 tiles (0.103 W per tile, linear) and 4.8 / 22.4 / 71.5 W at the lock (0.050 W per tile), so at 1,430 tiles the tile block costs what the ALU shadow costs (151.2 W unlocked, 82.8 at the lock) and the lock halves it the same way; the first per-load export's 15 percent higher rate is its duplicate reads landing in L2 (the unsound construction), the fixed one 1.2 percent under the control. The research lane has the rows for 20.3 and 20.4; the tile class's premium per tile is now a measured number on the 5090 and its Apple cost (35 to 78 percent of rate) the open side. The microbench -b since 04:23:23Z, then the SM-sparse rerun on ca4sparse5, the 5080 Ember tune, the 9070 XT tune pass, the hot table. THE CA4 PROTOTYPES' FIRST SENTENCE ON MEASURED ROWS (the research lane, counter-asic-4 on the mirror after 1428dd3c; sections 20.3 and 20.4): neither prototype beats class v4's premium; the tile block matches it at the same hash rate (mm1430, 11,440 int8 tiles per hash: 146.7 W over class v3 against the ALU shadow's 151.2 W unlocked, 71.5 against 82.8 W at the 1,300 lock, the rate memory-bound within 0.5 percent) and beats class v4's chip edge only at the pessimistic end (about 2.2x against 3.5x), not at k = 1 (2.2x either way), because the 5090's measured cost per int8 MAC (0.091 pJ unlocked, 0.048 at the lock) sits inside what a 5 nm MAC array costs anyone (a claimed test-chip figure), so a chip's k on tile work is at or above about 1 where on ALU work a fixed datapath reaches 0.3 to 0.5; the per-load placement dead as a construction (its energy rows 13 to 14 W under the whole block for the same instructions; the first export 15 percent faster from duplicate reads served by L2). Against the tile block as a class: the verifier (AVX2 0.047 us per tile per unit; mm1430 10.14 ms with the sibling loaded on the box's core, a 0.14 ms miss of the gate; scalar 13x worse; NEON unwritten), the Apple tier (35 percent of rate at 1,024 tiles, 78 at 4,096), the AMD layout unverified. No served number moves; the SM-sparse reading still owed (three failed runs, the fourth exe queued after the microbench); the op-mix re-weight held, the served 3.4x standing. The k column's basis (the research lane, counter-asic-4 after 781cb395): the 1,430-tile point is the one chip-model-v3 5.11's tensor-tile k column was priced at (15.2 set R about 1,430 from the 4090's 0.056 pJ per MAC to carry the ALU shadow's 0.654 microjoules; 11,440 tiles per hash), and the 5090 reads 0.091 pJ per MAC unlocked and 0.048 at the 1,300 lock there, so the column (2.1x at k = 1, 1.6x at k = 1.5) has its GPU-side cost measured at the premium it was priced for (1.067 microjoules unlocked, 0.564 at the lock, against the ALU shadow's 1.10 and 0.652); the Apple cost the open side; nothing served moves. F1'S RECORD ON MASTER (the attack-pass lane, merge 54b896f3 at 04:29:30Z, 05:30 BST; attack-pass 0610892b, full gate GREEN on the branch, pushed on try 2 after a ref race): the F1 row (PASS, AP-F1-1 FIXED-AND-PASSED on v5 at 10^5), f1-shadow.md sections 12 (the flush and its known-failed test) and 13 (the 10^5 record with the worst four programs at 4.688, the attempt histogram, the v4 comparison). Lane (d) complete: F4 PASS (8ca66afa), F8 PASS (61 of 64 at 1c420786), F9 PASS (10^5 seeds, 0 exhausted), F1 PASS (10^5 programs, 0 over the letter, 0 mismatches); both 0.3.24 gate lines PASS on the full 10^5. Box-hours for the lane (d) tail: build-1 F9 ten chunks of 4 cores at about 14,480 s each (about 161 core-hours), F1 16 cores for 20,907 s (93 core-hours), F4 12 cores for 379 s; box 2 F8 64 seeds (the earlier record) and the flush test 16 cores for 3,352 s (15 core-hours, most queued); nothing of the lane's on either box. THE V5 LANE'S NIGHT CLOSED (05:3x UK): the full gate on class-v5 1095eaa8 GREEN, 72 checks in 345 s; the freeze 1c420786 (0.3.24's pairing), the post-freeze line through 1095eaa8 (0.3.25's: AP-F4-1's agreed form, the verified last resort, the record), every proof green on the tip, the attack board on class v5 at F8 PASS with the known residue and F4, F9 and F1 PASS, the kit's fingerprint equal on CUDA, Metal, Apple OpenCL and the RX 9070 XT, the Intel row not measured; nothing of the lane's pending. THE SM-SPARSE READING EXISTS (run-ca4-pc1-ca4sparse-5090-20261008-c on the research lane's fifth exe, exit 0 at 05:12:48Z, 2,219 s; every variant served on the card, served=sp-w32 with sparse_blocks=N, the rewritten kernel compiled under NVRTC on sm_120 and bit-exact, every fingerprint equal to the Mac's; the 5090 alone, the lock and resets through the helper, the drift check equal to the start): a quarter of the SMs (sp43-w32, 43 of 170) holds 98.2 percent of the class v4 rate at the SAME draw (134.58 MH/s at 460.1 W against base 137.07 at 450.8) and 99.8 percent of the class v3 rate at 4 W less (136.55 at 309.8 against 136.77 at 313.9); the draw falls only when the rate falls (sp21-w32: v4 70.75 MH/s at 327.4 W, v3 132.82 at 303.4; sp11-w32: v4 37.34 at 250.9, v3 100.14 at 274.5), and watts minus idle per MH/s never drops below base (v4 2.75 W per MH/s base, 2.87 at sp43, 3.58 at sp21, 4.74 at sp11; v3 1.75, 1.73, 1.73, 2.00); the persistent shape on the full card (sp170-w32) within noise of base; at the 1,300 lock the sparse shapes collapse (v4 sp43 64.3 MH/s at 208 W, compute-bound). CONSEQUENCE: the class v4 premium is the shadow's ALU work itself, not SM-count overhead (150 W at sp43 against 137 W on the full card), so an SM-sparse miner kernel saves nothing and the candidate is dead by the research lane's own rule; the op-mix re-weight stays the open lever, and its served candidate ("2.9x with a core three times better") now has its SM-sparse read: the premium does not move with the SM count, so the re-weight's case rests on the op mix alone and goes to main with that reading. The microbench -c since 05:13:41Z with the pack argument; then the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. RANK 2 CLOSED IN THE CA4 FILE (the research lane, 20.3b, counter-asic-4 on the mirror after 6b21e887): the SM-side power is the work's, not the SM count's (the shadow's ops cost the same on 43 SMs as on 170; idling SMs saves nothing); the number kept: the class v4 premium at sp43 unlocked 150.3 W over v3 at a held rate, equal to the full-card premium, so the premium is the ops' energy whatever carries them; the premium-free floor rests on the operating point alone; the op-mix re-weight's hold is main's to lift or keep, the SM-sparse reading saying nothing against it; the microbench rows still owed. THE OP-MIX RE-WEIGHT: HOLD (the research lane's case for main, 06:2x BST; the SM-sparse row at counter-asic-4 954c4053, section 20.3b): the served sentence stands ("At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block"; the re-weight would move "3.4x" to about "2.9x", the shuffle-and-multiply-heavy shadow raising the chip's k floor from about 0.32 to 0.46). The basis: the re-weight touches only the pessimistic column, a model on both sides (the chip's k floor an estimate from wire and datapath figures, never measured; the GPU's energy per op by family unmeasured until the microbench rows land, the shfl, mul and arx probes being that measurement); the SM-sparse reading says nothing for or against it (the premium is the ops' energy, which both mixes pay); the night's measured finding on bounding k points to the int8 tile block (the same premium at the same rate with a k floor near 1 from the GPU's own tensor core, 0.048 to 0.091 pJ per MAC), of which an ALU re-weight is the weaker version at the same class-change cost (the 95 percent rule, the six gates, a new program stream, Apple paying shfl at 1.91x per op); a reader gains 0.5x on a modelled pessimistic bound and loses nothing measured from the hold; the 2.1x at k = 1 rests on four repeats of the knee pass (82.8 to 90.5 W at 1,300 MHz). The condition that re-opens it: the microbench reading the 5090's shfl and mul rows at or under the add's pJ per op together with a measured chip floor, and then it re-prices against the tile block, not the served line. Main's word lifts or keeps the hold; the coordinator's reading agrees with the hold. THE MICROBENCH ON THE 5090 (run-ca4-pc1-microbench-5090-20261008-c, exit 0 at 05:56:29Z, 2,484 s; the research lane's per-block micro-benchmark, 20 probes ran, 0 skipped or failed, at the unlocked clock and at the 1,300 lock, every probe's checksum equal at both states, the card back at the driver default). Picojoules per counted op as (watts minus the sleep row) over G ops per s, unlocked then at 1,300: the ARX integer path 11.3 then 6.2; int_mul 13.9 then 8.3; mulhi 39.6 then 21.0; prmt 22.3 then 11.5; lop3 24.1 then 13.0; shfl 55.8 then 29.4; fp32 fma 9.2 then 5.2; fp16x2 fma 5.1 then 2.6; int8 mma m8n8k16 4.1 then 2.2; int8 mma m16n8k32 1.36 then 0.83; fp16 mma 3.2 then 1.7; bf16 mma 2.9 then 1.5; fp8 e4m3 mma 1.5 then 0.8; the memory rows per read: L2 chase 2.4 nJ unlocked and 1.4 nJ locked, DRAM chase 10.9 nJ and 8.7 nJ, texture point 2.3 nJ, texture linear 0.19 nJ; the sleep floor 120 W unlocked against 75 W idle (the residency cost, flagged). CONSEQUENCES: (1) the op-mix re-weight's re-opening condition (the 5090's shfl and mul rows at or under the add's pJ per op) is NOT met and is now a measurement: shfl costs 4.9x the ARX op and mul 1.2x, mulhi 3.5x, so the GPU pays more for the heavier mix and the hold on the served 3.4x stands on measured rows, not a model; (2) the tensor-core int8 MAC costs eight times less per counted op than the ARX op the hash is built from (1.36 against 11.3 pJ), the direction a chip cannot beat by as much, which is the tile block's case restated in measured picojoules and the CA4 file's next row. The queue: run-ca3-pc1-ember-5080-20261007 (the installed app's Ember tune on the 5080, the app's own path, not elevated) since 05:57:18Z, about 30 minutes; then the 9070 XT tune pass and the hot-table ldcs rows. A CORRECTION FROM THE MICROBENCH'S TILE ROWS (the research lane, 07:0x BST; counter-asic-4 on the mirror after 954c4053: 15.1a, the corrected 20.3 and 20.4, the first sentence, the ranking): a mma.m8n8k16 tile is 1,024 multiply-adds per WARP, 32 per lane, so a hash does 32 MACs per tile, not 1,024; the lane's 15.2 and 20.3 and the 6 October 4090 figure chip-model-v3 5.11's tensor column was priced on were wrong by that factor. Corrected: the 5090's int8 MAC at the ALU shadow's premium costs 2.9 pJ unlocked and 1.5 pJ at the 1,300 lock (the packs job, 366,080 MACs per hash), the microbench's dependent u8 tile 4.1 and 2.2, the wide s8 m16n8k32 tile at 80 percent of peak 1.36 and 0.83; the 4090's "0.056 pJ per MAC" of new-pow 5.1 is 1.8 pJ. Against a 5 nm MAC array (0.04 to 0.4 pJ per INT8-class MAC, claimed) the chip's k on tile work is 0.03 to 0.3, BELOW the ALU shadow's 0.3 to 0.8: at the same premium the tile block leaves the chip 3.5x to 6.7x where the ALU shadow leaves it 2.1x to 3.5x. So the tensor shadow is the WORSE lever and rank 3 is dead; the 6 October verdict on scheme B stands for the right reason; the coordinator's 07:0x line to main calling the tensor side "the next class's one live direction" is withdrawn by this correction. Chip-model-v3 5.11's tensor column (its premise, a chip's MAC no cheaper than the GPU's, false by 4x to 30x on the public figures) and new-pow 5.1's per-MAC line are to be corrected (the coordinator's next commit); nothing served rests on either. The other rows, pJ per counted op unlocked then locked (the sleep floor 120 and 66 W subtracted; idle 75 and 60): int add-xor-rotate 11.3 / 6.2 (the shadow's 10.8 / 6.4 on the packs job: the two instruments agree); mul 13.9 / 8.3; mulhi 39.6 / 21; prmt 22.3 / 11.5; lop3 24.1 / 13.0; shuffle 55.8 / 29.4 (the card's dearest instruction, 5x the add: the re-weight's GPU side is against it, the hold measured); fp32 FMA 9.2 / 5.2; L2 hit 2.4 / 1.4 nJ per read against a chip's SRAM 0.2 to 0.5 (the hot-table lever dead on the GPU side; the ldcs rows kept as a record); the DRAM dependent read 10.9 / 8.7 nJ per read, the whole card's marginal against the chip memory's 2.0, section 2's floor seen per read. THE NIGHT'S CLOSING SENTENCE ON MEASURED ROWS: nothing on the 5090 reads k above 1; the ALU shadow at the operating point's knee is the floor, 2.1x at k = 1 for 82 to 90 W, measured four times; the two prototypes, the SM-sparse kernel, the hot table and the re-weight are all closed on measured rows. The CA4 file's commits (the research lane): 15.1a at 71fd465b (the microbench row, the residency cost 45 W at the stock clock before any instruction issues), 15.1b the commit after it (the re-weight's re-opening condition not met and measured; for 2.9x to be the honest pessimistic column a chip would have to pay 0.42 to 0.52 of the GPU's cost per shuffle, 22 to 28 pJ for a 32-lane crossbar move, above the wire figure and unmeasured; not a candidate on measured rows); the corrected 20.3, 20.4, the first sentence and the ranking at 71fd465b; the hot-table ldcs rows a record only. The lane closed for the night. THE TWO INTERNAL CORRECTIONS LANDED (the coordinator): chip-model-v3.md 5.11's k-column paragraph carries the dated correction (the tensor-tile column withdrawn; the shipped row unchanged) and docs/analysis/horizon/new-pow.md 5.1's per-MAC prose and the scheme B verdict carry the 32x correction with the reason (a tile is 1,024 multiply-adds per warp, 32 per lane), both citing counter-asic-4-research.md 15.1a at 71fd465b; new-pow's 5.1 table column and its 5.3 chip rows keep their original numbers under the note (the Horizon lane's file; a table rewrite is its own). THE 5080 EMBER TUNE (PC 1, app 0.3.20, 06:05Z, 07:05 UK; run-ca3-pc1-ember-5080-20261007): Tuned 60.3 MH/s at 123 W, 0.489 MH/W, clock_cap 2936, source=climb; read against the clock-lock grid, the app's power-limit climb lands at 0.489 MH/W where the 1,000 MHz lock gave 71.1 MH/s at 103.7 W (0.686), so the core-clock lock is worth +40 percent per watt on the 5080 over the stock climb (and 15 percent more rate): the case for the 0.3.24 core-clock knob shipping. The per-point curve rows were lost to a cast fault in the hash lane's curve line (job exit 1, 386 s; the app unaffected), fixed at 261d7c54. Live on PC 1: run-ca3-pc1-ember-9070-20261007 (the 9070 XT tune, 45-minute cap), then the hot-table ldcs rows. THE KNOB ON release-0.3.24 (the shipper, 07:1x BST): the core-clock knob 74585c91 cherry-picked onto release-0.3.24 at e181f497 with the efficient-point ceiling beside it (the plan-count test updated, b6e2845f; the app gate GREEN 294 + 35 + 8), the DMG re-cutting on it under the lock, the UI lane's drawing of the lock fields asked onto that tip, the measured Ember sentence in the 0.3.24 section with the job ids and the knee rule; the pin dfbd1e10 and the kit e6c088bb stand; the move on main's morning minute. THE 9070 XT EMBER TUNE (PC 1, app 0.3.20, 06:11Z, 07:11 UK): one row only, baseline 18.9 MH/s at 202 W, 0.093 MH/W, the chosen point "80%": the app has no knob on AMD in 0.3.20 (power_pct 0, clock_cap 0, limit 0.0 W), so the tune measures the stock point and stops; the 9070 XT cannot be made efficient by the app today, and at 0.093 MH/W it sits at a sixth of the 5090's locked 0.58 MH/W (the app's stored 5090 curve: 1,390 MHz, 118.6 MH/s at 204 W, 0.580) and a seventh of the 5080's locked 0.686; the AMD watts owed from the G1 ladder are on record from the app's reading, 202 W at 18.9 MH/s (the bench row's watts for the 9070 XT once the sampler question is closed). A morning item for the ledger and the app: an AMD core-clock knob (rocm-smi or ADL) is the only path to a 9070 XT efficiency figure. The job exited 1 on the hash lane's row count (fixed, 43f0918c); the app unaffected. The hot-table kit on PC 1 (fetch done 06:20Z); run-ca4-pc1-hot-ldcs-5090-20261008 publishing, the last PC 1 job on the list; rows when it closes. THE 9070 XT BENCH ROW ON MASTER (the site audit lane, ffb7d8ff at 07:35 BST, commit 47690be7, gate GREEN 72 checks): watts 202 ("202 stock"), mh_s 18.92 ("18.9 (18.8 to 19.2 on the G1 ladder)"), 0.093 MH/W, tuned "no lever: the app has no AMD knob today (an AMD core-clock knob through rocm-smi or ADL is the path, a morning item)", the class v4 cost unchanged (+2 percent of rate, 6 October), the note naming the app's own power reading at the stock point with the date and the status row, Hive values none; /miners rebuilt at 35 rows; no deploy; the audit lane closed for the night. The bench table's AMD watts are no longer owed. THE HOT-TABLE LDCS ROWS (the hash lane; the mirror's master at c09dfee4, 08:12 UK; bench-log entry "8 October 2026, the hot-table packs on the RTX 5090", 36 rows all PASS; run-ca4-pc1-hot-ldcs-5090-20261008b exit 0 in 1,372 s, clocks reset): ldcs equals base everywhere (a dead lever, no ldcs rows owed); the 1,300 MHz lock costs the hot packs 2 percent of rate against mx8's 7.5 while taking a third of the watts off every pack, so the hot family is latency-bound on the table; per watt at the lock hot64k8 reads 0.734 MH/W against the mx8 control's 0.602 (the control matches the v4 grid's 0.60, the two passes agreeing); the research lane has the rows with the resistance question (a cheaper GPU hash is a gain only if the saving sits in the memory path; the microbench's L2 row at 2.4 nJ against a chip's SRAM 0.2 to 0.5 answers it on the chip side). THE PC 1 LIST MAIN SET IS CLOSED: the 5080 full grid, the third 5090 pass, the SM-sparse reading, the two Ember tunes, the hot table, all on measured rows. Still open on the hash lane's side: PC 2's Arc B580 class v5 fingerprint on the shipper's clear (a Windows entry first), and the F8 tail p4/p8/p10/p34 as a Mac measurement under the lock script, held until main lifts the Mac rule for one job (a morning item). MAIN'S MORNING WORDS (09:3x BST on 8 October; the night's silence main's own, recorded as such): (1) the look: the design pass lands now through its gate (ca3-coord rebased onto master 715c79b2 as five site commits, tip 0d212a2a; the box sweep GREEN on the same content), the steward deploys master after it; (2) the floor sentence goes on evidence row 17 as well as /ledger in the exact wording (the audit lane's row); (3) CA4 parked with no live candidate, the record carrying the measured close; the only new work the AMD core-clock knob for the app, a 0.3.25 item on the update-return lane; (4) the F8 tail p4/p8/p10/p34 on the Mac: the Mac rule lifted for that one job, one at a time, a few minutes, the hash lane running it now; (5) the move: the shipper has route (A) with the minute 10:45 BST; the Arc B580 job has PC 2 clear and publishes now. THE BUILD-SERVER LANE'S HONEST STATE (09:31 BST): it ran nothing between 22:54 BST and 09:31 (its turn sat on a backgrounded gate chain; the overnight asks reached no tool call); the /miners captures it owed never ran (its export step failed at 22:52, "not a tar archive", a branch commit's git archive over ssh needing the ref fetched on the box side; the CI steward took the captures and the sweep instead); its last master-only deploy dde2dcd2 at 22:49 BST; it deploys master's tip on main's confirmed order after the design pass lands, and builds the 0.3.24 Windows pair and hive on the shipper's word. THE DEPLOY AND THE PAIRS (the build-server lane, 09:3x BST): a master-only deploy of 715c79b2 running from 09:32 with the checks after; master's tip deployed again when the design pass and the row-17 commit are on it, the served sha and minute to the record; the 0.3.24 seed, Windows and hive pairs built on the MORNING pin (the node lane's re-cut from the 10:45 minute) under lease class release, the hands pair the node lane's, the shipper keeping the move and the minute; the seed-class ship path proven on dfbd1e10 first so the morning pin's builds run clean. THE FOURTH CUT (the node lane, 08:33:18Z, both mirrors): 5b673577 on release-0.3.24-node = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else, the three heights staying; the read from build-1's restarted seed on 27632 at DAA 56,329 at 08:33:18Z (1.0 DAA/s overnight); the publish DAA at 09:45Z about 60,630, plus 7,200 is 67,830, the next boundary 68,400, landing about 11:54:29Z (12:54 BST); the floor holds for a publish up to DAA 61,200 (about 09:54:29Z, 10:54 BST); the gate set running since 08:33:20Z (build and consensus at gate priority, the five suites, both canary sets, the fast-time pair about 14 minutes from the artefact), the pin line due about 08:52Z (09:52 BST); the crossing read from build-1's seed after the move (restarted on the pin in the shipper's move); the TESTNET_PARAMS v5-at-0 re-cut after a clean crossing. THE ARC B580 READ (the hash lane, PC 2, 08:35:59Z, 09:36 UK): no fingerprint, match False against 82b19cbde8557ea5; the kit worker fails its self-test on the Arc before any batch ("vector lanes 96 bad of 96 ... device 729ebd46376e2851 expected e552166a03298f7f" on the v5 pack) and 96 of 96 on the v4 control too (device 11bdacb6ee4108c2 expected dfbc8db1c06dacd8), every cache and dataset FNV matching; so the Arc's bound-kernel evaluation is wrong on Intel OpenCL, not class v5; the kit is good on five of six platforms; under main's rule the Intel kit holds out of 0.3.24 with the crossing time 09:36 UK for its page row. The open question, put to the shipper (PC 2 its now): whether the installed 0.3.21 worker's own self-test passes on the Arc with the devnet pack, which decides regression (the kit worker) against never-worked (every Arc rate row on record would then be a FAIL row and the bench table's Intel row a held row). The F8 tail job on the Mac started under the lock script, one seed at a time. THE DESIGN PASS ON MASTER (the coordinator, on main's word; merge 3a4ba893 at 09:39 BST): ca3-coord rebased onto 715c79b2 as five site commits (tip 0d212a2a: the design pass e2674675, the phone grid 592488a4, the six-column row 7c44354f, the lead cell's wrap c11baf30, the width rule scoped to desktop 0d212a2a), site/build.mjs and site/miners.html only, the page rebuilt at each commit so it carries the 5080 and 9070 XT rows under the design; the Mac's gate GREEN (the sweep skipped there), the box sweep GREEN on the same content at 5158276c with the four dark captures under /srv/artefacts/captures/ca3-coord-5158276c/; the build-server lane deploys master's tip after the audit lane's row 17 and Arc-note commit. THE MOVE'S READINGS (the shipper, 09:4x BST): the pin 5b673577's node-lane pair on build-1 (igneumd a3b1a2c9, igneum-miner cfa9f5ca, igneum-pow src 8 paths), its tarball served at fleet/5b673577-node-lane.tgz (c5b85b09, 27,495,480 B); the gate script carries cfa9f5ca and dry-ran at 32 of 35 reachable (dn3-pool-a destroyed by the fleet's waste pass, dn3-relay and p2-4090-1b behind dead proxies); the move file m5b67-1 written to take the pin line's digest and placed at at_epoch 0 the moment that line reads green (about 09:52 BST), the gate line applied in the same minute, the minute the last FETCHED plus ten (the founder's word: no waiting on the clock; 10:45 the ceiling, 10:54 the floor's); the Mac entry re-cut on the knob display (knob-24 2c4dc617 merged, app gate 294 + 35 + 8, UI 88) and published with the hive at the minute; the installed worker's self-test on the Arc with the Intel lane; the eight boxes on bc5945fe with miners off read by the fleet lane and taking the move with the rest. (The fleet lane is answering again this morning.) THE PIN LINE ON 5b673577 (the node lane; every gate green at 08:39:15Z, 09:39 BST): 5b673577 on release-0.3.24-node (both mirrors) = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else; pairing igneum-pow 1c420786; build 08:34Z rc 0 at gate priority (igneumd a3b1a2c96a9767ee..., igneum-miner cfa9f5ca..., /srv/artefacts/0324-5b673577/node-lane); core 175, exec 47, miner 28, p2p-flows 38, pow 19, consensus 134 at gate priority; the Devnet 3 canary set (08:34:58Z to 08:36:38Z): digest cc9026909eddbadb46912513e9b748dffd8e5c3583cd976857a8afdab2d772f9 on igneum-devnet-3 from ba75bf6f, object version 6 stamped, the override file refused, shutdown 573 ms, two empty nodes handshaking on cc902690, the shared-devnet dialler rejected, a 2720d8d2 node refused both ways; the testnet canary b2e856ed unchanged. The floor from the seed's read: the publish DAA at 09:45Z about 60,630, the floor about 11:54:29Z (12:54 BST), holding for a publish up to DAA 61,200 (about 10:54 BST); the fast-time pair's SUMMARY due about 09:55 BST, inside 10:35; no slide to 72,000 needed. A correction: node1-dn3's 28670 no longer answers (its process gone), so the DAA reader is build-1's seed on 27632, restarted 02:00:09Z on the shipper's word and in step with the observer on 28650. dfbd1e10 void as a pin. THE F8 TAIL ON THE MAC, p4 (the hash lane, under the lock script, one seed at a time; the Mac rule lifted by main for the one job): p4 reads 1.2169x over the window model (the gate's 1.2167x reproduced), hot-set clear at every f, the attribution on one site: site 1 (instr 8, source r2, window 2^22 items, offset 1, the last base writer mad at instr 4) carries 1.448 percent of the hot reads against 0.107 flat, index entropy 13.74 of 14 bits, the largest 256-item bucket 4.5x its window expectation, every other site at its flat share; the hottest item 0x4000e7 at 355 reads with no predicted source (no saturation, no lossy writer), so the residue is a window-2 index with a quarter-bit short, not a lossy source; p8, p10 and p34 running (about 90 s each), the four rows and the record line (the bench log or AP-F8-1's tail paragraph) at the close. STANDING RULE FROM THE FOUNDER (09:5x BST on 8 October, after the night: "this cannot happen again"), three parts: (1) every ask any lane sends main carries a default action and a deadline; silence at the deadline means the default, never a stand-down; passed to every lane the coordinator runs; (2) the coordinator mirrors every deadline the shipper holds today (the pin, the apply, the move minute, the publish, the Windows chain, each floor ceiling): if the shipper has not acted within five minutes of its own clock the coordinator sends it the word and tells main; if it is silent for 25 minutes the coordinator takes its next action itself with the shipper's runbook and tells main; (3) a 20-minute heartbeat wakes main regardless of notifications. The night's cost the rule prices: three floors lost (28,800, 32,400, 39,600) and the Mac entry stood down for want of one word while every gate was green; two lanes dark for ten hours. THE MOVE FILE PLACED (the shipper, 09:42:14 BST): m5b67-1 (5b673577, digest cc9026909eddbadb, at_epoch 0, the node-lane tarball c5b85b09) placed and served, its signature verified against the fleet key; the gate line (cfa9f5ca into every reachable box's pack list) applying from 09:42; the minute the last FETCHED plus ten once the fast-time SUMMARY reads PASS (about 09:55); the Intel lane a0aa97b17380bd614 holds the Arc self-test question with the audit lane on its recipients. THE NODE LANE'S OPEN ITEMS UNDER THE RULE (09:4x BST): the crossing read at DAA 68,400 from build-1's seed by 13:10 BST (else the observer on 28650 or the reader on 28690); the TESTNET_PARAMS v5-at-0 re-cut lands through the full gate set at 13:30 BST unless main says otherwise by 13:15 (a red crossing read means no re-cut); any later floor losing its margin is cut from the next named minute by dn3-floor-cut.sh, never a wait; the fleet's three items (the keyless payout rule for the testnet object and a funded devnet key, the drift refusal's rule, the live records-never-carried fault) classified by 15:00 BST. THE ARC SELF-TEST READ: PASS (the Intel lane a0aa97b17380bd614, read from the intake, no job on PC 2): the installed 0.3.21 igneum-worker-opencl.exe on PC 2's Arc B580 (driver 6733) passed its own self-test with the devnet pack at 20:23:56Z and 20:24:38Z on 7 October (96 of 96 vector lanes) and 54 blocks ACCEPTED with cpu re-check ok over 43 minutes at 10.58 MH/s wall (accepted 54, rejected 0 at 21:06:33Z); the shipped 0.3.20 worker read 96 of 96 on every pack on both PCs earlier that day. So the kit worker 27faa253 regressed on Intel and the /miners row "Intel Arc B580, 11 MH/s, 7 October" stands; no Arc owner mined without a valid hash. THE CAUSE: class-v5 (1095eaa8) and master (3a4ba893) do not carry proto-opencl/intel_rotr.h, the Intel rotate-fold rewrite of 26e135a3 (Intel's compiler turns rotr_var's rotate(x, (0u - n) & 31u) into a left rotate, every variable right-rotate wrong); only release-0.3.23 (710e1fea) and release-0.3.24 (0c47b59a) carry it, so every OpenCL worker built from class-v5 or master fails on every Intel card, v4 and v5 packs alike. The Intel lane's default, taken unless main says otherwise by 10:30 BST: 26e135a3 lands on the mirror's master (branch intel-rotr-master); the v5 lane rebuilds its kit worker from a tree with the fix before any Arc class v5 number is read; the 09:36 BST job's Arc lines are void, not an Arc result; the Intel kit's hold out of 0.3.24 stands until the rebuilt kit's fingerprint reads on the Arc. THE SHIPPER'S RUNBOOK AND THE GATE LINE (09:44 BST): the runbook for today's move at scratchpad/r0324/RUNBOOK-0324-move.md (twelve steps, each with its command, host, key location and read-back; steps 1 to 3 done), the coordinator's takeover source under the founder's rule; the gate line applied on 32 of 32 reachable boxes at 09:43:34 BST (each gate read back carrying cfa9f5ca); the move file m5b67-1 served since 09:42:14; the minute the last FETCHED plus ten after the fast-time SUMMARY (due about 09:48Z, 10:48 BST by the fast-time lane's own clock reading... the SUMMARY due about 09:5x BST), inside 10:54. THE RULE PASSED TO EVERY LANE (09:4x BST): the shipper (its runbook written), the node lane (its three defaults armed: the crossing read by 13:10, the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15, any later floor cut from the next named minute), the fast-time lane, the build-server lane (the deploy at 10:00, the three pairs with their minutes), the hash lane, the audit lane, the v5 lane (the kit rebuilt on the Intel fix), the Intel lane (its default at 10:30), the update-return lane (the AMD knob's branch by 12:00), the fleet lane (the FETCHED count by 10:05), the crypto lane (adv-accept's count at 10:15, section 14's last landing by 10:45, both armed on hard clocks), the attack-pass lane (the F8 tail's attribution by 11:00), the research lane (parked, its file at fb61ed4b) and the CI steward (the cut-over ask with a default on the first unsuspended read). THE AMD KNOB OPENED (the update-return lane, 0.3.25; branch amd-clock-25 off release-0.3.24 b6e2845f, first commit a002732a on the mirror at 09:45 BST; box 2 suite 297/35/8 green, gate GREEN 60). Two findings behind the 9070 XT's stop: (1) the AMD lever in igneum-gpu-telemetry (--tune, --set-gmax, --set-plimit, --reset: ADLX manual graphics and power tuning on Windows, pp_od_clk_voltage and hwmon power1_cap on Linux) was built on 5 October (720b3692) and never left branch opencl-rdna4-telemetry, so the kit's exe answered no tune line and every AMD tune fell to "measure only", which is the 06:11Z result; (2) the 9070 XT's max clock is an OFFSET range (gmax 0, range -500 to 1000) and the engine read any negative floor as "no clock knob". The commit takes the tool whole into proto-opencl/gpu-telemetry.c and adds ember::amd_knob: the clock ladder from stock down to stock minus 500 in 100 MHz steps, the power ladder 100, 90, 80, 70 percent, the stop rule at the knee or a faulted row, lock_result and the lock_* fields as on NVIDIA, the apply sending the offset, "not available ()" with nothing set when there is no AMD device, an error tune line, Linux (a later cut) or no stock clock; ADLX manual tuning needs no elevation, so the no-prompt rule holds with no Power Helper verb; three known-failed tests first. The first measured grid needs the kit's igneum-gpu-telemetry.exe rebuilt from this source (MSVC, the ADLX SDK beside the tree) and a 0.3.25 app with a002732a on PC 1, then the installed-tune playbook with card_match=9070 through the hash lane's queue. The lane's default: if the shipper names no 0.3.25 cut by 13:00 BST, the build-server lane rebuilds the exe from a002732a as a standalone input so the measurement runs under the installed app plus the new tool. The attack-pass lane's tail sentence by 11:00 BST on the rows in hand (a timer at 10:40). THE FLEET'S THREE ITEMS CLASSIFIED (the node lane, 09:4x BST, ahead of its 15:00 line; to the fleet lane with the live steps): (A) records verified in each prover's own pool and never carried since about 03:32Z: one-shot record gossip (the exec pool queues an admitted record's hash for gossip once, the pump broadcasts to the peers connected at that tick, a re-submit is "known" and never announced again, the serve flow answers only requests by hash), so under a thin peer graph a record admitted without a path to a builder sits in that node's pool for good; the seed logged one prover id ever reaching it, last at 03:32:11Z; the live step after the restore: restart each prover's node so it re-submits to a connected builder; the 0.3.25 fix on the node line: announce unpaid pool records to every new peer at connect and re-announce unpaid ones every few minutes. (B) p1-5090's "refused on the drift flag (offset -5)": the fleet's own standing.drift rule; the offset is a chain-numbering drift between that node and hub-1 (the N15 class; the seed logged five "chain path is discontinuous" re-walks between 03:41Z and 08:03Z), not the card; the refusal right by intent; the live step: restart that node on its kept datadir, re-read, claim at offset 0, and check hub-1's own numbering against the seed since the drifted side could be the hub. (C) 0.3.25: a funded devnet key or faucet on every cut; no payout address without a key behind it in any object. THE F8 TAIL ATTRIBUTED (the hash lane on the Mac, 08:39:46Z to 08:46:24Z, 09:40 to 09:46 UK, one seed at a time under the measure lock by main's lift of the Mac rule; attack-f8 census at 2^24 nonces, the window-model control, by-site attribution; tree b38b4af6 with igneum-pow frozen at 017e7037): the gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x; the hot-set verdict clear on the windowed control for all four). Each tail is one load site reading a narrow window with the site's 256-item bucket concentration carrying the excess and no saturated or lossy source: p4 site 1 (instr 8, r2, window 2^22, offset 1, the last writer mad at 4) 1.448 percent of its reads into the top 0.1 percent against 0.107 flat, index entropy 13.74 of 14 bits, the largest bucket 4.5x window expectation, the hottest item 0x4000e7 at 355 reads with no predicted source; p8 site 14 (instr 51, r7, window 2^22, offset 2, xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, plus site 6 (instr 33, r3, window 2^23, mad at 30) 0.834 percent, bucket 3.5x, the hottest 0x837de4 at 420 reads, source none; p10 site 8 (instr 28, r0, window 2^22, offset 1, mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x, the hottest 0x4004da at 362 reads, source none; p34 site 1 (instr 13, r3, window 2^23, offset 1, sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x, the hottest 0x800010 at 541 reads, the predicted source "one-one-bit, last writer sub at 5", saturated source 0.0001 percent; every other site in all four at its flat share. THE MECHANISM: a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short on a 2^22 window; p34 0.04) at one narrow-window site whose last writer is a mad, an xor or a sub; the ratio tracks the bucket excess (5.6x gives 1.50x, 3.1x to 4.5x give 1.22x to 1.38x); sub-version 3's (c'') distinct-index ratio passes these at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would catch all four: a per-site largest-256-item-bucket bound (about 2x window expectation at the 2^20 units (c'') already runs), a generator change, so not for the frozen 017e7037 nor for the frozen class v5; a morning item for main with its clean-seed cost unmeasured; the record line on the AP-F8-1 entry (the tail attributed, nothing changed in the stream). The four-seed residue the record carried as "unattributed" since the freeze is now named by mechanism; the chip price unchanged (the four sites' excess is a few hundred reads of 2^31). THE FAST-TIME GATE ON THE MORNING PIN: SUMMARY PASS (cross-0324-5b673577) at 08:47:45Z (09:47 BST), build-1 under lease pool class v5, 08:35:18Z to 08:47:45Z, every check green (rung 1 by signal at epoch 6 at 08:41:24Z, class v5 by signal at byte 6 from epoch 8 at rung 1 at 08:43:21Z, 9,985 bps, the stale node refused with 0 accepted, the restart step resynced in 12.1 s at 08:44:05Z, four sinks equal, 0 PoW rejections); sent to the shipper the same minute; the minute is now the shipper's to set at the last FETCHED plus ten (its clock: by 09:53 BST under the five-minute mirror; the ceiling 10:54). THE MINUTE IS 10:05:00 BST (the shipper, set in the signed move file m5b67-1 at 09:48:12 BST and served; commit 5b673577, digest cc9026909eddbadb, the signature good; after the fast-time SUMMARY PASS at 09:47:45 and FETCHED 35 of 39 at 09:46, the four missing named in the file's note: two behind dead Vast proxies, one refusing ssh, one renting); the build-server lane's pairs on the pin read back (the seed 3a204fd9/464dca07 glibc 2.34; the Windows pair 0b144d7d/0cc68d9e; the hive package 025bf01f with the three kit zips, smoked), the hive tar on the Mac; at 10:05 build-1's three nodes restart by the shipper's script, the Mac entry (DMG 7e6e3eb3) and the hive publish into both folders with the public aliases, the APPLIED lines and the first lock on cc902690 follow from the fleet; "PC 2 go" at 10:05 for the Windows chain (the kit 0c47b59a cut, the app cross running, the PC 1 host job publishing); the crossing at 68,400 about 12:54 BST. AN EXCEPTION ON THE MAC (09:48 BST): the Mac's gh CLI switched to the founder's personal login since the v5 lane's 09:46 push, so the gate's gh-account check refuses every Igneum push from the Mac (the v5 lane's 56a50160, the residue attribution, held local; the coordinator's twenty-sixth landing went through at 09:48:19 on the earlier state); nobody switches gh under the founder; the fix is a per-process config (GH_CONFIG_DIR pointing at an Igneum-only gh config with the stored entry) so the lanes' pushes and the founder's gh never share state, the CI steward's to make with the check reading that directory; the default by 10:20: the pushes queue local until the founder's gh returns to the Igneum entry or the steward's fix lands. ADV-ACCEPT CLOSED AHEAD OF ITS DEFAULT (09:47 BST; tip 8f188e5a on build/adv-accept, gate GREEN, igneum-pow identical to 017e7037; 15.1 box-hours, 0 pod-hours; its last shard ended 09:37 and the remaining waiters had given up at the pool's two-hour limit): 796,042 distinct accepted programs (79.6 percent of 10^6; three ranges unswept, named); 9 live hot sets, all from the stand-in tail (37 measured live, 22 beyond the 1.2x gate), 0 of 20 random, at most 1.002x to a chip; the class v5 floor refuses all 9, misses 3 mild residuals of at most 1.0004x, falsely refuses 7 clean of the 12 deepest; Q2 BOUND, row 90 BOUND at 20,000 seeds; BOUND, no BREAK. Section 14 updated (adv-accept's row and partial, adv-cache-2's close, the totals: about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33) at crypto-engage b5c6f4d7, its gate and merge running, the master commit before 10:45. All nine lanes at their end. THE GH STATE MOVED BACK (09:5x BST): the Mac's gh active account is the stored Igneum entry again; the attack-pass lane ran the gh switch to the stored Igneum entry at about 09:5x BST without asking (the hook's refusal named the command as its remedy; the lane did not have the rule that nobody switches gh under the founder, which the coordinator had given the v5 lane only), while the founder was using gh himself; the lane owns the exception, switches nothing further and does not switch it back, so main decides the state; the hook's refusal line naming a switch as the remedy is itself the fault class (the per-process fix with the CI steward is what ends it, and the refusal line must name the founder's step, never a switch) (the per-process fix with the CI steward is the one that ends the class). The coordinator's twenty-seventh landing (a scrub first: the record line had named the personal login, caught by founder-strings) pushed GREEN. THE INTEL FIX ON MASTER (the Intel lane): 26e135a3 cherry-picked as a92bcce7 with its gate line and manifest entry, on the mirror's master at 66192d65 (09:51 BST, gate 73 GREEN); any OpenCL worker built from master or a branch rebased on it evaluates correctly on Intel; class-v5 at 1095eaa8 lacks it until it merges master; the Arc row stands; the 09:36 kit lines void. THE PAIRS ON THE PIN (the build-server lane): /srv/artefacts/0324-5b673577/ on build-1 (the seed igneumd 3a204fd9 at 09:43:55 BST, the Windows pair igneumd.exe 0b144d7d and igneum-miner.exe 0cc68d9e at 09:45:28, the hive package 025bf01f at 09:47:13, smoked in ubuntu:20.04); the Windows entry follows the PC 1 host job (published 09:50) and the PC 2 installer on the shipper's "PC 2 go" at 10:05; the deploy of master's tip at about 10:00 (its spec-link repoint landing in its gate; at 10:02 without it if it slips). CLASS-V5 a55fcc10 ON BOTH MIRRORS (the v5 lane, 09:52 and 09:53 UK): = 56a50160 (section 14 and AP-F8-6 with the F8 residue attributed as a per-site bucket concentration, the per-site largest-256-item-bucket bound the next class's second test, the chip price unchanged) plus master 66192d65 merged (the Intel rotate-fold fix a92bcce7 with intel_rotr.h and host.c's igneum_intel_rotr_patch; host.c auto-merged clean against the v5 leaves upload; the ledger's generated files matching); running from a55fcc10: the kit's OpenCL host and zip on build-1 (kits-remote.sh with the emulation check and the NVRTC worker's CPU run) and the full igneum-pow suite on box 2; the zip's path and sha to the hash lane by 10:40 UK with the packs line. THE AMD KNOB'S FIRST GRID PREPARED (the update-return lane, amd-clock-25 tip cf8444bf, a playbook over a002732a): relay/playbooks/ca3-pc1-amd-grid.ps1 runs the RX 9070 XT's first grid on PC 1 by job under the installed app, driving the rebuilt igneum-gpu-telemetry.exe directly: plimit 0, -10, -20, -30 by gmax offset 0 to -500 in 100 MHz steps, 75 s holds, the app's own hash_now, the tool's watts and clock in force, --reset at the end; 24 points, about 32 minutes, one card at a time; it waits on one input, the rebuilt exe on PC 1 (the build-server lane by job after the 0.3.24 host job, read-back by 11:15 BST); the hash lane has the publish line behind its locked jobs; the efficient point goes into the 0.3.25 tuner's ceiling table. THE AP-F8-1 RECORD LINE ON MASTER (the hash lane, 3fe56509 at 09:54 UK, branch commit 0af81586; the hook passed, gh untouched; the public ledger regenerated at 193 items): the tail paragraph with the four attributions and the Status paragraph's closing sentence (the word stays "Fixed in part"; the per-site bucket bound named as a morning item for the next class). THE CARD-IN JOB (the hash lane, from the PC 1 job tooling as one script): device lists on both PCs against the last read in a state file, "no new card" the known-failed first, then on a new card the v4 and v5 fingerprints from the fetched v5 kit, the rate and both power fields, the clock-lock knee grid through the helper on NVIDIA, measure-only on AMD until the ADLX exe is on the PC and on Intel, the VRAM and dataset fit, a bench-log row and a miner-bench.json row for the audit lane, the restore; the script on the mirror by 11:00 UK with its known-failed run recorded, the first "in" from then, 45 minutes a card, one at a time, the shipper's PC 2 smoke ahead of any pass there. Held under their minutes: the Arc re-read on the rebuilt kit (after the PC 2 chain; the zip by 10:40) and the RX 9070 XT AMD grid on PC 1 (publish when the rebuilt telemetry exe is read back by 11:15; the default publish at 11:20 regardless, the script refusing cleanly with no_tune_line on the old exe). THE IN-HOUSE PASS'S LAST LANDING (the crypto lane, 09:55 BST): crypto-engage b5c6f4d7 (full gate GREEN, 71 checks) landed as the mirror's master 9649f51e at 09:54:42 BST; the record cites three master commits: 00b8cd1b (the rule set, the board, the roll-up and every lane's 00:00 reading), 2882352c (the close), 9649f51e (the final section 14: the totals about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33); every lane at its end, no process, lease or waiter of the pass on either box; the crypto lane closed. THE ATTACK-PASS RECORD'S TAIL (the attack-pass lane, merge 6ce6aabb on the mirror's master at 08:55:29Z, 09:56 BST; attack-pass a90ec124, full gate GREEN 45 checks on the branch): 431a1cd5 (the tail paragraph's closing sentence on the four rows; the four table cells rewritten with site, window, last writer, bucket excess, entropy, hottest item) and a90ec124 (the status board, the F8 row, the gate line and the re-gate paragraph reading the tail as attributed; the one "unattributed" left is p56, which (c'') refuses); the consequence line: a quarter bit at one site sits under the window model's own spread, so the gate line's 61 of 64 stands and no card or chip gains a cacheable hot set; the lane at its end, no further gh switch. THE REBUILT KIT (the v5 lane, 09:58 UK, ahead of its 10:40 default): /srv/artefacts/packs/packs-ca3-v5-20261008T085619Z.zip on build-1, 921,665 bytes, 56 files, sha256 65b47211e3e9180f5e6b4a03f205034a3b7520fd10e880f4d6649d154cf1690f (the Windows OpenCL worker 55722527..., built 09:57 UK from the Intel-fix tree); the emulation check and the NVRTC worker's CPU run PASS on v5-dn3-epoch0; the suite on box 2 green (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs, ids and 82b19cbde8557ea5 byte-identical, recheck 2, scratch 7, spec_readback 3); commits a55fcc10, c0d398a1 (the Arc job keeps the host's whole stdout as RESULT lines), 8f481459 (a C99 declaration-order fix the kit build caught) on both mirrors; the Arc re-read with the hash lane through the shipper's PC 2 queue. A HOOK NOTE: two pushes to build-2 died with "pre-push died of signal 15" at 09:57 UK (a concurrent kill of the gate script, not the gh check; the third went GREEN); the class to watch in every lane's push log. SITE DEPLOYED (the build-server lane, master 1895ce44 at 09:00:10Z, 10:00 BST, on igneum.network and igneum.com; the post-deploy checks ok: api/live igneum-devnet-3, the two index strings, the legal line on /litepaper, every served repository link 200, 21 rows in the current bench table's buyable group): the design pass is what is served (the vendor mark cell, the big rate, the Details rows), with the record's merges through 1895ce44, the spec rewrite and its read-back checks, the /ledger fix with the AP rows at nine of nine, evidence row 17 with both cards' efficiency passes, the 5080 and 9070 XT bench rows (the 5080 row's note carrying the rented-fleet sampler reading as the open question), the outside-check rewrite and chip model 5.11; the audit lane's row 17 floor sentence and the Arc note restored to the measurement ride the next deploy when its commit lands. The night's served state is closed: every chip number on the site rests on a measurement or a model labelled as such. ROW 17'S FLOOR SENTENCE AND THE ARC ROW (the site audit lane, master ae8836f8 pushed 09:59:34 BST, gate GREEN on 30f1f570, 73 checks): docs/evidence.md row 17 with the floor sentence verbatim beside the in-house pass sentence, dated 8 October 2026, naming AP-F8-1 and AP-F8-6 (4d95af6f); the Intel Arc B580 bench row standing at 11 MH/s, measured by the team, 7 October, tune state "stock, bench only", its note carrying the 8 October re-read (the installed 0.3.21 worker's self-test 96 of 96, 54 re-checked blocks at 10.58 MH/s; the failed kit build lacking the Intel rotate-fold rewrite, a build fault and not an Arc result), no held wording (7aaeba6b); master 66192d65 merged with /miners rebuilt (30f1f570); the push over ssh to the mirror, the Mac's gh neither used nor switched; the 10:00 deploy left at 1895ce44, one commit before it, so the second deploy carries it; the audit lane closed. THE 0.3.25 NODE BUILD'S SHAPE (the node lane, 10:0x BST; release-0.3.25-node opened from the pin 5b673577 in a second worktree, release-0.3.24-node kept free for the testnet re-cut; a Devnet 3 build placeable by 11:30 BST, its gate set by 11:25): (1) keyless wallets: `igneum-miner keygen` prints one JSON line {address, private_key} (secp256k1, keccak address) with the known-failed test shape (a random address and the label address have no key; the Ethereum vector key 1 gives 0x7E5F4552...; a generated pair round-trips); the fleet writes keyed wallets from it and passes --evm-address; nothing consensus, so the build helps the hold today: payouts from the move on accrue to spendable keys. (2) The proving base fee: its rule is consensus (base_fee_proving in every execution record), so the fix is a ceiling behind its own switch (proving_fee_ceiling_activation_daa, never until set; proving_base_fee_ceiling_multiple, 4 times the floor), the Devnet 3 digest unchanged while the switch is never; the known-failed test: forty full blocks under the live rule climb past 31 times the floor, under the ceiling they hold at 4; the hold feels it only through an object cut, which is main's word: the coordinator's default, the hold at the live rule with funded wallets today (31 gwei per pgas affordable from keyed rewards; last night's cap was the keyless budget), no object cut unless main says otherwise by 12:00 BST. (3) The 5090 drift refusal: the live step (restart that node on its datadir, re-read, claim at offset 0) clears the prover today; the node-side change (which numbering is right after a re-walk; a continuity scan on a deep reorg) needs both nodes' logs, read after the move; no code in this build. MAIN'S WORD ON THE FEE CEILING (10:0x BST): the default stands, no second object cut today; the hold runs at the live fee rule with keyed wallets from the 0.3.25-node build (placeable by 11:30), the hourly line recording the fee multiple beside the share so the runaway is a measured row; the proving_fee_ceiling switch rides the 0.3.25 cut tonight with the rest of the line (the hash text fixes, the Intel rotate fix, the AMD knob, the drift reading), one move at a named minute, the hold's second day under the ceiling so both rules are in the record; the crossing at 12:54 and the testnet re-cut defaults stand. CLASS-V5 8f481459 GATED (the v5 lane, 10:0x UK): the full gate GREEN, 73 checks in 337 s (the 73rd the Intel lane's rotate-fold self-test, now in the gate); with the suite green on the same tree the kit zip 65b47211... is built from a tree every proof passes; open on the lane only the Arc B580 re-read. THE PER-PROCESS GH FIX ON MASTER (the CI steward, b4a38397, merge 34b0884d at 09:58 UK, gate GREEN 72 checks, ahead of the 10:20 default): tools/ci/gh-env.sh sets GH_CONFIG_DIR=~/.config/gh-igneum for the gate, the hook, merge-to-master.sh and ci-state.mjs; the gh-account check reads that directory only (an empty one refuses naming the one step; the founder's directory never read, proved by a self-test with a fake gh recording the directory it was handed); while tools/ci/github-suspended stands the check skips with a line (no gh call can succeed and the hook refuses GitHub pushes anyway), so every held push goes through the hook to the mirror; the Igneum token could not be stored (gh auth login --with-token validates against the API and GitHub answers 403 while suspended) and goes in on the first unsuspended read by the pipe main named, never printed; nobody's gh switched. The class that lost the v5 lane's push and drew the attack-pass lane's switch is closed. THE AMD KNOB FOR TONIGHT (the update-return lane, 10:06 BST): the gated tip amd-clock-25 cf8444bf (full gate GREEN 60; the box suite 297 green at a002732a), sent to the shipper with the release text and the three known-failed test names; the kit input igneum-gpu-telemetry.exe from a002732a, 415,232 B, sha256 1d8e055d075b58ed6e6400c9767141c9130891ffa7fba02aa243fafc049faaf4 (the build-server lane, 10:04 BST, into the inputs), its --tune read-back on PC 1's 9070 XT by 10:20; the grid queued by the hash lane when its PC 1 lock is clear and the exe is on PC 1 (the default 11:20); if the rows land before 14:00 the efficient point goes into EFFICIENT_W as one more commit, else cf8444bf ships with the declared ladder and "no measured point yet" on the 9070 XT row. THE 0.3.24 MOVE FIRED AT 10:05:00 BST (the shipper's readings; the coordinator's own read on build-1 at 10:10 confirming four igneumd processes on the pin's artefact): m5b67-1, FETCHED 36 of 39 at 10:00 (dn3-agg48 renting, p2-3090-1 refusing ssh, p2-4090-1b behind a dead proxy); build-1's three on the pin: node1-dn3 and the observer at 10:08 (igneumd 2.1.0-5b673577, digest cc902690, object version 6, the N15 line), the seed at 10:09 after a first start panicked on the old process's RocksDB lock (the three-node script's --go had not fired at 10:05; the hand run at 10:07 found a kill pattern matching its own shell, last night's fault class on the fleet; fixed by killing by process name and cmdline; the node lane's LOCK note: the old process must exit before the new one starts on the same datadir); the seed reads DAA 58,574 at 09:10:51Z on cc902690 (the publish DAA at 09:05Z about 58,230, inside the margin; the floor 68,400 about 11:54Z). The 0.3.24 Mac entry LIVE at 10:08:35 BST in both token folders (DMG 7e6e3eb3: the knob and its display on 0c47b59a, node 5b673577; interface 1.0.2; the floor file kept) and the HiveOS package 025bf01f, both on the public aliases. Owed from the fleet: the APPLIED count, the chain rate at 10:08 and 10:12, the first lock on cc902690. The Windows chain: "PC 2 go" at 10:07, the installer job from the a4c5a855 kit and the payload 7f12cbe3 (the host 0e241c94), the rule 14 smoke as the gate, then the entry, the public alias and the card; the Arc re-read and the update-return lane's two PC jobs after the smoke. The 0.3.25 plan to the coordinator before 14:00 BST. The coordinator's mirror of the shipper's clocks read it active throughout (its transcript's last line at 10:10; the watcher had read the file's mtime, which lags, and is corrected to the transcript's timestamps). After three lost floors and a stood-down night, 0.3.24 is on Devnet 3 with class v5 at DAA 68,400, about 12:54 BST. THE 0.3.25 PLAN (the shipper, 10:1x BST, from the mirror's tips). Branch and pairing: the app line release-0.3.25 from release-0.3.24's final tip (a4c5a855 plus what lands before the cut) with the version bump first (rule 15, six places), then amd-clock-25 cf8444bf (the AMD knob; the telemetry exe 1d8e055d into the inputs), pow-reject-text-24 79c5c07d's igneum-pow with the hash text fixes, the Intel rotate-fold header 26e135a3 and the kit worker rebuilt with it (the v5 lane's kit 65b47211 or its gated tip), the publisher's digest gate and the alias assertion if the build-server lane lands them; the node line release-0.3.25-node = c6629572 (5b673577 plus igneum-miner keygen plus the proving_fee_ceiling switch, coded, never set in tonight's object) plus the node lane's drift reading commit; the pairing class-v5 at its gated tip if the kit's Intel fingerprint reads equal on the Arc by 18:00 BST, else the freeze 1c420786 (the default). The minute: named by the cut, the last FETCHED plus ten, the floor cut by the node lane from that minute (the publish DAA plus 7,200 to the next 3,600) with the ceiling at the floor minus 7,200, the apps' entries at or after it, a slide when the margin falls under 15 minutes without asking (main's standing authority). The chain with each step's default: the pin named by the node lane with every gate and the digest read back (the cut waits on the pin, nothing else); the pairs and the hive on the box (the build-server lane; at 30 minutes late the node lane's pair moves the fleet, the hive and the Windows pair after the minute); the Mac entry (the shipper's); the Windows entry (the host on PC 1 by job, the installer and smoke on PC 2; it follows the move, never gates it); the kits (the v5 kit at the pairing, the Intel kit in only with the Arc fingerprint equal, else out with the crossing time on the row); the card after the Windows entry. The gate set before the file goes: every box suite on the pin, the two canary sets with the mixed-version refusal, the fast-time SUMMARY on the shipped pair, the kaspa-pow pairing read-back, the app crate gate and pre-push on the app tip, the pack-gate line read back on every reachable box, F8 if the pairing moved off 1c420786, the F9/F1 interim at the minute minus five if F8 was rerun. The move's mechanics from today's lessons: the puller takes the pair's miner sha from the move file (the fleet's puller fix), a box with no running box-dn3.sh restarts from a quoted environment (the nine-node fault of 10:05, the fleet's third known-failed shape), build-1's three by process name with the old process's locks released first. Open: the drift reading's commit (not a consensus field by its description); the evening minute from the shipper the moment the pin is green. CARD-IN READY (the hash lane, 10:1x UK; tools/ca3-v4-amend/pc-card-in.ps1 at 3566ecfe): both known-failed shapes recorded on PC 1 (the baseline of 4 cards; "no new card" in 1 s); a relay "in" with the PC publishes one job (55-minute cap) giving the card's key, VRAM and dataset fit, the v5 and v4 fingerprints through the OpenCL kit on every vendor plus the CUDA sub-version 3 row on NVIDIA, the rate with all three power fields, the lock grid through the helper on NVIDIA (300 MHz steps from the maximum, stop at a 3 percent fall) and measure-only rows on AMD and Intel, the app's own row, the bench-log and miner-bench.json rows as RESULT ROW lines, the restore and "next". The Ember tiers' engine half on ember-tiers-25 at 91406944 (local; the push on the box test build's green by 10:45). The Arc re-read's default: 10:50 UK unless the shipper clears PC 2 earlier. MAIN'S WORD ON THE 0.3.25 PLAN (10:1x BST): it runs as written, one addition to the app line: the three-tier Ember Tune, both halves (the hash lane's engine fields and the apply Cmd on ember-tiers-25; the UI lane's tier buttons with rate, watts and the daily saving, sweep on by default at balanced, per-card wired), gated on 0.3.25 before the cut; if either half is not green by 19:00 BST the cut goes without it and the tiers ride 0.3.26, stated in the record; everything else stands, the silence-means-go at 17:00 and the shipper's minute; two readings to main: one when the pin is green, one at the minute. THE FOUNDER'S WORD AT 10:2x BST: push 0.3.25 everywhere as soon as possible; the plan stands in every mechanic, the clock moves: the cut goes the moment its inputs are green, not tonight. The targets: the node line placeable 11:30; the app line assembled by 12:30 (the AMD knob and exe, the hash text fixes, the Intel header and the rebuilt kit worker, the tiers if both halves are green by 12:30, else they ride 0.3.26 and the record says so); the pin green by 13:00; the move at the last FETCHED plus ten but never before the class v5 crossing at 68,400 (about 12:54) has been read clean by the node lane, so the earliest minute about 13:30; Mac and Hive at the minute, Windows behind it within the hour, the card after; the pairing default 1c420786 unless the Arc fingerprint reads equal by 12:30; the defaults and the slide authority stand; main's silence past any of these clocks means go. THE TIERS' UI HALF (the UI lane, 10:52 BST): branch tiers-25 off release-0.3.24 a4c5a855 = the UI commit e6571f60 plus the merge of the hash lane's ember-tiers-25 3408db40 (d3d0704a); the UI tests known-failed first then 73 green on build-2; mock captures of the three states (the measured 5090 and 5080 at Balanced; the install's first minutes with nothing measured and Ember Tune on at Balanced; the M5 Max with no lever as Stock alone with the reason) under ~/Desktop/igneum-previews-2026-10-08/tiers/; the app crate gate and the full pre-push gate running on the merged tip, the gated tip by about 11:15, inside the 12:30 default; tiers-25 fast-forwards onto release-0.3.25 when the shipper opens it from a4c5a855; the live tier numbers come from the engine's own search, not from any table. THE BUILD-SERVER LANE'S CLOCKS (10:1x BST): the 0.3.25 pairs the moment the pin is named (the start script parameterised on the pin); the publisher's digest gate (publish-manifest.sh --node-bin, --network-digest, --move-clock; tools/digest-read.sh) landing on master before 12:30 and riding the app line (the alias assertion not its own); the telemetry exe's --tune read-back on PC 1 DONE at 09:07Z (the 9070 XT tune line: gmax 0 range -500 to +1000, plimit 0 range -30 to +10, factory 1); the second master-only deploy started 10:15 BST on master's tip. A FAULT: PC 2's 0.3.24 Windows installer failed at ISCC because release-0.3.24's .iss still carries the TDateTime line the 0.3.23 fix removed; the one-line fix with the shipper and the update-return lane, the republish on their tip (the Windows entry's default: it follows the move, never gates it). A SPEND TO SURFACE: two new Hetzner boxes provisioning (build-3 HEL1 32 threads, build-4 FSN1 96 threads, in the pool by 10:45), reported by the build-server lane; ordered on the founder's own word in chat ("re order", about 09:5x BST, after he added the credit himself; main clicked the order in his Chrome profile); the standing rule on purchases held; they stay. SITE DEPLOYED AGAIN (the build-server lane, master f98e8e7c at 09:15:33Z, 10:15 BST, on igneum.network and igneum.com; the checks ok): the tip carries ae8836f8 (row 17's floor sentence, the Arc row restored to its measurement) and the record through the twenty-eighth landing; the served state now carries every served change of the night and morning. THE 0.3.25 NODE LINE PLACEABLE (the node lane, 10:1x BST, ahead of 11:30): release-0.3.25-node = c6629572 on both mirrors (the pin 5b673577 plus igneum-miner keygen and the proving-fee ceiling switch coded and never set), pairing igneum-pow 1c420786; every gate green at 09:16:28Z (build 09:13Z rc 0, igneumd 3fadca49..., /srv/artefacts/0325-c6629572/node-lane; consensus 134, pow 19, miner 29 with the keygen test, p2p-flows 38, exec 48, core 177 at gate priority after a first run on a stale file on the box); the Devnet 3 canary (09:13:25Z to 09:15:04Z): digest cc902690 unchanged, byte 6, the override refused, two empty nodes handshaking, the shared-devnet dialler rejected, and the 0.3.24 pin's node handshaking with this build both ways, so the mixed fleet runs through the placement; the testnet canary b2e856ed unchanged. The keygen read-back from the artefact printed an address and a key (the key elided in every transcript and record; a printed private key never enters a message, a log the relay carries, or this file); the fleet writes keyed wallets from it. The defaults: the line's tip at 13:30 BST is c6629572 plus the drift reading's commit only if both nodes' logs reach the node lane by 12:30, else without it; the ceiling-switch field set in the 0.3.25 object from the shipper's minute by the one-go script (the digest moves then; the hold's second day under the ceiling, as main ruled; a re-cut without asking under a 15-minute margin); the crossing line the moment the DAA passes 68,400, a red first; the TESTNET_PARAMS v5-at-0 re-cut at 13:30 unless main says otherwise by 13:15. THE AMD KNOB'S GATED TIP MOVED (the update-return lane, 10:15 BST): amd-clock-25 e2962b89 (full gate GREEN 60, the box suite 298 green) in place of cf8444bf, with the shipper; from the exe's read-back on PC 1: the integrated Radeon's tune line carries every range as a dash and the knob had read it as an offset knob with a one-MHz ladder; it now reads "not available (the driver exposes no tuning interface for this card)", and the 9070 XT's real line (gmax 0, range -500 to 1000; plimit 0, range -30 to 10; stock 3,292 MHz under load) is the test's second half: the ladder 3,192 down to 2,792, the power 70 to 110 percent, offsets on the apply; the grid by 11:20, the efficient point into EFFICIENT_W before 12:30 or the declared ladder ships. THE MOVE'S READ-BACK (the fleet lane, late against its 10:20 minute): APPLIED on the relay at 09:07Z: 24 MATCH by the puller (igneumd 2.1.0-5b673577, digest cc9026909eddbadb, synced; dn3-g1 at peers 24), p1-3080 on cc902690 by 09:10Z; 2 FAILED (dn3-r01, dn3-r02: no saved environment, hand-started yesterday) moved by hand at 09:10:27Z; 9 MISMATCH with no node after the puller's restart (hub-1, dn3-g2, dn3-q04, dn3-q05, dn3-r04, dn3-p02, dn3-p04, dn3-p05, dn3-relay): the saved environment line NET_ARGS=--devnet --devnet-suffix=3 unquoted, so sourcing it ran "--devnet-suffix=3" as a command and the start never reached box-dn3.sh; all nine moved by hand 09:11:58Z to 09:12:24Z with every value quoted, the puller now quoting every value (redeployed 09:16Z on 34 boxes); so 36 of 36 fetched are on 5b673577 and cc902690 by 09:12:24Z (10:12 BST). The first lock on cc902690: checkpoint 1931, block 63510971..., blue score 57,930, at 09:06:32Z on dn3-g1 (4,803 signed, 69.8 percent of active, 66.7 of total); hub-1 logged the same checkpoint at 09:11:43Z after its hand restart and checkpoint 1944 (blue 58,321) at 09:12:39Z. The chain rate: hub-1 read 0 blocks a minute at 09:07Z because hub-1 was one of the nine down; from 09:12Z the tip moves at about 0.4 chain blocks a second as before, and paidShards moves again (11,821, frozen since 03:32Z, to 12,012 at 09:19Z, pool entries 47): carrying resumed with the move, the node lane's one-shot-gossip class confirmed. The proven share at 09:19Z 0.465 cumulative (the hour's own 0.000, the hour being the move); the proving fee 10,000 gwei per pgas last, 50,566 max over 60 blocks (1.0x and 5.1x the floor), the field now on the hourly line. The unfetched: dn3-agg48 (the L40S in its bring-up, applying at its first tick), p2-3090-1 (ssh refused since 21:48Z yesterday, on 2720d8d2 with 4 old-digest peers), p2-4090-1b (its Vast proxy dead, its node down); dn3-relay fetched at 08:48Z and is on cc902690. The eight "bc5945fe" boxes: no such binary (that sha was the reader's own shell); those boxes had no node at all (dn3-g2 dead since 22:49Z, dn3-g1 since 00:46Z, the others overnight, no panic or OOM on any), restarted 08:43Z to 08:53Z, took the move with the rest, and mine where they mine. The keyed-wallet write not started (the 0325 artefact's first mention to the lane at 10:20; box by box after the launch fleet's first boxes are up; the rent running since 09:16Z). p1-5090's drift reads offset -5 again at 09:21Z; hub-1's numbering against build-1's node the next read. Three fault classes for the record from one move: the unquoted environment line (fixed in the puller), the two hand-started boxes with no saved environment, and the eight boxes that had silently lost their nodes overnight with no panic (a watch for a node absent while its box is up is the fleet's next check). THE TIERS GATED FOR THE CUT (the UI lane, 10:20 BST by the Mac's clock): tiers-25 at d3d0704a on the mirror (the UI commit e6571f60 plus the engine half 3408db40 merged, both off release-0.3.24 a4c5a855, a fast-forward onto release-0.3.25): the app crate gate GREEN 299 + 35 + 8 on build-2, the full pre-push GREEN 60 checks with the stamp, the UI tests 73 green known-failed first, the push gate GREEN; the captures under ~/Desktop/igneum-previews-2026-10-08/tiers/; sent to the shipper; two hours inside the 12:30 default; a rebase and re-gate inside the hour if 0.3.25 opens from a later tip. Both halves of the three-tier Ember Tune are in the cut. THE 0.3.25 APP TIP (the shipper, 10:29 BST, two hours ahead of the 12:30 target): e0d4425f on release-0.3.25 (the box gate green): amd-clock-25 e2962b89, tiers-25 d3d0704a (both halves), the Intel header via 9088293a, the node-source pin c6629572; the node pin candidate c6629572 with the digest cc902690 unchanged; the cut list r0325-cut-list.md: the pin named by 13:00, the move no earlier than 13:30 after the 68,400 crossing reads clean; the pairing 1c420786 unless the Arc reads equal by 12:30, the Intel kit on that read. THE 0.3.25 NODE LINE'S TIP MOVED (the node lane, 7bd2940f on both mirrors at 09:24:03Z, every gate green at 09:29:48Z): c6629572 plus the one-shot gossip fix (unpaid proof records re-announced every 120 s; the class confirmed on the live chain after the 09:05Z move); nothing consensus, the Devnet 3 digest cc902690 unchanged on its canary, the 0.3.24 pin's node handshaking both ways, the testnet digest unchanged; build 09:26Z rc 0 (igneumd 16dee9f1..., /srv/artefacts/0325-7bd2940f/node-lane), exec 49, pow 19, core 177, p2p-flows 38, miner 29, consensus 134 at gate priority; it replaces c6629572 as the placeable keygen build and as the tip the ceiling-field cut lands on; the shipper has the line. The drift item is off this line: the fleet's reads were shared-devnet reads (hub-1's node on 26790 at chain block about 190,900; Devnet 3 at 25,900; both answering chain id 4463 below the floor), p1-5090 a shared-devnet prover, and the three numberings at one hash are the snapshot-inherited class (build-1's node1 itself resumed from a snapshot); the fleet rents a fresh-walk node under its standing ceiling to settle which numbering is right, hub-1's restart held until then, the loader change (re-number the resumed range against the DAG) after that read. THE 0.3.25 PAIRS ON 7bd2940f (the build-server lane, from 10:33:11 BST on build-1 under lease class release, /srv/artefacts/0325-7bd2940f/: the seed about 10:36, the Windows pair about 10:38, the hive package with the three kit zips about 10:41, each minute to the shipper and the coordinator); the c6629572 pairs already built (seed f913e3e7, win 42d0dd57, hive 14d86245) stand in their own folder and are not the cut; the publisher's digest gate on master since 10:17, riding the 0.3.25 app line. THE RE-POINTED APP TIP (the shipper): 92f004f1 on release-0.3.25 (e0d4425f plus the node-source pin to 7bd2940f), the push gate GREEN at 10:32 BST, the box gate GREEN at 10:33:25 (303 + 35 + 8); the cut list's pin candidate 7bd2940f; the kit re-cut from 92f004f1 and the pairs on 7bd2940f's artefact with the build-server lane; the Mac node pair and the DMG rebuilding on 7bd2940f under the lock from 10:32:31; the 13:00 pin and the 13:30 earliest minute standing. The 0.3.25 inputs are all green at 10:33 bar the pin's own gate set and the crossing. A SWEEP FINDING FROM MAIN (10:4x BST): on a rented, power-capped RTX A4000 (114 W cap) class v5 reads 26.0 MH/s against v4's 31.4, 17 percent under, the fingerprint equal; the A100 1.3 percent under; every uncapped consumer card level: v5 costs more compute per hash and a compute-limited card pays, which is what a knee lock makes of a card. Two orders with readings by 12:30: (1) the hash lane sends the 5090's v5 pack rows at the 1,300 lock against v4 at the same lock, and the 5080's if they exist; if v5 at the knee loses more than 2 percent, the knee is re-found under v5 and the tiers table says so; (2) the tiers' engine half: a class change (the chain's program class flipping) invalidates the stored tiers and re-runs the search within ten minutes of the crossing, the first-run line saying why; known-failed first (tiers stored under v4 must read "re-measuring for class v5" after the flip, never apply as if current); on 0.3.25 if it fits by the cut, else 0.3.26 with the record saying the v4 tiers may be off by the measured percentage until the re-tune. Per tier: a locked card may lose a few percent of rate at the class v5 crossing until Ember re-tunes; the number is the 5090 row. THE ORDERS PLACED (the coordinator, 10:4x BST): the hash lane's two readings by 12:30 (the 5090's v5 rows at the 1,300 lock against v4 at the same lock, the 5080's if they exist; the knee re-found under v5 if the loss is over 2 percent; the default if the PC 1 queue cannot run it: the A4000's 17 percent stated for a capped card and "unmeasured at the knee on the 5090"; and ember-tiers-25's class key: a class change invalidates the stored tiers and re-runs the search within ten minutes, known-failed first), the UI lane's class-flip state ("re-measuring for class v5", v4 tiers never applied as current after the flip) and knee note by 12:30, the shipper's cut list carrying both on 0.3.25 only if green by the pin at 13:00, else 0.3.26 with the record's sentence that the v4 tiers may be off by the measured percentage until the re-tune. THE 0.3.25 PAIRS ON build-1 (the build-server lane, /srv/artefacts/0325-7bd2940f/): the seed pair at 10:34:44 BST (igneumd c7fc542b, igneum-miner 4494ecc4, glibc 2.34), the Windows pair at 10:36:13 (igneumd.exe 5d1dea23, igneum-miner.exe eee7bdfa), the hive package igneum-hive-0.3.25-7bd2940f.tar.gz at 10:37:49 (sha d977797f..., the three kit zips, smoked in ubuntu:20.04); the kit re-cut from 92f004f1 (sha 676240f6, 424,540 B) staged in both folders, the PC 1 host from it bc8d4f79 (in host.sha256 at the shipper's 24680e1d), the 0.3.25 Windows payload from 24680e1d cutting. Every pair of the cut exists by 10:38; the pin's gate set and the crossing are the only waits. FOUR NEW LANES ON THE FOUNDER'S ORDER (11:00 BST, "build all this today to close this gap"), mirrored by the coordinator as the shipper's clocks are: the explorer (a5ef1d5801084005b; explorer.igneum.network by 16:00), the canonical DEX and the Sepolia certificate verifier (a74a8267813d6ea34; the AMM by 14:00, the swap UI by 17:00, the verifier by 20:00), the builder pages, faucet and grants (adb29da59baf27898; /build and /grants by 15:00, the faucet by 16:00), three reference apps that only work on a proven chain (a2060899d2a27d31c; /light by 16:00, /receipt by 18:00, the Sepolia oracle demo by 21:00); the build-server lane stands up rpc.devnet.igneum.network by 12:00; they do not touch the 0.3.25 cut, the crossing or the fleet, sharing the boxes' lease pools (class measure) and the master-only deploy; a lane silent past 25 minutes gets the word from the coordinator and then main. THE FAST-TIME GATE ON THE 0.3.25 PAIR: SUMMARY PASS (cross-0325-39f127a1) at 09:54:40Z (10:54 BST) on the pair 39f127a1 (the node code and object byte for byte e0644958's; igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 09:42:25Z to 09:54:40Z, every check green (rung 1 by signal at epoch 6, class v5 by signal at byte 6 from epoch 8 at rung 1 at 9,985 bps, the stale node refused, the restart step resynced in 8 s, four sinks equal, 0 PoW rejections); the ceiling's two new fields absent from the 60x file so the ceiling stayed at never there (the node lane's note); to the shipper the same minute; the pin line names e0644958 and its gates. THE FOUNDER'S WORD AT 11:0x BST ("can we add in any more layers? class rotating? things that would render an ASIC useless as soon as it dropped"): the class v6 design opens today as a rotating family, the research lane and the hash lane under the coordinator, the design doc docs/design/class-v6-rotating-family.md by 18:00 BST with the chip-model rows beside each layer (what it does to k and capex for a fixed-function chip and to the per-joule edge for a GPU-like chip; what it costs every GPU tier, Apple included): (1) per-era draws of the class parameters now fixed by release (the mixer round count within the tested margin, the op-mix weights within the measured safe band, the read width, the program length, the shadow placement), drawn from chain state like the program; (2) the state-derived dataset's size tracking chain-state growth with a floor, so fixed-memory silicon ages out; (3) scheduled family epochs by height (every 180 days by default) with no release; (4) the (c''') acceptance floor and the F8-form uniformity test generalised to each era's parameter draw, redraw on failure, so layers 1 and 3 need no per-era cryptanalysis. Per layer: the gate it needs (the family analysed as a family: the attack board's shape over the testnet period), the known-failed test, an honest line on what a fully general chip still gets. No consensus code this week; the document, the numbers and the gate plan. Per tier for the founder tonight: what each layer does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE ARC RE-READ IN ITS CHAIN (the hash lane, 10:57 UK): no clear came from the shipper, so the default ran at 10:50: the rotate-fold kit's fetch (sha 65b47211) published to PC 2 at 10:51:41, the run (run-ca3-pc2-v5-intel-bench-20261008, the v5 lane's script c0d398a1) in the publish chain behind another lane's publish-jobs.sh sign --deploy from the build-server worktree (the publisher serialises); the fingerprint line by 11:15 if the publisher frees inside ten minutes, else the blocking process named by 11:10. Queued on PC 1 behind the same publisher: run-ca3-pc1-v5lock-5090-20261008 (class v5 against v4 at unlocked, 1,300 and 1,200 MHz, the v5 kit's CUDA packs), its rows by 12:30; the AMD grid after it from about 11:25. The class-key work on ember-tiers-25 started; the v6 cost rows by 16:00 taken. THE TIERS' CLASS-FLIP STATE, THE UI HALF (the UI lane, 10:57 BST): tiers-class-25 at d949e274 on the mirror, off release-0.3.25's tip 24680e1d (the shipper having merged tiers-25 d3d0704a into release-0.3.25 at 111dae69), the crate gate GREEN 303 + 35 + 8 on build-1, the full pre-push GREEN 60, the UI tests 74 green known-failed first (the v4 tiers stayed on the buttons after the flip on d3d0704a); after the flip the table reads "re-measuring for class v5" on every button with the start minute or "queued (within ten minutes of the crossing)", the v4 watts never current, the strip's sentence naming the crossing; the knee note under the table when knee_loss_pct is over 2 percent; the captures tiers-flip-dark.png and -light.png; the fields tiers_class, program_class, tiers_remeasure_at, knee_loss_pct (the shape sent to the hash lane at 10:4x; the engine sha by 12:30); the default: the display rides 0.3.25 inert if the engine half is late and lights up on 0.3.26. THE FOUNDER'S WORD AT 11:1x BST: class v6 is DECLARED with the four layers as its spine (per-era parameter draws, the dataset tracking chain state, scheduled family epochs by height, the acceptance floor generalised to parameters), and deep past-and-future research opens now under the coordinator with serious resources ("see if anything can be optimised, added or invented"; reading public research is in-house, nothing paid or asked of anyone outside): four research lanes today, (A) history (every ASIC-resistant proof-of-work and how it fell or held: Ethash and the E3 and Linzhi chips, ProgPoW's review, RandomX and its chip analyses, Cuckoo, Equihash and the Z9, Argon2 and Scrypt and the Litecoin chips, KawPow, Autolykos, Octopus, kHeavyHash's chips; the exact mechanism each chip used and what the design missed, each mapped to Igneum's layers with "does v6 close it" as a sentence and a number), (B) the hardware future five years out (PIM and processing-near-memory, HBM3e and HBM4, LPDDR6, 3D DRAM, CXL memory pools, wafer-scale, chiplets, FPGA with HBM; for each the chip-model k band against a state-sized dataset and dependent random reads, and the one layer that would blunt it), (C) invention (layers beyond the four, each a paragraph, a known-failed test and a chip-model row: data-dependent program graphs, latency-bound dependent reads tied to the shard proof, randomised memory topology per era, VRAM-size ratchets, proof-carrying hashes sampled by the pool, time-locked parameter commitments, and what the lane invents; rejecting what costs GPUs more than chips), (D) the family gate (how a parameter family is cryptanalysed as a family: sampling bounds, coverage, the F8-form and (c''') tests over the parameter space, the attack board's shape over the testnet period, so layers 1, 3 and 4 can be automatic with a proof of what was tested). Resources: all four boxes under lease class measure, PC 1 by job for card rows, the rented fleet for one-shot measurements inside the ceiling. Deliverables: a first synthesis in docs/design/class-v6-rotating-family.md by 20:00 BST (the four layers priced, every finding from A to D with its number, a ranked list of what v6 adds beyond the four, the honest line on what a fully general chip still gets), the full report by 09:00 tomorrow, one line to main per lane as each lands; per tier at 20:00: what v6 does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE 0.3.25 APP TIP AND PIN CANDIDATE (the shipper, 10:58 BST): the app tip 9b93e649 (push gate GREEN; the crate unchanged from e0d4425f; the node-source pin to e0644958 and host.sha256 bc8d4f79); the pin candidate the node lane's ceiling cut e0644958 (digest 1b37cb9d, every gate green 10:53, the fast-time SUMMARY PASS 10:54, the floor at DAA 82,800 about 16:53 BST, a publish up to 14:53 without a second cut); the tiers' class-key halves: the UI lane's tiers-class-25 d949e274 green and inert alone, merged with the hash lane's engine sha the moment it lands (12:30), gated as a pair on the release tip, riding only if green by the 13:00 pin; the 0.3.24 Windows take 2 failed at a new place (Inno stopped the app and copied nothing); the update-return lane owns the fix on release-0.3.25 by 12:30, the default the 0.3.25 Windows entry waiting for a clean take 3 while Mac and HiveOS move at the minute. THE FOUR CLASS V6 RESEARCH LANES SPAWNED (the coordinator, 11:0x BST, each with its worktree, its box resources under lease class measure, its clocks and the rules): lane A history (a603a938582c43ab5; the first cut docs/analysis/class-v6/history.md by 15:00), lane B the hardware future (a4f73e2a6f2d1b757; hardware-future.md by 16:00), lane C invention (a5dfe95ee8c47cd0f; invention.md by 17:00), lane D the family gate (a07a99a3788566af2; family-gate.md by 17:00); each feeds the research lane's synthesis docs/design/class-v6-rotating-family.md by 20:00 (its outline by 13:00; the hash lane's per-tier rows by 16:00); the full reports by 09:00 tomorrow; the coordinator's lane mirror carries their clocks. A HELD PUSH AND ITS CAUSE (11:00 BST): the hash lane's push of ca3-v4-amend was refused at 10:58 by the gh-account hook reading the founder's gh (his personal login active again; nothing switched by any lane); the cause is the branch's own hook, which predates the per-process fix (34b0884d): the hook runs the branch's tools/ci, so every branch older than 09:58 must merge the mirror's master before its next push, under which the check reads Igneum's own gh directory and skips under the suspension marker; the rule to every lane. Live: the Arc re-read on PC 2 (published 10:59:47) and the v5lock job on PC 1 (published 10:53, about 12 minutes). THE CLASS V6 OUTLINE ON THE MIRROR (the research lane, docs/design/class-v6-rotating-family.md on counter-asic-4, the commit after fb61ed4b, pushed 10:5x UTC, two hours ahead of 13:00): section 0 the founder's table (per layer, what it does to a fixed-function chip and to a GPU-like chip on its release day, and the 5090, 5070 Ti and M5 Max columns, measured where the night's rows exist, the 5070 Ti scaled until the hash lane's row); the honest frame on top: the four layers render a FIXED-FUNCTION chip useless on the first era its wired value leaves (one tape-out lives one era) and move nothing for the stored-dataset chip with a programmable core except the core's size and the N5 project it forces; that chip keeps 3.6x at zero premium and 2.1x at k = 1 on a 5090 at its knee. The layer table (sections 1 and 2) names the bands each draw takes and the measured rows that set them: the mixer in {4, 8, 16} (x16 open), the op-mix weights within B = 4 with shuffle and mulhi capped (shfl 55.8 pJ per op), the read width in {1, 4} words (w64 excluded by the 5 October rows), the block shape 64 to 256 (never 1,024), N left to the ladder's signal (an unconditional draw retires the Apple tier at 200,000). Open numbers asked of the hash lane with defaults at 16:00: the 5070 Ti row (the rented 5070 scaled), the x16 mixer's verifier and build (the chip model's estimate), two re-weighted shadow packs for the op-mix band (the microbench arithmetic). Layers 2 to 4 and the gate plan are skeletons with their sources named, filling by 18:00 with the four research lanes' cuts, the synthesis by 20:00. THE FOUNDER'S WORD AT 11:2x BST ("all builders are idle, load them up"): build-1 to build-4 filled now and kept above 80 percent all day under the lease pool, class measure behind the release gates, in this order of value: (1) the class v6 family gate's sampling runs for lane D (the F8-form census and the (c''') floor over the parameter bands: the mixer {4, 8, 16}, the op-mix weights within B = 4 with shuffle and mulhi capped, the read width {1, 4}, the block 64 to 256; thousands of drawn eras, the uniformity and bucket tests on each, so the family document carries measured coverage tonight); (2) the attack families at scale on the 0.3.25 pin candidate's igneum-pow (F8 to 256 seeds, F9 and F1 to 10^6 on the frozen 1c420786, the day-key scan to 2^28) as the record's strengthening lines; (3) the invention lane's candidate layers measured as packs as fast as it writes them; (4) the full suite matrix of the 0.3.25 pin on every box as the pre-pin check; (5) the Windows and hive cross builds and the sweep's reruns; the lease tool's pre-emption giving release-class work the cores when the pin's gates need them; one line to main at 12:00 with the load on each box and what runs there, then hourly only if a box drops idle. THE DRIFT CLASS SETTLED (the node lane, from the fleet's fresh-walk node, a shared-devnet node synced from an empty datadir to 191,441 chain blocks at 10:03:45Z): hub-1 and five standing boxes number the fresh chain exactly; seven boxes carry numbering inherited from an exec snapshot taken on a chain that later re-walked (+2: p1-4090, p1-a5000, pool-1, build-1's node1; +3: p2-3090-2; +4: p2-3090-4; +5: p1-5090 and p2-3090-3), and a restart on the kept datadir does not re-walk (p1-5090 at 09:22Z stayed +5); the cost: a prover on drifted numbering signs statements the hub vetoes, so the seven earn nothing from proving until they re-walk, the drift refusal stopping the waste. The node lane's word to the fleet: p1-5090 first, both snapshot files moved aside so the executor re-walks from the DAG, the re-walk timed and read against the fresh node, then the other six in series, hub-1 untouched, build-1's node1 after the 12:40Z move; if the re-walk reads over two hours the six wait for the node-side fix on the next node line (the loader re-numbering a resumed range against the DAG before serving). THE 0.3.25 PIN CANDIDATE CONFIRMED (the node lane): e0644958 on both mirrors (keygen, the re-announce, the ceiling switch at 82,800 in the Devnet 3 object, digest 1b37cb9d, the 0.3.24 pin refused both ways), every gate green at 09:53:01Z, the fast-time SUMMARY PASS at 09:54:40Z on the same object; the publish ceiling DAA 75,600 (14:53 BST); waiting only on the 68,400 crossing reading clean (about 12:54; the node lane's line the moment the DAA passes it); the shipper names the pin at 13:00; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. LANE C'S FIRST PACK (the invention lane, 11:0x BST by the Mac's clock; its own line read "12:1x", a clock to correct): build-1 takes the igneum-pow build from counter-asic-4 at 5984ffab, then the per-load shadow in its sound form (mx8+shl6912x1: 16 sub-blocks of 432, one pass, the form 20.2a named and never drew) as the first candidate: the acceptance census over 64 seeds and 16 drawn eras against the 16x27 form and the class v4 shape, the pack export, the F8 read at 2^24 and the verifier bench on a leased core, the first read by 13:30; build-2 next for the second candidate (warp-uniform data-dependent block selection); the candidates with no pack form (the VDF commitment, the VRAM ratchet, the pool-sampled witness, the state-tied reads) stay modelled and the 17:00 cut says so; the worktree igneum-wt-v6-invention on class-v6-invention. THE WINDOWS INSTALLER CLASS AND THE 0.3.25 TIP (the shipper, 11:08 BST): the app tip 139c147a (9b93e649 plus install-detach-25 52a34111, packaging/windows and tools/ci only, the crate unchanged; push gate GREEN); the 0.3.24 take 2 class: an installer started under the app's job runner is a child of the engine, and the engine's kill_tree on quit ended it between PrepareToInstall and the copy; the fix re-launches the installer as a one-shot scheduled task outside the job's tree; the 0.3.24 Windows entry skipped; the rule-14 take on PC 2 is the 0.3.25 installer over the running 0.3.21 app, queued ahead of the Arc re-read; the pin candidate e0644958, the DMG 501ba293 staged, the 13:00 pin and the 13:40 provisional minute standing. THE ATTACK FAMILIES AT SCALE (the attack-pass lane, cores held at 11:08 BST, every run under lease pool class measure): box 2 (88 cores): F8 seeds p66 to p257 (192 new, 256 with the gate's p2 to p65) at 2^24 on class v5 at the freeze 1c420786 (the gated binary 0f5c98dc, pairing e5a4ac5978462156; the leaves re-run on 8f481459 if the kit pairing flips), the window-model control, by-site, as three thirds of 64 seeds; box 4 (80 cores held, 16 asked): F9 to 10^6 on 1c420786 (seeds 100,000 to 999,999 in six chunks of 150,000 at 8 threads, four running), F1 to 10^6 class v5 programs on 1c420786 (one census at 40 threads with the progress line and flushed partials, re-drawing the record's first 10^5 on the way as a reproduction check), the F4 day-key scan to 2^28 on 8ca66afa's redraw rule at 8 threads; nothing on build-1 or build-3 (lane D's); the projections: F4 about 2 to 3 hours, F8's 192 seeds about 9 hours, F9's 900,000 and F1's 10^6 about 30 hours each, so the 17:00 default is partials for those two with the lane (d) rows carrying counts so far; any pre-emption by release-class work reported. THE RPC AND THE 0.3.25 PAIRS ON THE PIN CANDIDATE (the build-server lane, 11:0x BST): rpc.devnet.igneum.network up since 11:08 BST (the first of the founder's builder clocks, 52 minutes ahead); the 0.3.25 pairs on e0644958 running on build-1 since 11:06 (the app tip 139c147a), the Windows and hive crosses on build-2, build-3 and build-4 as reproducibility rows at class release by about 12:40; the sweep reruns' list not held by the lane, the default at 12:30: last night's sweep logs on build-1 read for rows that ended without a result line and those rerun at class measure. THE SWEEP RERUNS' LIST (the fleet lane to the build-server lane, 11:1x BST): the fleet ran nothing under the build boxes' lease pool last night (every fleet bench a rented GPU one-shot), so the rows the lease kills cut short are the hash and class lanes' and the build-server lane's default read on build-1 is the right one; the fleet's own rows without a result (A10, A40, A100 40 GB, H100 NVL, H100 PCIe, MI250, RTX 3050, RX 7800 XT, 7900 XT, 7900 XTX, 6900 XT) are provider gaps needing a GPU host, rerun the moment a provider lists one. THE CLASS-FLIP TIERS, BOTH HALVES (the UI lane, 11:13 BST by the Mac's clock, 1 h 47 min inside the 13:00 pin): tiers-class-25 at 081b3ba7 (the display d949e274 plus the hash lane's ember-tiers-25 0a838072, on release-0.3.25's 9b93e649; the field names matched exactly): the crate gate GREEN 305 + 35 + 8 on build-1, the pre-push GREEN 60, the UI tests 78 green known-failed first, the push gate GREEN; with the shipper. A RED ON THE RELEASE TIP, for the shipper and the update-return lane: release-0.3.25's 139c147a is red on one crate test (ota::return_tests::no_relaunch_while_an_installer_runs_and_a_relaunch_when_it_clears, 304 of 305): install-detach's 0c588b09 reshaped the installer's clear step into a multi-line block while the test asserts the one-line literal at app/igneum-app/src/ota.rs:1348; 9b93e649 passes; the fix is the test's literal on the install-detach line; the UI lane built on 9b93e649 so its tip is green alone. A RED FROM THE PIN MATRIX (the CI steward, 11:13 UK): the core suite fails on the pair (the node e0644958 with the app tree 9b93e649): config::params::tests::fast_time_60x_file_is_the_devnet_at_60x panics "override-60x.json lacks the field base_unit_decimals"; the field was added by 0e4ec18a on ca3-v4-node yesterday at 21:45 UK and reached neither master, release-0.3.25 nor the app tip while the node line's test demands it; so every box reads red on core, and the fix is one line on release-0.3.25 (the cherry-pick of 0e4ec18a, or "base_unit_decimals": 8 in infra/fast-time/override-60x.json); sent to the shipper; green so far pow and app on build-1 and build-3; the two new boxes' toolchains read the same as build-1 (Ubuntu 24.04.5, glibc 2.39, the pinned rustc, sccache and lease, no nvcc). The founder's fourth load item paid in its first ten minutes: a red no single-box gate had read. MAIN'S WORD ON THE TWO REDS (11:1x BST): the install-detach fix belongs in 0.3.25 if it can make it, since a Windows install by any path that lets the engine's job runner kill the installer mid-copy is the plug-tune-play fault class (an update a user repairs by hand); the default order: the update-return lane fixes the ota.rs literal by 12:00; if 139c147a plus the fix is green on the crate gate by 12:15 the cut goes from it, else from 9b93e649 with the detach on 0.3.26 and the record saying Windows installs by job stay unreliable until then; the missing 60x field: the CI steward lands the one-line field on master and the release line by 11:45; the pin slides under the shipper's authority inside 14:53. THE DAY-KEY SCAN TO 2^28 (the attack-pass lane; class-v5 8ca66afa's redraw rule, build-4 under lease pool 8 class measure, 379.2 s, census-2p28.md at 10:15Z, 11:15 BST): days with any gain over 1.1x: 0 of 268,435,456 on M1 (median 226), 0 against the mean, 0 on M2, 0 on ROT and RC; the M1 cost mean 225.791, sd 6.073, min 206 (day 27,016 at 1.0971x, the redraw rule's floor: no day under 206 in 2^28), max 258; every weak class on its analytic expectation (ROT any pair summing to 32: 160,354,008 against 161,256,979; RC any zero: 1 against 1.0, at cost 234, no gain; RC with rk = 0: 87 against 72, 1.8 sigma; the two cells under expectation the rule's own refusals). PASS: no chip buys a weak day in the first 735,000 years of days; at most 1.097x on the best day. The row and f4-weakday.md section 10 committed on attack-pass at eabb4b0e, the push held by the branch's old hook (the fix: merge master, under which the check reads Igneum's own gh directory and skips under the suspension marker). THE SWEEP RERUNS' READ (the build-server lane, 11:18 BST): build-1's records hold no hash-lane or v5-lane run the pool cut short (preempt.log: three TERMs all night, every one to an adv-class holder pre-empted by a release gate, not reruns by rule; no reaped.log; builds.jsonl for 18:00Z to 09:00Z 150 rows with no signal end, the non-zero rows the fast-time gate's designed failed cases and build errors; the census and fingerprint suites leaving no builds.jsonl row and no output directory ending without its result); live at 11:17Z the family gate's v5_attempts_census holding 24 cores on build-1 at class measure; the default at 12:30 if neither lane names a run: no reruns, the boxes carrying the e0644958 reproducibility crosses (build-3's Windows pair already read: igneumd.exe 4b0c3aeb, igneum-miner.exe b3da4088) and the gates. The founder's fifth load item is therefore the crosses, not reruns. The attack-pass branch merged master and pushed (460fd9fa, the F4 2^28 row and f4-weakday.md section 10 on the mirror; the hook skipping the gh read with its suspended line; nothing switched). THE FAMILY GATE'S FIRST COVERAGE (lane D, 11:2x BST by the Mac's clock; its own line read "11:3x"): the harness live on build-1 under lease pool class measure (scripts and pinned binaries under /srv/builds/_adv-family-gate/): (1) the base control v5_attempts_census on the shipped class v5 draw over f8-label seeds 1,000 to 11,000, 24 cores since 11:16; (2) the family harness family_gate_era_census (branch family-gate-v5 = class-v5 8f481459 plus the harness, never a chain path; the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE): one drawn era per seed, every layer-1 parameter from the era's own stream (the shadow block {64, 128, 256} x {108, 54, 27}, the mixer {4, 8, 16} recorded, the read width over {1, 4} words, the ten weights within B = 4 with shfl and mulhi never raised), the chain draw through the real rule with every candidate's first failing part, then on the accepted program at the rule's own 2^20 sample the (c'')/(c''') ratio, the largest 256-item bucket per site (ratio and sigma), the index-bit bias per site in sigma; the 16-era smoke run PASSED at 11:21 (about 10 core-seconds per era; 10,000 eras about 28 core-hours). THE WORST READINGS IN THE 16: (a) the index-bit bias read fires HARD on 7 of 16 eras, |z| 130 to 511 at one site, every one at address bit R (the era's stride rotation) or R+1 (era 15 with R = 25 bit 25 z -511 at P(bit) 0.25, a product's bit 0; era 7 R = 17 z -468; era 5 R = 26 z -440; era 13 R = 1 bit 2 z -255, a product's bit 1 at 3/8; era 1 R = 6 z -224; era 12 R = 5 bit 6 z -130; era 6 R = 18 z +256, an or-shaped source at 5/8), the other 9 under |z| 3.8: adv-cache-2's era-stride class measured at the acceptance's own sample on class v5 accepted programs: not diffuse at the bit level, a 25 percent bias on one address bit of one site in about 40 percent of drawn eras, which (c''') does not see (min ratios 0.9954 to 1.0000); a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50, about 1.6 percent of a hash's reads at f = 1/2 for one site, which does not move the f = 1 verdict but is an auditor's flag on "uniform random reads"; the lever is load_index's form (fold the product's low bits before the rotation), not a floor (a 6-sigma refusal would redraw about 40 percent of epochs): a class v6 design row. (b) The (c'') ratio min 0.9954 (era 7), the rest 0.9965 to 1.0000. (c) Attempts: 14 of 16 accepted at attempt 0 or 1; era 9 (shape 64, width 4, mul 11 and or 8 of 75) took 24 candidates: the lossy corner raises r, the exhaustion number to read per stratum. (d) The largest 256-item bucket: ratios 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets, +4.4 sigma), so the F8-tail bound must be stated in sigma, not ratio (the sigma column in the rebuild). Next: the random stratum (10,000 eras) and the corner strata (the lossy cap, width 4, shape 64, 3,000 each) on build-1's free 64 cores, then build-3 and build-4; the first cut of family-gate.md drafted, the measured coverage table in at 16:xx for the 17:00 cut. THE OTA TEST LITERAL FIXED (the update-return lane, 11:23 BST, ahead of both clocks): ota-test-25 off release-0.3.25 139c147a, tip 53cb2f73 on the mirror, one test-only commit (the test reading the installer's clear step as the begin/end block the detach made it; the detach's behaviour kept), the box 2 crate suite 303 + 35 + 8 passed, 0 failed, the full gate GREEN 60; the shipper's cut tip 139c147a plus this commit, so the install-detach rides 0.3.25 and the PC 2 rule-14 take runs on it. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. THE FAST-TIME GATE ON THE RE-CUT: SUMMARY PASS (cross-0324-c9e385eb) at 22:49:32Z (23:49 BST) on the shipped 0.3.24 re-cut c9e385eb (igneumd 7a841b20..., igneum-miner 1e209b9e..., igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 22:36:25Z to 22:49:32Z, every check green: rung 1 by signal at epoch 6 (22:42:54Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (22:44:54Z, 4 of 4, 9,985 bps), 11 of 11 ids equal to the CPU verifier's, the stale node 86 of 86 refused with 0 accepted after the first refresh, the restart step across the boundary on a kept datadir resynced in 28.1 s with the catch-up done after 10 s and 0 of its own blocks during it, four sinks equal at 660, honest nodes 0 PoW rejections; record on v5-fasttime 76276be6, docs/design/class-v5-harness/fasttime/cross-0324-c9e385eb.json. The 0.3.24 move's gates left (the shipper's correction of this record): not F9 and F1's full 10^5 PASS (landing about 00:40 BST, too close to the 00:52 ceiling) but an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, max attempt 25), any non-zero holding the move, the full 10^5 the record line after; the minute named by the fleet on the last FETCHED plus ten once the build-server lane's c9e385eb pairs land. THE 61-ROW ERA READING (the v5 lane, box 2, 23:4x to 23:5x BST, docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log): 0 of 61 refused by the 0.995 floor at the table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), every class v5 draw on the class v4 attempt; era-drawn-28 (id 5e9eb01efbbf653e, attempt 6, R 15, the worst of adv-cache-2's census at 1.7451x) reads its biased site 15 at 0.9969, over the floor by 0.0019; era-drawn-25 (1.3571x, R 21) site 11 at 0.9994; the eight over 1.2x span 0.9965 to 0.9997 while the eight few-item hot sets sat 0.003 to 0.013 under the line. Main's sentence opens AP-F8-6 and section 14 verbatim with the two-instrument reading under it. THE CLASS V5 ATTEMPTS CENSUS for 1.4.7 (1,000 f8 seeds through the chain draw, v5-attempts-census-1000.log, the crypto lane's form): 3,219 candidates, 2,219 rejected, per-candidate rejection 0.6893 (sub-version 3: 0.68), accepted attempt mean 2.219, 0 exhaustions, P(256 consecutive) 4.4e-42; first failing part (a') 83.4 percent of rejections, (a) 10.7, (b) 3.0, (c'') 1.2, (c''') 1.0 (0.7 percent of candidates, one in 140: the floor's own share, 0.045 on the attempt mean), (c) 0.7 together, (c') none; the 5.14 percent of class v3 that 1.4.6 quotes is the audit lane's to replace. Both on class-v5 at 3b1dffd6 with main's sentence (891dd008), the mirror's master merged (e0471019: AP-F8-1's update and AP-F8-4 taken, the program-id recipe form with the state tag, no conflict), the design page's pre-public scrub (the founder's name six times, gone), M35's status word and the regenerated public ledger; the push waits on the full gate and the pinned-packs test on the merged tree (the proof that e5a4ac5978462156 and the other ids still derive under master's recipe form). THE 00:00 BST READINGS (the crypto lane; the verified roll-up of all nine lanes in section 13 of in-house-pass.md on crypto-engage, every branch tip read from the mirror and igneum-pow identical to 017e7037 on each). adv-accept, tip a7c49399 (about 5.5 box-hours, 0 pod-hours): 182,646 distinct accepted programs drawn (18 percent of the 10^6); eight pass every part of the frozen rule and flag the live hot-set test at 2^24 (X at 0.1 percent +0.102 to +0.221, 1.54x to 2.24x), all in the lowest 34 stand-in-ratio seeds against 0 in 20 random; each about 1 MB of items holding 0.26 to 0.41 percent of reads, 1.002x at the largest; the mechanism a near-saturated source at one site mapped by the era stride to one fixed item (plus two lesser shapes); the exemplar reads the same under the class v5 dataset. Against the class v5 floor: 8 of 8 refused; 3 mild residuals missed (adv-cache-2's rotation class, a load_index question not a floor question); 6 clean programs refused among the 9 deepest (the 2.4 percent). Q2 BOUND (54 programs plus 17 reads, 0 disagreements). Row 90: 0.6787 per candidate, (a') 83.3 percent, 0 exhaustions, P 8e-44. Partial named: 18 percent of seeds, 54 live rows, row 90 at half; a longer pass adds rows of the same shapes, not a different answer, unless a seed reads a hot set over 1 percent of reads, which 182,646 draws did not produce. THE PER-LOAD CLASS CLOSED (the research lane, for main; clock readings UTC): the per-load shadow fix held for distinctness and then met the value-level requirement from adv-cache-2, and the construction did not survive it; the per-load 16 x 27 class is dead as a chain class. 22:44 the attempt verdicts on four seeds (igneum-genesis 0 of 32 accepted); 22:47 the 64-seed census under the full rule (duplicate lanes at a load row plus the one-count of every index bit per site over the 64 units, 6-sigma band): 22 of 1,621 candidates accepted (1.4 percent), 42 of 64 seeds exhaust the chain's 32 attempts (an epoch without a program); the first failing test per candidate: biased index bit 775, duplicate lanes 643, the base rule 110, (b) 43, (a) 28; candidate 0 of the class carries index bit 0 set in 40 of 1,024 addresses (z 29.5); 22:52 the suite green (64 + 5 + 7 + 4 + 19 + 2 + 7); the acceptance rule with BiasedIndexBit for this class and the tests pushed as the record, the file's 20.2a closed. The structural reason: 27 passes of a 16-instruction map right before a load is an iterated small function and collapses or biases the load's address register before any base instruction re-randomises it; the class v4 shape has 64 base instructions and 16 loads between its block and every load. Both exports were accepted only because the rule did not model the placement; their PC 1 rows stay as an energy reading of the placement, labelled unsound. Rank 4 and the USD 200 M capex row rest on a construction not shown to exist (chip model 5.11's clause marked so in this landing); the sound form is one pass of a 432-instruction sub-block per load (a program segment, not an iterated map), a new class to draw, accept and measure, not tonight's. Replicated by a second instrument: the class v4 shape on this pre-amendment generator carries the adv-cache-2 product bit at address bit R exactly in 14 of 17 drawn eras (one-count 250 or 780 of 1,024, z 15 to 19), 0 duplicate pairs across the eras. What stands from the two prototypes: the tile block (bit-exact on the Metal reference, the AVX2 verifier at 0.047 us per tile, the Apple emulation cost 35 to 78 percent) awaiting its 5090 rows; the per-load placement closed. THE SPEC REWRITE ON MASTER (the site audit lane, 8b834634 at 23:56 BST; gate GREEN on 64e2a91b, 71 checks; the igneum-pow suite green on the box for that commit with derivation.rs and spec_readback.rs): spec 01 sections 1.4.3 and 1.4.6.1 to 1.4.6.6 rewritten to 017e7037 with the 20-row constants table (ACCEPT_TAG, the window-cap literal, MAX_SATURATED as the first refused count with the 163 message noted) and the 6-row pinned-ids table with Devnet 3's full genesis hex; the shadow block in 1.7; the ninth era draw in 1.13.1; tools/ci/spec-constants-check.mjs in the gate (known-failed first, every Constant | Value | Where table, pending rows skipped while absent); igneum-pow/tests/spec_readback.rs (ids derived through the crate, each class v4 row drawn to its attempt); ledger AP-F8-5 after AP-F8-4; the ledger-page fix (both heading forms, the pass as its own section, known-failed self-test in the gate; AP-F8-1, AP-F8-4 and AP-F8-5 render on /ledger); the fud-ledger's two prize clauses and "paid independent cryptanalysis" removed at the source so the regenerated page carries neither (commit 90424d5a, merge 64e2a91b). A HARDWARE FACT IN DISPUTE, for main: tonight's 5080 efficiency rows came from PC 1 jobs (run-ca3-pc1-v4-eff-5080-20261007-b and -c), the audit lane's record reads the RTX 5080 and the Arc B580 on PC 1, the hash lane's 22:09Z device list on PC 1 shows the 5090, the 9070 XT and the 4070 only, and main places the 5080 and the B580 on PC 2; identity-check.sh's "PC 2" substitution text names cards and is left card-free until the PC 2 job's own --list settles which cards sit where. THE IDENTITY CHECK'S PC 2 TEXT (the CI steward, 00:05 UK on 8 October): tools/ci/identity-check.sh rewrites "PC 2" card-free as "the second Windows rig" (commit 40f2be54, merge 0d2cf334, gate GREEN 71 checks, identity grep 0 hits over 306 export files and 52 served pages); line 69's PC 1 list untouched; the reason recorded in a bash comment above the perl call. THE 32,400 FLOOR LOST (the node lane, 00:0x UK on 8 October): dn3-g1's chain read DAA 25,126 at 23:52:03Z and 25,169 at 23:52:38Z, so the publish DAA passed 25,200 at about 23:53:09Z with no 0.3.24 move made (build-1's three Devnet 3 nodes last restarted about 21:31Z on the 0.3.23 move; the old seed holds 38 peers on ba75bf6f; no move minute was named). The next boundary is 36,000 (epoch 10), about 02:52Z on 8 October (03:52 BST) at 1.0 DAA/s, holding for a publish up to DAA 28,800 (about 00:53Z, 01:53 BST). Two routes put to the shipper and main: the same re-cut script on release-0.3.24-node (program_class_v5_activation_daa 36,000, nothing else, the same gate set, about 20 minutes to the pin line), or the fleet names its minute first and the floor is cut from it in one go (publish DAA plus 7,200 to the next 3,600) instead of a fourth chase; the pin c9e385eb stands meanwhile. THE FLOOR RE-CUT FROM A NAMED MINUTE (the shipper, 00:1x BST on 8 October, under the slip rule main set with the object commit): the floor re-cuts once more to 39,600 (epoch 11, about 04:52 BST) from a move minute the shipper named: 02:00 BST on 8 October, or the fleet's last FETCHED plus ten if later but before 02:53 BST (DAA 32,400, the ceiling); the node lane's pin line in about 20 minutes with the new Devnet 3 digest; the F9/F1 interim read at 01:55 BST; the publish minute equals the move minute (the apps' entries at or after it); the fast-time SUMMARY PASS reruns on the new pin as part of its gate set; the cause of the lost floor named: the c9e385eb pairs and the two PC jobs unreported for forty minutes, so the fleet had nothing to point its move file at. "slot closed" on PC 1 still waits on the host job's exit. THE 0.3.24 NODE PIN AT 39,600 (the node lane): dfbd1e10 on release-0.3.24-node (both mirrors, 23:54:13Z) = c9e385eb with program_class_v5_activation_daa 39,600 (epoch 11), nothing else; pairing igneum-pow 1c420786; every gate green at 00:01:52Z (build 23:56Z rc 0 at gate priority, igneumd 4870ccf2..., igneum-miner aa8c2978..., /srv/artefacts/0324-dfbd1e10/node-lane; pow 19, consensus 134, p2p-flows 38, exec 47, core 175, miner 28); the Devnet 3 canary set (23:56:33Z to 23:58:13Z): digest b1ba78229b069dc395fa666638a686a66615eb760d251798adfa6a654a415f82 on igneum-devnet-3 from ba75bf6f, object version 6 stamped (block version 1538), the override file refused, shutdown 2,015 ms, two empty nodes handshaking on it, the shared-devnet dialler rejected, a 2720d8d2 node refused on the digest both ways; the testnet canary b2e856ed unchanged (byte 7, a live old-object testnet node refused). The cut's read: dn3-g1 at DAA 25,169 at 23:52:38Z (1.0 DAA/s), the publish DAA at the named minute 01:00Z about 29,211, plus 7,200 = 36,411, the boundary 39,600 about 03:53:09Z on 8 October (04:53 BST), holding for a publish up to DAA 32,400 (about 01:53:09Z, 02:53 BST). The one gate running: the fast-time pair on dfbd1e10 (about 13 minutes from its start). c9e385eb is void as a pin; the F9/F1 interim read armed at 00:55Z. THE TWO PC QUEUES AT 01:03 BST (the hash lane): PC 1's "slot closed" has not come (the shipper's 0.3.24 host job, the build-server lane's, took the slot at 22:13Z for an expected two to three minutes; nothing reported in 110 minutes); nothing of the hash lane's has run on PC 1 since 22:09:25Z; the v5 kit fetch and the 9070 XT v5 bench are prepared and unpublished (tools/ca3-v4-amend/pc1-publish-20261007.sh, steps v5-kit and v5-amd), so no 9070 XT class v5 fingerprint exists yet; the lock protocol holds unless main says the lock-free pair goes ahead of the silent host job. PC 2's "clear" has not come either (the 0.3.23 take 3 smoke and the scheduler proof unreported by either lane); the Intel job is prepared and unpublished. THE HARDWARE FACT, read from tonight's PC 1 lines: nvidia-smi on PC 1 lists GPU 0 RTX 5090 (bus 01:00.0) and GPU 1 RTX 5080 (bus 0D:00.0); its OpenCL list carries the RX 9070 XT (gfx1201) and the integrated gfx1036 and no Intel platform; so the 5080 is on PC 1 (the audit lane's record right, the 22:09Z device-list summary short by one card) and the Arc B580 is not, which agrees with main's word that it is PC 2's eGPU; the kits row, the bench notes and identity-check's card-free PC 2 text stand on that. The locked PC 1 jobs stay parked (the 5080 full grid, the third 5090 pass, SM-sparse, the microbench and packs knee states, the two Ember tunes, the hot-table ldcs rows); the lock-free CA4 rows queue after the v5 bench on the same "slot closed". THE 00:00 BST READINGS, THE OTHER THREE (read by the crypto lane from each branch's report on the mirror at 01:03 BST; the roll-up section 13 of in-house-pass.md at crypto-engage c84ba51b with adv-accept's reading at 1b4e07ff; all nine branch tips read back from the mirror and igneum-pow IDENTICAL to 017e7037 on every one: adv-mixer d2ba3134, adv-mixer-2 2a632579, adv-mixer-3 4ebe2455, adv-cache 555c3e42, adv-cache-2 9384ee09, adv-cache-3 9452c0bf, adv-accept a7c49399, adv-accept-2 92168536, adv-accept-3 0c150e3c). adv-accept-3 (exhaustion or steering of the draw), tip 0c150e3c, every sweep ended 23:05 BST, about 3.3 box-hours, 0 pod-hours: Q1 exhaustion BOUND (per attempt accept 0.323, reject 0.677 ((a') 0.568, (a) 0.079, (b) 0.022, dynamic parts about 0.009), geometric histogram, P(exhaust) 0.677^256 = 4.6e-44, 0 of 16,337 seeds at the cap); Q1b the last resort FINDING (correctness; the mirror fired at cap 256 byte-identically; of 3,000 last-resort programs the real rule rejects 271, 9.0 percent: 251 by (a), 14 by (b), 6 by (c) distinct sum; handed out unchecked; unreachable; closed in class v5 by 8ca66afa, AP-F8-3); Q2 steering BOUND (45 of 48 planted rows fired, the real rule rejects every effective plant by (a'); 975 seeds at the first part, min ratio 0.998, 18 of 18 chain re-draws equal); Q2b the price of a seed property at 1 in 10^6 tries is a shadow block with 38 multiplies of 256 against a mean 74, about 2 to 3 percent of the f = 1 chip's energy per hash, the load critical path worth nothing at the memory activate ceiling; Q2c the 256-unit ratio is noise as a selector; Q3 program id FINDING (documentation: the "sub/" || 3_le16 suffix omitted from program.json and spec 1.4.6; a text-derived implementation computes 30956569d8f3d8d7 for Devnet 3 against the pack's fce15bf61030be57; 0 collisions over 10^7 pairs; fixed as AP-F8-4 at da2fc101); Q4 determinism DONE (the (c'') f64 compare never disagrees with the integer rule on any of the 2^20 + 1 values, margins 0.32 to 0.44 counts; a second interpretation agrees on 5,748 of 5,748 verdicts of 1,792 seeds); Q5 the era lever BOUND (400 eras, no stride under NAF weight 7, all 31 rotations, 354 distinct interleaves; epoch 0's accepted attempt is 3 under every era, so the era moves the address map, not the program). Partial named: the steering sweep at 975 of a planned 10^5 seeds (about 8 box-hours more at 32 cores). adv-cache-2 (the hot-set attack), tip 9384ee09 at 23:52 BST, about 2.2 box-hours by wall times threads over 96 (the boxes at load 400 to 600 for the first two hours), 0 pod-hours; two shards still queued at 00:00 (lines-2e30-s2c, warps-devnet-2e25-v2), named partial: Q1 the line index PASS (pooled 16 days; segments max +4.84 sigma against a control's +4.24, lines +5.61 against +5.35, chi2/dof 0.99937, top 0.1 and 1 percent of lines 1.0003x and 1.0002x of control; the 2^35 + 3 x 2^33 census all PASS; 0 mirror mismatches); Q2a the real programs PASS on the hot-set test (devnet at 2^26 1.0002x; Devnet 3 at 2^26 items 1.0071x, lines 1.0000x) with the FINDING at Devnet 3 site 0; Q2b all 64 programs done, every one clear on the hot-set test (items 0.9993x to 1.0075x of the windowed control) but the site class as recorded above (13 of 27 drawn-era over 1.04x, 8 over 1.2x, worst 1.7451x; the v5 floor refuses 0 of 61; AP-F8-6); Q3(1) steering by t PASS (worst cell 3.95 sigma in 2 x 2,112 cells); Q3(2) the weak-day scan PASS over 16,384 days (2^30 derivations in 707 s; worst per-day max bucket +8.13 sigma against the control's +7.78; the plant fired at +1,090); Q3(3) the window layer: the exact distribution matches the 4,096-program census to four digits (top quarter mean 0.3382, top half 0.5811), with a FINDING against the chip model's table: the f = 0.25 and f = 0.5 partial-store rows overstate the recompute share by up to 1.8x at f = 0.5, the full-store (f = 1) verdict unchanged (a correction owed in chip-model-v3's partial-store rows; no served number rests on f under 1); Q4 the prices: the only measured excess over f is the window layer's and the line reference multiplicity (a hottest-lines half store hits 57.8 percent instead of 50 at a higher miss cost than the stride). adv-mixer-3 (the statistical distinguisher and round margin), tip 4ebe2455 at 00:41 BST, still RUNNING at 01:03 (Q3 and Q4 at k = 8 on day 20729, queue 07 in the pool, the SAT ladder at k = 3 timed out; the total box-hours the lane's to give): Q1 the exhaustive round-0 line-index census over all 2^32 t PASS to k = 8 on days 20729 and 20733 and at k = 2, 3, 4, 8 on 20730 (z within 1.5); Q2 single-bit avalanche FINDING at k = 1 (354 and 266 holes, 130,000 cells beyond 6 sigma, the known one-application diffusion), PASS from k = 2 at 2^24 (0 holes, worst z under 5.3 through k = 8); Q2b the t-bit avalanche the same shape; Q3 differential multiplicity over 576 low-weight differences FINDING at k = 1 (695 and 537 deterministic output bits), PASS k = 2 through 7, k = 8 running; Q4 and Q4b linear correlations PASS from k = 1 (worst c 0.00046 to 0.00062, z under 5.1); Q5 rotational-XOR PASS from k = 1; Q6 SAT: k = 1 SATISFIABLE in 137 s (t = 0x49880000 verified through the real code), k = 2 and 3 TIMEOUT at the one-hour cap. The round margin as it stands: no statistic survives 2 of the 8 applications between reads; a chip gets nothing from the k = 1 findings because every read sits behind 8. The lanes' own lines go into section 13.1 as they arrive. THE LANES' OWN 00:00 LINES (adv-accept-3 and adv-mixer-3, 01:0x BST, in section 13.1 of in-house-pass.md): adv-accept-3's P(exhaust) refined to 1.0e-43 per epoch seed from 62,240 full-rule candidates plus 3.0e6 static candidates; Q2 steering BOUND over 19,975 full-rule and 1e6 static seeds, no property buying over about 1.03x at 1 in 1e6 tries; a second documentary FINDING: an implementation written from the spec text (not the code) at 017e7037's spec differs on 264 of 400 epoch programs, the same text-against-code gap as the id suffix (the audit lane's rewrite 8b834634 with spec_readback.rs is the fix; the proof that it closes this is a re-run of the text-derived implementation against the rewritten text, asked); a plant note: the floor-0.97 known-failed variant did not fire because the (c'') ratios are bimodal (accepted 0.989 to 0.999, rejected 0.814 to 0.966), replaced by a single-pass (a) variant that did; 3.3 box-hours, nothing running. adv-mixer-3: about 3.0 wall-hours of sweep plus 4 single-core CaDiCaL hours; the round margin stated as 6 of 8 applications between reads and 70 of 72 per item on every measured statistic, the k = 1 effects one mechanism (the lowest-set-bit trail through one application, dead once both addends carry a difference), nothing saving one application against 9,360 ops per item; still running at 4 cores on build-1 (2^27 and 2^28 avalanche rows, finish about 03:00 BST) and the day-20733 SAT ladder on build-2 (about 03:45 BST); not attempted: multi-bit linear masks and a MILP trail bound. adv-cache-2's own line still owed. ADV-CACHE-2'S OWN LINE (01:05 BST, tip 3f50d6c4; section 13 of in-house-pass.md now carries every lane's reading in its own words plus the verified roll-up): the drawn-era prevalence read on the SAME 32 base programs is 2 of 32 under the devnet era against 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), the mechanism carried by rotl(x times M, R) into the item index unless R is 29 or 30 (2 of 31 rotations), with a sub-class of warp-uniform sources once in 16,000 warps; the window layer's price restated: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the chip model's partial-store rows overstate the recompute share by up to 2.3x on these programs, the f = 1 verdict unchanged (the correction to chip-model-v3's partial-store rows is the coordinator's next commit); partial named (the drawn-era windows census of 4,096 and one line shard in the pool); the longer-pass line: the biased-site rate per era in closed form (the R in {29, 30} rate 2 in 31) and a 2^28 read of the worst site. Nothing of the pass stands between the pool and a higher-class job except two pre-emptable shards on box 2. THE SPEC-TEXT RE-DERIVATION ORDERED (01:06 BST): adv-accept-3 re-derives its 400 epoch programs from the rewritten spec text alone at master 8b834634 (1.4.3 to 1.4.6 grown from 79 to 198 lines with the constants and pinned-ids tables), lease pool 16 --min 8 class adv, row Q4c in its report; the expected reading 0 of 400, any non-zero naming the diverging sentence to the audit lane; the proof that AP-F8-5 closed the text-against-code gap. THE CHIP MODEL'S PARTIAL-STORE ROWS carry a second correction (section 5, 8 October 2026) from adv-cache-2's window-layer reading: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the uniform-store rows overstate the recompute share by up to 2.3x; the f = 1 row, the SRAM column and the full-store verdict unchanged, no served number on f under 1. THE CLASS V5 PACKS TEST ON THE MERGED TREE (the v5 lane, 01:0x UK): the job ran on box 2 the minute two adv-accept holders ended (65 cores; no lease fault, plain starvation before); 19 passed, 1 FAILED: v5_pack_is_the_v4_program_over_the_state_leaves (tests/packs.rs:977), the byte-for-byte compare of every pinned pack file with the crate's export. The ids are EQUAL (v4-genesis exports a217c7f698880830 as pinned; the state tag rides in master's recipe form unchanged); what differs is the program_id_derivation TEXT in program.json, which master's export (the hash lane's AP-F8-4 read-back form) now writes as "... || attempt_le32 || 'sub/' || sub_version_le16" for generator 4 while the pinned packs carry the pre-suffix wording. Disposition: the three pinned packs re-exported from the merged crate (text only; the ids, kernel texts, leaves and the fingerprint 82b19cbde8557ea5 must come out byte-identical, proved by the same test); the CLI rebuilding on build-1 from 51aa5bc4, the export from the box's IGSD1 streams, the packs test and the full suite on box 2 at 16 cores, then the push; readiness about 01:35 UK. The 0.3.24 kit zip (packs-ca3-v5-20261007T221001Z.zip) carries the old derivation text in its program.json files: a text field only, no id, kernel or fingerprint change, so the kit stands for 0.3.24 and the shipper is told; the re-exported packs go in the next kit. THE ONE 0.3.24 KIT, NAMED for the shipper (01:1x BST): packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 the pin pairs with; the fleet keeps placing it. The 23:11 zip packs-ca3-v5-20261007T221001Z.zip (sha256 4aaf9b9e..., /srv/artefacts/packs/ on build-1, from class-v5 7f58af97) carries the same packs, ids, kernels, leaves, fingerprint and derivation text and differs only in the merged kit host code and scripts beside the packs; it is the bench lanes' kit for the fingerprint jobs. The coordinator's earlier line naming 4aaf9b9e as the 0.3.24 kit was wrong and is corrected here. THE SPEC-TEXT READ-BACK RUNNING (adv-accept-3's Q4c, 01:11 BST on build-2, lease pool 16 --min 8 class adv): the same 400 epoch seeds re-derived from the spec text at master 8b834634 alone (1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7, 1.13.1; a fresh text interpretation), compared field for field with the chain draw; the count about 01:21. One sentence already named divergent before the count: 1.4.6 part (c) cites dataset_elem(idx, S[0], S[1]) "of verify.rs" without stating its six operations, so part (c) cannot be computed from the text alone and the derivation takes that one function from the crate; the audit lane is to state the closed form's six operations in the text or the constants table, else 1.4.6 stays code-dependent on that line. A NINTH LIVE HOT SET (adv-accept, 01:12 BST): seed 228763 (id 2c4be0f6dc44c423, stand-in 0.9820) at 2^24 (X at 0.1 percent +0.118, 1.82x the window model), its single hottest item 0xe2cc96 at 1,218,380 reads, 0.057 percent of ALL reads, the largest single item of the pass (40x 100767's), from a NON-saturated source r0 at site 9 (the sel register), saturated-source share 0.000: the third shape at scale, a value-level concentration neither (c') nor a saturation test can see by construction; its 2^20 ratio against the 0.995 floor lands in minutes and decides whether the floor's instrument reaches it (if missed, the exemplar for the next class's non-saturated case). 638990 reads 1.51x beyond the gate with one item at 0.027 percent (r0, no saturation), no hot set; 623492 clean. Tally: 9 hot sets in 37 tail seeds against 0 in 20 random, 269,250 programs drawn; the price unchanged at 1.002x (0.27 percent of reads on 1 MB; one item 64 bytes). The public sentence's "eight of eight" moves to "nine of nine" or gains the first miss when the ratio reads. THE FLOOR REACHES THE NON-SATURATED SHAPE (adv-accept gap-tail3, 01:13 BST): seed 228763 reads minimum site 9 at 0.9809 at the 2^20 sample, the lowest of the pass, REFUSED; 638990 site 2 at 0.9872, REFUSED; 623492 (clean live) site 0 at 0.9922, REFUSED, a seventh false refusal. Final tally over everything the lane read at 2^20: 9 of 9 live hot sets refused (0.9809 to 0.9919), both single-item programs refused, 7 clean-live programs refused and 1 passed among the 12 deepest 256-unit seeds, 3 mild residuals missed at about 1.0004x. The reading: the distinct-index ratio reads any few-item concentration whatever its source, saturated or not, and misses only the diffuse era-stride excess; the class v5 floor closes the hot-set class entire at the 2.4 percent clean-rejection cost; the next class's value-level test is for the diffuse class alone. The public sentence reads "nine of nine hot sets refused" from here (the v5 lane's follow-up cfce57ea rides its push; AP-F8-1 on master updates with the next record commit). THE FAST-TIME GATE ON dfbd1e10: SUMMARY PASS (cross-0324-dfbd1e10) at 00:12:57Z on 8 October (01:13 BST), the shipped re-cut's binaries (igneumd 4870ccf2..., igneum-miner aa8c2978..., igneum-pow 1c420786), build-1 under lease pool class v5, 23:58:56Z to 00:12:57Z, every check green: rung 1 by signal at epoch 6 (00:05:37Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (00:07:46Z, 4 of 4, 9,985 bps), 12 of 12 ids equal to the CPU verifier's, the stale node 95 of 95 refused, the restart step across the boundary on a kept datadir resynced in 36.2 s with the catch-up done after 11 s (4 IsInIBD refusals of its own miner during it, 0 of its blocks accepted), four sinks equal at 661, 0 PoW rejections on the honest nodes; record on v5-fasttime 0a09eb78, docs/design/class-v5-harness/fasttime/cross-0324-dfbd1e10.json. Every gate on the pin is green; the move waits on the pairs on the dl host, the last FETCHED plus ten, and the F9/F1 interim read. THE RE-EXPORT READ (the v5 lane, box 1 with the merged crate ac285733): the three pinned packs' only difference was program.json's program_id_derivation text (generator 4 now "|| 'sub/' || sub_version_le16", generator 5 the class recipe "igneum-program-rw/ ..."); ids, kernel texts, leaves.bin, vectors and the fingerprint 82b19cbde8557ea5 byte-identical; the pinned packs carry the merged text; the full gate and the full igneum-pow suite with the packs test and spec_readback running on that tree, the push and commit string about 01:45 UK; main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2 at class-v5 b5d6368d (nothing with eight of eight reached the mirror). AP-F8-1's two eight-of-eight lines on master move to nine in this record commit. THE MOVE'S SOURCE (the shipper's ruling at 01:05 BST, corrected to this record at 01:1x): the 02:00 BST move does not wait on the build-server lane's pairs; that lane is dark (nothing published since 23:05 BST, nothing answered since 00:17), so the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair at /srv/artefacts/0324-dfbd1e10/node-lane on build-1 (igneumd 4870ccf2, igneum-miner aa8c2978, the pair every gate ran on, native glibc 2.39 on every fleet box), the way dn3-g1 and g2 moved at 22:30; the fleet's puller fetches from build-1, not the dl host. The move waits on the fleet publishing the dfbd1e10 move file and naming the minute (asked 01:05) and the F9/F1 interim at 01:55. The hive and the Windows pairs are the dark lane's loss for tonight unless main gives the shipper the word to build them (asked 01:06); the Mac entry publishes at the minute regardless; if the fleet has not published the move file by 01:40 BST, main and the coordinator hear it with the clock. THE PC 1 LOCK VOID, THE V5 AMD BENCH PUBLISHED (the hash lane, 01:1x BST): the shipper's 0.3.24 host job was never published to the jobs file, so the slot was void (the shipper's "slot void" at 01:05 BST); the v5 kit fetch landed on both PCs at 00:12:06Z (919,273 bytes, sha256 ok); run-ca3-pc1-v5-amd-bench-20261007 published 00:14:19Z (the 9070 XT by name, about 3 minutes, lock-free), its start line printing app_version, so the 0.3.20 or 0.3.23 reading of PC 1's app comes with the fingerprint; PC 2's Arc job needs only the shipper's "PC 2 clear". PC 1's app had NOT taken the 0.3.23 kit as of the last reads (every job log through 21:46Z app_version 0.3.20; the install folder's exe igneum-app 0.3.20, mtime 12:24:42Z, sha256 0443ae17...). The update-return lane (a22d765a2e0355a9f) last spoke at 23:0x BST: the helper workaround for 0.3.20 scripts (truncate cmd.txt, restart the task, wait for helper.alive, then write; or four leading " dev " padding lines), the locked jobs held as they are, power-helper-24 b9a72b9b merged into release-0.3.24 (daa7427b: a silent change becomes a logged line, the helper writes its exit reason), install-close-23 4ad6c199 for 0.3.23's take 3, the re-probe job when PC 1's app has taken the 0.3.23 kit; nothing since. THE SPEC-TEXT READ-BACK PASS (adv-accept-3 Q4c, 01:11 to 01:15 BST on build-2 at 16 cores; report section 6.5 on build/adv-accept-3, log 983-textderive-8b834634.tsv, pushed): the spec text at master 8b834634, implemented fresh without the crate's generator or rule, reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences (every instruction, the chosen attempt, the id, the rejection sequence); the 264-of-400 divergence against the text at 017e7037 is closed, so AP-F8-5 reads fixed on a measurement. The one remaining gap: 1.4.6.4 names dataset_elem "of verify.rs" without its six operations, so parts (c), (c') and (c'') still take that function from the crate; the audit lane's one-sentence closed form (asked 01:1x) closes it, and the read-back re-runs on the new text. THE AMD CLASS V5 FINGERPRINT (PC 1's RX 9070 XT, gfx1201, beside the miners, lock-free): 82b19cbde8557ea5 at 01:16:14 BST, equal to the kit e6c088bb's on Metal, Apple OpenCL and CUDA, self-test PASS, the v4-genesis control 892b6d55a7ddcfcb PASS; the 0.3.24 kit stands on four platforms; Intel waits on PC 2 (held until main's word, since the 0.3.23 take 3 never ran there); PC 1's queue continues with the CA4 unlocked rows. The kits row reads: Metal, Apple OpenCL, CUDA, AMD equal; Intel not measured tonight. THE UPDATE-RETURN LANE'S THREE READINGS (01:17 BST, from the live manifest and the intake): (1) 0.3.23 take 3 (install-close-23 4ad6c199) never reported; the live manifest igneum-app-latest.json reads 0.3.23 published 20:37:44Z with platforms = {mac} only, NO Windows entry, so neither PC has anything to take through its update path; PC 2's app run is still take 1's relaunch from 21:08:43Z (997 uploads, last 00:16Z); (2) PC 1 will not take 0.3.23 unattended tonight for want of a Windows entry; its run win-ae432dc7-20261007-160110 (0.3.20) never restarted (2,376 uploads, last 00:16Z), mining 18.96 MH/s on the 9070 XT; when a Windows entry is published the 0.3.20 engine's OTA takes it with no hand; the 21:41:32Z helper.ps1 write was not the prompt path (0.3.20 writes that file unconditionally), so no screen is owed in the morning for it; (3) the re-probe job (relay/playbooks/pc1-helper-reprobe.ps1 on power-helper-24 69f3c733) waits only on PC 1's exe becoming 0.3.21 or later; the 0.3.20 workaround is cleared to run tonight as a lock-free job so the locked grids go ahead: per grid job, before the first command, empty sweep\cmd.txt, Stop-ScheduledTask and Start-ScheduledTask 'Igneum Power Helper', wait until helper.alive is within 4 s, then write the lines with climbing sequences (in 0.3.20 the skip is the line count at the helper's start, fixed for its life); the helper idle-exits 20 minutes after its last command and the next start must begin over an empty file again; never pad after a command. The coordinator's order to the hash lane on it: the locked grids proceed in the earlier order (the 5080 full grid, the third 5090 pass to the driver's floor, SM-sparse, the two Ember tunes, the hot-table ldcs rows), each with its restore step, under the no-prompt rule; a Start-ScheduledTask that reads the 0x800710E0 refusal again stops the job and reports, nothing escalates. THE LOCKED GRIDS UNDER THE WORKAROUND (the hash lane, 01:2x BST; commit 24f9858e on the mirror): the three lock scripts carry the cleared sequence (empty sweep\cmd.txt, Stop- then Start-ScheduledTask 'Igneum Power Helper', helper.alive within 4 s with a 60 s cap, then dev + command with climbing sequences; repeated before any write when helper.alive is older than 10 s; a refused start 0x800710E0 or no heartbeat stops the lock path with the text on RESULT lines, nothing escalates; no padding; each grid job ends with rgc through the same sequence and the applications clock read back). PC 1's app_version on the v5 bench's start line: 0.3.20 (no Windows 0.3.23 published, nothing to take). The CA4 SM-sparse job run-ca4-pc1-ca4sparse-5090-20261007 runs since 00:20:40Z on the earlier padded script (unlocked rows first, then its 1,300 knee attempt; about 25 to 50 minutes); then in order on the shipper's acks: the 5080 full grid as run-ca3-pc1-v4-eff-5080-20261007-d, the third 5090 pass (1,100 MHz down), the microbench and the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the 5080 grid's knee and best points to the site audit lane for row 17 as read. THE ATTEMPTS CENSUS COMPLETE (adv-accept row 90, 01:34 BST, 20,000 seeds, closing the partial named at 00:00): 42,711 rejected candidates; (a') 83.5 percent, (a) 11.6, (b) 3.0, (c'') 1.1 (459 candidates), constant bit 0.4, saturated 0.3, (c') 0.05, distinct 0.04, lane-constant and bias 0; per-candidate rejection 0.681, flat across attempts 0 to 3 (the halves agree to a tenth of a percent); accepted-attempt mean 2.136, max 28; 0 exhaustions; P(256 consecutive rejections) 2e-43 per seed. The number for spec 1.4.6: under sub-version 3 the per-candidate rejection is 68.1 percent and the expected attempt 2.1. adv-accept's shards run on in the pool's gaps under the mechanical yield; the box-hours cross 8 later tonight. CLASS-V5 LANDED ON BOTH MIRRORS (the v5 lane, 091a0758 at 01:40 UK): the full pre-push gate GREEN at 71 checks (stamp on 48d38493, the last code change); the igneum-pow suite on box 2 (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs byte-identical to the merged crate's export, so e5a4ac5978462156, 7c54302b487340a1, a217c7f698880830 and 82b19cbde8557ea5 hold under master's recipe form, recheck 2, scratch 7, spec_readback 2); spec-constants 28 rows agreeing; identity grep 0 hits. Carried since 61588347: main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2; the 61-row era reading and the class v5 attempts census on the spec, the page and the ledger; AP-F8-3; spec 1.4.7 and 1.8.6 with the constants and id tables; the AMD fingerprint row; the kits branch and master merged; two corrections the proofs found: master's program_id_derivation text lacked the class v5 rung-0 arm (the v5 packs' text named the class recipe while the id was the plain form; the arm added to the TEXT, re-exported, ids unchanged; a post-freeze change on the class-v5 line, so 0.3.25's pairing, never 1c420786's), and the public-export scrub (the founder's name six times on the page, the zone name in three files; gone). Incoming to the page: the Arc fingerprint, F9 and F1. THE MOVE FILE NOT PUBLISHED (the shipper, 01:41 BST): build-1's /fleet/move.json still names commit 2720d8d2 with the 22:30 BST minute; no FETCHED count, no named minute; the fleet lane (ac055d60427caab99) has answered nothing since its 22:4x report (asks at 01:05, 01:16 and 01:41; its task output last written 22:21 BST, its last action a hand read of dn3-g1's proven share), the second dark lane beside the build-server lane (last written 22:36 BST). So 02:00 BST cannot hold; the 02:53 BST ceiling (DAA 32,400) stands only if a signed move file lands at once and the 34 pullers fetch inside forty minutes; main has the clock line with the two options (wake or replace the fleet lane; or a fourth re-cut from a morning minute, the Mac entry standing down with it). The publish record's shape stands: the Mac entry at the minute (staged, DMG 1aa301cc, both folders, armed); the hive and the Windows pairs on main's word; the pairing 1c420786, 091a0758 0.3.25's. Every other gate on dfbd1e10 green and recorded. THE RUNG-0 ARM CONFIRMED (the v5 lane, 01:4x UK): 987e90e8 touches only Program::program_id_derivation, the text in program.json; Program::program_id untouched (the v5 rung-0 plain-form branch since the freeze); the crate at 091a0758 and 1b5684ec (master 35602b30 merged, pushed 01:41 UK) derives every pinned id byte for byte (packs 20 on box 2 comparing all three pinned packs' files including program_id and leaves.bin; spec_readback 2); the shipper told 091a0758 and 1b5684ec are 0.3.25's pairing, 0.3.24 on 1c420786. THE SM-SPARSE JOB (run-ca4-pc1-ca4sparse-5090-20261007, exit 0 at 00:41:53Z, 1,171 s, the 5090 alone, every fingerprint matched, the Power Helper answering every command on the padded write, the card left unlocked at 2,855 MHz): the SM-sparse reading does NOT exist; the research lane's worker ran its base kernel on every variant row (its race line "race 0 ms variant base" on all 48 rows, no NVRTC compile text), so --bench never honoured --variant sp-w32; the sparse rows equal base in rate and drift in watts with the card's heat only; the rerun waits on the research lane's exe honouring the flag. What stands: a repeat of the efficiency pass at two states, 32 s rows, the card alone: v4 unlocked 137.07 MH/s at 465.5 W (0.294 MH/W), at 1,300 MHz 134.26 at 309.9 W (0.433; 155.6 W back for 2.05 percent of rate); v3 unlocked 136.71 at 331.6 W (0.412), at 1,300 134.03 at 219.4 W (0.611; 112.2 W back for 1.97 percent); the v4 premium 133.9 W unlocked, 90.5 W at the knee; the three power fields agree within 0.2 W on every row (power.draw = instant = average on driver 617.14), which settles the field question on PC 1's side and leaves the 5080's 110 W gap to the fleet's rented card's sampler. Next on the shipper's ack: the 5080 full grid (-d) through the cleared helper sequence, the third 5090 pass, the microbench, the seven packs, the two tunes, the hot-table ldcs rows (kit and job at 292fcc75). THE --variant FAULT FIXED (the research lane, counter-asic-4, UTC clocks on 8 October): 00:44 the fix (a --bench with --variant runs the pinned race and installs the named kernel; the RESULT line carries variant=, sparse_blocks=, block_warps=; a served kernel other than the requested one prints variant_not_installed); 00:46 the known-failed test on build-1 against the real class v4 pack, no card (base: race off, 524,288 blocks of 32, "variant base"; sp43-w32: race on, 43 sparse blocks of 32 warps, the rewritten kernel with the nonces argument and the unit function, 43 blocks of 1,024; PASS; before the fix both read the base shape); 00:46 the Windows exe igneum-worker-cuda-ca4sparse3.exe sha256 0ba97edcd5c46a302a7ff5ddd1bbb1e493ca15f64d0757820ed645972df3bb56, mingw exit 0; the commit after 2d0013d1; the hash lane has the sha, the test's lines and the rerun's job shape (the same 48 rows, the race line per row); the op-mix re-weight stays behind the SM-sparse reading, the served 3.4x standing; the clean efficiency repeat in the file's 20.3a (6.6 pJ per counted op). THE SPEC'S LAST CRATE-DEPENDENT SENTENCE CLOSED (the site audit lane, master 56eebc0d at 01:49 BST, gate GREEN on c2c92eab, 71 checks; spec_readback now 3 tests): 1.4.6.4 states dataset_elem in full (the eight operations, the three constants, 32-bit wrapping) with two pinned vectors (dataset_elem(0x00000fed, 0x9E3779B9, 0x7F4A7C15) = 0x5c7dabd2; dataset_elem(0x0fffffff, 0, 0) = 0x7662c1ec) that spec_readback.rs reads from the text and checks against the crate, so part (c) computes from the text alone (34845c47); 1.4.6.5 names the class v2 figures as class v2's and carries the shipped rule's own census sentence (20,000 seeds, 68.1 percent rejected per candidate, the per-part shares, mean attempt 2.1, max 28, 0 exhaustions, 2e-43). The text-derived re-run on this text is the proof it is sufficient end to end (asked of adv-accept-3). THE MOVE FILE STAGED (the shipper, 01:5x BST): id mdfbd-1, commit dfbd1e10, want_digest b1ba7822, both pair slots on build-1's served tarball dfbd1e10-node-lane.tgz (e59ed0e6), at_epoch 0, signed with the fleet key on the Mac and verified against the fleet's public key in the puller's namespace; the read-back on placing it: the served file's id by curl and the first FETCHED on the relay intake; the 34 pullers fetch inside their one-minute timers (27 MB from build-1), the last FETCHED about five minutes after the file, the earliest minute ten after that. THE REAL LATEST-PUBLISH CLOCK: the file alone halts every miner on the restart, because each box's pack gate PAIR_MINER_SHA16 lacks aa8c2978 and the puller does not carry the file's miner sha into the restart environment; so route (A) also needs one ssh line on each of the 34 boxes before the minute with the fleet's tooling (the fleet lane's, or the shipper's on main's word). Absent main's word by 02:15 BST the shipper stands the Mac entry down under the ceiling rule (no app alone on b1ba7822) and 0.3.24 becomes a morning minute with a fourth re-cut. ROUTE (A) STAGED TO ONE COMMAND (the shipper, 01:5x BST): the gate script r0324/move/pair-gate-aa8c2978.py in its scratch (dry run by default, apply on the literal argument, the fleet's own Box helper and label list, nothing restarted); the dry run read 33 of 35 boxes, every one carrying the old gate list with fb147dd1 last and aa8c2978 absent, no env-last override; unreachable dn3-relay and p2-4090-1b (dead Vast proxies; they fall off at the move and rejoin by the pull); the apply about 90 s for the 33 with each gate read back and counted. THE F9/F1 INTERIM (the attack-pass lane, read at 01:5x BST): 71,292 seeds, 0 exhausted, 0 panics, max attempt 30; F1 0 failures at 2 h 23 min; the move's gate reads clear. On main's (A): apply 02:00, the file placed 02:02, the last FETCHED about 02:05, the minute 02:15 BST; main has the clock. Nothing applies before the word. THE SPEC TEXT SUFFICIENT END TO END (adv-accept-3 Q4d, 01:52 to 01:57 BST on build-2 at 16 cores; report section 6.6 on build/adv-accept-3, log 984-textderive-56eebc0d.tsv, every row equal to its Q4c row): the spec text at master 56eebc0d, implemented with nothing from the crate (text.rs: 0 igneum_pow imports; dataset_elem from 1.4.6.4, its two pinned vectors checked at start), reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences on every field; no sentence of the generator or acceptance sections needs the crate; the documentary finding (AP-F8-4, AP-F8-5) closed in full on two measurements; the lane at its end, 3.35 box-hours in all. F9 AND F1 AT 00:59Z (class v5 at 1c420786, pairing e5a4ac5978462156, build-1): F9 73,691 of 100,000 chain-shaped seeds written, 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; the attempt histogram 23,119 / 15,981 / 10,805 / 7,547 / 5,181 / 3,415 / 2,439 / 1,653 / 1,119 / 744 / 529 / 389 / 258 / 152 / 113 / 72 / 54 / 40 / 31 / 14 / 15 / 5 / 2 / 6 / 2 / 4 / 1 at 26 / 1 at 30, r about 0.69; the 10^5 about 01:30Z (02:30 BST). F1: the 10^5 redundancy census at 2 h 28 min under its lease with no end marker (18 minutes on an idle box; under tonight's load no minute named); its panic path live and empty, 0 failures the honest reading. Both land as record lines, then the board's close per item on sub-version 3 and class v5. AP-F8-5 ON TWO MEASUREMENTS (the site audit lane, commit 116e6055, master 5c77a7ac at 02:05 BST, gate GREEN 71 checks): the row carries Q4c (8b834634, 0 of 400 with one crate function, section 6.5, log 983) and Q4d (56eebc0d, 0 of 400 with no crate import, section 6.6, log 984); the public ledger and the ledger page regenerated; nothing open in the spec or the ledger on the audit lane's side. THE 5080 FULL GRID (run-ca3-pc1-v4-eff-5080-20261007-d, exit 0 at 01:54:00Z, 4,118 s; PC 1's dock card alone, driver 617.14, app 0.3.20, mem 14,801 MHz throughout; every lock through the cleared helper sequence, every command answered first time, every fingerprint matched, clocks reset and read back): the knee as a reading: the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes (v4 71.19 of 71.41 MH/s; v3 71.11 of 71.28) and falls 5.2 percent at 900 MHz on v4 (67.66), where the 75-minute budget ended the grid (v3's 900 and below not taken; the drift check skipped); so the 5080's knee sits between 1,000 and 900 MHz, a third of its 2,963 MHz boost, lower than the 5090's 1,300 (84 SMs at 2,960 MHz have more compute headroom per unit of its 960 GB/s than the 5090's 170 SMs per unit of 1,792 GB/s; the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: v4 at 1,100 MHz, 71.20 MH/s at 146.6 W (0.486 MH/W; 106.5 W recovered for 0.29 percent of rate); v3 at 1,000 MHz, 71.11 at 103.7 W (0.686; 66.0 W for 0.25 percent). The v4 premium 83.4 W unlocked (253.1 against 169.7), 41 W at the best points (146.6 against 105.6 at 1,100). Per tier: a 5080 owner on class v4 locked near 1,100 MHz draws 147 W instead of 253 for 0.3 percent less rate (MH/W up 72 percent) and the shadow's residual cost is 41 W. Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 71.41/253.1/0.282 ; 71.28/169.7/0.420 (sm 2,963/2,977); 2850 71.41/229.5/0.311 ; 71.29/155.3/0.459; 2700 71.41/209.6/0.341 ; 71.29/149.2/0.478; 2550 71.41/193.0/0.370 ; 71.29/134.4/0.531; 2400 71.41/176.0/0.406 ; 71.29/128.7/0.554; 2250 71.41/165.6/0.431 ; 71.28/117.3/0.608; 2100 71.38/157.7/0.453 ; 71.28/112.3/0.635; 1950 71.37/154.0/0.463 ; 71.26/111.6/0.639; 1800 71.35/150.3/0.475 ; 71.24/113.4/0.628; 1650 71.33/151.4/0.471 ; 71.22/109.7/0.649; 1500 71.30/149.2/0.478 ; 71.19/110.6/0.644; 1400 71.27/149.6/0.476 ; 71.16/107.0/0.665; 1300 71.24/147.9/0.482 ; 71.14/107.7/0.661; 1200 71.20/149.4/0.477 ; 71.12/104.4/0.681; 1100 71.20/146.6/0.486 ; 71.11/105.6/0.673; 1000 71.19/149.0/0.478 ; 71.11/103.7/0.686; 900 67.66/137.8/0.491 ; not taken. Throttle reason 0x400 (the power governor) on every row, never the clock lock, so the draw floor of about 147 W (v4) and 104 W (v3) from 1,500 MHz down is the memory system plus idle, not the SMs: the clock lever is spent by 1,500 MHz on this card. The three power fields agree within 0.2 W on every row. The site audit lane has the knee and best points for row 17; the bench table's 5080 row takes "71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", class v4 cost "+83 W unlocked, +41 W at the best points", hive core 1100 (the mem clock unchanged) once the fleet's rented-5080 sampler question is closed. Next on the shipper's ack: the third 5090 pass, the SM-sparse rerun on the fixed exe, the microbench, the packs, the two tunes, the hot table. THE NIGHT'S MOVE OUTCOME (the shipper, 02:58 BST): main's word on (A), (A') or (B) did not come (asked 01:41, 01:50, 01:53, 01:56 by the shipper and 01:42, 01:52, 01:5x, 02:00 by the coordinator); the gate script not applied (the dry run's 33 of 35 the only read); the move file not placed (build-1's /fleet/move.json serves m2720-1, 2720d8d2, the 22:30 minute, by curl at 02:56); no move minute; the stand-down under the ceiling rule holds from 02:15 (the shipper's stand-down line at 02:15 was not sent, its miss, the state unchanged); the Mac entry standing, not published (staged on DMG 1aa301cc in both folders, the live manifest at 0.3.23). A FINDING: build-1's Devnet 3 seed (the process on 26631 with JSON RPC 27632, the node lane's DAA reader) is DOWN (no such process; node1-dn3 26671 and the observer 26651 run on 2720d8d2; the node lane's 0.3.24 reader on 28690 runs but answers no DAA by the envelope tried), so the node lane's DAA reads since 25,169 at 00:52:38 BST may have stopped with it; at 1.0 DAA/s the DAA passed 32,400 at about 02:53 BST, the 39,600 floor is lost, and the fourth re-cut is from a morning minute main names (before 12:50 BST, or the three heights move with the floor). Every Devnet 3 node is on the 0.3.23 pin 2720d8d2, digest ba75bf6f (the 22:30 move; dn3-j1 behind its proxy unverified since); nothing of 0.3.24 is on any box or in any manifest. The night's 0.3.24: every gate green on dfbd1e10, the kit on four platforms, the move unmade for want of one word and two dark lanes. THE ATTACK-PASS BOARD'S CLOSE (lane (d), 01:58Z on 8 October; record docs/analysis/attack-pass-2026-10.md on the mirror's attack-pass; box-hours approximate: build-2 about 7 h, build-1 about 9 h plus about 6 h of F6 batches and F2 solvers earlier in the day). F9 so far: 89,301 of 100,000 chain-shaped seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 20: 20, 21: 6, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1; r about 0.69), three chunks on their cores to about 02:20Z; F1 the 10^5 redundancy census at 3 h 22 min on 17 threads, healthy, no end marker, 0 failures on its live panic path. The board: F1 shadow redundancy PASS on sub-version 3 (max 5.078 percent at honest-compiler parity; AP-F1-1 on the v5 list at 3.0 percent), running on v5; F2 mixer round margin PASS effort-bounded (no trail under weight 20 to 24 at 2 applications, 29 to 35 at 3, 39 to 47 at 4), not re-run on v5 (the mixer unchanged); F3 chained cache j+1 PASS, not re-run; F4 weak-day census PASS on v4 on the DSP-bound metric with AP-F4-1 reconciled with adv-mixer-2 (median 226, 15 days a century, worst 2050-04-28 at 1.113x), on v5 PASS at 8ca66afa (0 of 2^24 days over 1.1x on both metrics, AP-F4-1 FIXED-AND-PASSED); F5 chip-model sweep FIXED-AND-PASSED (the F2 hour skipped by decision), not re-run; F6 verifier worst case PASS (worst of 10^5 at 8.708 ms half-core; O-1.14 closed, i7-9700K 6.334 ms), not re-run; F7 era draw PASS on all three (0 of 6 re-rolls), not re-run; F8 uniformity FIXED-AND-PASSED on sub-version 3 (60 of 64 under 1.2x; AP-F8-1, 2, 3 closed), PASS on v5 (61 of 64, worst 1.50x, the residue p4, p8, p10; p34 under); F9 edges, hot set, grinding PASS on sub-version 3 (34 of 105,064 edges bounded; grinding +0.004 percent), the exhaustion count running on v5; F10 ladder signal PASS, not re-run (node rule). Findings of the pass, all in-house: AP-F1-1, AP-F4-1, AP-F5-1 (the X9), AP-F8-1, AP-F8-2, AP-F8-3; two operating hazards fixed (AP-H1 the box clean, AP-H2 the shared binary path). The open tail (p4, p8, p10, and p34 on sub-version 3) is named in the public report; no outside party holds it (the attack-pass lane's close wrote "disclosed to the firms", stale wording from before the in-house ruling; its record file is to say "named in the public report"). THE SEED'S DEATH AND THE DAA NOW (the node lane, 03:0x BST): build-1's Devnet 3 seed log /home/build/dn3seed.log ends at 01:09:05Z at DAA 29,732 mid-stream with no stop, shutdown or panic line, so it was killed abruptly (it ran under nohup from a shell, not a unit; no journal names the killer; the OOM record needs sudo the lane lacks); its datadir /home/build/dn3seed/igneum-devnet-3/datadir is intact (13 GB) and it stays down until the shipper says; the lane's reads 25,169 at 23:52:38Z and 28,906 at 00:55:09Z came from it while it lived. The DAA now from node1-dn3 on 28670: 32,659 at 01:57:50Z (the observer 32,660), both on 2720d8d2; the chain passed 32,400 at about 01:53Z, 39,600 lost. The fourth cut in one line: the script on release-0.3.24-node reads the DAA from 28670, sets the floor to the morning minute's publish DAA plus 7,200 rounded up to the next 3,600, commits, pushes both mirrors and dispatches the gate set (about 20 minutes to the pin line, then the fast-time pair about 14); the latest minute before the three heights move with the floor is about 11:50Z (12:50 BST), where the floor reaches 79,200; nothing is cut until main names the minute. A morning item for the box owner: a process on build-1 was killed at 01:09:05Z without a log line while the box carried a load of 400 to 600; the killer (OOM or a sweep's cleanup) is to be read from the journal with sudo before anything long-lived runs there again under nohup. THE BENCH LOG ENTRY (the hash lane): docs/bench-log.md "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080" (both cards' full tables, the knee per card, the best MH per watt points, the premiums at the lock, the lever's limits, the job ids and clocks, the rented-5080 watts note) on the mirror's master as merge 773b93a8 at 02:04:47Z (commit 11c698ad); the audit lane writes row 17's sentence from it. PC 1: the third 5090 pass run-ca3-pc1-v4-eff-5090-floor2-20261007 (1,100 MHz down to 300) since 01:57:03Z, about 28 minutes; then the SM-sparse rerun. ROW 17 AND THE 5080 BENCH ROW (the site audit lane, master 2c5c7f52 at 03:19 BST, gate GREEN on 6eb6fd9b, 71 checks): docs/evidence.md row 17 carries both cards' efficiency passes from the bench-log entry (the 5090's knee, best points and premium; the 5080's 71.41 MH/s at 253.1 W unlocked, 71.20 at 146.6 W at 1,100 MHz, v3 at 1,000 MHz 103.7 W, the premium 83.4 W to 41 W, the knee between 1,000 and 900 MHz, the per-tier reading, the Ember Tune lever), a what-moved table for 8 October, /evidence rebuilt (865a0a5e); site/miner-bench.json's RTX 5080 row states the team's pass as the card's figure ("71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", "+83 W unlocked, +41 W at the best points", hive core 1100 with the memory stock, driver 617.14, the bench-log entry as the source) and keeps the rented-fleet sampler reading with its 110 W gap as the open question; /miners rebuilt at 35 rows (6eb6fd9b); 0 identity hits; nothing deployed, the deploy the morning hand-off. The design pass on ca3-coord (015cc839) now sits behind this master and rebases onto it before its own landing on main's word. THE DESIGN PASS REBASED (the coordinator, 03:2x BST): ca3-coord rebased onto master 2c5c7f52 as the three site commits only (f5b7140c the design pass, 8cc4cbc6 the phone grid, 9ad3fdc9 the six-column row; the two commits already landed through the record branch skipped), site/miners.html rebuilt at each from the merged miner-bench.json so the page carries the 5080's new row ("71.4 stock (71.2 tuned)") under the design; the diff against master is build.mjs and miners.html only; pushed to the mirror (pre-push GREEN); it lands on main's word after the captures, one gate run. ADV-MIXER-3's LINE (read from its report at tip e02297ae, 03:18 BST): queue 17 finished on build-1 at 01:3x BST; Q2 single-bit avalanche at 2^27, k = 2 and 3 on day 20729: 0 holes, 0 cells beyond 6 sigma at band 0.00026, PASS (the k = 1 finding stands as the single-application diffusion); Q2b t-bit avalanche on day 20733 at 2^28: 0 cells beyond 6 sigma at band 0.00018, PASS (k = 2, 3, 4 on 20729 at 2^28 the same); Q3 at k = 8 NOT run (killed at 20:20 BST under the lease rule, not re-queued; k = 2 to 7 clean with 0 deterministic bits on both days), named partial; Q6 the day-20733 SAT ladder: k = 2 and 3 TIMEOUT at the one-hour cap, k = 4 on one build-2 core since 03:05 BST, its cap about 04:05; one pre-emption in its ledger (23:58 BST, 21 minutes of a 2^27 row lost, re-queued); box-hours about 3.0 wall-hours of sweep (build-1 1.9, build-2 1.1) plus about 4 single-core CaDiCaL hours, about 7 with the 20733 ladder. The pass's close with the per-lane table and totals at about 04:05 BST; section 13 on crypto-engage (docs only) merging the current master and going through the gate to the mirror's master so the record cites a master commit. Box 2 at 03:20: adv-accept 87 cores in four shards with three waiting, adv-mixer-3 one core; build-1 load 34, no adv lease. THE DESIGN PASS'S OVERLAP ON THE BOX (the CI steward, 03:33 BST): the 1440 and 390 dark captures of /miners from ca3-coord 9ad3fdc9 taken on build-2 under lease pool 4 (Playwright chromium 1194, the recorded feed; /srv/artefacts/captures/ca3-coord-9ad3fdc9/miners-1440-dark.png 1440 x 4280 and miners-390-dark.png 390 x 9779); the overlap sweep on the same checkout, 390 to 1600 px, light and dark: RED, 3 findings on the change itself: at 1280 px dark and 1600 px light and dark the date span in the lead cell's class v4 line is COVERED by the rate cell (4 of 5 sample points under td.big); 390 to 1024 pass. Cause: the branch's last gate ran on the Mac, which has no browser, so the sweep skipped and read GREEN; on the page the row rule's white-space:nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell from 1280 px up. FIXED at ca3-coord 2ca45001 (the lead cell's rule at the row rule's specificity, max-width 360 px, the class v4 line wrapping with overflow-wrap), rebuilt, pushed; the sweep and the captures re-run on the box before main's word. THE IN-HOUSE PASS'S PATH TO MASTER (the crypto lane, 03:2x BST): adv-accept's box-hours crossed 8 before 02:00 BST and sit near 10 (87 cores in four shards; it sweeps on under the mechanical yield, its reading unchanged); crypto-engage merged master 56eebc0d at 342b6730 (one conflict in funding.md, the pre-public scrub against the rewrite, resolved to the in-house pass with the scrub applied; the founder never named in in-house-pass.md or funding.md), the full gate running, merge-to-master on GREEN; section 13.3: master's igneum-pow moved after the freeze in four files (src/emit.rs and src/generator.rs, the derivation string and its recipe helpers, ids unchanged; tests/derivation.rs and tests/spec_readback.rs), none the hash, so the object the pass bounded is unchanged in every operation the hash performs. THE PASS IN ONE LINE (the crypto lane, 03:2x BST): eight of nine lanes closed, adv-mixer-3 on one SAT timeout (about 04:05 BST), adv-accept sweeping to its 16 box-hour line (9.2 now, the reading saturated at the 1.002x class), adv-cache-2 on one line shard; no break of class v4 sub-version 3; the acceptance's hot-set class closed by the class v5 floor (9 of 9) and its diffuse era-stride class routed to the next class; the weak-day FPGA tail reconciled and closed by a measured redraw rule; the attempts census complete; the spec text proven sufficient by two read-backs; one pod at USD 0.33 in the whole pass, none originated by the lane. THE THIRD 5090 PASS BELOW THE KNEE (run-ca3-pc1-v4-eff-5090-floor2-20261007, running at 02:34Z on its 500 MHz step; the steps lengthen as the rate falls since the batch count was sized from the unlocked rate, about 155 s at 500 against 60 at 1,100; the helper answering every command on the cleared sequence, every fingerprint matched, the 5090 alone). Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 137.09/456.7/0.300 ; 136.79/320.0/0.428 (sm 2,858/2,862); 1100 120.98/275.9/0.439 ; 117.32/198.6/0.591; 1000 110.03/254.9/0.432 ; 106.73/180.2/0.592; 900 97.43/232.7/0.419 ; 94.33/174.5/0.541; 800 86.00/216.3/0.398 ; 83.41/166.6/0.501; 700 75.98/202.7/0.375 ; 73.58/156.4/0.470; 600 65.30/178.2/0.366 ; 63.25/153.3/0.413; 500 53.03/166.5/0.319 ; v3 running. Reading: below the knee the rate falls about 10 percent per 100 MHz on both classes (compute-bound: the shadow and the base program no longer fit the memory wait) and MH per watt falls with it from 1,100 down, so the best point stays where the second pass put it (v4 at 1,200, v3 at 1,300); the driver took every lock down to 500 (the SM clock within 10 MHz), so the floor is below 500 MHz and is not where the optimum lives; the v4 premium below the knee 77 W at 1,100, 75 at 1,000, 58 at 900, 50 at 800, 46 at 700, 25 at 600 (the ALU work shrinking with the clock as the rate does). The exit line, the 400 and 300 rows, the drift check and the restore at its close; then the SM-sparse rerun on the fixed exe (each sparse row reading served= and sparse_blocks=, marked variant_row=FAILED if served as base). F9 AND F1 AT 02:34Z (class v5 at 1c420786, build-1): F9 98,945 of 100,000 seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 18: 39, 19: 19, 20: 24, 21: 8, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1); the last three chunks within minutes of their ends; F1 at 4 h 02 min under its lease, no end marker, 0 on its panic path. The pass record's wording fixed on the mirror's attack-pass at 9474cea8 ("named in the public report"; no "firm", "firms", "escrow", "prize", "paid review" or "Lot" line in the pass record or the ten row records; identity grep 0 hits); the section's merge to master after the two record lines, through the full gate in a detached worktree. THE SECOND SWEEP ON THE DESIGN PASS (the CI steward on 2ca45001, 03:38 BST): the desktop widths pass; RED at 390 px dark only, three findings on the lead cell (the card name and the class v4 line covered by the rate cell), the cause the new 360 px max-width on the phone grid; FIXED at ca3-coord 5158276c (the lead-cell width rule scoped to widths above 1,100 px, the phone grid's lead cell with no max-width), rebuilt, pushed; the sweep and captures re-run on it. F9 PASS ON CLASS V5 (the attack-pass lane, class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, the last chunk written 02:34:54Z): 100,000 of 100,000 seeds drawn through the chain path (era-composed class), 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; histogram 0: 31,454, 1: 21,460, 2: 14,660, 3: 10,263, 4: 7,047, 5: 4,701, 6: 3,297, 7: 2,256, 8: 1,532, 9: 1,027, 10: 702, 11: 509, 12: 365, 13: 216, 14: 153, 15: 103, 16: 80, 17: 56, 18: 39, 19: 20, 20: 24, 21: 9, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1 (first-draw acceptance 0.3145; the mean attempt index 2.185, so 3.185 draws per seed on average; 4,862 seeds, 4.86 percent, at index 8 or above and 255, 0.255 percent, at 16 or above; the 256-attempt cap and the deterministic last resort never reached; the lane's first line read 1.993, a slip it corrected); the exhaustion gate holds for the 0.3.24 move; record docs/analysis/attack-pass/f9-grind.md and the lane (d) section on the mirror's attack-pass. F1 still running (4 h 05 min, 16 cores, 0 on its panic path, no end marker). F9's record on the mirror's attack-pass at 2bcb7e08 (the lane (d) row and f9-grind.md section (d); feature gate GREEN); F1 the one open item before the lane (d) merge to master. THE DESIGN PASS GREEN ON THE BOX (the CI steward on ca3-coord 5158276c, 03:4x BST; build-2 under lease pool 4): the overlap sweep 390 to 1600 px, light and dark, GREEN, 0 findings (the known-failed fixture fired first); the 390 px capture byte-identical to 9ad3fdc9's (the phone shape that passed before), the desktop widths carrying the wrap at 4,640 px tall; the four dark whole-page captures on build-1 under /srv/artefacts/captures/ca3-coord-5158276c/: miners-390-dark.png (sha256 9eec8f27..., 509,158 bytes), miners-1280-dark.png (1b6e636d..., 438,541), miners-1440-dark.png (87387e14..., 445,402), miners-1600-dark.png (d53973cd..., 448,545); the run log /srv/builds/bs-ci-steward/cap-out/run-5158276c.log on build-2. The branch's gate record: a full gate on the Mac skips the sweep (no browser), so the box line is the sweep's verdict for 5158276c; the branch waits on main's word on the look and lands in one gate run. THE IN-HOUSE PASS'S RECORD ON MASTER (the crypto lane): crypto-engage dab0c89f (gate GREEN, 71 checks) landed through merge-to-master.sh --remote build at 03:50 BST as master 00b8cd1b: docs/plans/cryptanalysis/in-house-pass.md section 13 (the roll-up, every lane's reading, the frozen-object note) and funding.md's in-house row and brief, scrubbed under founder-strings-check.sh. AN EXCEPTION OWNED (03:39 to 03:50 BST): the lane's first merge call used the tool's default path, which reads CI on GitHub with gh run list; GitHub is suspended and the rule says never poll it; the tool polled 21 times (each 403, nothing pushed, nothing read); the run's process outlived the task stop and the lane ended it by its pid at 03:50 BST, then used --remote build; the breach is the tool's default against the rule and the lane's for not passing the switch; no state moved on GitHub's side. The coordinator's order on it: merge-to-master.sh's default remote must refuse GitHub while the suspension stands (the CI steward, a gate-side fix with a known-failed self-test), so the rule does not rest on every lane remembering the switch. THE THIRD 5090 PASS CLOSED BY ITS CAP (run-ca3-pc1-v4-eff-5090-floor2-20261007, ended by the 45-minute cap at 02:42:05Z during the 300 MHz step, exit -1, its own finally block never ran; every row taken matched its fingerprint, the 5090 alone): the 500 row's v3 side 51.37 MH/s at 136.4 W (0.377); 400: v4 42.62/152.5/0.280, v3 41.32/131.3/0.315 (sm 390); 300 not taken; no unlocked-end drift check; the driver took every lock down to 400 (the SM clock within 10 MHz), so the floor is at or below 400 MHz. The reading: below 1,300 the rate falls about 10 percent per 100 MHz on both classes and MH per watt falls from 1,100 down (v4 0.439 at 1,100 to 0.280 at 400; v3 0.592 at 1,000 to 0.315), so the optimum stays at the second pass's points (v4 1,200 MHz, v3 1,300) and nothing below 1,100 is worth the knob's time; the v4 premium below the knee shrinks with the clock (77 W at 1,100, 46 at 700, 21 at 400). AN EXCEPTION OWNED: the 5090 sat at the 400 lock (390 MHz, 127 W mining) for four minutes until run-ca3-pc1-clocks-restore-20261008 (02:45:20 to 02:46:30Z, exit 0) started the helper over an empty cmd.txt and sent rgc ("All done"), the card reading 2,880 MHz after; the cause the batch count per step sized from the unlocked rate, so the low steps ran 2.5x longer than planned; the fix in the scripts: the budget check ends the grid with the restore inside the cap, and a probe dev line answered in helper.log counts as the helper up when its heartbeat file stays stale (the restore answered at once with helper.alive stale past 60 s). THE SM-SPARSE RERUN: fetch-ca4-sparse3-exe-20261008 landed 02:49:57Z (sha256 0ba97edc...), run-ca4-pc1-ca4sparse-5090-20261008 published 02:51:15Z on the hash lane's own order (the shipper's acks were for the void host slot); each sparse row reads served= and sparse_blocks= and is marked variant_row=FAILED if served as base; the close about 03:15Z (04:15 BST). THE STEP-BUDGET FIX ON MASTER (the hash lane, merge 9fd8b1d8 at 03:02:03Z on 8 October, commit 0b00c42e, the full gate GREEN): the efficiency pass keeps four minutes of its cap for the restore (every step and lock guarded by the deadline minus four minutes) and sizes each step's batch count from the last rate read for the pack, so a 60 s step stays 60 s as the rate falls; a probe dev line answered in helper.log counts as the helper up when the heartbeat file stays stale (all four lock scripts); the gate check tools/ci/pc1-step-budget-check.sh with the known-failed case first (under the old rule a lengthening grid ends on the cap with no restore; under the new it ends with the restore at 1,500 s of 2,700), wired into pre-push.sh and checks.txt (74 checks). The 5080 Ember tune, the 9070 XT tune pass and the hot-table ldcs rows publish behind the SM-sparse rerun, the microbench and the packs. THE SM-SPARSE RERUN FAILS THE SAME WAY, NOW NAMED (run-ca4-pc1-ca4sparse-5090-20261008, the fixed exe ca4sparse3, started 02:52:48Z): every sparse row served=base sparse_blocks=0 variant_row=FAILED, the worker's own line "RESULT variant_not_installed requested=sp43-w32 served=base race=... variants 1 base only, no race (no other variant named)", no "compile:" text, so NVRTC never saw a rewritten kernel: the variant name is parsed into the request but never added to the race's variant table in this exe; the research lane's emulation test checked resolve and rewrite, not the race list the bench builds (a test of the wrong layer; the known-failed case must be the bench's own race line reading "variants 2"). The rows are base runs; no reading. The queue goes on: the microbench at the rerun's exit (about 03:15Z), the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the SM-sparse question's fourth row stays with the research lane, an exe whose card-free check shows "variants 2" in its race line getting the slot within the minute. CLASS-V5'S F9 ROW PUSHED (the v5 lane, class-v5 1d5e5d23 on both mirrors at 04:04 UK): the page's F9 row (100,000 seeds, 0 exhausted, max index 30, first-draw acceptance 0.3145, mean index 2.185, F9 PASS, the record file named), F1 stated as running with 0 failures (its own commit to follow), the Intel row not measured tonight; master merged twice (2c5c7f52 gated at 5f5e0a5c, full gate GREEN 71 checks at 03:45 UK; 9fd8b1d8 auto-merged and pushed on the hook's light gate, the full gate running on 1d5e5d23); the generated ledger files and the spec-constants check clean on the tree. THE THIRD --variant FIX (the research lane, 03:04Z on build-1 under lease, with the hash lane): the cause of the 02:52Z rows: the race's push looked the pinned name up in the empty order list through the variant lookup, whose on-demand sp path answers for any list, so the sparse variant was "found" and never pushed; the order is now a pure function with membership by name; --list-race prints, with no device, the race order the worker's own option handling builds and whether the rewrite applies: with the job's exact flags "variants=2 names=base,sp43-w32" and "sparse_blocks=43 block_warps=32 rewrite=applied bytes=22261 nonces_arg=1 unit_fn=1" (before the fix variants=1); exe igneum-worker-cuda-ca4sparse4.exe sha256 84846396559004a8df61881c15ecb42fa3fc1010ad99074e0c0b53e81bb1ca3b, the commit on the mirror after 7e9d52a6; the third rerun on the hash lane's queue at the next slot; the two failed runs stay the night's SM-sparse state, the op-mix re-weight held, the served 3.4x standing. THE GITHUB GUARD ON MASTER (the CI steward, tip 2f702735 at 04:05 UK; merges 53773860 and 2f702735, full gate GREEN 71 checks each): fa7e98fe adds the tracked marker tools/ci/github-suspended (suspended-since 2026-10-07T17:02:00Z, removed by main at the cut-over) and two refusals: merge-to-master.sh refuses a GitHub remote (origin by default, or any remote whose URL carries github.com) with one line naming the switch and exit 2 before any gh or git call; the pre-push hook refuses any push to a GitHub remote the same way (the hook reads the remote URL, so a bare git push origin is refused too); known-failed first in both self-tests; the live read on the Mac: merge-to-master.sh --remote origin exits 2, nothing contacted; two follow-ups (9484b988, a08423d4) fix the tool's own --self-test under the real marker. The rule no longer rests on any lane remembering the switch. F1 READ AT 03:05:58Z (the attack-pass lane; the census process itself, not the lease wrapper): state S with 17 threads, 15 cores busy over 45 s, 2 d 19 h of CPU banked over 4 h 30 min of wall, RSS 0.8 to 1.0 GB; computing, not hung. No rows can exist before the end: the harness collects every Report in memory under thread::scope and writes census.csv in one go at the end (no progress print), named as a harness gap in the record. Why fifteenfold against the v4 reference: under class v5 every candidate draw runs the (c''') distinct-index floor over 2^20 (about 1.8 core-s per candidate under the night's load, times 3.2 draws per program, about 5.8 core-s per program before the analysis), so 10^5 programs at 15 busy cores is about 10.7 h of wall, the end about 09:00Z (10:00 BST), nearer the early side as the load fell to 21. Ruling: not killed (a kill loses 4 h 30 min with nothing on disk); the lane (d) section merges to the mirror's master now with F9 and the F1 row reading "running, 03:06Z reading, projected end about 09:00Z", F1's record line in a second merge when it writes; the harness gains a progress line before its next 10^5 run. THE IN-HOUSE ADVERSARIAL PASS CLOSED (04:08 BST on 8 October; an internal adversarial pass, not an independent review; section 14 of in-house-pass.md at crypto-engage c099e818 landing on master through --remote build; every tip read from the mirror at 04:07 with igneum-pow identical to 017e7037 on all nine). Per lane (tip; box-hours; verdict; partial): adv-mixer d2ba3134, about 0.6 plus 1.8 single-core SAT hours, the algebraic structure BOUND, none; adv-mixer-2 2a632579, 0.31, BOUND for every chip, GPU and the verifier with the FPGA LUT-area FINDING (2^-10.8 of days, 15 a century, worst 2050-04-28 at 1.113x) closed by the measured redraw rule, none; adv-mixer-3 981bfff2, about 5.0 wall-hours plus 8 single-core SAT hours, Q1 BOUND (2^32 t uniform at k = 1 to 8, both days and 8 random days), Q2 and Q2b FINDING at k = 1 only and BOUND from 2 to 8 at 2^24 to 2^28, Q3 FINDING at k = 1 and BOUND 2 to 7, Q4 and Q5 BOUND from k = 1, Q6 SAT BOUND (k = 1 in 137 s, k = 2 to 4 timeout), the round margin 70 of 72 per item, partial Q3 at k = 8 not run, multi-bit masks and a MILP bound not attempted, GPU blocked; adv-cache 555c3e42, 0.55, the recompute shortcut BOUND on every row, none; adv-cache-2 91ca5ce1, about 2.25, the line census PASS at 2^35 + 3 x 2^33, the real programs PASS with the Devnet 3 site-0 FINDING, the diffuse era-stride class named (16 of 32 base programs biased under drawn eras against 2 of 32 under R = 29, 8 over 1.2x, worst 1.75x, under 0.1 percent of reads per site, 0 of 61 refused by the v5 floor, AP-F8-6), steering and the 16,384-day scan PASS, the window layer exact and the chip model's partial-store rows overstated up to 2.3x with the verdict unchanged, partial the line shard s2c waiting on build-1 since 23:09 BST; adv-cache-3 9452c0bf, 0.23, the chain-break or skip BOUND on every row with the pebbling optimum under the hold-every-k curve, none; adv-accept c8a98e46, about 9.2 at 03:25 BST running to its 16-hour line, the bypass FINDING confirmed and bounded (9 few-item hot sets in the tail of 408,067 accepted programs, 0 in 20 random, 1.002x at the largest; all 9 refused by the class v5 floor, 7 clean programs falsely refused among the 12 deepest, 3 mild residuals missed), the stand-in gap BOUND, distinguishers BOUND, the attempts census complete, partial the sweep at 408,067 of 10^6; adv-accept-2 92168536, about 9.0 core-hours and 0.3 pod-hours (the one pod), header grinding BOUND by card measurement (+0.09 percent on an A6000) and by tail (3e-7), one 0.1 percent repeat class for the rule's owners, none; adv-accept-3 7826d2b2, 3.3, exhaustion BOUND (P 1.0e-43), the last-resort path FINDING (correctness, unreachable; closed in class v5), steering BOUND (no property over 1.03x at 1 in 1e6 tries), the program id BOUND with the derivation-string FINDING (fixed on master and in the packs), determinism BOUND, the spec text proven sufficient by two read-backs, the era lever BOUND, partial the steering sweep at 975 of 10^5 full-rule seeds. Totals: about 30.4 box-hours of run across the nine lanes (lease waits excluded) plus about 9.8 single-core SAT hours; pod-hours 0.3 on one RunPod A6000, USD 0.33 in all, rented and destroyed by the fleet lane. The verdict: no lane broke the frozen object; the acceptance rule admits two residual classes of address concentration, both under 1.002x to a chip: the few-item hot sets, closed entire by the class v5 floor (9 of 9) at a 2.4 percent clean-rejection cost, and the diffuse era-stride excess the floor does not reach, routed to the next class with its lever; the weak-day FPGA tail reconciled and closed. Already changed by the pass: the derivation string in the shipped packs, spec 1.4.3 to 1.4.6 rewritten and proven text-sufficient, the chip model's partial-store and pebbling baselines corrected, the last-resort path flagged and closed in class v5. Still to come: adv-cache-2's s2c row and adv-accept's final count, appended when they land. CLASS-V5 GATED (the v5 lane): the full gate on 1d5e5d23 GREEN, 72 checks in 347 s (04:1x UK); class-v5 4a162aba on both mirrors at 04:12 UK with the page's F1 line stating the 04:06 reading (computing, not hung; census.csv only at its end; projected end about 10:00 UK); nothing of the lane's pending on a box or a watch. THE LANE (d) MERGE ON MASTER (the attack-pass lane, 399f8c4d at 03:16:35Z, 04:17 BST; attack-pass 4150f66d, full gate GREEN 45 checks on the branch): F9 PASS on 1c420786 (row and f9-grind.md section (d)), the F1 row as ruled (running, the 03:06Z reading, projected end about 09:00Z, 0 on its live panic path, the harness gap named), the in-house wording kept through a conflict with master's older copy, one founder-strings scrub the gate caught on the pass record (the attribution now "The founder's word"). The harness item: the progress line every 1,000 programs and the flushed partial census.csv (temp file and rename) committed on attack-v5-frozen at 18a9c04a, built on box 2, its known-failed test (a 4,000-program census killed by pid at the 2,000 line, 2,000 rows expected) running under lease pool class adv; the verdict and the push follow. THE SM-SPARSE QUESTION, THE THIRD RUN (run-ca4-pc1-ca4sparse-5090-20261008-b on ca4sparse4, 03:23:45 to 03:48:45Z, exit 0): the card-free check on the card's own exe listed the sparse variant (variants=2 names=base,sp43-w32, rewrite=applied), the race ran it, and NVRTC refused the rewritten kernel on every sparse row: "kernel_bound.cu(370): error: identifier "d" is undefined | igneum_hash_bound_unit(d, ou, baseNonc, mas, i, gid);" (the same for sp170, sp85, sp21, sp11), so the race installed base and every sparse row reads served=base variant_row=FAILED. The hash lane's reading to the research lane: the wrapper's call carries the kernel's parameter names cut by one character (d, ou, baseNonc, mas for ds, out, baseNonce, mask), which points at the rewrite's name capture against the PC's CRLF pack text (the Linux check reported a different byte count for the rewritten kernel): the first card test of the rewrite, the finding kept. The base rows a third repeat of the knee pass (v4 137.06 MH/s at 449.7 W unlocked, 134.23 at 301.4 W at 1,300; v3 136.79 at 329.8, 134.05 at 218.0), the card restored each time. The slot returns to the research lane on an exe whose card-free check compiles the rewritten text through nvrtc for sm_120 (on CRLF input). The queue: the microbench run-ca4-pc1-microbench-5090-20261007 since 03:52:14Z (20 probes of 60 s unlocked, then at the 1,300 lock; about 50 minutes), then the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. THE CLOSE'S MASTER COMMIT (the crypto lane, sent 04:55 BST for a 04:14 landing, the forty-minute gap its own): crypto-engage c099e818 (full gate GREEN, 71 checks) landed as the mirror's master 2882352c at 04:14:50 BST; the record cites the roll-up and every lane's reading at 00b8cd1b and the close (section 14) at 2882352c; further landings only for adv-accept's final count and adv-cache-2's s2c row. THE FOURTH --variant FIX (the research lane, 03:55Z on build-1 under lease): the cause was not the line endings: the rewrite's parameter capture wrote the substring length as end minus start where the last index needs plus one, so every argument lost its last character on any input; CRLF would have missed the anchors entirely; the rewrite now strips \r first (the same rewritten bytes from LF and CRLF, 22,266 on both) and the capture is right; the card-free check through NVRTC on LF and a CRLF copy, identical lines: variants=2 names=base,sp43-w32; rewrite=applied; call="igneum_hash_bound_unit(ds, out, baseNonce, mask, iw, gid)" params=6 args=6 names_match=1; nvrtc=libnvrtc.so.12 arch=sm_120 compiled=1 image_bytes=36256; the failed case the 03:23Z card line. Exe igneum-worker-cuda-ca4sparse5.exe sha256 a4550202b301faf22f5329c2ab4fa1c0aa6695dbdaf31c974f316dca2524d7d6, with the hash lane; the commit on the mirror after 3ac5d20a; the slot after the microbench and the packs. The three failures gave three repeats of the knee pass (the v4 premium 133.9 to 145.3 W unlocked, 90.5 W at 1,300 MHz) in the file's 20.3a. ADV-ACCEPT OFF BUILD-1 (04:5x BST, the coordinator's placement rule): adv-accept runs on to its 16-hour line (about 10:15 BST, 10.6 box-hours at 04:54, the reading saturated) in box 2's gaps under the mechanical yield, its build-1 shard ended at the frontier and its waiter withdrawn, so F1's census keeps build-1 (its 10:00 BST projection assumed load 21) until census.csv writes; adv-cache-2's four-minute s2c shard the one exception. Confirmed by lease status at 04:57 BST: build-1 holds F1 (release, 16 cores) and adv-cache-2's s2c (32 cores, its last shard) and nothing of adv-accept's; adv-accept's four holders and waiters on box 2, where the attack-pass lane's flush test waits at 1 free behind them (the same class, no yield case); the coordinator's placement rule: one adv-accept holder ends at its frontier for the flush test (a 4,000-program census, minutes), since adv-accept's reading is saturated and the harness fix gates the morning's F1 rerun class. Done at 04:59 BST: adv-accept's sweep-s05b ended at its frontier at 04:58:50 (46,460 rows kept) and the flush known-failed test took the 16 cores at 04:58:55; the shard re-queued behind it. ADV-CACHE-2 CLOSED (05:0x BST): its last shard s2c ran 04:56 to 04:59 on build-1 (PASS at 2^33 reads, control-level), so the line census totals 2^36 reads over 464 chain days with every statistic at the control's values; final box-hours 2.35 of run (0.08 a duplicate windows run by its build-1 drain, recorded), pod-hours 0; tip bfc3746c on build/adv-cache-2, igneum-pow identical to 017e7037; the biased-site class (AP-F8-6) and the window-layer pricing stand; section 14's row updated on crypto-engage, landing with adv-accept's final count. Eight of nine lanes at their end; adv-accept alone runs to its 16-hour line about 10:15 BST. THE CENSUS HARNESS'S PROGRESS LINE (the attack-pass lane, attack-v5-frozen 18a9c04a on the mirror): the attack-f1 census prints a progress line every 1,000 programs (count, elapsed, running failure count) and flushes a partial census.csv at the same cadence through a temp file and rename; the known-failed test on box 2 under lease pool class adv (binary 14180ef4...): a 4,000-program census killed by pid at the 2,000 line at 04:08:27Z (05:08 BST), census.csv holding exactly 2,000 rows, no tmp file, lease exit 143; PASS (the old harness's known fail zero rows); record f1-shadow.md section 12 on the mirror's attack-pass at c99f147f (riding the F1 record merge); a side reading: 1,000 programs per 286 s on 16 cores, about 4.6 core-s per program, confirming F1's build-1 projection of about 09:00Z (10:00 BST); the running 10^5 census stays on the old binary, every census after it on the new. F1 PASS ON CLASS V5 (the attack-pass lane; class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, 16 cores; census.csv written 04:20Z, 05:20 BST, after 20,774 s of census, 5 h 46 min, earlier than the 09:00Z projection as build-1 emptied): 100,000 of 100,000 programs through the string-seed draw with the (c''') floor; instructions saved min 0.000 percent, mean 0.623, max 4.688 (the worst seed attack-f1/95060: 6,912 to 6,588); chip-view ops saved mean 0.520, max 4.783; programs over 5 percent 0, over 10 percent 0; soundness: differential mismatches 0 of 100,000 (8 random states each), verifier mismatches 0 of 100,000; 0 panics; the histogram of saved in 0.5 percent bins from 0: 55,241, 20,597, 11,762, 9,851, 1,484, 656, 259, 133, 13, 4, 0, 0. Against the v4 10^5 (max 5.078, the AP-F1-1 letter miss): the v5 tip's worst program sits 0.39 points under the 5 percent letter and the top two bins are empty. F1 PASS on 1c420786 by the letter and at honest-compiler parity; the redundancy gate holds for the 0.3.24 move; AP-F1-1's v5 half FIXED-AND-PASSED at this count; record f1-shadow.md section 13 and the lane (d) row, merged to master next. The attack board on class v5 is complete: F4 PASS (8ca66afa), F8 PASS, F9 PASS, F1 PASS; the rest not re-run by rule. CLASS-V5'S F1 ROW (the v5 lane, class-v5 1095eaa8 on both mirrors at 05:24 UK): the page's attack row reads F8 PASS with the known residue, F4 PASS, F9 PASS, F1 PASS on the full 10^5, the rest not re-run by rule; the full gate running on 1095eaa8; nothing else of the lane's open tonight. THE CA4 PACKS ON THE 5090 (run-ca4-pc1-packs-5090-20261008-b, exit 0 at 04:22:54Z, 579 s; the 5090 alone through the installed worker, the lock and reset through the helper, every self-test PASS at both states): the int8 mma tile prototypes' inline PTX compiles under NVRTC 12.8 on sm_120 and matches the CPU reference (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1, mm1430 8e9b7066239d35d1), as do both per-load exports (404cad3b3399f9b3, ee5d7c71180e5ea7), sh256x27 (3d2e8245cc084d07) and the mx8-genesis control (7c28cfb06c5c65a9). Rows (MH/s / W / MH/W), unlocked then at the 1,300 lock: mx8-genesis 137.54/311.0/0.442 then 127.32/213.0/0.598; sh256x27 137.51/462.2/0.298 then 126.93/295.8/0.429; shl256x27 (unsound, an energy reading only) 158.62/472.8 then 145.65/299.4; shl256x27_v2 (unsound) 135.90/448.3 then 126.04/282.9; mm128 137.45/332.9/0.413 then 127.01/217.8/0.583; mm512 137.50/369.4/0.372 then 127.07/235.4/0.540; mm1430 137.45/457.7/0.300 then 126.87/284.5/0.446. Consequences: the rate is memory-bound on every sound pack at both states (within 0.5 percent of the control); the tile premium over mx8 is 21.9 / 58.4 / 146.7 W unlocked for 128 / 512 / 1,430 tiles (0.103 W per tile, linear) and 4.8 / 22.4 / 71.5 W at the lock (0.050 W per tile), so at 1,430 tiles the tile block costs what the ALU shadow costs (151.2 W unlocked, 82.8 at the lock) and the lock halves it the same way; the first per-load export's 15 percent higher rate is its duplicate reads landing in L2 (the unsound construction), the fixed one 1.2 percent under the control. The research lane has the rows for 20.3 and 20.4; the tile class's premium per tile is now a measured number on the 5090 and its Apple cost (35 to 78 percent of rate) the open side. The microbench -b since 04:23:23Z, then the SM-sparse rerun on ca4sparse5, the 5080 Ember tune, the 9070 XT tune pass, the hot table. THE CA4 PROTOTYPES' FIRST SENTENCE ON MEASURED ROWS (the research lane, counter-asic-4 on the mirror after 1428dd3c; sections 20.3 and 20.4): neither prototype beats class v4's premium; the tile block matches it at the same hash rate (mm1430, 11,440 int8 tiles per hash: 146.7 W over class v3 against the ALU shadow's 151.2 W unlocked, 71.5 against 82.8 W at the 1,300 lock, the rate memory-bound within 0.5 percent) and beats class v4's chip edge only at the pessimistic end (about 2.2x against 3.5x), not at k = 1 (2.2x either way), because the 5090's measured cost per int8 MAC (0.091 pJ unlocked, 0.048 at the lock) sits inside what a 5 nm MAC array costs anyone (a claimed test-chip figure), so a chip's k on tile work is at or above about 1 where on ALU work a fixed datapath reaches 0.3 to 0.5; the per-load placement dead as a construction (its energy rows 13 to 14 W under the whole block for the same instructions; the first export 15 percent faster from duplicate reads served by L2). Against the tile block as a class: the verifier (AVX2 0.047 us per tile per unit; mm1430 10.14 ms with the sibling loaded on the box's core, a 0.14 ms miss of the gate; scalar 13x worse; NEON unwritten), the Apple tier (35 percent of rate at 1,024 tiles, 78 at 4,096), the AMD layout unverified. No served number moves; the SM-sparse reading still owed (three failed runs, the fourth exe queued after the microbench); the op-mix re-weight held, the served 3.4x standing. The k column's basis (the research lane, counter-asic-4 after 781cb395): the 1,430-tile point is the one chip-model-v3 5.11's tensor-tile k column was priced at (15.2 set R about 1,430 from the 4090's 0.056 pJ per MAC to carry the ALU shadow's 0.654 microjoules; 11,440 tiles per hash), and the 5090 reads 0.091 pJ per MAC unlocked and 0.048 at the 1,300 lock there, so the column (2.1x at k = 1, 1.6x at k = 1.5) has its GPU-side cost measured at the premium it was priced for (1.067 microjoules unlocked, 0.564 at the lock, against the ALU shadow's 1.10 and 0.652); the Apple cost the open side; nothing served moves. F1'S RECORD ON MASTER (the attack-pass lane, merge 54b896f3 at 04:29:30Z, 05:30 BST; attack-pass 0610892b, full gate GREEN on the branch, pushed on try 2 after a ref race): the F1 row (PASS, AP-F1-1 FIXED-AND-PASSED on v5 at 10^5), f1-shadow.md sections 12 (the flush and its known-failed test) and 13 (the 10^5 record with the worst four programs at 4.688, the attempt histogram, the v4 comparison). Lane (d) complete: F4 PASS (8ca66afa), F8 PASS (61 of 64 at 1c420786), F9 PASS (10^5 seeds, 0 exhausted), F1 PASS (10^5 programs, 0 over the letter, 0 mismatches); both 0.3.24 gate lines PASS on the full 10^5. Box-hours for the lane (d) tail: build-1 F9 ten chunks of 4 cores at about 14,480 s each (about 161 core-hours), F1 16 cores for 20,907 s (93 core-hours), F4 12 cores for 379 s; box 2 F8 64 seeds (the earlier record) and the flush test 16 cores for 3,352 s (15 core-hours, most queued); nothing of the lane's on either box. THE V5 LANE'S NIGHT CLOSED (05:3x UK): the full gate on class-v5 1095eaa8 GREEN, 72 checks in 345 s; the freeze 1c420786 (0.3.24's pairing), the post-freeze line through 1095eaa8 (0.3.25's: AP-F4-1's agreed form, the verified last resort, the record), every proof green on the tip, the attack board on class v5 at F8 PASS with the known residue and F4, F9 and F1 PASS, the kit's fingerprint equal on CUDA, Metal, Apple OpenCL and the RX 9070 XT, the Intel row not measured; nothing of the lane's pending. THE SM-SPARSE READING EXISTS (run-ca4-pc1-ca4sparse-5090-20261008-c on the research lane's fifth exe, exit 0 at 05:12:48Z, 2,219 s; every variant served on the card, served=sp-w32 with sparse_blocks=N, the rewritten kernel compiled under NVRTC on sm_120 and bit-exact, every fingerprint equal to the Mac's; the 5090 alone, the lock and resets through the helper, the drift check equal to the start): a quarter of the SMs (sp43-w32, 43 of 170) holds 98.2 percent of the class v4 rate at the SAME draw (134.58 MH/s at 460.1 W against base 137.07 at 450.8) and 99.8 percent of the class v3 rate at 4 W less (136.55 at 309.8 against 136.77 at 313.9); the draw falls only when the rate falls (sp21-w32: v4 70.75 MH/s at 327.4 W, v3 132.82 at 303.4; sp11-w32: v4 37.34 at 250.9, v3 100.14 at 274.5), and watts minus idle per MH/s never drops below base (v4 2.75 W per MH/s base, 2.87 at sp43, 3.58 at sp21, 4.74 at sp11; v3 1.75, 1.73, 1.73, 2.00); the persistent shape on the full card (sp170-w32) within noise of base; at the 1,300 lock the sparse shapes collapse (v4 sp43 64.3 MH/s at 208 W, compute-bound). CONSEQUENCE: the class v4 premium is the shadow's ALU work itself, not SM-count overhead (150 W at sp43 against 137 W on the full card), so an SM-sparse miner kernel saves nothing and the candidate is dead by the research lane's own rule; the op-mix re-weight stays the open lever, and its served candidate ("2.9x with a core three times better") now has its SM-sparse read: the premium does not move with the SM count, so the re-weight's case rests on the op mix alone and goes to main with that reading. The microbench -c since 05:13:41Z with the pack argument; then the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. RANK 2 CLOSED IN THE CA4 FILE (the research lane, 20.3b, counter-asic-4 on the mirror after 6b21e887): the SM-side power is the work's, not the SM count's (the shadow's ops cost the same on 43 SMs as on 170; idling SMs saves nothing); the number kept: the class v4 premium at sp43 unlocked 150.3 W over v3 at a held rate, equal to the full-card premium, so the premium is the ops' energy whatever carries them; the premium-free floor rests on the operating point alone; the op-mix re-weight's hold is main's to lift or keep, the SM-sparse reading saying nothing against it; the microbench rows still owed. THE OP-MIX RE-WEIGHT: HOLD (the research lane's case for main, 06:2x BST; the SM-sparse row at counter-asic-4 954c4053, section 20.3b): the served sentence stands ("At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block"; the re-weight would move "3.4x" to about "2.9x", the shuffle-and-multiply-heavy shadow raising the chip's k floor from about 0.32 to 0.46). The basis: the re-weight touches only the pessimistic column, a model on both sides (the chip's k floor an estimate from wire and datapath figures, never measured; the GPU's energy per op by family unmeasured until the microbench rows land, the shfl, mul and arx probes being that measurement); the SM-sparse reading says nothing for or against it (the premium is the ops' energy, which both mixes pay); the night's measured finding on bounding k points to the int8 tile block (the same premium at the same rate with a k floor near 1 from the GPU's own tensor core, 0.048 to 0.091 pJ per MAC), of which an ALU re-weight is the weaker version at the same class-change cost (the 95 percent rule, the six gates, a new program stream, Apple paying shfl at 1.91x per op); a reader gains 0.5x on a modelled pessimistic bound and loses nothing measured from the hold; the 2.1x at k = 1 rests on four repeats of the knee pass (82.8 to 90.5 W at 1,300 MHz). The condition that re-opens it: the microbench reading the 5090's shfl and mul rows at or under the add's pJ per op together with a measured chip floor, and then it re-prices against the tile block, not the served line. Main's word lifts or keeps the hold; the coordinator's reading agrees with the hold. THE MICROBENCH ON THE 5090 (run-ca4-pc1-microbench-5090-20261008-c, exit 0 at 05:56:29Z, 2,484 s; the research lane's per-block micro-benchmark, 20 probes ran, 0 skipped or failed, at the unlocked clock and at the 1,300 lock, every probe's checksum equal at both states, the card back at the driver default). Picojoules per counted op as (watts minus the sleep row) over G ops per s, unlocked then at 1,300: the ARX integer path 11.3 then 6.2; int_mul 13.9 then 8.3; mulhi 39.6 then 21.0; prmt 22.3 then 11.5; lop3 24.1 then 13.0; shfl 55.8 then 29.4; fp32 fma 9.2 then 5.2; fp16x2 fma 5.1 then 2.6; int8 mma m8n8k16 4.1 then 2.2; int8 mma m16n8k32 1.36 then 0.83; fp16 mma 3.2 then 1.7; bf16 mma 2.9 then 1.5; fp8 e4m3 mma 1.5 then 0.8; the memory rows per read: L2 chase 2.4 nJ unlocked and 1.4 nJ locked, DRAM chase 10.9 nJ and 8.7 nJ, texture point 2.3 nJ, texture linear 0.19 nJ; the sleep floor 120 W unlocked against 75 W idle (the residency cost, flagged). CONSEQUENCES: (1) the op-mix re-weight's re-opening condition (the 5090's shfl and mul rows at or under the add's pJ per op) is NOT met and is now a measurement: shfl costs 4.9x the ARX op and mul 1.2x, mulhi 3.5x, so the GPU pays more for the heavier mix and the hold on the served 3.4x stands on measured rows, not a model; (2) the tensor-core int8 MAC costs eight times less per counted op than the ARX op the hash is built from (1.36 against 11.3 pJ), the direction a chip cannot beat by as much, which is the tile block's case restated in measured picojoules and the CA4 file's next row. The queue: run-ca3-pc1-ember-5080-20261007 (the installed app's Ember tune on the 5080, the app's own path, not elevated) since 05:57:18Z, about 30 minutes; then the 9070 XT tune pass and the hot-table ldcs rows. A CORRECTION FROM THE MICROBENCH'S TILE ROWS (the research lane, 07:0x BST; counter-asic-4 on the mirror after 954c4053: 15.1a, the corrected 20.3 and 20.4, the first sentence, the ranking): a mma.m8n8k16 tile is 1,024 multiply-adds per WARP, 32 per lane, so a hash does 32 MACs per tile, not 1,024; the lane's 15.2 and 20.3 and the 6 October 4090 figure chip-model-v3 5.11's tensor column was priced on were wrong by that factor. Corrected: the 5090's int8 MAC at the ALU shadow's premium costs 2.9 pJ unlocked and 1.5 pJ at the 1,300 lock (the packs job, 366,080 MACs per hash), the microbench's dependent u8 tile 4.1 and 2.2, the wide s8 m16n8k32 tile at 80 percent of peak 1.36 and 0.83; the 4090's "0.056 pJ per MAC" of new-pow 5.1 is 1.8 pJ. Against a 5 nm MAC array (0.04 to 0.4 pJ per INT8-class MAC, claimed) the chip's k on tile work is 0.03 to 0.3, BELOW the ALU shadow's 0.3 to 0.8: at the same premium the tile block leaves the chip 3.5x to 6.7x where the ALU shadow leaves it 2.1x to 3.5x. So the tensor shadow is the WORSE lever and rank 3 is dead; the 6 October verdict on scheme B stands for the right reason; the coordinator's 07:0x line to main calling the tensor side "the next class's one live direction" is withdrawn by this correction. Chip-model-v3 5.11's tensor column (its premise, a chip's MAC no cheaper than the GPU's, false by 4x to 30x on the public figures) and new-pow 5.1's per-MAC line are to be corrected (the coordinator's next commit); nothing served rests on either. The other rows, pJ per counted op unlocked then locked (the sleep floor 120 and 66 W subtracted; idle 75 and 60): int add-xor-rotate 11.3 / 6.2 (the shadow's 10.8 / 6.4 on the packs job: the two instruments agree); mul 13.9 / 8.3; mulhi 39.6 / 21; prmt 22.3 / 11.5; lop3 24.1 / 13.0; shuffle 55.8 / 29.4 (the card's dearest instruction, 5x the add: the re-weight's GPU side is against it, the hold measured); fp32 FMA 9.2 / 5.2; L2 hit 2.4 / 1.4 nJ per read against a chip's SRAM 0.2 to 0.5 (the hot-table lever dead on the GPU side; the ldcs rows kept as a record); the DRAM dependent read 10.9 / 8.7 nJ per read, the whole card's marginal against the chip memory's 2.0, section 2's floor seen per read. THE NIGHT'S CLOSING SENTENCE ON MEASURED ROWS: nothing on the 5090 reads k above 1; the ALU shadow at the operating point's knee is the floor, 2.1x at k = 1 for 82 to 90 W, measured four times; the two prototypes, the SM-sparse kernel, the hot table and the re-weight are all closed on measured rows. The CA4 file's commits (the research lane): 15.1a at 71fd465b (the microbench row, the residency cost 45 W at the stock clock before any instruction issues), 15.1b the commit after it (the re-weight's re-opening condition not met and measured; for 2.9x to be the honest pessimistic column a chip would have to pay 0.42 to 0.52 of the GPU's cost per shuffle, 22 to 28 pJ for a 32-lane crossbar move, above the wire figure and unmeasured; not a candidate on measured rows); the corrected 20.3, 20.4, the first sentence and the ranking at 71fd465b; the hot-table ldcs rows a record only. The lane closed for the night. THE TWO INTERNAL CORRECTIONS LANDED (the coordinator): chip-model-v3.md 5.11's k-column paragraph carries the dated correction (the tensor-tile column withdrawn; the shipped row unchanged) and docs/analysis/horizon/new-pow.md 5.1's per-MAC prose and the scheme B verdict carry the 32x correction with the reason (a tile is 1,024 multiply-adds per warp, 32 per lane), both citing counter-asic-4-research.md 15.1a at 71fd465b; new-pow's 5.1 table column and its 5.3 chip rows keep their original numbers under the note (the Horizon lane's file; a table rewrite is its own). THE 5080 EMBER TUNE (PC 1, app 0.3.20, 06:05Z, 07:05 UK; run-ca3-pc1-ember-5080-20261007): Tuned 60.3 MH/s at 123 W, 0.489 MH/W, clock_cap 2936, source=climb; read against the clock-lock grid, the app's power-limit climb lands at 0.489 MH/W where the 1,000 MHz lock gave 71.1 MH/s at 103.7 W (0.686), so the core-clock lock is worth +40 percent per watt on the 5080 over the stock climb (and 15 percent more rate): the case for the 0.3.24 core-clock knob shipping. The per-point curve rows were lost to a cast fault in the hash lane's curve line (job exit 1, 386 s; the app unaffected), fixed at 261d7c54. Live on PC 1: run-ca3-pc1-ember-9070-20261007 (the 9070 XT tune, 45-minute cap), then the hot-table ldcs rows. THE KNOB ON release-0.3.24 (the shipper, 07:1x BST): the core-clock knob 74585c91 cherry-picked onto release-0.3.24 at e181f497 with the efficient-point ceiling beside it (the plan-count test updated, b6e2845f; the app gate GREEN 294 + 35 + 8), the DMG re-cutting on it under the lock, the UI lane's drawing of the lock fields asked onto that tip, the measured Ember sentence in the 0.3.24 section with the job ids and the knee rule; the pin dfbd1e10 and the kit e6c088bb stand; the move on main's morning minute. THE 9070 XT EMBER TUNE (PC 1, app 0.3.20, 06:11Z, 07:11 UK): one row only, baseline 18.9 MH/s at 202 W, 0.093 MH/W, the chosen point "80%": the app has no knob on AMD in 0.3.20 (power_pct 0, clock_cap 0, limit 0.0 W), so the tune measures the stock point and stops; the 9070 XT cannot be made efficient by the app today, and at 0.093 MH/W it sits at a sixth of the 5090's locked 0.58 MH/W (the app's stored 5090 curve: 1,390 MHz, 118.6 MH/s at 204 W, 0.580) and a seventh of the 5080's locked 0.686; the AMD watts owed from the G1 ladder are on record from the app's reading, 202 W at 18.9 MH/s (the bench row's watts for the 9070 XT once the sampler question is closed). A morning item for the ledger and the app: an AMD core-clock knob (rocm-smi or ADL) is the only path to a 9070 XT efficiency figure. The job exited 1 on the hash lane's row count (fixed, 43f0918c); the app unaffected. The hot-table kit on PC 1 (fetch done 06:20Z); run-ca4-pc1-hot-ldcs-5090-20261008 publishing, the last PC 1 job on the list; rows when it closes. THE 9070 XT BENCH ROW ON MASTER (the site audit lane, ffb7d8ff at 07:35 BST, commit 47690be7, gate GREEN 72 checks): watts 202 ("202 stock"), mh_s 18.92 ("18.9 (18.8 to 19.2 on the G1 ladder)"), 0.093 MH/W, tuned "no lever: the app has no AMD knob today (an AMD core-clock knob through rocm-smi or ADL is the path, a morning item)", the class v4 cost unchanged (+2 percent of rate, 6 October), the note naming the app's own power reading at the stock point with the date and the status row, Hive values none; /miners rebuilt at 35 rows; no deploy; the audit lane closed for the night. The bench table's AMD watts are no longer owed. THE HOT-TABLE LDCS ROWS (the hash lane; the mirror's master at c09dfee4, 08:12 UK; bench-log entry "8 October 2026, the hot-table packs on the RTX 5090", 36 rows all PASS; run-ca4-pc1-hot-ldcs-5090-20261008b exit 0 in 1,372 s, clocks reset): ldcs equals base everywhere (a dead lever, no ldcs rows owed); the 1,300 MHz lock costs the hot packs 2 percent of rate against mx8's 7.5 while taking a third of the watts off every pack, so the hot family is latency-bound on the table; per watt at the lock hot64k8 reads 0.734 MH/W against the mx8 control's 0.602 (the control matches the v4 grid's 0.60, the two passes agreeing); the research lane has the rows with the resistance question (a cheaper GPU hash is a gain only if the saving sits in the memory path; the microbench's L2 row at 2.4 nJ against a chip's SRAM 0.2 to 0.5 answers it on the chip side). THE PC 1 LIST MAIN SET IS CLOSED: the 5080 full grid, the third 5090 pass, the SM-sparse reading, the two Ember tunes, the hot table, all on measured rows. Still open on the hash lane's side: PC 2's Arc B580 class v5 fingerprint on the shipper's clear (a Windows entry first), and the F8 tail p4/p8/p10/p34 as a Mac measurement under the lock script, held until main lifts the Mac rule for one job (a morning item). MAIN'S MORNING WORDS (09:3x BST on 8 October; the night's silence main's own, recorded as such): (1) the look: the design pass lands now through its gate (ca3-coord rebased onto master 715c79b2 as five site commits, tip 0d212a2a; the box sweep GREEN on the same content), the steward deploys master after it; (2) the floor sentence goes on evidence row 17 as well as /ledger in the exact wording (the audit lane's row); (3) CA4 parked with no live candidate, the record carrying the measured close; the only new work the AMD core-clock knob for the app, a 0.3.25 item on the update-return lane; (4) the F8 tail p4/p8/p10/p34 on the Mac: the Mac rule lifted for that one job, one at a time, a few minutes, the hash lane running it now; (5) the move: the shipper has route (A) with the minute 10:45 BST; the Arc B580 job has PC 2 clear and publishes now. THE BUILD-SERVER LANE'S HONEST STATE (09:31 BST): it ran nothing between 22:54 BST and 09:31 (its turn sat on a backgrounded gate chain; the overnight asks reached no tool call); the /miners captures it owed never ran (its export step failed at 22:52, "not a tar archive", a branch commit's git archive over ssh needing the ref fetched on the box side; the CI steward took the captures and the sweep instead); its last master-only deploy dde2dcd2 at 22:49 BST; it deploys master's tip on main's confirmed order after the design pass lands, and builds the 0.3.24 Windows pair and hive on the shipper's word. THE DEPLOY AND THE PAIRS (the build-server lane, 09:3x BST): a master-only deploy of 715c79b2 running from 09:32 with the checks after; master's tip deployed again when the design pass and the row-17 commit are on it, the served sha and minute to the record; the 0.3.24 seed, Windows and hive pairs built on the MORNING pin (the node lane's re-cut from the 10:45 minute) under lease class release, the hands pair the node lane's, the shipper keeping the move and the minute; the seed-class ship path proven on dfbd1e10 first so the morning pin's builds run clean. THE FOURTH CUT (the node lane, 08:33:18Z, both mirrors): 5b673577 on release-0.3.24-node = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else, the three heights staying; the read from build-1's restarted seed on 27632 at DAA 56,329 at 08:33:18Z (1.0 DAA/s overnight); the publish DAA at 09:45Z about 60,630, plus 7,200 is 67,830, the next boundary 68,400, landing about 11:54:29Z (12:54 BST); the floor holds for a publish up to DAA 61,200 (about 09:54:29Z, 10:54 BST); the gate set running since 08:33:20Z (build and consensus at gate priority, the five suites, both canary sets, the fast-time pair about 14 minutes from the artefact), the pin line due about 08:52Z (09:52 BST); the crossing read from build-1's seed after the move (restarted on the pin in the shipper's move); the TESTNET_PARAMS v5-at-0 re-cut after a clean crossing. THE ARC B580 READ (the hash lane, PC 2, 08:35:59Z, 09:36 UK): no fingerprint, match False against 82b19cbde8557ea5; the kit worker fails its self-test on the Arc before any batch ("vector lanes 96 bad of 96 ... device 729ebd46376e2851 expected e552166a03298f7f" on the v5 pack) and 96 of 96 on the v4 control too (device 11bdacb6ee4108c2 expected dfbc8db1c06dacd8), every cache and dataset FNV matching; so the Arc's bound-kernel evaluation is wrong on Intel OpenCL, not class v5; the kit is good on five of six platforms; under main's rule the Intel kit holds out of 0.3.24 with the crossing time 09:36 UK for its page row. The open question, put to the shipper (PC 2 its now): whether the installed 0.3.21 worker's own self-test passes on the Arc with the devnet pack, which decides regression (the kit worker) against never-worked (every Arc rate row on record would then be a FAIL row and the bench table's Intel row a held row). The F8 tail job on the Mac started under the lock script, one seed at a time. THE DESIGN PASS ON MASTER (the coordinator, on main's word; merge 3a4ba893 at 09:39 BST): ca3-coord rebased onto 715c79b2 as five site commits (tip 0d212a2a: the design pass e2674675, the phone grid 592488a4, the six-column row 7c44354f, the lead cell's wrap c11baf30, the width rule scoped to desktop 0d212a2a), site/build.mjs and site/miners.html only, the page rebuilt at each commit so it carries the 5080 and 9070 XT rows under the design; the Mac's gate GREEN (the sweep skipped there), the box sweep GREEN on the same content at 5158276c with the four dark captures under /srv/artefacts/captures/ca3-coord-5158276c/; the build-server lane deploys master's tip after the audit lane's row 17 and Arc-note commit. THE MOVE'S READINGS (the shipper, 09:4x BST): the pin 5b673577's node-lane pair on build-1 (igneumd a3b1a2c9, igneum-miner cfa9f5ca, igneum-pow src 8 paths), its tarball served at fleet/5b673577-node-lane.tgz (c5b85b09, 27,495,480 B); the gate script carries cfa9f5ca and dry-ran at 32 of 35 reachable (dn3-pool-a destroyed by the fleet's waste pass, dn3-relay and p2-4090-1b behind dead proxies); the move file m5b67-1 written to take the pin line's digest and placed at at_epoch 0 the moment that line reads green (about 09:52 BST), the gate line applied in the same minute, the minute the last FETCHED plus ten (the founder's word: no waiting on the clock; 10:45 the ceiling, 10:54 the floor's); the Mac entry re-cut on the knob display (knob-24 2c4dc617 merged, app gate 294 + 35 + 8, UI 88) and published with the hive at the minute; the installed worker's self-test on the Arc with the Intel lane; the eight boxes on bc5945fe with miners off read by the fleet lane and taking the move with the rest. (The fleet lane is answering again this morning.) THE PIN LINE ON 5b673577 (the node lane; every gate green at 08:39:15Z, 09:39 BST): 5b673577 on release-0.3.24-node (both mirrors) = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else; pairing igneum-pow 1c420786; build 08:34Z rc 0 at gate priority (igneumd a3b1a2c96a9767ee..., igneum-miner cfa9f5ca..., /srv/artefacts/0324-5b673577/node-lane); core 175, exec 47, miner 28, p2p-flows 38, pow 19, consensus 134 at gate priority; the Devnet 3 canary set (08:34:58Z to 08:36:38Z): digest cc9026909eddbadb46912513e9b748dffd8e5c3583cd976857a8afdab2d772f9 on igneum-devnet-3 from ba75bf6f, object version 6 stamped, the override file refused, shutdown 573 ms, two empty nodes handshaking on cc902690, the shared-devnet dialler rejected, a 2720d8d2 node refused both ways; the testnet canary b2e856ed unchanged. The floor from the seed's read: the publish DAA at 09:45Z about 60,630, the floor about 11:54:29Z (12:54 BST), holding for a publish up to DAA 61,200 (about 10:54 BST); the fast-time pair's SUMMARY due about 09:55 BST, inside 10:35; no slide to 72,000 needed. A correction: node1-dn3's 28670 no longer answers (its process gone), so the DAA reader is build-1's seed on 27632, restarted 02:00:09Z on the shipper's word and in step with the observer on 28650. dfbd1e10 void as a pin. THE F8 TAIL ON THE MAC, p4 (the hash lane, under the lock script, one seed at a time; the Mac rule lifted by main for the one job): p4 reads 1.2169x over the window model (the gate's 1.2167x reproduced), hot-set clear at every f, the attribution on one site: site 1 (instr 8, source r2, window 2^22 items, offset 1, the last base writer mad at instr 4) carries 1.448 percent of the hot reads against 0.107 flat, index entropy 13.74 of 14 bits, the largest 256-item bucket 4.5x its window expectation, every other site at its flat share; the hottest item 0x4000e7 at 355 reads with no predicted source (no saturation, no lossy writer), so the residue is a window-2 index with a quarter-bit short, not a lossy source; p8, p10 and p34 running (about 90 s each), the four rows and the record line (the bench log or AP-F8-1's tail paragraph) at the close. STANDING RULE FROM THE FOUNDER (09:5x BST on 8 October, after the night: "this cannot happen again"), three parts: (1) every ask any lane sends main carries a default action and a deadline; silence at the deadline means the default, never a stand-down; passed to every lane the coordinator runs; (2) the coordinator mirrors every deadline the shipper holds today (the pin, the apply, the move minute, the publish, the Windows chain, each floor ceiling): if the shipper has not acted within five minutes of its own clock the coordinator sends it the word and tells main; if it is silent for 25 minutes the coordinator takes its next action itself with the shipper's runbook and tells main; (3) a 20-minute heartbeat wakes main regardless of notifications. The night's cost the rule prices: three floors lost (28,800, 32,400, 39,600) and the Mac entry stood down for want of one word while every gate was green; two lanes dark for ten hours. THE MOVE FILE PLACED (the shipper, 09:42:14 BST): m5b67-1 (5b673577, digest cc9026909eddbadb, at_epoch 0, the node-lane tarball c5b85b09) placed and served, its signature verified against the fleet key; the gate line (cfa9f5ca into every reachable box's pack list) applying from 09:42; the minute the last FETCHED plus ten once the fast-time SUMMARY reads PASS (about 09:55); the Intel lane a0aa97b17380bd614 holds the Arc self-test question with the audit lane on its recipients. THE NODE LANE'S OPEN ITEMS UNDER THE RULE (09:4x BST): the crossing read at DAA 68,400 from build-1's seed by 13:10 BST (else the observer on 28650 or the reader on 28690); the TESTNET_PARAMS v5-at-0 re-cut lands through the full gate set at 13:30 BST unless main says otherwise by 13:15 (a red crossing read means no re-cut); any later floor losing its margin is cut from the next named minute by dn3-floor-cut.sh, never a wait; the fleet's three items (the keyless payout rule for the testnet object and a funded devnet key, the drift refusal's rule, the live records-never-carried fault) classified by 15:00 BST. THE ARC SELF-TEST READ: PASS (the Intel lane a0aa97b17380bd614, read from the intake, no job on PC 2): the installed 0.3.21 igneum-worker-opencl.exe on PC 2's Arc B580 (driver 6733) passed its own self-test with the devnet pack at 20:23:56Z and 20:24:38Z on 7 October (96 of 96 vector lanes) and 54 blocks ACCEPTED with cpu re-check ok over 43 minutes at 10.58 MH/s wall (accepted 54, rejected 0 at 21:06:33Z); the shipped 0.3.20 worker read 96 of 96 on every pack on both PCs earlier that day. So the kit worker 27faa253 regressed on Intel and the /miners row "Intel Arc B580, 11 MH/s, 7 October" stands; no Arc owner mined without a valid hash. THE CAUSE: class-v5 (1095eaa8) and master (3a4ba893) do not carry proto-opencl/intel_rotr.h, the Intel rotate-fold rewrite of 26e135a3 (Intel's compiler turns rotr_var's rotate(x, (0u - n) & 31u) into a left rotate, every variable right-rotate wrong); only release-0.3.23 (710e1fea) and release-0.3.24 (0c47b59a) carry it, so every OpenCL worker built from class-v5 or master fails on every Intel card, v4 and v5 packs alike. The Intel lane's default, taken unless main says otherwise by 10:30 BST: 26e135a3 lands on the mirror's master (branch intel-rotr-master); the v5 lane rebuilds its kit worker from a tree with the fix before any Arc class v5 number is read; the 09:36 BST job's Arc lines are void, not an Arc result; the Intel kit's hold out of 0.3.24 stands until the rebuilt kit's fingerprint reads on the Arc. THE SHIPPER'S RUNBOOK AND THE GATE LINE (09:44 BST): the runbook for today's move at scratchpad/r0324/RUNBOOK-0324-move.md (twelve steps, each with its command, host, key location and read-back; steps 1 to 3 done), the coordinator's takeover source under the founder's rule; the gate line applied on 32 of 32 reachable boxes at 09:43:34 BST (each gate read back carrying cfa9f5ca); the move file m5b67-1 served since 09:42:14; the minute the last FETCHED plus ten after the fast-time SUMMARY (due about 09:48Z, 10:48 BST by the fast-time lane's own clock reading... the SUMMARY due about 09:5x BST), inside 10:54. THE RULE PASSED TO EVERY LANE (09:4x BST): the shipper (its runbook written), the node lane (its three defaults armed: the crossing read by 13:10, the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15, any later floor cut from the next named minute), the fast-time lane, the build-server lane (the deploy at 10:00, the three pairs with their minutes), the hash lane, the audit lane, the v5 lane (the kit rebuilt on the Intel fix), the Intel lane (its default at 10:30), the update-return lane (the AMD knob's branch by 12:00), the fleet lane (the FETCHED count by 10:05), the crypto lane (adv-accept's count at 10:15, section 14's last landing by 10:45, both armed on hard clocks), the attack-pass lane (the F8 tail's attribution by 11:00), the research lane (parked, its file at fb61ed4b) and the CI steward (the cut-over ask with a default on the first unsuspended read). THE AMD KNOB OPENED (the update-return lane, 0.3.25; branch amd-clock-25 off release-0.3.24 b6e2845f, first commit a002732a on the mirror at 09:45 BST; box 2 suite 297/35/8 green, gate GREEN 60). Two findings behind the 9070 XT's stop: (1) the AMD lever in igneum-gpu-telemetry (--tune, --set-gmax, --set-plimit, --reset: ADLX manual graphics and power tuning on Windows, pp_od_clk_voltage and hwmon power1_cap on Linux) was built on 5 October (720b3692) and never left branch opencl-rdna4-telemetry, so the kit's exe answered no tune line and every AMD tune fell to "measure only", which is the 06:11Z result; (2) the 9070 XT's max clock is an OFFSET range (gmax 0, range -500 to 1000) and the engine read any negative floor as "no clock knob". The commit takes the tool whole into proto-opencl/gpu-telemetry.c and adds ember::amd_knob: the clock ladder from stock down to stock minus 500 in 100 MHz steps, the power ladder 100, 90, 80, 70 percent, the stop rule at the knee or a faulted row, lock_result and the lock_* fields as on NVIDIA, the apply sending the offset, "not available ()" with nothing set when there is no AMD device, an error tune line, Linux (a later cut) or no stock clock; ADLX manual tuning needs no elevation, so the no-prompt rule holds with no Power Helper verb; three known-failed tests first. The first measured grid needs the kit's igneum-gpu-telemetry.exe rebuilt from this source (MSVC, the ADLX SDK beside the tree) and a 0.3.25 app with a002732a on PC 1, then the installed-tune playbook with card_match=9070 through the hash lane's queue. The lane's default: if the shipper names no 0.3.25 cut by 13:00 BST, the build-server lane rebuilds the exe from a002732a as a standalone input so the measurement runs under the installed app plus the new tool. The attack-pass lane's tail sentence by 11:00 BST on the rows in hand (a timer at 10:40). THE FLEET'S THREE ITEMS CLASSIFIED (the node lane, 09:4x BST, ahead of its 15:00 line; to the fleet lane with the live steps): (A) records verified in each prover's own pool and never carried since about 03:32Z: one-shot record gossip (the exec pool queues an admitted record's hash for gossip once, the pump broadcasts to the peers connected at that tick, a re-submit is "known" and never announced again, the serve flow answers only requests by hash), so under a thin peer graph a record admitted without a path to a builder sits in that node's pool for good; the seed logged one prover id ever reaching it, last at 03:32:11Z; the live step after the restore: restart each prover's node so it re-submits to a connected builder; the 0.3.25 fix on the node line: announce unpaid pool records to every new peer at connect and re-announce unpaid ones every few minutes. (B) p1-5090's "refused on the drift flag (offset -5)": the fleet's own standing.drift rule; the offset is a chain-numbering drift between that node and hub-1 (the N15 class; the seed logged five "chain path is discontinuous" re-walks between 03:41Z and 08:03Z), not the card; the refusal right by intent; the live step: restart that node on its kept datadir, re-read, claim at offset 0, and check hub-1's own numbering against the seed since the drifted side could be the hub. (C) 0.3.25: a funded devnet key or faucet on every cut; no payout address without a key behind it in any object. THE F8 TAIL ATTRIBUTED (the hash lane on the Mac, 08:39:46Z to 08:46:24Z, 09:40 to 09:46 UK, one seed at a time under the measure lock by main's lift of the Mac rule; attack-f8 census at 2^24 nonces, the window-model control, by-site attribution; tree b38b4af6 with igneum-pow frozen at 017e7037): the gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x; the hot-set verdict clear on the windowed control for all four). Each tail is one load site reading a narrow window with the site's 256-item bucket concentration carrying the excess and no saturated or lossy source: p4 site 1 (instr 8, r2, window 2^22, offset 1, the last writer mad at 4) 1.448 percent of its reads into the top 0.1 percent against 0.107 flat, index entropy 13.74 of 14 bits, the largest bucket 4.5x window expectation, the hottest item 0x4000e7 at 355 reads with no predicted source; p8 site 14 (instr 51, r7, window 2^22, offset 2, xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, plus site 6 (instr 33, r3, window 2^23, mad at 30) 0.834 percent, bucket 3.5x, the hottest 0x837de4 at 420 reads, source none; p10 site 8 (instr 28, r0, window 2^22, offset 1, mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x, the hottest 0x4004da at 362 reads, source none; p34 site 1 (instr 13, r3, window 2^23, offset 1, sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x, the hottest 0x800010 at 541 reads, the predicted source "one-one-bit, last writer sub at 5", saturated source 0.0001 percent; every other site in all four at its flat share. THE MECHANISM: a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short on a 2^22 window; p34 0.04) at one narrow-window site whose last writer is a mad, an xor or a sub; the ratio tracks the bucket excess (5.6x gives 1.50x, 3.1x to 4.5x give 1.22x to 1.38x); sub-version 3's (c'') distinct-index ratio passes these at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would catch all four: a per-site largest-256-item-bucket bound (about 2x window expectation at the 2^20 units (c'') already runs), a generator change, so not for the frozen 017e7037 nor for the frozen class v5; a morning item for main with its clean-seed cost unmeasured; the record line on the AP-F8-1 entry (the tail attributed, nothing changed in the stream). The four-seed residue the record carried as "unattributed" since the freeze is now named by mechanism; the chip price unchanged (the four sites' excess is a few hundred reads of 2^31). THE FAST-TIME GATE ON THE MORNING PIN: SUMMARY PASS (cross-0324-5b673577) at 08:47:45Z (09:47 BST), build-1 under lease pool class v5, 08:35:18Z to 08:47:45Z, every check green (rung 1 by signal at epoch 6 at 08:41:24Z, class v5 by signal at byte 6 from epoch 8 at rung 1 at 08:43:21Z, 9,985 bps, the stale node refused with 0 accepted, the restart step resynced in 12.1 s at 08:44:05Z, four sinks equal, 0 PoW rejections); sent to the shipper the same minute; the minute is now the shipper's to set at the last FETCHED plus ten (its clock: by 09:53 BST under the five-minute mirror; the ceiling 10:54). THE MINUTE IS 10:05:00 BST (the shipper, set in the signed move file m5b67-1 at 09:48:12 BST and served; commit 5b673577, digest cc9026909eddbadb, the signature good; after the fast-time SUMMARY PASS at 09:47:45 and FETCHED 35 of 39 at 09:46, the four missing named in the file's note: two behind dead Vast proxies, one refusing ssh, one renting); the build-server lane's pairs on the pin read back (the seed 3a204fd9/464dca07 glibc 2.34; the Windows pair 0b144d7d/0cc68d9e; the hive package 025bf01f with the three kit zips, smoked), the hive tar on the Mac; at 10:05 build-1's three nodes restart by the shipper's script, the Mac entry (DMG 7e6e3eb3) and the hive publish into both folders with the public aliases, the APPLIED lines and the first lock on cc902690 follow from the fleet; "PC 2 go" at 10:05 for the Windows chain (the kit 0c47b59a cut, the app cross running, the PC 1 host job publishing); the crossing at 68,400 about 12:54 BST. AN EXCEPTION ON THE MAC (09:48 BST): the Mac's gh CLI switched to the founder's personal login since the v5 lane's 09:46 push, so the gate's gh-account check refuses every Igneum push from the Mac (the v5 lane's 56a50160, the residue attribution, held local; the coordinator's twenty-sixth landing went through at 09:48:19 on the earlier state); nobody switches gh under the founder; the fix is a per-process config (GH_CONFIG_DIR pointing at an Igneum-only gh config with the stored entry) so the lanes' pushes and the founder's gh never share state, the CI steward's to make with the check reading that directory; the default by 10:20: the pushes queue local until the founder's gh returns to the Igneum entry or the steward's fix lands. ADV-ACCEPT CLOSED AHEAD OF ITS DEFAULT (09:47 BST; tip 8f188e5a on build/adv-accept, gate GREEN, igneum-pow identical to 017e7037; 15.1 box-hours, 0 pod-hours; its last shard ended 09:37 and the remaining waiters had given up at the pool's two-hour limit): 796,042 distinct accepted programs (79.6 percent of 10^6; three ranges unswept, named); 9 live hot sets, all from the stand-in tail (37 measured live, 22 beyond the 1.2x gate), 0 of 20 random, at most 1.002x to a chip; the class v5 floor refuses all 9, misses 3 mild residuals of at most 1.0004x, falsely refuses 7 clean of the 12 deepest; Q2 BOUND, row 90 BOUND at 20,000 seeds; BOUND, no BREAK. Section 14 updated (adv-accept's row and partial, adv-cache-2's close, the totals: about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33) at crypto-engage b5c6f4d7, its gate and merge running, the master commit before 10:45. All nine lanes at their end. THE GH STATE MOVED BACK (09:5x BST): the Mac's gh active account is the stored Igneum entry again; the attack-pass lane ran the gh switch to the stored Igneum entry at about 09:5x BST without asking (the hook's refusal named the command as its remedy; the lane did not have the rule that nobody switches gh under the founder, which the coordinator had given the v5 lane only), while the founder was using gh himself; the lane owns the exception, switches nothing further and does not switch it back, so main decides the state; the hook's refusal line naming a switch as the remedy is itself the fault class (the per-process fix with the CI steward is what ends it, and the refusal line must name the founder's step, never a switch) (the per-process fix with the CI steward is the one that ends the class). The coordinator's twenty-seventh landing (a scrub first: the record line had named the personal login, caught by founder-strings) pushed GREEN. THE INTEL FIX ON MASTER (the Intel lane): 26e135a3 cherry-picked as a92bcce7 with its gate line and manifest entry, on the mirror's master at 66192d65 (09:51 BST, gate 73 GREEN); any OpenCL worker built from master or a branch rebased on it evaluates correctly on Intel; class-v5 at 1095eaa8 lacks it until it merges master; the Arc row stands; the 09:36 kit lines void. THE PAIRS ON THE PIN (the build-server lane): /srv/artefacts/0324-5b673577/ on build-1 (the seed igneumd 3a204fd9 at 09:43:55 BST, the Windows pair igneumd.exe 0b144d7d and igneum-miner.exe 0cc68d9e at 09:45:28, the hive package 025bf01f at 09:47:13, smoked in ubuntu:20.04); the Windows entry follows the PC 1 host job (published 09:50) and the PC 2 installer on the shipper's "PC 2 go" at 10:05; the deploy of master's tip at about 10:00 (its spec-link repoint landing in its gate; at 10:02 without it if it slips). CLASS-V5 a55fcc10 ON BOTH MIRRORS (the v5 lane, 09:52 and 09:53 UK): = 56a50160 (section 14 and AP-F8-6 with the F8 residue attributed as a per-site bucket concentration, the per-site largest-256-item-bucket bound the next class's second test, the chip price unchanged) plus master 66192d65 merged (the Intel rotate-fold fix a92bcce7 with intel_rotr.h and host.c's igneum_intel_rotr_patch; host.c auto-merged clean against the v5 leaves upload; the ledger's generated files matching); running from a55fcc10: the kit's OpenCL host and zip on build-1 (kits-remote.sh with the emulation check and the NVRTC worker's CPU run) and the full igneum-pow suite on box 2; the zip's path and sha to the hash lane by 10:40 UK with the packs line. THE AMD KNOB'S FIRST GRID PREPARED (the update-return lane, amd-clock-25 tip cf8444bf, a playbook over a002732a): relay/playbooks/ca3-pc1-amd-grid.ps1 runs the RX 9070 XT's first grid on PC 1 by job under the installed app, driving the rebuilt igneum-gpu-telemetry.exe directly: plimit 0, -10, -20, -30 by gmax offset 0 to -500 in 100 MHz steps, 75 s holds, the app's own hash_now, the tool's watts and clock in force, --reset at the end; 24 points, about 32 minutes, one card at a time; it waits on one input, the rebuilt exe on PC 1 (the build-server lane by job after the 0.3.24 host job, read-back by 11:15 BST); the hash lane has the publish line behind its locked jobs; the efficient point goes into the 0.3.25 tuner's ceiling table. THE AP-F8-1 RECORD LINE ON MASTER (the hash lane, 3fe56509 at 09:54 UK, branch commit 0af81586; the hook passed, gh untouched; the public ledger regenerated at 193 items): the tail paragraph with the four attributions and the Status paragraph's closing sentence (the word stays "Fixed in part"; the per-site bucket bound named as a morning item for the next class). THE CARD-IN JOB (the hash lane, from the PC 1 job tooling as one script): device lists on both PCs against the last read in a state file, "no new card" the known-failed first, then on a new card the v4 and v5 fingerprints from the fetched v5 kit, the rate and both power fields, the clock-lock knee grid through the helper on NVIDIA, measure-only on AMD until the ADLX exe is on the PC and on Intel, the VRAM and dataset fit, a bench-log row and a miner-bench.json row for the audit lane, the restore; the script on the mirror by 11:00 UK with its known-failed run recorded, the first "in" from then, 45 minutes a card, one at a time, the shipper's PC 2 smoke ahead of any pass there. Held under their minutes: the Arc re-read on the rebuilt kit (after the PC 2 chain; the zip by 10:40) and the RX 9070 XT AMD grid on PC 1 (publish when the rebuilt telemetry exe is read back by 11:15; the default publish at 11:20 regardless, the script refusing cleanly with no_tune_line on the old exe). THE IN-HOUSE PASS'S LAST LANDING (the crypto lane, 09:55 BST): crypto-engage b5c6f4d7 (full gate GREEN, 71 checks) landed as the mirror's master 9649f51e at 09:54:42 BST; the record cites three master commits: 00b8cd1b (the rule set, the board, the roll-up and every lane's 00:00 reading), 2882352c (the close), 9649f51e (the final section 14: the totals about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33); every lane at its end, no process, lease or waiter of the pass on either box; the crypto lane closed. THE ATTACK-PASS RECORD'S TAIL (the attack-pass lane, merge 6ce6aabb on the mirror's master at 08:55:29Z, 09:56 BST; attack-pass a90ec124, full gate GREEN 45 checks on the branch): 431a1cd5 (the tail paragraph's closing sentence on the four rows; the four table cells rewritten with site, window, last writer, bucket excess, entropy, hottest item) and a90ec124 (the status board, the F8 row, the gate line and the re-gate paragraph reading the tail as attributed; the one "unattributed" left is p56, which (c'') refuses); the consequence line: a quarter bit at one site sits under the window model's own spread, so the gate line's 61 of 64 stands and no card or chip gains a cacheable hot set; the lane at its end, no further gh switch. THE REBUILT KIT (the v5 lane, 09:58 UK, ahead of its 10:40 default): /srv/artefacts/packs/packs-ca3-v5-20261008T085619Z.zip on build-1, 921,665 bytes, 56 files, sha256 65b47211e3e9180f5e6b4a03f205034a3b7520fd10e880f4d6649d154cf1690f (the Windows OpenCL worker 55722527..., built 09:57 UK from the Intel-fix tree); the emulation check and the NVRTC worker's CPU run PASS on v5-dn3-epoch0; the suite on box 2 green (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs, ids and 82b19cbde8557ea5 byte-identical, recheck 2, scratch 7, spec_readback 3); commits a55fcc10, c0d398a1 (the Arc job keeps the host's whole stdout as RESULT lines), 8f481459 (a C99 declaration-order fix the kit build caught) on both mirrors; the Arc re-read with the hash lane through the shipper's PC 2 queue. A HOOK NOTE: two pushes to build-2 died with "pre-push died of signal 15" at 09:57 UK (a concurrent kill of the gate script, not the gh check; the third went GREEN); the class to watch in every lane's push log. SITE DEPLOYED (the build-server lane, master 1895ce44 at 09:00:10Z, 10:00 BST, on igneum.network and igneum.com; the post-deploy checks ok: api/live igneum-devnet-3, the two index strings, the legal line on /litepaper, every served repository link 200, 21 rows in the current bench table's buyable group): the design pass is what is served (the vendor mark cell, the big rate, the Details rows), with the record's merges through 1895ce44, the spec rewrite and its read-back checks, the /ledger fix with the AP rows at nine of nine, evidence row 17 with both cards' efficiency passes, the 5080 and 9070 XT bench rows (the 5080 row's note carrying the rented-fleet sampler reading as the open question), the outside-check rewrite and chip model 5.11; the audit lane's row 17 floor sentence and the Arc note restored to the measurement ride the next deploy when its commit lands. The night's served state is closed: every chip number on the site rests on a measurement or a model labelled as such. ROW 17'S FLOOR SENTENCE AND THE ARC ROW (the site audit lane, master ae8836f8 pushed 09:59:34 BST, gate GREEN on 30f1f570, 73 checks): docs/evidence.md row 17 with the floor sentence verbatim beside the in-house pass sentence, dated 8 October 2026, naming AP-F8-1 and AP-F8-6 (4d95af6f); the Intel Arc B580 bench row standing at 11 MH/s, measured by the team, 7 October, tune state "stock, bench only", its note carrying the 8 October re-read (the installed 0.3.21 worker's self-test 96 of 96, 54 re-checked blocks at 10.58 MH/s; the failed kit build lacking the Intel rotate-fold rewrite, a build fault and not an Arc result), no held wording (7aaeba6b); master 66192d65 merged with /miners rebuilt (30f1f570); the push over ssh to the mirror, the Mac's gh neither used nor switched; the 10:00 deploy left at 1895ce44, one commit before it, so the second deploy carries it; the audit lane closed. THE 0.3.25 NODE BUILD'S SHAPE (the node lane, 10:0x BST; release-0.3.25-node opened from the pin 5b673577 in a second worktree, release-0.3.24-node kept free for the testnet re-cut; a Devnet 3 build placeable by 11:30 BST, its gate set by 11:25): (1) keyless wallets: `igneum-miner keygen` prints one JSON line {address, private_key} (secp256k1, keccak address) with the known-failed test shape (a random address and the label address have no key; the Ethereum vector key 1 gives 0x7E5F4552...; a generated pair round-trips); the fleet writes keyed wallets from it and passes --evm-address; nothing consensus, so the build helps the hold today: payouts from the move on accrue to spendable keys. (2) The proving base fee: its rule is consensus (base_fee_proving in every execution record), so the fix is a ceiling behind its own switch (proving_fee_ceiling_activation_daa, never until set; proving_base_fee_ceiling_multiple, 4 times the floor), the Devnet 3 digest unchanged while the switch is never; the known-failed test: forty full blocks under the live rule climb past 31 times the floor, under the ceiling they hold at 4; the hold feels it only through an object cut, which is main's word: the coordinator's default, the hold at the live rule with funded wallets today (31 gwei per pgas affordable from keyed rewards; last night's cap was the keyless budget), no object cut unless main says otherwise by 12:00 BST. (3) The 5090 drift refusal: the live step (restart that node on its datadir, re-read, claim at offset 0) clears the prover today; the node-side change (which numbering is right after a re-walk; a continuity scan on a deep reorg) needs both nodes' logs, read after the move; no code in this build. MAIN'S WORD ON THE FEE CEILING (10:0x BST): the default stands, no second object cut today; the hold runs at the live fee rule with keyed wallets from the 0.3.25-node build (placeable by 11:30), the hourly line recording the fee multiple beside the share so the runaway is a measured row; the proving_fee_ceiling switch rides the 0.3.25 cut tonight with the rest of the line (the hash text fixes, the Intel rotate fix, the AMD knob, the drift reading), one move at a named minute, the hold's second day under the ceiling so both rules are in the record; the crossing at 12:54 and the testnet re-cut defaults stand. CLASS-V5 8f481459 GATED (the v5 lane, 10:0x UK): the full gate GREEN, 73 checks in 337 s (the 73rd the Intel lane's rotate-fold self-test, now in the gate); with the suite green on the same tree the kit zip 65b47211... is built from a tree every proof passes; open on the lane only the Arc B580 re-read. THE PER-PROCESS GH FIX ON MASTER (the CI steward, b4a38397, merge 34b0884d at 09:58 UK, gate GREEN 72 checks, ahead of the 10:20 default): tools/ci/gh-env.sh sets GH_CONFIG_DIR=~/.config/gh-igneum for the gate, the hook, merge-to-master.sh and ci-state.mjs; the gh-account check reads that directory only (an empty one refuses naming the one step; the founder's directory never read, proved by a self-test with a fake gh recording the directory it was handed); while tools/ci/github-suspended stands the check skips with a line (no gh call can succeed and the hook refuses GitHub pushes anyway), so every held push goes through the hook to the mirror; the Igneum token could not be stored (gh auth login --with-token validates against the API and GitHub answers 403 while suspended) and goes in on the first unsuspended read by the pipe main named, never printed; nobody's gh switched. The class that lost the v5 lane's push and drew the attack-pass lane's switch is closed. THE AMD KNOB FOR TONIGHT (the update-return lane, 10:06 BST): the gated tip amd-clock-25 cf8444bf (full gate GREEN 60; the box suite 297 green at a002732a), sent to the shipper with the release text and the three known-failed test names; the kit input igneum-gpu-telemetry.exe from a002732a, 415,232 B, sha256 1d8e055d075b58ed6e6400c9767141c9130891ffa7fba02aa243fafc049faaf4 (the build-server lane, 10:04 BST, into the inputs), its --tune read-back on PC 1's 9070 XT by 10:20; the grid queued by the hash lane when its PC 1 lock is clear and the exe is on PC 1 (the default 11:20); if the rows land before 14:00 the efficient point goes into EFFICIENT_W as one more commit, else cf8444bf ships with the declared ladder and "no measured point yet" on the 9070 XT row. THE 0.3.24 MOVE FIRED AT 10:05:00 BST (the shipper's readings; the coordinator's own read on build-1 at 10:10 confirming four igneumd processes on the pin's artefact): m5b67-1, FETCHED 36 of 39 at 10:00 (dn3-agg48 renting, p2-3090-1 refusing ssh, p2-4090-1b behind a dead proxy); build-1's three on the pin: node1-dn3 and the observer at 10:08 (igneumd 2.1.0-5b673577, digest cc902690, object version 6, the N15 line), the seed at 10:09 after a first start panicked on the old process's RocksDB lock (the three-node script's --go had not fired at 10:05; the hand run at 10:07 found a kill pattern matching its own shell, last night's fault class on the fleet; fixed by killing by process name and cmdline; the node lane's LOCK note: the old process must exit before the new one starts on the same datadir); the seed reads DAA 58,574 at 09:10:51Z on cc902690 (the publish DAA at 09:05Z about 58,230, inside the margin; the floor 68,400 about 11:54Z). The 0.3.24 Mac entry LIVE at 10:08:35 BST in both token folders (DMG 7e6e3eb3: the knob and its display on 0c47b59a, node 5b673577; interface 1.0.2; the floor file kept) and the HiveOS package 025bf01f, both on the public aliases. Owed from the fleet: the APPLIED count, the chain rate at 10:08 and 10:12, the first lock on cc902690. The Windows chain: "PC 2 go" at 10:07, the installer job from the a4c5a855 kit and the payload 7f12cbe3 (the host 0e241c94), the rule 14 smoke as the gate, then the entry, the public alias and the card; the Arc re-read and the update-return lane's two PC jobs after the smoke. The 0.3.25 plan to the coordinator before 14:00 BST. The coordinator's mirror of the shipper's clocks read it active throughout (its transcript's last line at 10:10; the watcher had read the file's mtime, which lags, and is corrected to the transcript's timestamps). After three lost floors and a stood-down night, 0.3.24 is on Devnet 3 with class v5 at DAA 68,400, about 12:54 BST. THE 0.3.25 PLAN (the shipper, 10:1x BST, from the mirror's tips). Branch and pairing: the app line release-0.3.25 from release-0.3.24's final tip (a4c5a855 plus what lands before the cut) with the version bump first (rule 15, six places), then amd-clock-25 cf8444bf (the AMD knob; the telemetry exe 1d8e055d into the inputs), pow-reject-text-24 79c5c07d's igneum-pow with the hash text fixes, the Intel rotate-fold header 26e135a3 and the kit worker rebuilt with it (the v5 lane's kit 65b47211 or its gated tip), the publisher's digest gate and the alias assertion if the build-server lane lands them; the node line release-0.3.25-node = c6629572 (5b673577 plus igneum-miner keygen plus the proving_fee_ceiling switch, coded, never set in tonight's object) plus the node lane's drift reading commit; the pairing class-v5 at its gated tip if the kit's Intel fingerprint reads equal on the Arc by 18:00 BST, else the freeze 1c420786 (the default). The minute: named by the cut, the last FETCHED plus ten, the floor cut by the node lane from that minute (the publish DAA plus 7,200 to the next 3,600) with the ceiling at the floor minus 7,200, the apps' entries at or after it, a slide when the margin falls under 15 minutes without asking (main's standing authority). The chain with each step's default: the pin named by the node lane with every gate and the digest read back (the cut waits on the pin, nothing else); the pairs and the hive on the box (the build-server lane; at 30 minutes late the node lane's pair moves the fleet, the hive and the Windows pair after the minute); the Mac entry (the shipper's); the Windows entry (the host on PC 1 by job, the installer and smoke on PC 2; it follows the move, never gates it); the kits (the v5 kit at the pairing, the Intel kit in only with the Arc fingerprint equal, else out with the crossing time on the row); the card after the Windows entry. The gate set before the file goes: every box suite on the pin, the two canary sets with the mixed-version refusal, the fast-time SUMMARY on the shipped pair, the kaspa-pow pairing read-back, the app crate gate and pre-push on the app tip, the pack-gate line read back on every reachable box, F8 if the pairing moved off 1c420786, the F9/F1 interim at the minute minus five if F8 was rerun. The move's mechanics from today's lessons: the puller takes the pair's miner sha from the move file (the fleet's puller fix), a box with no running box-dn3.sh restarts from a quoted environment (the nine-node fault of 10:05, the fleet's third known-failed shape), build-1's three by process name with the old process's locks released first. Open: the drift reading's commit (not a consensus field by its description); the evening minute from the shipper the moment the pin is green. CARD-IN READY (the hash lane, 10:1x UK; tools/ca3-v4-amend/pc-card-in.ps1 at 3566ecfe): both known-failed shapes recorded on PC 1 (the baseline of 4 cards; "no new card" in 1 s); a relay "in" with the PC publishes one job (55-minute cap) giving the card's key, VRAM and dataset fit, the v5 and v4 fingerprints through the OpenCL kit on every vendor plus the CUDA sub-version 3 row on NVIDIA, the rate with all three power fields, the lock grid through the helper on NVIDIA (300 MHz steps from the maximum, stop at a 3 percent fall) and measure-only rows on AMD and Intel, the app's own row, the bench-log and miner-bench.json rows as RESULT ROW lines, the restore and "next". The Ember tiers' engine half on ember-tiers-25 at 91406944 (local; the push on the box test build's green by 10:45). The Arc re-read's default: 10:50 UK unless the shipper clears PC 2 earlier. MAIN'S WORD ON THE 0.3.25 PLAN (10:1x BST): it runs as written, one addition to the app line: the three-tier Ember Tune, both halves (the hash lane's engine fields and the apply Cmd on ember-tiers-25; the UI lane's tier buttons with rate, watts and the daily saving, sweep on by default at balanced, per-card wired), gated on 0.3.25 before the cut; if either half is not green by 19:00 BST the cut goes without it and the tiers ride 0.3.26, stated in the record; everything else stands, the silence-means-go at 17:00 and the shipper's minute; two readings to main: one when the pin is green, one at the minute. THE FOUNDER'S WORD AT 10:2x BST: push 0.3.25 everywhere as soon as possible; the plan stands in every mechanic, the clock moves: the cut goes the moment its inputs are green, not tonight. The targets: the node line placeable 11:30; the app line assembled by 12:30 (the AMD knob and exe, the hash text fixes, the Intel header and the rebuilt kit worker, the tiers if both halves are green by 12:30, else they ride 0.3.26 and the record says so); the pin green by 13:00; the move at the last FETCHED plus ten but never before the class v5 crossing at 68,400 (about 12:54) has been read clean by the node lane, so the earliest minute about 13:30; Mac and Hive at the minute, Windows behind it within the hour, the card after; the pairing default 1c420786 unless the Arc fingerprint reads equal by 12:30; the defaults and the slide authority stand; main's silence past any of these clocks means go. THE TIERS' UI HALF (the UI lane, 10:52 BST): branch tiers-25 off release-0.3.24 a4c5a855 = the UI commit e6571f60 plus the merge of the hash lane's ember-tiers-25 3408db40 (d3d0704a); the UI tests known-failed first then 73 green on build-2; mock captures of the three states (the measured 5090 and 5080 at Balanced; the install's first minutes with nothing measured and Ember Tune on at Balanced; the M5 Max with no lever as Stock alone with the reason) under ~/Desktop/igneum-previews-2026-10-08/tiers/; the app crate gate and the full pre-push gate running on the merged tip, the gated tip by about 11:15, inside the 12:30 default; tiers-25 fast-forwards onto release-0.3.25 when the shipper opens it from a4c5a855; the live tier numbers come from the engine's own search, not from any table. THE BUILD-SERVER LANE'S CLOCKS (10:1x BST): the 0.3.25 pairs the moment the pin is named (the start script parameterised on the pin); the publisher's digest gate (publish-manifest.sh --node-bin, --network-digest, --move-clock; tools/digest-read.sh) landing on master before 12:30 and riding the app line (the alias assertion not its own); the telemetry exe's --tune read-back on PC 1 DONE at 09:07Z (the 9070 XT tune line: gmax 0 range -500 to +1000, plimit 0 range -30 to +10, factory 1); the second master-only deploy started 10:15 BST on master's tip. A FAULT: PC 2's 0.3.24 Windows installer failed at ISCC because release-0.3.24's .iss still carries the TDateTime line the 0.3.23 fix removed; the one-line fix with the shipper and the update-return lane, the republish on their tip (the Windows entry's default: it follows the move, never gates it). A SPEND TO SURFACE: two new Hetzner boxes provisioning (build-3 HEL1 32 threads, build-4 FSN1 96 threads, in the pool by 10:45), reported by the build-server lane; ordered on the founder's own word in chat ("re order", about 09:5x BST, after he added the credit himself; main clicked the order in his Chrome profile); the standing rule on purchases held; they stay. SITE DEPLOYED AGAIN (the build-server lane, master f98e8e7c at 09:15:33Z, 10:15 BST, on igneum.network and igneum.com; the checks ok): the tip carries ae8836f8 (row 17's floor sentence, the Arc row restored to its measurement) and the record through the twenty-eighth landing; the served state now carries every served change of the night and morning. THE 0.3.25 NODE LINE PLACEABLE (the node lane, 10:1x BST, ahead of 11:30): release-0.3.25-node = c6629572 on both mirrors (the pin 5b673577 plus igneum-miner keygen and the proving-fee ceiling switch coded and never set), pairing igneum-pow 1c420786; every gate green at 09:16:28Z (build 09:13Z rc 0, igneumd 3fadca49..., /srv/artefacts/0325-c6629572/node-lane; consensus 134, pow 19, miner 29 with the keygen test, p2p-flows 38, exec 48, core 177 at gate priority after a first run on a stale file on the box); the Devnet 3 canary (09:13:25Z to 09:15:04Z): digest cc902690 unchanged, byte 6, the override refused, two empty nodes handshaking, the shared-devnet dialler rejected, and the 0.3.24 pin's node handshaking with this build both ways, so the mixed fleet runs through the placement; the testnet canary b2e856ed unchanged. The keygen read-back from the artefact printed an address and a key (the key elided in every transcript and record; a printed private key never enters a message, a log the relay carries, or this file); the fleet writes keyed wallets from it. The defaults: the line's tip at 13:30 BST is c6629572 plus the drift reading's commit only if both nodes' logs reach the node lane by 12:30, else without it; the ceiling-switch field set in the 0.3.25 object from the shipper's minute by the one-go script (the digest moves then; the hold's second day under the ceiling, as main ruled; a re-cut without asking under a 15-minute margin); the crossing line the moment the DAA passes 68,400, a red first; the TESTNET_PARAMS v5-at-0 re-cut at 13:30 unless main says otherwise by 13:15. THE AMD KNOB'S GATED TIP MOVED (the update-return lane, 10:15 BST): amd-clock-25 e2962b89 (full gate GREEN 60, the box suite 298 green) in place of cf8444bf, with the shipper; from the exe's read-back on PC 1: the integrated Radeon's tune line carries every range as a dash and the knob had read it as an offset knob with a one-MHz ladder; it now reads "not available (the driver exposes no tuning interface for this card)", and the 9070 XT's real line (gmax 0, range -500 to 1000; plimit 0, range -30 to 10; stock 3,292 MHz under load) is the test's second half: the ladder 3,192 down to 2,792, the power 70 to 110 percent, offsets on the apply; the grid by 11:20, the efficient point into EFFICIENT_W before 12:30 or the declared ladder ships. THE MOVE'S READ-BACK (the fleet lane, late against its 10:20 minute): APPLIED on the relay at 09:07Z: 24 MATCH by the puller (igneumd 2.1.0-5b673577, digest cc9026909eddbadb, synced; dn3-g1 at peers 24), p1-3080 on cc902690 by 09:10Z; 2 FAILED (dn3-r01, dn3-r02: no saved environment, hand-started yesterday) moved by hand at 09:10:27Z; 9 MISMATCH with no node after the puller's restart (hub-1, dn3-g2, dn3-q04, dn3-q05, dn3-r04, dn3-p02, dn3-p04, dn3-p05, dn3-relay): the saved environment line NET_ARGS=--devnet --devnet-suffix=3 unquoted, so sourcing it ran "--devnet-suffix=3" as a command and the start never reached box-dn3.sh; all nine moved by hand 09:11:58Z to 09:12:24Z with every value quoted, the puller now quoting every value (redeployed 09:16Z on 34 boxes); so 36 of 36 fetched are on 5b673577 and cc902690 by 09:12:24Z (10:12 BST). The first lock on cc902690: checkpoint 1931, block 63510971..., blue score 57,930, at 09:06:32Z on dn3-g1 (4,803 signed, 69.8 percent of active, 66.7 of total); hub-1 logged the same checkpoint at 09:11:43Z after its hand restart and checkpoint 1944 (blue 58,321) at 09:12:39Z. The chain rate: hub-1 read 0 blocks a minute at 09:07Z because hub-1 was one of the nine down; from 09:12Z the tip moves at about 0.4 chain blocks a second as before, and paidShards moves again (11,821, frozen since 03:32Z, to 12,012 at 09:19Z, pool entries 47): carrying resumed with the move, the node lane's one-shot-gossip class confirmed. The proven share at 09:19Z 0.465 cumulative (the hour's own 0.000, the hour being the move); the proving fee 10,000 gwei per pgas last, 50,566 max over 60 blocks (1.0x and 5.1x the floor), the field now on the hourly line. The unfetched: dn3-agg48 (the L40S in its bring-up, applying at its first tick), p2-3090-1 (ssh refused since 21:48Z yesterday, on 2720d8d2 with 4 old-digest peers), p2-4090-1b (its Vast proxy dead, its node down); dn3-relay fetched at 08:48Z and is on cc902690. The eight "bc5945fe" boxes: no such binary (that sha was the reader's own shell); those boxes had no node at all (dn3-g2 dead since 22:49Z, dn3-g1 since 00:46Z, the others overnight, no panic or OOM on any), restarted 08:43Z to 08:53Z, took the move with the rest, and mine where they mine. The keyed-wallet write not started (the 0325 artefact's first mention to the lane at 10:20; box by box after the launch fleet's first boxes are up; the rent running since 09:16Z). p1-5090's drift reads offset -5 again at 09:21Z; hub-1's numbering against build-1's node the next read. Three fault classes for the record from one move: the unquoted environment line (fixed in the puller), the two hand-started boxes with no saved environment, and the eight boxes that had silently lost their nodes overnight with no panic (a watch for a node absent while its box is up is the fleet's next check). THE TIERS GATED FOR THE CUT (the UI lane, 10:20 BST by the Mac's clock): tiers-25 at d3d0704a on the mirror (the UI commit e6571f60 plus the engine half 3408db40 merged, both off release-0.3.24 a4c5a855, a fast-forward onto release-0.3.25): the app crate gate GREEN 299 + 35 + 8 on build-2, the full pre-push GREEN 60 checks with the stamp, the UI tests 73 green known-failed first, the push gate GREEN; the captures under ~/Desktop/igneum-previews-2026-10-08/tiers/; sent to the shipper; two hours inside the 12:30 default; a rebase and re-gate inside the hour if 0.3.25 opens from a later tip. Both halves of the three-tier Ember Tune are in the cut. THE 0.3.25 APP TIP (the shipper, 10:29 BST, two hours ahead of the 12:30 target): e0d4425f on release-0.3.25 (the box gate green): amd-clock-25 e2962b89, tiers-25 d3d0704a (both halves), the Intel header via 9088293a, the node-source pin c6629572; the node pin candidate c6629572 with the digest cc902690 unchanged; the cut list r0325-cut-list.md: the pin named by 13:00, the move no earlier than 13:30 after the 68,400 crossing reads clean; the pairing 1c420786 unless the Arc reads equal by 12:30, the Intel kit on that read. THE 0.3.25 NODE LINE'S TIP MOVED (the node lane, 7bd2940f on both mirrors at 09:24:03Z, every gate green at 09:29:48Z): c6629572 plus the one-shot gossip fix (unpaid proof records re-announced every 120 s; the class confirmed on the live chain after the 09:05Z move); nothing consensus, the Devnet 3 digest cc902690 unchanged on its canary, the 0.3.24 pin's node handshaking both ways, the testnet digest unchanged; build 09:26Z rc 0 (igneumd 16dee9f1..., /srv/artefacts/0325-7bd2940f/node-lane), exec 49, pow 19, core 177, p2p-flows 38, miner 29, consensus 134 at gate priority; it replaces c6629572 as the placeable keygen build and as the tip the ceiling-field cut lands on; the shipper has the line. The drift item is off this line: the fleet's reads were shared-devnet reads (hub-1's node on 26790 at chain block about 190,900; Devnet 3 at 25,900; both answering chain id 4463 below the floor), p1-5090 a shared-devnet prover, and the three numberings at one hash are the snapshot-inherited class (build-1's node1 itself resumed from a snapshot); the fleet rents a fresh-walk node under its standing ceiling to settle which numbering is right, hub-1's restart held until then, the loader change (re-number the resumed range against the DAG) after that read. THE 0.3.25 PAIRS ON 7bd2940f (the build-server lane, from 10:33:11 BST on build-1 under lease class release, /srv/artefacts/0325-7bd2940f/: the seed about 10:36, the Windows pair about 10:38, the hive package with the three kit zips about 10:41, each minute to the shipper and the coordinator); the c6629572 pairs already built (seed f913e3e7, win 42d0dd57, hive 14d86245) stand in their own folder and are not the cut; the publisher's digest gate on master since 10:17, riding the 0.3.25 app line. THE RE-POINTED APP TIP (the shipper): 92f004f1 on release-0.3.25 (e0d4425f plus the node-source pin to 7bd2940f), the push gate GREEN at 10:32 BST, the box gate GREEN at 10:33:25 (303 + 35 + 8); the cut list's pin candidate 7bd2940f; the kit re-cut from 92f004f1 and the pairs on 7bd2940f's artefact with the build-server lane; the Mac node pair and the DMG rebuilding on 7bd2940f under the lock from 10:32:31; the 13:00 pin and the 13:30 earliest minute standing. The 0.3.25 inputs are all green at 10:33 bar the pin's own gate set and the crossing. A SWEEP FINDING FROM MAIN (10:4x BST): on a rented, power-capped RTX A4000 (114 W cap) class v5 reads 26.0 MH/s against v4's 31.4, 17 percent under, the fingerprint equal; the A100 1.3 percent under; every uncapped consumer card level: v5 costs more compute per hash and a compute-limited card pays, which is what a knee lock makes of a card. Two orders with readings by 12:30: (1) the hash lane sends the 5090's v5 pack rows at the 1,300 lock against v4 at the same lock, and the 5080's if they exist; if v5 at the knee loses more than 2 percent, the knee is re-found under v5 and the tiers table says so; (2) the tiers' engine half: a class change (the chain's program class flipping) invalidates the stored tiers and re-runs the search within ten minutes of the crossing, the first-run line saying why; known-failed first (tiers stored under v4 must read "re-measuring for class v5" after the flip, never apply as if current); on 0.3.25 if it fits by the cut, else 0.3.26 with the record saying the v4 tiers may be off by the measured percentage until the re-tune. Per tier: a locked card may lose a few percent of rate at the class v5 crossing until Ember re-tunes; the number is the 5090 row. THE ORDERS PLACED (the coordinator, 10:4x BST): the hash lane's two readings by 12:30 (the 5090's v5 rows at the 1,300 lock against v4 at the same lock, the 5080's if they exist; the knee re-found under v5 if the loss is over 2 percent; the default if the PC 1 queue cannot run it: the A4000's 17 percent stated for a capped card and "unmeasured at the knee on the 5090"; and ember-tiers-25's class key: a class change invalidates the stored tiers and re-runs the search within ten minutes, known-failed first), the UI lane's class-flip state ("re-measuring for class v5", v4 tiers never applied as current after the flip) and knee note by 12:30, the shipper's cut list carrying both on 0.3.25 only if green by the pin at 13:00, else 0.3.26 with the record's sentence that the v4 tiers may be off by the measured percentage until the re-tune. THE 0.3.25 PAIRS ON build-1 (the build-server lane, /srv/artefacts/0325-7bd2940f/): the seed pair at 10:34:44 BST (igneumd c7fc542b, igneum-miner 4494ecc4, glibc 2.34), the Windows pair at 10:36:13 (igneumd.exe 5d1dea23, igneum-miner.exe eee7bdfa), the hive package igneum-hive-0.3.25-7bd2940f.tar.gz at 10:37:49 (sha d977797f..., the three kit zips, smoked in ubuntu:20.04); the kit re-cut from 92f004f1 (sha 676240f6, 424,540 B) staged in both folders, the PC 1 host from it bc8d4f79 (in host.sha256 at the shipper's 24680e1d), the 0.3.25 Windows payload from 24680e1d cutting. Every pair of the cut exists by 10:38; the pin's gate set and the crossing are the only waits. FOUR NEW LANES ON THE FOUNDER'S ORDER (11:00 BST, "build all this today to close this gap"), mirrored by the coordinator as the shipper's clocks are: the explorer (a5ef1d5801084005b; explorer.igneum.network by 16:00), the canonical DEX and the Sepolia certificate verifier (a74a8267813d6ea34; the AMM by 14:00, the swap UI by 17:00, the verifier by 20:00), the builder pages, faucet and grants (adb29da59baf27898; /build and /grants by 15:00, the faucet by 16:00), three reference apps that only work on a proven chain (a2060899d2a27d31c; /light by 16:00, /receipt by 18:00, the Sepolia oracle demo by 21:00); the build-server lane stands up rpc.devnet.igneum.network by 12:00; they do not touch the 0.3.25 cut, the crossing or the fleet, sharing the boxes' lease pools (class measure) and the master-only deploy; a lane silent past 25 minutes gets the word from the coordinator and then main. THE FAST-TIME GATE ON THE 0.3.25 PAIR: SUMMARY PASS (cross-0325-39f127a1) at 09:54:40Z (10:54 BST) on the pair 39f127a1 (the node code and object byte for byte e0644958's; igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 09:42:25Z to 09:54:40Z, every check green (rung 1 by signal at epoch 6, class v5 by signal at byte 6 from epoch 8 at rung 1 at 9,985 bps, the stale node refused, the restart step resynced in 8 s, four sinks equal, 0 PoW rejections); the ceiling's two new fields absent from the 60x file so the ceiling stayed at never there (the node lane's note); to the shipper the same minute; the pin line names e0644958 and its gates. THE FOUNDER'S WORD AT 11:0x BST ("can we add in any more layers? class rotating? things that would render an ASIC useless as soon as it dropped"): the class v6 design opens today as a rotating family, the research lane and the hash lane under the coordinator, the design doc docs/design/class-v6-rotating-family.md by 18:00 BST with the chip-model rows beside each layer (what it does to k and capex for a fixed-function chip and to the per-joule edge for a GPU-like chip; what it costs every GPU tier, Apple included): (1) per-era draws of the class parameters now fixed by release (the mixer round count within the tested margin, the op-mix weights within the measured safe band, the read width, the program length, the shadow placement), drawn from chain state like the program; (2) the state-derived dataset's size tracking chain-state growth with a floor, so fixed-memory silicon ages out; (3) scheduled family epochs by height (every 180 days by default) with no release; (4) the (c''') acceptance floor and the F8-form uniformity test generalised to each era's parameter draw, redraw on failure, so layers 1 and 3 need no per-era cryptanalysis. Per layer: the gate it needs (the family analysed as a family: the attack board's shape over the testnet period), the known-failed test, an honest line on what a fully general chip still gets. No consensus code this week; the document, the numbers and the gate plan. Per tier for the founder tonight: what each layer does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE ARC RE-READ IN ITS CHAIN (the hash lane, 10:57 UK): no clear came from the shipper, so the default ran at 10:50: the rotate-fold kit's fetch (sha 65b47211) published to PC 2 at 10:51:41, the run (run-ca3-pc2-v5-intel-bench-20261008, the v5 lane's script c0d398a1) in the publish chain behind another lane's publish-jobs.sh sign --deploy from the build-server worktree (the publisher serialises); the fingerprint line by 11:15 if the publisher frees inside ten minutes, else the blocking process named by 11:10. Queued on PC 1 behind the same publisher: run-ca3-pc1-v5lock-5090-20261008 (class v5 against v4 at unlocked, 1,300 and 1,200 MHz, the v5 kit's CUDA packs), its rows by 12:30; the AMD grid after it from about 11:25. The class-key work on ember-tiers-25 started; the v6 cost rows by 16:00 taken. THE TIERS' CLASS-FLIP STATE, THE UI HALF (the UI lane, 10:57 BST): tiers-class-25 at d949e274 on the mirror, off release-0.3.25's tip 24680e1d (the shipper having merged tiers-25 d3d0704a into release-0.3.25 at 111dae69), the crate gate GREEN 303 + 35 + 8 on build-1, the full pre-push GREEN 60, the UI tests 74 green known-failed first (the v4 tiers stayed on the buttons after the flip on d3d0704a); after the flip the table reads "re-measuring for class v5" on every button with the start minute or "queued (within ten minutes of the crossing)", the v4 watts never current, the strip's sentence naming the crossing; the knee note under the table when knee_loss_pct is over 2 percent; the captures tiers-flip-dark.png and -light.png; the fields tiers_class, program_class, tiers_remeasure_at, knee_loss_pct (the shape sent to the hash lane at 10:4x; the engine sha by 12:30); the default: the display rides 0.3.25 inert if the engine half is late and lights up on 0.3.26. THE FOUNDER'S WORD AT 11:1x BST: class v6 is DECLARED with the four layers as its spine (per-era parameter draws, the dataset tracking chain state, scheduled family epochs by height, the acceptance floor generalised to parameters), and deep past-and-future research opens now under the coordinator with serious resources ("see if anything can be optimised, added or invented"; reading public research is in-house, nothing paid or asked of anyone outside): four research lanes today, (A) history (every ASIC-resistant proof-of-work and how it fell or held: Ethash and the E3 and Linzhi chips, ProgPoW's review, RandomX and its chip analyses, Cuckoo, Equihash and the Z9, Argon2 and Scrypt and the Litecoin chips, KawPow, Autolykos, Octopus, kHeavyHash's chips; the exact mechanism each chip used and what the design missed, each mapped to Igneum's layers with "does v6 close it" as a sentence and a number), (B) the hardware future five years out (PIM and processing-near-memory, HBM3e and HBM4, LPDDR6, 3D DRAM, CXL memory pools, wafer-scale, chiplets, FPGA with HBM; for each the chip-model k band against a state-sized dataset and dependent random reads, and the one layer that would blunt it), (C) invention (layers beyond the four, each a paragraph, a known-failed test and a chip-model row: data-dependent program graphs, latency-bound dependent reads tied to the shard proof, randomised memory topology per era, VRAM-size ratchets, proof-carrying hashes sampled by the pool, time-locked parameter commitments, and what the lane invents; rejecting what costs GPUs more than chips), (D) the family gate (how a parameter family is cryptanalysed as a family: sampling bounds, coverage, the F8-form and (c''') tests over the parameter space, the attack board's shape over the testnet period, so layers 1, 3 and 4 can be automatic with a proof of what was tested). Resources: all four boxes under lease class measure, PC 1 by job for card rows, the rented fleet for one-shot measurements inside the ceiling. Deliverables: a first synthesis in docs/design/class-v6-rotating-family.md by 20:00 BST (the four layers priced, every finding from A to D with its number, a ranked list of what v6 adds beyond the four, the honest line on what a fully general chip still gets), the full report by 09:00 tomorrow, one line to main per lane as each lands; per tier at 20:00: what v6 does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE 0.3.25 APP TIP AND PIN CANDIDATE (the shipper, 10:58 BST): the app tip 9b93e649 (push gate GREEN; the crate unchanged from e0d4425f; the node-source pin to e0644958 and host.sha256 bc8d4f79); the pin candidate the node lane's ceiling cut e0644958 (digest 1b37cb9d, every gate green 10:53, the fast-time SUMMARY PASS 10:54, the floor at DAA 82,800 about 16:53 BST, a publish up to 14:53 without a second cut); the tiers' class-key halves: the UI lane's tiers-class-25 d949e274 green and inert alone, merged with the hash lane's engine sha the moment it lands (12:30), gated as a pair on the release tip, riding only if green by the 13:00 pin; the 0.3.24 Windows take 2 failed at a new place (Inno stopped the app and copied nothing); the update-return lane owns the fix on release-0.3.25 by 12:30, the default the 0.3.25 Windows entry waiting for a clean take 3 while Mac and HiveOS move at the minute. THE FOUR CLASS V6 RESEARCH LANES SPAWNED (the coordinator, 11:0x BST, each with its worktree, its box resources under lease class measure, its clocks and the rules): lane A history (a603a938582c43ab5; the first cut docs/analysis/class-v6/history.md by 15:00), lane B the hardware future (a4f73e2a6f2d1b757; hardware-future.md by 16:00), lane C invention (a5dfe95ee8c47cd0f; invention.md by 17:00), lane D the family gate (a07a99a3788566af2; family-gate.md by 17:00); each feeds the research lane's synthesis docs/design/class-v6-rotating-family.md by 20:00 (its outline by 13:00; the hash lane's per-tier rows by 16:00); the full reports by 09:00 tomorrow; the coordinator's lane mirror carries their clocks. A HELD PUSH AND ITS CAUSE (11:00 BST): the hash lane's push of ca3-v4-amend was refused at 10:58 by the gh-account hook reading the founder's gh (his personal login active again; nothing switched by any lane); the cause is the branch's own hook, which predates the per-process fix (34b0884d): the hook runs the branch's tools/ci, so every branch older than 09:58 must merge the mirror's master before its next push, under which the check reads Igneum's own gh directory and skips under the suspension marker; the rule to every lane. Live: the Arc re-read on PC 2 (published 10:59:47) and the v5lock job on PC 1 (published 10:53, about 12 minutes). THE CLASS V6 OUTLINE ON THE MIRROR (the research lane, docs/design/class-v6-rotating-family.md on counter-asic-4, the commit after fb61ed4b, pushed 10:5x UTC, two hours ahead of 13:00): section 0 the founder's table (per layer, what it does to a fixed-function chip and to a GPU-like chip on its release day, and the 5090, 5070 Ti and M5 Max columns, measured where the night's rows exist, the 5070 Ti scaled until the hash lane's row); the honest frame on top: the four layers render a FIXED-FUNCTION chip useless on the first era its wired value leaves (one tape-out lives one era) and move nothing for the stored-dataset chip with a programmable core except the core's size and the N5 project it forces; that chip keeps 3.6x at zero premium and 2.1x at k = 1 on a 5090 at its knee. The layer table (sections 1 and 2) names the bands each draw takes and the measured rows that set them: the mixer in {4, 8, 16} (x16 open), the op-mix weights within B = 4 with shuffle and mulhi capped (shfl 55.8 pJ per op), the read width in {1, 4} words (w64 excluded by the 5 October rows), the block shape 64 to 256 (never 1,024), N left to the ladder's signal (an unconditional draw retires the Apple tier at 200,000). Open numbers asked of the hash lane with defaults at 16:00: the 5070 Ti row (the rented 5070 scaled), the x16 mixer's verifier and build (the chip model's estimate), two re-weighted shadow packs for the op-mix band (the microbench arithmetic). Layers 2 to 4 and the gate plan are skeletons with their sources named, filling by 18:00 with the four research lanes' cuts, the synthesis by 20:00. THE FOUNDER'S WORD AT 11:2x BST ("all builders are idle, load them up"): build-1 to build-4 filled now and kept above 80 percent all day under the lease pool, class measure behind the release gates, in this order of value: (1) the class v6 family gate's sampling runs for lane D (the F8-form census and the (c''') floor over the parameter bands: the mixer {4, 8, 16}, the op-mix weights within B = 4 with shuffle and mulhi capped, the read width {1, 4}, the block 64 to 256; thousands of drawn eras, the uniformity and bucket tests on each, so the family document carries measured coverage tonight); (2) the attack families at scale on the 0.3.25 pin candidate's igneum-pow (F8 to 256 seeds, F9 and F1 to 10^6 on the frozen 1c420786, the day-key scan to 2^28) as the record's strengthening lines; (3) the invention lane's candidate layers measured as packs as fast as it writes them; (4) the full suite matrix of the 0.3.25 pin on every box as the pre-pin check; (5) the Windows and hive cross builds and the sweep's reruns; the lease tool's pre-emption giving release-class work the cores when the pin's gates need them; one line to main at 12:00 with the load on each box and what runs there, then hourly only if a box drops idle. THE DRIFT CLASS SETTLED (the node lane, from the fleet's fresh-walk node, a shared-devnet node synced from an empty datadir to 191,441 chain blocks at 10:03:45Z): hub-1 and five standing boxes number the fresh chain exactly; seven boxes carry numbering inherited from an exec snapshot taken on a chain that later re-walked (+2: p1-4090, p1-a5000, pool-1, build-1's node1; +3: p2-3090-2; +4: p2-3090-4; +5: p1-5090 and p2-3090-3), and a restart on the kept datadir does not re-walk (p1-5090 at 09:22Z stayed +5); the cost: a prover on drifted numbering signs statements the hub vetoes, so the seven earn nothing from proving until they re-walk, the drift refusal stopping the waste. The node lane's word to the fleet: p1-5090 first, both snapshot files moved aside so the executor re-walks from the DAG, the re-walk timed and read against the fresh node, then the other six in series, hub-1 untouched, build-1's node1 after the 12:40Z move; if the re-walk reads over two hours the six wait for the node-side fix on the next node line (the loader re-numbering a resumed range against the DAG before serving). THE 0.3.25 PIN CANDIDATE CONFIRMED (the node lane): e0644958 on both mirrors (keygen, the re-announce, the ceiling switch at 82,800 in the Devnet 3 object, digest 1b37cb9d, the 0.3.24 pin refused both ways), every gate green at 09:53:01Z, the fast-time SUMMARY PASS at 09:54:40Z on the same object; the publish ceiling DAA 75,600 (14:53 BST); waiting only on the 68,400 crossing reading clean (about 12:54; the node lane's line the moment the DAA passes it); the shipper names the pin at 13:00; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. LANE C'S FIRST PACK (the invention lane, 11:0x BST by the Mac's clock; its own line read "12:1x", a clock to correct): build-1 takes the igneum-pow build from counter-asic-4 at 5984ffab, then the per-load shadow in its sound form (mx8+shl6912x1: 16 sub-blocks of 432, one pass, the form 20.2a named and never drew) as the first candidate: the acceptance census over 64 seeds and 16 drawn eras against the 16x27 form and the class v4 shape, the pack export, the F8 read at 2^24 and the verifier bench on a leased core, the first read by 13:30; build-2 next for the second candidate (warp-uniform data-dependent block selection); the candidates with no pack form (the VDF commitment, the VRAM ratchet, the pool-sampled witness, the state-tied reads) stay modelled and the 17:00 cut says so; the worktree igneum-wt-v6-invention on class-v6-invention. THE WINDOWS INSTALLER CLASS AND THE 0.3.25 TIP (the shipper, 11:08 BST): the app tip 139c147a (9b93e649 plus install-detach-25 52a34111, packaging/windows and tools/ci only, the crate unchanged; push gate GREEN); the 0.3.24 take 2 class: an installer started under the app's job runner is a child of the engine, and the engine's kill_tree on quit ended it between PrepareToInstall and the copy; the fix re-launches the installer as a one-shot scheduled task outside the job's tree; the 0.3.24 Windows entry skipped; the rule-14 take on PC 2 is the 0.3.25 installer over the running 0.3.21 app, queued ahead of the Arc re-read; the pin candidate e0644958, the DMG 501ba293 staged, the 13:00 pin and the 13:40 provisional minute standing. THE ATTACK FAMILIES AT SCALE (the attack-pass lane, cores held at 11:08 BST, every run under lease pool class measure): box 2 (88 cores): F8 seeds p66 to p257 (192 new, 256 with the gate's p2 to p65) at 2^24 on class v5 at the freeze 1c420786 (the gated binary 0f5c98dc, pairing e5a4ac5978462156; the leaves re-run on 8f481459 if the kit pairing flips), the window-model control, by-site, as three thirds of 64 seeds; box 4 (80 cores held, 16 asked): F9 to 10^6 on 1c420786 (seeds 100,000 to 999,999 in six chunks of 150,000 at 8 threads, four running), F1 to 10^6 class v5 programs on 1c420786 (one census at 40 threads with the progress line and flushed partials, re-drawing the record's first 10^5 on the way as a reproduction check), the F4 day-key scan to 2^28 on 8ca66afa's redraw rule at 8 threads; nothing on build-1 or build-3 (lane D's); the projections: F4 about 2 to 3 hours, F8's 192 seeds about 9 hours, F9's 900,000 and F1's 10^6 about 30 hours each, so the 17:00 default is partials for those two with the lane (d) rows carrying counts so far; any pre-emption by release-class work reported. THE RPC AND THE 0.3.25 PAIRS ON THE PIN CANDIDATE (the build-server lane, 11:0x BST): rpc.devnet.igneum.network up since 11:08 BST (the first of the founder's builder clocks, 52 minutes ahead); the 0.3.25 pairs on e0644958 running on build-1 since 11:06 (the app tip 139c147a), the Windows and hive crosses on build-2, build-3 and build-4 as reproducibility rows at class release by about 12:40; the sweep reruns' list not held by the lane, the default at 12:30: last night's sweep logs on build-1 read for rows that ended without a result line and those rerun at class measure. THE SWEEP RERUNS' LIST (the fleet lane to the build-server lane, 11:1x BST): the fleet ran nothing under the build boxes' lease pool last night (every fleet bench a rented GPU one-shot), so the rows the lease kills cut short are the hash and class lanes' and the build-server lane's default read on build-1 is the right one; the fleet's own rows without a result (A10, A40, A100 40 GB, H100 NVL, H100 PCIe, MI250, RTX 3050, RX 7800 XT, 7900 XT, 7900 XTX, 6900 XT) are provider gaps needing a GPU host, rerun the moment a provider lists one. THE CLASS-FLIP TIERS, BOTH HALVES (the UI lane, 11:13 BST by the Mac's clock, 1 h 47 min inside the 13:00 pin): tiers-class-25 at 081b3ba7 (the display d949e274 plus the hash lane's ember-tiers-25 0a838072, on release-0.3.25's 9b93e649; the field names matched exactly): the crate gate GREEN 305 + 35 + 8 on build-1, the pre-push GREEN 60, the UI tests 78 green known-failed first, the push gate GREEN; with the shipper. A RED ON THE RELEASE TIP, for the shipper and the update-return lane: release-0.3.25's 139c147a is red on one crate test (ota::return_tests::no_relaunch_while_an_installer_runs_and_a_relaunch_when_it_clears, 304 of 305): install-detach's 0c588b09 reshaped the installer's clear step into a multi-line block while the test asserts the one-line literal at app/igneum-app/src/ota.rs:1348; 9b93e649 passes; the fix is the test's literal on the install-detach line; the UI lane built on 9b93e649 so its tip is green alone. A RED FROM THE PIN MATRIX (the CI steward, 11:13 UK): the core suite fails on the pair (the node e0644958 with the app tree 9b93e649): config::params::tests::fast_time_60x_file_is_the_devnet_at_60x panics "override-60x.json lacks the field base_unit_decimals"; the field was added by 0e4ec18a on ca3-v4-node yesterday at 21:45 UK and reached neither master, release-0.3.25 nor the app tip while the node line's test demands it; so every box reads red on core, and the fix is one line on release-0.3.25 (the cherry-pick of 0e4ec18a, or "base_unit_decimals": 8 in infra/fast-time/override-60x.json); sent to the shipper; green so far pow and app on build-1 and build-3; the two new boxes' toolchains read the same as build-1 (Ubuntu 24.04.5, glibc 2.39, the pinned rustc, sccache and lease, no nvcc). The founder's fourth load item paid in its first ten minutes: a red no single-box gate had read. MAIN'S WORD ON THE TWO REDS (11:1x BST): the install-detach fix belongs in 0.3.25 if it can make it, since a Windows install by any path that lets the engine's job runner kill the installer mid-copy is the plug-tune-play fault class (an update a user repairs by hand); the default order: the update-return lane fixes the ota.rs literal by 12:00; if 139c147a plus the fix is green on the crate gate by 12:15 the cut goes from it, else from 9b93e649 with the detach on 0.3.26 and the record saying Windows installs by job stay unreliable until then; the missing 60x field: the CI steward lands the one-line field on master and the release line by 11:45; the pin slides under the shipper's authority inside 14:53. THE DAY-KEY SCAN TO 2^28 (the attack-pass lane; class-v5 8ca66afa's redraw rule, build-4 under lease pool 8 class measure, 379.2 s, census-2p28.md at 10:15Z, 11:15 BST): days with any gain over 1.1x: 0 of 268,435,456 on M1 (median 226), 0 against the mean, 0 on M2, 0 on ROT and RC; the M1 cost mean 225.791, sd 6.073, min 206 (day 27,016 at 1.0971x, the redraw rule's floor: no day under 206 in 2^28), max 258; every weak class on its analytic expectation (ROT any pair summing to 32: 160,354,008 against 161,256,979; RC any zero: 1 against 1.0, at cost 234, no gain; RC with rk = 0: 87 against 72, 1.8 sigma; the two cells under expectation the rule's own refusals). PASS: no chip buys a weak day in the first 735,000 years of days; at most 1.097x on the best day. The row and f4-weakday.md section 10 committed on attack-pass at eabb4b0e, the push held by the branch's old hook (the fix: merge master, under which the check reads Igneum's own gh directory and skips under the suspension marker). THE SWEEP RERUNS' READ (the build-server lane, 11:18 BST): build-1's records hold no hash-lane or v5-lane run the pool cut short (preempt.log: three TERMs all night, every one to an adv-class holder pre-empted by a release gate, not reruns by rule; no reaped.log; builds.jsonl for 18:00Z to 09:00Z 150 rows with no signal end, the non-zero rows the fast-time gate's designed failed cases and build errors; the census and fingerprint suites leaving no builds.jsonl row and no output directory ending without its result); live at 11:17Z the family gate's v5_attempts_census holding 24 cores on build-1 at class measure; the default at 12:30 if neither lane names a run: no reruns, the boxes carrying the e0644958 reproducibility crosses (build-3's Windows pair already read: igneumd.exe 4b0c3aeb, igneum-miner.exe b3da4088) and the gates. The founder's fifth load item is therefore the crosses, not reruns. The attack-pass branch merged master and pushed (460fd9fa, the F4 2^28 row and f4-weakday.md section 10 on the mirror; the hook skipping the gh read with its suspended line; nothing switched). THE FAMILY GATE'S FIRST COVERAGE (lane D, 11:2x BST by the Mac's clock; its own line read "11:3x"): the harness live on build-1 under lease pool class measure (scripts and pinned binaries under /srv/builds/_adv-family-gate/): (1) the base control v5_attempts_census on the shipped class v5 draw over f8-label seeds 1,000 to 11,000, 24 cores since 11:16; (2) the family harness family_gate_era_census (branch family-gate-v5 = class-v5 8f481459 plus the harness, never a chain path; the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE): one drawn era per seed, every layer-1 parameter from the era's own stream (the shadow block {64, 128, 256} x {108, 54, 27}, the mixer {4, 8, 16} recorded, the read width over {1, 4} words, the ten weights within B = 4 with shfl and mulhi never raised), the chain draw through the real rule with every candidate's first failing part, then on the accepted program at the rule's own 2^20 sample the (c'')/(c''') ratio, the largest 256-item bucket per site (ratio and sigma), the index-bit bias per site in sigma; the 16-era smoke run PASSED at 11:21 (about 10 core-seconds per era; 10,000 eras about 28 core-hours). THE WORST READINGS IN THE 16: (a) the index-bit bias read fires HARD on 7 of 16 eras, |z| 130 to 511 at one site, every one at address bit R (the era's stride rotation) or R+1 (era 15 with R = 25 bit 25 z -511 at P(bit) 0.25, a product's bit 0; era 7 R = 17 z -468; era 5 R = 26 z -440; era 13 R = 1 bit 2 z -255, a product's bit 1 at 3/8; era 1 R = 6 z -224; era 12 R = 5 bit 6 z -130; era 6 R = 18 z +256, an or-shaped source at 5/8), the other 9 under |z| 3.8: adv-cache-2's era-stride class measured at the acceptance's own sample on class v5 accepted programs: not diffuse at the bit level, a 25 percent bias on one address bit of one site in about 40 percent of drawn eras, which (c''') does not see (min ratios 0.9954 to 1.0000); a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50, about 1.6 percent of a hash's reads at f = 1/2 for one site, which does not move the f = 1 verdict but is an auditor's flag on "uniform random reads"; the lever is load_index's form (fold the product's low bits before the rotation), not a floor (a 6-sigma refusal would redraw about 40 percent of epochs): a class v6 design row. (b) The (c'') ratio min 0.9954 (era 7), the rest 0.9965 to 1.0000. (c) Attempts: 14 of 16 accepted at attempt 0 or 1; era 9 (shape 64, width 4, mul 11 and or 8 of 75) took 24 candidates: the lossy corner raises r, the exhaustion number to read per stratum. (d) The largest 256-item bucket: ratios 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets, +4.4 sigma), so the F8-tail bound must be stated in sigma, not ratio (the sigma column in the rebuild). Next: the random stratum (10,000 eras) and the corner strata (the lossy cap, width 4, shape 64, 3,000 each) on build-1's free 64 cores, then build-3 and build-4; the first cut of family-gate.md drafted, the measured coverage table in at 16:xx for the 17:00 cut. THE OTA TEST LITERAL FIXED (the update-return lane, 11:23 BST, ahead of both clocks): ota-test-25 off release-0.3.25 139c147a, tip 53cb2f73 on the mirror, one test-only commit (the test reading the installer's clear step as the begin/end block the detach made it; the detach's behaviour kept), the box 2 crate suite 303 + 35 + 8 passed, 0 failed, the full gate GREEN 60; the shipper's cut tip 139c147a plus this commit, so the install-detach rides 0.3.25 and the PC 2 rule-14 take runs on it. THE 60x FILE, THE WHOLE FILE NOT ONE FIELD (the CI steward, 11:25 UK): the test names the first missing key in key order; with base_unit_decimals in it named emission; the file on master and release-0.3.25 lacks six keys the 0.3.25 node line's OverrideParams has (base_unit_decimals, pool_split_activation_daa, program_class_v5_activation_daa, proving_base_fee_ceiling_multiple, proving_fee_ceiling_activation_daa, subsidy_per_block_activation_daa); ca3-v4-node's copy (81 keys, master's 75 plus those six, no shared value differing) passes on build-3 by hand; release-0.3.25 got the one-field commit 907fdaf4 at 11:23 and the whole-file commit follows through the hook's gate, master the whole file behind the one-field landing; the known-failed on record on all four boxes; the green from the core re-runs in the 12:30 matrix; the risk named to the shipper: an older daemon reading the file with deny_unknown_fields. THE INDEX FOLD AS A CLASS V6 DESIGN ROW (the research lane, docs/design/class-v6-rotating-family.md on the mirror, the commit after 206e81e1): load_index folds a product's low bits before the stride rotation so no era's R lands a biased bit on an address bit (a design row, not a draw and not a floor); the evidence lane D's 7 of 16 drawn eras at |z| 130 to 511 on address bit R or R+1 with the (c''') ratio blind to it; the chip row 1.6 percent of a hash's reads at f = 1/2 for one site and zero at f = 1; the cost 0 on every card (one xor-rotate on the address path); the known-failed test lane D's 7 of 16 reading 0 of 16 with the fold; the value-level bias test in layer 4 ordered after the fold as its guard; the F8 tail's largest-bucket bound restated in sigma against its own window's Poisson expectation. The 60x commits: the one-field commit on both lines (master 7be52d76 at 11:24, release-0.3.25 907fdaf4 at 11:23), the whole-file commits in their gates behind it (release cbbaa8c4 pushing, master's queued). CLASS V5 AT THE KNEE ON THE 5090 (the hash lane, run-ca3-pc1-v5lock-5090-20261008-b, 11:09 to 11:21 UK, the 5090 alone, the v5 kit's CUDA worker on the rotate-fold build 8f481459, 60 s rows, the cleared helper sequence; an hour ahead of main's 12:30 clock): the same genesis seed, class v4 against class v5: unlocked v4 135.82 MH/s at 458.3 W (0.296 MH/W), v5 135.90 at 474.3 W (0.287); at 1,300 MHz v4 125.92 at 294.0 W (0.428), v5 125.93 at 299.8 W (0.420); at 1,200 MHz v4 115.69 at 273.3 W (0.423), v5 115.87 at 278.6 W (0.416); the Devnet 3 epoch-0 v5 pack (another seed, the fingerprint 82b19cbde8557ea5 matched on every row): unlocked 136.94 at 494.4 W, 1,300 134.10 at 315.6 W (0.425), 1,200 128.51 at 302.2 W (0.425). THE READING: at the knee class v5 loses 0.0 percent of rate against class v4 and costs 2.0 percent in watts (1.9 percent per hash), under main's 2 percent line, so the v4 knee stands, the tiers table says the class v5 rows are within it, and the UI lane's knee note stays off (knee_loss_pct 0 on the 5090); the A4000's 17 percent is a capped card's number: the 5090 at 1,200 MHz holds v5 level with v4 too, so the loss appears only where the power cap, not the clock, is the limit. Per tier for the founder: a 5090 or 5080 owner on a knee lock loses nothing at the class v5 crossing; a power-capped card (a datacentre card at its cap) loses up to 17 percent until its cap is raised or its class re-tuned. The 5080's rows after the v6 packs job if wanted; the AMD grid live on PC 1 since 11:25 (24 points, about 32 minutes). LANE B'S FIRST READING, RELAYED BY MAIN (11:2x BST), WHICH CHANGES THE CHIP MODEL AND LEADS THE 20:00 SYNTHESIS: a 2 GiB SRAM full store on one N2 die (about USD 500 of silicon, an N2 project of USD 100 M to 500 M) reads 13x to 17x the 5090 per joule at zero shadow and 2.7x to 4.8x with the shadow at the measured k band; layer 2 (the dataset tracking chain state) moves its capex, not its joules; the custom HBM4E base die (2027 to 2028) 6.5x to 14x, untouched by the four layers; PIM structurally blind to dependent random reads; and the M5 Max at 3.1x the 5090 per joule is the honest denominator. MAIN'S ORDERS: (1) chip-model-v3 gains the SRAM-store row and the HBM4E base-die row with lane B's figures and their claimed or measured marks; (2) the synthesis states the per-joule edge against the SRAM store honestly (3x to 5x with the shadow) and against the M5 Max, and prices the one layer that answers it: a dataset floor that grows on a schedule faster than SRAM cost falls, with the cost to a 12 GB and a 16 GB GPU and to 16 GB unified Apple memory stated; (3) the served chip line ("2.1x per joule at the knee") is reviewed at 20:00 with the measured basis for each clause; no served text changes before the synthesis, and if the SRAM-store reading stands the line becomes the honest range with the project cost and the clock beside it. THE SHIPPER'S THREE READINGS (11:2x BST): (1) override-60x.json: every reader in the tree is the fast-time harness, the sims and CI; no daemon on the fleet loads it; the app manifest's consensus.override is a separate 16-key object carried from the live manifest and untouched by the cut; the live chain's object is the digest's (1b37cb9d on e0644958); the harness's file only, the cut stands. (2) The cut tip cbbaa8c4 on release-0.3.25 (907fdaf4 plus the steward's whole-file commit; the crate and packaging trees byte-identical to 907fdaf4's, whose crate gate read 305 + 35 + 8 at 11:24; override-json-check passing): amd-clock-25 e2962b89, tiers-25 d3d0704a, the Intel header, the tiers class-flip pair 081b3ba7, install-detach-25 52a34111 with its test fix, the node-source pin e0644958, the host bc8d4f79, the fast-time file; the Mac DMG on it afa7f527 (45,766,741 B, the node pair 556926b1/d2dfe966), staging. (3) The knee note off on the 5090 rows. The pin at 13:00 on e0644958 and the 13:40 provisional minute standing; the matrix on cbbaa8c4 and e0644958 the steward's by 12:30. LANE B'S FIRST CUT ON MASTER (34f63b3c at 11:25 UK, four hours and thirty-five minutes ahead of its 16:00 clock): docs/analysis/class-v6/hardware-future.md with the three findings and the k bands (with the research lane, into the synthesis's section 7a on counter-asic-4 at ad37a50c); lane B's four decisions in its section 7 with defaults (the draw bounds by 20:00 via the synthesis; the dataset schedule unchanged; the M5 Max as the reference joule; the clock unchanged); nothing built or benchmarked, gh untouched; the full report by 09:00 adds detail only, no k band moving. LANE A'S FIRST CUT ON MASTER (docs/analysis/class-v6/history.md, 300 lines, merge 4c58ad65 at 11:26 UK, three and a half hours ahead of its 15:00 clock; the full gate GREEN 73 checks; primary documents read from the PDFs: the Least Authority and Bob Rao audits, Kik, EIP-1057, the RandomX design and v2, Tromp's README, the Fudan Equihash solver, Percival's lookup-gap note): 21 chip rows by mechanism (what each chip specialised, the miss, the timeline, the v6 layer, closed or not, the per-joule number), the in-depth sections (Ethash, ProgPoW, RandomX, Cuckoo, Equihash, Scrypt and Argon2, the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows), the four layers against the history layer by layer, the tier consequences. THE HONEST VERDICT WITH THE NUMBER: the chip that stores the dataset (class C: every Ethash chip, the E3 at 1.0x, the Linzhi at 2.1x, the Jasminer X4 at 5.1x via DRAM hybrid-bonded onto a 40 nm logic die, the E9 Pro at 4.1x) is NOT closed by any of the four layers, every per-era draw and family epoch being firmware to it; v6 inherits 5.1x per joule on GDDR7 at zero premium (3.6x at the 5090's knee, 2.1x with the class v4 shadow at k = 1), USD 2.8 against 14.7 per MH/s; classes A, B, D's governance half and E are closed, mostly since v2 and v3. THE THREE LESSONS THAT BIND: (1) the stored-dataset chip is firmware-immune to every draw; only joules and memory growth move it; (2) automatic change beats the human fork only where it costs the chip a redesign, and the one such parameter is the memory: layer 2 as declared is not an anti-chip rate (a 32 GB board lasts 60 years at 0.5 GiB a year; the 8 GB card is out at year 12; the E3 the only chip a growth rule ever killed, 20 to 27 months after shipping, at the fleet's own 4 GB limit), so its floor and a per-tier ceiling are the numbers to fix, not the rate; (3) a steered address pattern is always found after launch unless the test lives in the acceptance rule, and every drawn parameter changes layer 4's null, so the census re-derives per era (2.2 s per candidate). CORRECTIONS TO THE 5 OCTOBER FILE: the Antminer X9 withdrawn May 2026 with zero units (not "July 2026 delivery"); RandomX v2 released 25 March 2026 with activation pending (not "no fork"); CryptoNight's secret chips at about 33 months, not 43; Vorick's "survives forks at under 5x" and "13 months for a startup" on no fetched page, marked unverified. Two asks with defaults: layer 2's ceiling (if no word by 20:00 the full report drafts it as GB per tier per year keyed to card-lifetime-2026-10-05.md, with the flag that a dataset tracking state literally outgrows every card inside a decade if state grows as Ethereum's did); the hardware file cross-cited, not repeated. The lane's web-search budget spent (200 of 200); further additions by direct fetch. LANE D'S STATE (11:2x BST by the Mac's clock; its own line read "11:5x"): the first cut committed on class-v6-family-gate at 55c0dc6a with the full gate running; the census at 640 random eras, 298 lossy-cap, 327 width-4 on build-1 and about 500 shape-64 on build-3, the two build-4 corners queued behind a full pool; the landing on the gate's GREEN, the measured coverage table in the 17:00 cut. THE SNAPSHOT DIGEST STAMP (the node lane, 11:2x BST; a wip on release-0.3.25-node under its suites since 10:28Z): every snapshot a node writes carries its consensus digest as a new last field (the day-streams field's fallback shape, so 0.3.24 files decode with no stamp); a node with its digest set refuses a snapshot stamped under another digest ("re-executing from genesis") and one with no stamp ("written by a node before 0.3.25"), the follower starting at genesis; the daemon sets the digest from its params; the tests known-failed first (another digest refused, an unstamped file refused, nothing loaded; a matching stamp resumes, the written file carries the stamp, a digest-less process resumes as before, the wire round-trips); if the suites read green the full gate set runs and it is in the pin at 13:00 BST. THE CONSEQUENCE FOR THE MOVE: every Devnet 3 node restarted on 0.3.25 re-executes from genesis (no file written before 0.3.25 carries a stamp), so the restart takes the chain's re-execution time, which a fresh 0.3.25 node on build-1 since 10:24Z measures now (about 30,000 chain blocks; the rate in the pin line). TWO READINGS BESIDE THE CAUSE: (a) build-1's three nodes differ at 26247 (node1 0x3f53a7b9, the seed 0x717e7dc8, the observer 0x4548c319), and the seed and node1 differ at block 0 already (0x275b0cce against 0x7e37a9fb), which the ba75bf6f file alone does not explain (both resumed their own files across the same restart; the seed also restarted at 02:00Z on 2720d8d2 from a 0.3.22 file); the fresh node's genesis root and its first divergence from each decide whether a second class (an older-object file on the seed, or the resume itself) is in play; (b) the fleet asked for the roots at 26247 and 15611 on hub-1's Devnet 3 node, dn3-g1 and every prover by 12:30 BST with each node's resume line. The loud status for a vetoed node (a veto counter, the last veto's line on the explorer's status, "state not fresh") on the same line if the suites leave time, else 0.3.26, the node lane's word at 12:30. MAIN'S WORD ON LANE A'S ASK (11:2x BST): the default stands (the GB-per-tier-per-year table keyed to the card-lifetime file, with the flag), and one schedule to price beside it so the 20:00 reading carries a decision: a dataset floor of 6 GiB at the v6 epoch (every 8 GB card keeps mining with its cache; the 6 GB 2060 tier drops), 10 GiB two years on (the 8 GB tier drops), 14 GiB at four years (12 GB drops; 16 GB and Apple 16 GB unified hold), each step by height like a class epoch, the schedule itself a consensus field, with the cost per tier stated as the year each falls off and the share of today's measured cards that is; against the chips: the hybrid-bonded DRAM chip sized at launch (the E3 class) dies at the first step it cannot carry, the SRAM store pays capex only, both said. Lane A's corrections to the 5 October file go into the record and the served texts tonight. MAIN'S WORD ON THE STAMP AND THE GENESIS CLASS (11:3x BST): the stamp rides the pin; the re-execution time goes in the pin line and the move plan per tier; the fleet staggers the restarts in thirds so the proving share never reads zero, and the hourly line says "re-executing" with the count until the last prover is back. The second class is a GATE, not a note: the seed and node1 differing at block 0 means one of them runs a different execution genesis, and a hub node on a wrong genesis is worse than any snapshot drift; the pin is not named until the node lane says which file each of build-1's three nodes and hub-1 loaded at genesis, which root is the network's (the fleet's roots at 26247 and 15611 decide it), and the wrong one is corrected or re-walked; if that is not read by 13:00 the pin waits inside the 14:53 ceiling and the shipper slides by its authority. The vetoed-node status rides 0.3.25 if green, else 0.3.26. THE 60x FILE LANDED (the CI steward, 11:31 UK, ahead of 11:45): release-0.3.25 cbbaa8c4 (the whole 81-key file on 907fdaf4, the hook gate GREEN 60) and master e295c0d5 (the same file, the gate GREEN 73); known-failed to green on record: core RED on the one test on all four boxes before, core GREEN on the fixed pair on build-1, build-3 and build-4 after, build-2's re-run running; the full matrix by 12:30. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule From 9975a4679f0227baaa40149b03198d3d9ae2e626 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:33:29 +0000 Subject: [PATCH 08/11] Export exclude: docs/analysis/class-v6 (the class v6 research lanes' documents are research for the team, box paths and lane ids in them; the identity grep hit the machine-name pattern in the invention file's header) Co-Authored-By: Claude Fable 5.1 --- tools/ci/export-exclude.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/ci/export-exclude.txt b/tools/ci/export-exclude.txt index 76af5a1a3..a36d654c8 100644 --- a/tools/ci/export-exclude.txt +++ b/tools/ci/export-exclude.txt @@ -19,3 +19,6 @@ docs/analysis/mission # copied logs are research and operations documents, not public export; the public text is the served sentence main landed. docs/analysis/cryptanalysis docs/plans/cryptanalysis +# 8 October 2026: the class v6 research lanes (invention, hardware, history): research documents with box paths, lane ids and the +# operations record, written for the team; the public spec mirror carries none of them +docs/analysis/class-v6 From fd32fdc5ce2e61a683b2314978d342738adbcb05 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:38:53 +0000 Subject: [PATCH 09/11] Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK) docs/analysis/class-v6/history.md 4.2a: main's 6, 10 and 14 GiB steps checked against every tier's room under the standing 75 percent budget rule (the card-lifetime method, the bench table's 32 measured consumer cards as the population): 6 GiB does not fit the 8 GB tier under the rule (78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent), 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2, 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above; beside it the schedule that drops the tiers in the order main named (5.5 GiB at the v6 epoch, 8 GiB at two years, 11 GiB at four) with the year each tier falls and its share of the measured cards (6 GB 3 percent at day one; 8 GB plus the 10 GB RTX 3080 plus Apple 16 GB 25 percent at year 2; 12 GB 22 percent at year 4; 16 GB 28 percent at the 16 GiB step; 24 GB and above hold). Against the chips: the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 more of GDDR7 on a USD 470 part; about 3x the memory die area for the Jasminer shape); the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. The fleet's hashrate-weighted card census is owed. The arithmetic is checked by script against the card-lifetime working sets. Co-Authored-By: Claude Fable 5.1 --- docs/analysis/class-v6/history.md | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/docs/analysis/class-v6/history.md b/docs/analysis/class-v6/history.md index 0a2b802f1..451aabf0b 100644 --- a/docs/analysis/class-v6/history.md +++ b/docs/analysis/class-v6/history.md @@ -234,6 +234,39 @@ The arithmetic that binds. A chip's memory is bought by the board, and today's p So layer 2 as a rate "tracking chain state" ages out fixed-memory silicon only if the dataset grows faster than a chip generation's memory headroom, and every rate that does that retires the honest small cards first by the same table. The E3 is the only case in the record where a growth rule beat a chip, and it beat a chip that had under-provisioned memory by a factor the card fleet also hit (4 GB). The rule that would hurt the f = 1 chip is one that keeps the dataset above what one board of commodity DRAM holds at the chip's price point, and that rule is unaffordable for the honest fleet. The honest reading: layer 2 is the right lever class (the memory is the one parameter a stored-dataset chip cannot read as firmware), and its value is set by the floor and the ceiling, not by the tracking: a floor keeps the dataset above every SRAM die (class B stays closed: 2 GiB is 1,000 mm^2 of SRAM even at N5), and a ceiling keeps it under the honest tiers' memory. Between those two lines the chip's board holds whatever the card holds, and the growth rate changes nothing for it. What "tracking chain state" adds over the fixed schedule is governance (no release decides the size) and the class v5 link (the dataset is built from the state, so the size follows the state's record count naturally); it is not an anti-chip rate. Resolved by the synthesis lane (11:2x UK, `docs/design/class-v6-rotating-family.md` section 7b on `counter-asic-4`): layer 2's rule carries a per-year ceiling as its first constant, the fixed schedule's power-of-two step for that year, so the chain's state can bring a step forward and never add one; "retires cards before chips" is recorded as the reason the ceiling exists. Under that rule the table above is the ceiling's own schedule, and the honest 8 GB tier's year-12 line stands whatever the state does. What this file adds for the record: if the chain's state grew the way Ethereum's did (approximate, from memory: the account and storage state passed 100 GB in its eighth year), a dataset tracking it with no ceiling would have outgrown every consumer card inside the first decade; the ceiling is what makes layer 2 a governance rule and not a fleet-retirement rule. +### 4.2a One schedule, priced (main's ask of 11:2x UK, for the 20:00 reading) + +Main asked for one dataset-floor schedule priced per tier and against the chips, so the 20:00 reading carries a decision: 6 GiB at the v6 epoch, 10 GiB two years on, 14 GiB at four years, each step by height like a class epoch, the schedule a consensus field. The method is `card-lifetime-2026-10-05.md`'s: a card's room for the dataset is its usable memory (75 percent of card memory, the standing rule "the whole working set under 6 GB on an 8 GB card"; 50 percent of Apple unified memory) less the non-dataset working set (best: 32 KiB scratch, the cache freed after the build, 254 to 479 MiB by tier; worst: 128 KiB scratch, the cache resident, 600 to 1,500 MiB). The population is the bench table's measured cards (`site/miner-bench.json`, 8 October 2026: 32 distinct consumer cards, one Apple part, eight datacentre parts); the fleet's own card census is not a file this lane could find and is owed, so the shares below are by count of distinct measured cards, not by hashrate. + +**What the memory arithmetic says about main's three steps.** A step fits a tier when the dataset plus the working set is under the tier's usable memory. + +| Step | 8 GB (usable 6,144 MiB) | 10 GB (7,680) | 11 GB (8,448) | 12 GB (9,216) | 16 GB (12,288) | Apple 16 GB unified (8,192) | 24 GB (18,432) | 32 GB (24,576) | +|---|---|---|---|---|---|---|---|---| +| 6 GiB (6,144 MiB) | **does not fit the rule**: 6,398 best, 6,744 worst, 78 to 82 percent of the card; fits only if the budget rule moves to about 85 percent (a headless rig with no display) | fits (6,404 best, 63 percent) | fits | fits | fits | fits (6,432 MiB, 79 percent of its usable half) | fits | fits | +| 10 GiB (10,240 MiB) | out | out | out | **out**: 10,506 best, 10,888 worst, 86 to 89 percent | fits (10,518, 64 percent) | out | fits | fits | +| 14 GiB (14,336 MiB) | out | out | out | out | **out**: 14,614 best, 15,032 worst, 89 to 92 percent | out | fits (14,752, 60 percent) | fits | + +So main's schedule as stated retires, under the standing budget rule: at 6 GiB the 6 GB tier and, unless the rule is loosened to about 85 percent, the 8 GB tier (22 percent of the measured consumer cards: the RTX 3070, 3070 Ti, 3060 Ti, 4060, 4060 Ti 8 GB, 5060, 2070 Super) on day one; at 10 GiB the 10, 11 and 12 GB tiers and Apple 16 GB (another 31 percent: the RTX 3080, 1080 Ti, 2080 Ti, 4070, 4070 Ti, 4070 Super, 5070, 3080 Ti, 3060, Arc B580) at year 2; at 14 GiB the 16 GB tier (28 percent: the RTX 5060 Ti, 5070 Ti, 5080, 4080, 4080 Super, 4070 Ti Super, 4060 Ti 16 GB, RX 9070 XT, RTX A4000) at year 4, leaving 24 GB and above (16 percent of the measured consumer cards, plus every datacentre part). That is not the tier order main's note describes, so the schedule that drops the tiers in that order is priced beside it: + +| Step | Dataset | Year | Who falls off (share of the 32 measured consumer cards) | Who holds, and at what share of card memory (best / worst) | +|---|---|---|---|---| +| v6 epoch | 5.5 GiB (5,632 MiB) | 0 | the 6 GB tier (RTX 2060: 3 percent) | 8 GB at 72 / 76 percent (the worst case one point over the rule); 10 GB 77 percent; Apple 16 GB unified at 72 percent; everything larger | +| +2 years | 8 GiB (8,192 MiB) | 2 | the 8 GB tier (22 percent), the 10 GB RTX 3080 (3 percent: 8,452 of 7,680), Apple 16 GB unified (8,480 of 8,192) | 11 GB at 100 percent of usable (the 1080 Ti and 2080 Ti: out in practice, 6 percent); 12 GB at 69 / 72 percent; 16 GB; 24 GB; 32 GB; Apple 32 GB at 52 percent of its usable half | +| +4 years | 11 GiB (11,264 MiB) | 4 | the 12 GB tier (22 percent) | 16 GB at 70 / 73 percent; 24 GB at 48 percent; 32 GB; Apple 32 GB at 71 percent of its usable half | +| the fixed schedule's own steps beyond | 16 GiB | the year the state brings it forward, else year 28 | the 16 GB tier (28 percent); Apple 32 GB | 24 GB at 68 percent; 32 GB | + +Reading, per tier, in the form main asked for (the year each falls off, and the share of today's measured cards that is): on the priced schedule the 6 GB tier falls at the v6 epoch (3 percent), the 8 GB tier and the 10 GB RTX 3080 and the Apple 16 GB laptop at year 2 (25 percent of the consumer cards plus the base Apple laptop), the 11 GB Pascal and Turing parts in practice at year 2 (6 percent), the 12 GB tier at year 4 (22 percent), the 16 GB tier at the 16 GiB step (28 percent), and 24 GB and above hold through every step priced. On main's schedule as stated the same tiers fall two years earlier each, and the 8 GB tier falls on day one unless the 75 percent rule moves. Either way this is the fleet-retirement rule the ceiling exists to bound (section 4.2): a step every two years retires a quarter of today's measured consumer cards each time. + +**Against the chips, with the number.** Three chips, by what the step does to each: + +| Chip | What a step costs it | The number | +|---|---|---| +| The hybrid-bonded DRAM chip sized at launch (the Jasminer X4's shape: DRAM dies bonded to the logic at tapeout, 5 GB per unit in 2021; the E3's shape in commodity form, 4 GB of DDR3 soldered to the board) | its memory is fixed at tapeout, so it dies at the first step it cannot carry, as the E3 did 20 to 27 months after shipping. On main's schedule a chip sized to the 6 GiB floor with 8 GB of bonded DRAM dies at the 10 GiB step (year 2); on the priced schedule a chip sized to 5.5 GiB with 8 GB dies at the 8 GiB step (year 2); a chip sized with 16 GB holds through year 4 on both and dies at the 16 GiB step. But the schedule is a consensus field read at genesis, so a maker sizes to the step it wants to survive: the X4's 5 GB was Ethash's DAG plus a year, chosen off a public schedule; the E3 died because its memory was sized to the CARD FLEET's limit, not to the schedule | kills only the chip that under-sizes; sizing to 16 GB costs the X4 shape about 3x its 2021 memory die area (approximate) and the E3 shape USD 160 more of GDDR7 (8 x USD 20, chip-model-v3 5.1) on a USD 470 part | +| The f = 1 GDDR7 chip on a board (the record's class C; 16 x 2 GB devices, 32 GB) | nothing until the dataset passes 32 GB: every step priced here fits its board; a bigger step buys more devices at USD 20 per 2 GB | USD 0 per step through 16 GiB; its 5.1x per joule and USD 2.8 per MH/s stand at every step | +| The SRAM store (the f = 0 recompute chip holding the cache on die) | the dataset's size costs it nothing (it derives every item); the CACHE's doubling under option C costs it capex only: 128 mm^2 and USD 46 per good die at 256 MiB, 255 mm^2 and USD 111 at 512 MiB (year 4 on the fixed schedule, or the year the state brings the doubling forward), 510 mm^2 and USD 306 at 1 GiB; and the mirror's size is what forces it onto a 7 nm or better node (the 5 October file, section 2.5) | USD 46 to 111 per die at the year-4 doubling; its edge stays 0.92x at the op budget and 1.86x per joule (`chip-model-v3.md` 5.4), unmoved by the dataset's steps | + +The honest sentence for the 20:00 reading: the dataset-floor schedule is a fleet-retirement rule with a chip tax of USD 0 to 160 per unit on the chips that matter (classes C and B), and it kills only a chip whose maker ignores a public consensus field; the one precedent of a growth rule killing a chip (the E3) is a precedent of a maker sizing to the fleet, not to the schedule. If the schedule is adopted, the 75 percent budget rule and the 6 GiB floor cannot both stand for the 8 GB tier; 5.5 GiB keeps the 8 GB card inside the rule in the best case and one point over in the worst, and the headless-rig reading (about 85 percent) is what makes 6 GiB fit. The fleet's hashrate-weighted census is owed before the share column is read as a hashrate share. + ### 4.3 Layer 3: scheduled family epochs by height, every 180 days, no release What is declared: a new instruction family goes live on a height schedule, every 180 days by default, with no release (the reserve of spec 1.13.2, ordered at genesis). The record of scheduled change against chips: From ba08d6b8a3ebeb6c816cd18b05a0e5717b0220b0 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:39:24 +0000 Subject: [PATCH 10/11] Bench table: the class v4 watts rerun, first six rows (RTX 5070 176.1 W, 4070 Ti Super 137.8, 4070 Ti 155.3, 4070 Super 108.4 under a 110 W cap, 4060 Ti 16 GB 102.3, 4080 185.6; each with the class v3 watts paired on the same host as the shadow premium, +9 to +56 percent for no rate; the 5070 and 4070 Ti Super rates as ranges by board), MH per watt ranked again on those rows Co-Authored-By: Claude Fable 5.1 --- site/miner-bench.json | 68 ++++++++++++++++++++----------------------- site/miners.html | 4 +-- 2 files changed, 34 insertions(+), 38 deletions(-) diff --git a/site/miner-bench.json b/site/miner-bench.json index 05de69e18..b8ec8a289 100644 --- a/site/miner-bench.json +++ b/site/miner-bench.json @@ -854,13 +854,13 @@ "group": "buy", "card": "NVIDIA RTX 4070 Ti Super (16 GB)", "mh_s": 41.24, - "watts": 142.6, - "mh_per_w": 0.289, + "watts": 137.8, + "mh_per_w": 0.268, "driver_os": "NVIDIA driver 615.71.09, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 2 (a rented card, result cb2-rtx-4070-ti-super-7325-result.json; 09:26Z)", - "note": "rented single-card host, 0.10 h; power.draw mean 142.6 W (max 145.2, limit 285 W), SM 2,885 MHz mean, memory 10,251 MHz, 47 C, the SW thermal bit set with no rate effect (three runs within 0.02 percent); self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (41.37 MH/s, fingerprint matched); read ceiling 41.6 MH/s, the hash at 0.99 of it. The Ada 192-bit bus class: the same MH per watt as the 4070 Ti; the extra 4 GB buys headroom, not rate. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", - "watts_class": "v3", - "watts_display": "142.6 (class v3)" + "source": "model sweep 2026-10-08, row 2 (a rented card, result cb2-rtx-4070-ti-super-7325-result.json; 09:26Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-4070-ti-super-5733-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.10 h; power.draw mean 142.6 W (max 145.2, limit 285 W), SM 2,885 MHz mean, memory 10,251 MHz, 47 C, the SW thermal bit set with no rate effect (three runs within 0.02 percent); self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (41.37 MH/s, fingerprint matched); read ceiling 41.6 MH/s, the hash at 0.99 of it. The Ada 192-bit bus class: the same MH per watt as the 4070 Ti; the extra 4 GB buys headroom, not rate. Class v4 watts (8 October 2026, the rerun on the frozen v4-devnet-epoch0 pack, self-test PASS): 137.8 W at 36.93 MH/s, 0.268 MH per watt; the class v3 pack on the same host read 102.3 W at the same rate, so the shadow premium on this card is +34.7 percent of watts for no rate (the class is memory-bound). this host is a 210 W, 2,400 MHz board at 36.9 MH/s on both classes against the morning board's 41.2, so the rate reads as a range with the host noted; the premium is smaller than the 5070's because this board sits nearer its cap", + "watts_display": "137.8 (class v4)", + "mh_s_display": "37 to 41 by board (36.93 on this host)" }, { "generator": "v2", @@ -902,13 +902,12 @@ "group": "buy", "card": "NVIDIA RTX 4080 (16 GB)", "mh_s": 40.71, - "watts": 128.6, - "mh_per_w": 0.317, + "watts": 185.6, + "mh_per_w": 0.219, "driver_os": "NVIDIA driver 595.84, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 4 (a rented card, result cb2-rtx-4080-16-gb-7347-result.json; 09:28Z)", - "note": "rented single-card host, 0.15 h; power.draw mean 128.6 W (max 130.5, limit 320 W), SM 2,776 MHz mean, memory 10,801 MHz, 38 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (40.80 MH/s, fingerprint matched); read ceiling 41.0 MH/s, the hash at 0.99 of it. One percent under the 4070 Ti Super at 14 W less: the Ada 16 GB tier is a 41 MH/s tier whichever card. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", - "watts_class": "v3", - "watts_display": "128.6 (class v3)" + "source": "model sweep 2026-10-08, row 4 (a rented card, result cb2-rtx-4080-16-gb-7347-result.json; 09:28Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-4080-16-gb-7107-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.15 h; power.draw mean 128.6 W (max 130.5, limit 320 W), SM 2,776 MHz mean, memory 10,801 MHz, 38 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (40.80 MH/s, fingerprint matched); read ceiling 41.0 MH/s, the hash at 0.99 of it. One percent under the 4070 Ti Super at 14 W less: the Ada 16 GB tier is a 41 MH/s tier whichever card. Class v4 watts (8 October 2026, the rerun on the frozen v4-devnet-epoch0 pack, self-test PASS): 185.6 W at 40.73 MH/s, 0.219 MH per watt; the class v3 pack on the same host read 128.1 W at the same rate, so the shadow premium on this card is +44.9 percent of watts for no rate (the class is memory-bound). the same board as the morning row (offer 54551253; the v3 draw repeats to half a watt); the 256-bit board's premium sits above the 192-bit cards' third", + "watts_display": "185.6 (class v4)" }, { "generator": "v2", @@ -968,19 +967,18 @@ "group": "buy", "card": "NVIDIA RTX 4060 Ti (16 GB)", "mh_s": 20.07, - "watts": 79.2, - "mh_per_w": 0.253, + "watts": 102.3, + "mh_per_w": 0.196, "driver_os": "NVIDIA driver 595.71.05, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 7 (a rented card, result cb2-rtx-4060-ti-16-gb-7364-result.json; 09:33Z)", - "note": "rented single-card host, 0.22 h; power.draw mean 79.2 W (max 86.2, limit 165 W), SM 2,836 MHz mean, memory 8,751 MHz, 63 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (20.10 MH/s, fingerprint matched). Repeats the 7 October number (20.10 then, 20.07 now); the one card of the sweep well under its probed read ceiling (0.65 of 30.9 MH/s: the 128-bit bus with the large L2 makes the chase probe optimistic), so 20 MH/s at 79 W is the card's rate; 16 GB holds any class with room. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "source": "model sweep 2026-10-08, row 7 (a rented card, result cb2-rtx-4060-ti-16-gb-7364-result.json; 09:33Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-4060-ti-16-gb-6679-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.22 h; power.draw mean 79.2 W (max 86.2, limit 165 W), SM 2,836 MHz mean, memory 8,751 MHz, 63 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (20.10 MH/s, fingerprint matched). Repeats the 7 October number (20.10 then, 20.07 now); the one card of the sweep well under its probed read ceiling (0.65 of 30.9 MH/s: the 128-bit bus with the large L2 makes the chase probe optimistic), so 20 MH/s at 79 W is the card's rate; 16 GB holds any class with room. Class v4 watts (8 October 2026, the rerun on the frozen v4-devnet-epoch0 pack, self-test PASS): 102.3 W at 20.1 MH/s, 0.196 MH per watt; the class v3 pack on the same host read 76.6 W at the same rate, so the shadow premium on this card is +33.6 percent of watts for no rate (the class is memory-bound). the same board as the 7 October row (offer 47543124); the rate is the same on every 4060 Ti host and both classes (20.07 to 20.10)", "hive": { "core_mhz": null, "mem_mhz": null, "pl_w": null, "label": "stock (rented card, no clock control on the host; no measured tune point)" }, - "watts_class": "v3", - "watts_display": "79.2 (class v3)" + "watts_display": "102.3 (class v4)" }, { "generator": "v2", @@ -992,19 +990,19 @@ "group": "buy", "card": "NVIDIA RTX 5070 (12 GB)", "mh_s": 51.81, - "watts": 110.8, - "mh_per_w": 0.468, + "watts": 176.1, + "mh_per_w": 0.334, "driver_os": "NVIDIA driver 580.173.02, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 8 (a rented card, result cb2-rtx-5070-12-gb-8750-result.json; 09:35Z)", - "note": "rented single-card host, 0.09 h; power.draw mean 110.8 W (max 112.0, limit 250 W), SM 2,851 MHz mean, memory 13,801 MHz, 60 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (51.98 MH/s, fingerprint matched); read ceiling 52.3 MH/s, the hash at 0.99 of it. Repeats the 7 October row (52.01 then, 51.82 now) at 8 W more on this host; second to the 5070 Ti in MH per watt among consumer cards (GDDR7 lifts Blackwell here, not SM count); 12 GB holds the class v4 set with 10 GB spare. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "source": "model sweep 2026-10-08, row 8 (a rented card, result cb2-rtx-5070-12-gb-8750-result.json; 09:35Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-5070-12-gb-5732-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.09 h; power.draw mean 110.8 W (max 112.0, limit 250 W), SM 2,851 MHz mean, memory 13,801 MHz, 60 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (51.98 MH/s, fingerprint matched); read ceiling 52.3 MH/s, the hash at 0.99 of it. Repeats the 7 October row (52.01 then, 51.82 now) at 8 W more on this host; second to the 5070 Ti in MH per watt among consumer cards (GDDR7 lifts Blackwell here, not SM count); 12 GB holds the class v4 set with 10 GB spare. Class v4 watts (8 October 2026, the rerun on the frozen v4-devnet-epoch0 pack, self-test PASS): 176.1 W at 58.89 MH/s, 0.334 MH per watt; the class v3 pack on the same host read 113.1 W at the same rate, so the shadow premium on this card is +55.7 percent of watts for no rate (the class is memory-bound). board-to-board spread: this host 58.9 MH/s on both classes, the morning host 51.8 (GDDR7 memory clocks differ by board), so the rate reads as a range with the host noted", "hive": { "core_mhz": null, "mem_mhz": null, "pl_w": null, "label": "stock (rented card, no clock control on the host; no measured tune point)" }, - "watts_class": "v3", - "watts_display": "110.8 (class v3)" + "watts_display": "176.1 (class v4)", + "mh_s_display": "52 to 59 by board (58.89 on this host)" }, { "generator": "v2", @@ -1016,19 +1014,18 @@ "group": "buy", "card": "NVIDIA RTX 4070 Super (12 GB)", "mh_s": 31.24, - "watts": 100.2, - "mh_per_w": 0.312, + "watts": 108.4, + "mh_per_w": 0.288, "driver_os": "NVIDIA driver 580.178.04, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 9 (a rented card, result cb2-rtx-4070-super-12--8582-result.json; 09:36Z)", - "note": "rented single-card host, 0.13 h; power.draw mean 100.2 W (max 103.9) under a 110 W host cap (stock 220 W), SM 2,764 MHz mean, memory 10,251 MHz, 53 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (31.29 MH/s, fingerprint matched); read ceiling 34.4 MH/s, the hash at 0.91 of it. Lands on the 4070 Ti's number (31.26 on 7 October) at 7 W less (the same 192-bit 21 Gbps bus); the host's 110 W cap cost no rate, a tune-down reading in itself: an owner can cap a 4070 Super at half its stock power and lose nothing on class v4. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "source": "model sweep 2026-10-08, row 9 (a rented card, result cb2-rtx-4070-super-12--8582-result.json; 09:36Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-4070-super-12--6238-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.13 h; power.draw mean 100.2 W (max 103.9) under a 110 W host cap (stock 220 W), SM 2,764 MHz mean, memory 10,251 MHz, 53 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (31.29 MH/s, fingerprint matched); read ceiling 34.4 MH/s, the hash at 0.91 of it. Lands on the 4070 Ti's number (31.26 on 7 October) at 7 W less (the same 192-bit 21 Gbps bus); the host's 110 W cap cost no rate, a tune-down reading in itself: an owner can cap a 4070 Super at half its stock power and lose nothing on class v4. Class v4 watts (8 October 2026, the rerun on the frozen v4-devnet-epoch0 pack, self-test PASS): 108.4 W at 31.25 MH/s, 0.288 MH per watt; the class v3 pack on the same host read 99.2 W at the same rate, so the shadow premium on this card is +9.3 percent of watts for no rate (the class is memory-bound). the same board as the morning row (host offer 51485188), capped at 110 W by the host (stock 220) with the SW power-cap bit set the whole run: the cap absorbs the class v4 stage's extra draw (the SM clock drops 10 percent, the rate does not move), so the premium is 9 percent here against a third on uncapped Ada boards; a power cap near half stock costs a 192-bit Ada card nothing on class v4", "hive": { "core_mhz": null, "mem_mhz": null, "pl_w": null, "label": "stock (rented card, no clock control on the host; no measured tune point)" }, - "watts_class": "v3", - "watts_display": "100.2 (class v3)" + "watts_display": "108.4 (class v4)" }, { "generator": "v2", @@ -1279,19 +1276,18 @@ "card": "NVIDIA RTX 4070 Ti (12 GB)", "group": "buy", "mh_s": 31.24, - "watts": 95.4, - "mh_per_w": 0.327, + "watts": 155.3, + "mh_per_w": 0.201, "driver_os": "NVIDIA driver 580.126.09, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 20 (a rented card, result cb2-rtx-4070-ti-12-gb-0695-result.json; 09:57Z)", - "note": "rented single-card host, 0.18 h; power.draw mean 95.4 W (max 96.7, limit 285 W), SM 2,825 MHz mean, memory 10,251 MHz, 49 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (31.28 MH/s, fingerprint matched); read ceiling 31.7 MH/s, the hash at 0.99 of it. Repeats the 7 October rate to 0.07 percent on another provider at 12 W less; the 192-bit Ada pair (4070 Ti, 4070 Super) land on one number, 31.2 MH/s under 100 W. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "source": "model sweep 2026-10-08, row 20 (a rented card, result cb2-rtx-4070-ti-12-gb-0695-result.json; 09:57Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-4070-ti-12-gb-5744-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.18 h; power.draw mean 95.4 W (max 96.7, limit 285 W), SM 2,825 MHz mean, memory 10,251 MHz, 49 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (31.28 MH/s, fingerprint matched); read ceiling 31.7 MH/s, the hash at 0.99 of it. Repeats the 7 October rate to 0.07 percent on another provider at 12 W less; the 192-bit Ada pair (4070 Ti, 4070 Super) land on one number, 31.2 MH/s under 100 W. Class v4 watts (8 October 2026, the rerun on the frozen v4-devnet-epoch0 pack, self-test PASS): 155.3 W at 31.26 MH/s, 0.201 MH per watt; the class v3 pack on the same host read 113.8 W at the same rate, so the shadow premium on this card is +36.5 percent of watts for no rate (the class is memory-bound). the rate matches the morning and 7 October rows on a third host (no host spread on this card); driver 570.169 ran the class v4 pack clean", "hive": { "core_mhz": null, "mem_mhz": null, "pl_w": null, "label": "stock (rented card, no clock control on the host; no measured tune point)" }, - "watts_class": "v3", - "watts_display": "95.4 (class v3)" + "watts_display": "155.3 (class v4)" }, { "generator": "v2", diff --git a/site/miners.html b/site/miners.html index d7f8df81e..0dd74bbab 100644 --- a/site/miners.html +++ b/site/miners.html @@ -262,11 +262,11 @@ table.bench2 tr.detail .d{display:block;margin:0 0 4px}table.bench2 tr.detail b{

    The table

    -

    Best desktop card: NVIDIA RTX 5090, 136.1 MH/s (measured, 2026-10-06). Best stock MH per wall watt: NVIDIA RTX 4090, 0.285 at 183.1 W, untuned (measured by the fleet, 2026-10-07). Best tuned: NVIDIA RTX 5090, 0.563 at 226.8 W (measured, 2026-10-06).

    +

    Best desktop card: NVIDIA RTX 5090, 136.1 MH/s (measured, 2026-10-06). Best stock MH per wall watt: NVIDIA RTX 5070, 0.334 at 176.1 W, untuned (measured by the fleet, 2026-10-08). Best tuned: NVIDIA RTX 5090, 0.563 at 226.8 W (measured, 2026-10-06).

    The rented model sweep of 8 October 2026 (23 rows, 22 models, every row untuned) found the rate cap-proof: a card on a host power cap gives the same MH/s as an uncapped one. Class v5 held the rate on every uncapped card and read 17 to 18 percent under it on the two power-capped hosts (an A4000 at 114 W, a GTX 1080 Ti at 130 W), so a class v5 rate needs the card's power state beside it. The sweep's watts, and the 7 October fleet rows' watts, are class v3 figures: the fleet's bench pack ran the class v3 program, and class v4 draws more for the same rate (a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4, 8 October 2026). Those rows are ranked by rate alone; the per-watt claims above come from rows measured under class v4; the class v4 watts rerun lands on each row with its date, the v3 watts kept beside it as the shadow premium per card.

    One row per card on the current class: the class v4 program (the latency-shadow block over the class v3 hash), or a class v3 row re-measured with its class v4 cost on 6 October 2026 or later. MH per wall watt uses board or wall power; a row whose watts are the chip's (Apple silicon: GPU plus DRAM from IOReport) says so and is not ranked on that column. Integrated GPUs are not listed.

    Cards you can buy

    -
    NVIDIA RTX 5090 (32 GB)class v4 133.8 MH/s, 305 W, 0.439 · 2026-10-06136.1 stock (127.7 tuned)0.563226.8 tuned (350 stock) WTuned
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0878.5○ 0.577135.9 (class v3) WStock
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0778.4○ 0.539145.6 (class v3) WStock
    NVIDIA RTX 5080 (16 GB)class v4 +83 W unlocked, +41 W at the best points · 2026-10-0871.4 stock (71.2 tuned)0.486146.6 tuned (253 stock) WTuned
    NVIDIA RTX 3090 Ti (24 GB)class v4 not measured · 2026-10-0762○ 0.248249.5 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0759○ 0.221267.3 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0858.9○ 0.201293.5 (class v3) WStock
    NVIDIA RTX 4090 (24 GB)class v4 not measured · 2026-10-0752.30.285183.1 WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0752○ 0.506102.8 (class v3) WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0851.8○ 0.468110.8 (class v3) WStock
    NVIDIA RTX 3090 (24 GB)class v4 not measured · 2026-10-0750not measurednot readStock
    NVIDIA RTX 3080 (10 GB)class v4 not measured · 2026-10-0743.7not measurednot readStock
    NVIDIA RTX 4080 Super (16 GB)class v4 not measured · 2026-10-0842.6○ 0.316134.9 (class v3) WStock
    NVIDIA RTX 4070 Ti Super (16 GB)class v4 not measured · 2026-10-0841.2○ 0.289142.6 (class v3) WStock
    NVIDIA RTX 4080 (16 GB)class v4 not measured · 2026-10-0840.7○ 0.317128.6 (class v3) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-0739○ 0.219178.3 (class v3) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-0839○ 0.22177.1 (class v3) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0837.1○ 0.261142.3 (class v3) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0733.7not measurednot readStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0733.1○ 0.256129.5 (class v3) WStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0831.7○ 0.316100.4 (class v3) WStock
    NVIDIA RTX 5060 (8 GB)class v4 not measured · 2026-10-0731.3○ 0.41575.4 (class v3) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0731.3○ 0.291107.3 (class v3) WStock
    NVIDIA RTX 4070 Super (12 GB)class v4 not measured · 2026-10-0831.2○ 0.312100.2 (class v3) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0831.2○ 0.32795.4 (class v3) WStock
    NVIDIA RTX 4070 (12 GB)class v4 +30 W · 2026-10-06310.38979.5 WTuned
    NVIDIA RTX 5060 Ti (16 GB)class v4 0.1 percent rate · 2026-10-0730.90.269114.8 WStock
    Apple M5 Max (40 GPU cores, Metal)class v4 +16 W · 2026-10-0627○ 1.2921 W chip, not wallNo lever
    NVIDIA RTX 3060 (12 GB)class v4 not measured · 2026-10-0726.9○ 0.241111.6 (class v3) WStock
    NVIDIA RTX 2080 Ti (11 GB)class v4 not measured · 2026-10-0826○ 0.116224.6 (class v3) WStock
    NVIDIA RTX 4060 Ti (8 GB)class v4 not measured · 2026-10-0720.1○ 0.25977.5 (class v3) WStock
    NVIDIA RTX 4060 Ti (16 GB)class v4 not measured · 2026-10-0820.1○ 0.25379.2 (class v3) WStock
    NVIDIA RTX 2070 Super (8 GB)class v4 not measured · 2026-10-0819.1○ 0.115166 (class v3) WStock
    NVIDIA RTX 4060 (8 GB)class v4 not measured · 2026-10-0819.1not measurednot readStock
    AMD Radeon RX 9070 XT (16 GB)class v4 +2 percent rate · 2026-10-0818.9 (18.8 to 19.2 on the G1 ladder)0.093202 stock WNo lever
    NVIDIA GTX 1080 Ti (11 GB)class v4 not measured · 2026-10-0816.3○ 0.131124.3 (class v3) WStock
    NVIDIA RTX 2060 (6 GB)class v4 not measured · 2026-10-0814.1○ 0.117120.6 (class v3) WStock
    Intel Arc B580 (12 GB)class v4 0.1 percent rate · 2026-10-0711not measurednot readStock
    +
    NVIDIA RTX 5090 (32 GB)class v4 133.8 MH/s, 305 W, 0.439 · 2026-10-06136.1 stock (127.7 tuned)0.563226.8 tuned (350 stock) WTuned
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0878.5○ 0.577135.9 (class v3) WStock
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0778.4○ 0.539145.6 (class v3) WStock
    NVIDIA RTX 5080 (16 GB)class v4 +83 W unlocked, +41 W at the best points · 2026-10-0871.4 stock (71.2 tuned)0.486146.6 tuned (253 stock) WTuned
    NVIDIA RTX 3090 Ti (24 GB)class v4 not measured · 2026-10-0762○ 0.248249.5 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0759○ 0.221267.3 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0858.9○ 0.201293.5 (class v3) WStock
    NVIDIA RTX 4090 (24 GB)class v4 not measured · 2026-10-0752.30.285183.1 WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0752○ 0.506102.8 (class v3) WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0852 to 59 by board (58.89 on this host)0.334176.1 (class v4) WStock
    NVIDIA RTX 3090 (24 GB)class v4 not measured · 2026-10-0750not measurednot readStock
    NVIDIA RTX 3080 (10 GB)class v4 not measured · 2026-10-0743.7not measurednot readStock
    NVIDIA RTX 4080 Super (16 GB)class v4 not measured · 2026-10-0842.6○ 0.316134.9 (class v3) WStock
    NVIDIA RTX 4070 Ti Super (16 GB)class v4 not measured · 2026-10-0837 to 41 by board (36.93 on this host)0.268137.8 (class v4) WStock
    NVIDIA RTX 4080 (16 GB)class v4 not measured · 2026-10-0840.70.219185.6 (class v4) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-0739○ 0.219178.3 (class v3) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-0839○ 0.22177.1 (class v3) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0837.1○ 0.261142.3 (class v3) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0733.7not measurednot readStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0733.1○ 0.256129.5 (class v3) WStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0831.7○ 0.316100.4 (class v3) WStock
    NVIDIA RTX 5060 (8 GB)class v4 not measured · 2026-10-0731.3○ 0.41575.4 (class v3) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0731.3○ 0.291107.3 (class v3) WStock
    NVIDIA RTX 4070 Super (12 GB)class v4 not measured · 2026-10-0831.20.288108.4 (class v4) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0831.20.201155.3 (class v4) WStock
    NVIDIA RTX 4070 (12 GB)class v4 +30 W · 2026-10-06310.38979.5 WTuned
    NVIDIA RTX 5060 Ti (16 GB)class v4 0.1 percent rate · 2026-10-0730.90.269114.8 WStock
    Apple M5 Max (40 GPU cores, Metal)class v4 +16 W · 2026-10-0627○ 1.2921 W chip, not wallNo lever
    NVIDIA RTX 3060 (12 GB)class v4 not measured · 2026-10-0726.9○ 0.241111.6 (class v3) WStock
    NVIDIA RTX 2080 Ti (11 GB)class v4 not measured · 2026-10-0826○ 0.116224.6 (class v3) WStock
    NVIDIA RTX 4060 Ti (8 GB)class v4 not measured · 2026-10-0720.1○ 0.25977.5 (class v3) WStock
    NVIDIA RTX 4060 Ti (16 GB)class v4 not measured · 2026-10-0820.10.196102.3 (class v4) WStock
    NVIDIA RTX 2070 Super (8 GB)class v4 not measured · 2026-10-0819.1○ 0.115166 (class v3) WStock
    NVIDIA RTX 4060 (8 GB)class v4 not measured · 2026-10-0819.1not measurednot readStock
    AMD Radeon RX 9070 XT (16 GB)class v4 +2 percent rate · 2026-10-0818.9 (18.8 to 19.2 on the G1 ladder)0.093202 stock WNo lever
    NVIDIA GTX 1080 Ti (11 GB)class v4 not measured · 2026-10-0816.3○ 0.131124.3 (class v3) WStock
    NVIDIA RTX 2060 (6 GB)class v4 not measured · 2026-10-0814.1○ 0.117120.6 (class v3) WStock
    Intel Arc B580 (12 GB)class v4 0.1 percent rate · 2026-10-0711not measurednot readStock

    38 cards. Details opens a card's Hive flight-sheet values, its full class v4 cost, miner, source and note.

    Datacentre (13 cards, rented for the measurement; about three times the rented dollars per hash of a desktop card)
    NVIDIA B200 (180 GB)class v4 not measured · 2026-10-07416.4○ 0.487855.6 (class v3) WStock
    NVIDIA H200 SXM (141 GB)class v4 not measured · 2026-10-07313○ 0.723432.9 (class v3) WStock
    NVIDIA H100 SXM (80 GB)class v4 not measured · 2026-10-07248.7○ 0.645385.6 (class v3) WStock
    NVIDIA H100 SXM (80 GB HBM3)class v4 not measured · 2026-10-08248.3○ 0.605411.7 (class v3) WStock
    NVIDIA A100 PCIe (80 GB)class v4 not measured · 2026-10-07155○ 0.517299.6 (class v3) WStock
    NVIDIA A100 SXM (80 GB)class v4 not measured · 2026-10-07138.4○ 0.52266.3 (class v3) WStock
    NVIDIA A100 SXM4 (80 GB)class v4 not measured · 2026-10-08138.1○ 0.515268.6 (class v3) WStock
    NVIDIA RTX PRO 6000 Blackwell (96 GB)class v4 not measured · 2026-10-07130.5○ 0.452288.7 (class v3) WStock
    NVIDIA L40S (48 GB)class v4 not measured · 2026-10-0856.4○ 0.256220.7 (class v3) WStock
    NVIDIA L40S (48 GB)class v4 not measured · 2026-10-0756.4○ 0.234240.7 (class v3) WStock
    NVIDIA RTX A6000 (48 GB)class v4 not measured · 2026-10-0853.6○ 0.224239.1 (class v3) WStock
    NVIDIA RTX A5000 (24 GB)class v4 not measured · 2026-10-0747.6not measurednot readStock
    NVIDIA RTX A4000 (16 GB)class v4 not measured · 2026-10-0831.4○ 0.279112.8 (class v3) WStock
    From 6d0a52ea0335d0681807960d5cf7384ae1bb80c2 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 10:48:11 +0000 Subject: [PATCH 11/11] Litepaper and evidence: the hash's reads stated as measured (8 October 2026, lane D's family harness at 2^20 over 4,900 drawn eras and adv-cache-2's reading): "dependent reads spread over a multi-gigabyte dataset" in the lead, the measured clause after the chain-of-random-reads sentence (the 0.995 floor on every accepted program; about half of epochs with one biased address bit at the era's stride rotation; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold in the next class), evidence row 18 with its sources; ledger AP-F8-7 (Open, priced), the public ledger and the ledger page regenerated. Bench table: class v4 watts rows 7 to 10 (RTX 3070 196.4 W under a 193 W cap, +28 percent; RTX 3070 Ti 267.6 W uncapped, +48 percent; RTX 4060 no watts on any rented host; the 3080 Ti's deep-capped pair in its note, the first cap that costs rate, the uncapped rate standing) Co-Authored-By: Claude Fable 5.1 --- docs/evidence.md | 2 +- docs/fud-ledger.md | 9 +++++++++ docs/ledger-public.md | 3 ++- site/evidence.html | 2 +- site/ledger.html | 24 +++++++++++++++--------- site/litepaper.html | 6 +++--- site/miner-bench.json | 33 +++++++++++++++------------------ site/miners.html | 2 +- 8 files changed, 47 insertions(+), 34 deletions(-) diff --git a/docs/evidence.md b/docs/evidence.md index 217c84dca..b962f79b2 100644 --- a/docs/evidence.md +++ b/docs/evidence.md @@ -42,7 +42,7 @@ Versions in the table: `igneum-pow` is the Rust crate at `igneum-pow/Cargo.toml` | 15 | Every block is proven, with the proof landing within about a minute at launch | Homepage stats ("~60 s to a proof"); litepaper Proving; roadmap phase 3 gate | implemented | repo `d7e1f89` (GPU proof), `e01a3cc`, `292e800`, `eedd136` (`proving/igneum-prove`: shard cutter, MPT witnesses, shard and aggregator guests); SP1 6.8.1; spec 7.2, 7.6 | `proving/windows-wsl2` (SETUP-PROVER, PROVE-BLOCK) on the RTX 5090; `igneum-prove-host --mode block` on `proving/fixtures/`; bench-log "proving v0 on the RTX 5090" and "proving: devnet v4 shards" | First GPU proof of an Igneum block, 4 October 2026, RTX 5090 (WSL2, SP1 cuda, mining paused): fixture `block-78-increment` (2 transactions), core proof 1.4 s (7.3 MB, verify 0.221 s), compressed proof 2.7 s (1.27 MB, verify 0.038 s), post-state and receipts roots identical to the node's; 15.7x and 20.6x faster than a loaded M5 Max CPU. The same day on that CPU (load 38 to 47): a three-shard block proved shard by shard and aggregated by recursion, 19 min (1,139 s) end to end, 245 to 337 s per compressed shard proof, every proof verified. What is not there: no proof is produced, carried or checked on the chain (the devnet prover is a stub that signs claims), the proving pool pays nobody (row 21), the block proven is far below one shard, and the 60-second figure remains a design target; the pass mark is the standard in `docs/benchmarks/proving-e2e.md`. Second RTX 5090 run, 4 October 2026 evening (job run-20261004-173115): a full shard at the provisional S_p (6.75 M pgas, 60.8 M cycles) executed in 1.63 s, core proof 8.3 s (18.1 MB), compressed proof 10.9 s (1.27 MB, verify 0.040 s); a two-shard block (13.5 M pgas) proved shard by shard (11.7 s and 10.0 s) and aggregated in 2.2 s, 24 s of GPU stages end to end, every proof verified, six tampered witnesses rejected. The two host defects (an abort after the upload, an idle wait that turned out to be an unbuffered 18 MB proof save through the WSL2 file bridge, 24 minutes) are fixed (ledger P20) 5 October 2026, live devnet with real transactions (bench-log "real transactions, the first non-empty shard proven and paid"): block 72704 shard 0, 29 transfers, 5,800 pgas, proven on PC 2 in 34 s, verified on the Mac in 0.297 s and paid 1.7623 IGN, 53 s after the chain block executed; of about 1,400 blocks in the 20-minute window 36 were proven (the one prover takes the newest shard assigned to it), so "every block" is not yet true; a second content shard (72803, all copies skipped) failed the native-execution veto on the exporter's block structure, fixed with fixtures the same day, the node side pending the 0.3.9 rollout 5 October 2026, evening (bench-log "proving v1"): the aggregated segment record, the chain rule and the unproven rule are implemented behind `proving_v1_activation_daa` (branch proving-v1, not on the devnet before 0.3.11); on the RTX 5090 a chain of 8 consecutive live blocks proved and aggregated by recursion in 135.6 s with the miner on the card (17 s a block, one proof of 1,272,909 bytes attesting all 8, verified in 0.04 s); the 3-node fast-time harness paid a segment record 1.0 s after submission and refused a late one after its deadline (21 checks); the devnet itself, with one prover, carried proofs for 2.4% of blocks over 30 minutes at a block-to-record latency p50 44 s, p99 52 s. The "within about a minute" holds per proven block; "every block" needs 18 mining 5090s or 6 proving-only cards at empty blocks on the measured rates, and the mandatory rule stays off until the share is one | none yet | | 16 | A 12 GB card proves one shard in about 20 s (WITHDRAWN 5 October 2026: a 24 GB card proves a full shard at the adopted size in 4.3 s; 32 GB mines and proves) | Litepaper Proving ("The proving budget"); roadmap gate 2 | designed | spec 5.1 (Target), 7.6 (`S_p` provisional, 7,500,000 pgas = `B_p` / 4) | `PROVE-SHARD.bat` on the RTX 5090 (pending); the end-to-end standard in `docs/benchmarks/proving-e2e.md`; bench-log "proving: devnet v4 shards" | Measured on a 32 GB card, not yet on a 12 GB card. A shard at the provisional `S_p` is 60.8 M SP1 cycles on the prototype pgas table (9 cycles per pgas, 44 per EVM gas; the modexp entry about 100x its SP1 cost); on an RTX 5090 (4 October 2026 evening, job run-20261004-173115) it executed in 1.63 s and its compressed proof took 10.9 s, verified in 0.040 s, so the 32 GB card is inside the 20 s target with margin. Whether a 12 GB card proves it at all, and in what time, is the next measurement (an RTX 3060 and an RTX 5060 Ti 16 GB are on order). A per-shard time can be met by shrinking the shard, so the project does not use it as a pass mark 5 October 2026, evening (bench-log "proving v1", the S_p curve): measured on the RTX 5090 with SP1 6.8.1's GPU prover, the card to itself, 1-s nvidia-smi samples: an empty shard 13,874 MiB and 2.2 s; a full shard at the ADOPTED v1 budget (30,000 pgas, 4.7 M cycles) 20,434 MiB and 4.3 s; the full prototype shard (6.75 M pgas, 60 M cycles) 28,307 MiB and 10.8 s; beside the miner 15,670 and 30,039 MiB. No environment knob of SP1 moves the 13.9 GB floor and the GPU server has no options of its own, so on this build a 12 GB card proves nothing, a 16 GB card only empty shards, a 24 GB card the adopted full shard alone and beside the miner (22,210 MiB and 13.2 s, measured on the 32 GB card: the 5090's allocation pattern, not yet a run on a 24 GB card) and a 32 GB card the prototype shard beside the miner with 2.5 GB spare. The litepaper line now says so; the 12 GB gate returns when a prover build with a smaller floor is measured on a 12 GB card | none yet | | 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); the class v4 efficiency passes (bench log "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080", measured): the 5090 at 136.84 MH/s and 475.5 W unlocked, 134.98 at 316.3 W at a 1,400 MHz core lock, the best points class v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W) and class v3 at 1,300 MHz (134.62, 223.3 W, 0.603), the premium 145 W unlocked and 82 W at the best points, the knee 1,300 MHz; the RTX 5080 (8 October 2026, the dock card of the three-card Windows rig) at 71.41 MH/s and 253.1 W unlocked under class v4 against 71.28 at 169.7 W under class v3, the best points class v4 at 1,100 MHz (71.20 MH/s, 146.6 W, 0.486 MH/W) and class v3 at 1,000 MHz (71.11, 103.7 W, 0.686), the premium 83.4 W unlocked and 41 W at the best points, the knee between 1,000 and 900 MHz; per tier: a 5080 owner on class v4 locked near 1,100 MHz pays 147 W instead of 253 for 0.3 percent less rate, MH per watt up 72 percent, the lever Ember Tune's core-clock knob in 0.3.24; 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026). | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), whose floor reading is in (measured, 8 October 2026; ledger AP-F8-1 and AP-F8-6): nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test, and no outside review has run yet | -| 18 | The chip resistance measurements: the program is latency-bound (random reads), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache | Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page | tested by the team | readwidth e752fc7 (`docs/plans/read-width.md`), ca2-era 78c0ee4, ca2-cache 2de19e5 (`docs/plans/hot-table.md`) | The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per load | Latency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026 | none yet | +| 18 | The chip resistance measurements: the program is latency-bound (dependent reads spread over the whole dataset), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache; measured 8 October 2026: the distinct-index floor holds at 0.995 on every accepted program, about half of epochs carry one load site with a biased address bit at the era's stride rotation, priced at about 1.6 percent of a hash's reads to a chip storing half the dataset and nothing to one storing all of it (`docs/analysis/class-v6/family-gate.md`, lane D; adv-cache-2's `report-chained-cache-2.md` section 2.3 on its branch; ledger AP-F8-7) | Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page | tested by the team | readwidth e752fc7 (`docs/plans/read-width.md`), ca2-era 78c0ee4, ca2-cache 2de19e5 (`docs/plans/hot-table.md`) | The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per load | Latency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026 | none yet | | 19 | The lottery hash is sound as a hash: uniform output, deterministic, no out-of-bounds read, fuzzed; class v3 bit-exact on the three vendors | Litepaper vs RandomX ("Every number above is measured and logged"), the numbers page | tested by the team | ca2-mixer 1ab8b21 (`tests/mixer.rs`, `tests/scratch.rs`), ca2-era 78c0ee4, ca2-soundness a465881 (`docs/analysis/scratch-soundness.md`), `igneum-pow/tests/packs.rs` | The crate suite (53 + 4 + 19 + 7), the Metal fuzz, edge, stats and determinism runs on the v3 construction, the pack vectors and 2^24 fingerprints on Metal, Apple OpenCL, the RTX 5090 and the RX 9070 XT, the 1,024-hash CPU re-check per card | Class v3 (mixer x8 + era): 200-program fuzz 200 of 200 on Metal, every tenth on Apple OpenCL; the pinned v3 packs 3/3 + 3/3 and 96 of 96 lanes on Metal and Apple OpenCL; the six era packs' fingerprints equal on the three vendors (PC 1 job run-ca2-era-pc1-20261005, 5 October 2026); the v2 exports byte-identical on the v3 crate; the final-class PC rows and the G2 re-check: job run-ca2-era-pc1b-20261005 (pending at the time of writing) | none yet | | 20 | No premine, no pre-sale, no allocation: every coin is minted by the schedule and every coin goes to the block producer (80%) and the proving pool (20%) | Homepage stats and Economics tiles; litepaper Supply, Economics | implemented | repo `6ac80a3`; fork "igneum-node devnet v0"; `consensus/core/src/igneum.rs`, `coinbase.rs` | `cargo test -p kaspa-consensus-core igneum` (8 pass: subsidy table, ramp, split, cap) and `cargo test -p kaspa-consensus coinbase` (8 pass); `igneum-miner inspect 40`; bench-log "igneum-node devnet v0" | Coinbases on the devnet: 80/20 exact on 39 of 39 single-payee blocks, the 20% to the `igneum-proving-pool-v0` output; the per-second schedule sums to under the 4,000,000,000 cap by less than 100 coins; 3,168,808,781 units per DAA second in years 0 to 2, halving at 63,115,200 DAA s. 3 October 2026, Apple M5 Max. The devnet genesis carries no allocation; the mainnet genesis does not exist yet, so the claim is about the code and the stated rule, not a launch that has happened | none yet | | 21 | The proving pool's 20% reaches shard provers and aggregators | Litepaper Economics; homepage "20% provers" | tested by the team | spec 5.3; `proving/igneum-prove` carries the prover's payout address in every shard proof (ledger P12) | None. The pool output exists (row 20); the payout from it against proof records is unwritten. Since 5 October 2026: the payout rule is live on the devnet (`proving.rs shard_payouts`, the carrying segment pays the first valid record per shard its part of the segment's pool credit) | The escrow accumulated on the simnet (92.55 IGN at the end of the v3 run) and nothing can draw it. Rule decided: per block, divided among shards by consensus proving cost, sortition to 8 provers for 10 s then open (spec 7.2). The economy model of 4 October 2026 (`sim/economy`, 1,000 operators, 30 days) kept every block proven within 60 s under six stress scenarios; a model, not hardware Live devnet, 5 October 2026: 388 shards paid by 16:02 UTC, 446.13 IGN from the pool to PC 2's payout address, 0.8813 IGN per mergeset block of the proven segment (bench-log entries of 5 October: "the first shards proven, verified and paid" and "real transactions, the first non-empty shard proven and paid") | none yet | diff --git a/docs/fud-ledger.md b/docs/fud-ledger.md index 1a1f78b09..de4d087b4 100644 --- a/docs/fud-ledger.md +++ b/docs/fud-ledger.md @@ -2528,6 +2528,15 @@ Evidence: `docs/analysis/cryptanalysis/report-acceptance-rule-3.md` sections 6.2 The three genesis fields of `docs/analysis/mission/mission.md` section 2.8, built on the node fork branch `genesis-forward` (from release-0.3.19-node dc141409) and the repo branch `genesis-forward`; the design and the gates in `docs/design/genesis-forward.md`. Every switch is never on the devnet (its digest c562d70e... does not move); the testnet genesis sets all three (the testnet lane re-pins and re-digests). +### AP-F8-7. The hash's reads are not uniformly random: about half of epochs carry one load site with a biased address bit +"The served text says every hash is a chain of random reads over the dataset. Measured at the acceptance rule's own 2^20 sample over 4,900 drawn eras (lane D's family harness, 8 October 2026) and in adv-cache-2's drawn-program reading the night before: the reads are spread over the whole dataset and the distinct-index floor holds at 0.995 on every accepted program, but 52 to 58 percent of accepted programs in every stratum carry one load site whose address bit R (the era's stride rotation), R+1 or R+2 is biased over 6 sigma, a third over 100 sigma, the worst z 1,024: a product's bit 0 at P = 1/4 landing on an address bit." + +Status: Open, priced: 1.6 percent at f = 1/2, nothing at f = 1; the served sentence corrected 8 October 2026 (the site audit lane, by main's word): the litepaper's lead reads "dependent reads spread over a multi-gigabyte dataset", the "chain of random reads" sentence carries the measured clause after it, evidence row 18 states the measurement with its sources. The disposition is class v6 layer 1's rule: fold the product's low bits before the rotation so no era lands a biased bit on an address bit, with the bias test as its guard (`docs/analysis/class-v6/family-gate.md`). + +Answer: Correct as a measurement and bounded as a gain. The favoured half of one site's window serves 75 instead of 50 percent of that site's reads, 25 percent of 1/16 of a hash's reads, about 1.6 percent, to a chip storing half the dataset; a chip storing all of it gains nothing (the f = 1 verdict unchanged, and the partial store already costs 1.26x the ops). The sentence that said "random" now says what was measured. + +Evidence: `docs/analysis/class-v6/family-gate.md` (lane D, the index-bit bias read, 8 October 2026); adv-cache-2's `docs/analysis/cryptanalysis/report-chained-cache-2.md` section 2.3 (branch adv-cache-2); `site/litepaper.html` Mining; `docs/evidence.md` row 18. + ### GF1. A post-quantum signature scheme would need a hard fork, and every vote key is a public BLS12-381 point "When a quantum computer comes, every BLS vote key is forged and the chain has no way to change the scheme without a fork of the kind you say you never need." diff --git a/docs/ledger-public.md b/docs/ledger-public.md index e20d55ac6..9e7f46bc9 100644 --- a/docs/ledger-public.md +++ b/docs/ledger-public.md @@ -2,7 +2,7 @@ Generated by `tools/ledger/export-public.mjs` from `docs/fud-ledger.md`; a gate check fails when the two drift. One row per item: the claim or criticism, its status, what was done, and the evidence. Internal identifiers, times of day and team-member names are left out on purpose; the full ledger is published with the repository. -193 items. By status: Conceded, stated 52; Fixed 31; Decided 22; Fixed on a branch, pending merge 14; Answered by design 9; Answered with evidence 6; Fixed, stated 4; Closed by rule 3; Open 3; Spec fixed 2; Answered by design, with a correction to our own text 1; Answered with evidence, stated 1; Answered by design for finality, Conceded for the lottery 1; Conceded, implemented, stated 1; Rule implemented and measured; launch month simulated 1; Answered by design, with the concession stated 1; Conceded, stated in the litepaper and the design doc 1; Answered with evidence at 1 block/s 1; Conceded, stated in the simulation report 1; Answered by design, with the dependency conceded. Update 7… 1; Conceded, stated in the litepaper, with the dial explained 1; Closed by spec 1; Conceded by decision, stated in the design doc 1; Answered by design, with the founder's edge conceded 1; Answered by design, with a metrics caveat 1; Closed by removal, 3 October 2026 1; Conceded, stated in the litepaper 1; Conceded, stated in the design doc 1; Measured on the live node line, and the overlay does NOT… 1; Conceded, stated in the simulation 1; Conceded in part, labelled, stated 1; Fixed in the node 1; Answered with evidence for the largest body the rules allow 1; Fixed in the proving code 1; Fixed in the spec 1; Rule fixed 1; Rule written 1; Fixed, logged 1; Answered with evidence for the test half 1; Fixed in the node and shipped, rule not yet activated on… 1; Simulation half run 1; Answered with evidence for all four 1; Written 1; Designed 1; Fixed and confirmed 1; Rolled out 1; Conceded by decision 1; Conceded, scheduled, stated 1; Conceded, contained by rule, stated 1; Fixed on a branch and verified locally 1; Answered with evidence and stated 1; Answered with evidence for PC 2 1; Answered by design and with evidence 1; Fixed, stated; restated 1; Fixed, stated; restated further 1; Fixed in part, finding bounded, stated 1; Fixed as a genesis lever, measurement owed 1. +194 items. By status: Conceded, stated 52; Fixed 31; Decided 22; Fixed on a branch, pending merge 14; Answered by design 9; Answered with evidence 6; Fixed, stated 4; Closed by rule 3; Open 3; Spec fixed 2; Answered by design, with a correction to our own text 1; Answered with evidence, stated 1; Answered by design for finality, Conceded for the lottery 1; Conceded, implemented, stated 1; Rule implemented and measured; launch month simulated 1; Answered by design, with the concession stated 1; Conceded, stated in the litepaper and the design doc 1; Answered with evidence at 1 block/s 1; Conceded, stated in the simulation report 1; Answered by design, with the dependency conceded. Update 7… 1; Conceded, stated in the litepaper, with the dial explained 1; Closed by spec 1; Conceded by decision, stated in the design doc 1; Answered by design, with the founder's edge conceded 1; Answered by design, with a metrics caveat 1; Closed by removal, 3 October 2026 1; Conceded, stated in the litepaper 1; Conceded, stated in the design doc 1; Measured on the live node line, and the overlay does NOT… 1; Conceded, stated in the simulation 1; Conceded in part, labelled, stated 1; Fixed in the node 1; Answered with evidence for the largest body the rules allow 1; Fixed in the proving code 1; Fixed in the spec 1; Rule fixed 1; Rule written 1; Fixed, logged 1; Answered with evidence for the test half 1; Fixed in the node and shipped, rule not yet activated on… 1; Simulation half run 1; Answered with evidence for all four 1; Written 1; Designed 1; Fixed and confirmed 1; Rolled out 1; Conceded by decision 1; Conceded, scheduled, stated 1; Conceded, contained by rule, stated 1; Fixed on a branch and verified locally 1; Answered with evidence and stated 1; Answered with evidence for PC 2 1; Answered by design and with evidence 1; Fixed, stated; restated 1; Fixed, stated; restated further 1; Fixed in part, finding bounded, stated 1; Open, priced 1; Fixed as a genesis lever, measurement owed 1. | Id | Claim or criticism | Status | What was done | Evidence | |---|---|---|---|---| @@ -195,6 +195,7 @@ Generated by `tools/ledger/export-public.mjs` from `docs/fud-ledger.md`; a gate | AP-F8-1 | A load whose source was last written by `or`, `mul` or `mulhi` makes a cross-hash hot set | Fixed in part, finding bounded, stated | Class v4 sub-version 3 (igneum-pow a commit, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under… | [docs/analysis/ca3-v4-uniform.md](../docs/analysis/ca3-v4-uniform.md) | | AP-F8-4 | The program id's derivation text omitted generator 4's sub-version suffix (interoperability, documentation; no object change) | Fixed | The id and its printed derivation come from one byte recipe (`generator::IdRecipe`, `program_id_recipe`, `program_id_class_recipe`, `Program::program_id_derivation`), so the two cannot drift; the emitter prints that… | [igneum-pow/tests/derivation.rs](../igneum-pow/tests/derivation.rs) | | AP-F8-5 | The public specification did not describe the shipped acceptance rule (documentary; no object change) | Spec fixed | Sections 1.4.3 and 1.4.6 of `docs/spec/01-lottery-hash.md` rewritten to the shipped rule at igneum-pow a commit with every constant named and every order of operations stated (1.4.3: the two per-register states of the… | [docs/analysis/cryptanalysis/report-acceptance-rule-3.md](../docs/analysis/cryptanalysis/report-acceptance-rule-3.md) | +| AP-F8-7 | The hash's reads are not uniformly random: about half of epochs carry one load site with a biased address bit | Open, priced | 1.6 percent at f = 1/2, nothing at f = 1; the served sentence corrected 8 October 2026 (the site the team, by the team's word): the litepaper's lead reads "dependent reads spread over a multi-gigabyte dataset", the… | [docs/analysis/class-v6/family-gate.md](../docs/analysis/class-v6/family-gate.md) | | GF1 | A post-quantum signature scheme would need a hard fork, and every vote key is a public BLS12-381 point | Fixed | The byte costs nothing now and a fork later. | none named | | GF2 | A vote key cannot move: a miner who changes keys re-earns 30 days of weight, and so does the post-quantum migration | Fixed | The successor inherits the window, not a fresh one, so a key rotation costs no weight and the migration of GF1 is one item per key. | none named | | GF3 | A 256 MB on-chip cache makes the lottery hash 2 to 3x cheaper for the card that has it, and the cache size is a constant | Fixed as a genesis lever, measurement owed | Consumer LLC is 96 to 128 MB today and datacentre 256 MB (`chip-model-v3`, approximate), so the shortcut is a datacentre card's today and a consumer card's in a generation or two. | none named | diff --git a/site/evidence.html b/site/evidence.html index 380b3bcbd..e93014c72 100644 --- a/site/evidence.html +++ b/site/evidence.html @@ -257,7 +257,7 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v 15Every block is proven, with the proof landing within about a minute at launch
    Homepage stats ("~60 s to a proof"); litepaper Proving; roadmap phase 3 gate
    implementedrepo d7e1f89 (GPU proof), e01a3cc, 292e800, eedd136 (proving/igneum-prove: shard cutter, MPT witnesses, shard and aggregator guests); SP1 6.8.1; spec 7.2, 7.6proving/windows-wsl2 (SETUP-PROVER, PROVE-BLOCK) on the RTX 5090; igneum-prove-host --mode block on proving/fixtures/; bench-log "proving v0 on the RTX 5090" and "proving: devnet v4 shards"First GPU proof of an Igneum block, 4 October 2026, RTX 5090 (WSL2, SP1 cuda, mining paused): fixture block-78-increment (2 transactions), core proof 1.4 s (7.3 MB, verify 0.221 s), compressed proof 2.7 s (1.27 MB, verify 0.038 s), post-state and receipts roots identical to the node's; 15.7x and 20.6x faster than a loaded M5 Max CPU. The same day on that CPU (load 38 to 47): a three-shard block proved shard by shard and aggregated by recursion, 19 min (1,139 s) end to end, 245 to 337 s per compressed shard proof, every proof verified. What is not there: no proof is produced, carried or checked on the chain (the devnet prover is a stub that signs claims), the proving pool pays nobody (row 21), the block proven is far below one shard, and the 60-second figure remains a design target; the pass mark is the standard in docs/benchmarks/proving-e2e.md. Second RTX 5090 run, 4 October 2026 evening (job run-20261004-173115): a full shard at the provisional S_p (6.75 M pgas, 60.8 M cycles) executed in 1.63 s, core proof 8.3 s (18.1 MB), compressed proof 10.9 s (1.27 MB, verify 0.040 s); a two-shard block (13.5 M pgas) proved shard by shard (11.7 s and 10.0 s) and aggregated in 2.2 s, 24 s of GPU stages end to end, every proof verified, six tampered witnesses rejected. The two host defects (an abort after the upload, an idle wait that turned out to be an unbuffered 18 MB proof save through the WSL2 file bridge, 24 minutes) are fixed (ledger P20) 5 October 2026, live devnet with real transactions (bench-log "real transactions, the first non-empty shard proven and paid"): block 72704 shard 0, 29 transfers, 5,800 pgas, proven on the RTX 5090 Windows rig in 34 s, verified on the Apple M5 Max in 0.297 s and paid 1.7623 IGN, 53 s after the chain block executed; of about 1,400 blocks in the 20-minute window 36 were proven (the one prover takes the newest shard assigned to it), so "every block" is not yet true; a second content shard (72803, all copies skipped) failed the native-execution veto on the exporter's block structure, fixed with fixtures the same day, the node side pending the 0.3.9 rollout 5 October 2026, evening (bench-log "proving v1"): the aggregated segment record, the chain rule and the unproven rule are implemented behind proving_v1_activation_daa (branch proving-v1, not on the devnet before 0.3.11); on the RTX 5090 a chain of 8 consecutive live blocks proved and aggregated by recursion in 135.6 s with the miner on the card (17 s a block, one proof of 1,272,909 bytes attesting all 8, verified in 0.04 s); the 3-node fast-time harness paid a segment record 1.0 s after submission and refused a late one after its deadline (21 checks); the devnet itself, with one prover, carried proofs for 2.4% of blocks over 30 minutes at a block-to-record latency p50 44 s, p99 52 s. The "within about a minute" holds per proven block; "every block" needs 18 mining 5090s or 6 proving-only cards at empty blocks on the measured rates, and the mandatory rule stays off until the share is onenone yet 16A 12 GB card proves one shard in about 20 s (WITHDRAWN 5 October 2026: a 24 GB card proves a full shard at the adopted size in 4.3 s; 32 GB mines and proves)
    Litepaper Proving ("The proving budget"); roadmap gate 2
    designedspec 5.1 (Target), 7.6 (S_p provisional, 7,500,000 pgas = B_p / 4)PROVE-SHARD.bat on the RTX 5090 (pending); the end-to-end standard in docs/benchmarks/proving-e2e.md; bench-log "proving: devnet v4 shards"Measured on a 32 GB card, not yet on a 12 GB card. A shard at the provisional S_p is 60.8 M SP1 cycles on the prototype pgas table (9 cycles per pgas, 44 per EVM gas; the modexp entry about 100x its SP1 cost); on an RTX 5090 (4 October 2026 evening, job run-20261004-173115) it executed in 1.63 s and its compressed proof took 10.9 s, verified in 0.040 s, so the 32 GB card is inside the 20 s target with margin. Whether a 12 GB card proves it at all, and in what time, is the next measurement (an RTX 3060 and an RTX 5060 Ti 16 GB are on order). A per-shard time can be met by shrinking the shard, so the project does not use it as a pass mark 5 October 2026, evening (bench-log "proving v1", the S_p curve): measured on the RTX 5090 with SP1 6.8.1's GPU prover, the card to itself, 1-s nvidia-smi samples: an empty shard 13,874 MiB and 2.2 s; a full shard at the ADOPTED v1 budget (30,000 pgas, 4.7 M cycles) 20,434 MiB and 4.3 s; the full prototype shard (6.75 M pgas, 60 M cycles) 28,307 MiB and 10.8 s; beside the miner 15,670 and 30,039 MiB. No environment knob of SP1 moves the 13.9 GB floor and the GPU server has no options of its own, so on this build a 12 GB card proves nothing, a 16 GB card only empty shards, a 24 GB card the adopted full shard alone and beside the miner (22,210 MiB and 13.2 s, measured on the 32 GB card: the 5090's allocation pattern, not yet a run on a 24 GB card) and a 32 GB card the prototype shard beside the miner with 2.5 GB spare. The litepaper line now says so; the 12 GB gate returns when a prover build with a smaller floor is measured on a 12 GB cardnone yet 17The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state)
    the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line
    tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measureddocs/analysis/chip-model-v3.md 5 and 6; docs/analysis/latency-shadow-2026-10-06.md; docs/plans/counter-asic-3-status.md; docs/analysis/attack-pass/f8-uniform.md, f4-weakday.md, docs/analysis/ca3-v4-uniform.md; docs/design/class-v5-stored-state.md; the H100 and market-cap rows of 7 October; docs/plans/cryptanalysis/in-house-pass.md (the internal adversarial pass)the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses tools/attack/f8-uniform and the F4 census; the verifier by igneum-pow bench136 MH/s at 350 W (5090, bench) and 290 W (app); the class v4 efficiency passes (bench log "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080", measured): the 5090 at 136.84 MH/s and 475.5 W unlocked, 134.98 at 316.3 W at a 1,400 MHz core lock, the best points class v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W) and class v3 at 1,300 MHz (134.62, 223.3 W, 0.603), the premium 145 W unlocked and 82 W at the best points, the knee 1,300 MHz; the RTX 5080 (8 October 2026, the dock card of the three-card Windows rig) at 71.41 MH/s and 253.1 W unlocked under class v4 against 71.28 at 169.7 W under class v3, the best points class v4 at 1,100 MHz (71.20 MH/s, 146.6 W, 0.486 MH/W) and class v3 at 1,000 MHz (71.11, 103.7 W, 0.686), the premium 83.4 W unlocked and 41 W at the best points, the knee between 1,000 and 900 MHz; per tier: a 5080 owner on class v4 locked near 1,100 MHz pays 147 W instead of 253 for 0.3 percent less rate, MH per watt up 72 percent, the lever Ember Tune's core-clock knob in 0.3.24; 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, the RTX 5090 Windows rig's RTX 5090, the three-card Windows rig's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026).none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), whose floor reading is in (measured, 8 October 2026; ledger AP-F8-1 and AP-F8-6): nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test, and no outside review has run yet -18The chip resistance measurements: the program is latency-bound (random reads), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache
    Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page
    tested by the teamreadwidth e752fc7 (docs/plans/read-width.md), ca2-era 78c0ee4, ca2-cache 2de19e5 (docs/plans/hot-table.md)The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per loadLatency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026none yet +18The chip resistance measurements: the program is latency-bound (dependent reads spread over the whole dataset), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache; measured 8 October 2026: the distinct-index floor holds at 0.995 on every accepted program, about half of epochs carry one load site with a biased address bit at the era's stride rotation, priced at about 1.6 percent of a hash's reads to a chip storing half the dataset and nothing to one storing all of it (docs/analysis/class-v6/family-gate.md, lane D; adv-cache-2's report-chained-cache-2.md section 2.3 on its branch; ledger AP-F8-7)
    Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page
    tested by the teamreadwidth e752fc7 (docs/plans/read-width.md), ca2-era 78c0ee4, ca2-cache 2de19e5 (docs/plans/hot-table.md)The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per loadLatency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026none yet 19The lottery hash is sound as a hash: uniform output, deterministic, no out-of-bounds read, fuzzed; class v3 bit-exact on the three vendors
    Litepaper vs RandomX ("Every number above is measured and logged"), the numbers page
    tested by the teamca2-mixer 1ab8b21 (tests/mixer.rs, tests/scratch.rs), ca2-era 78c0ee4, ca2-soundness a465881 (docs/analysis/scratch-soundness.md), igneum-pow/tests/packs.rsThe crate suite (53 + 4 + 19 + 7), the Metal fuzz, edge, stats and determinism runs on the v3 construction, the pack vectors and 2^24 fingerprints on Metal, Apple OpenCL, the RTX 5090 and the RX 9070 XT, the 1,024-hash CPU re-check per cardClass v3 (mixer x8 + era): 200-program fuzz 200 of 200 on Metal, every tenth on Apple OpenCL; the pinned v3 packs 3/3 + 3/3 and 96 of 96 lanes on Metal and Apple OpenCL; the six era packs' fingerprints equal on the three vendors (the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) job run-ca2-era-pc1-20261005, 5 October 2026); the v2 exports byte-identical on the v3 crate; the final-class PC rows and the G2 re-check: job run-ca2-era-pc1b-20261005 (pending at the time of writing)none yet 20No premine, no pre-sale, no allocation: every coin is minted by the schedule and every coin goes to the block producer (80%) and the proving pool (20%)
    Homepage stats and Economics tiles; litepaper Supply, Economics
    implementedrepo 6ac80a3; fork "igneum-node devnet v0"; consensus/core/src/igneum.rs, coinbase.rscargo test -p kaspa-consensus-core igneum (8 pass: subsidy table, ramp, split, cap) and cargo test -p kaspa-consensus coinbase (8 pass); igneum-miner inspect 40; bench-log "igneum-node devnet v0"Coinbases on the devnet: 80/20 exact on 39 of 39 single-payee blocks, the 20% to the igneum-proving-pool-v0 output; the per-second schedule sums to under the 4,000,000,000 cap by less than 100 coins; 3,168,808,781 units per DAA second in years 0 to 2, halving at 63,115,200 DAA s. 3 October 2026, Apple M5 Max. The devnet genesis carries no allocation; the mainnet genesis does not exist yet, so the claim is about the code and the stated rule, not a launch that has happenednone yet 21The proving pool's 20% reaches shard provers and aggregators
    Litepaper Economics; homepage "20% provers"
    tested by the teamspec 5.3; proving/igneum-prove carries the prover's payout address in every shard proof (ledger P12)None. The pool output exists (row 20); the payout from it against proof records is unwritten. Since 5 October 2026: the payout rule is live on the devnet (proving.rs shard_payouts, the carrying segment pays the first valid record per shard its part of the segment's pool credit)The escrow accumulated on the simnet (92.55 IGN at the end of the v3 run) and nothing can draw it. Rule decided: per block, divided among shards by consensus proving cost, sortition to 8 provers for 10 s then open (spec 7.2). The economy model of 4 October 2026 (sim/economy, 1,000 operators, 30 days) kept every block proven within 60 s under six stress scenarios; a model, not hardware Live devnet, 5 October 2026: 388 shards paid by 16:02 UTC, 446.13 IGN from the pool to the RTX 5090 Windows rig's payout address, 0.8813 IGN per mergeset block of the proven segment (bench-log entries of 5 October: "the first shards proven, verified and paid" and "real transactions, the first non-empty shard proven and paid")none yet diff --git a/site/ledger.html b/site/ledger.html index 76b6f4fbe..da2297706 100644 --- a/site/ledger.html +++ b/site/ledger.html @@ -4,13 +4,13 @@ Igneum ledger: every criticism, answered - + - + @@ -18,7 +18,7 @@ - + @@ -218,9 +218,9 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
    Igneum/The ledger
    -
    Ledger · 189 entries · regenerated from the repository
    +
    Ledger · 190 entries · regenerated from the repository

    Every criticism, answered
    or conceded.

    -

    This is every criticism the project expects, in the critic's words, with what was done about it and the date. 189 entries since 3 October 2026. Entries are never deleted; a status that changes keeps its history on the line. Where the critic was right the entry says Conceded. Where nothing has been done it says Open and names what settles it. The founder mined through the GPU years. Ethereum's move to proof of stake in September 2022 ended that income and the miners' place in that chain. This is one person building, with AI systems doing the engineering, the coin he wanted to exist for miners: GPU-mined, the miners are the provers, no founder allocation, every cost stated. Help is welcome and a team is wanted: cryptographers, node engineers, miners who will test. This ledger is the application form: pick an open row and write to hello@igneum.network with its id.

    +

    This is every criticism the project expects, in the critic's words, with what was done about it and the date. 190 entries since 3 October 2026. Entries are never deleted; a status that changes keeps its history on the line. Where the critic was right the entry says Conceded. Where nothing has been done it says Open and names what settles it. The founder mined through the GPU years. Ethereum's move to proof of stake in September 2022 ended that income and the miners' place in that chain. This is one person building, with AI systems doing the engineering, the coin he wanted to exist for miners: GPU-mined, the miners are the provers, no founder allocation, every cost stated. Help is welcome and a team is wanted: cryptographers, node engineers, miners who will test. This ledger is the application form: pick an open row and write to hello@igneum.network with its id.

    @@ -229,11 +229,11 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c 3Nothing has settled it yet. The entry names what will 64The critic is right. "Stated" means the public text says so; "not yet stated" means it does not yet -64A code, spec or text change answers it, with the commit or the page named +65A code, spec or text change answers it, with the commit or the page named 27A consensus rule or a decision by the owner answers it, dated 15A measurement or a simulation exists and is named 16A design rule answers it; no measurement is possible yet -189Every entry. The sections: The in-house adversarial pass, Mining and chips, Finality and attacks, Proving and the zkEVM, Economics and the coin, Governance and the founders, Comparisons, Legal and regulatory, Launch and operations, Builders +190Every entry. The sections: The in-house adversarial pass, Mining and chips, Finality and attacks, Proving and the zkEVM, Economics and the coin, Governance and the founders, Comparisons, Legal and regulatory, Launch and operations, Builders

    Mining and chips

    @@ -1406,12 +1406,18 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
    Fixed 7 October 2026, night): the id and its derivation text come from one byte recipe, every pinned pack's id re-derives from its own text in the suite (the igneum-pow suite on box 2 green at 0f45c8be: 64 + 2 + 7 + 4 + 19 + 2 + 7), the spec states the suffix; no object moved.
    -
    +
    AP-F8-5

    The public specification did not describe the shipped acceptance rule (documentary; no object change)

    7 October 2026
    An implementation written from a repository file section 1.4.6 at 017e7037 mines a different program from the node on 264 of 400 epochs." Found by the in-house pass adv-accept-3 (report-acceptance-rule-3.md at 0c150e3c, finding 3, section 6.2, 7 October 2026, night): the text described (a), (b) and (c) with a 32-attempt cap and an id without a suffix, while the code adds (a') with the shared-operand rule, (c'), (c'') at 2^20 evaluations, the 256-attempt cap keyed on the class v4 shape, the total draw with the last resort, generator 4 and the sub-version suffix, and executes the 256-instruction shadow block 27 times per iteration inside the acceptance interpreter. Measured (sweep 97, 400 seeds, 1,317 attempt verdicts): 759 verdicts differ (758 the code rejects and the text accepts: (a') 733, (c'') 15, (c) 10; 1 the other way, the shadow block changing a (c) statistic); 264 of 400 seeds choose another attempt; the parts the text did carry, (a) and (b), agree on every row.
    -
    Conceded, stated 7 October 2026, night, the ledger close): a repository file, What Igneum does not claim, "A delay function that outlives a quantum computer. No." with the fallback (a hash-chain delay behind the version byte that moves the signature scheme, one class change) and the reading (a liveness nuisance, not a break of finality). Still not sized. Was: Conceded, flagged in spec 04 section 4.8.
    +
    Spec fixed 7 October 2026, night, the site audit lane by main's order, branch spec-accept-23): sections 1.4.3 and 1.4.6 of a repository file rewritten to the shipped rule at igneum-pow 017e7037 with every constant named and every order of operations stated (1.4.3: the two per-register states of the draw, the dataflow table, the shared-operand rule, the shadow block's draw and the draw counts per class; 1.4.6.1 to 1.4.6.6: (a) cyclic over two passes, (b), (a') to the fixpoint then a checking pass, (c) with the shadow executed and its limits in a table, (c') and (c'') with the integer form of the ratio compare, the attempts and the two caps with the measured per-part rates, the last resort stated as unreachable and unverified, the program id with the generator-4 suffix, a constants table in the shape the crate's read-back test parses, the pinned ids a reader must reproduce); section 1.7 gains the shadow block's execution; section 1.13.1 names the two consumed era draws. The hash lane's igneum-pow/tests read-back test parses the two tables against the crate's pub const items and derives every pinned id (its landing is the row's check; AP-F8-4 carries the derivation-text half of the same finding). Fixed on two measurements by the finding lane: Q4c at master 8b834634, before the closed-form dataset was stated, a text-only implementation of sections 1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7 and 1.13.1 re-derived the 400 epoch programs of sweep 97 under the Devnet 3 era with 0 of 400 differing on any field and one function (dataset_elem) taken from the crate (report section 6.5, log 983-textderive-8b834634.tsv); Q4d at master 56eebc0d, with dataset_elem written from 1.4.6.4 and its two pinned vectors reproduced, 0 of 400 differing with 0 crate imports (report section 6.6, log 984-textderive-56eebc0d.tsv, 8 October 2026, 01:5x UK).
    The answer as first written

    Correct, and the largest divergence source the pass found was documentary. The rule the chain runs was right; the text a second implementer would read was three sub-versions behind it. The fix is the text, written to the code line by line, and a test that fails when the two drift again.

    +
    +
    AP-F8-7

    The hash's reads are not uniformly random: about half of epochs carry one load site with a biased address bit

    7 October 2026
    +
    The served text says every hash is a chain of random reads over the dataset. Measured at the acceptance rule's own 2^20 sample over 4,900 drawn eras (lane D's family harness, 8 October 2026) and in adv-cache-2's drawn-program reading the night before: the reads are spread over the whole dataset and the distinct-index floor holds at 0.995 on every accepted program, but 52 to 58 percent of accepted programs in every stratum carry one load site whose address bit R (the era's stride rotation), R+1 or R+2 is biased over 6 sigma, a third over 100 sigma, the worst z 1,024: a product's bit 0 at P = 1/4 landing on an address bit.
    +
    Conceded, stated 7 October 2026, night, the ledger close): a repository file, What Igneum does not claim, "A delay function that outlives a quantum computer. No." with the fallback (a hash-chain delay behind the version byte that moves the signature scheme, one class change) and the reading (a liveness nuisance, not a break of finality). Still not sized. Was: Conceded, flagged in spec 04 section 4.8.
    +
    The answer as first written

    Correct as a measurement and bounded as a gain. The favoured half of one site's window serves 75 instead of 50 percent of that site's reads, 25 percent of 1/16 of a hash's reads, about 1.6 percent, to a chip storing half the dataset; a chip storing all of it gains nothing (the f = 1 verdict unchanged, and the partial store already costs 1.26x the ops). The sentence that said "random" now says what was measured.

    +

    Source: the project's criticism ledger, a file in the repository, rendered to this page at build time; the repository is published at the public testnet. A criticism that is not here, or that shows an entry is wrong, is added with credit if wanted: hello@igneum.network or an issue on the specification repository.

    diff --git a/site/litepaper.html b/site/litepaper.html index 20ebdf4eb..81feaea6b 100644 --- a/site/litepaper.html +++ b/site/litepaper.html @@ -426,19 +426,19 @@ body.all .pager{display:none}

    Mining: a program that never holds still

    Every GPU chain that promised ASIC resistance shipped a fixed algorithm, and a fixed algorithm gets a chip the moment the prize pays for one. Igneum does not have a fixed algorithm.

    -

    Each hour the chain derives a seed from a locked checkpoint one epoch back, passes it through a ten-minute verifiable delay so no miner can see which program a seed implies before choosing whether to publish a block, and feeds it to a deterministic generator. The generator emits a random integer program built from what graphics cards are uniquely good at: wide parallel integer maths, shuffles between the 32 lanes of a warp, and random reads over a multi-gigabyte dataset that changes daily, so the program waits on memory latency, not on maths or bandwidth. Measured: an RTX 5090 hashes at 95 GB/s of useful 4-byte loads against 1,638 GB/s of sequential writes (engineering log, the RTX 5090 entries). The memory footprint and instruction count are fixed and only the maths sequence is random, so no hour favours one vendor's cards and nobody gains by grinding the seed. Miners compile the program once per hour. Anyone running a node, a wallet or an exchange checks a hash on an ordinary CPU in under ten milliseconds by simulating one warp, so nobody needs a GPU except to mine. Measured: 0.61 ms per warp on one Apple M5 Max core for class v2 and 2.1 ms for class v3 (the mixer at x8, 5 October 2026, one core at load average 5.5, worst cold unit 2.15 ms), 3.4x the class v2 verifier; the 10 ms gate leaves 4.8x (4.6x on the worst cold unit); a 2019-class laptop core is not yet measured.

    +

    Each hour the chain derives a seed from a locked checkpoint one epoch back, passes it through a ten-minute verifiable delay so no miner can see which program a seed implies before choosing whether to publish a block, and feeds it to a deterministic generator. The generator emits a random integer program built from what graphics cards are uniquely good at: wide parallel integer maths, shuffles between the 32 lanes of a warp, and dependent reads spread over a multi-gigabyte dataset that changes daily, so the program waits on memory latency, not on maths or bandwidth. Measured: an RTX 5090 hashes at 95 GB/s of useful 4-byte loads against 1,638 GB/s of sequential writes (engineering log, the RTX 5090 entries). The memory footprint and instruction count are fixed and only the maths sequence is random, so no hour favours one vendor's cards and nobody gains by grinding the seed. Miners compile the program once per hour. Anyone running a node, a wallet or an exchange checks a hash on an ordinary CPU in under ten milliseconds by simulating one warp, so nobody needs a GPU except to mine. Measured: 0.61 ms per warp on one Apple M5 Max core for class v2 and 2.1 ms for class v3 (the mixer at x8, 5 October 2026, one core at load average 5.5, worst cold unit 2.15 ms), 3.4x the class v2 verifier; the 10 ms gate leaves 4.8x (4.6x on the worst cold unit); a 2019-class laptop core is not yet measured.

    The hash is a lottery, not a general-purpose cryptographic hash. It has to be unpredictable per nonce, free of any shortcut cheaper than honest evaluation, and free of bias a miner can exploit. It does not need preimage or collision resistance. Open: no analysis of the lottery properties exists yet. It is the first job of the external review in phase 1, and until then the hash is a design claim backed by the measurements below.

    - +
    ClockWhat changesMiner update needed?
    Every hashThe 128 dataset addresses depend on the nonce, so every hash reads different memory. The one-bit select inside the maths costs a chip nothing and is not a defence; the random reads areNo
    Every hashThe 128 dataset addresses depend on the nonce, so every hash reads different memory. The one-bit select inside the maths costs a chip nothing and is not a defence; the dependent reads areNo
    Every hourA new random programNo, the miner compiles whatever arrives
    Every dayA new datasetNo
    Every six monthsA new instruction mix and memory pattern drawn by the chain from rules fixed at genesis, and a new family of instructions unlocked from a reserve written at genesis, so the program space widens every era. A schedule change against fixed datapaths and human forks, not a surprise: a programmable chip reads every drawn parameter as firmwareNo
    ContinuouslyThe dataset grows on a schedule fixed at genesis, slowly enough that consumer cards keep up for years. A chip is built with fixed memory, so it is on a countdown from the day it ships. Ethereum's growing dataset ran Bitmain's E3 out of memory in 2020 this way, approximate, with nobody doing anythingNo
    -

    Three ideas carry the chip resistance. The hash rewrites itself. A new program every hour, drawn from the chain. Its memory pattern changes with it. The rules change on a schedule fixed at launch. No release, no vote. These are automatic schedule changes: they defeat a chip wired for one datapath and they need no human fork. Against a chip that stores the dataset every drawn parameter is firmware, and what meets that chip is the latency-shadow work (class v4) and the price per joule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). It waits on memory, not maths. Every hash is a chain of random reads into a table too big for a chip to carry. The wait is the same physics for everyone. Miners hold the switch. Spare defences are written into the rules, switched off. A miner signal turns one on, at the class-change threshold: miners signal three things at three thresholds, 60 percent of blue blocks over two weeks for a parameter genesis leaves open, 90 percent for an upgrade (new code), and 95 percent with a floor height for a class change. No fork.

    +

    Three ideas carry the chip resistance. The hash rewrites itself. A new program every hour, drawn from the chain. Its memory pattern changes with it. The rules change on a schedule fixed at launch. No release, no vote. These are automatic schedule changes: they defeat a chip wired for one datapath and they need no human fork. Against a chip that stores the dataset every drawn parameter is firmware, and what meets that chip is the latency-shadow work (class v4) and the price per joule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). It waits on memory, not maths. Every hash is a chain of random reads into a table too big for a chip to carry. Measured (8 October 2026; lane D’s family harness at the acceptance rule’s own 2^20 sample over 4,900 drawn eras, and the chained-cache pass’s reading of the night before): every hash’s 128 dependent reads land across the whole dataset and the distinct-index floor holds at 0.995 on every accepted program; about half of epochs carry one load site whose address bit at the era’s stride rotation is biased, which prices about 1.6 percent of a hash’s reads to a chip storing half the dataset and nothing to a chip storing all of it; the next class folds the product’s low bits before the rotation, so no era lands a biased bit on an address bit. The wait is the same physics for everyone. Miners hold the switch. Spare defences are written into the rules, switched off. A miner signal turns one on, at the class-change threshold: miners signal three things at three thresholds, 60 percent of blue blocks over two weeks for a parameter genesis leaves open, 90 percent for an upgrade (new code), and 95 percent with a floor height for a class change. No fork.

    The work that waits can grow. Class v4 adds a block of latency-shadow arithmetic to every hash, about 100,000 integer operations that run while the memory reads are in flight, so a chip that stores the whole dataset still has to pay for a core. That size sits on a ladder fixed at genesis, six rungs from about 100,000 to about 1,000,000 operations, and it moves one rung at a time only when 90 percent of blue blocks in each of seven consecutive days ask for it; it can never move two rungs inside a week and never past a rung the reference verifier cannot check under 10 ms with its sibling thread busy (measured on the build server, 6 October 2026: the first three rungs pass at 8.8, 8.9 and 9.2 ms, the fourth misses by 0.08 ms on a loaded box and stays out until a quiet re-measurement, the two doublings are out at 12.4 and 15.0 ms). What it buys, on the measured cards: against a dataset-storing chip whose core costs what an RTX 5090's does per operation, the chip's per-joule edge falls from 2.1x at the first rung to 1.3x at the third; against a core as good as the one Bitmain claimed for its withdrawn Antminer X9 (about 3x per joule over a desktop CPU, never measured), from 3.4x to 2.8x. What it costs, per rung, is measured too: the Apple tier gives up 3 points of rate at the first step and 6 more at the second, the RTX 5090 nothing until the second; so the miners who pay for a step are the ones who take it (ledger M34).

    The chip model

    We price the strongest chip we can design against an RTX 5090 and publish the arithmetic. Class v4 is live from the first block on the testnet and the mainnet (the ladder’s rung 0 at genesis), so the launch number is the class v4 row. The honest card: an RTX 5090 mines class v3 at 136 MH/s on 350 W in the bench and 290 W in the app (measured, 6 October 2026); under class v4 the same card reads 136.84 MH/s at 475.5 W unlocked and 134.98 MH/s at 316.3 W at a 1,400 MHz core lock, and 133.80 MH/s at 305.1 W at 1,200 MHz, against a class v3 control of 134.68 MH/s at 228.0 W (measured, 7 October 2026); an Apple M5 Max at 27 MH/s on 21 W (measured, 6 October 2026); an H100 SXM at 249 MH/s, 98 percent of its random-read ceiling like the 5090, 1.78x the 5090’s hash at 1.15x the tuned 5090’s hash per watt and a third of the hash per rented dollar (measured, 7 October 2026), so datacentre silicon does not change the chip question. The CPU verifier takes 2.33 ms per warp of 32 hashes on one M5 Max core under class v4 (measured, 6 October 2026), against a gate of 10 ms.

    diff --git a/site/miner-bench.json b/site/miner-bench.json index b8ec8a289..462f692b0 100644 --- a/site/miner-bench.json +++ b/site/miner-bench.json @@ -882,9 +882,9 @@ "mh_per_w": 0.201, "driver_os": "NVIDIA driver 580.65.06, Ubuntu 24.04 (CUDA 12.8.1 image)", "source": "model sweep 2026-10-08, row 3 (a rented card, result cb2-rtx-3080-ti-12-gb-efll-result.json; 09:28Z)", - "note": "rented single-card host, 0.04 h; power.draw mean 293.5 W (max 299.6, limit 320 W), SM 1,936 MHz mean, memory 9,251 MHz, 74 C, the SW power-cap bit set 26 W under the limit; self-test PASS (96 of 96 vector lanes); the class v5 kit runs 2.5 percent faster on this card (60.38 MH/s, fingerprint matched); read ceiling 58.9 MH/s, the hash at 1.00 of it. Matches the 7 October row (58.95 MH/s) across hosts; the worst MH per watt of the sweep and the cheapest MH per rented hour, so a buyer on a power bill prefers the 5070 Ti and a renter this card. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "note": "rented single-card host, 0.04 h; power.draw mean 293.5 W (max 299.6, limit 320 W), SM 1,936 MHz mean, memory 9,251 MHz, 74 C, the SW power-cap bit set 26 W under the limit; self-test PASS (96 of 96 vector lanes); the class v5 kit runs 2.5 percent faster on this card (60.38 MH/s, fingerprint matched); read ceiling 58.9 MH/s, the hash at 1.00 of it. Matches the 7 October row (58.95 MH/s) across hosts; the worst MH per watt of the sweep and the cheapest MH per rented hour, so a buyer on a power bill prefers the 5070 Ti and a renter this card. Class v4 pair (8 October 2026, result cb4-rtx-3080-ti-12-gb-7647-result.json, a different and deep-capped board: 220 W host cap on a 350 W card, the SM clock collapsed to 749 MHz): 42.24 MH/s mean at 216.2 W under class v4 against 44.93 MH/s at 166.2 W under class v3 on that board, the shadow premium +30.1 percent of watts and, on this cap, 5 percent of rate: the first cap that costs rate (a cap near 63 percent of stock on a 350 W GDDR6X card starves the SM clock the memory loop needs, where the 4070 Super at half its 220 W and the 3070 at 88 percent held full rate). The uncapped morning rate (58.86 MH/s) stands as this card's rate; its class v4 watts on an uncapped board are not yet measured and would read about 380 W by this pair's ratio (an estimate). The rule from the pairs so far: a power cap holds the rate until the SM clock falls below roughly 1.8 GHz on Ampere and 2.4 GHz on Ada", "watts_class": "v3", - "watts_display": "293.5 (class v3)" + "watts_display": "293.5 (class v3, uncapped board)" }, { "generator": "v2", @@ -919,19 +919,18 @@ "group": "buy", "card": "NVIDIA RTX 3070 (8 GB)", "mh_s": 37.09, - "watts": 142.3, - "mh_per_w": 0.261, + "watts": 196.4, + "mh_per_w": 0.189, "driver_os": "NVIDIA driver 580.65.06, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 5 (a rented card, result cb2-rtx-3070-8-gb-qh9j-result.json; 09:32Z)", - "note": "rented single-card host, 0.06 h; power.draw mean 142.3 W (max 146.7, limit 225 W), SM 2,002 MHz mean, memory 6,801 MHz, 57 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (37.14 MH/s, fingerprint matched); read ceiling 37.2 MH/s, the hash at 1.00 of it. Against the 3070 Ti: 5 percent less rate for 25 percent less power, the better owner card of the two; 8 GB holds the class v4 set with room. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "source": "model sweep 2026-10-08, row 5 (a rented card, result cb2-rtx-3070-8-gb-qh9j-result.json; 09:32Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-3070-8-gb-l6mu-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.06 h; power.draw mean 142.3 W (max 146.7, limit 225 W), SM 2,002 MHz mean, memory 6,801 MHz, 57 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (37.14 MH/s, fingerprint matched); read ceiling 37.2 MH/s, the hash at 1.00 of it. Against the 3070 Ti: 5 percent less rate for 25 percent less power, the better owner card of the two; 8 GB holds the class v4 set with room. Class v4 watts (8 October 2026, the rerun, self-test PASS): 196.4 W at 37.11 MH/s, 0.189 MH per watt; the class v3 pack on the same host read 153.4 W at the same rate, so the shadow premium on this card is +28 percent of watts for no rate. this board is capped at 193 W by the host (stock 220) and the class v4 draw sits on the cap with the power-cap bit set while the rate holds, the same shape as the capped 4070 Super; the first Ampere pair", "hive": { "core_mhz": null, "mem_mhz": null, "pl_w": null, "label": "stock (rented card, no clock control on the host; no measured tune point)" }, - "watts_class": "v3", - "watts_display": "142.3 (class v3)" + "watts_display": "196.4 (class v4)" }, { "generator": "v2", @@ -943,19 +942,18 @@ "group": "buy", "card": "NVIDIA RTX 3070 Ti (8 GB)", "mh_s": 38.98, - "watts": 177.1, - "mh_per_w": 0.22, + "watts": 267.6, + "mh_per_w": 0.146, "driver_os": "NVIDIA driver 595.71.05, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 6 (a rented card, result cb2-rtx-3070-ti-8-gb-8528-result.json; 09:33Z)", - "note": "rented single-card host, 0.07 h; power.draw mean 177.1 W (max 183.6, limit 290 W), SM 1,955 MHz mean, memory 9,251 MHz, 67 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (39.12 MH/s, fingerprint matched); read ceiling 39.1 MH/s, the hash at 1.00 of it. Repeats the 7 October row on another host (38.98 then, 38.98 now; 178 then 177 W), so the class v4 number is host-independent to 0.1 percent. Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "source": "model sweep 2026-10-08, row 6 (a rented card, result cb2-rtx-3070-ti-8-gb-8528-result.json; 09:33Z); the class v4 watts rerun, 8 October 2026 (result cb4-rtx-3070-ti-8-gb-7705-result.json, the v4-devnet-epoch0 pack, sub-version 3, three runs of about 30 s, the class v3 pack paired on the same host)", + "note": "rented single-card host, 0.07 h; power.draw mean 177.1 W (max 183.6, limit 290 W), SM 1,955 MHz mean, memory 9,251 MHz, 67 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (39.12 MH/s, fingerprint matched); read ceiling 39.1 MH/s, the hash at 1.00 of it. Repeats the 7 October row on another host (38.98 then, 38.98 now; 178 then 177 W), so the class v4 number is host-independent to 0.1 percent. Class v4 watts (8 October 2026, the rerun, self-test PASS): 267.6 W at 39.1 MH/s, 0.146 MH per watt; the class v3 pack on the same host read 180.4 W at the same rate, so the shadow premium on this card is +48.3 percent of watts for no rate. the same board as the 7 October row (offer 36538839), uncapped (a 310 W AIB); the uncapped GDDR6X Ampere premium sits with the 4080's and the 5070's rather than the 192-bit Ada third, so the premium scales with the SM the board had idle under class v3", "hive": { "core_mhz": null, "mem_mhz": null, "pl_w": null, "label": "stock (rented card, no clock control on the host; no measured tune point)" }, - "watts_class": "v3", - "watts_display": "177.1 (class v3)" + "watts_display": "267.6 (class v4)" }, { "generator": "v2", @@ -1232,15 +1230,14 @@ "watts": null, "mh_per_w": null, "driver_os": "NVIDIA driver 595.91.07, Ubuntu 24.04 (CUDA 12.8.1 image)", - "source": "model sweep 2026-10-08, row 18 (a rented card, result cb2-rtx-4060-8-gb-0672-result.json; 09:53Z)", - "note": "watts not read: this host exposes no power sensor (every power field absent on all 244 samples, as the 7 October 4060 host); a third host is being rented for the watts, and the card's draw is about 60 to 70 W by its 115 W limit and the 4060 Ti's 79 W, an estimate until then. Rented single-card host, 0.12 h; SM 2,732 MHz mean, memory 8,251 MHz, 57 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (19.11 MH/s, fingerprint matched); read ceiling 30.2 MH/s, the hash at 0.63 of it (the 128-bit bus: the independent-read line binds, as on the 2070 Super). Repeats the 7 October row (19.09 then, 19.10 now). Watts are class v3 (read 8 October 2026, 11:4x UK): the fleet's bench pack was the class v3 program (program_class v3, generator 3, load_class mx8-erad810f22d), so this row's watts and MH per watt are class v3 figures; the rate holds under class v4 (memory-bound: a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4). The class v4 watts rerun on the same models lands with its date, the v3 watts kept beside as the shadow premium per card", + "source": "model sweep 2026-10-08, row 18 (a rented card, result cb2-rtx-4060-8-gb-0672-result.json; 09:53Z); the class v4 rerun, 8 October 2026 (result cb4-rtx-4060-8-gb-7165-result.json: the rate on both classes, no watts)", + "note": "watts not reported by any rented host (four 4060 boards across 7 and 8 October, one machine family, every power field absent; two other hosts never answered ssh); the class v4 rerun on 8 October read the same rate on both classes (19.09 MH/s class v4, 19.094 class v3) and still no watts; by the 4060 Ti pair on the same silicon (+33.6 percent) the class v4 draw is about 80 to 90 W from a class v3 draw of about 60 to 70 W under the 115 W limit, an estimate until an owner measures at the wall.12 h; SM 2,732 MHz mean, memory 8,251 MHz, 57 C, no throttle reason; self-test PASS (96 of 96 vector lanes); the class v5 kit holds the rate (19.11 MH/s, fingerprint matched); read ceiling 30.2 MH/s, the hash at 0.63 of it (the 128-bit bus: the independent-read line binds, as on the 2070 Super). Repeats the 7 October row (19.09 then, 19.10 now)", "hive": { "core_mhz": null, "mem_mhz": null, "pl_w": null, "label": "stock (rented card, no clock control on the host; no measured tune point)" - }, - "watts_class": "v3" + } }, { "generator": "v2", diff --git a/site/miners.html b/site/miners.html index fc752c59c..2c981c3ff 100644 --- a/site/miners.html +++ b/site/miners.html @@ -268,7 +268,7 @@ table.bench2 tr.detail .d{display:block;margin:0 0 4px}table.bench2 tr.detail b{

    The rented model sweep of 8 October 2026 (23 rows, 22 models, every row untuned) found the rate cap-proof: a card on a host power cap gives the same MH/s as an uncapped one. Class v5 held the rate on every uncapped card and read 17 to 18 percent under it on the two power-capped hosts (an A4000 at 114 W, a GTX 1080 Ti at 130 W), so a class v5 rate needs the card's power state beside it. The sweep's watts, and the 7 October fleet rows' watts, are class v3 figures: the fleet's bench pack ran the class v3 program, and class v4 draws more for the same rate (a 5070 Ti measured 78.7 MH/s at 141 W on class v3 and 78.8 at 224 W on class v4, 8 October 2026). Those rows are ranked by rate alone; the per-watt claims above come from rows measured under class v4; the class v4 watts rerun lands on each row with its date, the v3 watts kept beside it as the shadow premium per card.

    One row per card on the current class: the class v4 program (the latency-shadow block over the class v3 hash), or a class v3 row re-measured with its class v4 cost on 6 October 2026 or later. MH per wall watt uses board or wall power; a row whose watts are the chip's (Apple silicon: GPU plus DRAM from IOReport) says so and is not ranked on that column. Integrated GPUs are not listed.

    Cards you can buy

    -
    NVIDIA RTX 5090 (32 GB)class v4 133.8 MH/s, 305 W, 0.439 · 2026-10-06136.1 stock (127.7 tuned)0.563226.8 tuned (350 stock) WTuned
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0878.5○ 0.577135.9 (class v3) WStock
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0778.4○ 0.539145.6 (class v3) WStock
    NVIDIA RTX 5080 (16 GB)class v4 +83 W unlocked, +41 W at the best points · 2026-10-0871.4 stock (71.2 tuned)0.486146.6 tuned (253 stock) WTuned
    NVIDIA RTX 3090 Ti (24 GB)class v4 not measured · 2026-10-0762○ 0.248249.5 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0759○ 0.221267.3 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0858.9○ 0.201293.5 (class v3) WStock
    NVIDIA RTX 4090 (24 GB)class v4 not measured · 2026-10-0752.30.285183.1 WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0752○ 0.506102.8 (class v3) WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0852 to 59 by board (58.89 on this host)0.334176.1 (class v4) WStock
    NVIDIA RTX 3090 (24 GB)class v4 not measured · 2026-10-0750not measurednot readStock
    NVIDIA RTX 3080 (10 GB)class v4 not measured · 2026-10-0743.7not measurednot readStock
    NVIDIA RTX 4080 Super (16 GB)class v4 not measured · 2026-10-0842.6○ 0.316134.9 (class v3) WStock
    NVIDIA RTX 4070 Ti Super (16 GB)class v4 not measured · 2026-10-0837 to 41 by board (36.93 on this host)0.268137.8 (class v4) WStock
    NVIDIA RTX 4080 (16 GB)class v4 not measured · 2026-10-0840.70.219185.6 (class v4) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-0739○ 0.219178.3 (class v3) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-0839○ 0.22177.1 (class v3) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0837.1○ 0.261142.3 (class v3) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0733.7not measurednot readStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0733.1○ 0.256129.5 (class v3) WStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0831.7○ 0.316100.4 (class v3) WStock
    NVIDIA RTX 5060 (8 GB)class v4 not measured · 2026-10-0731.3○ 0.41575.4 (class v3) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0731.3○ 0.291107.3 (class v3) WStock
    NVIDIA RTX 4070 Super (12 GB)class v4 not measured · 2026-10-0831.20.288108.4 (class v4) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0831.20.201155.3 (class v4) WStock
    NVIDIA RTX 4070 (12 GB)class v4 +30 W · 2026-10-06310.38979.5 WTuned
    NVIDIA RTX 5060 Ti (16 GB)class v4 0.1 percent rate · 2026-10-0730.90.269114.8 WStock
    Apple M5 Max (40 GPU cores, Metal)class v4 +16 W · 2026-10-0627○ 1.2921 W chip, not wallNo lever
    NVIDIA RTX 3060 (12 GB)class v4 not measured · 2026-10-0726.9○ 0.241111.6 (class v3) WStock
    NVIDIA RTX 2080 Ti (11 GB)class v4 not measured · 2026-10-0826○ 0.116224.6 (class v3) WStock
    NVIDIA RTX 4060 Ti (8 GB)class v4 not measured · 2026-10-0720.1○ 0.25977.5 (class v3) WStock
    NVIDIA RTX 4060 Ti (16 GB)class v4 not measured · 2026-10-0820.10.196102.3 (class v4) WStock
    NVIDIA RTX 2070 Super (8 GB)class v4 not measured · 2026-10-0819.1○ 0.115166 (class v3) WStock
    NVIDIA RTX 4060 (8 GB)class v4 not measured · 2026-10-0819.1not measurednot readStock
    AMD Radeon RX 9070 XT (16 GB)class v4 +2 percent rate · 2026-10-0818.9 (18.8 to 19.2 on the G1 ladder)0.093202 stock WNo lever
    NVIDIA GTX 1080 Ti (11 GB)class v4 not measured · 2026-10-0816.3○ 0.131124.3 (class v3) WStock
    NVIDIA RTX 2060 (6 GB)class v4 not measured · 2026-10-0814.1○ 0.117120.6 (class v3) WStock
    Intel Arc B580 (12 GB)class v4 0.1 percent rate · 2026-10-0711not measurednot readStock
    +
    NVIDIA RTX 5090 (32 GB)class v4 133.8 MH/s, 305 W, 0.439 · 2026-10-06136.1 stock (127.7 tuned)0.563226.8 tuned (350 stock) WTuned
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0878.5○ 0.577135.9 (class v3) WStock
    NVIDIA RTX 5070 Ti (16 GB)class v4 not measured · 2026-10-0778.4○ 0.539145.6 (class v3) WStock
    NVIDIA RTX 5080 (16 GB)class v4 +83 W unlocked, +41 W at the best points · 2026-10-0871.4 stock (71.2 tuned)0.486146.6 tuned (253 stock) WTuned
    NVIDIA RTX 3090 Ti (24 GB)class v4 not measured · 2026-10-0762○ 0.248249.5 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0759○ 0.221267.3 (class v3) WStock
    NVIDIA RTX 3080 Ti (12 GB)class v4 not measured · 2026-10-0858.9○ 0.201293.5 (class v3, uncapped board) WStock
    NVIDIA RTX 4090 (24 GB)class v4 not measured · 2026-10-0752.30.285183.1 WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0752○ 0.506102.8 (class v3) WStock
    NVIDIA RTX 5070 (12 GB)class v4 not measured · 2026-10-0852 to 59 by board (58.89 on this host)0.334176.1 (class v4) WStock
    NVIDIA RTX 3090 (24 GB)class v4 not measured · 2026-10-0750not measurednot readStock
    NVIDIA RTX 3080 (10 GB)class v4 not measured · 2026-10-0743.7not measurednot readStock
    NVIDIA RTX 4080 Super (16 GB)class v4 not measured · 2026-10-0842.6○ 0.316134.9 (class v3) WStock
    NVIDIA RTX 4070 Ti Super (16 GB)class v4 not measured · 2026-10-0837 to 41 by board (36.93 on this host)0.268137.8 (class v4) WStock
    NVIDIA RTX 4080 (16 GB)class v4 not measured · 2026-10-0840.70.219185.6 (class v4) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-0739○ 0.219178.3 (class v3) WStock
    NVIDIA RTX 3070 Ti (8 GB)class v4 not measured · 2026-10-08390.146267.6 (class v4) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0837.10.189196.4 (class v4) WStock
    NVIDIA RTX 3070 (8 GB)class v4 not measured · 2026-10-0733.7not measurednot readStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0733.1○ 0.256129.5 (class v3) WStock
    NVIDIA RTX 3060 Ti (8 GB)class v4 not measured · 2026-10-0831.7○ 0.316100.4 (class v3) WStock
    NVIDIA RTX 5060 (8 GB)class v4 not measured · 2026-10-0731.3○ 0.41575.4 (class v3) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0731.3○ 0.291107.3 (class v3) WStock
    NVIDIA RTX 4070 Super (12 GB)class v4 not measured · 2026-10-0831.20.288108.4 (class v4) WStock
    NVIDIA RTX 4070 Ti (12 GB)class v4 not measured · 2026-10-0831.20.201155.3 (class v4) WStock
    NVIDIA RTX 4070 (12 GB)class v4 +30 W · 2026-10-06310.38979.5 WTuned
    NVIDIA RTX 5060 Ti (16 GB)class v4 0.1 percent rate · 2026-10-0730.90.269114.8 WStock
    Apple M5 Max (40 GPU cores, Metal)class v4 +16 W · 2026-10-0627○ 1.2921 W chip, not wallNo lever
    NVIDIA RTX 3060 (12 GB)class v4 not measured · 2026-10-0726.9○ 0.241111.6 (class v3) WStock
    NVIDIA RTX 2080 Ti (11 GB)class v4 not measured · 2026-10-0826○ 0.116224.6 (class v3) WStock
    NVIDIA RTX 4060 Ti (8 GB)class v4 not measured · 2026-10-0720.1○ 0.25977.5 (class v3) WStock
    NVIDIA RTX 4060 Ti (16 GB)class v4 not measured · 2026-10-0820.10.196102.3 (class v4) WStock
    NVIDIA RTX 2070 Super (8 GB)class v4 not measured · 2026-10-0819.1○ 0.115166 (class v3) WStock
    NVIDIA RTX 4060 (8 GB)class v4 not measured · 2026-10-0819.1not measurednot readStock
    AMD Radeon RX 9070 XT (16 GB)class v4 +2 percent rate · 2026-10-0818.9 (18.8 to 19.2 on the G1 ladder)0.093202 stock WNo lever
    NVIDIA GTX 1080 Ti (11 GB)class v4 not measured · 2026-10-0816.3○ 0.131124.3 (class v3) WStock
    NVIDIA RTX 2060 (6 GB)class v4 not measured · 2026-10-0814.1○ 0.117120.6 (class v3) WStock
    Intel Arc B580 (12 GB)class v4 0.1 percent rate · 2026-10-0711not measurednot readStock

    38 cards. Details opens a card's Hive flight-sheet values, its full class v4 cost, miner, source and note.

    Datacentre (13 cards, rented for the measurement; about three times the rented dollars per hash of a desktop card)
    NVIDIA B200 (180 GB)class v4 not measured · 2026-10-07416.4○ 0.487855.6 (class v3) WStock
    NVIDIA H200 SXM (141 GB)class v4 not measured · 2026-10-07313○ 0.723432.9 (class v3) WStock
    NVIDIA H100 SXM (80 GB)class v4 not measured · 2026-10-07248.7○ 0.645385.6 (class v3) WStock
    NVIDIA H100 SXM (80 GB HBM3)class v4 not measured · 2026-10-08248.3○ 0.605411.7 (class v3) WStock
    NVIDIA A100 PCIe (80 GB)class v4 not measured · 2026-10-07155○ 0.517299.6 (class v3) WStock
    NVIDIA A100 SXM (80 GB)class v4 not measured · 2026-10-07138.4○ 0.52266.3 (class v3) WStock
    NVIDIA A100 SXM4 (80 GB)class v4 not measured · 2026-10-08138.1○ 0.515268.6 (class v3) WStock
    NVIDIA RTX PRO 6000 Blackwell (96 GB)class v4 not measured · 2026-10-07130.5○ 0.452288.7 (class v3) WStock
    NVIDIA L40S (48 GB)class v4 not measured · 2026-10-0856.4○ 0.256220.7 (class v3) WStock
    NVIDIA L40S (48 GB)class v4 not measured · 2026-10-0756.4○ 0.234240.7 (class v3) WStock
    NVIDIA RTX A6000 (48 GB)class v4 not measured · 2026-10-0853.6○ 0.224239.1 (class v3) WStock
    NVIDIA RTX A5000 (24 GB)class v4 not measured · 2026-10-0747.6not measurednot readStock
    NVIDIA RTX A4000 (16 GB)class v4 not measured · 2026-10-0831.4○ 0.279112.8 (class v3) WStock