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+# Counter ASIC: the public description in four levels
+
+the project lead, 5 October 2026 (night): "not an information overload". Four levels; the layer names appear only from level 3 down, next to their numbers. Numbers come from the final table of `docs/plans/counter-asic-2-status.md`; a number still owed is marked `[owed: ...]`, never guessed. the project lead's copy law throughout.
+
+## Level 1: one sentence (site hero, litepaper abstract)
+
+Built for graphics cards. A custom chip gains under 2x, and the model and the bounty are public.
+
+## Level 2: one site card, one short litepaper section
+
+Three ideas, no layer names, no widths, no SRAM.
+
+**The hash rewrites itself.** A new program every hour, drawn from the chain. Its memory pattern and its read widths change with it. The rules change on a schedule fixed at launch. No release, no vote.
+
+**It waits on memory, not maths.** Every hash is a chain of random reads into a table too big for a chip to carry. The wait is the same physics for everyone.
+
+**Miners hold the switch.** Spare defences are written into the rules, switched off. A 90% miner signal turns one on. No fork.
+
+A custom chip gains under 2x. Model published, bounty standing. [link: the numbers page]
+
+Litepaper only, a fourth paragraph: No hash has stayed free of chips forever. Igneum does not claim to. It claims the gain is small, the response takes a week, and both are measured.
+
+Site card placement: the Mine section of `site/index.html` beside "no chip can be built for it" (which this card replaces: the claim is a bounded gain, not impossibility). Litepaper placement: `site/litepaper.html` section `mining`, replacing the paragraph that begins "Everything above is automatic" and the "What Igneum does not claim" line on chips; the vs RandomX table keeps its rows, with the "Changes over time" row's Igneum cell reading "A new program every hour, its memory pattern and read widths with it; era draws and reserved families on a schedule fixed at genesis".
+
+## Level 3: the numbers page (`site/bench.html`, section "Counter ASIC")
+
+Per card, the bench table: the v2 class and the v3 class, hash rate, bytes per hash, the latency-bound share (rate over the card's random-read ceiling per load), the CPU verifier per warp, with machine, date and command. The chip model before and after Counter ASIC 2.0 (the m16 model's gain arithmetic at the v2 class and at the v3 class, with the SRAM a mirror needs, cited or approximate as the analysis says). The bounty terms (spec O-1.17: the leaderboard by card model, the standing bounty for any chip design beating a GPU by more than 2x, January 2027). Here the layers are named next to their numbers: read width, per-program mix, scratch, era layout, working set, hot table, cache schedule, the reserved integer-matrix family.
+
+| Card | v2 MH/s | v3 MH/s | v3 bytes per hash | Latency-bound share v3 | Verifier ms per warp v3 |
+|---|---|---|---|---|---|
+| Apple M5 Max (Metal) | 27.7 | [owed: readwidth table] | | | |
+| RTX 5090 (CUDA) | [owed] | [owed] | | | |
+| RX 9070 XT (OpenCL, eGPU) | 18.0 | [owed] | | | |
+
+Chip model, before and after: [owed: from docs/analysis/sram-mirror.md and the hot-table and scratch analyses].
+
+## Level 4: the analysis documents
+
+`docs/plans/counter-asic-2.md` (the plan and the layer table), `docs/plans/read-width.md`, `docs/plans/era-layout.md`, `docs/plans/hot-table.md`, `docs/analysis/scratch-soundness.md`, `docs/analysis/sram-mirror.md`, `docs/analysis/int8-matrix-family.md`, `docs/analysis/m16-recompute-attacker-2026-10-05.md`, the bench log entries of 5 October 2026 (night), the specification sections 1.4 to 1.13.