diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md
index 6c87f93c6..ec5ba3297 100644
--- a/docs/plans/counter-asic-3-status.md
+++ b/docs/plans/counter-asic-3-status.md
@@ -20,7 +20,7 @@ The test every result is judged against (the project lead, 6 October): a chip ma
 | 2 | Per-day item-derivation program (reserve entry, verifier gate, daily build) | ca3-derive | INTERIM merged (acb96ee, dd5041b); 5090 job queued on PC 2 | GO as reserve R0; NO-GO for genesis-live at dr736 (verifier 4.9 ms per unit on one M5 Max core, about 12 ms on a 2019-class core by the 2.5x rule, over the gate; dr368 2.69 ms passes both); urgency LOW after item 1 (the stored-dataset chip derives no item) |
 | 4 + 5 | Share-pattern detector, trigger rules, FPGA lane, layer 9 against 7 | ca3-detector | CLOSED, merged (c0642af, merge ed06814) | detector.mjs + 7 of 7 tests + one observer hook, dry run quiet on the devnet (max correlation 0.53 against the 0.8 edge; excess spread 0 to 5.2 percent); funding.md rule 5: bounty escrowed and benchmark live before daily issuance crosses USD 20,000 a day; epoch-length.md sections 11 and 12: signal trigger M = 6 windows; FPGA soft overlay 0.30x to 0.39x per watt on the measured basis, 0.7x to 1.9x at the bank-bound ceiling (unmeasured); layer 9 ranks above layer 7. The live observer is NOT restarted yet: the write path is untested; one restart after item 7's hook merges, then the first live detector row is recorded here |
 | 3 | Cryptanalysis brief in funding.md | ca3-crypto-brief | CLOSED, merged (43c3ead) | funding.md line item USD 80k to 160k, reviewer shortlist, ranked break list; verdict GO to commission (no outreach, no spend) |
-| 6 + 7 | Reserve order with step costs, vendor-share metric | ca3-reserve | running (Mac first; 5090 job after PC 2 clears) | |
+| 6 + 7 | Reserve order with step costs, vendor-share metric | ca3-reserve | merged to 6422b6f (merge fcce185); the 5090 family job queued on PC 2 | proposed reserve order R1 byte permute, R2 popcount and clz, R3 indexed shuffle, R4 bit-field extract, R5 variable shifts, R6 select, R7 andn, R8 mm8 (`docs/plans/counter-asic-3-reserve.md`, a decision for the project lead, not in the spec); vendor-share.mjs with tests and one observer hook; repro.md carried from repro-bench (dda9fa3) with section 8: today's devnet NVIDIA 0.986 of blue blocks, Intel 0.014, coverage 1.00 at 135.8 MH/s with PC 1 off |
 | 8 (added by item 1's finding, coordinator 08:xx UTC) | Program work in the latency shadow: the hash rate, watts and verifier cost at N = 50,000, 100,000, 200,000 ops per hash on the M5 Max and the 5090; the 5090 power-cap rows | ca3-shadow | running (Mac first; 5090 job after PC 2 clears) | |
 
 ## 3. Measured numbers
@@ -87,6 +87,7 @@ Step cost per family on the M5 Max as a ratio to the add-xor-rotate chain (881 G
 | Found by | What was wrong | Fixed |
 |---|---|---|
 | item 3 (43c3ead) | spec 01 section 1.13.1's era table and `docs/plans/mixer-x4.md` section 2 still said `mixer_mult = 4`; the code (`LoadClass::MX8`, `V3_CLASS`) and spec 1.8.5 say 8 | both lines corrected on ca3-coord, 6 October 2026 |
+| the coordinator's merge of ca3-shadow | `git add -A docs` staged `docs/bench-log.md` with its conflict markers inside (a conflicted path is marked resolved by `git add`), so 45f3019 carried markers into HEAD; found at the ca3-reserve merge as nested markers | the three 6 October entries kept in order with every marker removed (fcce185); a tracked-file marker check added to CI (below) so the shape fails the build next time |
 | the merge of ca3-derive and ca3-shadow | both added a field to `LoadClass` (`derive_len`, `shadow`); resolved as the union, every other literal spreads `..`; `cargo test -p igneum-pow` on the merged tree (cargo 1.99 at `~/.cargo/bin`; the Homebrew 1.69 on PATH cannot read the lock file): 59 + 7 + 4 + 19 + 7 = 96 passed, 0 failed, the pinned v2 and v3 packs byte for byte | merged 09:10 UTC |
 | item 3 | the mixer's op count: 144 integer ops per application as written in `memhard.rs` (128 with RC and rk hoisted) against the 130 the chip model prices (`chip-model-v3.md` section 1, from spec 1.8.4) | items 1 and 2 asked to state which figure their rows use and why; the status close carries the answer |