diff --git a/docs/evidence.md b/docs/evidence.md index 5f454be6..9cb19a95 100644 --- a/docs/evidence.md +++ b/docs/evidence.md @@ -41,7 +41,7 @@ Versions in the table: `igneum-pow` is the Rust crate at `igneum-pow/Cargo.toml` | 14 | Ethereum bytecode runs unchanged, with the documented differences of spec 7.1 | Homepage Build card; litepaper Building | tested by the team | as row 13; fixes `F-exec-A`, `F-exec-B` (spec 7.5) | `tools/evm-smoke/smoke.mjs`: deploy via viem, `increment`, `hashLoop`, `eth_estimateGas`, `eth_getLogs`; `tools/exec-attacks` scenarios 1 and 3; bench-log "execution layer attack fixes" | Deployment, calls, reverts, logs and gas estimates behave as viem expects; chain id 4463; the prototype pgas table gives 0.0095 to 0.028 pgas per gas, below the design's band before calibration, 3 October 2026. 4 October 2026: a transaction that would cross the block's proving budget is refused by the mempool and, if forced in, aborted and charged with its nonce advanced (25 of 25 checks; 30 of 30 malformed cases). Apple M5 Max. The `Prover` precompile, proof records and the shard planner are not in the node | none yet | | 15 | Every block is proven, with the proof landing within about a minute at launch | Homepage stats ("~60 s to a proof"); litepaper Proving; roadmap phase 3 gate | implemented | repo `d7e1f89` (GPU proof), `e01a3cc`, `292e800`, `eedd136` (`proving/igneum-prove`: shard cutter, MPT witnesses, shard and aggregator guests); SP1 6.8.1; spec 7.2, 7.6 | `proving/windows-wsl2` (SETUP-PROVER, PROVE-BLOCK) on the RTX 5090; `igneum-prove-host --mode block` on `proving/fixtures/`; bench-log "proving v0 on the RTX 5090" and "proving: devnet v4 shards" | First GPU proof of an Igneum block, 4 October 2026, RTX 5090 (WSL2, SP1 cuda, mining paused): fixture `block-78-increment` (2 transactions), core proof 1.4 s (7.3 MB, verify 0.221 s), compressed proof 2.7 s (1.27 MB, verify 0.038 s), post-state and receipts roots identical to the node's; 15.7x and 20.6x faster than a loaded M5 Max CPU. The same day on that CPU (load 38 to 47): a three-shard block proved shard by shard and aggregated by recursion, 19 min (1,139 s) end to end, 245 to 337 s per compressed shard proof, every proof verified. What is not there: no proof is produced, carried or checked on the chain (the devnet prover is a stub that signs claims), the proving pool pays nobody (row 21), the block proven is far below one shard, and the 60-second figure remains a design target; the pass mark is the standard in `docs/benchmarks/proving-e2e.md`. Second RTX 5090 run, 4 October 2026 evening (job run-20261004-173115): a full shard at the provisional S_p (6.75 M pgas, 60.8 M cycles) executed in 1.63 s, core proof 8.3 s (18.1 MB), compressed proof 10.9 s (1.27 MB, verify 0.040 s); a two-shard block (13.5 M pgas) proved shard by shard (11.7 s and 10.0 s) and aggregated in 2.2 s, 24 s of GPU stages end to end, every proof verified, six tampered witnesses rejected. The two host defects (an abort after the upload, an idle wait that turned out to be an unbuffered 18 MB proof save through the WSL2 file bridge, 24 minutes) are fixed (ledger P20) 5 October 2026, live devnet with real transactions (bench-log "real transactions, the first non-empty shard proven and paid"): block 72704 shard 0, 29 transfers, 5,800 pgas, proven on PC 2 in 34 s, verified on the Mac in 0.297 s and paid 1.7623 IGN, 53 s after the chain block executed; of about 1,400 blocks in the 20-minute window 36 were proven (the one prover takes the newest shard assigned to it), so "every block" is not yet true; a second content shard (72803, all copies skipped) failed the native-execution veto on the exporter's block structure, fixed with fixtures the same day, the node side pending the 0.3.9 rollout 5 October 2026, evening (bench-log "proving v1"): the aggregated segment record, the chain rule and the unproven rule are implemented behind `proving_v1_activation_daa` (branch proving-v1, not on the devnet before 0.3.11); on the RTX 5090 a chain of 8 consecutive live blocks proved and aggregated by recursion in 135.6 s with the miner on the card (17 s a block, one proof of 1,272,909 bytes attesting all 8, verified in 0.04 s); the 3-node fast-time harness paid a segment record 1.0 s after submission and refused a late one after its deadline (21 checks); the devnet itself, with one prover, carried proofs for 2.4% of blocks over 30 minutes at a block-to-record latency p50 44 s, p99 52 s. The "within about a minute" holds per proven block; "every block" needs 18 mining 5090s or 6 proving-only cards at empty blocks on the measured rates, and the mandatory rule stays off until the share is one | none yet | | 16 | A 12 GB card proves one shard in about 20 s (WITHDRAWN 5 October 2026: a 24 GB card proves a full shard at the adopted size in 4.3 s; 32 GB mines and proves) | Litepaper Proving ("The proving budget"); roadmap gate 2 | designed | spec 5.1 (Target), 7.6 (`S_p` provisional, 7,500,000 pgas = `B_p` / 4) | `PROVE-SHARD.bat` on the RTX 5090 (pending); the end-to-end standard in `docs/benchmarks/proving-e2e.md`; bench-log "proving: devnet v4 shards" | Measured on a 32 GB card, not yet on a 12 GB card. A shard at the provisional `S_p` is 60.8 M SP1 cycles on the prototype pgas table (9 cycles per pgas, 44 per EVM gas; the modexp entry about 100x its SP1 cost); on an RTX 5090 (4 October 2026 evening, job run-20261004-173115) it executed in 1.63 s and its compressed proof took 10.9 s, verified in 0.040 s, so the 32 GB card is inside the 20 s target with margin. Whether a 12 GB card proves it at all, and in what time, is the next measurement (an RTX 3060 and an RTX 5060 Ti 16 GB are on order). A per-shard time can be met by shrinking the shard, so the project does not use it as a pass mark 5 October 2026, evening (bench-log "proving v1", the S_p curve): measured on the RTX 5090 with SP1 6.8.1's GPU prover, the card to itself, 1-s nvidia-smi samples: an empty shard 13,874 MiB and 2.2 s; a full shard at the ADOPTED v1 budget (30,000 pgas, 4.7 M cycles) 20,434 MiB and 4.3 s; the full prototype shard (6.75 M pgas, 60 M cycles) 28,307 MiB and 10.8 s; beside the miner 15,670 and 30,039 MiB. No environment knob of SP1 moves the 13.9 GB floor and the GPU server has no options of its own, so on this build a 12 GB card proves nothing, a 16 GB card only empty shards, a 24 GB card the adopted full shard alone and beside the miner (22,210 MiB and 13.2 s, measured on the 32 GB card: the 5090's allocation pattern, not yet a run on a 24 GB card) and a 32 GB card the prototype shard beside the miner with 2.5 GB spare. The litepaper line now says so; the 12 GB gate returns when a prover build with a smaller floor is measured on a 12 GB card | none yet | -| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (k = 1) to 3.9x (k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 12 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 core claimed and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.9x, 2.8x at launch; 1.067x at the ceiling; 12 percent on 12 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026). | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word | +| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (k = 1) to 3.9x (k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 core claimed and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.9x, 2.8x at launch; 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026). | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word | | 18 | The chip resistance measurements: the program is latency-bound (random reads), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache | Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page | tested by the team | readwidth e752fc7 (`docs/plans/read-width.md`), ca2-era 78c0ee4, ca2-cache 2de19e5 (`docs/plans/hot-table.md`) | The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per load | Latency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026 | none yet | | 19 | The lottery hash is sound as a hash: uniform output, deterministic, no out-of-bounds read, fuzzed; class v3 bit-exact on the three vendors | Litepaper vs RandomX ("Every number above is measured and logged"), the numbers page | tested by the team | ca2-mixer 1ab8b21 (`tests/mixer.rs`, `tests/scratch.rs`), ca2-era 78c0ee4, ca2-soundness a465881 (`docs/analysis/scratch-soundness.md`), `igneum-pow/tests/packs.rs` | The crate suite (53 + 4 + 19 + 7), the Metal fuzz, edge, stats and determinism runs on the v3 construction, the pack vectors and 2^24 fingerprints on Metal, Apple OpenCL, the RTX 5090 and the RX 9070 XT, the 1,024-hash CPU re-check per card | Class v3 (mixer x8 + era): 200-program fuzz 200 of 200 on Metal, every tenth on Apple OpenCL; the pinned v3 packs 3/3 + 3/3 and 96 of 96 lanes on Metal and Apple OpenCL; the six era packs' fingerprints equal on the three vendors (PC 1 job run-ca2-era-pc1-20261005, 5 October 2026); the v2 exports byte-identical on the v3 crate; the final-class PC rows and the G2 re-check: job run-ca2-era-pc1b-20261005 (pending at the time of writing) | none yet | | 20 | No premine, no pre-sale, no allocation: every coin is minted by the schedule and every coin goes to the block producer (80%) and the proving pool (20%) | Homepage stats and Economics tiles; litepaper Supply, Economics | implemented | repo `6ac80a3`; fork "igneum-node devnet v0"; `consensus/core/src/igneum.rs`, `coinbase.rs` | `cargo test -p kaspa-consensus-core igneum` (8 pass: subsidy table, ramp, split, cap) and `cargo test -p kaspa-consensus coinbase` (8 pass); `igneum-miner inspect 40`; bench-log "igneum-node devnet v0" | Coinbases on the devnet: 80/20 exact on 39 of 39 single-payee blocks, the 20% to the `igneum-proving-pool-v0` output; the per-second schedule sums to under the 4,000,000,000 cap by less than 100 coins; 3,168,808,781 units per DAA second in years 0 to 2, halving at 63,115,200 DAA s. 3 October 2026, Apple M5 Max. The devnet genesis carries no allocation; the mainnet genesis does not exist yet, so the claim is about the code and the stated rule, not a launch that has happened | none yet | diff --git a/docs/plans/counter-asic-3-public-text-2026-10-07.md b/docs/plans/counter-asic-3-public-text-2026-10-07.md index a5f36ecb..395f618f 100644 --- a/docs/plans/counter-asic-3-public-text-2026-10-07.md +++ b/docs/plans/counter-asic-3-public-text-2026-10-07.md @@ -16,7 +16,7 @@ The chip model. We price the strongest chip we can design against an RTX 5090 an | The same chip at the ladder's second rung (about 200,000 ops per hash), reached by miner signal | about 2.8x | modelled, 7 October 2026 | | Any chip under class v5, where the dataset is the chain's own state | a stateless or stale chip is wrong on every item, so the stored-dataset chip and the recompute chip are removed as categories; the verifier pays 0.2 ms more per warp | designed, 7 October 2026 | | A chip caching the hottest 0.1 percent of items (about 1 MB of SRAM) | bounded at 1.067x at the ceiling, 1.005x on about half the hours and 1.048x on 5 percent | measured census of 1,024 programs, 7 October 2026; the source rule in the next class | -| A per-day FPGA that recomputes the dataset with cheap multipliers on a weak day | at most 12 percent more hash rate on 12 days a century, nothing on the other days and nothing for any chip | measured census of 2^24 days, 7 October 2026; the rule in the next class | +| A per-day FPGA that recomputes the dataset with cheap multipliers on a weak day | at most 12 percent more multiplier area on an FPGA's per-day build on 15 days a century, nothing on the other days and nothing for any chip | measured census of 2^24 days, 7 October 2026; the rule in the next class | | When a stored-dataset chip pays for itself | at about USD 100 M of market cap in the first two years, not before | modelled, 7 October 2026 | | The baseline the work started from: the same chip under class v3, without the shadow (the Ethash class) | 5x to 9x (5.1x on GDDR7, 9.2x on eight HBM3 stacks; the Ethash chips of this class reached 2.1x to 4.8x) | modelled, 6 October 2026; the precedent measured by others, 2020 to 2022; never the launch state | @@ -30,4 +30,4 @@ Your card against the strongest chip we can price: an RTX 5090 at 136 MH/s on 35 | # | Claim | Where it is made | Status | Version or commit | Reproducible test | Result, date, machine | Independent verification | |---|---|---|---|---|---|---|---| -| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (k = 1) to 3.9x (k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 12 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 core claimed and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.9x, 2.8x at launch; 1.067x at the ceiling; 12 percent on 12 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word | +| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (k = 1) to 3.9x (k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 core claimed and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.9x, 2.8x at launch; 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word | diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 344e5ca6..5d6397dc 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -455,7 +455,7 @@ Reading so far: the class v4 premium at the unlocked clock is +145 W on this car | 1,400 | 134.98 | 316.3 | 0.427 | 134.68 | 228.0 | 0.591 | 1,387 | | unlocked, end | 136.75 | 473.0 | | 136.5x | 329.7 | | 2,843 / 2,850 | -Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of 6 October, which was read at the app's tuned cap) and 88.3 W at the 1,400 MHz lock; v4's rate is +0.18 percent over v3 unlocked and +0.23 percent at the lock; the rate is memory-bound on the whole grid (136.8 to 135.0 MH/s from 2,850 to 1,400); the best MH per watt sits at the lowest lock on the grid, so the knee is below 1,400 MHz. the founder's thesis holds in part: 57 W of the 145 W premium comes back by the lock alone; 88 W stays as the shadow's ALU work at the floor clock. Throttle reasons: the SW power-cap governor (0x400) from unlocked to 2,163, the lock itself (0x4) from 2,100 down on v4 and 1,650 down on v3; 75 C at the top, 59 C at 1,400. The owed 5090 clock rows (2,781 / 2,472 / 2,163 / 1,854) are in this table. Per tier: a 5090 owner on class v4 who locks the core at 1,400 MHz pays 316 W instead of 476 W for 1.4 percent less rate, MH per watt up 48 percent, the v4 premium down from 145 to 88 W; the lever is NVIDIA's -lgc through the helper; AMD has the helper's ADLX tune line or nothing; the Mac has no lever. MAIN'S ORDERS ON IT (20:2x UK): (1) the second pass now, 1,400 MHz down to the driver's floor in 100 MHz steps on v4 and the v3 control, to find the knee and the premium at it, then the same grid on the 5080; (2) the knob into Ember Tune for 0.3.23 (after the power-cap search, a core-clock search downward from the cap's point until the rate falls more than 1 percent, taking the best MH/W, the fingerprint on every step, stored per card; the Mac stated as no lever) through the UI lane; (3) the bench table's 5090 row gains the locked point and the class v4 cost column reads the locked premium beside the unlocked one (done: the 1,400 MHz row 134.98 MH/s at 316.3 W, 0.427 MH/W, the Hive values 1,400 / 13,801 / 575 as the driver's default limit). DEVNET 3's FIRST LOCK (the fleet lane): 19:02:46Z, checkpoint 235 LOCKED on block 50266abe... (blue score 7,050), identical on dn3-g1 (signed 98.4 percent of active) and dn3-g2 (100.1 percent), at DAA about 7,298 (the 7,200 window filled at 19:01Z); wave 1 of the second nodes GREEN on all five at 19:17:00Z, wave 2 from 19:17Z; the 0.3.22 pin candidate 34a2dbaa passed its last gate at 19:07Z (the join-and-restart read on dn3-c1 with the N15 line) and the Devnet 3 sweep to it runs. The fleet's 19:03Z table: 43 rows, 44 GPUs, USD 257 a day, today about USD 460 of the ceiling at 19:20Z; dn3-twin (a broken CUDA host) and dn3-q02 (never answered) destroyed; p12-vast, w-target and w-poison repurposed to Devnet 3. THE SITE: a0e0c83a deployed 19:17:28Z with the Hive column. THE BOXES: build-1 read 601 / 552 / 471 and build-2 401 / 417 / 400 at 19:17Z, the sum being adversarial binaries started by hand over ssh at 64 to 89 threads each (the crypto lane's one-sweep lock not holding the sum); MAIN'S RULE for every lane under this one: no run starts on a box except through the build-server lane's `lease pool -- cmd` (landing within the quarter hour); hand-started runs killed by their kill files and re-queued through the lease; the release builds and the v5 suites outrank the sweeps. THE SHIPPER cuts class v5 as 0.3.24 the minute every v5 gate is green, at any hour; this lane's gate board is the only clock. THE (c''') CENSUS NUMBER (the v5 lane, 21:03 UK; 4,600 f8 seeds, box 2, 48 cores, 1,256 s; log docs/design/class-v5-harness/v5-census-4600-0.log): the 0.995 per-site floor rejects 112 of 4,600 class v4 sub-version 3 accepted programs (2.435 percent); the same 112 move to a later class v5 attempt; the attempts mean 2.174 to 2.248 (+3.4 percent; the tail unchanged, max 24 on both); 0 class v5 accepted programs under the floor. The spread of the v4-accepted programs' minimum site ratio at the 2^20 sample: min 0.9807, p0.1 0.9831, p1 0.9906, p5 0.9962, median 0.9999; under 0.98 none, under 0.99 43 (0.935 percent), under 0.995 112, under 0.998 517, under 0.999 868. Two corrections to the relayed premise: the clean spread is not "0.9960 minimum, p1 0.9990" on the chain's own draw (a smaller sample), and 0.99 would NOT refuse the exemplar (0.9919). So 0.995 is the lowest round floor that refuses seed 100767 with the model's spread under it, at one extra draw attempt on 2.4 percent of epochs (about 0.3 s of acceptance each, no consensus cost, no change to the hash or the kits); the band it rejects is where every measured program so far is a weak hot-set program (adv-accept's live-low20 row: the first read, seed 3664 at 1.31x, beyond the 1.2x gate; its four measured lowest-ratio seeds all beyond). The per-site hot-item test is the same statistic at the 2^20 sample and costs 30 s per candidate at 2^24 against the floor's 0 extra, so it is not a competitor. The defender's call: keep 0.995; the freeze commit carries the number into accept.rs and section 14 and goes the minute the full suite and the gate read green (f17849eb staged). THE PRE-PUBLIC SCRUB: master's text pass (9b8eb23a, 3b4b6c63) names the founder as "the founder" in every tracked text file and the CI check founder-strings refuses the name; this record follows it from here (three lines of the efficiency pass reintroduced the name through a merge and are fixed). THE V5 FAST-TIME LINES ON THE FIRST MATCHED PAIR 959b57c9 (igneumd 519ee6c4..., igneum-pow ab6f980b; harness v5-fasttime 6de9cf74): (1) the ladder climb plus the v5 crossing with the stale node: rung 1 by miner signal from epoch 6 at 19:56:38Z; class v5 by signal from epoch 8 (DAA 480) at rung 1 at 19:58:31Z on 3 of 3 honest nodes, byte 6 at 9,985 bps, before the floor; the prelude reads v4 at epochs 0 and 1 (b1680b57 verified); honest nodes 0 PoW rejections; the stale node 122 of 122 refused by its own node; the SUMMARY FAIL at 20:04:00Z on line 3 alone. (2) Digest-compat SUMMARY PASS 20:08:30Z (one digest c0d6998e with the v5 key absent on the new binary and on the pre-v5 control 2720d8d2; the set key moves it to 8d8f6208 with no peer and the refusal line; 180 s of mixed mining, 79 new and 101 old blocks, 0 rejected). (3) THE RESTART STEP FAILED: n2 stopped at DAA 457 and restarted on its own datadir at DAA 500 (19:59:10Z), the IBD catch-up engaged and did not complete: the relay flow treated the engine's "class v5 needs the execution state" on a relayed epoch-8 block as a rule refusal twelve seconds in, the flow error tore down the peer's flows and the catch-up's body sync with them, the block went into the N6 refused memory, the peer was banned 600 s at 20:00:09Z, and the deferred headers were never validated; n2 on its own fork to the end (600 against 660). FIXED by the node lane at a3b2049d on class-v5-node-wire (20:0xZ): the relay flow holds off a block in the v5 state-wait class at its three validation sites (no strike, no N6 memory, the flow stays up; the next inv or the catch-up's deferred chunk brings it back once the executor has the state), is_v5_state_wait shared with the IBD catch-up, kaspa-p2p-flows 38 of 38 at 20:08:23Z. (4) One program id per epoch equal to the CLI's v5 id: 11 of 11 (v4 at rungs 0 and 1, v5 at rung 1 with the window's stream), the Devnet 3 genesis pack's e5a4ac5978462156 reproduced; the known-failed shape FAIL as it must at 19:04:01Z. THE SECOND MATCHED PAIR 63524e28 landed 20:16:49Z on build-1 (/srv/artefacts/v5-pair-63524e28/, igneumd sha256 4f93697f5b97c30205b7e1c8e521924ba85f849a5d35f1470ff0a1b2a17cbbae; fork v5-object-0323 = 959b57c9 + the relay hold-off a3b2049d + the pool lane's tag rename 7455b8d5 + main's chain id by height, Devnet 3 chain id 4464 from the v5 floor; igneum-pow ab6f980b; suites consensus 126, core 154, pow 19, exec 46, p2p-flows 38, miner 25); the fast-time lane re-runs the crossing with the restart step on it; the v5 object commit waits on that PASS, the freeze commit and dn3-g1's DAA at the cut. THE IN-HOUSE PASS: adv-accept's tally at 2^24: of the 16 lowest stand-in-ratio seeds, 9 beyond the 1.2x gate and 3 hot sets (100767 at 2.05x; 4346 at X/f 1.78, 2.24x; 5245 at 1.29, 1.86x); of 17 random accepted programs 1 beyond and 0 hot sets; the selector's false-positive rate 7 of 16 on the gate, 13 of 16 on the hot-set test; each hot set about 1 MB of items at 0.3 percent of reads, 1.002x; whether the 0.995 floor refuses 4346 and 5245 is a measurement in hand (their minimum-site ratios at 2^20), not a given. adv-accept-2 at its natural end (92168536): header grinding BOUND by measurement and by tail (1e8 hashes per real program on the windowed random baseline down to the 3e-7 tail, net gain 3e-7x); the rotate-identity repeat class present in 21.0 percent of 300 drawn programs at under 0.1 percent of loads on the worst, absent from the two real programs, a rule question for the next class. Lanes at a natural end: adv-cache, adv-accept-2. THE SITE: b8f501e9 deployed 20:17:42Z with the compact table; its 1600 px capture read five columns clipped at the article column's edge (about 900 px against a 1,400 px table), so the table now fits the column (nine columns, the generator in the detail row, the text columns wrapping and the numbers not, no forced width). THE FOUNDER'S QUESTION ON THE CLASS V4 PREMIUM ("we need a solution, deep research, other methods, something must be doable even if it is revolutionary"; a research lane, counter-asic-4, on the literature and the alternatives by 23:30Z). THE ONE COMPUTATION FROM THIS LANE (chip-model-v3 section 5.10, on the mirror's master at aa829826): class v5 ON and the shadow at ZERO leaves the strongest chip, the f = 1 stored-dataset chip, at 5.1x (GDDR7, the 5090's own 16 devices without the GPU: 166 MH/s at 78 W with a farm-shared node) to 9.1x (HBM3 eight stacks: 666 MH/s at 175 W) per joule over the 5090's 0.417 MH/W, the class v3 figures of 5.6 less a rounding, because the node is a farm cost and not a chip cost (class-v5 2a.2: one node serves a farm, the leaves ship at 16.5 KB/s to 10,000 members, the rebuild is the same 32 ms per window every GPU pays); only a chip forced to carry its own node (85 W, approximate) falls near 2x, and only the small ones (one HBM3 stack 1.8x, the GDDR7 board 2.5x; the eight-stack package 6.2x). So the shadow stays the only lever in the model that reaches the memory-system chip, and the premium is its price; what class v5 buys is the recompute and stale chips gone as categories and every miner holding and following the chain. THE RESEARCH LANE's READING of the three shapes (21:4x UK; its identity edge = (E_card + F) / (E_mem + k F), F the GPU's premium per hash, k the chip core's energy per op over the GPU's): at the 1,400 MHz lock (v3 1.69 uJ per hash, v4 2.34, the premium 0.65 uJ = 6.5 pJ per counted op) the premium-free edge is 3.6x on GDDR7 and 5.3x on one HBM3 stack, 2.1x at F = 0.65 and k = 1, the asymptote 1/k; the premium needed for 2x at k = 1 is 0.76 uJ (103 W) at the lock and 1.41 uJ (175 W) at the stock point; at k at or under 0.5 no premium reaches 2x; a premium of zero is impossible by any hash-side lever (a joule the chip must spend is a joule the GPU spends first). Shape 1 (the shadow at the floor clock): correct and measured by the 1,400 row; it halves the premium and leaves k as the whole question (the edge's derivative in F at F = 0 is minus 5.7x per uJ at k = 1 and minus 0.2x per uJ at k = 0.3; the family mix with the highest k, shuffles and multiplies, is the right content; the tensor block has k near 1 but 0.056 pJ per MAC, so it forces no joules without 26x the verifier). Shape 2 (per-read work a chip cannot amortise): no construction found (the chip's lane count is set by its own latency, lane state is SRAM at pJ per access, extra reads scale both rates; row, bank, refresh and burst shaping have no asymmetry); one candidate for a measurement, not a claim: a hot table kept L2-resident through cache-policy hints (dataset loads evict-first, hot loads evict-last), since a 64 MiB SRAM read on a chip is not cheaper than a GPU L2 hit (the 3.0 layer 5 measurement used no hints and lost 13 to 16 percent). Shape 3 (the refresh as the cost): dead by arithmetic (a 1 GiB rebuild about 0.1 J on a chip against 280 kJ of hashing an hour). What lowers the premium-free floor is the card's own E_card: the 5090's idle 74 to 91 W plus its memory system's 55 W bound the floor near 2.0x on GDDR7 at any operating point; the two measurements that read how much of the 100 W between is reachable are the knee below 1,400 MHz (the floor pass, on PC 1's queue) and an SM-sparse kernel (the hash on a fraction of the SMs with 4 to 8 chains per thread, the rest clock-gated), both ordered to the hash lane with the L2 cache-policy hot table as PC 1 queue tail items (worker launch shapes, --bench only, no consensus change). THE FIVE RATIOS (adv-accept, 21:35 BST, at the acceptance's 2^20 sample, closed form and live to 1e-4): 4346 (bbb38e847011c354) minimum site 2 at 0.9840 REFUSED by (c''') at 0.995; 5245 (beaad44840bb9e4e) site 8 at 0.9831 REFUSED; 106924 at 0.9821 and 107022 at 0.9877 REFUSED; Devnet 3's epoch-0 class v4 program (fce15bf61030be57) site 0 at 0.9992 (live 0.9993) MISSED; era-fixed-20 (11f9f955b21d56c9) site 11 at 0.9997 MISSED; era-drawn-2 (7ceb797d31eedb3e) site 13 at 0.9992 MISSED. THE DEFENDER'S RULING: the (c''') floor at 0.995 closes the HOT-SET HALF of the class (every program with X_f at or above f that any lane measured, 100767 included) and NOT the class; the residual is the shadow-block-written value-level concentration below a ratio floor's resolution (1.26x to 1.45x of the top 0.1 percent share, 0.03 to 0.1 percent of a hash's reads each, minimum sites 0.9992 to 0.9997, which no floor reaches without sitting inside the clean seeds' own spread), chip gain under 1.001x, its lever a value-level source test at live scale or a per-site hot-item test, routed to the next class as a named item; section 14 of the v5 design says so with the five numbers verbatim; the freeze proceeds on the suite's green, both the floor's number and its reach measured. adv-mixer-2 (49656c2e) confirms AP-F4-1's class from outsider inputs (model A an FPGA LUT-area gain for a per-day build, 1.0 on every GPU, verifier and chip with a general multiplier; P(A at or above 1.1x) = 2^-10.8 per day on the exact median 226; model C under 2^-20 at 1.1x), the two censuses' medians (226 against 231) to be reconciled side by side in the record; its redraw rule to the v5 lane as a second independent statement. The kits lane's box-side body moved to tools/class-v5/kits-on-box.sh run by path under the inline-rm rule (v5-kits 4f9d96d2); the kit zip stands. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of 6 October, which was read at the app's tuned cap) and 88.3 W at the 1,400 MHz lock; v4's rate is +0.18 percent over v3 unlocked and +0.23 percent at the lock; the rate is memory-bound on the whole grid (136.8 to 135.0 MH/s from 2,850 to 1,400); the best MH per watt sits at the lowest lock on the grid, so the knee is below 1,400 MHz. the founder's thesis holds in part: 57 W of the 145 W premium comes back by the lock alone; 88 W stays as the shadow's ALU work at the floor clock. Throttle reasons: the SW power-cap governor (0x400) from unlocked to 2,163, the lock itself (0x4) from 2,100 down on v4 and 1,650 down on v3; 75 C at the top, 59 C at 1,400. The owed 5090 clock rows (2,781 / 2,472 / 2,163 / 1,854) are in this table. Per tier: a 5090 owner on class v4 who locks the core at 1,400 MHz pays 316 W instead of 476 W for 1.4 percent less rate, MH per watt up 48 percent, the v4 premium down from 145 to 88 W; the lever is NVIDIA's -lgc through the helper; AMD has the helper's ADLX tune line or nothing; the Mac has no lever. MAIN'S ORDERS ON IT (20:2x UK): (1) the second pass now, 1,400 MHz down to the driver's floor in 100 MHz steps on v4 and the v3 control, to find the knee and the premium at it, then the same grid on the 5080; (2) the knob into Ember Tune for 0.3.23 (after the power-cap search, a core-clock search downward from the cap's point until the rate falls more than 1 percent, taking the best MH/W, the fingerprint on every step, stored per card; the Mac stated as no lever) through the UI lane; (3) the bench table's 5090 row gains the locked point and the class v4 cost column reads the locked premium beside the unlocked one (done: the 1,400 MHz row 134.98 MH/s at 316.3 W, 0.427 MH/W, the Hive values 1,400 / 13,801 / 575 as the driver's default limit). DEVNET 3's FIRST LOCK (the fleet lane): 19:02:46Z, checkpoint 235 LOCKED on block 50266abe... (blue score 7,050), identical on dn3-g1 (signed 98.4 percent of active) and dn3-g2 (100.1 percent), at DAA about 7,298 (the 7,200 window filled at 19:01Z); wave 1 of the second nodes GREEN on all five at 19:17:00Z, wave 2 from 19:17Z; the 0.3.22 pin candidate 34a2dbaa passed its last gate at 19:07Z (the join-and-restart read on dn3-c1 with the N15 line) and the Devnet 3 sweep to it runs. The fleet's 19:03Z table: 43 rows, 44 GPUs, USD 257 a day, today about USD 460 of the ceiling at 19:20Z; dn3-twin (a broken CUDA host) and dn3-q02 (never answered) destroyed; p12-vast, w-target and w-poison repurposed to Devnet 3. THE SITE: a0e0c83a deployed 19:17:28Z with the Hive column. THE BOXES: build-1 read 601 / 552 / 471 and build-2 401 / 417 / 400 at 19:17Z, the sum being adversarial binaries started by hand over ssh at 64 to 89 threads each (the crypto lane's one-sweep lock not holding the sum); MAIN'S RULE for every lane under this one: no run starts on a box except through the build-server lane's `lease pool -- cmd` (landing within the quarter hour); hand-started runs killed by their kill files and re-queued through the lease; the release builds and the v5 suites outrank the sweeps. THE SHIPPER cuts class v5 as 0.3.24 the minute every v5 gate is green, at any hour; this lane's gate board is the only clock. THE (c''') CENSUS NUMBER (the v5 lane, 21:03 UK; 4,600 f8 seeds, box 2, 48 cores, 1,256 s; log docs/design/class-v5-harness/v5-census-4600-0.log): the 0.995 per-site floor rejects 112 of 4,600 class v4 sub-version 3 accepted programs (2.435 percent); the same 112 move to a later class v5 attempt; the attempts mean 2.174 to 2.248 (+3.4 percent; the tail unchanged, max 24 on both); 0 class v5 accepted programs under the floor. The spread of the v4-accepted programs' minimum site ratio at the 2^20 sample: min 0.9807, p0.1 0.9831, p1 0.9906, p5 0.9962, median 0.9999; under 0.98 none, under 0.99 43 (0.935 percent), under 0.995 112, under 0.998 517, under 0.999 868. Two corrections to the relayed premise: the clean spread is not "0.9960 minimum, p1 0.9990" on the chain's own draw (a smaller sample), and 0.99 would NOT refuse the exemplar (0.9919). So 0.995 is the lowest round floor that refuses seed 100767 with the model's spread under it, at one extra draw attempt on 2.4 percent of epochs (about 0.3 s of acceptance each, no consensus cost, no change to the hash or the kits); the band it rejects is where every measured program so far is a weak hot-set program (adv-accept's live-low20 row: the first read, seed 3664 at 1.31x, beyond the 1.2x gate; its four measured lowest-ratio seeds all beyond). The per-site hot-item test is the same statistic at the 2^20 sample and costs 30 s per candidate at 2^24 against the floor's 0 extra, so it is not a competitor. The defender's call: keep 0.995; the freeze commit carries the number into accept.rs and section 14 and goes the minute the full suite and the gate read green (f17849eb staged). THE PRE-PUBLIC SCRUB: master's text pass (9b8eb23a, 3b4b6c63) names the founder as "the founder" in every tracked text file and the CI check founder-strings refuses the name; this record follows it from here (three lines of the efficiency pass reintroduced the name through a merge and are fixed). THE V5 FAST-TIME LINES ON THE FIRST MATCHED PAIR 959b57c9 (igneumd 519ee6c4..., igneum-pow ab6f980b; harness v5-fasttime 6de9cf74): (1) the ladder climb plus the v5 crossing with the stale node: rung 1 by miner signal from epoch 6 at 19:56:38Z; class v5 by signal from epoch 8 (DAA 480) at rung 1 at 19:58:31Z on 3 of 3 honest nodes, byte 6 at 9,985 bps, before the floor; the prelude reads v4 at epochs 0 and 1 (b1680b57 verified); honest nodes 0 PoW rejections; the stale node 122 of 122 refused by its own node; the SUMMARY FAIL at 20:04:00Z on line 3 alone. (2) Digest-compat SUMMARY PASS 20:08:30Z (one digest c0d6998e with the v5 key absent on the new binary and on the pre-v5 control 2720d8d2; the set key moves it to 8d8f6208 with no peer and the refusal line; 180 s of mixed mining, 79 new and 101 old blocks, 0 rejected). (3) THE RESTART STEP FAILED: n2 stopped at DAA 457 and restarted on its own datadir at DAA 500 (19:59:10Z), the IBD catch-up engaged and did not complete: the relay flow treated the engine's "class v5 needs the execution state" on a relayed epoch-8 block as a rule refusal twelve seconds in, the flow error tore down the peer's flows and the catch-up's body sync with them, the block went into the N6 refused memory, the peer was banned 600 s at 20:00:09Z, and the deferred headers were never validated; n2 on its own fork to the end (600 against 660). FIXED by the node lane at a3b2049d on class-v5-node-wire (20:0xZ): the relay flow holds off a block in the v5 state-wait class at its three validation sites (no strike, no N6 memory, the flow stays up; the next inv or the catch-up's deferred chunk brings it back once the executor has the state), is_v5_state_wait shared with the IBD catch-up, kaspa-p2p-flows 38 of 38 at 20:08:23Z. (4) One program id per epoch equal to the CLI's v5 id: 11 of 11 (v4 at rungs 0 and 1, v5 at rung 1 with the window's stream), the Devnet 3 genesis pack's e5a4ac5978462156 reproduced; the known-failed shape FAIL as it must at 19:04:01Z. THE SECOND MATCHED PAIR 63524e28 landed 20:16:49Z on build-1 (/srv/artefacts/v5-pair-63524e28/, igneumd sha256 4f93697f5b97c30205b7e1c8e521924ba85f849a5d35f1470ff0a1b2a17cbbae; fork v5-object-0323 = 959b57c9 + the relay hold-off a3b2049d + the pool lane's tag rename 7455b8d5 + main's chain id by height, Devnet 3 chain id 4464 from the v5 floor; igneum-pow ab6f980b; suites consensus 126, core 154, pow 19, exec 46, p2p-flows 38, miner 25); the fast-time lane re-runs the crossing with the restart step on it; the v5 object commit waits on that PASS, the freeze commit and dn3-g1's DAA at the cut. THE IN-HOUSE PASS: adv-accept's tally at 2^24: of the 16 lowest stand-in-ratio seeds, 9 beyond the 1.2x gate and 3 hot sets (100767 at 2.05x; 4346 at X/f 1.78, 2.24x; 5245 at 1.29, 1.86x); of 17 random accepted programs 1 beyond and 0 hot sets; the selector's false-positive rate 7 of 16 on the gate, 13 of 16 on the hot-set test; each hot set about 1 MB of items at 0.3 percent of reads, 1.002x; whether the 0.995 floor refuses 4346 and 5245 is a measurement in hand (their minimum-site ratios at 2^20), not a given. adv-accept-2 at its natural end (92168536): header grinding BOUND by measurement and by tail (1e8 hashes per real program on the windowed random baseline down to the 3e-7 tail, net gain 3e-7x); the rotate-identity repeat class present in 21.0 percent of 300 drawn programs at under 0.1 percent of loads on the worst, absent from the two real programs, a rule question for the next class. Lanes at a natural end: adv-cache, adv-accept-2. THE SITE: b8f501e9 deployed 20:17:42Z with the compact table; its 1600 px capture read five columns clipped at the article column's edge (about 900 px against a 1,400 px table), so the table now fits the column (nine columns, the generator in the detail row, the text columns wrapping and the numbers not, no forced width). THE FOUNDER'S QUESTION ON THE CLASS V4 PREMIUM ("we need a solution, deep research, other methods, something must be doable even if it is revolutionary"; a research lane, counter-asic-4, on the literature and the alternatives by 23:30Z). THE ONE COMPUTATION FROM THIS LANE (chip-model-v3 section 5.10, on the mirror's master at aa829826): class v5 ON and the shadow at ZERO leaves the strongest chip, the f = 1 stored-dataset chip, at 5.1x (GDDR7, the 5090's own 16 devices without the GPU: 166 MH/s at 78 W with a farm-shared node) to 9.1x (HBM3 eight stacks: 666 MH/s at 175 W) per joule over the 5090's 0.417 MH/W, the class v3 figures of 5.6 less a rounding, because the node is a farm cost and not a chip cost (class-v5 2a.2: one node serves a farm, the leaves ship at 16.5 KB/s to 10,000 members, the rebuild is the same 32 ms per window every GPU pays); only a chip forced to carry its own node (85 W, approximate) falls near 2x, and only the small ones (one HBM3 stack 1.8x, the GDDR7 board 2.5x; the eight-stack package 6.2x). So the shadow stays the only lever in the model that reaches the memory-system chip, and the premium is its price; what class v5 buys is the recompute and stale chips gone as categories and every miner holding and following the chain. THE RESEARCH LANE's READING of the three shapes (21:4x UK; its identity edge = (E_card + F) / (E_mem + k F), F the GPU's premium per hash, k the chip core's energy per op over the GPU's): at the 1,400 MHz lock (v3 1.69 uJ per hash, v4 2.34, the premium 0.65 uJ = 6.5 pJ per counted op) the premium-free edge is 3.6x on GDDR7 and 5.3x on one HBM3 stack, 2.1x at F = 0.65 and k = 1, the asymptote 1/k; the premium needed for 2x at k = 1 is 0.76 uJ (103 W) at the lock and 1.41 uJ (175 W) at the stock point; at k at or under 0.5 no premium reaches 2x; a premium of zero is impossible by any hash-side lever (a joule the chip must spend is a joule the GPU spends first). Shape 1 (the shadow at the floor clock): correct and measured by the 1,400 row; it halves the premium and leaves k as the whole question (the edge's derivative in F at F = 0 is minus 5.7x per uJ at k = 1 and minus 0.2x per uJ at k = 0.3; the family mix with the highest k, shuffles and multiplies, is the right content; the tensor block has k near 1 but 0.056 pJ per MAC, so it forces no joules without 26x the verifier). Shape 2 (per-read work a chip cannot amortise): no construction found (the chip's lane count is set by its own latency, lane state is SRAM at pJ per access, extra reads scale both rates; row, bank, refresh and burst shaping have no asymmetry); one candidate for a measurement, not a claim: a hot table kept L2-resident through cache-policy hints (dataset loads evict-first, hot loads evict-last), since a 64 MiB SRAM read on a chip is not cheaper than a GPU L2 hit (the 3.0 layer 5 measurement used no hints and lost 13 to 16 percent). Shape 3 (the refresh as the cost): dead by arithmetic (a 1 GiB rebuild about 0.1 J on a chip against 280 kJ of hashing an hour). What lowers the premium-free floor is the card's own E_card: the 5090's idle 74 to 91 W plus its memory system's 55 W bound the floor near 2.0x on GDDR7 at any operating point; the two measurements that read how much of the 100 W between is reachable are the knee below 1,400 MHz (the floor pass, on PC 1's queue) and an SM-sparse kernel (the hash on a fraction of the SMs with 4 to 8 chains per thread, the rest clock-gated), both ordered to the hash lane with the L2 cache-policy hot table as PC 1 queue tail items (worker launch shapes, --bench only, no consensus change). THE FIVE RATIOS (adv-accept, 21:35 BST, at the acceptance's 2^20 sample, closed form and live to 1e-4): 4346 (bbb38e847011c354) minimum site 2 at 0.9840 REFUSED by (c''') at 0.995; 5245 (beaad44840bb9e4e) site 8 at 0.9831 REFUSED; 106924 at 0.9821 and 107022 at 0.9877 REFUSED; Devnet 3's epoch-0 class v4 program (fce15bf61030be57) site 0 at 0.9992 (live 0.9993) MISSED; era-fixed-20 (11f9f955b21d56c9) site 11 at 0.9997 MISSED; era-drawn-2 (7ceb797d31eedb3e) site 13 at 0.9992 MISSED. THE DEFENDER'S RULING: the (c''') floor at 0.995 closes the HOT-SET HALF of the class (every program with X_f at or above f that any lane measured, 100767 included) and NOT the class; the residual is the shadow-block-written value-level concentration below a ratio floor's resolution (1.26x to 1.45x of the top 0.1 percent share, 0.03 to 0.1 percent of a hash's reads each, minimum sites 0.9992 to 0.9997, which no floor reaches without sitting inside the clean seeds' own spread), chip gain under 1.001x, its lever a value-level source test at live scale or a per-site hot-item test, routed to the next class as a named item; section 14 of the v5 design says so with the five numbers verbatim; the freeze proceeds on the suite's green, both the floor's number and its reach measured. adv-mixer-2 (49656c2e) confirms AP-F4-1's class from outsider inputs (model A an FPGA LUT-area gain for a per-day build, 1.0 on every GPU, verifier and chip with a general multiplier; P(A at or above 1.1x) = 2^-10.8 per day on the exact median 226; model C under 2^-20 at 1.1x), the two censuses' medians (226 against 231) to be reconciled side by side in the record; its redraw rule to the v5 lane as a second independent statement. The kits lane's box-side body moved to tools/class-v5/kits-on-box.sh run by path under the inline-rm rule (v5-kits 4f9d96d2); the kit zip stands. MAIN'S RULINGS (21:4x UK). (1) The class v5 freeze does not wait on the three milder concentrations the 0.995 floor misses (Devnet 3's first program among them): their chip gain is bounded under 1.002x by their size, so the freeze proceeds with the floor as it is, the record names them as the residual, and the fix question (a value-level source test at live scale) is a 0.3.25 item. (2) The weak-day census reconciled at median 226 (F4's NAF weight had counted the carry digit at position 32, which a 32-bit multiplier never pays; 0.333 digits per word, 5.3 adders per day, the whole of 231 against 226 and of 12 against 15 days a century, the same worst day in both; F4's record section 9 carries both medians side by side, mirrored in adv-mixer-2's report): 5.69e-4 of days (2^-10.8), 15 days a century over 1.1x on FPGA LUT area, worst 2050-04-28 at 1.113x, the DSP-bound readings at 0 for k at least 2, F4's PASS against class v4 unchanged; every public text saying "12 days a century" becomes "15 days a century" (done in this landing on the litepaper table, /claims through it, evidence row 17 and the public text file, the sentence now "at most 12 percent more multiplier area on an FPGA's per-day build on 15 days a century, nothing on the other days and nothing for any chip"); the site audit lane told. (3) THE HALVING, ruled to the fleet (21:4x UK), neither (a) nor (b) as written: on every standing box the OLD shared-devnet miner stops and the Devnet 3 miner keeps the card at full rate (one miner per card, the exception over); hub-1, pool-1 and the live seed stay on the old chain as its voters and miners until every poller has moved; the old-chain nodes on the boxes stay up as voters without mining; no 3070 fallback; the fleet reports per-box restore lines. THE IN-HOUSE PASS, MORE CLOSES: adv-cache-3 COMPLETE (bc2d01d5, 0.23 slot-hours; every row BOUND or PASS, every plant fired; the exhaustive w = 2 image census at all 64 depths equal to the random-function recursion to 2 x 10^-5; the flip-table ladder at 2^18 lines no single-bit bias from two double rounds up). adv-accept-3 (aa359962): a correctness FINDING for the rule's owners, no chain consequence: the deterministic last-resort program (after 256 failed attempts) FAILS the real rule in 223 of 2,500 seeds (209 by part (a), a cyclic stale load) yet is handed to the chain unchecked, unreachable at 4.6e-44 per epoch; ruled to class v5's generator as the commit after the freeze (the last resort passing the rule by construction, known-failed first on one of the 223 seeds; sub-version 3's stated as unreachable and unverified, class v5's as verified); also the 256-unit stand-in ratio is noise as a selector (the three lowest of 4,975 clean live at 1.0002x worst), the selector working only at the 2^20-unit read. Lanes complete or at a natural end: adv-cache, adv-accept-2, adv-cache-3; adv-mixer on its last solve. The kits lane's box-side body moved to tools/class-v5/kits-on-box.sh by path (v5-kits 4f9d96d2) under the inline-rm rule. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule diff --git a/site/evidence.html b/site/evidence.html index c9282467..a7fb3b72 100644 --- a/site/evidence.html +++ b/site/evidence.html @@ -254,7 +254,7 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v 14Ethereum bytecode runs unchanged, with the documented differences of spec 7.1
Homepage Build card; litepaper Building
tested by the teamas row 13; fixes F-exec-A, F-exec-B (spec 7.5)tools/evm-smoke/smoke.mjs: deploy via viem, increment, hashLoop, eth_estimateGas, eth_getLogs; tools/exec-attacks scenarios 1 and 3; bench-log "execution layer attack fixes"Deployment, calls, reverts, logs and gas estimates behave as viem expects; chain id 4463; the prototype pgas table gives 0.0095 to 0.028 pgas per gas, below the design's band before calibration, 3 October 2026. 4 October 2026: a transaction that would cross the block's proving budget is refused by the mempool and, if forced in, aborted and charged with its nonce advanced (25 of 25 checks; 30 of 30 malformed cases). Apple M5 Max. The Prover precompile, proof records and the shard planner are not in the nodenone yet 15Every block is proven, with the proof landing within about a minute at launch
Homepage stats ("~60 s to a proof"); litepaper Proving; roadmap phase 3 gate
implementedrepo d7e1f89 (GPU proof), e01a3cc, 292e800, eedd136 (proving/igneum-prove: shard cutter, MPT witnesses, shard and aggregator guests); SP1 6.8.1; spec 7.2, 7.6proving/windows-wsl2 (SETUP-PROVER, PROVE-BLOCK) on the RTX 5090; igneum-prove-host --mode block on proving/fixtures/; bench-log "proving v0 on the RTX 5090" and "proving: devnet v4 shards"First GPU proof of an Igneum block, 4 October 2026, RTX 5090 (WSL2, SP1 cuda, mining paused): fixture block-78-increment (2 transactions), core proof 1.4 s (7.3 MB, verify 0.221 s), compressed proof 2.7 s (1.27 MB, verify 0.038 s), post-state and receipts roots identical to the node's; 15.7x and 20.6x faster than a loaded M5 Max CPU. The same day on that CPU (load 38 to 47): a three-shard block proved shard by shard and aggregated by recursion, 19 min (1,139 s) end to end, 245 to 337 s per compressed shard proof, every proof verified. What is not there: no proof is produced, carried or checked on the chain (the devnet prover is a stub that signs claims), the proving pool pays nobody (row 21), the block proven is far below one shard, and the 60-second figure remains a design target; the pass mark is the standard in docs/benchmarks/proving-e2e.md. Second RTX 5090 run, 4 October 2026 evening (job run-20261004-173115): a full shard at the provisional S_p (6.75 M pgas, 60.8 M cycles) executed in 1.63 s, core proof 8.3 s (18.1 MB), compressed proof 10.9 s (1.27 MB, verify 0.040 s); a two-shard block (13.5 M pgas) proved shard by shard (11.7 s and 10.0 s) and aggregated in 2.2 s, 24 s of GPU stages end to end, every proof verified, six tampered witnesses rejected. The two host defects (an abort after the upload, an idle wait that turned out to be an unbuffered 18 MB proof save through the WSL2 file bridge, 24 minutes) are fixed (ledger P20) 5 October 2026, live devnet with real transactions (bench-log "real transactions, the first non-empty shard proven and paid"): block 72704 shard 0, 29 transfers, 5,800 pgas, proven on the RTX 5090 Windows rig in 34 s, verified on the Apple M5 Max in 0.297 s and paid 1.7623 IGN, 53 s after the chain block executed; of about 1,400 blocks in the 20-minute window 36 were proven (the one prover takes the newest shard assigned to it), so "every block" is not yet true; a second content shard (72803, all copies skipped) failed the native-execution veto on the exporter's block structure, fixed with fixtures the same day, the node side pending the 0.3.9 rollout 5 October 2026, evening (bench-log "proving v1"): the aggregated segment record, the chain rule and the unproven rule are implemented behind proving_v1_activation_daa (branch proving-v1, not on the devnet before 0.3.11); on the RTX 5090 a chain of 8 consecutive live blocks proved and aggregated by recursion in 135.6 s with the miner on the card (17 s a block, one proof of 1,272,909 bytes attesting all 8, verified in 0.04 s); the 3-node fast-time harness paid a segment record 1.0 s after submission and refused a late one after its deadline (21 checks); the devnet itself, with one prover, carried proofs for 2.4% of blocks over 30 minutes at a block-to-record latency p50 44 s, p99 52 s. The "within about a minute" holds per proven block; "every block" needs 18 mining 5090s or 6 proving-only cards at empty blocks on the measured rates, and the mandatory rule stays off until the share is onenone yet 16A 12 GB card proves one shard in about 20 s (WITHDRAWN 5 October 2026: a 24 GB card proves a full shard at the adopted size in 4.3 s; 32 GB mines and proves)
Litepaper Proving ("The proving budget"); roadmap gate 2
designedspec 5.1 (Target), 7.6 (S_p provisional, 7,500,000 pgas = B_p / 4)PROVE-SHARD.bat on the RTX 5090 (pending); the end-to-end standard in docs/benchmarks/proving-e2e.md; bench-log "proving: devnet v4 shards"Measured on a 32 GB card, not yet on a 12 GB card. A shard at the provisional S_p is 60.8 M SP1 cycles on the prototype pgas table (9 cycles per pgas, 44 per EVM gas; the modexp entry about 100x its SP1 cost); on an RTX 5090 (4 October 2026 evening, job run-20261004-173115) it executed in 1.63 s and its compressed proof took 10.9 s, verified in 0.040 s, so the 32 GB card is inside the 20 s target with margin. Whether a 12 GB card proves it at all, and in what time, is the next measurement (an RTX 3060 and an RTX 5060 Ti 16 GB are on order). A per-shard time can be met by shrinking the shard, so the project does not use it as a pass mark 5 October 2026, evening (bench-log "proving v1", the S_p curve): measured on the RTX 5090 with SP1 6.8.1's GPU prover, the card to itself, 1-s nvidia-smi samples: an empty shard 13,874 MiB and 2.2 s; a full shard at the ADOPTED v1 budget (30,000 pgas, 4.7 M cycles) 20,434 MiB and 4.3 s; the full prototype shard (6.75 M pgas, 60 M cycles) 28,307 MiB and 10.8 s; beside the miner 15,670 and 30,039 MiB. No environment knob of SP1 moves the 13.9 GB floor and the GPU server has no options of its own, so on this build a 12 GB card proves nothing, a 16 GB card only empty shards, a 24 GB card the adopted full shard alone and beside the miner (22,210 MiB and 13.2 s, measured on the 32 GB card: the 5090's allocation pattern, not yet a run on a 24 GB card) and a 32 GB card the prototype shard beside the miner with 2.5 GB spare. The litepaper line now says so; the 12 GB gate returns when a prover build with a smaller floor is measured on a 12 GB cardnone yet -17The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (k = 1) to 3.9x (k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 12 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state)
the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line
tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 core claimed and never measureddocs/analysis/chip-model-v3.md 5 and 6; docs/analysis/latency-shadow-2026-10-06.md; docs/plans/counter-asic-3-status.md; docs/analysis/attack-pass/f8-uniform.md, f4-weakday.md, docs/analysis/ca3-v4-uniform.md; docs/design/class-v5-stored-state.md; the H100 and market-cap rows of 7 October; docs/plans/cryptanalysis/in-house-pass.md (the internal adversarial pass)the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses tools/attack/f8-uniform and the F4 census; the verifier by igneum-pow bench136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.9x, 2.8x at launch; 1.067x at the ceiling; 12 percent on 12 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, the RTX 5090 Windows rig's RTX 5090, the three-card Windows rig's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026).none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word +17The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (k = 1) to 3.9x (k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state)
the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line
tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 core claimed and never measureddocs/analysis/chip-model-v3.md 5 and 6; docs/analysis/latency-shadow-2026-10-06.md; docs/plans/counter-asic-3-status.md; docs/analysis/attack-pass/f8-uniform.md, f4-weakday.md, docs/analysis/ca3-v4-uniform.md; docs/design/class-v5-stored-state.md; the H100 and market-cap rows of 7 October; docs/plans/cryptanalysis/in-house-pass.md (the internal adversarial pass)the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses tools/attack/f8-uniform and the F4 census; the verifier by igneum-pow bench136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.9x, 2.8x at launch; 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, the RTX 5090 Windows rig's RTX 5090, the three-card Windows rig's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026).none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word 18The chip resistance measurements: the program is latency-bound (random reads), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache
Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page
tested by the teamreadwidth e752fc7 (docs/plans/read-width.md), ca2-era 78c0ee4, ca2-cache 2de19e5 (docs/plans/hot-table.md)The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per loadLatency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026none yet 19The lottery hash is sound as a hash: uniform output, deterministic, no out-of-bounds read, fuzzed; class v3 bit-exact on the three vendors
Litepaper vs RandomX ("Every number above is measured and logged"), the numbers page
tested by the teamca2-mixer 1ab8b21 (tests/mixer.rs, tests/scratch.rs), ca2-era 78c0ee4, ca2-soundness a465881 (docs/analysis/scratch-soundness.md), igneum-pow/tests/packs.rsThe crate suite (53 + 4 + 19 + 7), the Metal fuzz, edge, stats and determinism runs on the v3 construction, the pack vectors and 2^24 fingerprints on Metal, Apple OpenCL, the RTX 5090 and the RX 9070 XT, the 1,024-hash CPU re-check per cardClass v3 (mixer x8 + era): 200-program fuzz 200 of 200 on Metal, every tenth on Apple OpenCL; the pinned v3 packs 3/3 + 3/3 and 96 of 96 lanes on Metal and Apple OpenCL; the six era packs' fingerprints equal on the three vendors (the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) job run-ca2-era-pc1-20261005, 5 October 2026); the v2 exports byte-identical on the v3 crate; the final-class PC rows and the G2 re-check: job run-ca2-era-pc1b-20261005 (pending at the time of writing)none yet 20No premine, no pre-sale, no allocation: every coin is minted by the schedule and every coin goes to the block producer (80%) and the proving pool (20%)
Homepage stats and Economics tiles; litepaper Supply, Economics
implementedrepo 6ac80a3; fork "igneum-node devnet v0"; consensus/core/src/igneum.rs, coinbase.rscargo test -p kaspa-consensus-core igneum (8 pass: subsidy table, ramp, split, cap) and cargo test -p kaspa-consensus coinbase (8 pass); igneum-miner inspect 40; bench-log "igneum-node devnet v0"Coinbases on the devnet: 80/20 exact on 39 of 39 single-payee blocks, the 20% to the igneum-proving-pool-v0 output; the per-second schedule sums to under the 4,000,000,000 cap by less than 100 coins; 3,168,808,781 units per DAA second in years 0 to 2, halving at 63,115,200 DAA s. 3 October 2026, Apple M5 Max. The devnet genesis carries no allocation; the mainnet genesis does not exist yet, so the claim is about the code and the stated rule, not a launch that has happenednone yet diff --git a/site/litepaper.html b/site/litepaper.html index b2d0903a..8a9b13fc 100644 --- a/site/litepaper.html +++ b/site/litepaper.html @@ -445,7 +445,7 @@ body.all .pager{display:none} The same chip at the ladder’s second rung (about 200,000 ops per hash), reached by miner signalabout 2.8xmodelled, 7 October 2026 Any chip under class v5, where the dataset is the chain’s own statea stateless or stale chip is wrong on every item, so the stored-dataset chip and the recompute chip are removed as categories; the verifier pays 0.2 ms more per warpdesigned, 7 October 2026 A chip caching the hottest 0.1 percent of items (about 1 MB of SRAM)bounded at 1.067x at the ceiling, 1.005x on about half the hours and 1.048x on 5 percentmeasured census of 1,024 programs, 7 October 2026; the source rule in the next class - A per-day FPGA that recomputes the dataset with cheap multipliers on a weak dayat most 12 percent more hash rate on 12 days a century, nothing on the other days and nothing for any chipmeasured census of 2^24 days, 7 October 2026; the rule in the next class + A per-day FPGA that recomputes the dataset with cheap multipliers on a weak dayat most 12 percent more multiplier area on an FPGA’s per-day build on 15 days a century, nothing on the other days and nothing for any chipmeasured census of 2^24 days, 7 October 2026; the rule in the next class When a stored-dataset chip pays for itselfat about USD 100 M of market cap in the first two years, not beforemodelled, 7 October 2026 The baseline the work started from: the same chip under class v3, without the shadow (the Ethash class)5x to 9x (5.1x on GDDR7, 9.2x on eight HBM3 stacks; the Ethash chips of this class reached 2.1x to 4.8x)modelled, 6 October 2026; the precedent measured by others, 2020 to 2022; never the launch state