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class v5 design page: the attack-pass lane's AP-F4-1 mixer-draw acceptance rule recorded as a v5 item beside the hot-set bound (NAF sum under 163 redrawn, NAF weight at least 4 per word, at least 4 distinct rotations; 6.1e-4 rejections per day; F4's 2^24-day census as the gate)

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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igneum-labs 2026-10-07 09:00:55 +00:00
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docs/design/class-v5-stored-state.md
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@ -219,7 +219,7 @@ The prototype's rows stand meanwhile (new-pow 5.2): 63.083 against 63.088 MH/s,
Implemented on `class-v5` and `class-v5-node` (this page's time line in section 0 names each commit): the design; `igneum_pow::blake2b`, `igneum_pow::state` (leaves, sample, the leaf XOR in `memhard::derive_items`), `V5_CLASS`, `ProgramClass::V5`, generator 5, the emitters' build kernel with the leaf buffer, the CLI's `--program-class v5 --state <stream>`; the fork's `DayStream`, the day-state capture in the executor, the provider in `kaspa_pow`, `program_class_v5_activation_daa`, the v5 signal rule and tally, the RPC fields, the daemon lines, the miner's fetch; the tests with the known-failed cases first; the pinned v5 packs; the harness.
Owed, named here so nobody looks for them: an acceptance-rule bound on a program's hot-set share (the Counter ASIC lane's item for v5, 09:5x UK, on main's word: the attack-pass lane's F8 found that on a class v4 program the top 0.1 percent of items take 0.52 percent of reads, 4.05x a uniform map, one item 153x the mean, most of it class v4's designed per-site windows of layer 8; the v5 rule rejects a draw whose windows and offsets coincide into a hot set beyond the window model's tail, with the rejection's cost stated in accepted programs per 64 seeds under the 2.0 bounds; the bound's definition and number come from the hash lane's window-model analysis on branch ca3-v4-uniform and the gate is F8's 64-seed census, `tools/attack/f8-uniform` on branch attack-pass phase E, the top 0.1 percent within the bound on every seed, re-gated by the attack-pass lane; nothing of it touches v4, which is on the vote); the exec snapshot wire carrying the day streams (version 2); the GPU worker hosts' leaf buffer (`proto-cuda/nvrtc`, `proto-opencl`, `proto-metal`: the kernel text carries it, the hosts must upload it); the pool protocol's daily fetch (spec 09); the day-state witness in the pruning-proof format (with the class-signal witness); the spec text (01 1.8.5 the leaf line, 1.12 the cut and the reference block, 10 the witness); the 2019-class core row (O-1.14); Devnet 2 across a real day boundary.
Owed, named here so nobody looks for them: an acceptance-rule bound on a program's hot-set share (the Counter ASIC lane's item for v5, 09:5x UK, on main's word: the attack-pass lane's F8 found that on a class v4 program the top 0.1 percent of items take 0.52 percent of reads, 4.05x a uniform map, one item 153x the mean, most of it class v4's designed per-site windows of layer 8; the v5 rule rejects a draw whose windows and offsets coincide into a hot set beyond the window model's tail, with the rejection's cost stated in accepted programs per 64 seeds under the 2.0 bounds; the bound's definition and number come from the hash lane's window-model analysis on branch ca3-v4-uniform and the gate is F8's 64-seed census, `tools/attack/f8-uniform` on branch attack-pass phase E, the top 0.1 percent within the bound on every seed, re-gated by the attack-pass lane; nothing of it touches v4, which is on the vote); beside it, the mixer-draw acceptance rule of the attack-pass lane's AP-F4-1 (`docs/analysis/attack-pass/f4-weakday.md` sections 6.7, 7 and 8 on branch attack-pass, relayed 10:0x UK): the day key's MUL block has a tail of cheap multipliers (low NAF weight), a tail of a sum with no weak class behind it; against the DSP-bound datapath F4 passes (0 of 2^28 days over 1.1x), on the LUT-adder metric 5,476 of 2^24 days are over 1.1x (the worst 1.173x; the worst calendar day in the first 100 years is chain day 29,337 at 1.121x), worth at most 12.1 percent more hash rate that day to a per-day LUT-recompute FPGA and nothing to a stored-dataset FPGA or any chip; the v5 rule for the day's mixer draw: reject a MUL block with NAF sum under 163 (M1 cost under 211) and redraw from the next stream values, NAF weight at least 4 per word, at least 4 distinct ROT amounts, total rejection 6.1e-4 per day, the first calendar redraw at day 22,633 (5.2 years in), no devnet or testnet pack changes; gate: F4's harness (the 2^24-day census under both metrics, the worst day's M1 cost at or above 211 after the rule), re-gated by the attack-pass lane against this branch; it is the mixer-draw side of `memhard.rs` (`MixParams::with_shape`), independent of the leaves, and lands behind the v5 class; the exec snapshot wire carrying the day streams (version 2); the GPU worker hosts' leaf buffer (`proto-cuda/nvrtc`, `proto-opencl`, `proto-metal`: the kernel text carries it, the hosts must upload it); the pool protocol's daily fetch (spec 09); the day-state witness in the pruning-proof format (with the class-signal witness); the spec text (01 1.8.5 the leaf line, 1.12 the cut and the reference block, 10 the witness); the 2019-class core row (O-1.14); Devnet 2 across a real day boundary.
## 12. The litepaper paragraph and the ledger row