From 9cfa33489469ba822c3443df7fae7bbb47be42a6 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 21:21:00 +0000 Subject: [PATCH 01/28] Site: the GPU bench table presents the same data the way a buyer reads it (the founder, 7 October 2026): cards you can buy first, sorted by hash rate; datacentre cards collapsed; the Apple row's chip-watt basis marked and unranked under MH per wall watt; one 5090 row with the class v4 knee as its class v4 figure and the efficiency-pass rows in its note; the best desktop card line above the table Co-Authored-By: Claude Fable 5.1 (cherry picked from commit 2336a3c5cb2cb9a652c494ab6f9334319f8752f3) --- site/build.mjs | 31 ++++--- site/miner-bench.json | 182 ++++++++++++++++++------------------------ site/miners.html | 17 ++-- 3 files changed, 111 insertions(+), 119 deletions(-) diff --git a/site/build.mjs b/site/build.mjs index 61a58d40a..f233a9453 100644 --- a/site/build.mjs +++ b/site/build.mjs @@ -419,8 +419,10 @@ for (const [file, active] of PAGES) { { const bj = JSON.parse(readFileSync(join(here, 'miner-bench.json'), 'utf8')); const isCurrent = (r) => r.generator === 'v2' && r.date >= '2026-10-06'; - const byMhW = (a, b) => ((b.mh_per_w ?? -1) - (a.mh_per_w ?? -1)) || (b.mh_s - a.mh_s) || (a.card < b.card ? -1 : 1); - const cur = bj.rows.filter(isCurrent).sort(byMhW); + const byRate = (a, b) => (b.mh_s - a.mh_s) || (a.card < b.card ? -1 : 1); + const curAll = bj.rows.filter(isCurrent).sort(byRate); + const cur = curAll.filter(r => r.group !== 'datacentre'); + const dcRows = curAll.filter(r => r.group === 'datacentre'); const earlier = bj.rows.filter(r => !isCurrent(r)).sort((a, b) => (a.card < b.card ? -1 : a.card > b.card ? 1 : a.generator < b.generator ? -1 : a.generator > b.generator ? 1 : b.mh_s - a.mh_s)); const rows = bj.rows; const fmt = (n) => Number(n).toLocaleString('en-GB', { maximumFractionDigits: 1 }); @@ -430,16 +432,17 @@ for (const [file, active] of PAGES) { // capture showed eleven columns clipped at five, every row inflated by off-screen wrapped text). The detail row moves // with its data row on a sort. const heads = [ - ['Card', 'card', 'text'], ['MH/s', 'mh_s', 'num'], ['W', 'watts', 'num'], ['MH/W', 'mh_per_w', 'num'], + ['Card', 'card', 'text'], ['MH/s', 'mh_s', 'num'], ['W', 'watts', 'num'], ['MH per wall watt', 'mh_per_w', 'num'], ['v4 cost', 'v4_cost_short', 'text'], ['Tuned', 'tuned_short', 'text'], ['Hive core / mem / PL', 'hive_short', 'text'], ['Date', 'date', 'text'], ['Who', 'by', 'text'], ]; // the short forms are one clause: the first watts or percent figure of the cost ("+16 W", "+145.3 W unlocked"), the // tune state's first words; the full sentences live in the detail row - const shortV4 = (r) => { const v = r.v4_cost || 'not measured'; if (/^not measured/.test(v)) return 'not measured'; const m = v.match(/^([+-]?[\d.,]+\s*(?:W|percent)(?:\s+(?:unlocked|of rate))?)/); return m ? m[1].replace(' of rate', ' rate') : v.split(/[,;(]| for | at /)[0].trim(); }; + const shortV4 = (r) => { if (r.v4_short) return r.v4_short; const v = r.v4_cost || 'not measured'; if (/^not measured/.test(v)) return 'not measured'; const m = v.match(/^([+-]?[\d.,]+\s*(?:W|percent)(?:\s+(?:unlocked|of rate))?)/); return m ? m[1].replace(' of rate', ' rate') : v.split(/[,;(]| for | at /)[0].trim(); }; const shortTuned = (r) => { const v = r.tuned || 'stock, mining'; return v.split(/[:;(]/)[0].replace('full Ember Tune', 'Ember Tune').replace('stock, bench only', 'stock, bench').replace('no lever on Apple silicon', 'no lever').trim(); }; const shortHive = (r) => { const h = r.hive; return (h && h.core_mhz != null) ? fmt(h.core_mhz) + ' / ' + fmt(h.mem_mhz) + ' / ' + fmt(h.pl_w) + ' W' : 'stock'; }; const cells = (r) => [ - [r.card, r.card], [fmt(r.mh_s), r.mh_s], [r.watts == null ? 'not read' : fmt(r.watts), r.watts ?? -1], [r.mh_per_w == null ? 'not measured' : fmt3(r.mh_per_w), r.mh_per_w ?? -1], + [r.card, r.card], [r.mh_s_display || fmt(r.mh_s), r.mh_s], [r.watts_display || (r.watts == null ? 'not read' : fmt(r.watts) + (r.watt_basis === 'chip' ? ' (chip watts, not wall)' : '')), r.watts ?? -1], + [r.mh_per_w == null ? 'not measured' : (r.watt_basis === 'chip' ? '\u25CB ' + fmt3(r.mh_per_w) + ' (chip watts, not ranked)' : fmt3(r.mh_per_w)), r.watt_basis === 'chip' ? -1 : (r.mh_per_w ?? -1)], [shortV4(r), shortV4(r)], [shortTuned(r), shortTuned(r)], [shortHive(r), r.hive && r.hive.core_mhz != null ? 'a ' + r.hive.core_mhz : 'z stock'], [r.date, r.date], [r.by.replace('measured by the ', '').replace('reported by the ', 'reported, '), r.by], ]; const detail = (r) => { @@ -455,7 +458,7 @@ for (const [file, active] of PAGES) { return parts.join(' · '); }; const render = (list, id) => '
' + - heads.map(([h, k, t]) => ``).join('') + + heads.map(([h, k, t]) => ``).join('') + '' + list.map(r => '' + cells(r).map(([c, v]) => ``).join('') + '' + ``).join('') + '
${esc(String(c))}
${detail(r)}
'; const sortScript = ``; - const sortStyle = ''; + const sortStyle = ''; const table = render(cur, 'bench-current'); + const dcTable = render(dcRows, 'bench-datacentre'); + const best = cur.slice().sort(byRate)[0]; + const bestLine = best ? `

Best desktop card: ${esc(best.card.replace(/ \(.*$/, ''))}, ${esc(fmt(best.mh_s))} MH/s, ${esc(fmt3(best.mh_per_w))} MH per wall watt tuned (measured, ${esc(best.date)}).

` : ''; const earlierTable = render(earlier, 'bench-earlier'); // Ember Tune's fleet priors (site/miner-priors.json, tools/tuning.mjs --priors --site): one row per card model, // driver major and program class; a row under the sample floor shows its count and no point @@ -496,10 +502,15 @@ for (const [file, active] of PAGES) { const body = scrubBench([ sortStyle, '

The table

', - '

One row per card on the current class: the class v4 program (the latency-shadow block over the class v3 hash), or a class v3 row re-measured with its class v4 cost on 6 October 2026 or later. Click a column header to sort; the table opens by MH per watt. Integrated GPUs are not listed. The earlier classes sit below, collapsed.

', + bestLine, + '

One row per card on the current class: the class v4 program (the latency-shadow block over the class v3 hash), or a class v3 row re-measured with its class v4 cost on 6 October 2026 or later. Cards you can buy first, sorted by hash rate; click a column header to sort. MH per wall watt uses board or wall power; a row whose watts are the chip\'s (Apple silicon: GPU plus DRAM from IOReport) says so and is not ranked on that column. Integrated GPUs are not listed. Datacentre cards and the earlier classes sit below, collapsed.

', '

Why the rate fell from the first bench to today. The genesis program did 104 dependent random 4-byte loads per hash over a 1 GiB dataset; the hourly program and class v3 do 128, with the mixer between them; class v4 adds about 100,000 integer operations per hash that ride in the memory wait. So the hash is bound by random-read bandwidth by design, and a card\'s MH/s is a relative number: the difficulty follows it, and the same card earns the same share of blocks at 136 MH/s on class v3 as it did at 228 MH/s on the genesis program. What a miner compares is hash per watt, and what the chain cares about is the chip edge, which the shadow work is there to cut.

', table, - `

Rows on the current class: ${cur.length}. Each row names the engineering log entry or the job it came from.

`, + `

Cards you can buy on the current class: ${cur.length}. Each row names the engineering log entry or the job it came from.

`, + '
Datacentre cards (' + dcRows.length + ' rows, rented for the measurement; about three times the rented dollars per hash of a desktop card)', + '

Rented cards measured on the class v4 program by the fleet, stock clocks. They mine; they are not what a home miner buys.

', + dcTable, + '
', '

The Hive flight sheet column. Where a card has a measured tune point, the column gives the core clock lock, the memory clock and the power limit to copy into a HiveOS flight sheet (core / mem / PL); the line under each row carries the label with the date, the class v4 cost in full, the miner and driver, the source and the note. Stock means no tune point has been measured yet. The Hive package mines at these settings through Hive\'s own overclock controls; the desktop app\'s Ember Tune lands on them by itself.

', '
Earlier classes (the genesis program, the hourly program, class v3 before the shadow): ' + earlier.length + ' rows, not comparable with the table above', '

These rows are the bench numbers of 3 and 4 October 2026: the genesis program (104 loads per hash), the hourly program and the first class v3 miner. A higher MH/s here is a different hash, not a faster card.

', @@ -520,7 +531,7 @@ for (const [file, active] of PAGES) { const toc = [{ lvl: 2, t: 'The table', id: 'table' }, { lvl: 2, t: 'How a row gets here', id: 'how' }, { lvl: 2, t: 'Fleet tuning priors', id: 'priors' }]; writeFileSync(join(here, 'miners.html'), page('Igneum GPU bench table', 'Measured Igneum hash rates per GPU: card, generator version, best MH/s, MH per watt where measured, miner version, date and the log entry each number came from.', body, toc, 'Measured hash rates per card on the Igneum lottery hash, with the generator version, the miner version, the date and the log entry behind each number.', - { path: '/miners', heading: 'GPU bench table', eyebrow: `${rows.length} measured rows, ${prows.length} fleet tuning models`, crumb: 'GPU bench table' })); + { path: '/miners', heading: 'GPU bench table', eyebrow: `${cur.length} cards you can buy, ${dcRows.length} datacentre, ${prows.length} fleet tuning models`, crumb: 'GPU bench table' })); built.push('miners.html (' + rows.length + ' rows)'); } diff --git a/site/miner-bench.json b/site/miner-bench.json index cf1f19082..bdceaa56f 100644 --- a/site/miner-bench.json +++ b/site/miner-bench.json @@ -1,5 +1,5 @@ { - "_about": "Rows of the public bench table at /miners (site/build.mjs). One row per card, generator version and miner version: the best measured rate. Later jobs append rows. Fields: card, generator (v1 | v2), mh_s (best measured MH/s), mh_per_w (MH per watt, null when the power was not measured), miner (the miner or package version), date (YYYY-MM-DD), source (the docs/bench-log.md heading, or the job id), by ('measured by the team' | 'reported by the fleet'), note (short, optional), watts (board power at the rate, null when not read), v4_cost (what the class v4 shadow costs this card against the class v3 control: watts and rate, measured; 'not measured' when not), tuned (the card's tune state at the row: 'full Ember Tune: ' | 'clock lock , cap ' | 'stock, bench only' | 'stock, mining'), driver_os (driver and OS where known). No machine names, no addresses, no owner names: the build scrubs the page and fails on any that survive. hive (the copy-in HiveOS flight-sheet values at the row's tune point: core MHz (a lock), mem MHz, pl W; each labelled measured with the date, or 'stock' where no tune point exists).", + "_about": "Rows of the public bench table at /miners (site/build.mjs). One row per card, generator version and miner version: the best measured rate. Later jobs append rows. Fields: card, generator (v1 | v2), mh_s (best measured MH/s), mh_per_w (MH per watt, null when the power was not measured), miner (the miner or package version), date (YYYY-MM-DD), source (the docs/bench-log.md heading, or the job id), by ('measured by the team' | 'reported by the fleet'), note (short, optional), watts (board power at the rate, null when not read), v4_cost (what the class v4 shadow costs this card against the class v3 control: watts and rate, measured; 'not measured' when not), tuned (the card's tune state at the row: 'full Ember Tune: ' | 'clock lock , cap ' | 'stock, bench only' | 'stock, mining'), driver_os (driver and OS where known). No machine names, no addresses, no owner names: the build scrubs the page and fails on any that survive. hive (the copy-in HiveOS flight-sheet values at the row's tune point: core MHz (a lock), mem MHz, pl W; each labelled measured with the date, or 'stock' where no tune point exists). group ('buy' | 'datacentre'); watt_basis ('chip' when the watts are the chip's, not the wall's); v4_short (the one-clause class v4 figure for the column).", "rows": [ { "card": "NVIDIA RTX 5090 (32 GB)", @@ -20,7 +20,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 5090 (32 GB)", @@ -41,7 +42,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 5090 (32 GB)", @@ -62,7 +64,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "Apple M5 Max (40 GPU cores, Metal)", @@ -83,7 +86,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "Apple M5 Max (40 GPU cores, Metal)", @@ -104,7 +108,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "Apple silicon laptop (model not reported)", @@ -125,7 +130,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 5060 Ti (16 GB)", @@ -146,41 +152,21 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 5090 (32 GB)", "generator": "v2", "mh_s": 136.1, - "watts": 350, - "mh_per_w": 0.389, - "miner": "igneum-worker-cuda bench, class v3 program (mx8-devnet-epoch0)", - "date": "2026-10-06", - "source": "bench log: 6 October 2026, Counter ASIC 3.0 item 8, the 5090 rows (the control row)", - "by": "measured by the team", - "note": "the control, unlocked; the 6 October +80 W reading was at the app's tuned cap; the rate is memory-bound from 2,850 to 1,400 MHz (136.8 to 135.0 MH/s), the best MH per watt at the lowest lock on the grid, so the knee is below 1,400 MHz (the second pass runs to the driver's floor)", - "v4_cost": "+145.3 W at the unlocked core (475.5 against 330.2 W) for +0.18 percent of rate; +88.3 W at the 1,400 MHz lock (316.3 against 228.0 W) for +0.23 percent; measured 7 October 2026 (the class v4 efficiency pass on the team's Windows desk machine, 60 s steps, every fingerprint matched)", - "tuned": "stock, bench only (unlocked core)", - "driver_os": "NVIDIA driver, Windows 11", - "hive": { - "core_mhz": null, - "mem_mhz": null, - "pl_w": null, - "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } - }, - { - "card": "NVIDIA RTX 5090 (32 GB)", - "generator": "v2", - "mh_s": 127.71, "watts": 226.8, "mh_per_w": 0.563, "miner": "Igneum Miner 0.3.13 + Ember Tune kit 6 (mining, class v3 program)", "date": "2026-10-06", - "source": "bench log: 6 October 2026, 16:01Z, Ember run 6 (ember-tune-pc1-6)", + "source": "bench log: 6 October 2026, Ember run 6; Counter ASIC 3.0 status: item 8's 5090 rows and the class v4 efficiency pass (7 October 2026)", "by": "measured by the team", - "note": "against 127.9 MH/s at 311.0 W untuned (0.411 MH/W): 84 W saved for 0.15 percent of rate; the ladder's floor, not yet its optimum", - "v4_cost": "not measured at this tune point (the Ember run was on the class v3 program); the unlocked and locked rows above carry the measured premium", + "note": "one row for the card: best rate 136.1 MH/s at 350 W stock unlocked on the class v3 control (bench, 6 October 2026); best MH per wall watt 127.71 MH/s at 226.8 W at the full Ember Tune point, 1,854 MHz (Ember run 6, 6 October 2026); the class v4 efficiency pass (7 October 2026, 60 s steps, every fingerprint matched): unlocked 136.84 MH/s at 475.5 W (0.288), the 1,400 MHz lock 134.98 at 316.3 W (0.427), the knee 1,300 MHz, the best point 1,200 MHz 133.80 at 305.1 W (0.439); the fleet's standing 5090 reads 100.6 MH/s at 308 W beside its prover (reported by the fleet)", + "v4_cost": "class v4 at the 1,200 MHz knee: 133.80 MH/s at 305.1 W (0.439 MH/W); the premium over class v3 81.8 W at the best points and 145.3 W unlocked, measured 7 October 2026", "tuned": "full Ember Tune: 1,854 MHz core lock at the 100 percent cap", "driver_os": "NVIDIA driver, Windows 11", "hive": { @@ -188,7 +174,11 @@ "mem_mhz": 13801, "pl_w": 460, "label": "measured 6 October 2026 (Ember run 6: the clock lock 1,854 MHz, the memory clock as read, the limit 460 W of 575 as the cap did not bind)" - } + }, + "v4_short": "133.8 MH/s, 305 W, 0.439", + "group": "buy", + "mh_s_display": "136.1 stock (127.7 tuned)", + "watts_display": "226.8 tuned (350 stock)" }, { "card": "NVIDIA RTX 4070 (12 GB)", @@ -209,7 +199,8 @@ "mem_mhz": 10251, "pl_w": 100, "label": "measured 6 October 2026 (Ember run 6: 1,863 MHz at the 50 percent cap of 200 W, 75.6 W drawn; the item 8 rows at 1,860 MHz and 160 W)" - } + }, + "group": "buy" }, { "card": "AMD Radeon RX 9070 XT (16 GB)", @@ -230,7 +221,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "Apple M5 Max (40 GPU cores, Metal)", @@ -242,7 +234,7 @@ "date": "2026-10-06", "source": "Counter ASIC 3.0 status: item 8, the Mac rows (IOReport GPU and DRAM watts)", "by": "measured by the team", - "note": "GPU plus DRAM watts, not wall", + "note": "GPU plus DRAM watts from IOReport, not wall power, so its MH per watt is not ranked against the cards' wall figures", "v4_cost": "+16 W for 1.5 percent of rate at 102,100 ops per hash, measured 6 October 2026", "tuned": "no lever on Apple silicon (no clock or power control exposed); stock", "driver_os": "macOS, Metal", @@ -251,7 +243,9 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "watt_basis": "chip", + "group": "buy" }, { "card": "Intel Arc B580 (12 GB)", @@ -272,7 +266,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA H100 SXM (80 GB)", @@ -293,7 +288,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "datacentre" }, { "card": "NVIDIA RTX 5080 (16 GB)", @@ -314,7 +310,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3070 Ti (8 GB)", @@ -335,7 +332,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3070 (8 GB)", @@ -356,7 +354,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3080 (10 GB)", @@ -377,7 +376,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3080 Ti (12 GB)", @@ -398,7 +398,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3090 (24 GB)", @@ -419,7 +420,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3090 Ti (24 GB)", @@ -440,7 +442,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 4090 (24 GB)", @@ -461,28 +464,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } - }, - { - "card": "NVIDIA RTX 5090 (32 GB), fleet", - "generator": "v2", - "mh_s": 100.6, - "watts": 308, - "mh_per_w": 0.327, - "miner": "hive package 0.3.20 igneum-miner, class v4 program", - "date": "2026-10-07", - "source": "the fleet's standing voter (status line, 7 October 2026)", - "by": "reported by the fleet", - "note": "a standing voter's status beside its prover, 18:00Z; 122 MH/s at 308 W earlier in the day (0.396 MH/W); the team's own 5090 rows above", - "v4_cost": "not measured (class v4 program only)", - "tuned": "stock, mining", - "driver_os": "NVIDIA driver, Ubuntu 24.04", - "hive": { - "core_mhz": null, - "mem_mhz": null, - "pl_w": null, - "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3060 (12 GB)", @@ -503,7 +486,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 3060 Ti (8 GB)", @@ -524,7 +508,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 4060 Ti (8 GB)", @@ -545,7 +530,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 4070 Ti (12 GB)", @@ -566,7 +552,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 5060 (8 GB)", @@ -587,7 +574,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 5070 (12 GB)", @@ -608,7 +596,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX 5070 Ti (16 GB)", @@ -629,7 +618,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "buy" }, { "card": "NVIDIA RTX A5000 (24 GB)", @@ -650,7 +640,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "datacentre" }, { "card": "NVIDIA L40S (48 GB)", @@ -671,7 +662,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "datacentre" }, { "card": "NVIDIA A100 PCIe (80 GB)", @@ -692,7 +684,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "datacentre" }, { "card": "NVIDIA A100 SXM (80 GB)", @@ -713,7 +706,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "datacentre" }, { "card": "NVIDIA H200 SXM (141 GB)", @@ -734,7 +728,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "datacentre" }, { "card": "NVIDIA B200 (180 GB)", @@ -755,7 +750,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } + }, + "group": "datacentre" }, { "card": "NVIDIA RTX PRO 6000 Blackwell (96 GB)", @@ -776,28 +772,8 @@ "mem_mhz": null, "pl_w": null, "label": "stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read)" - } - }, - { - "card": "NVIDIA RTX 5090 (32 GB)", - "generator": "v2", - "mh_s": 134.98, - "watts": 316.3, - "mh_per_w": 0.427, - "miner": "igneum-worker-cuda bench (installed worker 0.3.20), class v4 program v4-devnet-epoch0", - "date": "2026-10-07", - "source": "Counter ASIC 3.0 status: the class v4 efficiency pass (the efficiency pass job of 7 October 2026, 18:40 to 19:16 UTC, on the team's Windows desk machine, the core locked through the installed app's Power Helper task, no prompt)", - "by": "measured by the team", - "note": "the v3 control at the same lock 134.68 MH/s at 228.0 W (0.591 MH/W); recovered 159.2 W for 1.36 percent of rate against the unlocked class v4 point; the best MH per watt on the grid, so the knee is below 1,400 MHz", - "v4_cost": "+88.3 W at this lock for +0.23 percent of rate, measured 7 October 2026", - "tuned": "core lock 1,400 MHz (the efficiency pass's grid floor), memory 13,801 MHz, the driver's power limit untouched", - "driver_os": "NVIDIA driver 617.14, Windows 11", - "hive": { - "core_mhz": 1400, - "mem_mhz": 13801, - "pl_w": 575, - "label": "measured 7 October 2026 (the class v4 efficiency pass: the 1,400 MHz lock, the memory clock as read, the limit as the driver's default since the lock alone set the draw; the knee below 1,400 is the second pass's)" - } + }, + "group": "datacentre" } ] } diff --git a/site/miners.html b/site/miners.html index 92211c401..d13047073 100644 --- a/site/miners.html +++ b/site/miners.html @@ -213,7 +213,7 @@ table{min-width:560px}
Igneum/GPU bench table
-
38 measured rows, 0 fleet tuning models
+
21 cards you can buy, 8 datacentre, 0 fleet tuning models

GPU bench table

Measured hash rates per card on the Igneum lottery hash, with the generator version, the miner version, the date and the log entry behind each number.

@@ -222,17 +222,22 @@ table{min-width:560px}
-
+

The table

-

One row per card on the current class: the class v4 program (the latency-shadow block over the class v3 hash), or a class v3 row re-measured with its class v4 cost on 6 October 2026 or later. Click a column header to sort; the table opens by MH per watt. Integrated GPUs are not listed. The earlier classes sit below, collapsed.

+

Best desktop card: NVIDIA RTX 5090, 136.1 MH/s, 0.563 MH per wall watt tuned (measured, 2026-10-06).

+

One row per card on the current class: the class v4 program (the latency-shadow block over the class v3 hash), or a class v3 row re-measured with its class v4 cost on 6 October 2026 or later. Cards you can buy first, sorted by hash rate; click a column header to sort. MH per wall watt uses board or wall power; a row whose watts are the chip's (Apple silicon: GPU plus DRAM from IOReport) says so and is not ranked on that column. Integrated GPUs are not listed. Datacentre cards and the earlier classes sit below, collapsed.

Why the rate fell from the first bench to today. The genesis program did 104 dependent random 4-byte loads per hash over a 1 GiB dataset; the hourly program and class v3 do 128, with the mixer between them; class v4 adds about 100,000 integer operations per hash that ride in the memory wait. So the hash is bound by random-read bandwidth by design, and a card's MH/s is a relative number: the difficulty follows it, and the same card earns the same share of blocks at 136 MH/s on class v3 as it did at 228 MH/s on the genesis program. What a miner compares is hash per watt, and what the chain cares about is the chip edge, which the shadow work is there to cut.

-
Apple M5 Max (40 GPU cores, Metal)		27211.29+16 Wno leverstock2026-10-06team
Generator: v2 · Class v4 cost: +16 W for 1.5 percent of rate at 102,100 ops per hash, measured 6 October 2026 · Tuned: no lever on Apple silicon (no clock or power control exposed); stock · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-miner Metal worker, class v3 program (macOS, Metal) · Source: Counter ASIC 3.0 status: item 8, the Apple M5 Max rows (IOReport GPU and DRAM watts) · Note: GPU plus DRAM watts, not wall
NVIDIA H200 SXM (141 GB)		313432.90.723not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA H100 SXM (80 GB)		248.7385.60.645not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-worker-cuda bench (Linux), class v3 control (NVIDIA driver 580.126.09, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep, a rented card) · Note: 424.0 W maximum; 98 percent of its random-read ceiling like the 5090; 1.78x the 5090's hash at 1.15x the tuned 5090's hash per watt and a third of the hash per rented dollar
NVIDIA RTX 5090 (32 GB)		127.7226.80.563not measuredEmber Tune1,854 / 13,801 / 460 W2026-10-06team
Generator: v2 · Class v4 cost: not measured at this tune point (the Ember run was on the class v3 program); the unlocked and locked rows above carry the measured premium · Tuned: full Ember Tune: 1,854 MHz core lock at the 100 percent cap · Hive flight sheet: core lock 1,854 MHz, mem 13,801 MHz, PL 460 W (measured 6 October 2026 (Ember run 6: the clock lock 1,854 MHz, the memory clock as read, the limit 460 W of 575 as the cap did not bind)) · Miner: Igneum Miner 0.3.13 + Ember Tune kit 6 (mining, class v3 program) (NVIDIA driver, Windows 11) · Source: bench log: 6 October 2026, 16:01Z, Ember run 6 (ember-tune-pc1-6) · Note: against 127.9 MH/s at 311.0 W untuned (0.411 MH/W): 84 W saved for 0.15 percent of rate; the ladder's floor, not yet its optimum
NVIDIA RTX 5070 Ti (16 GB)		78.4145.60.539not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA A100 SXM (80 GB)		138.4266.30.52not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA A100 PCIe (80 GB)		155299.60.517not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 5070 (12 GB)		52102.80.506not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 5080 (16 GB)		71.2143.40.496not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.65.06, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04) · Note: 148.6 W maximum; the team's own 5080 on a dock reads 60 MH/s warming and gets its full Ember Tune on 7 October
NVIDIA B200 (180 GB)		416.4855.60.487not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX PRO 6000 Blackwell (96 GB)		130.5288.70.452not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 5090 (32 GB)		135316.30.427+88.3 Wcore lock 1,400 MHz1,400 / 13,801 / 575 W2026-10-07team
Generator: v2 · Class v4 cost: +88.3 W at this lock for +0.23 percent of rate, measured 7 October 2026 · Tuned: core lock 1,400 MHz (the efficiency pass's grid floor), memory 13,801 MHz, the driver's power limit untouched · Hive flight sheet: core lock 1,400 MHz, mem 13,801 MHz, PL 575 W (measured 7 October 2026 (the class v4 efficiency pass: the 1,400 MHz lock, the memory clock as read, the limit as the driver's default since the lock alone set the draw; the knee below 1,400 is the second pass's)) · Miner: igneum-worker-cuda bench (installed worker 0.3.20), class v4 program v4-devnet-epoch0 (NVIDIA driver 617.14, Windows 11) · Source: Counter ASIC 3.0 status: the class v4 efficiency pass (the efficiency pass job of 7 October 2026, 18:40 to 19:16 UTC, on the team's Windows desk machine, the core locked through the installed app's Power Helper task, no prompt) · Note: the v3 control at the same lock 134.68 MH/s at 228.0 W (0.591 MH/W); recovered 159.2 W for 1.36 percent of rate against the unlocked class v4 point; the best MH per watt on the grid, so the knee is below 1,400 MHz
NVIDIA RTX 5060 (8 GB)		31.375.40.415not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 5090 (32 GB)		136.13500.389+145.3 Wstock, benchstock2026-10-06team
Generator: v2 · Class v4 cost: +145.3 W at the unlocked core (475.5 against 330.2 W) for +0.18 percent of rate; +88.3 W at the 1,400 MHz lock (316.3 against 228.0 W) for +0.23 percent; measured 7 October 2026 (the class v4 efficiency pass on the team's Windows desk machine, 60 s steps, every fingerprint matched) · Tuned: stock, bench only (unlocked core) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-worker-cuda bench, class v3 program (mx8-devnet-epoch0) (NVIDIA driver, Windows 11) · Source: bench log: 6 October 2026, Counter ASIC 3.0 item 8, the 5090 rows (the control row) · Note: the control, unlocked; the 6 October +80 W reading was at the app's tuned cap; the rate is memory-bound from 2,850 to 1,400 MHz (136.8 to 135.0 MH/s), the best MH per watt at the lowest lock on the grid, so the knee is below 1,400 MHz (the second pass runs to the driver's floor)
NVIDIA RTX 4070 (12 GB)		3179.50.389+30 WEmber Tune1,863 / 10,251 / 100 W2026-10-06team
Generator: v2 · Class v4 cost: +30 W (79 to 109 W) for +0.4 percent of rate at 102,100 ops per hash, measured 6 October 2026 · Tuned: full Ember Tune: 1,860 MHz core lock, 160 W cap (Ember run 6: 1,863 MHz at the 50 percent cap, 75.6 W) · Hive flight sheet: core lock 1,863 MHz, mem 10,251 MHz, PL 100 W (measured 6 October 2026 (Ember run 6: 1,863 MHz at the 50 percent cap of 200 W, 75.6 W drawn; the item 8 rows at 1,860 MHz and 160 W)) · Miner: igneum-worker-cuda bench (installed worker), class v3 control (NVIDIA driver, Windows 11) · Source: Counter ASIC 3.0 status: item 8, the RTX 4070 rows (job run-ca3-pc1-4070-shadow-20261006) · Note: 79.3 to 79.8 W at the tune point; 28.78 MH/s at 75.6 W (0.381) in Ember run 6 mining
NVIDIA RTX 5090 (32 GB), fleet		100.63080.327not measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's standing voter (status line, 7 October 2026) · Note: a standing voter's status beside its prover, 18:00Z; 122 MH/s at 308 W earlier in the day (0.396 MH/W); the team's own 5090 rows above
NVIDIA RTX 4070 Ti (12 GB)		31.3107.30.291not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 4090 (24 GB)		52.3183.10.285not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, the RTX 4090 hands row · Note: the hands row: the card mines and proves (17.4 GB peak while proving); the standing 4090 voters read 44.5 to 50.8 MH/s this hour beside their provers
NVIDIA RTX 5060 Ti (16 GB)		30.9114.80.2690.1 percent ratestock, benchstock2026-10-07team
Generator: v2 · Class v4 cost: 0.1 percent of rate, measured 7 October 2026 · Tuned: stock, bench only (180 W default cap, never tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: Igneum Miner 0.3.19 package, prebuilt NVRTC worker (bench mode, class v4 program) (NVIDIA driver, Windows 11) · Source: bench log: 7 October 2026, the first 16 GB card: an RTX 5060 Ti in a Thunderbolt enclosure (run b) · Note: class v4 program, 128 loads per hash, 1 GiB dataset, 10-minute window on the card alone at the stock 180 W limit: 114.8 W mean; PCIe 4.0 x4 through the enclosure
NVIDIA RTX 4060 Ti (8 GB)		20.177.50.259not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 3060 Ti (8 GB)		33.1129.50.256not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 3090 Ti (24 GB)		62249.50.248not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.65.06, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 3060 (12 GB)		26.9111.60.241not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.126.09, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04) · Note: 114.5 W maximum; the Devnet 3 boxes read 23.7 to 25.7 MH/s beside their nodes
NVIDIA L40S (48 GB)		56.4240.70.234not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 3080 Ti (12 GB)		59267.30.221not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.65.06, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04) · Note: 283.0 W maximum
NVIDIA RTX 3070 Ti (8 GB)		39178.30.219not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 595.71.05, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
AMD Radeon RX 9070 XT (16 GB)		18.91990.095+2 percent ratestock, benchstock2026-10-06team
Generator: v2 · Class v4 cost: +2 percent of rate (19.29 against 18.92 MH/s) at 102,100 ops per hash, watts owed, measured 6 October 2026 · Tuned: stock, bench only (the AMD tune pass runs 7 October: set only if the ADLX tune line reads, else measure-only) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-worker-opencl bench (installed worker), class v3 control (Adrenalin 26.9.2, Windows 11) · Source: Counter ASIC 3.0 status: item 8, the RX 9070 XT rows (job run-ca3-pc1-amd-g1-shadow-20261006); watts from the app's telemetry read of 5 October 2026 (the job's ADLX sample parsed 0 rows) · Note: the card sits at 87 to 95 percent of its dependent random-read ceiling (2.42 to 2.68 G loads/s), in a Thunderbolt enclosure; AMD OpenCL 3683.0
NVIDIA RTX 3090 (24 GB)		50not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's standing voters (status lines, 7 October 2026) · Note: the best of four standing voters this hour (42.2 to 50.0 MH/s) beside their provers; watts not read
NVIDIA RTX A5000 (24 GB)		47.6not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's standing voter (status line, 7 October 2026) · Note: a standing voter's status line, 18:00Z; watts not read
NVIDIA RTX 3080 (10 GB)		43.7not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's standing voter (status line, 7 October 2026) and the sweep's hands row · Note: a standing voter's status line, 18:00Z; the hands row of the sweep reads 40.82 MH/s at 204.9 W; 10 GB, no prover
NVIDIA RTX 3070 (8 GB)		33.7not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's 0.3.21 wipe canary (status line, 7 October 2026) · Note: the 0.3.21 wipe canary's status line, 17:07Z, beside its node; watts not read
Intel Arc B580 (12 GB)		11not readnot measured0.1 percent ratestock, benchstock2026-10-07team
Generator: v2 · Class v4 cost: 0.1 percent of rate, measured 7 October 2026 · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-worker-opencl bench, class v4 program (Intel driver, Windows 11) · Source: bench log: 7 October 2026, the Intel Arc B580 (eGPU equals slot) · Note: the same rate in the Thunderbolt enclosure and the slot; watts not read on this run
-

Rows on the current class: 32. Each row names the engineering log entry or the job it came from.

+
NVIDIA RTX 5090 (32 GB)		136.1 stock (127.7 tuned)226.8 tuned (350 stock)0.563133.8 MH/s, 305 W, 0.439Ember Tune1,854 / 13,801 / 460 W2026-10-06team
Generator: v2 · Class v4 cost: class v4 at the 1,200 MHz knee: 133.80 MH/s at 305.1 W (0.439 MH/W); the premium over class v3 81.8 W at the best points and 145.3 W unlocked, measured 7 October 2026 · Tuned: full Ember Tune: 1,854 MHz core lock at the 100 percent cap · Hive flight sheet: core lock 1,854 MHz, mem 13,801 MHz, PL 460 W (measured 6 October 2026 (Ember run 6: the clock lock 1,854 MHz, the memory clock as read, the limit 460 W of 575 as the cap did not bind)) · Miner: Igneum Miner 0.3.13 + Ember Tune kit 6 (mining, class v3 program) (NVIDIA driver, Windows 11) · Source: bench log: 6 October 2026, Ember run 6; Counter ASIC 3.0 status: item 8's 5090 rows and the class v4 efficiency pass (7 October 2026) · Note: one row for the card: best rate 136.1 MH/s at 350 W stock unlocked on the class v3 control (bench, 6 October 2026); best MH per wall watt 127.71 MH/s at 226.8 W at the full Ember Tune point, 1,854 MHz (Ember run 6, 6 October 2026); the class v4 efficiency pass (7 October 2026, 60 s steps, every fingerprint matched): unlocked 136.84 MH/s at 475.5 W (0.288), the 1,400 MHz lock 134.98 at 316.3 W (0.427), the knee 1,300 MHz, the best point 1,200 MHz 133.80 at 305.1 W (0.439); the fleet's standing 5090 reads 100.6 MH/s at 308 W beside its prover (reported by the fleet)
NVIDIA RTX 5070 Ti (16 GB)		78.4145.60.539not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 5080 (16 GB)		71.2143.40.496not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.65.06, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04) · Note: 148.6 W maximum; the team's own 5080 on a dock reads 60 MH/s warming and gets its full Ember Tune on 7 October
NVIDIA RTX 3090 Ti (24 GB)		62249.50.248not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.65.06, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 3080 Ti (12 GB)		59267.30.221not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.65.06, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04) · Note: 283.0 W maximum
NVIDIA RTX 4090 (24 GB)		52.3183.10.285not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, the RTX 4090 hands row · Note: the hands row: the card mines and proves (17.4 GB peak while proving); the standing 4090 voters read 44.5 to 50.8 MH/s this hour beside their provers
NVIDIA RTX 5070 (12 GB)		52102.80.506not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 3090 (24 GB)		50not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's standing voters (status lines, 7 October 2026) · Note: the best of four standing voters this hour (42.2 to 50.0 MH/s) beside their provers; watts not read
NVIDIA RTX 3080 (10 GB)		43.7not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's standing voter (status line, 7 October 2026) and the sweep's hands row · Note: a standing voter's status line, 18:00Z; the hands row of the sweep reads 40.82 MH/s at 204.9 W; 10 GB, no prover
NVIDIA RTX 3070 Ti (8 GB)		39178.30.219not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 595.71.05, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 3070 (8 GB)		33.7not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's 0.3.21 wipe canary (status line, 7 October 2026) · Note: the 0.3.21 wipe canary's status line, 17:07Z, beside its node; watts not read
NVIDIA RTX 3060 Ti (8 GB)		33.1129.50.256not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 5060 (8 GB)		31.375.40.415not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 4070 Ti (12 GB)		31.3107.30.291not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX 4070 (12 GB)		3179.50.389+30 WEmber Tune1,863 / 10,251 / 100 W2026-10-06team
Generator: v2 · Class v4 cost: +30 W (79 to 109 W) for +0.4 percent of rate at 102,100 ops per hash, measured 6 October 2026 · Tuned: full Ember Tune: 1,860 MHz core lock, 160 W cap (Ember run 6: 1,863 MHz at the 50 percent cap, 75.6 W) · Hive flight sheet: core lock 1,863 MHz, mem 10,251 MHz, PL 100 W (measured 6 October 2026 (Ember run 6: 1,863 MHz at the 50 percent cap of 200 W, 75.6 W drawn; the item 8 rows at 1,860 MHz and 160 W)) · Miner: igneum-worker-cuda bench (installed worker), class v3 control (NVIDIA driver, Windows 11) · Source: Counter ASIC 3.0 status: item 8, the RTX 4070 rows (job run-ca3-pc1-4070-shadow-20261006) · Note: 79.3 to 79.8 W at the tune point; 28.78 MH/s at 75.6 W (0.381) in Ember run 6 mining
NVIDIA RTX 5060 Ti (16 GB)		30.9114.80.2690.1 percent ratestock, benchstock2026-10-07team
Generator: v2 · Class v4 cost: 0.1 percent of rate, measured 7 October 2026 · Tuned: stock, bench only (180 W default cap, never tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: Igneum Miner 0.3.19 package, prebuilt NVRTC worker (bench mode, class v4 program) (NVIDIA driver, Windows 11) · Source: bench log: 7 October 2026, the first 16 GB card: an RTX 5060 Ti in a Thunderbolt enclosure (run b) · Note: class v4 program, 128 loads per hash, 1 GiB dataset, 10-minute window on the card alone at the stock 180 W limit: 114.8 W mean; PCIe 4.0 x4 through the enclosure
Apple M5 Max (40 GPU cores, Metal)		2721 (chip watts, not wall)○ 1.29 (chip watts, not ranked)+16 Wno leverstock2026-10-06team
Generator: v2 · Class v4 cost: +16 W for 1.5 percent of rate at 102,100 ops per hash, measured 6 October 2026 · Tuned: no lever on Apple silicon (no clock or power control exposed); stock · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-miner Metal worker, class v3 program (macOS, Metal) · Source: Counter ASIC 3.0 status: item 8, the Apple M5 Max rows (IOReport GPU and DRAM watts) · Note: GPU plus DRAM watts from IOReport, not wall power, so its MH per watt is not ranked against the cards' wall figures
NVIDIA RTX 3060 (12 GB)		26.9111.60.241not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580.126.09, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04) · Note: 114.5 W maximum; the Devnet 3 boxes read 23.7 to 25.7 MH/s beside their nodes
NVIDIA RTX 4060 Ti (8 GB)		20.177.50.259not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
AMD Radeon RX 9070 XT (16 GB)		18.91990.095+2 percent ratestock, benchstock2026-10-06team
Generator: v2 · Class v4 cost: +2 percent of rate (19.29 against 18.92 MH/s) at 102,100 ops per hash, watts owed, measured 6 October 2026 · Tuned: stock, bench only (the AMD tune pass runs 7 October: set only if the ADLX tune line reads, else measure-only) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-worker-opencl bench (installed worker), class v3 control (Adrenalin 26.9.2, Windows 11) · Source: Counter ASIC 3.0 status: item 8, the RX 9070 XT rows (job run-ca3-pc1-amd-g1-shadow-20261006); watts from the app's telemetry read of 5 October 2026 (the job's ADLX sample parsed 0 rows) · Note: the card sits at 87 to 95 percent of its dependent random-read ceiling (2.42 to 2.68 G loads/s), in a Thunderbolt enclosure; AMD OpenCL 3683.0
Intel Arc B580 (12 GB)		11not readnot measured0.1 percent ratestock, benchstock2026-10-07team
Generator: v2 · Class v4 cost: 0.1 percent of rate, measured 7 October 2026 · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-worker-opencl bench, class v4 program (Intel driver, Windows 11) · Source: bench log: 7 October 2026, the Intel Arc B580 (eGPU equals slot) · Note: the same rate in the Thunderbolt enclosure and the slot; watts not read on this run
+

Cards you can buy on the current class: 21. Each row names the engineering log entry or the job it came from.

+
Datacentre cards (8 rows, rented for the measurement; about three times the rented dollars per hash of a desktop card) +

Rented cards measured on the class v4 program by the fleet, stock clocks. They mine; they are not what a home miner buys.

+
NVIDIA B200 (180 GB)		416.4855.60.487not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA H200 SXM (141 GB)		313432.90.723not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA H100 SXM (80 GB)		248.7385.60.645not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-worker-cuda bench (Linux), class v3 control (NVIDIA driver 580.126.09, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep, a rented card) · Note: 424.0 W maximum; 98 percent of its random-read ceiling like the 5090; 1.78x the 5090's hash at 1.15x the tuned 5090's hash per watt and a third of the hash per rented dollar
NVIDIA A100 PCIe (80 GB)		155299.60.517not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA A100 SXM (80 GB)		138.4266.30.52not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX PRO 6000 Blackwell (96 GB)		130.5288.70.452not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA L40S (48 GB)		56.4240.70.234not measuredstock, benchstock2026-10-07fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, bench only (rented, not tuned) · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-worker-cuda, class v4 program (NVIDIA driver 580, Ubuntu 24.04) · Source: bench log: 7 October 2026, every rentable card on the hash (the fleet's sweep on rented cards; hive package 0.3.20, Ubuntu 24.04)
NVIDIA RTX A5000 (24 GB)		47.6not readnot measurednot measuredstock, miningstock2026-10-07reported, fleet
Generator: v2 · Class v4 cost: not measured (class v4 program only) · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: hive package 0.3.20 igneum-miner, class v4 program (NVIDIA driver, Ubuntu 24.04) · Source: the fleet's standing voter (status line, 7 October 2026) · Note: a standing voter's status line, 18:00Z; watts not read
+

The Hive flight sheet column. Where a card has a measured tune point, the column gives the core clock lock, the memory clock and the power limit to copy into a HiveOS flight sheet (core / mem / PL); the line under each row carries the label with the date, the class v4 cost in full, the miner and driver, the source and the note. Stock means no tune point has been measured yet. The Hive package mines at these settings through Hive's own overclock controls; the desktop app's Ember Tune lands on them by itself.

Earlier classes (the genesis program, the hourly program, class v3 before the shadow): 6 rows, not comparable with the table above

These rows are the bench numbers of 3 and 4 October 2026: the genesis program (104 loads per hash), the hourly program and the first class v3 miner. A higher MH/s here is a different hash, not a faster card.

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Apple M5 Max (40 GPU cores, Metal)		45.2not readnot measurednot measuredstock, benchstock2026-10-03team
Generator: v1 · Class v4 cost: not measured · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: proto-metal bench (prototype, not mining) · Source: bench log: 3 October 2026, RTX 5090 first run (the Apple row of the same table) · Note: genesis program, 1 GiB dataset
Apple M5 Max (40 GPU cores, Metal)		26.7not readnot measurednot measuredstock, miningstock2026-10-04team
Generator: v2 · Class v4 cost: not measured · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-miner devnet v4, Metal worker with prepare · Source: bench log: 4 October 2026, first hourly program swap on the live devnet: compile-ahead, no pause, two cards · Note: live devnet v4, unbroken through the hour boundary
Apple silicon laptop (model not reported)		24.3not readnot measurednot measuredstock, miningstock2026-10-04reported, fleet
Generator: v2 · Class v4 cost: not measured · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: Igneum Miner 0.3.1 (DMG) · Source: bench log: 4 October 2026, first outside machine on the devnet: an Apple silicon laptop through the Igneum Miner app · Note: 21.0 MH/s average over 7 minutes, 24.3 MH/s at the moment of the report, 33 accepted blocks
NVIDIA RTX 5090 (32 GB)		229not readnot measurednot measuredstock, benchstock2026-10-03team
Generator: v1 · Class v4 cost: not measured · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: proto-cuda bench (prototype, not mining) · Source: bench log: 3 October 2026, RTX 5090, memory-hard dataset (pack igneum-genesis-mh) · Note: genesis program, 104 loads per hash, 1 GiB dataset
NVIDIA RTX 5090 (32 GB)		185.3not readnot measurednot measuredstock, benchstock2026-10-03team
Generator: v1 · Class v4 cost: not measured · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: proto-cuda bench (prototype, not mining) · Source: bench log: 3 October 2026, RTX 5090 first run, dataset sweep and second program · Note: hourly program, 128 loads per hash, 1 GiB dataset
NVIDIA RTX 5090 (32 GB)		124.2not readnot measurednot measuredstock, miningstock2026-10-04team
Generator: v2 · Class v4 cost: not measured · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: Igneum Miner 0.3.0 package, prebuilt NVRTC worker · Source: bench log: 4 October 2026, the gfx1036 worker fault and what the Apple M5 Max could and could not reproduce · Note: live devnet v4, 128 loads per hash, CPU re-check clean, 0 rejected
+
Apple M5 Max (40 GPU cores, Metal)		45.2not readnot measurednot measuredstock, benchstock2026-10-03team
Generator: v1 · Class v4 cost: not measured · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: proto-metal bench (prototype, not mining) · Source: bench log: 3 October 2026, RTX 5090 first run (the Apple row of the same table) · Note: genesis program, 1 GiB dataset
Apple M5 Max (40 GPU cores, Metal)		26.7not readnot measurednot measuredstock, miningstock2026-10-04team
Generator: v2 · Class v4 cost: not measured · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: igneum-miner devnet v4, Metal worker with prepare · Source: bench log: 4 October 2026, first hourly program swap on the live devnet: compile-ahead, no pause, two cards · Note: live devnet v4, unbroken through the hour boundary
Apple silicon laptop (model not reported)		24.3not readnot measurednot measuredstock, miningstock2026-10-04reported, fleet
Generator: v2 · Class v4 cost: not measured · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: Igneum Miner 0.3.1 (DMG) · Source: bench log: 4 October 2026, first outside machine on the devnet: an Apple silicon laptop through the Igneum Miner app · Note: 21.0 MH/s average over 7 minutes, 24.3 MH/s at the moment of the report, 33 accepted blocks
NVIDIA RTX 5090 (32 GB)		229not readnot measurednot measuredstock, benchstock2026-10-03team
Generator: v1 · Class v4 cost: not measured · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: proto-cuda bench (prototype, not mining) · Source: bench log: 3 October 2026, RTX 5090, memory-hard dataset (pack igneum-genesis-mh) · Note: genesis program, 104 loads per hash, 1 GiB dataset
NVIDIA RTX 5090 (32 GB)		185.3not readnot measurednot measuredstock, benchstock2026-10-03team
Generator: v1 · Class v4 cost: not measured · Tuned: stock, bench only · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: proto-cuda bench (prototype, not mining) · Source: bench log: 3 October 2026, RTX 5090 first run, dataset sweep and second program · Note: hourly program, 128 loads per hash, 1 GiB dataset
NVIDIA RTX 5090 (32 GB)		124.2not readnot measurednot measuredstock, miningstock2026-10-04team
Generator: v2 · Class v4 cost: not measured · Tuned: stock, mining · Hive flight sheet: stock (no measured tune point; the 5080 and 9070 XT passes and the class v4 efficiency pass land theirs when read) · Miner: Igneum Miner 0.3.0 package, prebuilt NVRTC worker · Source: bench log: 4 October 2026, the gfx1036 worker fault and what the Apple M5 Max could and could not reproduce · Note: live devnet v4, 128 loads per hash, CPU re-check clean, 0 rejected

How a row gets here

From 3231a80fe2cc7dd0823b1f7897c2229ef5da4f26 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 21:49:20 +0000 Subject: [PATCH 02/28] Site: the pages rebuilt on the record branch (the regrouped bench table and the outside-check text as built from this tree) Co-Authored-By: Claude Fable 5.1 --- docs/analysis/chip-model-v3.md | 6 ++++++ docs/evidence.md | 2 +- docs/plans/counter-asic-3-public-text-2026-10-07.md | 4 ++-- docs/plans/counter-asic-3-status.md | 2 +- site/claims.html | 4 ++++ site/evidence.html | 2 +- site/forbidden-strings.txt | 5 +++++ site/litepaper.html | 2 +- 8 files changed, 21 insertions(+), 6 deletions(-) diff --git a/docs/analysis/chip-model-v3.md b/docs/analysis/chip-model-v3.md index e98ed5e42..0fdfcdbb3 100644 --- a/docs/analysis/chip-model-v3.md +++ b/docs/analysis/chip-model-v3.md @@ -357,6 +357,12 @@ Reading: NO. Class v5 with the shadow at zero leaves the strongest chip at 5.1x Per tier: a miner on class v4 pays the premium and gets the 2.1x to 3.9x chip ceiling in exchange; on class v5 with the shadow kept the ceiling stays and the dataset is the chain's; on class v5 with the shadow dropped the premium goes and the ceiling returns to 5x to 9x. The decision is the founder's; this section gives the number. +### 5.11 Two columns from the counter-asic-4 research file (7 October 2026, 22:3x UK; `docs/analysis/counter-asic-4-research.md` sections 15 to 19 at bca23f96, the research lane's reading, carried here as the chip model's own columns) + +The k column. k is the chip core's energy per op over the GPU's at the same operating point, and the model's 3.4x row takes k about 0.33 for an ALU-shaped core. On the public figures the int8 tensor tile is the one GPU block whose energy per op a chip at the same node cannot undercut with certainty: the 4090 measures 0.056 pJ per MAC; NVIDIA's 5 nm INT4 test chip reads 0.021 pJ per MAC at 0.46 V and about 0.1 at nominal (JSSC 2023, via Dally's NASEM slides; claimed), so INT8 at 2x to 4x that gives k 0.7 to 3 with the centre near 1; every ALU-shaped block reads k 0.3 to 0.8 on the same sources. A shadow built of tensor tiles at the ALU shadow's premium (about 11,400 u8 tiles per hash) therefore gives 2.1x at k = 1 and 1.6x at k = 1.5 and removes the k 0.3 column from the table; it needs a SIMD byte-dot verifier (the scalar one at 12.4 ms fails the 10 ms gate). This is a design candidate, not the shipped stream: the shipped shadow is ALU-shaped and its row stays 2.1x at k = 1 and 3.4x at k about 0.33. + +The capex column. The `f = 1` GDDR7 chip of 5.5 is USD 2.8 per MH/s of silicon and memory, which is USD 0.00016 per MH/s-hour of capex over two years against USD 0.000023 of electricity: capex-dominated 7x, as the 5090 is (USD 14.7 per MH/s at MSRP, 10x). A 64 MiB hot table adds about USD 15 of N5 die, the shadow core USD 25 to 40, an interposer USD 200, so the chip's capex reaches at most about USD 4.3 per MH/s: the per-unit capex wall is unreachable by 3x to 7x, and the break-even market cap moves only through the project cost (the mission lane's model: about USD 100 M with the N5 shadow core, about 200 M if the shadow runs per load and forces one die or an interposer). Every figure here is modelled on cited or claimed parts; the research lane's microbench (20 probes, the mma_u8 and l2 rows the ones this model would take) is on PC 1's queue after the hot-table job. + ## 6. The per-day derivation (item 2) 6 October 2026, Counter ASIC 3.0 item 2, worker `derive` (`docs/plans/counter-asic-3-derivation.md`; everything diff --git a/docs/evidence.md b/docs/evidence.md index 4910bd485..07b80e10b 100644 --- a/docs/evidence.md +++ b/docs/evidence.md @@ -41,7 +41,7 @@ Versions in the table: `igneum-pow` is the Rust crate at `igneum-pow/Cargo.toml` | 14 | Ethereum bytecode runs unchanged, with the documented differences of spec 7.1 | Homepage Build card; litepaper Building | tested by the team | as row 13; fixes `F-exec-A`, `F-exec-B` (spec 7.5) | `tools/evm-smoke/smoke.mjs`: deploy via viem, `increment`, `hashLoop`, `eth_estimateGas`, `eth_getLogs`; `tools/exec-attacks` scenarios 1 and 3; bench-log "execution layer attack fixes" | Deployment, calls, reverts, logs and gas estimates behave as viem expects; chain id 4463; the prototype pgas table gives 0.0095 to 0.028 pgas per gas, below the design's band before calibration, 3 October 2026. 4 October 2026: a transaction that would cross the block's proving budget is refused by the mempool and, if forced in, aborted and charged with its nonce advanced (25 of 25 checks; 30 of 30 malformed cases). Apple M5 Max. The `Prover` precompile, proof records and the shard planner are not in the node | none yet | | 15 | Every block is proven, with the proof landing within about a minute at launch | Homepage stats ("~60 s to a proof"); litepaper Proving; roadmap phase 3 gate | implemented | repo `d7e1f89` (GPU proof), `e01a3cc`, `292e800`, `eedd136` (`proving/igneum-prove`: shard cutter, MPT witnesses, shard and aggregator guests); SP1 6.8.1; spec 7.2, 7.6 | `proving/windows-wsl2` (SETUP-PROVER, PROVE-BLOCK) on the RTX 5090; `igneum-prove-host --mode block` on `proving/fixtures/`; bench-log "proving v0 on the RTX 5090" and "proving: devnet v4 shards" | First GPU proof of an Igneum block, 4 October 2026, RTX 5090 (WSL2, SP1 cuda, mining paused): fixture `block-78-increment` (2 transactions), core proof 1.4 s (7.3 MB, verify 0.221 s), compressed proof 2.7 s (1.27 MB, verify 0.038 s), post-state and receipts roots identical to the node's; 15.7x and 20.6x faster than a loaded M5 Max CPU. The same day on that CPU (load 38 to 47): a three-shard block proved shard by shard and aggregated by recursion, 19 min (1,139 s) end to end, 245 to 337 s per compressed shard proof, every proof verified. What is not there: no proof is produced, carried or checked on the chain (the devnet prover is a stub that signs claims), the proving pool pays nobody (row 21), the block proven is far below one shard, and the 60-second figure remains a design target; the pass mark is the standard in `docs/benchmarks/proving-e2e.md`. Second RTX 5090 run, 4 October 2026 evening (job run-20261004-173115): a full shard at the provisional S_p (6.75 M pgas, 60.8 M cycles) executed in 1.63 s, core proof 8.3 s (18.1 MB), compressed proof 10.9 s (1.27 MB, verify 0.040 s); a two-shard block (13.5 M pgas) proved shard by shard (11.7 s and 10.0 s) and aggregated in 2.2 s, 24 s of GPU stages end to end, every proof verified, six tampered witnesses rejected. The two host defects (an abort after the upload, an idle wait that turned out to be an unbuffered 18 MB proof save through the WSL2 file bridge, 24 minutes) are fixed (ledger P20) 5 October 2026, live devnet with real transactions (bench-log "real transactions, the first non-empty shard proven and paid"): block 72704 shard 0, 29 transfers, 5,800 pgas, proven on PC 2 in 34 s, verified on the Mac in 0.297 s and paid 1.7623 IGN, 53 s after the chain block executed; of about 1,400 blocks in the 20-minute window 36 were proven (the one prover takes the newest shard assigned to it), so "every block" is not yet true; a second content shard (72803, all copies skipped) failed the native-execution veto on the exporter's block structure, fixed with fixtures the same day, the node side pending the 0.3.9 rollout 5 October 2026, evening (bench-log "proving v1"): the aggregated segment record, the chain rule and the unproven rule are implemented behind `proving_v1_activation_daa` (branch proving-v1, not on the devnet before 0.3.11); on the RTX 5090 a chain of 8 consecutive live blocks proved and aggregated by recursion in 135.6 s with the miner on the card (17 s a block, one proof of 1,272,909 bytes attesting all 8, verified in 0.04 s); the 3-node fast-time harness paid a segment record 1.0 s after submission and refused a late one after its deadline (21 checks); the devnet itself, with one prover, carried proofs for 2.4% of blocks over 30 minutes at a block-to-record latency p50 44 s, p99 52 s. The "within about a minute" holds per proven block; "every block" needs 18 mining 5090s or 6 proving-only cards at empty blocks on the measured rates, and the mandatory rule stays off until the share is one | none yet | | 16 | A 12 GB card proves one shard in about 20 s (WITHDRAWN 5 October 2026: a 24 GB card proves a full shard at the adopted size in 4.3 s; 32 GB mines and proves) | Litepaper Proving ("The proving budget"); roadmap gate 2 | designed | spec 5.1 (Target), 7.6 (`S_p` provisional, 7,500,000 pgas = `B_p` / 4) | `PROVE-SHARD.bat` on the RTX 5090 (pending); the end-to-end standard in `docs/benchmarks/proving-e2e.md`; bench-log "proving: devnet v4 shards" | Measured on a 32 GB card, not yet on a 12 GB card. A shard at the provisional `S_p` is 60.8 M SP1 cycles on the prototype pgas table (9 cycles per pgas, 44 per EVM gas; the modexp entry about 100x its SP1 cost); on an RTX 5090 (4 October 2026 evening, job run-20261004-173115) it executed in 1.63 s and its compressed proof took 10.9 s, verified in 0.040 s, so the 32 GB card is inside the 20 s target with margin. Whether a 12 GB card proves it at all, and in what time, is the next measurement (an RTX 3060 and an RTX 5060 Ti 16 GB are on order). A per-shard time can be met by shrinking the shard, so the project does not use it as a pass mark 5 October 2026, evening (bench-log "proving v1", the S_p curve): measured on the RTX 5090 with SP1 6.8.1's GPU prover, the card to itself, 1-s nvidia-smi samples: an empty shard 13,874 MiB and 2.2 s; a full shard at the ADOPTED v1 budget (30,000 pgas, 4.7 M cycles) 20,434 MiB and 4.3 s; the full prototype shard (6.75 M pgas, 60 M cycles) 28,307 MiB and 10.8 s; beside the miner 15,670 and 30,039 MiB. No environment knob of SP1 moves the 13.9 GB floor and the GPU server has no options of its own, so on this build a 12 GB card proves nothing, a 16 GB card only empty shards, a 24 GB card the adopted full shard alone and beside the miner (22,210 MiB and 13.2 s, measured on the 32 GB card: the 5090's allocation pattern, not yet a run on a 24 GB card) and a 32 GB card the prototype shard beside the miner with 2.5 GB spare. The litepaper line now says so; the 12 GB gate returns when a prover build with a smaller floor is measured on a 12 GB card | none yet | -| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026). | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word | +| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026). | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and no outside review has run yet | | 18 | The chip resistance measurements: the program is latency-bound (random reads), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache | Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page | tested by the team | readwidth e752fc7 (`docs/plans/read-width.md`), ca2-era 78c0ee4, ca2-cache 2de19e5 (`docs/plans/hot-table.md`) | The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per load | Latency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026 | none yet | | 19 | The lottery hash is sound as a hash: uniform output, deterministic, no out-of-bounds read, fuzzed; class v3 bit-exact on the three vendors | Litepaper vs RandomX ("Every number above is measured and logged"), the numbers page | tested by the team | ca2-mixer 1ab8b21 (`tests/mixer.rs`, `tests/scratch.rs`), ca2-era 78c0ee4, ca2-soundness a465881 (`docs/analysis/scratch-soundness.md`), `igneum-pow/tests/packs.rs` | The crate suite (53 + 4 + 19 + 7), the Metal fuzz, edge, stats and determinism runs on the v3 construction, the pack vectors and 2^24 fingerprints on Metal, Apple OpenCL, the RTX 5090 and the RX 9070 XT, the 1,024-hash CPU re-check per card | Class v3 (mixer x8 + era): 200-program fuzz 200 of 200 on Metal, every tenth on Apple OpenCL; the pinned v3 packs 3/3 + 3/3 and 96 of 96 lanes on Metal and Apple OpenCL; the six era packs' fingerprints equal on the three vendors (PC 1 job run-ca2-era-pc1-20261005, 5 October 2026); the v2 exports byte-identical on the v3 crate; the final-class PC rows and the G2 re-check: job run-ca2-era-pc1b-20261005 (pending at the time of writing) | none yet | | 20 | No premine, no pre-sale, no allocation: every coin is minted by the schedule and every coin goes to the block producer (80%) and the proving pool (20%) | Homepage stats and Economics tiles; litepaper Supply, Economics | implemented | repo `6ac80a3`; fork "igneum-node devnet v0"; `consensus/core/src/igneum.rs`, `coinbase.rs` | `cargo test -p kaspa-consensus-core igneum` (8 pass: subsidy table, ramp, split, cap) and `cargo test -p kaspa-consensus coinbase` (8 pass); `igneum-miner inspect 40`; bench-log "igneum-node devnet v0" | Coinbases on the devnet: 80/20 exact on 39 of 39 single-payee blocks, the 20% to the `igneum-proving-pool-v0` output; the per-second schedule sums to under the 4,000,000,000 cap by less than 100 coins; 3,168,808,781 units per DAA second in years 0 to 2, halving at 63,115,200 DAA s. 3 October 2026, Apple M5 Max. The devnet genesis carries no allocation; the mainnet genesis does not exist yet, so the claim is about the code and the stated rule, not a launch that has happened | none yet | diff --git a/docs/plans/counter-asic-3-public-text-2026-10-07.md b/docs/plans/counter-asic-3-public-text-2026-10-07.md index ee0afaded..583a12c57 100644 --- a/docs/plans/counter-asic-3-public-text-2026-10-07.md +++ b/docs/plans/counter-asic-3-public-text-2026-10-07.md @@ -20,7 +20,7 @@ The chip model. We price the strongest chip we can design against an RTX 5090 an | When a stored-dataset chip pays for itself | at about USD 100 M of market cap in the first two years, not before | modelled, 7 October 2026 | | The baseline the work started from: the same chip under class v3, without the shadow (the Ethash class) | 5x to 9x (5.1x on GDDR7, 9.2x on eight HBM3 stacks; the Ethash chips of this class reached 2.1x to 4.8x) | modelled, 6 October 2026; the precedent measured by others, 2020 to 2022; never the launch state | -What a miner sees from this. Class v4 costs a 5090 about 80 W more for 0.2 percent of rate, an M5 Max 16 W more for 1.5 percent, an RX 9070 XT and an RTX 4070 nothing (all measured, 6 October 2026). The ladder that sets how much work rides in the shadow starts at rung 0 at genesis and climbs by miner signal; its third rung is inadmissible today because a server core verifies it in 10.85 ms, over the gate (measured, 7 October 2026). On the devnet, which started on class v3, class v4 arrives by miner signal at a published height (a devnet fact, not a launch one). The next test of the model is an internal adversarial pass, not an independent review: three lanes that have never worked on the hash code attack the mixer, the chained cache and the acceptance rule with only what an outsider has (the public kit, the frozen object, the spec, the harnesses) and publish the break or the bound they reach. The one outside check is staged and waits on its escrow and the publish word. +What a miner sees from this. Class v4 costs a 5090 about 80 W more for 0.2 percent of rate, an M5 Max 16 W more for 1.5 percent, an RX 9070 XT and an RTX 4070 nothing (all measured, 6 October 2026). The ladder that sets how much work rides in the shadow starts at rung 0 at genesis and climbs by miner signal; its third rung is inadmissible today because a server core verifies it in 10.85 ms, over the gate (measured, 7 October 2026). On the devnet, which started on class v3, class v4 arrives by miner signal at a published height (a devnet fact, not a launch one). The next test of the model is an internal adversarial pass, not an independent review: three lanes that have never worked on the hash code attack the mixer, the chained cache and the acceptance rule with only what an outsider has (the public kit, the frozen object, the spec, the harnesses) and publish the break or the bound they reach. No outside review has run yet. ## 3. The miner page's line @@ -30,4 +30,4 @@ Your card against the strongest chip we can price: an RTX 5090 at 136 MH/s on 35 | # | Claim | Where it is made | Status | Version or commit | Reproducible test | Result, date, machine | Independent verification | |---|---|---|---|---|---|---|---| -| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word | +| 17 | The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state) | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measured | `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/plans/counter-asic-3-status.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; `docs/design/class-v5-stored-state.md`; the H100 and market-cap rows of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, PC 2's RTX 5090, PC 1's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and no outside review has run yet | diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 48a1c0d6a..35c6a8a84 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,7 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule diff --git a/site/claims.html b/site/claims.html index 347fd71c5..f86f4de02 100644 --- a/site/claims.html +++ b/site/claims.html @@ -229,6 +229,10 @@
  • A cryptography team. Not yet. One founder working with AI systems wrote the design and the code; external reviewers are named and paid before gate 3, and every security claim here is a design claim until then.
  • Finality that no amount of hardware can break. No. A miner holding a third of the last 30 days of blocks can split finality during a network partition, and two thirds can lock a bad checkpoint for a double-spend bounded by the 12-hour finality depth. Reaching a third takes at least ten days of producing every block on the chain, in public; an attacker matching the honest network needs twenty days for a third and never reaches two thirds. That is harder than attacking Bitcoin, where a majority can reorganise at once, and it is the limit of proof of work without stake or an outside chain. Igneum chose those limits on purpose. The floor is also bounded in time: an honest partition that lasts long enough for each side's own new blocks to reach two thirds of its window locks on both sides, about ten days of a 30-day window at an even split, and an operator must then resolve it (measured on a test network, 4 October 2026).
  • Finality that never pauses. No. A lock needs two thirds of all 30-day mining weight. Whenever less than two thirds of that weight is connected and signing, finality pauses until it returns or ages out of the window, up to 30 days. The chain keeps running on proof of work and the node reports the pause.
    • +
  • A label that costs nothing. No. Some investors and exchanges read "GPU-mined" as 2021 whatever the proofs do, and nothing here measures that cost. The only evidence will be whether the first miner apps and verifiable-compute apps sign despite the label.
    • +
  • A chain you can debug today. Not yet. The node does not serve debug_traceTransaction, eth_subscribe or eth_getProof, and there is no public RPC, faucet or explorer for the devnet. They come in a fixed order (docs and templates, then the tracing and subscription RPCs, then a public RPC, listing and faucet, then the explorer) and no outside team is invited to build before the second step is done.
    • +
  • A veto on job results. No. A segment proof is checked against every node's own execution; a proving job for another chain is not, because no full node can re-run an arbitrary program, so a soundness bug in the proof system in force reaches the requesting contract. A job output can mint nothing and touch no system contract, and an app that acts irreversibly on a job result keeps its own fallback.
    • +
  • A delay function that outlives a quantum computer. No. The class-group delay between a locked checkpoint and the next program seed falls to the same machine that would forge the vote keys; it is flagged in the specification, not yet sized, and the fallback is a hash-chain delay behind the same version byte that moves the signature scheme, so both flip in one class change. A grindable hourly seed is a liveness nuisance against the lottery, not a break of finality.
  • A finished protocol. The sustained-mining finality rule is the newest piece and the one that external review will try hardest to break. The specification, the review and the benchmarks are published as they happen.

    • Everything in this document is subject to the gates on the roadmap. Nothing in it is an offer to sell anything. Found an error, or a criticism this document does not answer? Email hello@igneum.network, or open an issue on the public specification repository: git.igneum.network/igneum-network/spec/issues. Post reaches Igneum Labs LTD, Unit IH-00-01-01-OF-01, Level 01, Innovation One, Dubai International Financial Centre.

    diff --git a/site/evidence.html b/site/evidence.html index a24934014..081cd0489 100644 --- a/site/evidence.html +++ b/site/evidence.html @@ -254,7 +254,7 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v 14Ethereum bytecode runs unchanged, with the documented differences of spec 7.1
    Homepage Build card; litepaper Building
    tested by the teamas row 13; fixes F-exec-A, F-exec-B (spec 7.5)tools/evm-smoke/smoke.mjs: deploy via viem, increment, hashLoop, eth_estimateGas, eth_getLogs; tools/exec-attacks scenarios 1 and 3; bench-log "execution layer attack fixes"Deployment, calls, reverts, logs and gas estimates behave as viem expects; chain id 4463; the prototype pgas table gives 0.0095 to 0.028 pgas per gas, below the design's band before calibration, 3 October 2026. 4 October 2026: a transaction that would cross the block's proving budget is refused by the mempool and, if forced in, aborted and charged with its nonce advanced (25 of 25 checks; 30 of 30 malformed cases). Apple M5 Max. The Prover precompile, proof records and the shard planner are not in the nodenone yet 15Every block is proven, with the proof landing within about a minute at launch
    Homepage stats ("~60 s to a proof"); litepaper Proving; roadmap phase 3 gate
    implementedrepo d7e1f89 (GPU proof), e01a3cc, 292e800, eedd136 (proving/igneum-prove: shard cutter, MPT witnesses, shard and aggregator guests); SP1 6.8.1; spec 7.2, 7.6proving/windows-wsl2 (SETUP-PROVER, PROVE-BLOCK) on the RTX 5090; igneum-prove-host --mode block on proving/fixtures/; bench-log "proving v0 on the RTX 5090" and "proving: devnet v4 shards"First GPU proof of an Igneum block, 4 October 2026, RTX 5090 (WSL2, SP1 cuda, mining paused): fixture block-78-increment (2 transactions), core proof 1.4 s (7.3 MB, verify 0.221 s), compressed proof 2.7 s (1.27 MB, verify 0.038 s), post-state and receipts roots identical to the node's; 15.7x and 20.6x faster than a loaded M5 Max CPU. The same day on that CPU (load 38 to 47): a three-shard block proved shard by shard and aggregated by recursion, 19 min (1,139 s) end to end, 245 to 337 s per compressed shard proof, every proof verified. What is not there: no proof is produced, carried or checked on the chain (the devnet prover is a stub that signs claims), the proving pool pays nobody (row 21), the block proven is far below one shard, and the 60-second figure remains a design target; the pass mark is the standard in docs/benchmarks/proving-e2e.md. Second RTX 5090 run, 4 October 2026 evening (job run-20261004-173115): a full shard at the provisional S_p (6.75 M pgas, 60.8 M cycles) executed in 1.63 s, core proof 8.3 s (18.1 MB), compressed proof 10.9 s (1.27 MB, verify 0.040 s); a two-shard block (13.5 M pgas) proved shard by shard (11.7 s and 10.0 s) and aggregated in 2.2 s, 24 s of GPU stages end to end, every proof verified, six tampered witnesses rejected. The two host defects (an abort after the upload, an idle wait that turned out to be an unbuffered 18 MB proof save through the WSL2 file bridge, 24 minutes) are fixed (ledger P20) 5 October 2026, live devnet with real transactions (bench-log "real transactions, the first non-empty shard proven and paid"): block 72704 shard 0, 29 transfers, 5,800 pgas, proven on the RTX 5090 Windows rig in 34 s, verified on the Apple M5 Max in 0.297 s and paid 1.7623 IGN, 53 s after the chain block executed; of about 1,400 blocks in the 20-minute window 36 were proven (the one prover takes the newest shard assigned to it), so "every block" is not yet true; a second content shard (72803, all copies skipped) failed the native-execution veto on the exporter's block structure, fixed with fixtures the same day, the node side pending the 0.3.9 rollout 5 October 2026, evening (bench-log "proving v1"): the aggregated segment record, the chain rule and the unproven rule are implemented behind proving_v1_activation_daa (branch proving-v1, not on the devnet before 0.3.11); on the RTX 5090 a chain of 8 consecutive live blocks proved and aggregated by recursion in 135.6 s with the miner on the card (17 s a block, one proof of 1,272,909 bytes attesting all 8, verified in 0.04 s); the 3-node fast-time harness paid a segment record 1.0 s after submission and refused a late one after its deadline (21 checks); the devnet itself, with one prover, carried proofs for 2.4% of blocks over 30 minutes at a block-to-record latency p50 44 s, p99 52 s. The "within about a minute" holds per proven block; "every block" needs 18 mining 5090s or 6 proving-only cards at empty blocks on the measured rates, and the mandatory rule stays off until the share is onenone yet 16A 12 GB card proves one shard in about 20 s (WITHDRAWN 5 October 2026: a 24 GB card proves a full shard at the adopted size in 4.3 s; 32 GB mines and proves)
    Litepaper Proving ("The proving budget"); roadmap gate 2
    designedspec 5.1 (Target), 7.6 (S_p provisional, 7,500,000 pgas = B_p / 4)PROVE-SHARD.bat on the RTX 5090 (pending); the end-to-end standard in docs/benchmarks/proving-e2e.md; bench-log "proving: devnet v4 shards"Measured on a 32 GB card, not yet on a 12 GB card. A shard at the provisional S_p is 60.8 M SP1 cycles on the prototype pgas table (9 cycles per pgas, 44 per EVM gas; the modexp entry about 100x its SP1 cost); on an RTX 5090 (4 October 2026 evening, job run-20261004-173115) it executed in 1.63 s and its compressed proof took 10.9 s, verified in 0.040 s, so the 32 GB card is inside the 20 s target with margin. Whether a 12 GB card proves it at all, and in what time, is the next measurement (an RTX 3060 and an RTX 5060 Ti 16 GB are on order). A per-shard time can be met by shrinking the shard, so the project does not use it as a pass mark 5 October 2026, evening (bench-log "proving v1", the S_p curve): measured on the RTX 5090 with SP1 6.8.1's GPU prover, the card to itself, 1-s nvidia-smi samples: an empty shard 13,874 MiB and 2.2 s; a full shard at the ADOPTED v1 budget (30,000 pgas, 4.7 M cycles) 20,434 MiB and 4.3 s; the full prototype shard (6.75 M pgas, 60 M cycles) 28,307 MiB and 10.8 s; beside the miner 15,670 and 30,039 MiB. No environment knob of SP1 moves the 13.9 GB floor and the GPU server has no options of its own, so on this build a 12 GB card proves nothing, a 16 GB card only empty shards, a 24 GB card the adopted full shard alone and beside the miner (22,210 MiB and 13.2 s, measured on the 32 GB card: the 5090's allocation pattern, not yet a run on a 24 GB card) and a 32 GB card the prototype shard beside the miner with 2.5 GB spare. The litepaper line now says so; the 12 GB gate returns when a prover build with a smaller floor is measured on a 12 GB cardnone yet -17The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state)
    the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line
    tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measureddocs/analysis/chip-model-v3.md 5 and 6; docs/analysis/latency-shadow-2026-10-06.md; docs/plans/counter-asic-3-status.md; docs/analysis/attack-pass/f8-uniform.md, f4-weakday.md, docs/analysis/ca3-v4-uniform.md; docs/design/class-v5-stored-state.md; the H100 and market-cap rows of 7 October; docs/plans/cryptanalysis/in-house-pass.md (the internal adversarial pass)the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses tools/attack/f8-uniform and the F4 census; the verifier by igneum-pow bench136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, the RTX 5090 Windows rig's RTX 5090, the three-card Windows rig's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026).none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and the one outside check is staged and waits on its escrow and the publish word +17The chip resistance claim: at launch the strongest chip in the public model reaches 2.1x (a core as good as a GPU lane, k = 1) to 3.4x (a core three times better, k about 0.33) per joule against an RTX 5090 under class v4, live from genesis on the testnet and the mainnet; the ladder's second rung brings it to about 2.8x; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; a stored-dataset chip pays for itself only at about USD 100 M of market cap in two years; without class v4 the same chip would reach 5x to 9x (the class v3 baseline, the devnet's starting state, never the launch state)
    the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line
    tested by the team (every card, the verifier, the two attack-pass bounds, the H100), the chip itself modelled, class v5 and the ladder designed, the X9 figure claimed against a CPU core and never measureddocs/analysis/chip-model-v3.md 5 and 6; docs/analysis/latency-shadow-2026-10-06.md; docs/plans/counter-asic-3-status.md; docs/analysis/attack-pass/f8-uniform.md, f4-weakday.md, docs/analysis/ca3-v4-uniform.md; docs/design/class-v5-stored-state.md; the H100 and market-cap rows of 7 October; docs/plans/cryptanalysis/in-house-pass.md (the internal adversarial pass)the chip model's arithmetic in its file; the card rows by the benchmark package; the attack-pass harnesses tools/attack/f8-uniform and the F4 census; the verifier by igneum-pow bench136 MH/s at 350 W (5090, bench) and 290 W (app); 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; 2.1x, 3.4x, 2.8x at launch; the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; USD 100 M; 5.1x to 9.2x the class v3 baseline; 6 and 7 October 2026, the M5 Max, the RTX 5090 Windows rig's RTX 5090, the three-card Windows rig's RX 9070 XT and RTX 4070, a rented H100 SXM, igneum-build-1 The k about 0.33 bound is the implied core of Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025), withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: a claimed, unmeasured figure carried as the pessimistic bound, not a calibration point (attack pass AP-F5-1, 7 October 2026).none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), and no outside review has run yet 18The chip resistance measurements: the program is latency-bound (random reads), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache
    Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page
    tested by the teamreadwidth e752fc7 (docs/plans/read-width.md), ca2-era 78c0ee4, ca2-cache 2de19e5 (docs/plans/hot-table.md)The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per loadLatency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026none yet 19The lottery hash is sound as a hash: uniform output, deterministic, no out-of-bounds read, fuzzed; class v3 bit-exact on the three vendors
    Litepaper vs RandomX ("Every number above is measured and logged"), the numbers page
    tested by the teamca2-mixer 1ab8b21 (tests/mixer.rs, tests/scratch.rs), ca2-era 78c0ee4, ca2-soundness a465881 (docs/analysis/scratch-soundness.md), igneum-pow/tests/packs.rsThe crate suite (53 + 4 + 19 + 7), the Metal fuzz, edge, stats and determinism runs on the v3 construction, the pack vectors and 2^24 fingerprints on Metal, Apple OpenCL, the RTX 5090 and the RX 9070 XT, the 1,024-hash CPU re-check per cardClass v3 (mixer x8 + era): 200-program fuzz 200 of 200 on Metal, every tenth on Apple OpenCL; the pinned v3 packs 3/3 + 3/3 and 96 of 96 lanes on Metal and Apple OpenCL; the six era packs' fingerprints equal on the three vendors (the three-card Windows rig (RTX 5090, RTX 4070, RX 9070 XT) job run-ca2-era-pc1-20261005, 5 October 2026); the v2 exports byte-identical on the v3 crate; the final-class PC rows and the G2 re-check: job run-ca2-era-pc1b-20261005 (pending at the time of writing)none yet 20No premine, no pre-sale, no allocation: every coin is minted by the schedule and every coin goes to the block producer (80%) and the proving pool (20%)
    Homepage stats and Economics tiles; litepaper Supply, Economics
    implementedrepo 6ac80a3; fork "igneum-node devnet v0"; consensus/core/src/igneum.rs, coinbase.rscargo test -p kaspa-consensus-core igneum (8 pass: subsidy table, ramp, split, cap) and cargo test -p kaspa-consensus coinbase (8 pass); igneum-miner inspect 40; bench-log "igneum-node devnet v0"Coinbases on the devnet: 80/20 exact on 39 of 39 single-payee blocks, the 20% to the igneum-proving-pool-v0 output; the per-second schedule sums to under the 4,000,000,000 cap by less than 100 coins; 3,168,808,781 units per DAA second in years 0 to 2, halving at 63,115,200 DAA s. 3 October 2026, Apple M5 Max. The devnet genesis carries no allocation; the mainnet genesis does not exist yet, so the claim is about the code and the stated rule, not a launch that has happenednone yet diff --git a/site/forbidden-strings.txt b/site/forbidden-strings.txt index ac88ce391..eec90bffd 100644 --- a/site/forbidden-strings.txt +++ b/site/forbidden-strings.txt @@ -38,3 +38,8 @@ disclosure prize # the rig names never reach a served page (verification lane, 7 October 2026: a substring grep read "PC 2" inside gRPC port numbers; this is the word-bounded check) \bPC [12]\b counsel is engaged +# 7 October 2026 (main's rule): the one outside check is never hinted at before its time; the phrase class, not the bare words (the proving pool's escrow and a staged build are ordinary) +outside check +waits on its escrow +staged and waits +the publish word diff --git a/site/litepaper.html b/site/litepaper.html index cf8cf3082..defe6ddf3 100644 --- a/site/litepaper.html +++ b/site/litepaper.html @@ -449,7 +449,7 @@ body.all .pager{display:none} When a stored-dataset chip pays for itselfat about USD 100 M of market cap in the first two years, not beforemodelled, 7 October 2026 The baseline the work started from: the same chip under class v3, without the shadow (the Ethash class)5x to 9x (5.1x on GDDR7, 9.2x on eight HBM3 stacks; the Ethash chips of this class reached 2.1x to 4.8x)modelled, 6 October 2026; the precedent measured by others, 2020 to 2022; never the launch state
    -

    What a miner sees from this. Class v4 costs a 5090 145 W more unlocked, 88 W more at a 1,400 MHz core lock and 82 W at the best operating points (class v4 at 1,200 MHz, class v3 at 1,300; the knee is 1,300 MHz on both), for 0.2 percent more rate (measured, 7 October 2026; the 80 W read on 6 October was at the app's tuned cap); an M5 Max 16 W more for 1.5 percent, an RX 9070 XT and an RTX 4070 nothing (measured, 6 October 2026). The ladder that sets how much work rides in the shadow starts at rung 0 at genesis and climbs by miner signal; its third rung is inadmissible today because a server core verifies it in 10.85 ms, over the gate (measured, 7 October 2026). Devnet 3 runs class v4 from its first block (7 October 2026); the first devnet started on class v3 and reaches class v4 by miner signal at a published height. The next test of the model is an internal adversarial pass, not an independent review: three lanes that have never worked on the hash code attack the mixer, the chained cache and the acceptance rule with only what an outsider has (the public kit, the frozen object, the spec, the harnesses) and publish the break or the bound they reach. The one outside check is staged and waits on its escrow and the publish word.

    +

    What a miner sees from this. Class v4 costs a 5090 145 W more unlocked, 88 W more at a 1,400 MHz core lock and 82 W at the best operating points (class v4 at 1,200 MHz, class v3 at 1,300; the knee is 1,300 MHz on both), for 0.2 percent more rate (measured, 7 October 2026; the 80 W read on 6 October was at the app's tuned cap); an M5 Max 16 W more for 1.5 percent, an RX 9070 XT and an RTX 4070 nothing (measured, 6 October 2026). The ladder that sets how much work rides in the shadow starts at rung 0 at genesis and climbs by miner signal; its third rung is inadmissible today because a server core verifies it in 10.85 ms, over the gate (measured, 7 October 2026). Devnet 3 runs class v4 from its first block (7 October 2026); the first devnet started on class v3 and reaches class v4 by miner signal at a published height. The next test of the model is an internal adversarial pass, not an independent review: three lanes that have never worked on the hash code attack the mixer, the chained cache and the acceptance rule with only what an outsider has (the public kit, the frozen object, the spec, the harnesses) and publish the break or the bound they reach. No outside review has run yet.

    No hash has stayed free of chips forever. Igneum does not claim to. It states the gain its own model finds, the response takes a week, and both are measured. The model is public: the numbers; the claim is tested by the in-house adversarial pass and the public benchmark. Monero has run on RandomX since 2019 (approximate) with no chip shipped. Bitmain opened Antminer X9 pre-orders on 26 December 2025 for July 2026 delivery, then withdrew the product in mid-May 2026 and refunded buyers before any unit shipped; none has been independently benchmarked. A box with about a 2x per joule edge over the best CPUs, and about 3x over a desktop, was withdrawn rather than face a RandomX re-tune of 1.5x or more. That is the band Igneum’s class v4 model sits in (2.1x to 3.4x over an RTX 5090), and the defence that held was a maintained algorithm with a credible upgrade path, which is what the ladder is.

    One thing takes a person, here and on every chain that exists: writing new code. A chain cannot safely write its own generator, and it cannot safely tell a chip from a wave of honest new cards by hashrate alone. If the design above ever failed, anyone could publish a new generator and miners would switch it on by signalling, as Monero's community can fork. Igneum is built to make that day unlikely, and does not depend on avoiding it.

    From 0690a36328cfcf405ba4e4ba285c10d62de4ed16 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:07:25 +0000 Subject: [PATCH 03/28] Counter ASIC 3.0 status: F8 PASS on class v5 (61 of 64, the residue named), the 0.3.24 pin 47b9b229, the AMD half of G1 paid, the helper fault read, the CA4 prototypes, the ledger close landed Co-Authored-By: Claude Fable 5.1 (cherry picked from commit 015cc8395a0300ae6ae5cc1690b4799e0eaead98) --- docs/plans/counter-asic-3-status.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 35c6a8a84..79a0de271 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,7 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule From be627a8994239abb27699ed3c5bd6005706efb34 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:19:30 +0000 Subject: [PATCH 04/28] Spec 01: the acceptance rule and the draw as igneum-pow ships them at c79f6d96 (adv-accept-3 finding 3, 7 October 2026 night; ledger AP-F8-5) 1.4.3 rewritten: the draw's two per-register states (fresh, fresh_value), the dataflow table and the shared-operand rule the class v4 shape uses for the load source, the empty-list fallback, the era window draws, the shadow block's draw from the same stream (256 ALU slots, era draws consumed), the draw counts per class (592, 720, 3,536). 1.4.6 rewritten into 1.4.6.1 to 1.4.6.6: (a) over two passes of the base instructions, (b), (a') to its fixpoint then a checking pass over base then shadow, (c) with the shadow block executed 27 times per iteration and its inputs and limits in tables, (c') saturated sources at 164 of 16,384, (c'') the distinct-index ratio at 2^20 evaluations with the 0.98 floor and its integer form, the attempts and the two caps (32; 256) with the measured per-part rates, the last resort stated as unreachable and unverified (fails (a) on 251 of 3,000 seeds), the program id with the generator-4 "sub/" || 3_le16 suffix and the class-rung form, a "Constants of the shipped rule" table and a "Pinned program ids" table in the shape the hash lane's read-back test parses. 1.7 gains the shadow block's execution; 1.13.1 names the ninth consumed era draw (the latency ladder); 1.8.5 carries the one-line pointer to class v5's 1.8.6 (agreed with the v5 lane). docs/fud-ledger.md AP-F8-5 (the finding, the fix, the check); docs/ledger-public.md regenerated. Co-Authored-By: Claude Fable 5.1 --- docs/fud-ledger.md | 9 ++ docs/ledger-public.md | 3 +- docs/spec/01-lottery-hash.md | 154 +++++++++++++++++++++++++++++++---- 3 files changed, 148 insertions(+), 18 deletions(-) diff --git a/docs/fud-ledger.md b/docs/fud-ledger.md index ca3002af7..c95f3e846 100644 --- a/docs/fud-ledger.md +++ b/docs/fud-ledger.md @@ -2501,6 +2501,15 @@ Owed (recorded, not run, by the founder's word): G2 (the CPU verifier on 1,024 h Status: Fixed in part, finding bounded, stated (7 October 2026, night, the Counter ASIC lane's words): class v4 sub-version 3 (igneum-pow 017e7037, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under 1.2x with the four-seed tail accepted by the coordinator as the window model's unattributed residue (no chip consequence); the pass then attributed the class by value (eight live hot sets at 1.54x to 2.24x in the lowest 30 of 29,032 accepted programs, each about 1 MB of items at 0.3 percent of reads, 1.002x to a chip); class v5 (1c420786, frozen 21:53 UK) carries the fix as rule (c'''), the per-site distinct-index floor at 0.995 on the state flag (its census refuses 2.435 percent of accepted programs; seven of seven live hot sets refused at 0.9821 to 0.9919; the eighth's ratio owed tonight), with a named residual (three mild shadow-block-written concentrations at 0.9992 to 0.9997, about 1.0004x, a value-level test in the next class); the record is `docs/plans/counter-asic-3-status.md` section 7c and the class v5 design's section 14. The eighth live hot set (seed 122960, id 4be7393ab6c84802, the deepest found: X_f +0.111 percent, 1.54x the window model, its hottest item at 475,616 reads from an all-ones source) reads minimum site 12 at 0.9824 at the acceptance's own 2^20 sample (live 0.9822), refused by class v5's (c''') floor at 0.995; so the floor refuses eight of eight live hot sets by X_f at or above f found in the tail of 88,051 accepted programs (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; what it misses stays the three mild shadow-block-written concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x to a chip, the value-level test in the next class (22:41 BST; the logs under `docs/analysis/cryptanalysis/logs/adv-accept/` on branch adv-accept; the v5 design's section 14). The RTX 5080 grid's knee is not in tonight; X37 keeps the 5080's stock premium only. +### AP-F8-5. The public specification did not describe the shipped acceptance rule (documentary; no object change) +"An implementation written from docs/spec/01-lottery-hash.md section 1.4.6 at 017e7037 mines a different program from the node on 264 of 400 epochs." Found by the in-house pass adv-accept-3 (report-acceptance-rule-3.md at 0c150e3c, finding 3, section 6.2, 7 October 2026, night): the text described (a), (b) and (c) with a 32-attempt cap and an id without a suffix, while the code adds (a') with the shared-operand rule, (c'), (c'') at 2^20 evaluations, the 256-attempt cap keyed on the class v4 shape, the total draw with the last resort, generator 4 and the sub-version suffix, and executes the 256-instruction shadow block 27 times per iteration inside the acceptance interpreter. Measured (sweep 97, 400 seeds, 1,317 attempt verdicts): 759 verdicts differ (758 the code rejects and the text accepts: (a') 733, (c'') 15, (c) 10; 1 the other way, the shadow block changing a (c) statistic); 264 of 400 seeds choose another attempt; the parts the text did carry, (a) and (b), agree on every row. + +Status: Spec fixed (7 October 2026, night, the site audit lane by main's order, branch spec-accept-23): sections 1.4.3 and 1.4.6 of `docs/spec/01-lottery-hash.md` rewritten to the shipped rule at igneum-pow 017e7037 with every constant named and every order of operations stated (1.4.3: the two per-register states of the draw, the dataflow table, the shared-operand rule, the shadow block's draw and the draw counts per class; 1.4.6.1 to 1.4.6.6: (a) cyclic over two passes, (b), (a') to the fixpoint then a checking pass, (c) with the shadow executed and its limits in a table, (c') and (c'') with the integer form of the ratio compare, the attempts and the two caps with the measured per-part rates, the last resort stated as unreachable and unverified, the program id with the generator-4 suffix, a constants table in the shape the crate's read-back test parses, the pinned ids a reader must reproduce); section 1.7 gains the shadow block's execution; section 1.13.1 names the two consumed era draws. The hash lane's `igneum-pow/tests` read-back test parses the two tables against the crate's `pub const` items and derives every pinned id (its landing is the row's check; AP-F8-4 carries the derivation-text half of the same finding). + +Answer: Correct, and the largest divergence source the pass found was documentary. The rule the chain runs was right; the text a second implementer would read was three sub-versions behind it. The fix is the text, written to the code line by line, and a test that fails when the two drift again. + +Evidence: `docs/analysis/cryptanalysis/report-acceptance-rule-3.md` sections 6.2 to 6.4 (branch adv-accept-3); `docs/spec/01-lottery-hash.md` 1.4.3, 1.4.6, 1.7, 1.13.1 (branch spec-accept-23); `igneum-pow/src/accept.rs`, `igneum-pow/src/generator.rs` at 017e7037. + ## Genesis forward-compatibility entries (7 October 2026, mission item 8, branch `genesis-forward`) The three genesis fields of `docs/analysis/mission/mission.md` section 2.8, built on the node fork branch `genesis-forward` (from release-0.3.19-node dc141409) and the repo branch `genesis-forward`; the design and the gates in `docs/design/genesis-forward.md`. Every switch is never on the devnet (its digest c562d70e... does not move); the testnet genesis sets all three (the testnet lane re-pins and re-digests). diff --git a/docs/ledger-public.md b/docs/ledger-public.md index 2cdcaa68e..529637680 100644 --- a/docs/ledger-public.md +++ b/docs/ledger-public.md @@ -2,7 +2,7 @@ Generated by `tools/ledger/export-public.mjs` from `docs/fud-ledger.md`; a gate check fails when the two drift. One row per item: the claim or criticism, its status, what was done, and the evidence. Internal identifiers, times of day and team-member names are left out on purpose; the full ledger is published with the repository. -191 items. By status: Conceded, stated 52; Fixed 30; Decided 22; Fixed on a branch, pending merge 14; Answered by design 9; Answered with evidence 6; Fixed, stated 4; Closed by rule 3; Open 3; Answered by design, with a correction to our own text 1; Answered with evidence, stated 1; Answered by design for finality, Conceded for the lottery 1; Conceded, implemented, stated 1; Rule implemented and measured; launch month simulated 1; Answered by design, with the concession stated 1; Conceded, stated in the litepaper and the design doc 1; Answered with evidence at 1 block/s 1; Conceded, stated in the simulation report 1; Answered by design, with the dependency conceded. Update 7… 1; Conceded, stated in the litepaper, with the dial explained 1; Closed by spec 1; Conceded by decision, stated in the design doc 1; Answered by design, with the founder's edge conceded 1; Answered by design, with a metrics caveat 1; Closed by removal, 3 October 2026 1; Conceded, stated in the litepaper 1; Conceded, stated in the design doc 1; Measured on the live node line, and the overlay does NOT… 1; Conceded, stated in the simulation 1; Conceded in part, labelled, stated 1; Fixed in the node 1; Answered with evidence for the largest body the rules allow 1; Spec fixed 1; Fixed in the proving code 1; Fixed in the spec 1; Rule fixed 1; Rule written 1; Fixed, logged 1; Answered with evidence for the test half 1; Fixed in the node and shipped, rule not yet activated on… 1; Simulation half run 1; Answered with evidence for all four 1; Written 1; Designed 1; Fixed and confirmed 1; Rolled out 1; Conceded by decision 1; Conceded, scheduled, stated 1; Conceded, contained by rule, stated 1; Fixed on a branch and verified locally 1; Answered with evidence and stated 1; Answered with evidence for PC 2 1; Answered by design and with evidence 1; Fixed, stated; restated 1; Fixed, stated; restated further 1; Fixed in part, finding bounded, stated 1; Fixed as a genesis lever, measurement owed 1. +192 items. By status: Conceded, stated 52; Fixed 30; Decided 22; Fixed on a branch, pending merge 14; Answered by design 9; Answered with evidence 6; Fixed, stated 4; Closed by rule 3; Open 3; Spec fixed 2; Answered by design, with a correction to our own text 1; Answered with evidence, stated 1; Answered by design for finality, Conceded for the lottery 1; Conceded, implemented, stated 1; Rule implemented and measured; launch month simulated 1; Answered by design, with the concession stated 1; Conceded, stated in the litepaper and the design doc 1; Answered with evidence at 1 block/s 1; Conceded, stated in the simulation report 1; Answered by design, with the dependency conceded. Update 7… 1; Conceded, stated in the litepaper, with the dial explained 1; Closed by spec 1; Conceded by decision, stated in the design doc 1; Answered by design, with the founder's edge conceded 1; Answered by design, with a metrics caveat 1; Closed by removal, 3 October 2026 1; Conceded, stated in the litepaper 1; Conceded, stated in the design doc 1; Measured on the live node line, and the overlay does NOT… 1; Conceded, stated in the simulation 1; Conceded in part, labelled, stated 1; Fixed in the node 1; Answered with evidence for the largest body the rules allow 1; Fixed in the proving code 1; Fixed in the spec 1; Rule fixed 1; Rule written 1; Fixed, logged 1; Answered with evidence for the test half 1; Fixed in the node and shipped, rule not yet activated on… 1; Simulation half run 1; Answered with evidence for all four 1; Written 1; Designed 1; Fixed and confirmed 1; Rolled out 1; Conceded by decision 1; Conceded, scheduled, stated 1; Conceded, contained by rule, stated 1; Fixed on a branch and verified locally 1; Answered with evidence and stated 1; Answered with evidence for PC 2 1; Answered by design and with evidence 1; Fixed, stated; restated 1; Fixed, stated; restated further 1; Fixed in part, finding bounded, stated 1; Fixed as a genesis lever, measurement owed 1. | Id | Claim or criticism | Status | What was done | Evidence | |---|---|---|---|---| @@ -193,6 +193,7 @@ Generated by `tools/ledger/export-public.mjs` from `docs/fud-ledger.md`; a gate | N2 | Any peer could crash any pruned node with a sync request below its retention | Fixed | `SyncManager::antipast_hashes_between` (the IBD headers path, `RequestHeaders`) unwrapped the GHOSTDAG reads of the requested low block and of every chain block of the walk; a pruned node holds no GHOSTDAG data below… | unit test `a_sync_request_below_retention_is_an_error_not_a_panic` (a chain of six headers, the genesis's GHOSTDAG… | | P23 | An unwound transaction leaves the node's view until its sender resends it | Fixed on a branch, pending merge | a fork a commit (the P23 commit, on the merge of `ledger-fixes` and `ledger-fixes-2` onto the 0.3.11 fork tip a commit); `EvmPool::on_chain_removed` (igneum/exec/src/pool.rs) and `ExecService::requeue_unwound`… | [igneum/exec/src/pool.rs](../igneum/exec/src/pool.rs) | | AP-F8-1 | A load whose source was last written by `or`, `mul` or `mulhi` makes a cross-hash hot set | Fixed in part, finding bounded, stated | Class v4 sub-version 3 (igneum-pow a commit, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under… | [docs/analysis/ca3-v4-uniform.md](../docs/analysis/ca3-v4-uniform.md) | +| AP-F8-5 | The public specification did not describe the shipped acceptance rule (documentary; no object change) | Spec fixed | Sections 1.4.3 and 1.4.6 of `docs/spec/01-lottery-hash.md` rewritten to the shipped rule at igneum-pow a commit with every constant named and every order of operations stated (1.4.3: the two per-register states of the… | [docs/analysis/cryptanalysis/report-acceptance-rule-3.md](../docs/analysis/cryptanalysis/report-acceptance-rule-3.md) | | GF1 | A post-quantum signature scheme would need a hard fork, and every vote key is a public BLS12-381 point | Fixed | The byte costs nothing now and a fork later. | none named | | GF2 | A vote key cannot move: a miner who changes keys re-earns 30 days of weight, and so does the post-quantum migration | Fixed | The successor inherits the window, not a fresh one, so a key rotation costs no weight and the migration of GF1 is one item per key. | none named | | GF3 | A 256 MB on-chip cache makes the lottery hash 2 to 3x cheaper for the card that has it, and the cache size is a constant | Fixed as a genesis lever, measurement owed | Consumer LLC is 96 to 128 MB today and datacentre 256 MB (`chip-model-v3`, approximate), so the shortcut is a datacentre card's today and a consumer card's in a generation or two. | none named | diff --git a/docs/spec/01-lottery-hash.md b/docs/spec/01-lottery-hash.md index 1366440d1..7b03ea9bf 100644 --- a/docs/spec/01-lottery-hash.md +++ b/docs/spec/01-lottery-hash.md @@ -118,30 +118,52 @@ The version 1 lever measurement (`load_weight = 17`, `proto-metal/MEMHARD.md` se ### 1.4.3 Draw order -From the program stream of 1.3.3, in this order, whether or not an op uses a value. +Implemented (`igneum-pow/src/generator.rs`, `candidate_from_words_class`; every path the chain and the packs take). From the program stream of 1.3.3, in this order, whether or not an op uses a value. The same procedure draws every class; a class changes what a draw is used for, never whether it is taken, so the stream stays aligned across classes. (1) Load slots. Let `p[0..62] = 1..63` (instruction 0 is never a load: nothing is fresh before it). For `i` in 0..15 draw `j = i + below(63 - i)` and swap `p[i]` and `p[j]`. The load slots are `p[0..15]`, a uniform 16-subset of 1..63. -(2) For each instruction `k` in 0..63, nine draws: +(2) For each instruction `k` in 0..63, in this order: ``` roll = below(75); op = first entry of the table of 1.4.2 whose cumulative weight exceeds roll (on a load slot the roll is drawn and ignored and op = load) dst = below(8) src: on an ALU slot a = below(7); src = a + (a >= dst) - on a load slot E = the registers other than dst, in register order, that an earlier instruction of this - program has written and that no later load has used as its source (E is empty before - instruction 0); if E is not empty, a = below(|E|) and src = E[a]; - if E is empty, a = below(7) and src = a + (a >= dst), and 1.4.6 (a) rejects the program + on a load slot E = the eligible registers (below), in register order; + if E is not empty, a = below(|E|) and src = E[a]; + if E is empty, a = below(7) and src = a + (a >= dst) (the fallback; 1.4.6 (a) or (a') rejects the program) b = below(8) (src2) imm = low32(next()) imm2 = low32(next()) rot = 1 + below(31) bit = below(32) mask = 1 << below(5) +under an era (every chain program of class v3 and v4; section 1.13.1): +k_off = below(3) +o = low32(next()) AND (2^k_off - 1) (k_off and o are kept on a load slot and are (0, 0) on an ALU slot) ``` -16 slot draws plus 64 x 9: 592 draws per program. A program is fully determined by its eight seed words. A load's source holds a value written in the same iteration that no earlier load has read, so no load repeats the address of an earlier load of the same hash, across the iteration boundary included (the first form of the rule, with every register eligible at instruction 0, left the wrap open and failed 1.4.6 (a) on 36 percent of programs; census section 7.1). +Eligible registers. Two per-register states are carried through the draw, updated after every instruction is drawn: + +| State | Start | After an instruction with `dst = d`, `src = a` | Used by | +|---|---|---|---| +| `fresh[r]` | all false | `fresh[a] = false` if the op is a load; then `fresh[d] = true` | every class | +| `fresh_value[r]` | all true | the table below, then the shared-operand rule | class v4 only | + +Under class v2 and class v3, `E` is every register `r != dst` with `fresh[r]`: written by an earlier instruction of this program and not read by a later load. Under the class v4 shape (`is_class_v4_shape`: the 256-instruction shadow block over the class v3 base, the pass count and the era set aside), `E` is every register `r != dst` with `fresh[r]` and `fresh_value[r]`: fresh by dataflow as well. The dataflow table (AP-F8-1, sub-version 2; `docs/analysis/ca3-v4-uniform.md`), evaluated with the values before the instruction: + +| Op drawn | `fresh_value[d]` after it | +|---|---| +| `load` | `fresh_value[a]` (a saturated source reads one fixed word and leaves a constant) | +| `add`, `sub`, `xor`, `mad`, `shfl` | `fresh_value[d] OR fresh_value[a]` | +| `rotl`, `rotr` | `fresh_value[d]` (a rotate maps all-ones and zero to themselves) | +| `or`, `mul`, `mulhi` | false | + +The shared-operand rule (sub-version 3): after `or d |= s`, a later `xor d ^= s` or `sub d -= s` with neither `d` nor `s` written in between computes `d AND NOT s`; after `xor d ^= s`, a later `or d |= s` computes `d OR s`. Either pair is lossy though its second op would count as injecting on its own (F8's p23: `or r6 |= r4; xor r6 ^= r4`). So the draw keeps `pair[d] = (op, s)` for the last `or` or `xor` written to `d`, and when the instruction drawn is the second half of such a pair on the same `s`, `fresh_value[d]` is set false whatever the table says. Then: `pair[d]` becomes `(op, a)` if the op is `or` or `xor` and the pair rule did not fire, else none; and every `pair[r]` whose `s` equals `d` is cleared (a write to a register clears every pair that names it as the operand). The `src2` register `b` takes no part in either state. + +(3) The latency-shadow block (class v4; Counter ASIC 3.0 item 8). After the 64 base instructions, `V4_SHADOW_INSTRS = 256` further instructions are drawn from the same stream, so the base program of a class v4 seed is the class v3 program of that seed draw for draw. Every shadow slot is an ALU slot: `roll = below(75)` and the op from the table of 1.4.2, `dst = below(8)`, `a = below(7); src = a + (a >= dst)`, `b = below(8)`, `imm`, `imm2`, `rot`, `bit`, `mask` as above; under an era `below(3)` and `next()` are drawn and ignored. No shadow instruction is a load, and the shadow block takes no part in the two states above during the draw (the acceptance rule's (a') reads it, section 1.4.6.3). The block runs `V4_SHADOW_REPS = 27` times at the end of every iteration (section 1.7); the latency ladder (`docs/design/latency-ladder.md`) moves the pass count alone and never the draw. + +Draw counts: 16 slot draws plus 64 x 9 = 592 under class v2; 64 x 11 + 16 = 720 under class v3 with an era; 720 + 256 x 11 = 3,536 under class v4 with an era. A program is fully determined by its eight seed words and its class. A load's source holds a value written in the same iteration that no earlier load has read, so no load repeats the address of an earlier load of the same hash, across the iteration boundary included (the first form of the rule, with every register eligible at instruction 0, left the wrap open and failed 1.4.6 (a) on 36 percent of programs; census section 7.1). Test vector: for seed `igneum-genesis` (attempt 0, program id `bcc1248b10cc90f2`, section 1.4.6) the first eight instructions are (`proto-cuda/packs/igneum-genesis-mh/program.json`): @@ -168,21 +190,115 @@ A program is transmitted as the seed bytes, never as instructions. A node hands ### 1.4.6 Program acceptance -Implemented (`igneum-pow/src/accept.rs`, `proto-metal/main.swift`; ledger M6 Fixed). A candidate program is accepted only if all of the following hold, and every conforming implementation MUST evaluate them identically. +Implemented (`igneum-pow/src/accept.rs`; `proto-metal/main.swift` for the class v2 parts; ledger M6 Fixed, AP-F8-1 to AP-F8-3, AP-F8-5). A candidate program is accepted only if every part below that applies to its class holds, and every conforming implementation MUST evaluate them identically. The verdict is accept or reject; the reason is the first failing part in the order of this section and is reported, never relied on. -(a) For every `load`, some instruction between the previous `load` from the same source register and this one, in cyclic order over the 64 instructions, writes that register. +| Part | Name | Class v2 and v3 | Class v4 | +|---|---|---|---| +| (a) | stale load source, cyclic | yes | yes | +| (b) | an injecting write per register | yes | yes | +| (a') | dataflow freshness to a fixpoint, with the shared-operand rule | no | yes | +| (c) | the dynamic test over 2,048 hashes | yes, the 64 base instructions | yes, with the shadow block executed | +| (c') | saturated load sources | no | yes | +| (c'') | the distinct-index ratio at 2^20 evaluations | no | yes | -(b) Every register `r0..r7` is the destination of at least one `add`, `sub`, `xor`, `mad`, `shfl` or `load`. +The class v4 parts and the class v4 cap are keyed on the class v4 shape (`accept::is_class_v4_shape`): the 256-instruction shadow block over the class v3 base, the pass count and the era set aside, so a rung of the ladder keeps every rule and class v2 and v3 verdicts never move. -(c) The program is interpreted (section 1.7) for 64 units at base nonces `low32(next()) AND NOT 31` from a SplitMix64 stream seeded with `FNV-1a-64("igneum-accept/" || seed words as little-endian bytes)`, with init words `I` equal to the seed words and dataset words `dataset_elem(idx, S[0], S[1])` of `verify.rs` (the six-operation closed form of the version 0.1 packs) at 2^28 words (`idx = src AND 0x0fffffff`, a constant of this rule whatever the live dataset size) in place of the memory-hard dataset. Over those 2,048 evaluations: no register has a bit equal in every final value; no `load` site (iteration, instruction) reads one address in all 32 lanes of any unit; the number of final register values equal to 0 or 2^32 - 1 is below 164 (1 percent of 16,384); every output bit's ones count is within 136 of 1,024 (6 sigma); and the number of distinct masked dataset addresses read by one lane in one evaluation, summed over the 2,048 evaluations, exceeds 245,760 (a mean above 120 of the 128 loads). +#### 1.4.6.1 Part (a): no stale load source -Attempts. Attempt 0 of a program seed `b` (the 32-byte epoch seed, or the UTF-8 of a seed string) is the candidate drawn from `seed_words_from_bytes(b)`. If it fails, attempt `k = 1, 2, ...` is drawn from `seed_words_from_bytes(b || k_le32)`; the first accepted candidate is the program of the epoch. Measured rejection rate under this generator: 5.14 percent over 100,000 seeds (census section 7) and the 20,000-seed confirmation of `docs/bench-log.md` (4 October 2026), so the probability that 32 consecutive candidates fail is below 2^-136, and an implementation MAY treat 32 consecutive failures as a consensus fault (`MAX_ATTEMPTS`). +Over the 64 base instructions, twice in a row (so the second pass sees the state carried over the iteration boundary): keep `pending[r]`, set when a load reads `r` and cleared when any instruction writes `r` (its `dst`). A load that reads `r` while `pending[r]` is set rejects the program. The shadow block is not read here. -Program id. `FNV-1a-64("igneum-program/" || generator_le32 || seed words as little-endian bytes || attempt_le32)` with `generator = 2` under class v2 and `generator = 3` under class v3, written into every pack. Two implementations that agree on the id agree on the generator version, the seed words and the attempt. +#### 1.4.6.2 Part (b): an injecting write per register -Why the closed form: the test is then a pure function of the program (no cache, no day), costs 1.3 to 3.4 ms on one core, and the census checked on 100,000 programs that its verdict agrees with the memory-hard dataset's on all but 39 threshold-edge cases (section 7.3). What the three parts catch: (a) the empty-list fallback of 1.4.3; (b) registers that saturate to all ones (2.4 percent of candidates); (c) zero-absorbing register sets, lane-constant load sites, output bias and value-level address repeats (2.1 percent). Not in the rule, and why: a contraction as the last write (80 percent of programs) and the `or` count are too common and (c) already catches the cases that matter; the load critical path is a hash-rate question, not a weakness. +Every register `r0..r7` is the `dst` of at least one `add`, `sub`, `xor`, `mad`, `shfl` or `load` among the 64 base instructions. The shadow block is not read here. -Test vectors for the rule (`igneum-pow accept --seed ...`): +#### 1.4.6.3 Part (a'): dataflow freshness in the steady state (class v4) + +The draw of 1.4.3 keeps in-pass sources fresh; this part closes the iteration boundary (a source last written late in the previous iteration or in the shadow block, which the draw's empty-list fallback can pick: F8's p11, an `or` at 63 feeding a load at 1). One pass walks the 64 base instructions then the 256 shadow instructions, in that order (the order of one iteration), applying the `fresh_value` table and the shared-operand rule of 1.4.3 to the states `fresh_value[0..7]` and `pair[0..7]`. Start with every register fresh and no pair (the init words are a per-lane hash of the nonce). Run passes until a pass changes neither state (the state only ever falls, so at most 8 passes change it; the implementation runs at most 9 and stops at the first unchanged one). Then run one checking pass in the same order: a load whose source is not fresh at that point rejects the program (`UnfreshLoadSource`, the instruction index counted over base then shadow). + +#### 1.4.6.4 Part (c): the dynamic test + +The program is interpreted for `ACCEPT_UNITS = 64` units of 32 lanes, `ACCEPT_HASHES = 2,048` hashes, with these inputs and nothing of the live chain: + +| Input | Value | +|---|---| +| Base nonces | the first 64 values of SplitMix64 seeded with `FNV-1a-64("igneum-accept/" || seed words as little-endian bytes)`, each `low32(next()) AND NOT 31`; unit `u` runs lanes `base_u + 0 .. base_u + 31` | +| Init words `I` | the program's eight seed words (section 1.6) | +| Dataset | `dataset_elem(idx, S[0], S[1])` of `verify.rs` (the closed form of the version 0.1 packs; `S[0]`, `S[1]` are seed words 0 and 1) at `ACCEPT_DATASET_LOG2 = 28`, 2^28 words, `MASK = 0x0fffffff`, whatever the live dataset size | +| Address of a load with source value `x` | without an era `idx = x AND MASK`; under an era the form of 1.13.1 at `D = 28`: `k = min(k_off, 2)`, `y = rotl(x * M, R)`, `idx = ((y AND (MASK >> k)) OR ((o AND (2^k - 1)) << (28 - k))) AND MASK` | +| Execution | section 1.7 exactly, the shadow block included under class v4: after instruction 63 of every iteration the 256 shadow instructions run 27 times with that iteration's `sel` (sub-version 3, AP-F8-3; until it, the test ran the base instructions alone and judged a program the chain never hashes) | + +During the run: a `load` whose 32 lanes compute one address in any unit rejects the program (`LaneConstantSite`, checked at every load of every iteration and unit, the shadow block has none). After the run, over the 2,048 final register states and 2,048 outputs, in this order: + +| Check | Limit | Reject | +|---|---|---| +| Nonce-independent bits | no register has a bit equal in all 2,048 final values | `ConstantBit` | +| Saturated finals | the number of final register values equal to 0 or 2^32 - 1 is below `MAX_SATURATED = 164` (1 percent of 16,384) | `Saturated` | +| (c'), (c'') | class v4 only, section 1.4.6.5 | | +| Output bias | every output bit's ones count is within `BIAS_TOLERANCE = 136` of 1,024 (6 sigma) | `OutputBias` | +| Distinct addresses | the number of distinct `idx` values one lane read in one hash, summed over the 2,048 hashes, exceeds `MIN_DISTINCT_SUM = 245,760` (a mean above 120 of the 128 loads; `loads x 2,048 x 120 / 128` for a class with another load count) | `DistinctAddresses` | + +#### 1.4.6.5 Parts (c') and (c''): the load sources (class v4) + +A load site is a load's ordinal within the iteration, 0 to 15, in instruction order. Both parts read the same interpreter and the same nonce stream as (c). + +(c') Saturated sources. Over the 64 units of (c), every site is evaluated 64 x 32 x 8 = 16,384 times. A site whose source value `x` was 0 or 2^32 - 1 in `MAX_SATURATED = 164` or more of them rejects the program (`SaturatedSource`, the first such site in order). A saturated source reads one fixed word whatever delivered the saturation; the draw's rule removes the writers it can see and this count catches every delivery. + +(c'') The distinct-index ratio. The one test that runs past the 64 units: `ACCEPT_UNITS_DISTINCT_V4 = 4,096` units, the first 4,096 base nonces of the same stream (the 64 of (c) are its first 64), so every site is evaluated `N = 2^20` times. For each site `s`, `d_s` is the number of distinct `idx` values it computed over those evaluations, `W_s = 2^28 >> min(k_off_s, 2)` is its window in words, and the expectation of a uniform source on that window is `E_s = N - N^2 / (2 W_s)` (an integer at these constants: 2^20 - 2^11, 2^20 - 2^12, 2^20 - 2^13). The site's ratio `d_s / E_s` must reach `MIN_DISTINCT_RATIO_V4 = 0.98`; the first site under it, in order, rejects the program (`LowEntropySite`). The implementation compares in f64; the integer comparison `50 d_s >= 49 E_s` gives the same verdict for every value of `d_s` at these constants (the margin is at least 0.32 of a count; adv-accept-3 section 6.1), and an implementation MAY use it. The floor sits in a measured gap: the accepted population's minimum is 0.983 to 0.989 and the rejected population's maximum 0.966 over 20,275 draws of two lanes, so a floor anywhere in 0.967 to 0.988 gives the same verdicts on every program seen (adv-accept-3 section 6.4). `MAX_SOURCE_REPEAT_V4 = 8` exists in the file and is not part of the rule. + +What the parts catch: (a) the empty-list fallback of 1.4.3; (b) registers that saturate to all ones (2.4 percent of class v2 candidates); (c) zero-absorbing register sets, lane-constant load sites, output bias and value-level address repeats (2.1 percent); (a') the cross-hash hot set of a load fed by `or`, `mul` or `mulhi` through the iteration boundary (AP-F8-1); (c') the same set delivered any other way; (c'') a low-entropy index band the lineage rules cannot see (F8's p23, p18, p19, p15, p56). Why (c) uses the closed form: the test is a pure function of the program (no cache, no day), costs about 3 ms on one core for the 64 units and 2.8 s with (c'') on the chosen candidate, and the census checked on 100,000 class v2 programs that its verdict agrees with the memory-hard dataset's on all but 39 threshold-edge cases (section 7.3). Not in the rule, and why: a contraction as the last write (80 percent of programs) and the `or` count are too common and (c) already catches the cases that matter; the load critical path is a hash-rate question, not a weakness; a 2^24 stage of (c'') does not separate the open F8 tail (p4, p8, p10, p34 read the clean seeds' values there; ledger AP-F8-1). + +#### 1.4.6.6 Attempts, the cap, the last resort and the program id + +Attempts. Attempt 0 of a program seed `b` (the 32-byte epoch seed, or the UTF-8 of a seed string) is the candidate drawn from `seed_words_from_bytes(b)`. If it is rejected, attempt `k = 1, 2, ...` is drawn from `seed_words_from_bytes(b || k_le32)`; the first accepted candidate is the program of the epoch. The cap is `MAX_ATTEMPTS = 32` under class v2 and v3 and `MAX_ATTEMPTS_V4 = 256` under the class v4 shape (`max_attempts_for`). + +| Rate, per candidate | Class v2 (census, 100,000 seeds, 4 October 2026) | Class v4 sub-version 3 (adv-accept-3, 3,009,928 candidates of 10^6 seeds and 62,240 of 19,975 full-rule seeds, 7 October 2026) | +|---|---|---| +| Accepted | 0.9486 | 0.323 | +| (a') | not a part | 0.568 | +| (a) | | 0.079 | +| (b) | | 0.022 | +| (c), (c'), (c'') together | | about 0.009 | +| Seeds reaching the cap | 0 of 100,000 | 0 of 1,019,975 | +| Probability a seed reaches the cap | below 2^-136 | 0.677^256, about 4.6 x 10^-44 | + +Under class v2 and v3 an implementation MAY treat the cap as a consensus fault. Under class v4 the draw is total (AP-F8-2): a seed whose 256 candidates are all rejected takes the last-resort program, the candidate at attempt 256 with every `or`, `mul` and `mulhi` of its base program and its shadow block rewritten to `xor` (`dst`, `src` and every other field kept), handed to the chain as drawn with no further check. With no lossy op left, (a') holds by construction. The rest of the rule is not checked on it, and does not hold on every seed: on 3,000 seeds the real rule rejects the last-resort program of 271 (251 by (a), the fallback-drawn load source the rewrite does not touch; 14 by (b); 6 by (c)'s distinct sum), so sub-version 3's last resort is stated here as unreachable and unverified (adv-accept-3 finding 1, ledger AP-F8-3); class v5 carries the verified construction (section 1.4.7). + +Program id. `FNV-1a-64("igneum-program/" || generator_le32 || seed words as little-endian bytes || attempt_le32 || suffix)` with `generator = 2` under class v2 and `generator = 3` under class v3 (no suffix), and `generator = 4` under class v4 with the suffix `"sub/" || sub_version_le16` (the class v4 stream's sub-version, `PROGRAM_SUBVERSION_V4 = 3` since 7 October 2026: `IGNEUM_PROGRAM_SUBVERSION` in program.h, `"sub_version"` in program.json; without the suffix Devnet 3's epoch-0 id reads 30956569d8f3d8d7 where the chain and the packs say fce15bf61030be57); class v5 is `generator = 5` with no suffix (section 1.4.7). A class v4 program at rung 0 of the ladder uses that form; a program of any other class or rung (a read-width, scratch, mixer, derivation, era, shadow or hot rung other than class v4's rung 0) uses the tag `"igneum-program-rw/"` and appends the class's fields after `attempt_le32` (`generator::program_id_class`). Every pack prints its own derivation as `program_id_derivation` in program.json, built from the byte recipe the id is hashed from, and a worker MUST refuse a pack whose generator version, class, era seed or sub-version is not its own (`packcheck.rs`). Two implementations that agree on the id agree on the generator version, the seed words, the attempt and, under class v4, the sub-version. + +Constants of the shipped rule. One row per constant the rule depends on, the value as the crate has it; a reader implementing from this text uses these and nothing else, and the crate's own test reads this table back against its `pub const` items. + +| Constant | Value | Where | +|---|---|---| +| generator::INSTR_COUNT | 64 | instructions per base program | +| generator::LOAD_SLOTS | 16 | load slots per program | +| generator::ITERATIONS | 8 | iterations per hash | +| generator::GENERATOR_VERSION_V4 | 4 | the class v4 generator | +| generator::PROGRAM_SUBVERSION_V4 | 3 | the id suffix "sub/" || le16 | +| generator::MAX_ATTEMPTS | 32 | the cap under class v2 and v3 | +| generator::MAX_ATTEMPTS_V4 | 256 | the cap under the class v4 shape | +| generator::V4_SHADOW_INSTRS | 256 | shadow instructions per program | +| generator::V4_SHADOW_REPS | 27 | shadow passes per iteration at rung 0 | +| accept::ACCEPT_UNITS | 64 | (c) units | +| accept::ACCEPT_HASHES | 2048 | (c) hashes | +| accept::ACCEPT_DATASET_LOG2 | 28 | log2 of the closed-form dataset | +| accept::MAX_SATURATED | 164 | (c) saturated finals and (c') saturated sources, exclusive limit | +| accept::BIAS_TOLERANCE | 136 | (c) output bias, inclusive | +| accept::MIN_DISTINCT_SUM | 245760 | (c) distinct-address sum, exclusive | +| accept::ACCEPT_UNITS_DISTINCT_V4 | 4096 | (c'') units, 2^20 evaluations per site | +| accept::MIN_DISTINCT_RATIO_V4 | 0.98 | (c'') ratio floor, inclusive | + +Pinned program ids. A reader who follows 1.4.3 and this section reproduces these from the seed, the attempt and the sub-version above; the crate's test derives each from the recipe and from the printed derivation text. + +| Seed | Attempt | Id | Note | +|---|---|---|---| +| edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 | 1 | a785001687d8688a | the shared devnet's epoch-0 seed under class v4 sub-version 3 (generator 4, the suffix); attempt 0 is rejected under class v4 | +| edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 | 0 | 73bcbfe8ccf988f1 | the same seed under class v3 (generator 3, no suffix): the class v3 control | +| edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 | 1 | c120d7963abdcd96 | must differ: generator 4 without the suffix, the stream of 6 October 2026 (sub-version 0, never stamped) | +| edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 | 1 | 1a4230699a6b9c60 | must differ: sub-version 1, the stream 0.3.20 and 0.3.21 shipped as object byte 5 | +| edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 | 1 | a788661687db4bb3 | must differ: sub-version 2, never shipped | +| 4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925 | 0 | fce15bf61030be57 | Devnet 3's epoch-0 seed (its genesis hash) under class v4 sub-version 3, accepted at attempt 0; 30956569d8f3d8d7 without the suffix | + +Test vectors for the class v2 rule (`igneum-pow accept --seed ...`): | Seed | Attempt 0 | Attempt 1 | |---|---|---| @@ -192,7 +308,7 @@ Test vectors for the rule (`igneum-pow accept --seed ...`): | `igneum-census-2026-10-03/37` | rejected, (c) 245,230 distinct addresses (mean 119.74) | accepted, `947705cc4eb1df0a` | | `igneum-census-2026-10-03/51` | rejected, (b) r4 has no injecting write | accepted, `9869afcc028bf9f1` | -The Rust crate and the Swift prototype derive identical instruction lists and identical 96-vector sets on all five seeds (`docs/bench-log.md`, 4 October 2026). +The Rust crate and the Swift prototype derive identical instruction lists and identical 96-vector sets on all five seeds (`docs/bench-log.md`, 4 October 2026). For the class v4 rule, a second implementation written from the module table of `accept.rs` and this section agreed with the crate on 5,748 of 5,748 attempt verdicts over 1,792 seeds, part for part, with its known-failed control fired (adv-accept-3 section 6.4); an implementation written from the text of this section as it stood before 7 October 2026 mined a different program on 264 of 400 epochs (adv-accept-3 section 6.2, ledger AP-F8-5), which is why every constant and every order of operations is now stated here. ## 1.5 Fixed memory footprint @@ -244,6 +360,8 @@ The output folding rotations (7, 14, 21; 9, 18, 27) are Implemented, prototype v `shfl` makes the 32 lanes of a unit interdependent: the hash of one nonce is defined only as a member of its aligned group of 32 (section 1.9). +Class v4 (Counter ASIC 3.0, the latency shadow): after instruction 63 of every iteration, and before the next iteration samples `sel`, the program's 256-instruction shadow block (section 1.4.3 (3)) is applied `V4_SHADOW_REPS` times with the iteration's `sel`, 27 at rung 0 of the latency ladder, so one hash runs 64 x 8 base instructions and 256 x 27 x 8 = 55,296 shadow instructions. The shadow holds no load. The acceptance interpreter of 1.4.6.4 runs the same block the same way (sub-version 3). The ladder (`docs/design/latency-ladder.md`) moves the pass count by miner signal and nothing else in this section. + ## 1.8 The memory-hard dataset Implemented (`memhard.rs`), construction and measurements in `proto-metal/MEMHARD.md`. Every constant below is a prototype value, to be fixed at gate 1, unless marked Definition. What fixes them is the shortcut-ratio and time-memory trade-off measurement on NVIDIA and AMD discrete cards (section 1.16 items 2 and 3) and an external review of the primitives (ledger M7). @@ -321,6 +439,8 @@ item(t) = s Eight dependent cache reads (`ITEM_ROUNDS = 8`, prototype value): the address of read `r` depends on every earlier read. Nine mixer applications under program class v2. +Under class v5 the item's init words carry the leaf of section 1.8.6. + Program class v3 (Counter ASIC 2.0, decided 5 October 2026, delegated; the founder confirms for the public testnet genesis) applies the mixer `m = 8` times per round with distinct round keys (`LoadClass::mixer_mult`; `docs/plans/mixer-x4.md` section 2), the eight dependent reads unchanged: ``` @@ -441,7 +561,7 @@ The era seed `E_n` is the 32-byte output of the 1-hour VDF of section 4.4 (in th `epoch_len` is the one era-table parameter set by miners rather than by the draw: 90% of blue blocks over a 7-day window carrying the same ladder index (3 bits of the header version, encoding Open in section 5.8) sets that length from the first day boundary at least 2 days after the window closes (section 5.7). It is not a code upgrade: the rule, the ladder and the window are genesis constants, and the chain carries no release. The era stream consumes its draw so that a future draw of this parameter changes no other parameter's value. The threat it answers is a per-program hard datapath (an FPGA fleet: 42 to 160 minutes per compile on a mid-size part, PRflow, FPT 2019, hours on large parts; at 600 s nothing it compiles ever runs); it does not answer a programmable chip, which the other layers answer. The floor 600 is set by the slowest compile-ahead measured (the Metal variant race, 38 s on the M5 Max, 6.3% of a 600-s epoch and inside the 600-s seed window; `docs/plans/epoch-length.md` section 6). -The table layout and the working-set window (Counter ASIC 2.0 layers 4 and 8, decided IN on 5 October 2026, delegated: the six-era hash-rate spread is 1.3% on the RTX 5090, 3.2% on the RX 9070 XT and 0.8% on the M5 Max, under the 5% rule; `docs/plans/era-layout.md`) are drawn under program class v3 by a second stream `S` seeded with words 0 and 1 of `seed_words_from_bytes("igneum-era/" || E_n)` (the index is not in the preimage: `E_n` commits to `n` through the VDF input), seven draws in this order whether or not a value is used: +The table layout and the working-set window (Counter ASIC 2.0 layers 4 and 8, decided IN on 5 October 2026, delegated: the six-era hash-rate spread is 1.3% on the RTX 5090, 3.2% on the RX 9070 XT and 0.8% on the M5 Max, under the 5% rule; `docs/plans/era-layout.md`) are drawn under program class v3 by a second stream `S` seeded with words 0 and 1 of `seed_words_from_bytes("igneum-era/" || E_n)` (the index is not in the preimage: `E_n` commits to `n` through the VDF input), nine draws in this order whether or not a value is used (the eighth and ninth, `epoch_len` and the latency ladder, are consumed and not read: both are set by miner signal, and consuming their slots means a later use of either changes no other draw; `generator::era_draw`): 1. `W = allowed[below(|allowed|)]`: the width in words of every dataset load of the era, from the genesis-fixed set `allowed`; the set is `{1}` (4 bytes, the read-width decision of 5 October 2026), so the draw is consumed and the width pinned. 2. `M = low32(next()) OR 1`: the stride multiplier, odd, so `x -> x * M` is a bijection. From 638eafdfd1fff53be306dc07101d06a6499948f7 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:26:19 +0000 Subject: [PATCH 05/28] Counter ASIC 3.0 status: the record landed (135489b7), adv-accept-3 closed with AP-F8-3 and the kits merge, the spec split and the constants check, the era-draw mechanism from adv-cache-2 and its disposition, the attempts census on the frozen rule, the PC 1 queue and the Intel job's move to PC 2, the hash lane's landing Co-Authored-By: Claude Fable 5.1 --- docs/plans/counter-asic-3-status.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 79a0de271..76c9d7aa1 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,7 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule From cba4c8c7be9d2a02038ba26ccc50b51cba1c8a45 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:35:40 +0000 Subject: [PATCH 06/28] release 0.3.22 section 16: the v5 floor re-cut to 32,400 (c9e385eb), the move minute's gate on an F9/F1 interim line, the Devnet 3 row wording Co-Authored-By: Claude Fable 5.1 --- docs/plans/release-0.3.22.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/plans/release-0.3.22.md b/docs/plans/release-0.3.22.md index bf2dcd568..71a4018ea 100644 --- a/docs/plans/release-0.3.22.md +++ b/docs/plans/release-0.3.22.md @@ -154,3 +154,11 @@ The 0.3.23 node's heights move Devnet 3's digest to ba75bf6f, and the one-box-at **The node pin: release-0.3.24-node = 47b9b229** (774f16c9's v5 object plus the testnet re-cut 34892a36), fast-forwarded on both mirrors at 23:01:05 BST after the Devnet 3 canary set read clean on its own binary (igneumd 6bc18ac2, igneum-miner b55b60c7, /srv/artefacts/0324-tn-47b9b229/node-lane; digest 4a284b1d with no file, object version 6 stamped into the headers, the override refused, shutdown 725 ms, two empty nodes handshaking, the shared-devnet dialler and a 2720d8d2 node refused both ways); the pairing igneum-pow class-v5 1c420786. **The hash-side board (the Counter lane, 23:0x BST):** F8 on 1c420786 PASS at 23:03 BST (64 seeds at 2^24 on the chain path with the v5 dataset, the pairing bit for bit, 61 of 64 under 1.2x, the three over inside the named residue p4/p8/p10, p10 1.5047x the worst), F4 PASS (byte-identical to v4's census), the (c''') floor measured, the kit e6c088bb byte-identical to the tip, the fingerprint 82b19cbde8557ea5 on three platforms (AMD on PC 1's queue, Intel deferred). **Main's ruling on the clock:** the cut's gates are F4, F8 and the consensus rerun, all green, so the cut runs now (the pin, the pairs, the hive, the staging, no gap); F9 (10^5 exhaustion) and F1 (10^5 redundancy), running on build-1 as strengthening lines, gate the PUBLISH and the one-minute move: the move file publishes at at_epoch 0 for the fetches, and its minute is named only after both read PASS; anything but PASS and the staging stays staged, main hears first. The 28,800 floor holds for a publish by 23:52 BST (the node lane re-reads dn3-g1 at 23:30 BST and on the minute); past it the constant re-cuts to 32,400 and the pairs with it. **The app tree: release-0.3.24 = 1a58f384 on the mirror** (the version bump first, rule 15 green at six places; dash-24 19ab2a87; pool-finish-22 05f86a7f with dn3-split-read.mjs as the pool lane's; igneum-pow and proto-cuda/packs-ca3-v5 from 1c420786, which the Mac node pair build on 774f16c9 needed (StateStream, StateLeaves, ProgramClass::V5) and the build-server lane's --ship seed class the same, its overlay re-pointed; publish-public.sh's interface fix 80a4cfb1; power-helper-24 f1395775 and b9a72b9b (the engine never runs an elevated helper of its own on Windows, the task registered S4U with the right power-helper-task@unattended, the helper's start facts and exit reasons); the Windows pin to 47b9b229); app gate GREEN on build-1 (289 + 35 + 8), UI 87, pre-push 60. The Mac node pair builds on 47b9b229 under the lock from 23:06 BST; the 0.3.24 host is a fresh PC 1 build (version.h 0.3.24) in a slot after the hash lane's family run; the pairs, the hive with three kit zips (the two sub-version 3 and the v5 kit) and the Windows chain on the build-server lane. The PC 1 helper reading (the update-return lane, 23:01 BST): the elevated helper on PC 1 is alive and blind, not dead: the 0.3.20 helper's pre-0.3.21 skip rule skipped every 2-line rewrite as present at start; Stop-ScheduledTask writes no exit line; 0x800710E0 is the scheduler's record of a Start meeting a running instance; no crash; the 0.3.23 kit carries the effective_skip fix and PC 1 answers again once that kit replaces its exe. + +## 16. The floor re-cut to 32,400 and the move minute's gate (23:3x BST) + +**Main's ruling (23:31 BST):** the 28,800 floor is lost to the clock (the pairs from 47b9b229, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST), so the constant re-cuts now rather than at 23:52: **release-0.3.24-node = c9e385eb** (23:32:09 BST; 47b9b229 with program_class_v5_activation_daa 32,400, epoch 9, everything else unchanged: byte 6, the window 86,400, the heights, the pool split at never, chain id 4463 below and 4464 from the floor, the testnet re-cut, pairing 1c420786); its gate set runs from 23:32:12 BST (the build at gate priority on build-1, consensus at gate priority and the five other suites on build-2, the Devnet 3 canary with the mixed-version step, the testnet canary, the fast-time pair); 774f16c9 and 47b9b229 are void as pins and their pairs with them. From dn3-g1's read at 23:30:17 BST (DAA 20,268 at 1.0 DAA/s): the floor lands about 02:52 BST on 8 October and holds for a move minute up to a publish at DAA 25,200, about 00:52 BST. After the digest move the node lane's DAA reads come from a 0.3.24 node the fleet names (build-1's 0.3.22 seed falls off at the move). The app side: release-0.3.24 = 25528e4b (the Windows pin to c9e385eb on 9854030b's crate); the Mac node pair and DMG rebuilt under the lock on c9e385eb from 23:34 BST. + +**The move minute's gate (main, 23:36 BST):** F9's full 10^5 completes about 00:40 BST, too close to the 00:52 ceiling, so the minute is named on the new pin, the last FETCHED plus ten, and an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, 0 exhausted, max attempt 25; geometric at 0.68, the same shape as sub-version 3's 10^6; exhaustion unreachable by construction with the 256 cap and the deterministic last resort); any non-zero before the minute holds the move and main hears first; the full 10^5 lands as the record line after. + +**The Devnet 3 row for the site and this record (main's wording through the Counter lane):** a 0.3.23 node that has not updated falls off at the digest move minute, not at the crossing; the crossing is the class change on nodes already past the digest. Served as: "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST", the minute filled when the fleet names it. From 2710410184ae3b03484db89d48a027b2c9054883 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:34:31 +0000 Subject: [PATCH 07/28] Counter ASIC 3.0 status: the per-load fix (2f718001) and the CA4 file's era split and Apple tile cost, the limit-163 fix branch, the floor re-cut to 32,400 and main's row wording, the era reading on the floor (0 of 29 refused, two instruments two classes), F4 PASS on class v5 Co-Authored-By: Claude Fable 5.1 --- docs/plans/counter-asic-3-status.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 76c9d7aa1..294d019e9 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,7 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule From 08b8316a36d0f4422e65990de7a0ff1e8b269b4a Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:37:41 +0000 Subject: [PATCH 08/28] Ledger AP-F8-1: the public sentence on what the class v5 floor refuses and what it does not reach (eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test), with the two-instrument reading and the AP-F8-6 pointer Co-Authored-By: Claude Fable 5.1 --- docs/fud-ledger.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/fud-ledger.md b/docs/fud-ledger.md index 09d7d35df..00339a5e7 100644 --- a/docs/fud-ledger.md +++ b/docs/fud-ledger.md @@ -2503,7 +2503,7 @@ Owed (recorded, not run, by the founder's word): G2 (the CPU verifier on 1,024 h Owed (recorded, not run, by the founder's word): G2 (the CPU verifier on 1,024 hashes per card) on the amended stream; G3 (the Metal fuzz, edge, stats and determinism runs) on the amended stream; the hash-rate ladder re-measure on the M5 Max and the RTX 5090 (the amendment changes the base program's source draws, not the op mix or the load count, so the latency-bound rows of `docs/analysis/latency-shadow-2026-10-06.md` are expected to hold within their spread; unmeasured); AMD (the RX 9070 XT, PC 1); the 2019-class verifier core (O-1.14); F8's phase E (the 64-seed dynamic census) on the amended stream, which is the attack-pass lane's and the test of the per-op table. The row reads FIXED-AND-PASSED only after phase E passes against the amended class. -Status: Fixed in part, finding bounded, stated (7 October 2026, night, the Counter ASIC lane's words): class v4 sub-version 3 (igneum-pow 017e7037, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under 1.2x with the four-seed tail accepted by the coordinator as the window model's unattributed residue (no chip consequence); the pass then attributed the class by value (eight live hot sets at 1.54x to 2.24x in the lowest 30 of 29,032 accepted programs, each about 1 MB of items at 0.3 percent of reads, 1.002x to a chip); class v5 (1c420786, frozen 21:53 UK) carries the fix as rule (c'''), the per-site distinct-index floor at 0.995 on the state flag (its census refuses 2.435 percent of accepted programs; seven of seven live hot sets refused at 0.9821 to 0.9919; the eighth's ratio owed tonight), with a named residual (three mild shadow-block-written concentrations at 0.9992 to 0.9997, about 1.0004x, a value-level test in the next class); the record is `docs/plans/counter-asic-3-status.md` section 7c and the class v5 design's section 14. The eighth live hot set (seed 122960, id 4be7393ab6c84802, the deepest found: X_f +0.111 percent, 1.54x the window model, its hottest item at 475,616 reads from an all-ones source) reads minimum site 12 at 0.9824 at the acceptance's own 2^20 sample (live 0.9822), refused by class v5's (c''') floor at 0.995; so the floor refuses eight of eight live hot sets by X_f at or above f found in the tail of 88,051 accepted programs (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; what it misses stays the three mild shadow-block-written concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x to a chip, the value-level test in the next class (22:41 BST; the logs under `docs/analysis/cryptanalysis/logs/adv-accept/` on branch adv-accept; the v5 design's section 14). The RTX 5080 grid's knee is not in tonight; X37 keeps the 5080's stock premium only. +Status: Fixed in part, finding bounded, stated (7 October 2026, night, the Counter ASIC lane's words): class v4 sub-version 3 (igneum-pow 017e7037, the audit-freeze tag) is frozen with the dataflow rule, the shared-operand rule, the 0.98 ratio and the total draw; the in-house pass's F8 re-gate reads 60 of 64 seeds under 1.2x with the four-seed tail accepted by the coordinator as the window model's unattributed residue (no chip consequence); the pass then attributed the class by value (eight live hot sets at 1.54x to 2.24x in the lowest 30 of 29,032 accepted programs, each about 1 MB of items at 0.3 percent of reads, 1.002x to a chip); class v5 (1c420786, frozen 21:53 UK) carries the fix as rule (c'''), the per-site distinct-index floor at 0.995 on the state flag (its census refuses 2.435 percent of accepted programs; seven of seven live hot sets refused at 0.9821 to 0.9919; the eighth's ratio owed tonight), with a named residual (three mild shadow-block-written concentrations at 0.9992 to 0.9997, about 1.0004x, a value-level test in the next class); the record is `docs/plans/counter-asic-3-status.md` section 7c and the class v5 design's section 14. The eighth live hot set (seed 122960, id 4be7393ab6c84802, the deepest found: X_f +0.111 percent, 1.54x the window model, its hottest item at 475,616 reads from an all-ones source) reads minimum site 12 at 0.9824 at the acceptance's own 2^20 sample (live 0.9822), refused by class v5's (c''') floor at 0.995; so the floor refuses eight of eight live hot sets by X_f at or above f found in the tail of 88,051 accepted programs (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; what it misses stays the three mild shadow-block-written concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x to a chip, the value-level test in the next class (22:41 BST; the logs under `docs/analysis/cryptanalysis/logs/adv-accept/` on branch adv-accept; the v5 design's section 14). The public sentence (the coordinator's wording, 7 October 2026, night): eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test. The reason, read by the in-house pass (adv-cache-2) and the class v5 lane together: the distinct-index count at 2^20 sees concentration on few word indices (the hot sets put about 3 percent of a site's reads on 512 indices, so the ratio falls to 0.98 to 0.992) and not a diffuse excess over the top 0.1 percent of items (16,384 items), which is what the era-stride low-bit law produces (13 of 27 drawn-era programs carry a site over 1.04x, 8 over 1.2x, worst 1.75x; 0 of 29 refused at the 2^20 sample, minimum sites 0.9965 to 1.0000); its chip value is about 1.0024x at the worst site read, under this row's bound by an order; the row for it is AP-F8-6. The RTX 5080 grid's knee is not in tonight; X37 keeps the 5080's stock premium only. ## Genesis forward-compatibility entries (7 October 2026, mission item 8, branch `genesis-forward`) From cc3548f55f69b53c964a8935f3cd18237212e062 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:41:59 +0000 Subject: [PATCH 09/28] Counter ASIC 3.0 status: main's public sentence on the floor and where it lives, adv-mixer-2 closed, the hash lane's branch on master (c8d15d9d) Co-Authored-By: Claude Fable 5.1 --- docs/plans/counter-asic-3-status.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index 294d019e9..74f6295fa 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,7 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule From 621e8add4099fdf49948770b05f0e583697b3d92 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Wed, 7 Oct 2026 22:43:44 +0000 Subject: [PATCH 10/28] Spec read-back and the ledger page (AP-F8-5, 7 October 2026 night) Spec 01 1.4.6: the constants table gains ACCEPT_TAG, LANES, the (c'') window-cap literal and the first-refused reading of MAX_SATURATED. tools/ci/spec-constants-check.mjs joins the gate: every "Constant | Value | Where" table of spec 01 against the crate's pub const items (an expression over constants evaluated, a byte string compared, a pending row skipped while the constant is absent), known-failed fixture first. igneum-pow/tests/spec_readback.rs derives every pinned id of the "Seed | Attempt | Id | Note" table through the crate and draws each class v4 row with its era to the stated attempt; a must-differ row asserts another id (box suite on the branch: 64 + 7 + 4 + 19 + 2 + 7 + 2 passed, build-remote rc 0). tools/ledger-page.mjs: both entry heading forms render (M1 and AP-F8-1; the single-letter form dropped every in-house pass row from /ledger), the pass gets its own section, a known-failed self-test in the gate. docs/fud-ledger.md drops the USD 50,000 prize clauses and "paid independent cryptanalysis" (decision item 1 of 6 October: no bounty; the in-house rule of 7 October), so the regenerated site/ledger.html carries neither. checks.txt regenerated (73 checks). Co-Authored-By: Claude Fable 5.1 --- docs/fud-ledger.md | 4 +- docs/spec/01-lottery-hash.md | 9 +- igneum-pow/tests/spec_readback.rs | 115 ++++++++++++++++++ site/ledger.html | 191 +++++++++++++++++------------- tools/ci/checks.txt | 2 + tools/ci/pre-push.sh | 2 + tools/ci/spec-constants-check.mjs | 138 +++++++++++++++++++++ tools/ledger-page.mjs | 49 +++++--- 8 files changed, 411 insertions(+), 99 deletions(-) create mode 100644 igneum-pow/tests/spec_readback.rs create mode 100644 tools/ci/spec-constants-check.mjs diff --git a/docs/fud-ledger.md b/docs/fud-ledger.md index c95f3e846..7eabfeb1d 100644 --- a/docs/fud-ledger.md +++ b/docs/fud-ledger.md @@ -29,7 +29,7 @@ Evidence locations referenced below: `docs/bench-log.md`, `proto-metal/TESTS.md` ### M1. The program space is tiny "Eleven integer ops, 64 instructions, 8 iterations, a splitmix register init. That is not RandomX. RandomX leans on a superscalar out-of-order CPU with floating point and branches. Yours is a sea of 32-bit ALUs and a memory bus. A chip for that is a weekend." -Status: Decided (6 October 2026, 17:35 UTC, by the owner; decisions item 1, corrected): no standing bounty. A team with a real 2x chip earns more by mining than any bounty pays, so a device bounty attracts nobody; the tiers announced at 17:25 UTC are withdrawn. The claim "under 2x" is backed by the paid independent cryptanalysis (the Monero route: four paid reviews, no bounty) and by the public benchmark with M22's metrics. Optional, the owner's call later: one cryptanalysis prize of USD 50,000 for a published 2x or better shortcut in the mixer, the chained cache or the acceptance rule, escrowed before it is named; nothing public before that. The claim stays a target until the audit and the benchmark have reported. Was: Open, program space counted, the claim stands as a target (5 October 2026, evening sweep). Was: Open, experiment scheduled. Sweep (5 October 2026): nothing runnable; the bounty, the public benchmark and a chip design are M22's decisions and hardware. The nearest number stays M16's arithmetic. +Status: Decided (6 October 2026, 17:35 UTC, by the owner; decisions item 1, corrected): no standing bounty. A team with a real 2x chip earns more by mining than any bounty pays, so a device bounty attracts nobody; the tiers announced at 17:25 UTC are withdrawn. The claim "under 2x" is backed by the in-house adversarial pass and by the public benchmark with M22's metrics. The claim stays a target until the audit and the benchmark have reported. Was: Open, program space counted, the claim stands as a target (5 October 2026, evening sweep). Was: Open, experiment scheduled. Sweep (5 October 2026): nothing runnable; the bounty, the public benchmark and a chip design are M22's decisions and hardware. The nearest number stays M16's arithmetic. Decision owner: the founder, decided 6 October 2026 (`docs/plans/ledger-decisions.md`, outcomes section). Sweep (5 October 2026, evening): the program space, swept as arithmetic from the version 2 generator (`igneum-pow/src/generator.rs`: 16 load slots as a uniform 16-subset of instructions 1 to 63, then nine draws per instruction, 592 draws per program; 10 non-load operations with weights 12/10/8/8/8/7/6/6/6/4; 8 registers; a 31-way rotation, a 32-way bit and a 5-way mask per instruction; two 32-bit immediates). Counting choices: the slot subset is 48.4 bits; the operation draw carries 3.26 bits of entropy (of log2 10 = 3.32); operations and registers alone give about 770 bits per program; with the rotation, bit and mask fields about 1,550 bits; with the immediates about 5,650 bits, all capped by the 256-bit seed, so the space a chip has to serve is 2^256 distinct programs drawn from a structure of about 2^1550 shapes, and the critic is right that it is a small instruction set: 12 operations, 8 registers, no floating point, no branches, by design (vendor-identical rounding). What the sweep adds to the ledger's answer is the number that matters for a fixed-function design, the spread a chip must absorb: under generator version 2 every accepted program does 120 to 128 distinct loads per hash (median 128.00, 20,000-program census), so the per-program hash-rate spread on a memory-bound device is the 1.10x residual the census measured, not the 2.7x of version 1; the chip's advantage therefore cannot come from the program (it is one fixed memory-bound shape) and must come from the memory system or from the recompute route, which is M16's cost model (`docs/analysis/m16-recompute-attacker-2026-10-05.md`: 1.5x to 2.4x at equal integer budget before any fixed-function factor, 3x to 6x with one, and the mixer-cost lever that cuts it below 1x). The experiment that closes M1 is unchanged: the bounty and the public benchmark (M22, decision owner the founder). @@ -1587,7 +1587,7 @@ Run (5 October 2026, night): `python3 sim/difficulty/record_report.py devnet-202 ### M22. The ASIC challenge has no scoring rules, and 2x is not the economic line "Your bounty says 'beats a GPU by more than 2x'. Per what? Hashes per second, per joule, per dollar, on the average program or the worst hour? A chip at 1.6x with half the capital cost wins. And nobody has published eligible hardware, funding or a judge." -Status: Decided (6 October 2026, 17:35 UTC, by the owner; decisions item 1, corrected): no bounty, so no bounty terms; M22's metrics (hashes per second and per joule per program over at least 100 epochs as a distribution, capital cost per unit of hash rate at a stated volume, the longevity term, the shortcut classes scored separately) become the public benchmark's scoring rules and the brief of the paid cryptanalysis; the optional USD 50,000 cryptanalysis prize, if ever set, is escrowed before it is named. Was: Open, decision for the founder (terms, judge and funding) and experiment scheduled (extends O-1.17). Sweep (5 October 2026): nothing runnable; the terms, judge and funding are the founder's decision. +Status: Decided (6 October 2026, 17:35 UTC, by the owner; decisions item 1, corrected): no bounty, so no bounty terms; M22's metrics (hashes per second and per joule per program over at least 100 epochs as a distribution, capital cost per unit of hash rate at a stated volume, the longevity term, the shortcut classes scored separately) become the public benchmark's scoring rules and the brief of the in-house adversarial pass. Was: Open, decision for the founder (terms, judge and funding) and experiment scheduled (extends O-1.17). Sweep (5 October 2026): nothing runnable; the terms, judge and funding are the founder's decision. Decision owner: the founder, decided 6 October 2026 (`docs/plans/ledger-decisions.md`, outcomes section). Answer: Correct. M1 and O-1.17 name a bounty for "more than 2x" without a metric, a judge or a fund, and 2x is a design target for the hash, not an economic threshold: a chip at 1.5x per joule and 3x per dollar of capital is an economic ASIC whatever the hash-rate ratio says. The scoring rules go out with the January 2027 benchmark: hashes per second and per joule measured per program over a published set of at least 100 epochs, reported as a distribution (worst decile, median), never as one average; capital cost per unit of hash rate at a stated volume; a longevity term against the instruction-family reserve and the dataset growth of spec 1.13; and the shortcut classes (recomputation, partial storage, weak-program selection) scored separately. Eligible hardware assumptions, the judge, the reward and the payer are the founder's decisions (fud-fixes row 50: the payer is the entity). The supportable public claim until a design has been scored: across the tested workloads and the stated economic assumptions, consumer GPUs remain competitive against the best independently proposed specialised design. Extends M1, M16 and C13. diff --git a/docs/spec/01-lottery-hash.md b/docs/spec/01-lottery-hash.md index 7b03ea9bf..63744afe4 100644 --- a/docs/spec/01-lottery-hash.md +++ b/docs/spec/01-lottery-hash.md @@ -265,29 +265,32 @@ Under class v2 and v3 an implementation MAY treat the cap as a consensus fault. Program id. `FNV-1a-64("igneum-program/" || generator_le32 || seed words as little-endian bytes || attempt_le32 || suffix)` with `generator = 2` under class v2 and `generator = 3` under class v3 (no suffix), and `generator = 4` under class v4 with the suffix `"sub/" || sub_version_le16` (the class v4 stream's sub-version, `PROGRAM_SUBVERSION_V4 = 3` since 7 October 2026: `IGNEUM_PROGRAM_SUBVERSION` in program.h, `"sub_version"` in program.json; without the suffix Devnet 3's epoch-0 id reads 30956569d8f3d8d7 where the chain and the packs say fce15bf61030be57); class v5 is `generator = 5` with no suffix (section 1.4.7). A class v4 program at rung 0 of the ladder uses that form; a program of any other class or rung (a read-width, scratch, mixer, derivation, era, shadow or hot rung other than class v4's rung 0) uses the tag `"igneum-program-rw/"` and appends the class's fields after `attempt_le32` (`generator::program_id_class`). Every pack prints its own derivation as `program_id_derivation` in program.json, built from the byte recipe the id is hashed from, and a worker MUST refuse a pack whose generator version, class, era seed or sub-version is not its own (`packcheck.rs`). Two implementations that agree on the id agree on the generator version, the seed words, the attempt and, under class v4, the sub-version. -Constants of the shipped rule. One row per constant the rule depends on, the value as the crate has it; a reader implementing from this text uses these and nothing else, and the crate's own test reads this table back against its `pub const` items. +Constants of the shipped rule. One row per constant the rule depends on, the value as the crate has it; a reader implementing from this text uses these and nothing else. `tools/ci/spec-constants-check.mjs` (the pre-push gate) reads every table of this shape in this file back against the crate's `pub const` items and fails on a difference; `igneum-pow/tests/spec_readback.rs` derives every pinned id below through the crate. | Constant | Value | Where | |---|---|---| | generator::INSTR_COUNT | 64 | instructions per base program | | generator::LOAD_SLOTS | 16 | load slots per program | | generator::ITERATIONS | 8 | iterations per hash | +| generator::LANES | 32 | lanes per unit | | generator::GENERATOR_VERSION_V4 | 4 | the class v4 generator | | generator::PROGRAM_SUBVERSION_V4 | 3 | the id suffix "sub/" || le16 | | generator::MAX_ATTEMPTS | 32 | the cap under class v2 and v3 | | generator::MAX_ATTEMPTS_V4 | 256 | the cap under the class v4 shape | | generator::V4_SHADOW_INSTRS | 256 | shadow instructions per program | | generator::V4_SHADOW_REPS | 27 | shadow passes per iteration at rung 0 | +| accept::ACCEPT_TAG | "igneum-accept/" | the domain tag of the base-nonce stream | | accept::ACCEPT_UNITS | 64 | (c) units | | accept::ACCEPT_HASHES | 2048 | (c) hashes | | accept::ACCEPT_DATASET_LOG2 | 28 | log2 of the closed-form dataset | -| accept::MAX_SATURATED | 164 | (c) saturated finals and (c') saturated sources, exclusive limit | +| accept::MAX_SATURATED | 164 | (c) saturated finals and (c') saturated sources: the first refused count (the reject message prints 163, the last allowed) | | accept::BIAS_TOLERANCE | 136 | (c) output bias, inclusive | | accept::MIN_DISTINCT_SUM | 245760 | (c) distinct-address sum, exclusive | | accept::ACCEPT_UNITS_DISTINCT_V4 | 4096 | (c'') units, 2^20 evaluations per site | | accept::MIN_DISTINCT_RATIO_V4 | 0.98 | (c'') ratio floor, inclusive | +| accept::distinct_ratio_pass | 2 | the window cap of (c''): `W_s = 2^28 >> min(k_off_s, 2)`, a literal inside the function | -Pinned program ids. A reader who follows 1.4.3 and this section reproduces these from the seed, the attempt and the sub-version above; the crate's test derives each from the recipe and from the printed derivation text. +Pinned program ids. A reader who follows 1.4.3 and this section reproduces these from the seed, the attempt and the sub-version above. The era seed of each chain row is the same 32 bytes as its program seed (the devnet stand-in of 1.13.1). `igneum-pow/tests/spec_readback.rs` derives each id through the crate and draws each class v4 row with the era to its stated attempt; a "must differ" row asserts the current derivation gives another id. | Seed | Attempt | Id | Note | |---|---|---|---| diff --git a/igneum-pow/tests/spec_readback.rs b/igneum-pow/tests/spec_readback.rs new file mode 100644 index 000000000..8f2a1725b --- /dev/null +++ b/igneum-pow/tests/spec_readback.rs @@ -0,0 +1,115 @@ +//! Spec read-back, the ids half (adv-accept-3 finding 3, ledger AP-F8-5, 7 October 2026): every table of +//! `docs/spec/01-lottery-hash.md` headed `| Seed | Attempt | Id | Note |` names program ids a reader of sections 1.4.3 +//! and 1.4.6 must reproduce. This test derives each one through the crate (never by re-hashing the hex in a script): +//! a row whose Note says "must differ" asserts the current derivation gives another id (an earlier stream or +//! sub-version of the same seed); every other row asserts `program_id` over `attempt_words(seed, attempt)` under the +//! row's generator (3 for "class v3", 5 for "generator 5", else 4) equals the id, and, for a class v4 row, that the +//! chain's own draw with the era seed (the same bytes unless the Note names another) accepts at that attempt. +//! The constants half is `tools/ci/spec-constants-check.mjs` (the pre-push gate; no build). +use igneum_pow::generator::{attempt_words, generate_from_seed_bytes_program_class, program_id, ProgramClass, GENERATOR_VERSION_V3, GENERATOR_VERSION_V4}; +use std::path::PathBuf; + +const SPEC: &str = "../docs/spec/01-lottery-hash.md"; + +struct Row { + line: usize, + seed: String, + attempt: u32, + id: u64, + note: String, +} + +fn rows() -> Vec { + let path = PathBuf::from(env!("CARGO_MANIFEST_DIR")).join(SPEC); + let text = std::fs::read_to_string(&path).unwrap_or_else(|e| panic!("{}: {e}", path.display())); + let lines: Vec<&str> = text.lines().collect(); + let header = |l: &str| { + let cells: Vec = l.trim().trim_matches('|').split('|').map(|c| c.trim().to_string()).collect(); + cells == ["Seed", "Attempt", "Id", "Note"] + }; + let mut out = Vec::new(); + let mut i = 0; + while i < lines.len() { + if !header(lines[i]) { + i += 1; + continue; + } + let mut j = i + 1; + if j < lines.len() && lines[j].trim_start().starts_with("|---") { + j += 1; + } + while j < lines.len() && lines[j].trim_start().starts_with('|') { + let cells: Vec = lines[j].trim().trim_matches('|').split('|').map(|c| c.trim().trim_matches('`').to_string()).collect(); + assert!(cells.len() >= 4, "{}:{}: a Seed | Attempt | Id | Note row needs four cells", SPEC, j + 1); + let attempt: u32 = cells[1].parse().unwrap_or_else(|_| panic!("{}:{}: attempt {:?} is not an integer", SPEC, j + 1, cells[1])); + let id = u64::from_str_radix(cells[2].trim_start_matches("0x"), 16).unwrap_or_else(|_| panic!("{}:{}: id {:?} is not 16 hex", SPEC, j + 1, cells[2])); + out.push(Row { line: j + 1, seed: cells[0].clone(), attempt, id, note: cells[3..].join("|") }); + j += 1; + } + i = j; + } + assert!(!out.is_empty(), "{SPEC}: no table headed | Seed | Attempt | Id | Note |"); + out +} + +fn seed_bytes(seed: &str) -> Vec { + let hex = seed.len() == 64 && seed.chars().all(|c| c.is_ascii_hexdigit()); + if hex { + (0..32).map(|k| u8::from_str_radix(&seed[2 * k..2 * k + 2], 16).unwrap()).collect() + } else { + seed.as_bytes().to_vec() + } +} + +fn generator_of(note: &str) -> u32 { + if note.contains("class v3") { + GENERATOR_VERSION_V3 + } else if note.contains("generator 5") { + 5 + } else { + GENERATOR_VERSION_V4 + } +} + +#[test] +fn every_pinned_id_of_the_spec_derives_from_the_crate() { + let rows = rows(); + let mut checked = 0; + for r in &rows { + let bytes = seed_bytes(&r.seed); + let words = attempt_words(&bytes, r.attempt); + let g = generator_of(&r.note); + let derived = program_id(g, &words, r.attempt); + if r.note.contains("must differ") { + assert_ne!(derived, r.id, "{}:{}: the must-differ id {:016x} equals the current derivation for seed {} attempt {}", SPEC, r.line, r.id, r.seed, r.attempt); + } else { + assert_eq!(derived, r.id, "{}:{}: the crate derives {:016x} for seed {} attempt {} under generator {g}, the spec says {:016x}", SPEC, r.line, derived, r.seed, r.attempt, r.id); + } + checked += 1; + } + assert!(checked >= 4, "the spec carries only {checked} pinned ids; the table has shrunk"); +} + +/// The chain's own draw (the era layout over the class v3 base, the shadow block, the full rule) accepts the class v4 +/// rows at the attempt the spec states; the era seed is the program seed unless the Note names another 64-hex value +/// after "era". +#[test] +fn the_chain_draw_accepts_each_class_v4_row_at_its_attempt() { + let rows = rows(); + let mut drawn = 0; + for r in rows.iter().filter(|r| !r.note.contains("must differ") && generator_of(&r.note) == GENERATOR_VERSION_V4) { + let bytes = seed_bytes(&r.seed); + let era: Vec = match r.note.find("era ") { + Some(k) => { + let hex: String = r.note[k + 4..].chars().take_while(|c| c.is_ascii_hexdigit()).collect(); + if hex.len() == 64 { seed_bytes(&hex) } else { bytes.clone() } + } + None => bytes.clone(), + }; + let p = generate_from_seed_bytes_program_class(&format!("spec:{}", &r.seed[..16.min(r.seed.len())]), &bytes, ProgramClass::V4, Some(&era)); + assert_eq!(p.attempt, r.attempt, "{}:{}: the draw accepted seed {} at attempt {}, the spec says {}", SPEC, r.line, r.seed, p.attempt, r.attempt); + assert_eq!(p.program_id(), r.id, "{}:{}: the drawn program's id is {:016x}, the spec says {:016x}", SPEC, r.line, p.program_id(), r.id); + drawn += 1; + } + assert!(drawn >= 1, "no class v4 row to draw"); +} diff --git a/site/ledger.html b/site/ledger.html index b5d65f082..e912bd22c 100644 --- a/site/ledger.html +++ b/site/ledger.html @@ -4,13 +4,13 @@ Igneum ledger: every criticism, answered - + - + @@ -18,7 +18,7 @@ - + @@ -53,7 +53,7 @@