From 4e406ded5c8c3d528e99dbc7e1bf3630a4fe3f62 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 19:21:36 +0000 Subject: [PATCH] Class v6: the genesis dataset size DECIDED at 4 GiB (the founder's word at 20:00 UK, FROZEN as class_v6_dataset_steps [(0, 4096 MiB)]); change (3) and the served policy sentence as decided; the chip line's a-node-ahead end 3.3x with the floor marked Co-Authored-By: Claude Fable 5.1 --- docs/design/class-v6-rotating-family.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/design/class-v6-rotating-family.md b/docs/design/class-v6-rotating-family.md index e4b3d6189..6bc75e6f1 100644 --- a/docs/design/class-v6-rotating-family.md +++ b/docs/design/class-v6-rotating-family.md @@ -307,7 +307,7 @@ The capex wall's two thresholds (lane 3, 10.3, re-folded 13:18 UK on lane 5's co The served line as the external review words it is in 10.0f and overrides this paragraph's wording. This lane's earlier sentence, kept for the record: a chip that stores the dataset reaches about 2.2x to 2.4x per joule against the honest NVIDIA tiers at their knee (the 5080 2.2x, the 5090 2.4x with a chip a node ahead; 2.0x against a chip on the GPU's own node, 2.8x two nodes ahead; 2.8x on the 5090 without the window) and under 2x only against the Apple tier (the M5 Max 1.5x), about 4x and 2.6x if it is built on an N2 SRAM store for USD 100 M or more, and under 1x per hash over its 180-day class life only above about USD 300 M a year of miner revenue (10.0a), with Monero's measured 1.0x to 1.5x beside it; no rotating layer moves the per-joule figures, and layer 3's class life is what sets the per-hash one; the layers decide which chip can be built and how long its tape-out lives. The worst case beside it, if a chip's core costs no more than its bare units (the floor k of 10.2): 4x and 2.4x against the DRAM board, 14x and 9x against the SRAM die (lane 3's line: 6x to 10x at the full shadow, never under 2x). In the other convention, the card's whole 330,000-op latency shadow priced on the chip at the synthesised core (lane 3's 10.3 table): the SRAM die 3.5x against a 5090 at stock and 2.2x at its knee (4.8x and 3.0x with a 2 nm core), the DRAM board 2.6x at stock. The record's claimed band (k 0.3 to 0.8) is confirmed from the chip side by the core row (0.56 at the lock), so the served 2.1x at k = 1 is the conservative end and 2.8x the measured-core reading. -The three class v6 changes it implies: (1) the op mix moves to the band's best mix as the genesis table (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0; the k lane's optimiser, 15:2x UK: +42 percent of k_eff on the unit floors, +15 percent on the core; the shuffle at its floor because the chip's butterfly is k 0.011 to 0.021, the lowest of every family; lane D: 0 of 3,000 eras exhausted under the band), and that table PASSED lane D's harness at the shipped parameters (the 18:00 UK verdict, family-gate.md 6.9; the table renormalised to the generator's 75 points by largest remainder as add 14, xor 13, mul 4, mad 11, shfl 3, rotl 10, sub 9, mulhi 2, rotr 9, or 0, the genesis table's spelling): attack-f8 at the exact table on 64 seeds at 2^20 on the Devnet 3 state 0 hot sets, 0 over 1.2x of the window model (the worst p3 1.103x), 12 of 64 on the bit-R bucket class (the shipped class 4 of 64 at 2^24); the attempts census on the or-floored copy (or at 1 of 75) at width 4 over 2,497 eras r = 0.329, mean attempt 0.49, max 10, 0 exhausted, (c''') 15.6 percent of reaching candidates (the width's cost; the band 14.6), the accepted minimum ratio p1 0.9960; at width 1 over 1,500 eras r = 0.191, mean 0.24, max 4, 0 exhausted, (c''') 1.0 percent; the index-bit read over 6 sigma in 40.5 percent of eras at width 4 and over 300 sigma in 9.3 (the band 44.9 and 9.4), so the table neither worsens nor fixes the bit-R mechanism and the fold in load_index stays the lever. **The table halves the draw's cost against the band and costs nothing at the floors or on the item map; it is the genesis table.** Owed: the exact or = 0 attempts rows at both widths (466 and 401 of 1,500 eras done when build-3 went unreachable); one point of or separates them from the rows above, so the verdict does not turn on them; (2) no SM-sparse default (measured dead on the 5090, 4090 and H100 at 1.3 to 3.9 percent at best; `--sm-sparse auto` ships off by default, on in the Efficiency and Balanced tiers at its measured 1 to 2.5 percent, 10.1 item 6; the per-watt gift of the hot table is the chip's, 20.3c); (3) the dataset schedule, on the coordinator's ruling (19:4x UK; 10.0u): the genesis size is the baseline being frozen and P03 does not score it; scored by adversary burden against commodity burden under the two constraints (the entry tier holds, the 12 GB tier keeps mine-and-prove), this lane recommends 4 GiB to the founder (the largest size inside both constraints, twice 2 GiB's chip ticket, +11.7 percent of a locked 5090's energy measured on the paired control; 5.5 GiB out on the 12 GB co-residence constraint), his word at 20:00 UK with 4 GiB the default; after the freeze every later step is a P03 change at 5 percent against that baseline and taken only when the chain's state outgrows it under 3.1's state term and ceiling; 2 GiB and 5.5 / 8.5 / 11.5 in the sensitivity workbook as the costed alternatives (lane 3's and lane A's schedule rows stay as their record); the read width pinned at 4 words (8 measured not free at stock and +11.2 percent at the lock, 16 never); and a fourth the sweep adds, (4) the 64-register window per lane as the core shape (k 0.78 at the lock against 0.56; 10.0c, the edge table 10.0e), its GPU side modelled until the generator carries a 64-entry init and fold rule (a half-day line) and a pack is measured, with the LIVENESS RULE main confirms (15:56 UK): the fold forming each load address consumes all 64 registers, so the result depends on the whole window and a chip cannot shrink it; a liveness tool that checks every drawn program for that dependency is an acceptance test beside the census (the chip's ticket USD 1,500 / 2,500 / 3,000; a tuned 5090 pays 1 to 5 percent per step; about a quarter of today's cards by count per step). +The three class v6 changes it implies: (1) the op mix moves to the band's best mix as the genesis table (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0; the k lane's optimiser, 15:2x UK: +42 percent of k_eff on the unit floors, +15 percent on the core; the shuffle at its floor because the chip's butterfly is k 0.011 to 0.021, the lowest of every family; lane D: 0 of 3,000 eras exhausted under the band), and that table PASSED lane D's harness at the shipped parameters (the 18:00 UK verdict, family-gate.md 6.9; the table renormalised to the generator's 75 points by largest remainder as add 14, xor 13, mul 4, mad 11, shfl 3, rotl 10, sub 9, mulhi 2, rotr 9, or 0, the genesis table's spelling): attack-f8 at the exact table on 64 seeds at 2^20 on the Devnet 3 state 0 hot sets, 0 over 1.2x of the window model (the worst p3 1.103x), 12 of 64 on the bit-R bucket class (the shipped class 4 of 64 at 2^24); the attempts census on the or-floored copy (or at 1 of 75) at width 4 over 2,497 eras r = 0.329, mean attempt 0.49, max 10, 0 exhausted, (c''') 15.6 percent of reaching candidates (the width's cost; the band 14.6), the accepted minimum ratio p1 0.9960; at width 1 over 1,500 eras r = 0.191, mean 0.24, max 4, 0 exhausted, (c''') 1.0 percent; the index-bit read over 6 sigma in 40.5 percent of eras at width 4 and over 300 sigma in 9.3 (the band 44.9 and 9.4), so the table neither worsens nor fixes the bit-R mechanism and the fold in load_index stays the lever. **The table halves the draw's cost against the band and costs nothing at the floors or on the item map; it is the genesis table.** Owed: the exact or = 0 attempts rows at both widths (466 and 401 of 1,500 eras done when build-3 went unreachable); one point of or separates them from the rows above, so the verdict does not turn on them; (2) no SM-sparse default (measured dead on the 5090, 4090 and H100 at 1.3 to 3.9 percent at best; `--sm-sparse auto` ships off by default, on in the Efficiency and Balanced tiers at its measured 1 to 2.5 percent, 10.1 item 6; the per-watt gift of the hot table is the chip's, 20.3c); (3) the dataset's genesis size DECIDED: 4 GiB, the founder's word at 20:00 UK (main's instruction applied the default as his word when no other figure came; 10.0u), FROZEN at genesis as class_v6_dataset_steps [(0, 4096 MiB)] in every D1 candidate's literal; scored by adversary burden against commodity burden under the two constraints (the entry tier holds, the 12 GB tier keeps mine-and-prove), the largest size inside both (twice 2 GiB's chip ticket for +11.7 percent of a locked 5090's energy on the paired control; 5.5 GiB out on the 12 GB co-residence constraint), the curve kept beside it with the 2 GiB alternative and the 5.5 GiB failure as the reasons; after the freeze every later step is a P03 change at 5 percent against that baseline and taken only when the chain's state outgrows it under 3.1's state term and ceiling; 2 GiB and 5.5 / 8.5 / 11.5 in the sensitivity workbook as the costed alternatives (lane 3's and lane A's schedule rows stay as their record); the read width pinned at 4 words (8 measured not free at stock and +11.2 percent at the lock, 16 never); and a fourth the sweep adds, (4) the 64-register window per lane as the core shape (k 0.78 at the lock against 0.56; 10.0c, the edge table 10.0e), its GPU side modelled until the generator carries a 64-entry init and fold rule (a half-day line) and a pack is measured, with the LIVENESS RULE main confirms (15:56 UK): the fold forming each load address consumes all 64 registers, so the result depends on the whole window and a chip cannot shrink it; a liveness tool that checks every drawn program for that dependency is an acceptance test beside the census (the chip's ticket USD 1,500 / 2,500 / 3,000; a tuned 5090 pays 1 to 5 percent per step; about a quarter of today's cards by count per step). #### 10.0a The second unit: cost per hash over the chip's life (the founder's question, 14:1x UK; modelled on measured card rows; SUPERSEDED as a headline by 10.0f item 1: the 180-day life below is the fixed-lane chip's row, and the programmable chip's 3-year life is the default) @@ -473,7 +473,7 @@ Two corrections this forces on the served numbers: (1) the honest adversary's ba **The first placed gated row (the k lane, 19:3x UK): the adversary's 32-register base core, placed and routed on ASAP7 (SPEF, a clock tree, 379,633 cells, a VCD with every pin annotated, the register file gated): about 7.0 pJ per lane-op at ASAP7 (one 300-cycle run, the program-load phase subtracted at the synthesis ratio, plus or minus 15 percent; the two-length solve within 20 minutes), 4.9 at N5, 3.5 at N3, 2.5 at N2; a model, never a lower bound. k at the lock 0.79 / 0.56 / 0.40 (N5 / N3 / N2). The GDDR7 board at the lock: 2.4x node-for-node, 2.8x a node ahead, 3.2x two ahead. So the placed gated base lands on this morning's synthesised ungated headline (6.9 pJ, k 0.56 at N3, 2.8x) to the digit: the gating and the placement cancel.** The core-only sentence for the base core is therefore "estimates a 2.8x energy-efficiency advantage (2.4x on the GPU's own node)" as a placed figure; the placed 64-register window core (the defence's chip side) is in detailed route (20:15 UK), expected at 8.5 to 10 pJ (k about 0.7 to 0.8 at N3 at the lock), which would read 2.5x a node ahead and 2.1x node-for-node, approximate until placed. The served sentence stays on the whole-machine rows of 10.0t (1.5x to 3.1x as complete machines), with this core-only row beside it marked. -**The two lanes reconciled (the k lane with the adversary lane, 19:5x UK; both rows placed and routed on ASAP7, the same node factors, DRAM term and GPU side; the joint table with the coordinator).** On the board identity the two genesis cores agree within 6 percent (the k lane's gated-flop 32-register core 2.41x same-node and 2.80x a node ahead; the adversary lane's SRAM-macro 64-register genesis core 2.28x and 2.72x); the adversary's 18-family bank costs a further 0.23x (2.05x and 2.45x); the rest of the gap to the whole machine's 1.5x is the complete-machine terms (the sustained rate at 82 percent of the activate ceiling, core leakage, PSU and VRM x1.21, cooling, the host; modelled, approximate), which the board identity does not carry: 40 percent of the gap is the core, 60 percent the machine terms. **The served line both lanes stand behind: 1.5x to 1.8x for the complete machine and 2.0x to 2.4x for the board alone, same node, both placed; a node ahead 1.8x to 2.1x and 2.45x to 2.8x.** The k lane's placed 64-register window core (the genesis families, gated flops) routed at 20:1x UK with its power report about 20:50, so the landing carries the expected 8.5 to 10 pJ per lane-op at ASAP7 (k about 0.7 to 0.8 at N3 at the lock, 2.5x a node ahead and 2.1x node-for-node) labelled approximate, the placed row the amendment with its minute; the placed base's two-length confirmation reads 6.7 pJ (2.4x same-node, 2.8x a node ahead). **The three-row served line both chip lanes stand behind, as the k lane gives it with the 32-lane floor in: 1.5x to 2.1x for the complete machine and 2.0x to 2.9x for the board alone, same node, placed, both lanes; a node ahead 1.8x to 2.4x and 2.45x to 3.2x.** +**The two lanes reconciled (the k lane with the adversary lane, 19:5x UK; both rows placed and routed on ASAP7, the same node factors, DRAM term and GPU side; the joint table with the coordinator).** On the board identity the two genesis cores agree within 6 percent (the k lane's gated-flop 32-register core 2.41x same-node and 2.80x a node ahead; the adversary lane's SRAM-macro 64-register genesis core 2.28x and 2.72x); the adversary's 18-family bank costs a further 0.23x (2.05x and 2.45x); the rest of the gap to the whole machine's 1.5x is the complete-machine terms (the sustained rate at 82 percent of the activate ceiling, core leakage, PSU and VRM x1.21, cooling, the host; modelled, approximate), which the board identity does not carry: 40 percent of the gap is the core, 60 percent the machine terms. **The served line both lanes stand behind: 1.5x to 1.8x for the complete machine and 2.0x to 2.4x for the board alone, same node, both placed; a node ahead 1.8x to 2.1x and 2.45x to 2.8x.** The k lane's placed 64-register window core (the genesis families, gated flops) routed at 20:1x UK with its power report about 20:50, so the landing carries the expected 8.5 to 10 pJ per lane-op at ASAP7 (k about 0.7 to 0.8 at N3 at the lock, 2.5x a node ahead and 2.1x node-for-node) labelled approximate, the placed row the amendment with its minute; the placed base's two-length confirmation reads 6.7 pJ (2.4x same-node, 2.8x a node ahead). **The three-row served line both chip lanes stand behind, as the coordinator carries it for the landing: 1.5x to 2.1x for the complete machine and 2.0x to 2.9x for the board alone, same node, placed, both lanes; a node ahead 1.8x to 2.4x and 2.45x to 3.3x; the 2.9x end marked as the resizer-downsized floor until the k lane's placed core32 lands by 21:00 UK.** The row to serve at 18:30 UK (the k lane, 17:5x UK; the placement of the gated 64-register core slipped to about 18:30 on a floorplan timing repair, the other five placed rows by 21:00): on the gated 64-register core, synthesis-only, a model never a lower bound (the GDDR7 board at the 5090's 1,300 MHz lock, 2.33 microjoules; E_chip = 0.466 + 102,100 x e_chip; node factors claimed): @@ -645,7 +645,7 @@ The rows. Commodity: the 5.5 GiB dataset costs the 5090 +4.8 percent of energy p The 8 GB tier's own rows change nothing in the verdict (the budget is set at the honest knee, which is the tuned Blackwell card; the 7600's -2.5 percent of rate at 5.5 GiB is inside it), and they narrow the sentence's claim to the card it is true of. -**The mapping control (the hash lane, PC 1's 5090, 17:21 to 17:26 UTC, one job, the same program with byte-equal instructions in three packs, fingerprints PASS) moves the first step again: the cost is the size's, not the mapping's, and 4 GiB does not sit inside the budget at the knee either.** At the 1,300 MHz lock: v3-4g (2^30 words, the mask path) 118.7 MH/s at 211.3 W, 1.780 microjoules; ds4g-ms (2^30 minus 2^16 words, multiply-shift) 119.0 at 212.0 W, 1.782 (+0.1 percent: the mapping's term at the knee is zero within noise); ds55 (5.5 GiB) 116.7 at 210.9 W, 1.807 (+1.5 percent over 4 GiB). Unlocked: v3-4g 2.264, ds4g-ms 2.318 (+2.4, watts noise on an equal rate), ds55 2.345. Against this card's 1 GiB rows from the earlier job (the lock 137.0 MH/s at 218.2 W, 1.593; stock 140.7 at 316.3 W, 2.248): the 4 GiB step costs +11.7 percent at the knee and +0.7 at stock; 5.5 GiB +13.4 and +4.3; the morning's +8 at 4 GiB was a different run of this card. So the size cost at the knee saturates above a few GiB (the TLB reach: 2 GiB +4 on the morning's row, 4 GiB +11.7, 5.5 GiB +13.4, 8 GiB +10 on the morning's row), and the choice between 4 and 5.5 GiB is a 1.5 percent question; the real question is whether any floor above 2 GiB is inside the budget at the knee. Under the 10 percent budget neither 4 nor 5.5 passes on the paired read; under the founder's P03 (at most 5 percent of joules per accepted work against the paired tuned baseline) neither passes at the knee and 2 GiB (+4 percent, the morning's row; the paired 2 GiB read is published on PC 1 as run-ca3-pc1-ds2g-5090-20261008 and cannot start while the runner is held by a withdrawn-but-fetched overnight job to its 600-minute cap, 20:2x UK, so the morning's row stands labelled and the paired read is an amendment with its minute) is the largest step that does. **The coordinator's ruling (19:4x UK) re-frames the decision: P03's 5 percent budget scores production candidate changes after the D1 freeze against the paired tuned baseline, and the genesis dataset size IS the baseline being frozen, so P03 does not score it; P06 names the sizes as candidates and the plan scores each by adversary burden against commodity burden, the recommended size being the one that maximises the adversary's burden while keeping the entry tier (8 GB) and the 12 GB tier's mine-and-prove co-residence; the founder's word at 20:00 UK, the default 4 GiB; after the freeze every later step is a P03 change at 5 percent against that baseline.** On that rule the curve reads: the entry tier holds every size to 5.5 GiB (the 4060 and the RX 7600, measured); the 12 GB tier's mine-and-prove co-residence holds at 4 GiB (about 12.0 of 12.3 GB) and fails at 5.5 (13.6 GB, measured on the 3060); so 5.5 GiB is out on the co-residence constraint and 4 GiB is the largest size inside both constraints, with twice 2 GiB's adversary burden (the hybrid's SRAM USD 500 against 250, the die two reticles against one) for +11.7 percent of a locked 5090's energy against +4 (measured) and nothing on the pure board. **This lane's recommendation to the founder: 4 GiB**, the burden stated beside it; 2 GiB is the costless alternative that buys half the ticket. This lane's earlier reading in this section (2 GiB under P03) stands as the record of the row, superseded by the ruling. The earlier reading kept for the record: the genesis floor is 2 GiB, class v5's designed size, which passes P03 at the knee on the measured row; the dataset grows only when the chain's own state outgrows it under 3.1's state term and ceiling; 4 GiB is the costed alternative beside 5.5 / 8.5 / 11.5 in the workbook. The chip-side burden at 2 GiB: nothing on the board, the hybrid's SRAM at its USD 250 baseline, the die at one reticle; the floor's ticket lever is zero at genesis and rises with the state, which is the honest reading of layer 2 (the floor was never the thing that held a chip; 10.0q and 12c).** What would reverse it: a paired 2 GiB knee read over 5 percent (then no floor above 1 GiB passes P03 at the knee and the layer-2 floor is the state term alone), or main ruling the budget's baseline as the card at stock rather than at its knee (then 4 GiB passes at +0.7 and 5.5 GiB at +4.3 under P03). **The sentence the site serves under the dataset policy:** "The dataset's size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB, over the 5 percent budget (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome; so the genesis size is the founder's decision on that scoring (this lane's recommendation 4 GiB, the largest size that keeps every entry card and a 12 GB card's mining and proving together), and every later step is scored at 5 percent against it and taken only when the chain's own state outgrows the dataset, not on a calendar." Labels: the card rows measured (PC 1 under the gen 4 caveat, the rented 5090 at stock); the chip tickets modelled and approximate; the 8.5 and 11.5 GiB knee costs expected, not measured. This revises the close's change (3): the schedule reads 4 GiB at genesis with the state term and ceiling of 3.1, the 5.5 / 8.5 / 11.5 steps retired to the sensitivity workbook as the costed alternative; lane 3's and lane A's schedule rows stay as their record. What would reverse it: a 5.5 GiB power-of-two-mapped control at the knee reading inside the budget (then the mapping, not the size, was the cost, and the fix is the mapping); the k and adversary lanes' rows putting the die's ticket under its coexistence lines (c) and (f), which no row today does. +**The mapping control (the hash lane, PC 1's 5090, 17:21 to 17:26 UTC, one job, the same program with byte-equal instructions in three packs, fingerprints PASS) moves the first step again: the cost is the size's, not the mapping's, and 4 GiB does not sit inside the budget at the knee either.** At the 1,300 MHz lock: v3-4g (2^30 words, the mask path) 118.7 MH/s at 211.3 W, 1.780 microjoules; ds4g-ms (2^30 minus 2^16 words, multiply-shift) 119.0 at 212.0 W, 1.782 (+0.1 percent: the mapping's term at the knee is zero within noise); ds55 (5.5 GiB) 116.7 at 210.9 W, 1.807 (+1.5 percent over 4 GiB). Unlocked: v3-4g 2.264, ds4g-ms 2.318 (+2.4, watts noise on an equal rate), ds55 2.345. Against this card's 1 GiB rows from the earlier job (the lock 137.0 MH/s at 218.2 W, 1.593; stock 140.7 at 316.3 W, 2.248): the 4 GiB step costs +11.7 percent at the knee and +0.7 at stock; 5.5 GiB +13.4 and +4.3; the morning's +8 at 4 GiB was a different run of this card. So the size cost at the knee saturates above a few GiB (the TLB reach: 2 GiB +4 on the morning's row, 4 GiB +11.7, 5.5 GiB +13.4, 8 GiB +10 on the morning's row), and the choice between 4 and 5.5 GiB is a 1.5 percent question; the real question is whether any floor above 2 GiB is inside the budget at the knee. Under the 10 percent budget neither 4 nor 5.5 passes on the paired read; under the founder's P03 (at most 5 percent of joules per accepted work against the paired tuned baseline) neither passes at the knee and 2 GiB (+4 percent, the morning's row; the paired 2 GiB read is published on PC 1 as run-ca3-pc1-ds2g-5090-20261008 and cannot start while the runner is held by a withdrawn-but-fetched overnight job to its 600-minute cap, 20:2x UK, so the morning's row stands labelled and the paired read is an amendment with its minute) is the largest step that does. **The coordinator's ruling (19:4x UK) re-frames the decision: P03's 5 percent budget scores production candidate changes after the D1 freeze against the paired tuned baseline, and the genesis dataset size IS the baseline being frozen, so P03 does not score it; P06 names the sizes as candidates and the plan scores each by adversary burden against commodity burden, the recommended size being the one that maximises the adversary's burden while keeping the entry tier (8 GB) and the 12 GB tier's mine-and-prove co-residence; the founder's word at 20:00 UK, the default 4 GiB; after the freeze every later step is a P03 change at 5 percent against that baseline.** On that rule the curve reads: the entry tier holds every size to 5.5 GiB (the 4060 and the RX 7600, measured); the 12 GB tier's mine-and-prove co-residence holds at 4 GiB (about 12.0 of 12.3 GB) and fails at 5.5 (13.6 GB, measured on the 3060); so 5.5 GiB is out on the co-residence constraint and 4 GiB is the largest size inside both constraints, with twice 2 GiB's adversary burden (the hybrid's SRAM USD 500 against 250, the die two reticles against one) for +11.7 percent of a locked 5090's energy against +4 (measured) and nothing on the pure board. **This lane's recommendation to the founder: 4 GiB**, the burden stated beside it; 2 GiB is the costless alternative that buys half the ticket. This lane's earlier reading in this section (2 GiB under P03) stands as the record of the row, superseded by the ruling. The earlier reading kept for the record: the genesis floor is 2 GiB, class v5's designed size, which passes P03 at the knee on the measured row; the dataset grows only when the chain's own state outgrows it under 3.1's state term and ceiling; 4 GiB is the costed alternative beside 5.5 / 8.5 / 11.5 in the workbook. The chip-side burden at 2 GiB: nothing on the board, the hybrid's SRAM at its USD 250 baseline, the die at one reticle; the floor's ticket lever is zero at genesis and rises with the state, which is the honest reading of layer 2 (the floor was never the thing that held a chip; 10.0q and 12c).** What would reverse it: a paired 2 GiB knee read over 5 percent (then no floor above 1 GiB passes P03 at the knee and the layer-2 floor is the state term alone), or main ruling the budget's baseline as the card at stock rather than at its knee (then 4 GiB passes at +0.7 and 5.5 GiB at +4.3 under P03). **The sentence the site serves under the dataset policy:** "The dataset's size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB, over the 5 percent budget (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome; so the dataset starts at 4 GiB, the largest size that keeps every entry card and a 12 GB card's mining and proving together, decided at genesis, and every later step is scored at 5 percent against it and taken only when the chain's own state outgrows the dataset, not on a calendar." Labels: the card rows measured (PC 1 under the gen 4 caveat, the rented 5090 at stock); the chip tickets modelled and approximate; the 8.5 and 11.5 GiB knee costs expected, not measured. This revises the close's change (3): the schedule reads 4 GiB at genesis with the state term and ceiling of 3.1, the 5.5 / 8.5 / 11.5 steps retired to the sensitivity workbook as the costed alternative; lane 3's and lane A's schedule rows stay as their record. What would reverse it: a 5.5 GiB power-of-two-mapped control at the knee reading inside the budget (then the mapping, not the size, was the cost, and the fix is the mapping); the k and adversary lanes' rows putting the die's ticket under its coexistence lines (c) and (f), which no row today does. #### 10.0v The served reference population and the cost-per-accepted-unit table (the pin the finish line missed, appended to the plan 18:16 UK; lane 3 at 2db4fe34, 18:03 UK, in this landing; every cell labelled; the script on build-4)