class v5: the first class v5 pack, Devnet 3's epoch 0 (genesis 4020cb43... as epoch and era seed, day 20,733, the genesis state's 11 leaves under root 7e37a9fb...), generator 5, program id e5a4ac5978462156, exported on igneum-build-1 at 18:06:41Z; its Metal fingerprint 82b19cbde8557ea5 on the M5 Max at 18:07:09Z (vectors 3 of 3, cache and dataset PASS); the page's time line

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
This commit is contained in:
igneum-labs 2026-10-07 18:07:55 +00:00
parent 99c8782c64
commit 3efd339786
15 changed files with 3824 additions and 0 deletions

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| 11:47 to 11:59 | The flip run on the quiet box: the chain did everything the design says (the flip, four v5 epochs, a root per epoch, the stale miner off on 52 of 52, the stateless node stopped at 480); six `FAILED CHECK`s were the harness's own scope (it compared the stateless node's sink with the others, counted the stale miner's rejections as a fault, and read the flip epoch's stream after the executor had dropped it: captures are kept two epochs); the checks fixed |
| 12:00 to 12:11 | PASS on every check (section 10) |
| 12:12 to 12:23 | The no-flip case PASS (section 10); both branches pushed; master merged for the build-2 test route (d1285cef) |
| 18:5x to 19:07 | Resumed on the project lead's first-priority order (build class v5 now, on the 0.3.23 line, byte 6): the frozen sub-version 3 (ca3-v4-amend 017e7037) merged into class-v5 and release-0.3.23-node into class-v5-node; the draw's and the acceptance rules' class keys set the state flag aside (the acceptance key had judged a v5 candidate under the pre-amendment rule and the draw diverged at instruction 0; fixed, 70 unit tests green on build-2 at 18:04Z); class v5 pinned to object byte 6 counted exactly (byte 7 is v4 sub-version 3); the gap list as section 13; the FIRST CLASS V5 PACK `proto-cuda/packs-ca3-v5/v5-dn3-epoch0` (Devnet 3's genesis 4020cb43... as epoch and era seed, day 20,733, the genesis state's 11 leaves under root 7e37a9fb...), exported on build-1 at 18:06:39 to 18:06:41Z, program id e5a4ac5978462156, its Metal fingerprint on the M5 Max under the measure lock at 18:07:04 to 18:07:09Z: 82b19cbde8557ea5, the three vector warps bit-exact, the build 29.8 ms GPU; the Metal pack bench takes `leaves.bin` |
| 13:2x | The coordinator's correction: the hot-set bound is NOT satisfied by sub-version 1 (F8's re-gate: nine of the first 30 seeds over 1.2x, p31 at 29.3x, 0.19 percent hot-set programs; saturated values pass saturation-preserving writers); v5 inherits the gap by merge and takes sub-version 2 by merge when it lands; the AP-F4-1 and AP-F1-1 rules come in the next round; the lane stops here |
| 12:5x to 13:21 | The amended class v4 taken in: ca3-v4-amend 8c728ca3 merged into class-v5 (4e737543) and release-0.3.20-node into class-v5-node (699db5a2); the source rule's class key sets the state flag aside so v5 and its rungs draw under it (a unit test pins the v5 chain draw equal to the amended v4's with no lossy-sourced load, the unamended v3 stream the known-failed case); generator 5 keeps `program_id(5, seed, attempt)` with no sub-version (the hash lane's reading: the suffix separates two streams inside generator 4); class v5 is object byte 6 above the amended v4's 5 (the fork, the harness, the default byte); igneum-pow 67 unit and 39 integration tests on igneum-build-2, the packs test with the re-exported control pack, the flip case PASS again with bytes 6,6,6 (the flip at epoch 8 on 3 of 3, 183 v5 blocks, the stale miner off on 59 of 59, the stateless node stopped at 480, equal roots) |
| 10:4x | The Counter ASIC coordinator relays the project lead's ruling of option A on AP-F8-1: the injecting-source load draw lands in class v4 itself on the hash lane's branch ca3-v4-amend (0.3.19); class v5 takes it by merging that branch once its commit is up, not by a second implementation; the page's section 11 row stands as the record of the bound and its gate |

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// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000". Do not edit by hand.
// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
// Built from source at runtime by proto-opencl/host.c, which passes these defines:
// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
#ifndef IGNEUM_GROUP
#define IGNEUM_GROUP 32
#endif
#ifndef IGNEUM_EXCHANGE
#define IGNEUM_EXCHANGE 0
#endif
#ifdef __OPENCL_VERSION__
#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
#if IGNEUM_EXCHANGE == 1
#ifdef cl_khr_subgroups
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
#endif
#ifdef cl_khr_subgroup_shuffle
#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
#endif
#elif IGNEUM_EXCHANGE == 2
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
#endif
#else
// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
#include "emu_opencl.h"
#endif
#if IGNEUM_EXCHANGE == 1
#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#elif IGNEUM_EXCHANGE == 2
#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#else
// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
#endif
static inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
static inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
static inline void mh_chacha_block(const uint* x, uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
static inline void mh_cache_segment(__global uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0xe23f9008u ^ prev[4];
x[5] = 0xde33e763u ^ prev[5];
x[6] = 0xc5ba415du ^ prev[6];
x[7] = 0x8ddf6786u ^ prev[7];
x[8] = 0x59f4a4beu ^ prev[8];
x[9] = 0x8a3bc680u ^ prev[9];
x[10] = 0x701b8e40u ^ prev[10];
x[11] = 0x3b59025au ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
static inline void mh_mixer(uint* s, uint rk) {
s[0] = (s[0] ^ (0xe5bef5a3u + rk)) * 0xd1d79e7fu;
s[1] = (s[1] ^ (0xdb2a7d90u + rk)) * 0xbcb61f8bu;
s[2] = (s[2] ^ (0xcd1fa7e1u + rk)) * 0x970e91abu;
s[3] = (s[3] ^ (0x30289419u + rk)) * 0xd749d96du;
s[4] = (s[4] ^ (0x0a730d58u + rk)) * 0x143d7339u;
s[5] = (s[5] ^ (0x432f8579u + rk)) * 0x2cde0d69u;
s[6] = (s[6] ^ (0x6ab978a5u + rk)) * 0x12d0a8c1u;
s[7] = (s[7] ^ (0x8c984f49u + rk)) * 0x2d335be9u;
s[8] = (s[8] ^ (0x788c3c9eu + rk)) * 0x80a8aae9u;
s[9] = (s[9] ^ (0x051eef02u + rk)) * 0x7ac896c7u;
s[10] = (s[10] ^ (0x05e77db9u + rk)) * 0x9de23db7u;
s[11] = (s[11] ^ (0x8b3cd4f3u + rk)) * 0xc362827du;
s[12] = (s[12] ^ (0x6948d6cfu + rk)) * 0x5f4cdb5bu;
s[13] = (s[13] ^ (0x0d8677f6u + rk)) * 0xfc6c5097u;
s[14] = (s[14] ^ (0xf9505c8cu + rk)) * 0x6f547f83u;
s[15] = (s[15] ^ (0x4513c163u + rk)) * 0x1ac31b47u;
MH_QR(s[0], s[4], s[8], s[12], 28u, 11u, 18u, 18u) MH_QR(s[1], s[5], s[9], s[13], 28u, 11u, 18u, 18u)
MH_QR(s[2], s[6], s[10], s[14], 28u, 11u, 18u, 18u) MH_QR(s[3], s[7], s[11], s[15], 28u, 11u, 18u, 18u)
MH_QR(s[0], s[5], s[10], s[15], 13u, 28u, 5u, 13u) MH_QR(s[1], s[6], s[11], s[12], 13u, 28u, 5u, 13u)
MH_QR(s[2], s[7], s[8], s[13], 13u, 28u, 5u, 13u) MH_QR(s[3], s[4], s[9], s[14], 13u, 28u, 5u, 13u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
static inline void mh_item(__global const uint* cache, __global const uint* leaf, uint t, uint* s) {
s[0] = 0xe23f9008u;
s[1] = 0xde33e763u;
s[2] = 0xc5ba415du;
s[3] = 0x8ddf6786u;
s[4] = 0x59f4a4beu;
s[5] = 0x8a3bc680u;
s[6] = 0x701b8e40u;
s[7] = 0x3b59025au;
s[8] = t * 0xd1d79e7fu + 0xe5bef5a3u;
s[9] = t * 0xbcb61f8bu + 0xdb2a7d90u;
s[10] = t * 0x970e91abu + 0xcd1fa7e1u;
s[11] = t * 0xd749d96du + 0x30289419u;
s[12] = t * 0x143d7339u + 0x0a730d58u;
s[13] = t * 0x2cde0d69u + 0x432f8579u;
s[14] = t * 0x12d0a8c1u + 0x6ab978a5u;
s[15] = t * 0x2d335be9u + 0x8c984f49u;
for (uint i = 0u; i < 16u; ++i) s[i] ^= leaf[i];
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// Class v5 (docs/design/class-v5-stored-state.md): leaf(t) = leaves[t mod nLeaves], 16 words per leaf (leaves.bin).
static inline __global const uint* mh_leaf(__global const uint* leaves, uint nLeaves, uint t) { return leaves + ((t % nLeaves) * 16u); }
// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 1 9 13 14 of w.
static inline uint mh_j(uint w) { return ((w >> 1u) & 1u) | (((w >> 9u) & 1u) << 1) | (((w >> 13u) & 1u) << 2) | (((w >> 14u) & 1u) << 3); }
static inline uint mh_t(uint w) { w = (w & 0x00003fffu) | ((w >> 15u) << 14u); w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x000001ffu) | ((w >> 10u) << 9u); w = (w & 0x00000001u) | ((w >> 2u) << 1u); return w; }
static inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 1u) << 2u) | (w & 0x00000001u) | (((j >> 0u) & 1u) << 1u); w = ((w >> 9u) << 10u) | (w & 0x000001ffu) | (((j >> 1u) & 1u) << 9u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 2u) & 1u) << 13u); w = ((w >> 14u) << 15u) | (w & 0x00003fffu) | (((j >> 3u) & 1u) << 14u); return w; }
// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w).
static inline uint mh_word(__global const uint* cache, __global const uint* leaves, uint nLeaves, uint w) { uint s[16]; mh_item(cache, mh_leaf(leaves, nLeaves, mh_t(w)), mh_t(w), s); return s[mh_j(w)]; }
// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
// The same constants as memhard.h in this pack (one emitter, three dialects).
__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
uint seg = (uint)get_global_id(0);
if (seg < nSegments) mh_cache_segment(cache, seg);
}
// Class v5: the window's leaves (leaves.bin, IGNEUM_STATE_LEAVES x 16 words) and their count.
__kernel void igneum_build(__global uint* ds, __global const uint* cache, __global const uint* leaves, uint nLeaves, uint nItems) {
uint t = (uint)get_global_id(0);
if (t < nItems) {
uint s[16];
mh_item(cache, mh_leaf(leaves, nLeaves, t), t, s);
for (uint i = 0u; i < 16u; ++i) ds[(ulong)mh_addr(t, i)] = s[i];
}
}
// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
{ uint x = nonce ^ 0xbe8c5a0cu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x7646e626u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint x = nonce ^ 0x7646e626u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0x508e29d0u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint x = nonce ^ 0x508e29d0u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0xfb8a5b4au; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint x = nonce ^ 0xfb8a5b4au; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0x53c50955u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint x = nonce ^ 0x53c50955u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0x685d62fcu; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint x = nonce ^ 0x685d62fcu; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x6065c013u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint x = nonce ^ 0x6065c013u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x881096ebu; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint x = nonce ^ 0x881096ebu; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0xbe8c5a0cu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r6 = r6 - r3; // 0 sub
r2 = r2 | r6; // 1 or
r4 = r4 + r0 + ((((sel >> 4u) & 1u) != 0u) ? 0x7731324bu : 0x1a579b38u); // 2 add
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 3 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r0 = r0 ^ t_; } // 4 shfl
r4 = r4 ^ r1; // 5 xor
r3 = r5 * r3 + r3; // 6 mad
r1 = r1 * r6; // 7 mul
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x08000000u) & mask]; // 8 load
r0 = r0 ^ r4; // 9 xor
r0 = r0 + r7 + ((((sel >> 30u) & 1u) != 0u) ? 0xb10fcef8u : 0xee083919u); // 10 add
r0 = mul_hi(r0, r2); // 11 mulhi
r5 = r5 ^ r4; // 12 xor
r7 = r3 * r0 + r7; // 13 mad
r3 = r3 ^ ds[((rotl_imm(r4 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 14 load
r2 = r2 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 15 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r7 = r7 ^ t_; } // 16 shfl
r7 = r7 * r6; // 17 mul
r2 = r3 * r1 + r2; // 18 mad
r5 = rotr_var(r5, r2); // 19 rotr
r5 = r5 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 20 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r6 = r6 ^ t_; } // 21 shfl
r1 = mul_hi(r1, r2); // 22 mulhi
r6 = r6 ^ r5; // 23 xor
r5 = r2 * r0 + r5; // 24 mad
r6 = r3 * r7 + r6; // 25 mad
r6 = r6 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 26 load
r1 = r5 * r5 + r1; // 27 mad
r0 = r0 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 28 load
r7 = r7 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x0b1f02c7u : 0xd5e6c37cu); // 29 add
r7 = r7 + r0 + ((((sel >> 0u) & 1u) != 0u) ? 0x2d6e8bd1u : 0x4e45ba51u); // 30 add
r0 = r0 ^ r2; // 31 xor
r6 = r6 + r2 + ((((sel >> 13u) & 1u) != 0u) ? 0x351422d2u : 0x1c91b2a1u); // 32 add
r4 = mul_hi(r4, r5); // 33 mulhi
r3 = rotr_var(r3, r5); // 34 rotr
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 35 load
r4 = rotl_imm(r4, 13u); // 36 rotl
r6 = r6 + r1 + ((((sel >> 7u) & 1u) != 0u) ? 0x64a28251u : 0x3f2970f7u); // 37 add
r2 = r2 * r0; // 38 mul
r3 = r3 + r4 + ((((sel >> 15u) & 1u) != 0u) ? 0x7378c955u : 0x3b7b3317u); // 39 add
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 40 load
r6 = r6 ^ r5; // 41 xor
r3 = r3 + r0 + ((((sel >> 2u) & 1u) != 0u) ? 0xb31f6a64u : 0x6678b059u); // 42 add
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 43 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r3 = r3 ^ t_; } // 44 shfl
r1 = mul_hi(r1, r5); // 45 mulhi
r0 = rotl_imm(r0, 6u); // 46 rotl
r1 = r1 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 47 load
r4 = r4 + r0 + ((((sel >> 17u) & 1u) != 0u) ? 0x5feccee6u : 0x43095946u); // 48 add
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 49 load
r2 = r2 - r3; // 50 sub
r7 = r7 + r2 + ((((sel >> 24u) & 1u) != 0u) ? 0x26e2b582u : 0xf45ecdf8u); // 51 add
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 52 load
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 53 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r7 = r7 ^ t_; } // 54 shfl
r1 = rotr_var(r1, r2); // 55 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r0 = r0 ^ t_; } // 56 shfl
r5 = rotl_imm(r5, 12u); // 57 rotl
r5 = r5 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x473b1718u : 0x6b4f35e8u); // 58 add
r4 = rotr_var(r4, r1); // 59 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r4 = r4 ^ t_; } // 60 shfl
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 61 load
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 62 load
r4 = r4 * r1; // 63 mul
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r6 = r6 | r0; // s0 or
r7 = r7 * r3; // s1 mul
r3 = r5 * r5 + r3; // s2 mad
r7 = r7 + r4 + ((((sel >> 6u) & 1u) != 0u) ? 0x38e58a06u : 0x97d3d105u); // s3 add
r6 = r6 + r0 + ((((sel >> 20u) & 1u) != 0u) ? 0x9629673du : 0x29b87b9au); // s4 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r6 = r6 ^ t_; } // s5 shfl
r5 = r3 * r5 + r5; // s6 mad
r3 = rotl_imm(r3, 5u); // s7 rotl
r0 = r0 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0x4a5f55e1u : 0xa7c1fb0fu); // s8 add
r5 = r5 * r7; // s9 mul
r4 = r4 ^ r5; // s10 xor
r6 = mul_hi(r6, r4); // s11 mulhi
r5 = rotl_imm(r5, 13u); // s12 rotl
r0 = r2 * r1 + r0; // s13 mad
r2 = mul_hi(r2, r4); // s14 mulhi
r3 = r3 | r1; // s15 or
r0 = r0 - r5; // s16 sub
r0 = r0 * r6; // s17 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 4u); r5 = r5 ^ t_; } // s18 shfl
r3 = r3 | r4; // s19 or
r6 = r3 * r2 + r6; // s20 mad
r0 = rotl_imm(r0, 11u); // s21 rotl
r3 = rotl_imm(r3, 25u); // s22 rotl
r6 = r6 ^ r4; // s23 xor
r4 = r4 | r2; // s24 or
r1 = r1 + r6 + ((((sel >> 7u) & 1u) != 0u) ? 0xfc2f6d17u : 0x53e74799u); // s25 add
r7 = rotr_var(r7, r6); // s26 rotr
r7 = r7 + r5 + ((((sel >> 27u) & 1u) != 0u) ? 0x787048dcu : 0xb8fae90eu); // s27 add
r4 = r4 ^ r1; // s28 xor
r6 = r6 ^ r1; // s29 xor
r2 = mul_hi(r2, r0); // s30 mulhi
r1 = rotr_var(r1, r4); // s31 rotr
r7 = r7 ^ r4; // s32 xor
r3 = r2 * r6 + r3; // s33 mad
r3 = r3 + r1 + ((((sel >> 12u) & 1u) != 0u) ? 0x9ffd510bu : 0xd2dc42ebu); // s34 add
r4 = r4 + r7 + ((((sel >> 7u) & 1u) != 0u) ? 0xf871ba37u : 0xad8eda6fu); // s35 add
r7 = r7 + r4 + ((((sel >> 3u) & 1u) != 0u) ? 0xd02d30cau : 0xb0cef8f4u); // s36 add
r4 = r3 * r2 + r4; // s37 mad
r5 = r7 * r7 + r5; // s38 mad
r3 = r3 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x82e98a22u : 0x2bd506e2u); // s39 add
r0 = rotl_imm(r0, 21u); // s40 rotl
r1 = r1 | r0; // s41 or
r7 = r7 + r5 + ((((sel >> 28u) & 1u) != 0u) ? 0x6435f6d8u : 0xc0386e49u); // s42 add
r1 = mul_hi(r1, r0); // s43 mulhi
r5 = r5 + r6 + ((((sel >> 12u) & 1u) != 0u) ? 0x1f682c68u : 0x3a8921a4u); // s44 add
r4 = r4 + r5 + ((((sel >> 1u) & 1u) != 0u) ? 0xf246e180u : 0xeeca4334u); // s45 add
r2 = r2 ^ r3; // s46 xor
r2 = r2 ^ r5; // s47 xor
r7 = r4 * r1 + r7; // s48 mad
r2 = r6 * r1 + r2; // s49 mad
r7 = r0 * r7 + r7; // s50 mad
r5 = r5 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x41bd68ccu : 0x745776d8u); // s51 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 1u); r3 = r3 ^ t_; } // s52 shfl
r4 = r4 | r0; // s53 or
r0 = r2 * r4 + r0; // s54 mad
r5 = rotl_imm(r5, 9u); // s55 rotl
r5 = r5 * r7; // s56 mul
r7 = rotl_imm(r7, 27u); // s57 rotl
r7 = r7 - r6; // s58 sub
r2 = rotl_imm(r2, 22u); // s59 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r7 = r7 ^ t_; } // s60 shfl
r4 = r4 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xcba6a161u : 0x60d0ff55u); // s61 add
r1 = r1 * r5; // s62 mul
r7 = mul_hi(r7, r6); // s63 mulhi
r5 = r5 * r0; // s64 mul
r2 = rotr_var(r2, r5); // s65 rotr
r0 = mul_hi(r0, r3); // s66 mulhi
r0 = r0 | r7; // s67 or
r0 = rotl_imm(r0, 19u); // s68 rotl
r0 = rotl_imm(r0, 1u); // s69 rotl
r2 = r2 | r3; // s70 or
r3 = r7 * r5 + r3; // s71 mad
r7 = r0 * r4 + r7; // s72 mad
r4 = r4 | r3; // s73 or
r3 = r3 ^ r1; // s74 xor
r1 = r1 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x8e35924eu : 0x3f4ffea2u); // s75 add
r1 = r1 * r3; // s76 mul
r0 = r3 * r2 + r0; // s77 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 16u); r2 = r2 ^ t_; } // s78 shfl
r1 = mul_hi(r1, r0); // s79 mulhi
r0 = mul_hi(r0, r4); // s80 mulhi
r4 = r4 * r2; // s81 mul
r5 = r5 - r7; // s82 sub
r0 = r2 * r3 + r0; // s83 mad
r7 = r7 - r2; // s84 sub
r1 = r1 ^ r2; // s85 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 16u); r6 = r6 ^ t_; } // s86 shfl
r3 = r0 * r0 + r3; // s87 mad
r0 = rotl_imm(r0, 20u); // s88 rotl
r1 = r1 - r5; // s89 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r6 = r6 ^ t_; } // s90 shfl
r5 = r5 ^ r1; // s91 xor
r5 = rotl_imm(r5, 12u); // s92 rotl
r6 = r1 * r2 + r6; // s93 mad
r2 = rotr_var(r2, r5); // s94 rotr
r0 = r0 | r4; // s95 or
r7 = r7 * r3; // s96 mul
r5 = r5 | r0; // s97 or
r3 = r3 + r1 + ((((sel >> 13u) & 1u) != 0u) ? 0x386bb642u : 0xbcfdd8a7u); // s98 add
r0 = r0 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xa3962d03u : 0xc921a021u); // s99 add
r1 = rotr_var(r1, r0); // s100 rotr
r2 = r2 + r4 + ((((sel >> 18u) & 1u) != 0u) ? 0xc5990c5cu : 0x70da4067u); // s101 add
r2 = rotl_imm(r2, 3u); // s102 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 4u); r1 = r1 ^ t_; } // s103 shfl
r0 = r0 ^ r2; // s104 xor
r4 = r4 + r3 + ((((sel >> 28u) & 1u) != 0u) ? 0xb15aec75u : 0x1a5880cbu); // s105 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 2u); r4 = r4 ^ t_; } // s106 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r7 = r7 ^ t_; } // s107 shfl
r1 = r7 * r3 + r1; // s108 mad
r0 = r2 * r3 + r0; // s109 mad
r2 = r2 | r4; // s110 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 1u); r6 = r6 ^ t_; } // s111 shfl
r2 = r5 * r3 + r2; // s112 mad
r4 = mul_hi(r4, r0); // s113 mulhi
r7 = rotl_imm(r7, 29u); // s114 rotl
r3 = r3 - r7; // s115 sub
r0 = mul_hi(r0, r1); // s116 mulhi
r4 = rotl_imm(r4, 12u); // s117 rotl
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0xc5e98ee5u : 0x24494ad3u); // s118 add
r0 = r0 + r4 + ((((sel >> 4u) & 1u) != 0u) ? 0xa97bc949u : 0x1b2d1c83u); // s119 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 4u); r5 = r5 ^ t_; } // s120 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r3 = r3 ^ t_; } // s121 shfl
r7 = rotl_imm(r7, 3u); // s122 rotl
r4 = rotr_var(r4, r6); // s123 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r6 = r6 ^ t_; } // s124 shfl
r5 = rotl_imm(r5, 21u); // s125 rotl
r0 = r3 * r1 + r0; // s126 mad
r0 = r0 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0xa7f6bb54u : 0xff14c08du); // s127 add
r7 = r7 ^ r4; // s128 xor
r3 = mul_hi(r3, r5); // s129 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r5 = r5 ^ t_; } // s130 shfl
r6 = mul_hi(r6, r4); // s131 mulhi
r5 = r5 ^ r3; // s132 xor
r0 = rotl_imm(r0, 19u); // s133 rotl
r4 = rotr_var(r4, r3); // s134 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 16u); r1 = r1 ^ t_; } // s135 shfl
r5 = r5 - r2; // s136 sub
r3 = r3 ^ r5; // s137 xor
r0 = r0 - r2; // s138 sub
r3 = r3 * r7; // s139 mul
r5 = r5 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0x2d465ca8u : 0x82ab98f4u); // s140 add
r4 = r4 + r1 + ((((sel >> 11u) & 1u) != 0u) ? 0x237a9d8eu : 0x80594390u); // s141 add
r3 = r7 * r0 + r3; // s142 mad
r0 = r0 | r3; // s143 or
r0 = mul_hi(r0, r1); // s144 mulhi
r6 = r6 ^ r2; // s145 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r7 = r7 ^ t_; } // s146 shfl
r0 = r0 + r1 + ((((sel >> 18u) & 1u) != 0u) ? 0xe68cf57eu : 0x07f15148u); // s147 add
r7 = r7 | r3; // s148 or
r4 = r4 ^ r2; // s149 xor
r7 = r7 ^ r1; // s150 xor
r5 = rotr_var(r5, r2); // s151 rotr
r0 = r0 * r7; // s152 mul
r4 = rotl_imm(r4, 16u); // s153 rotl
r6 = rotr_var(r6, r4); // s154 rotr
r6 = r6 ^ r1; // s155 xor
r6 = r6 | r3; // s156 or
r1 = r1 + r6 + ((((sel >> 19u) & 1u) != 0u) ? 0x84c2a09du : 0x14878c5au); // s157 add
r4 = r4 - r1; // s158 sub
r4 = r6 * r7 + r4; // s159 mad
r1 = r1 * r5; // s160 mul
r4 = r4 | r0; // s161 or
r7 = rotl_imm(r7, 21u); // s162 rotl
r0 = r0 - r1; // s163 sub
r1 = r1 * r0; // s164 mul
r2 = r2 - r1; // s165 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r0 = r0 ^ t_; } // s166 shfl
r0 = r0 - r4; // s167 sub
r1 = rotr_var(r1, r6); // s168 rotr
r7 = rotr_var(r7, r1); // s169 rotr
r3 = r1 * r3 + r3; // s170 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // s171 shfl
r2 = r2 - r1; // s172 sub
r7 = r7 ^ r6; // s173 xor
r4 = rotr_var(r4, r1); // s174 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r4 = r4 ^ t_; } // s175 shfl
r6 = r6 * r2; // s176 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r0 = r0 ^ t_; } // s177 shfl
r6 = r6 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0x509871e6u : 0x4fa43965u); // s178 add
r0 = r0 ^ r6; // s179 xor
r5 = r5 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb95b8a53u : 0xfb3c4bd8u); // s180 add
r6 = r6 * r3; // s181 mul
r7 = rotl_imm(r7, 1u); // s182 rotl
r0 = r0 + r7 + ((((sel >> 11u) & 1u) != 0u) ? 0x7047b7cfu : 0xc448a197u); // s183 add
r3 = r3 * r5; // s184 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 1u); r5 = r5 ^ t_; } // s185 shfl
r0 = r0 * r2; // s186 mul
r4 = mul_hi(r4, r7); // s187 mulhi
r2 = r7 * r2 + r2; // s188 mad
r7 = r7 - r2; // s189 sub
r2 = r2 + r5 + ((((sel >> 19u) & 1u) != 0u) ? 0x5caccc5du : 0x2fceaf49u); // s190 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r1 = r1 ^ t_; } // s191 shfl
r7 = r7 + r1 + ((((sel >> 20u) & 1u) != 0u) ? 0x857bb5feu : 0xba0cee62u); // s192 add
r6 = rotl_imm(r6, 22u); // s193 rotl
r3 = r3 ^ r7; // s194 xor
r7 = r7 * r0; // s195 mul
r3 = r3 ^ r5; // s196 xor
r5 = r5 + r1 + ((((sel >> 29u) & 1u) != 0u) ? 0xeae84577u : 0x8519428cu); // s197 add
r7 = r4 * r4 + r7; // s198 mad
r3 = r3 + r6 + ((((sel >> 8u) & 1u) != 0u) ? 0x0bfdbfa1u : 0x468639d3u); // s199 add
r5 = r3 * r4 + r5; // s200 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r2 = r2 ^ t_; } // s201 shfl
r7 = r7 + r4 + ((((sel >> 23u) & 1u) != 0u) ? 0x53ee8e50u : 0x18ec9a69u); // s202 add
r6 = r6 ^ r0; // s203 xor
r4 = r4 + r5 + ((((sel >> 4u) & 1u) != 0u) ? 0xac63376eu : 0x3e81485bu); // s204 add
r7 = r1 * r4 + r7; // s205 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r1 = r1 ^ t_; } // s206 shfl
r4 = r4 * r0; // s207 mul
r1 = r1 | r6; // s208 or
r6 = r6 + r4 + ((((sel >> 28u) & 1u) != 0u) ? 0x5b745519u : 0x66ccb75du); // s209 add
r1 = rotr_var(r1, r3); // s210 rotr
r5 = r5 - r4; // s211 sub
r4 = r4 ^ r7; // s212 xor
r1 = r1 + r7 + ((((sel >> 8u) & 1u) != 0u) ? 0x1c3dccf7u : 0x0ce0553du); // s213 add
r0 = mul_hi(r0, r1); // s214 mulhi
r3 = r3 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xfadc9205u : 0x96bfec89u); // s215 add
r0 = rotl_imm(r0, 4u); // s216 rotl
r6 = r6 ^ r4; // s217 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r6 = r6 ^ t_; } // s218 shfl
r7 = r0 * r1 + r7; // s219 mad
r4 = r4 * r0; // s220 mul
r2 = r6 * r0 + r2; // s221 mad
r5 = r5 ^ r4; // s222 xor
r0 = r0 * r5; // s223 mul
r2 = r2 + r0 + ((((sel >> 9u) & 1u) != 0u) ? 0x66b15c04u : 0x61495681u); // s224 add
r3 = rotr_var(r3, r2); // s225 rotr
r2 = r3 * r3 + r2; // s226 mad
r6 = r6 ^ r0; // s227 xor
r4 = rotl_imm(r4, 30u); // s228 rotl
r2 = r2 + r3 + ((((sel >> 29u) & 1u) != 0u) ? 0x25bc17c2u : 0x70d05c34u); // s229 add
r1 = rotr_var(r1, r5); // s230 rotr
r1 = r1 + r4 + ((((sel >> 8u) & 1u) != 0u) ? 0x2d8728f3u : 0x32a28384u); // s231 add
r1 = rotl_imm(r1, 6u); // s232 rotl
r2 = r2 + r0 + ((((sel >> 21u) & 1u) != 0u) ? 0x61e81fe6u : 0xcf0949f1u); // s233 add
r4 = rotl_imm(r4, 2u); // s234 rotl
r2 = r2 - r6; // s235 sub
r6 = r6 | r3; // s236 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r7 = r7 ^ t_; } // s237 shfl
r1 = r1 ^ r3; // s238 xor
r2 = rotl_imm(r2, 1u); // s239 rotl
r5 = rotr_var(r5, r2); // s240 rotr
r4 = rotl_imm(r4, 10u); // s241 rotl
r6 = r6 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0x0a67565du : 0xe204fb50u); // s242 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 2u); r1 = r1 ^ t_; } // s243 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r0 = r0 ^ t_; } // s244 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r5 = r5 ^ t_; } // s245 shfl
r4 = r4 ^ r5; // s246 xor
r7 = r7 ^ r2; // s247 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 16u); r0 = r0 ^ t_; } // s248 shfl
r1 = mul_hi(r1, r3); // s249 mulhi
r7 = r7 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x5a79fd6fu : 0x3d6daffdu); // s250 add
r6 = r6 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x6beb28c2u : 0x84334aeau); // s251 add
r7 = r7 - r1; // s252 sub
r5 = rotr_var(r5, r2); // s253 rotr
r2 = mul_hi(r2, r5); // s254 mulhi
r6 = r6 * r3; // s255 mul
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}
#if IGNEUM_EXCHANGE != 0
// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
}
#endif

View file

@ -0,0 +1,423 @@
// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000". Do not edit by hand.
// Bit-exact twin of the Metal kernel for the same seed (see proto-cuda/CHECKLIST.md and program.metal).
// Compiled ahead of time by nvcc together with proto-cuda/host.cu. No NVRTC.
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
#include "memhard.h"
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site, so both shift amounts are in 1..31.
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
// n is masked to 0..31; the second shift amount is masked too, so n == 0 gives x.
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__device__ __forceinline__ uint32_t ds_elem(uint32_t i, uint32_t d0, uint32_t d1) {
uint32_t x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset (MEMHARD.md). One thread per cache segment; one thread per 64-byte dataset item.
// The core functions (mh_cache_segment, mh_item) are in memhard.h and are also compiled for the host.
__global__ void igneum_cache_fill(uint32_t* cache, uint32_t nSegments) {
uint32_t seg = blockIdx.x * blockDim.x + threadIdx.x;
if (seg < nSegments) mh_cache_segment(cache, seg);
}
// Class v5: the window's leaves (leaves.bin, IGNEUM_STATE_LEAVES x 16 words) and their count.
__global__ void igneum_build(uint32_t* ds, const uint32_t* cache, const uint32_t* leaves, uint32_t nLeaves, uint32_t nItems) {
uint32_t t = blockIdx.x * blockDim.x + threadIdx.x;
if (t < nItems) {
uint32_t s[16];
mh_item(cache, mh_leaf(leaves, nLeaves, t), t, s);
for (uint32_t i = 0u; i < 16u; ++i) ds[(size_t)mh_addr(t, i)] = s[i];
}
}
// One hash per thread. blockDim.x is a multiple of 32; lane = threadIdx.x & 31 and every
// __shfl_xor_sync stays inside the lane's own warp, exactly like simd_shuffle_xor inside a
// 32-wide Metal SIMD group. Control flow is uniform, so the full 0xffffffff member mask is valid.
__global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ 0xbe8c5a0cu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x7646e626u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint32_t x = nonce ^ 0x7646e626u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0x508e29d0u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint32_t x = nonce ^ 0x508e29d0u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0xfb8a5b4au; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint32_t x = nonce ^ 0xfb8a5b4au; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0x53c50955u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint32_t x = nonce ^ 0x53c50955u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0x685d62fcu; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint32_t x = nonce ^ 0x685d62fcu; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x6065c013u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint32_t x = nonce ^ 0x6065c013u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x881096ebu; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint32_t x = nonce ^ 0x881096ebu; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0xbe8c5a0cu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r6 = r6 - r3; // 0 sub
r2 = r2 | r6; // 1 or
r4 = r4 + r0 + ((((sel >> 4u) & 1u) != 0u) ? 0x7731324bu : 0x1a579b38u); // 2 add
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 3 load
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // 4 shfl
r4 = r4 ^ r1; // 5 xor
r3 = r5 * r3 + r3; // 6 mad
r1 = r1 * r6; // 7 mul
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x08000000u) & mask]; // 8 load
r0 = r0 ^ r4; // 9 xor
r0 = r0 + r7 + ((((sel >> 30u) & 1u) != 0u) ? 0xb10fcef8u : 0xee083919u); // 10 add
r0 = __umulhi(r0, r2); // 11 mulhi
r5 = r5 ^ r4; // 12 xor
r7 = r3 * r0 + r7; // 13 mad
r3 = r3 ^ ds[((rotl_imm(r4 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 14 load
r2 = r2 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 15 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 16 shfl
r7 = r7 * r6; // 17 mul
r2 = r3 * r1 + r2; // 18 mad
r5 = rotr_var(r5, r2); // 19 rotr
r5 = r5 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 20 load
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r1 = __umulhi(r1, r2); // 22 mulhi
r6 = r6 ^ r5; // 23 xor
r5 = r2 * r0 + r5; // 24 mad
r6 = r3 * r7 + r6; // 25 mad
r6 = r6 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 26 load
r1 = r5 * r5 + r1; // 27 mad
r0 = r0 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 28 load
r7 = r7 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x0b1f02c7u : 0xd5e6c37cu); // 29 add
r7 = r7 + r0 + ((((sel >> 0u) & 1u) != 0u) ? 0x2d6e8bd1u : 0x4e45ba51u); // 30 add
r0 = r0 ^ r2; // 31 xor
r6 = r6 + r2 + ((((sel >> 13u) & 1u) != 0u) ? 0x351422d2u : 0x1c91b2a1u); // 32 add
r4 = __umulhi(r4, r5); // 33 mulhi
r3 = rotr_var(r3, r5); // 34 rotr
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 35 load
r4 = rotl_imm(r4, 13u); // 36 rotl
r6 = r6 + r1 + ((((sel >> 7u) & 1u) != 0u) ? 0x64a28251u : 0x3f2970f7u); // 37 add
r2 = r2 * r0; // 38 mul
r3 = r3 + r4 + ((((sel >> 15u) & 1u) != 0u) ? 0x7378c955u : 0x3b7b3317u); // 39 add
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 40 load
r6 = r6 ^ r5; // 41 xor
r3 = r3 + r0 + ((((sel >> 2u) & 1u) != 0u) ? 0xb31f6a64u : 0x6678b059u); // 42 add
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 43 load
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 44 shfl
r1 = __umulhi(r1, r5); // 45 mulhi
r0 = rotl_imm(r0, 6u); // 46 rotl
r1 = r1 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 47 load
r4 = r4 + r0 + ((((sel >> 17u) & 1u) != 0u) ? 0x5feccee6u : 0x43095946u); // 48 add
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 49 load
r2 = r2 - r3; // 50 sub
r7 = r7 + r2 + ((((sel >> 24u) & 1u) != 0u) ? 0x26e2b582u : 0xf45ecdf8u); // 51 add
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 52 load
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 53 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 54 shfl
r1 = rotr_var(r1, r2); // 55 rotr
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 56 shfl
r5 = rotl_imm(r5, 12u); // 57 rotl
r5 = r5 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x473b1718u : 0x6b4f35e8u); // 58 add
r4 = rotr_var(r4, r1); // 59 rotr
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 60 shfl
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 61 load
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 62 load
r4 = r4 * r1; // 63 mul
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint32_t sh = 0u; sh < 27u; ++sh) {
r6 = r6 | r0; // s0 or
r7 = r7 * r3; // s1 mul
r3 = r5 * r5 + r3; // s2 mad
r7 = r7 + r4 + ((((sel >> 6u) & 1u) != 0u) ? 0x38e58a06u : 0x97d3d105u); // s3 add
r6 = r6 + r0 + ((((sel >> 20u) & 1u) != 0u) ? 0x9629673du : 0x29b87b9au); // s4 add
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // s5 shfl
r5 = r3 * r5 + r5; // s6 mad
r3 = rotl_imm(r3, 5u); // s7 rotl
r0 = r0 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0x4a5f55e1u : 0xa7c1fb0fu); // s8 add
r5 = r5 * r7; // s9 mul
r4 = r4 ^ r5; // s10 xor
r6 = __umulhi(r6, r4); // s11 mulhi
r5 = rotl_imm(r5, 13u); // s12 rotl
r0 = r2 * r1 + r0; // s13 mad
r2 = __umulhi(r2, r4); // s14 mulhi
r3 = r3 | r1; // s15 or
r0 = r0 - r5; // s16 sub
r0 = r0 * r6; // s17 mul
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r1, 4); // s18 shfl
r3 = r3 | r4; // s19 or
r6 = r3 * r2 + r6; // s20 mad
r0 = rotl_imm(r0, 11u); // s21 rotl
r3 = rotl_imm(r3, 25u); // s22 rotl
r6 = r6 ^ r4; // s23 xor
r4 = r4 | r2; // s24 or
r1 = r1 + r6 + ((((sel >> 7u) & 1u) != 0u) ? 0xfc2f6d17u : 0x53e74799u); // s25 add
r7 = rotr_var(r7, r6); // s26 rotr
r7 = r7 + r5 + ((((sel >> 27u) & 1u) != 0u) ? 0x787048dcu : 0xb8fae90eu); // s27 add
r4 = r4 ^ r1; // s28 xor
r6 = r6 ^ r1; // s29 xor
r2 = __umulhi(r2, r0); // s30 mulhi
r1 = rotr_var(r1, r4); // s31 rotr
r7 = r7 ^ r4; // s32 xor
r3 = r2 * r6 + r3; // s33 mad
r3 = r3 + r1 + ((((sel >> 12u) & 1u) != 0u) ? 0x9ffd510bu : 0xd2dc42ebu); // s34 add
r4 = r4 + r7 + ((((sel >> 7u) & 1u) != 0u) ? 0xf871ba37u : 0xad8eda6fu); // s35 add
r7 = r7 + r4 + ((((sel >> 3u) & 1u) != 0u) ? 0xd02d30cau : 0xb0cef8f4u); // s36 add
r4 = r3 * r2 + r4; // s37 mad
r5 = r7 * r7 + r5; // s38 mad
r3 = r3 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x82e98a22u : 0x2bd506e2u); // s39 add
r0 = rotl_imm(r0, 21u); // s40 rotl
r1 = r1 | r0; // s41 or
r7 = r7 + r5 + ((((sel >> 28u) & 1u) != 0u) ? 0x6435f6d8u : 0xc0386e49u); // s42 add
r1 = __umulhi(r1, r0); // s43 mulhi
r5 = r5 + r6 + ((((sel >> 12u) & 1u) != 0u) ? 0x1f682c68u : 0x3a8921a4u); // s44 add
r4 = r4 + r5 + ((((sel >> 1u) & 1u) != 0u) ? 0xf246e180u : 0xeeca4334u); // s45 add
r2 = r2 ^ r3; // s46 xor
r2 = r2 ^ r5; // s47 xor
r7 = r4 * r1 + r7; // s48 mad
r2 = r6 * r1 + r2; // s49 mad
r7 = r0 * r7 + r7; // s50 mad
r5 = r5 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x41bd68ccu : 0x745776d8u); // s51 add
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r0, 1); // s52 shfl
r4 = r4 | r0; // s53 or
r0 = r2 * r4 + r0; // s54 mad
r5 = rotl_imm(r5, 9u); // s55 rotl
r5 = r5 * r7; // s56 mul
r7 = rotl_imm(r7, 27u); // s57 rotl
r7 = r7 - r6; // s58 sub
r2 = rotl_imm(r2, 22u); // s59 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s60 shfl
r4 = r4 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xcba6a161u : 0x60d0ff55u); // s61 add
r1 = r1 * r5; // s62 mul
r7 = __umulhi(r7, r6); // s63 mulhi
r5 = r5 * r0; // s64 mul
r2 = rotr_var(r2, r5); // s65 rotr
r0 = __umulhi(r0, r3); // s66 mulhi
r0 = r0 | r7; // s67 or
r0 = rotl_imm(r0, 19u); // s68 rotl
r0 = rotl_imm(r0, 1u); // s69 rotl
r2 = r2 | r3; // s70 or
r3 = r7 * r5 + r3; // s71 mad
r7 = r0 * r4 + r7; // s72 mad
r4 = r4 | r3; // s73 or
r3 = r3 ^ r1; // s74 xor
r1 = r1 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x8e35924eu : 0x3f4ffea2u); // s75 add
r1 = r1 * r3; // s76 mul
r0 = r3 * r2 + r0; // s77 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 16); // s78 shfl
r1 = __umulhi(r1, r0); // s79 mulhi
r0 = __umulhi(r0, r4); // s80 mulhi
r4 = r4 * r2; // s81 mul
r5 = r5 - r7; // s82 sub
r0 = r2 * r3 + r0; // s83 mad
r7 = r7 - r2; // s84 sub
r1 = r1 ^ r2; // s85 xor
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 16); // s86 shfl
r3 = r0 * r0 + r3; // s87 mad
r0 = rotl_imm(r0, 20u); // s88 rotl
r1 = r1 - r5; // s89 sub
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // s90 shfl
r5 = r5 ^ r1; // s91 xor
r5 = rotl_imm(r5, 12u); // s92 rotl
r6 = r1 * r2 + r6; // s93 mad
r2 = rotr_var(r2, r5); // s94 rotr
r0 = r0 | r4; // s95 or
r7 = r7 * r3; // s96 mul
r5 = r5 | r0; // s97 or
r3 = r3 + r1 + ((((sel >> 13u) & 1u) != 0u) ? 0x386bb642u : 0xbcfdd8a7u); // s98 add
r0 = r0 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xa3962d03u : 0xc921a021u); // s99 add
r1 = rotr_var(r1, r0); // s100 rotr
r2 = r2 + r4 + ((((sel >> 18u) & 1u) != 0u) ? 0xc5990c5cu : 0x70da4067u); // s101 add
r2 = rotl_imm(r2, 3u); // s102 rotl
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 4); // s103 shfl
r0 = r0 ^ r2; // s104 xor
r4 = r4 + r3 + ((((sel >> 28u) & 1u) != 0u) ? 0xb15aec75u : 0x1a5880cbu); // s105 add
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r0, 2); // s106 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // s107 shfl
r1 = r7 * r3 + r1; // s108 mad
r0 = r2 * r3 + r0; // s109 mad
r2 = r2 | r4; // s110 or
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 1); // s111 shfl
r2 = r5 * r3 + r2; // s112 mad
r4 = __umulhi(r4, r0); // s113 mulhi
r7 = rotl_imm(r7, 29u); // s114 rotl
r3 = r3 - r7; // s115 sub
r0 = __umulhi(r0, r1); // s116 mulhi
r4 = rotl_imm(r4, 12u); // s117 rotl
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0xc5e98ee5u : 0x24494ad3u); // s118 add
r0 = r0 + r4 + ((((sel >> 4u) & 1u) != 0u) ? 0xa97bc949u : 0x1b2d1c83u); // s119 add
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 4); // s120 shfl
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s121 shfl
r7 = rotl_imm(r7, 3u); // s122 rotl
r4 = rotr_var(r4, r6); // s123 rotr
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // s124 shfl
r5 = rotl_imm(r5, 21u); // s125 rotl
r0 = r3 * r1 + r0; // s126 mad
r0 = r0 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0xa7f6bb54u : 0xff14c08du); // s127 add
r7 = r7 ^ r4; // s128 xor
r3 = __umulhi(r3, r5); // s129 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 8); // s130 shfl
r6 = __umulhi(r6, r4); // s131 mulhi
r5 = r5 ^ r3; // s132 xor
r0 = rotl_imm(r0, 19u); // s133 rotl
r4 = rotr_var(r4, r3); // s134 rotr
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 16); // s135 shfl
r5 = r5 - r2; // s136 sub
r3 = r3 ^ r5; // s137 xor
r0 = r0 - r2; // s138 sub
r3 = r3 * r7; // s139 mul
r5 = r5 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0x2d465ca8u : 0x82ab98f4u); // s140 add
r4 = r4 + r1 + ((((sel >> 11u) & 1u) != 0u) ? 0x237a9d8eu : 0x80594390u); // s141 add
r3 = r7 * r0 + r3; // s142 mad
r0 = r0 | r3; // s143 or
r0 = __umulhi(r0, r1); // s144 mulhi
r6 = r6 ^ r2; // s145 xor
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s146 shfl
r0 = r0 + r1 + ((((sel >> 18u) & 1u) != 0u) ? 0xe68cf57eu : 0x07f15148u); // s147 add
r7 = r7 | r3; // s148 or
r4 = r4 ^ r2; // s149 xor
r7 = r7 ^ r1; // s150 xor
r5 = rotr_var(r5, r2); // s151 rotr
r0 = r0 * r7; // s152 mul
r4 = rotl_imm(r4, 16u); // s153 rotl
r6 = rotr_var(r6, r4); // s154 rotr
r6 = r6 ^ r1; // s155 xor
r6 = r6 | r3; // s156 or
r1 = r1 + r6 + ((((sel >> 19u) & 1u) != 0u) ? 0x84c2a09du : 0x14878c5au); // s157 add
r4 = r4 - r1; // s158 sub
r4 = r6 * r7 + r4; // s159 mad
r1 = r1 * r5; // s160 mul
r4 = r4 | r0; // s161 or
r7 = rotl_imm(r7, 21u); // s162 rotl
r0 = r0 - r1; // s163 sub
r1 = r1 * r0; // s164 mul
r2 = r2 - r1; // s165 sub
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // s166 shfl
r0 = r0 - r4; // s167 sub
r1 = rotr_var(r1, r6); // s168 rotr
r7 = rotr_var(r7, r1); // s169 rotr
r3 = r1 * r3 + r3; // s170 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // s171 shfl
r2 = r2 - r1; // s172 sub
r7 = r7 ^ r6; // s173 xor
r4 = rotr_var(r4, r1); // s174 rotr
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s175 shfl
r6 = r6 * r2; // s176 mul
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // s177 shfl
r6 = r6 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0x509871e6u : 0x4fa43965u); // s178 add
r0 = r0 ^ r6; // s179 xor
r5 = r5 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb95b8a53u : 0xfb3c4bd8u); // s180 add
r6 = r6 * r3; // s181 mul
r7 = rotl_imm(r7, 1u); // s182 rotl
r0 = r0 + r7 + ((((sel >> 11u) & 1u) != 0u) ? 0x7047b7cfu : 0xc448a197u); // s183 add
r3 = r3 * r5; // s184 mul
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 1); // s185 shfl
r0 = r0 * r2; // s186 mul
r4 = __umulhi(r4, r7); // s187 mulhi
r2 = r7 * r2 + r2; // s188 mad
r7 = r7 - r2; // s189 sub
r2 = r2 + r5 + ((((sel >> 19u) & 1u) != 0u) ? 0x5caccc5du : 0x2fceaf49u); // s190 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // s191 shfl
r7 = r7 + r1 + ((((sel >> 20u) & 1u) != 0u) ? 0x857bb5feu : 0xba0cee62u); // s192 add
r6 = rotl_imm(r6, 22u); // s193 rotl
r3 = r3 ^ r7; // s194 xor
r7 = r7 * r0; // s195 mul
r3 = r3 ^ r5; // s196 xor
r5 = r5 + r1 + ((((sel >> 29u) & 1u) != 0u) ? 0xeae84577u : 0x8519428cu); // s197 add
r7 = r4 * r4 + r7; // s198 mad
r3 = r3 + r6 + ((((sel >> 8u) & 1u) != 0u) ? 0x0bfdbfa1u : 0x468639d3u); // s199 add
r5 = r3 * r4 + r5; // s200 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // s201 shfl
r7 = r7 + r4 + ((((sel >> 23u) & 1u) != 0u) ? 0x53ee8e50u : 0x18ec9a69u); // s202 add
r6 = r6 ^ r0; // s203 xor
r4 = r4 + r5 + ((((sel >> 4u) & 1u) != 0u) ? 0xac63376eu : 0x3e81485bu); // s204 add
r7 = r1 * r4 + r7; // s205 mad
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s206 shfl
r4 = r4 * r0; // s207 mul
r1 = r1 | r6; // s208 or
r6 = r6 + r4 + ((((sel >> 28u) & 1u) != 0u) ? 0x5b745519u : 0x66ccb75du); // s209 add
r1 = rotr_var(r1, r3); // s210 rotr
r5 = r5 - r4; // s211 sub
r4 = r4 ^ r7; // s212 xor
r1 = r1 + r7 + ((((sel >> 8u) & 1u) != 0u) ? 0x1c3dccf7u : 0x0ce0553du); // s213 add
r0 = __umulhi(r0, r1); // s214 mulhi
r3 = r3 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xfadc9205u : 0x96bfec89u); // s215 add
r0 = rotl_imm(r0, 4u); // s216 rotl
r6 = r6 ^ r4; // s217 xor
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s218 shfl
r7 = r0 * r1 + r7; // s219 mad
r4 = r4 * r0; // s220 mul
r2 = r6 * r0 + r2; // s221 mad
r5 = r5 ^ r4; // s222 xor
r0 = r0 * r5; // s223 mul
r2 = r2 + r0 + ((((sel >> 9u) & 1u) != 0u) ? 0x66b15c04u : 0x61495681u); // s224 add
r3 = rotr_var(r3, r2); // s225 rotr
r2 = r3 * r3 + r2; // s226 mad
r6 = r6 ^ r0; // s227 xor
r4 = rotl_imm(r4, 30u); // s228 rotl
r2 = r2 + r3 + ((((sel >> 29u) & 1u) != 0u) ? 0x25bc17c2u : 0x70d05c34u); // s229 add
r1 = rotr_var(r1, r5); // s230 rotr
r1 = r1 + r4 + ((((sel >> 8u) & 1u) != 0u) ? 0x2d8728f3u : 0x32a28384u); // s231 add
r1 = rotl_imm(r1, 6u); // s232 rotl
r2 = r2 + r0 + ((((sel >> 21u) & 1u) != 0u) ? 0x61e81fe6u : 0xcf0949f1u); // s233 add
r4 = rotl_imm(r4, 2u); // s234 rotl
r2 = r2 - r6; // s235 sub
r6 = r6 | r3; // s236 or
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // s237 shfl
r1 = r1 ^ r3; // s238 xor
r2 = rotl_imm(r2, 1u); // s239 rotl
r5 = rotr_var(r5, r2); // s240 rotr
r4 = rotl_imm(r4, 10u); // s241 rotl
r6 = r6 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0x0a67565du : 0xe204fb50u); // s242 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r3, 2); // s243 shfl
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s244 shfl
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s245 shfl
r4 = r4 ^ r5; // s246 xor
r7 = r7 ^ r2; // s247 xor
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r6, 16); // s248 shfl
r1 = __umulhi(r1, r3); // s249 mulhi
r7 = r7 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x5a79fd6fu : 0x3d6daffdu); // s250 add
r6 = r6 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x6beb28c2u : 0x84334aeau); // s251 add
r7 = r7 - r1; // s252 sub
r5 = rotr_var(r5, r2); // s253 rotr
r2 = __umulhi(r2, r5); // s254 mulhi
r6 = r6 * r3; // s255 mul
}
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
// Host-side launch wrappers. Declared in program.h, called from host.cu.
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments) {
if (nSegments == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nSegments + block - 1u) / block;
igneum_cache_fill<<<grid, block>>>(cache, nSegments);
return cudaGetLastError();
}
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, const uint32_t* leaves, uint32_t nLeaves, uint32_t nItems) {
if (nItems == 0u || nLeaves == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nItems + block - 1u) / block;
igneum_build<<<grid, block>>>(ds, cache, leaves, nLeaves, nItems);
return cudaGetLastError();
}
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash<<<nonces / block, block>>>(ds, out, baseNonce, mask);
return cudaGetLastError();
}
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash, (int)(32u * blockWarps), 0);
}

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@ -0,0 +1,898 @@
// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000". Do not edit by hand.
// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
// Built from source at runtime by proto-opencl/host.c, which passes these defines:
// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
#ifndef IGNEUM_GROUP
#define IGNEUM_GROUP 32
#endif
#ifndef IGNEUM_EXCHANGE
#define IGNEUM_EXCHANGE 0
#endif
#ifdef __OPENCL_VERSION__
#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
#if IGNEUM_EXCHANGE == 1
#ifdef cl_khr_subgroups
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
#endif
#ifdef cl_khr_subgroup_shuffle
#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
#endif
#elif IGNEUM_EXCHANGE == 2
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
#endif
#else
// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
#include "emu_opencl.h"
#endif
#if IGNEUM_EXCHANGE == 1
#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#elif IGNEUM_EXCHANGE == 2
#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#else
// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
#endif
static inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
static inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
static inline void mh_chacha_block(const uint* x, uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
static inline void mh_cache_segment(__global uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0xe23f9008u ^ prev[4];
x[5] = 0xde33e763u ^ prev[5];
x[6] = 0xc5ba415du ^ prev[6];
x[7] = 0x8ddf6786u ^ prev[7];
x[8] = 0x59f4a4beu ^ prev[8];
x[9] = 0x8a3bc680u ^ prev[9];
x[10] = 0x701b8e40u ^ prev[10];
x[11] = 0x3b59025au ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
static inline void mh_mixer(uint* s, uint rk) {
s[0] = (s[0] ^ (0xe5bef5a3u + rk)) * 0xd1d79e7fu;
s[1] = (s[1] ^ (0xdb2a7d90u + rk)) * 0xbcb61f8bu;
s[2] = (s[2] ^ (0xcd1fa7e1u + rk)) * 0x970e91abu;
s[3] = (s[3] ^ (0x30289419u + rk)) * 0xd749d96du;
s[4] = (s[4] ^ (0x0a730d58u + rk)) * 0x143d7339u;
s[5] = (s[5] ^ (0x432f8579u + rk)) * 0x2cde0d69u;
s[6] = (s[6] ^ (0x6ab978a5u + rk)) * 0x12d0a8c1u;
s[7] = (s[7] ^ (0x8c984f49u + rk)) * 0x2d335be9u;
s[8] = (s[8] ^ (0x788c3c9eu + rk)) * 0x80a8aae9u;
s[9] = (s[9] ^ (0x051eef02u + rk)) * 0x7ac896c7u;
s[10] = (s[10] ^ (0x05e77db9u + rk)) * 0x9de23db7u;
s[11] = (s[11] ^ (0x8b3cd4f3u + rk)) * 0xc362827du;
s[12] = (s[12] ^ (0x6948d6cfu + rk)) * 0x5f4cdb5bu;
s[13] = (s[13] ^ (0x0d8677f6u + rk)) * 0xfc6c5097u;
s[14] = (s[14] ^ (0xf9505c8cu + rk)) * 0x6f547f83u;
s[15] = (s[15] ^ (0x4513c163u + rk)) * 0x1ac31b47u;
MH_QR(s[0], s[4], s[8], s[12], 28u, 11u, 18u, 18u) MH_QR(s[1], s[5], s[9], s[13], 28u, 11u, 18u, 18u)
MH_QR(s[2], s[6], s[10], s[14], 28u, 11u, 18u, 18u) MH_QR(s[3], s[7], s[11], s[15], 28u, 11u, 18u, 18u)
MH_QR(s[0], s[5], s[10], s[15], 13u, 28u, 5u, 13u) MH_QR(s[1], s[6], s[11], s[12], 13u, 28u, 5u, 13u)
MH_QR(s[2], s[7], s[8], s[13], 13u, 28u, 5u, 13u) MH_QR(s[3], s[4], s[9], s[14], 13u, 28u, 5u, 13u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
static inline void mh_item(__global const uint* cache, __global const uint* leaf, uint t, uint* s) {
s[0] = 0xe23f9008u;
s[1] = 0xde33e763u;
s[2] = 0xc5ba415du;
s[3] = 0x8ddf6786u;
s[4] = 0x59f4a4beu;
s[5] = 0x8a3bc680u;
s[6] = 0x701b8e40u;
s[7] = 0x3b59025au;
s[8] = t * 0xd1d79e7fu + 0xe5bef5a3u;
s[9] = t * 0xbcb61f8bu + 0xdb2a7d90u;
s[10] = t * 0x970e91abu + 0xcd1fa7e1u;
s[11] = t * 0xd749d96du + 0x30289419u;
s[12] = t * 0x143d7339u + 0x0a730d58u;
s[13] = t * 0x2cde0d69u + 0x432f8579u;
s[14] = t * 0x12d0a8c1u + 0x6ab978a5u;
s[15] = t * 0x2d335be9u + 0x8c984f49u;
for (uint i = 0u; i < 16u; ++i) s[i] ^= leaf[i];
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// Class v5 (docs/design/class-v5-stored-state.md): leaf(t) = leaves[t mod nLeaves], 16 words per leaf (leaves.bin).
static inline __global const uint* mh_leaf(__global const uint* leaves, uint nLeaves, uint t) { return leaves + ((t % nLeaves) * 16u); }
// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 1 9 13 14 of w.
static inline uint mh_j(uint w) { return ((w >> 1u) & 1u) | (((w >> 9u) & 1u) << 1) | (((w >> 13u) & 1u) << 2) | (((w >> 14u) & 1u) << 3); }
static inline uint mh_t(uint w) { w = (w & 0x00003fffu) | ((w >> 15u) << 14u); w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x000001ffu) | ((w >> 10u) << 9u); w = (w & 0x00000001u) | ((w >> 2u) << 1u); return w; }
static inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 1u) << 2u) | (w & 0x00000001u) | (((j >> 0u) & 1u) << 1u); w = ((w >> 9u) << 10u) | (w & 0x000001ffu) | (((j >> 1u) & 1u) << 9u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 2u) & 1u) << 13u); w = ((w >> 14u) << 15u) | (w & 0x00003fffu) | (((j >> 3u) & 1u) << 14u); return w; }
// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w).
static inline uint mh_word(__global const uint* cache, __global const uint* leaves, uint nLeaves, uint w) { uint s[16]; mh_item(cache, mh_leaf(leaves, nLeaves, mh_t(w)), mh_t(w), s); return s[mh_j(w)]; }
// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
// The same constants as memhard.h in this pack (one emitter, three dialects).
__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
uint seg = (uint)get_global_id(0);
if (seg < nSegments) mh_cache_segment(cache, seg);
}
// Class v5: the window's leaves (leaves.bin, IGNEUM_STATE_LEAVES x 16 words) and their count.
__kernel void igneum_build(__global uint* ds, __global const uint* cache, __global const uint* leaves, uint nLeaves, uint nItems) {
uint t = (uint)get_global_id(0);
if (t < nItems) {
uint s[16];
mh_item(cache, mh_leaf(leaves, nLeaves, t), t, s);
for (uint i = 0u; i < 16u; ++i) ds[(ulong)mh_addr(t, i)] = s[i];
}
}
// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
{ uint x = nonce ^ 0xbe8c5a0cu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x7646e626u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint x = nonce ^ 0x7646e626u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0x508e29d0u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint x = nonce ^ 0x508e29d0u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0xfb8a5b4au; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint x = nonce ^ 0xfb8a5b4au; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0x53c50955u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint x = nonce ^ 0x53c50955u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0x685d62fcu; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint x = nonce ^ 0x685d62fcu; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x6065c013u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint x = nonce ^ 0x6065c013u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x881096ebu; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint x = nonce ^ 0x881096ebu; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0xbe8c5a0cu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r6 = r6 - r3; // 0 sub
r2 = r2 | r6; // 1 or
r4 = r4 + r0 + ((((sel >> 4u) & 1u) != 0u) ? 0x7731324bu : 0x1a579b38u); // 2 add
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 3 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r0 = r0 ^ t_; } // 4 shfl
r4 = r4 ^ r1; // 5 xor
r3 = r5 * r3 + r3; // 6 mad
r1 = r1 * r6; // 7 mul
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x08000000u) & mask]; // 8 load
r0 = r0 ^ r4; // 9 xor
r0 = r0 + r7 + ((((sel >> 30u) & 1u) != 0u) ? 0xb10fcef8u : 0xee083919u); // 10 add
r0 = mul_hi(r0, r2); // 11 mulhi
r5 = r5 ^ r4; // 12 xor
r7 = r3 * r0 + r7; // 13 mad
r3 = r3 ^ ds[((rotl_imm(r4 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 14 load
r2 = r2 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 15 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r7 = r7 ^ t_; } // 16 shfl
r7 = r7 * r6; // 17 mul
r2 = r3 * r1 + r2; // 18 mad
r5 = rotr_var(r5, r2); // 19 rotr
r5 = r5 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 20 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r6 = r6 ^ t_; } // 21 shfl
r1 = mul_hi(r1, r2); // 22 mulhi
r6 = r6 ^ r5; // 23 xor
r5 = r2 * r0 + r5; // 24 mad
r6 = r3 * r7 + r6; // 25 mad
r6 = r6 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 26 load
r1 = r5 * r5 + r1; // 27 mad
r0 = r0 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 28 load
r7 = r7 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x0b1f02c7u : 0xd5e6c37cu); // 29 add
r7 = r7 + r0 + ((((sel >> 0u) & 1u) != 0u) ? 0x2d6e8bd1u : 0x4e45ba51u); // 30 add
r0 = r0 ^ r2; // 31 xor
r6 = r6 + r2 + ((((sel >> 13u) & 1u) != 0u) ? 0x351422d2u : 0x1c91b2a1u); // 32 add
r4 = mul_hi(r4, r5); // 33 mulhi
r3 = rotr_var(r3, r5); // 34 rotr
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 35 load
r4 = rotl_imm(r4, 13u); // 36 rotl
r6 = r6 + r1 + ((((sel >> 7u) & 1u) != 0u) ? 0x64a28251u : 0x3f2970f7u); // 37 add
r2 = r2 * r0; // 38 mul
r3 = r3 + r4 + ((((sel >> 15u) & 1u) != 0u) ? 0x7378c955u : 0x3b7b3317u); // 39 add
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 40 load
r6 = r6 ^ r5; // 41 xor
r3 = r3 + r0 + ((((sel >> 2u) & 1u) != 0u) ? 0xb31f6a64u : 0x6678b059u); // 42 add
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 43 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r3 = r3 ^ t_; } // 44 shfl
r1 = mul_hi(r1, r5); // 45 mulhi
r0 = rotl_imm(r0, 6u); // 46 rotl
r1 = r1 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 47 load
r4 = r4 + r0 + ((((sel >> 17u) & 1u) != 0u) ? 0x5feccee6u : 0x43095946u); // 48 add
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 49 load
r2 = r2 - r3; // 50 sub
r7 = r7 + r2 + ((((sel >> 24u) & 1u) != 0u) ? 0x26e2b582u : 0xf45ecdf8u); // 51 add
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 52 load
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 53 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r7 = r7 ^ t_; } // 54 shfl
r1 = rotr_var(r1, r2); // 55 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r0 = r0 ^ t_; } // 56 shfl
r5 = rotl_imm(r5, 12u); // 57 rotl
r5 = r5 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x473b1718u : 0x6b4f35e8u); // 58 add
r4 = rotr_var(r4, r1); // 59 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r4 = r4 ^ t_; } // 60 shfl
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 61 load
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 62 load
r4 = r4 * r1; // 63 mul
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r6 = r6 | r0; // s0 or
r7 = r7 * r3; // s1 mul
r3 = r5 * r5 + r3; // s2 mad
r7 = r7 + r4 + ((((sel >> 6u) & 1u) != 0u) ? 0x38e58a06u : 0x97d3d105u); // s3 add
r6 = r6 + r0 + ((((sel >> 20u) & 1u) != 0u) ? 0x9629673du : 0x29b87b9au); // s4 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r6 = r6 ^ t_; } // s5 shfl
r5 = r3 * r5 + r5; // s6 mad
r3 = rotl_imm(r3, 5u); // s7 rotl
r0 = r0 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0x4a5f55e1u : 0xa7c1fb0fu); // s8 add
r5 = r5 * r7; // s9 mul
r4 = r4 ^ r5; // s10 xor
r6 = mul_hi(r6, r4); // s11 mulhi
r5 = rotl_imm(r5, 13u); // s12 rotl
r0 = r2 * r1 + r0; // s13 mad
r2 = mul_hi(r2, r4); // s14 mulhi
r3 = r3 | r1; // s15 or
r0 = r0 - r5; // s16 sub
r0 = r0 * r6; // s17 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 4u); r5 = r5 ^ t_; } // s18 shfl
r3 = r3 | r4; // s19 or
r6 = r3 * r2 + r6; // s20 mad
r0 = rotl_imm(r0, 11u); // s21 rotl
r3 = rotl_imm(r3, 25u); // s22 rotl
r6 = r6 ^ r4; // s23 xor
r4 = r4 | r2; // s24 or
r1 = r1 + r6 + ((((sel >> 7u) & 1u) != 0u) ? 0xfc2f6d17u : 0x53e74799u); // s25 add
r7 = rotr_var(r7, r6); // s26 rotr
r7 = r7 + r5 + ((((sel >> 27u) & 1u) != 0u) ? 0x787048dcu : 0xb8fae90eu); // s27 add
r4 = r4 ^ r1; // s28 xor
r6 = r6 ^ r1; // s29 xor
r2 = mul_hi(r2, r0); // s30 mulhi
r1 = rotr_var(r1, r4); // s31 rotr
r7 = r7 ^ r4; // s32 xor
r3 = r2 * r6 + r3; // s33 mad
r3 = r3 + r1 + ((((sel >> 12u) & 1u) != 0u) ? 0x9ffd510bu : 0xd2dc42ebu); // s34 add
r4 = r4 + r7 + ((((sel >> 7u) & 1u) != 0u) ? 0xf871ba37u : 0xad8eda6fu); // s35 add
r7 = r7 + r4 + ((((sel >> 3u) & 1u) != 0u) ? 0xd02d30cau : 0xb0cef8f4u); // s36 add
r4 = r3 * r2 + r4; // s37 mad
r5 = r7 * r7 + r5; // s38 mad
r3 = r3 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x82e98a22u : 0x2bd506e2u); // s39 add
r0 = rotl_imm(r0, 21u); // s40 rotl
r1 = r1 | r0; // s41 or
r7 = r7 + r5 + ((((sel >> 28u) & 1u) != 0u) ? 0x6435f6d8u : 0xc0386e49u); // s42 add
r1 = mul_hi(r1, r0); // s43 mulhi
r5 = r5 + r6 + ((((sel >> 12u) & 1u) != 0u) ? 0x1f682c68u : 0x3a8921a4u); // s44 add
r4 = r4 + r5 + ((((sel >> 1u) & 1u) != 0u) ? 0xf246e180u : 0xeeca4334u); // s45 add
r2 = r2 ^ r3; // s46 xor
r2 = r2 ^ r5; // s47 xor
r7 = r4 * r1 + r7; // s48 mad
r2 = r6 * r1 + r2; // s49 mad
r7 = r0 * r7 + r7; // s50 mad
r5 = r5 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x41bd68ccu : 0x745776d8u); // s51 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 1u); r3 = r3 ^ t_; } // s52 shfl
r4 = r4 | r0; // s53 or
r0 = r2 * r4 + r0; // s54 mad
r5 = rotl_imm(r5, 9u); // s55 rotl
r5 = r5 * r7; // s56 mul
r7 = rotl_imm(r7, 27u); // s57 rotl
r7 = r7 - r6; // s58 sub
r2 = rotl_imm(r2, 22u); // s59 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r7 = r7 ^ t_; } // s60 shfl
r4 = r4 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xcba6a161u : 0x60d0ff55u); // s61 add
r1 = r1 * r5; // s62 mul
r7 = mul_hi(r7, r6); // s63 mulhi
r5 = r5 * r0; // s64 mul
r2 = rotr_var(r2, r5); // s65 rotr
r0 = mul_hi(r0, r3); // s66 mulhi
r0 = r0 | r7; // s67 or
r0 = rotl_imm(r0, 19u); // s68 rotl
r0 = rotl_imm(r0, 1u); // s69 rotl
r2 = r2 | r3; // s70 or
r3 = r7 * r5 + r3; // s71 mad
r7 = r0 * r4 + r7; // s72 mad
r4 = r4 | r3; // s73 or
r3 = r3 ^ r1; // s74 xor
r1 = r1 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x8e35924eu : 0x3f4ffea2u); // s75 add
r1 = r1 * r3; // s76 mul
r0 = r3 * r2 + r0; // s77 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 16u); r2 = r2 ^ t_; } // s78 shfl
r1 = mul_hi(r1, r0); // s79 mulhi
r0 = mul_hi(r0, r4); // s80 mulhi
r4 = r4 * r2; // s81 mul
r5 = r5 - r7; // s82 sub
r0 = r2 * r3 + r0; // s83 mad
r7 = r7 - r2; // s84 sub
r1 = r1 ^ r2; // s85 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 16u); r6 = r6 ^ t_; } // s86 shfl
r3 = r0 * r0 + r3; // s87 mad
r0 = rotl_imm(r0, 20u); // s88 rotl
r1 = r1 - r5; // s89 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r6 = r6 ^ t_; } // s90 shfl
r5 = r5 ^ r1; // s91 xor
r5 = rotl_imm(r5, 12u); // s92 rotl
r6 = r1 * r2 + r6; // s93 mad
r2 = rotr_var(r2, r5); // s94 rotr
r0 = r0 | r4; // s95 or
r7 = r7 * r3; // s96 mul
r5 = r5 | r0; // s97 or
r3 = r3 + r1 + ((((sel >> 13u) & 1u) != 0u) ? 0x386bb642u : 0xbcfdd8a7u); // s98 add
r0 = r0 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xa3962d03u : 0xc921a021u); // s99 add
r1 = rotr_var(r1, r0); // s100 rotr
r2 = r2 + r4 + ((((sel >> 18u) & 1u) != 0u) ? 0xc5990c5cu : 0x70da4067u); // s101 add
r2 = rotl_imm(r2, 3u); // s102 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 4u); r1 = r1 ^ t_; } // s103 shfl
r0 = r0 ^ r2; // s104 xor
r4 = r4 + r3 + ((((sel >> 28u) & 1u) != 0u) ? 0xb15aec75u : 0x1a5880cbu); // s105 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 2u); r4 = r4 ^ t_; } // s106 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r7 = r7 ^ t_; } // s107 shfl
r1 = r7 * r3 + r1; // s108 mad
r0 = r2 * r3 + r0; // s109 mad
r2 = r2 | r4; // s110 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 1u); r6 = r6 ^ t_; } // s111 shfl
r2 = r5 * r3 + r2; // s112 mad
r4 = mul_hi(r4, r0); // s113 mulhi
r7 = rotl_imm(r7, 29u); // s114 rotl
r3 = r3 - r7; // s115 sub
r0 = mul_hi(r0, r1); // s116 mulhi
r4 = rotl_imm(r4, 12u); // s117 rotl
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0xc5e98ee5u : 0x24494ad3u); // s118 add
r0 = r0 + r4 + ((((sel >> 4u) & 1u) != 0u) ? 0xa97bc949u : 0x1b2d1c83u); // s119 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 4u); r5 = r5 ^ t_; } // s120 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r3 = r3 ^ t_; } // s121 shfl
r7 = rotl_imm(r7, 3u); // s122 rotl
r4 = rotr_var(r4, r6); // s123 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r6 = r6 ^ t_; } // s124 shfl
r5 = rotl_imm(r5, 21u); // s125 rotl
r0 = r3 * r1 + r0; // s126 mad
r0 = r0 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0xa7f6bb54u : 0xff14c08du); // s127 add
r7 = r7 ^ r4; // s128 xor
r3 = mul_hi(r3, r5); // s129 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r5 = r5 ^ t_; } // s130 shfl
r6 = mul_hi(r6, r4); // s131 mulhi
r5 = r5 ^ r3; // s132 xor
r0 = rotl_imm(r0, 19u); // s133 rotl
r4 = rotr_var(r4, r3); // s134 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 16u); r1 = r1 ^ t_; } // s135 shfl
r5 = r5 - r2; // s136 sub
r3 = r3 ^ r5; // s137 xor
r0 = r0 - r2; // s138 sub
r3 = r3 * r7; // s139 mul
r5 = r5 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0x2d465ca8u : 0x82ab98f4u); // s140 add
r4 = r4 + r1 + ((((sel >> 11u) & 1u) != 0u) ? 0x237a9d8eu : 0x80594390u); // s141 add
r3 = r7 * r0 + r3; // s142 mad
r0 = r0 | r3; // s143 or
r0 = mul_hi(r0, r1); // s144 mulhi
r6 = r6 ^ r2; // s145 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r7 = r7 ^ t_; } // s146 shfl
r0 = r0 + r1 + ((((sel >> 18u) & 1u) != 0u) ? 0xe68cf57eu : 0x07f15148u); // s147 add
r7 = r7 | r3; // s148 or
r4 = r4 ^ r2; // s149 xor
r7 = r7 ^ r1; // s150 xor
r5 = rotr_var(r5, r2); // s151 rotr
r0 = r0 * r7; // s152 mul
r4 = rotl_imm(r4, 16u); // s153 rotl
r6 = rotr_var(r6, r4); // s154 rotr
r6 = r6 ^ r1; // s155 xor
r6 = r6 | r3; // s156 or
r1 = r1 + r6 + ((((sel >> 19u) & 1u) != 0u) ? 0x84c2a09du : 0x14878c5au); // s157 add
r4 = r4 - r1; // s158 sub
r4 = r6 * r7 + r4; // s159 mad
r1 = r1 * r5; // s160 mul
r4 = r4 | r0; // s161 or
r7 = rotl_imm(r7, 21u); // s162 rotl
r0 = r0 - r1; // s163 sub
r1 = r1 * r0; // s164 mul
r2 = r2 - r1; // s165 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r0 = r0 ^ t_; } // s166 shfl
r0 = r0 - r4; // s167 sub
r1 = rotr_var(r1, r6); // s168 rotr
r7 = rotr_var(r7, r1); // s169 rotr
r3 = r1 * r3 + r3; // s170 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // s171 shfl
r2 = r2 - r1; // s172 sub
r7 = r7 ^ r6; // s173 xor
r4 = rotr_var(r4, r1); // s174 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r4 = r4 ^ t_; } // s175 shfl
r6 = r6 * r2; // s176 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r0 = r0 ^ t_; } // s177 shfl
r6 = r6 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0x509871e6u : 0x4fa43965u); // s178 add
r0 = r0 ^ r6; // s179 xor
r5 = r5 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb95b8a53u : 0xfb3c4bd8u); // s180 add
r6 = r6 * r3; // s181 mul
r7 = rotl_imm(r7, 1u); // s182 rotl
r0 = r0 + r7 + ((((sel >> 11u) & 1u) != 0u) ? 0x7047b7cfu : 0xc448a197u); // s183 add
r3 = r3 * r5; // s184 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 1u); r5 = r5 ^ t_; } // s185 shfl
r0 = r0 * r2; // s186 mul
r4 = mul_hi(r4, r7); // s187 mulhi
r2 = r7 * r2 + r2; // s188 mad
r7 = r7 - r2; // s189 sub
r2 = r2 + r5 + ((((sel >> 19u) & 1u) != 0u) ? 0x5caccc5du : 0x2fceaf49u); // s190 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r1 = r1 ^ t_; } // s191 shfl
r7 = r7 + r1 + ((((sel >> 20u) & 1u) != 0u) ? 0x857bb5feu : 0xba0cee62u); // s192 add
r6 = rotl_imm(r6, 22u); // s193 rotl
r3 = r3 ^ r7; // s194 xor
r7 = r7 * r0; // s195 mul
r3 = r3 ^ r5; // s196 xor
r5 = r5 + r1 + ((((sel >> 29u) & 1u) != 0u) ? 0xeae84577u : 0x8519428cu); // s197 add
r7 = r4 * r4 + r7; // s198 mad
r3 = r3 + r6 + ((((sel >> 8u) & 1u) != 0u) ? 0x0bfdbfa1u : 0x468639d3u); // s199 add
r5 = r3 * r4 + r5; // s200 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r2 = r2 ^ t_; } // s201 shfl
r7 = r7 + r4 + ((((sel >> 23u) & 1u) != 0u) ? 0x53ee8e50u : 0x18ec9a69u); // s202 add
r6 = r6 ^ r0; // s203 xor
r4 = r4 + r5 + ((((sel >> 4u) & 1u) != 0u) ? 0xac63376eu : 0x3e81485bu); // s204 add
r7 = r1 * r4 + r7; // s205 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r1 = r1 ^ t_; } // s206 shfl
r4 = r4 * r0; // s207 mul
r1 = r1 | r6; // s208 or
r6 = r6 + r4 + ((((sel >> 28u) & 1u) != 0u) ? 0x5b745519u : 0x66ccb75du); // s209 add
r1 = rotr_var(r1, r3); // s210 rotr
r5 = r5 - r4; // s211 sub
r4 = r4 ^ r7; // s212 xor
r1 = r1 + r7 + ((((sel >> 8u) & 1u) != 0u) ? 0x1c3dccf7u : 0x0ce0553du); // s213 add
r0 = mul_hi(r0, r1); // s214 mulhi
r3 = r3 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xfadc9205u : 0x96bfec89u); // s215 add
r0 = rotl_imm(r0, 4u); // s216 rotl
r6 = r6 ^ r4; // s217 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r6 = r6 ^ t_; } // s218 shfl
r7 = r0 * r1 + r7; // s219 mad
r4 = r4 * r0; // s220 mul
r2 = r6 * r0 + r2; // s221 mad
r5 = r5 ^ r4; // s222 xor
r0 = r0 * r5; // s223 mul
r2 = r2 + r0 + ((((sel >> 9u) & 1u) != 0u) ? 0x66b15c04u : 0x61495681u); // s224 add
r3 = rotr_var(r3, r2); // s225 rotr
r2 = r3 * r3 + r2; // s226 mad
r6 = r6 ^ r0; // s227 xor
r4 = rotl_imm(r4, 30u); // s228 rotl
r2 = r2 + r3 + ((((sel >> 29u) & 1u) != 0u) ? 0x25bc17c2u : 0x70d05c34u); // s229 add
r1 = rotr_var(r1, r5); // s230 rotr
r1 = r1 + r4 + ((((sel >> 8u) & 1u) != 0u) ? 0x2d8728f3u : 0x32a28384u); // s231 add
r1 = rotl_imm(r1, 6u); // s232 rotl
r2 = r2 + r0 + ((((sel >> 21u) & 1u) != 0u) ? 0x61e81fe6u : 0xcf0949f1u); // s233 add
r4 = rotl_imm(r4, 2u); // s234 rotl
r2 = r2 - r6; // s235 sub
r6 = r6 | r3; // s236 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r7 = r7 ^ t_; } // s237 shfl
r1 = r1 ^ r3; // s238 xor
r2 = rotl_imm(r2, 1u); // s239 rotl
r5 = rotr_var(r5, r2); // s240 rotr
r4 = rotl_imm(r4, 10u); // s241 rotl
r6 = r6 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0x0a67565du : 0xe204fb50u); // s242 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 2u); r1 = r1 ^ t_; } // s243 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r0 = r0 ^ t_; } // s244 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r5 = r5 ^ t_; } // s245 shfl
r4 = r4 ^ r5; // s246 xor
r7 = r7 ^ r2; // s247 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 16u); r0 = r0 ^ t_; } // s248 shfl
r1 = mul_hi(r1, r3); // s249 mulhi
r7 = r7 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x5a79fd6fu : 0x3d6daffdu); // s250 add
r6 = r6 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x6beb28c2u : 0x84334aeau); // s251 add
r7 = r7 - r1; // s252 sub
r5 = rotr_var(r5, r2); // s253 rotr
r2 = mul_hi(r2, r5); // s254 mulhi
r6 = r6 * r3; // s255 mul
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}
#if IGNEUM_EXCHANGE != 0
// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
}
#endif
// Header-bound variant (bind.rs): the init words come from initw, not SEEDW. Same body as igneum_hash.
IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask, __global const uint* initw) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
uint iw0 = initw[0], iw1 = initw[1], iw2 = initw[2], iw3 = initw[3], iw4 = initw[4], iw5 = initw[5], iw6 = initw[6], iw7 = initw[7];
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
{ uint x = nonce ^ iw0; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw1; }
{ uint x = nonce ^ iw1; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw2; }
{ uint x = nonce ^ iw2; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw3; }
{ uint x = nonce ^ iw3; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw4; }
{ uint x = nonce ^ iw4; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw5; }
{ uint x = nonce ^ iw5; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw6; }
{ uint x = nonce ^ iw6; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw7; }
{ uint x = nonce ^ iw7; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw0; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r6 = r6 - r3; // 0 sub
r2 = r2 | r6; // 1 or
r4 = r4 + r0 + ((((sel >> 4u) & 1u) != 0u) ? 0x7731324bu : 0x1a579b38u); // 2 add
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 3 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r0 = r0 ^ t_; } // 4 shfl
r4 = r4 ^ r1; // 5 xor
r3 = r5 * r3 + r3; // 6 mad
r1 = r1 * r6; // 7 mul
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x08000000u) & mask]; // 8 load
r0 = r0 ^ r4; // 9 xor
r0 = r0 + r7 + ((((sel >> 30u) & 1u) != 0u) ? 0xb10fcef8u : 0xee083919u); // 10 add
r0 = mul_hi(r0, r2); // 11 mulhi
r5 = r5 ^ r4; // 12 xor
r7 = r3 * r0 + r7; // 13 mad
r3 = r3 ^ ds[((rotl_imm(r4 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 14 load
r2 = r2 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 15 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r7 = r7 ^ t_; } // 16 shfl
r7 = r7 * r6; // 17 mul
r2 = r3 * r1 + r2; // 18 mad
r5 = rotr_var(r5, r2); // 19 rotr
r5 = r5 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 20 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r6 = r6 ^ t_; } // 21 shfl
r1 = mul_hi(r1, r2); // 22 mulhi
r6 = r6 ^ r5; // 23 xor
r5 = r2 * r0 + r5; // 24 mad
r6 = r3 * r7 + r6; // 25 mad
r6 = r6 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 26 load
r1 = r5 * r5 + r1; // 27 mad
r0 = r0 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 28 load
r7 = r7 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x0b1f02c7u : 0xd5e6c37cu); // 29 add
r7 = r7 + r0 + ((((sel >> 0u) & 1u) != 0u) ? 0x2d6e8bd1u : 0x4e45ba51u); // 30 add
r0 = r0 ^ r2; // 31 xor
r6 = r6 + r2 + ((((sel >> 13u) & 1u) != 0u) ? 0x351422d2u : 0x1c91b2a1u); // 32 add
r4 = mul_hi(r4, r5); // 33 mulhi
r3 = rotr_var(r3, r5); // 34 rotr
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 35 load
r4 = rotl_imm(r4, 13u); // 36 rotl
r6 = r6 + r1 + ((((sel >> 7u) & 1u) != 0u) ? 0x64a28251u : 0x3f2970f7u); // 37 add
r2 = r2 * r0; // 38 mul
r3 = r3 + r4 + ((((sel >> 15u) & 1u) != 0u) ? 0x7378c955u : 0x3b7b3317u); // 39 add
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 40 load
r6 = r6 ^ r5; // 41 xor
r3 = r3 + r0 + ((((sel >> 2u) & 1u) != 0u) ? 0xb31f6a64u : 0x6678b059u); // 42 add
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 43 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r3 = r3 ^ t_; } // 44 shfl
r1 = mul_hi(r1, r5); // 45 mulhi
r0 = rotl_imm(r0, 6u); // 46 rotl
r1 = r1 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 47 load
r4 = r4 + r0 + ((((sel >> 17u) & 1u) != 0u) ? 0x5feccee6u : 0x43095946u); // 48 add
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 49 load
r2 = r2 - r3; // 50 sub
r7 = r7 + r2 + ((((sel >> 24u) & 1u) != 0u) ? 0x26e2b582u : 0xf45ecdf8u); // 51 add
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 52 load
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 53 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r7 = r7 ^ t_; } // 54 shfl
r1 = rotr_var(r1, r2); // 55 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r0 = r0 ^ t_; } // 56 shfl
r5 = rotl_imm(r5, 12u); // 57 rotl
r5 = r5 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x473b1718u : 0x6b4f35e8u); // 58 add
r4 = rotr_var(r4, r1); // 59 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r4 = r4 ^ t_; } // 60 shfl
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 61 load
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 62 load
r4 = r4 * r1; // 63 mul
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r6 = r6 | r0; // s0 or
r7 = r7 * r3; // s1 mul
r3 = r5 * r5 + r3; // s2 mad
r7 = r7 + r4 + ((((sel >> 6u) & 1u) != 0u) ? 0x38e58a06u : 0x97d3d105u); // s3 add
r6 = r6 + r0 + ((((sel >> 20u) & 1u) != 0u) ? 0x9629673du : 0x29b87b9au); // s4 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r6 = r6 ^ t_; } // s5 shfl
r5 = r3 * r5 + r5; // s6 mad
r3 = rotl_imm(r3, 5u); // s7 rotl
r0 = r0 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0x4a5f55e1u : 0xa7c1fb0fu); // s8 add
r5 = r5 * r7; // s9 mul
r4 = r4 ^ r5; // s10 xor
r6 = mul_hi(r6, r4); // s11 mulhi
r5 = rotl_imm(r5, 13u); // s12 rotl
r0 = r2 * r1 + r0; // s13 mad
r2 = mul_hi(r2, r4); // s14 mulhi
r3 = r3 | r1; // s15 or
r0 = r0 - r5; // s16 sub
r0 = r0 * r6; // s17 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 4u); r5 = r5 ^ t_; } // s18 shfl
r3 = r3 | r4; // s19 or
r6 = r3 * r2 + r6; // s20 mad
r0 = rotl_imm(r0, 11u); // s21 rotl
r3 = rotl_imm(r3, 25u); // s22 rotl
r6 = r6 ^ r4; // s23 xor
r4 = r4 | r2; // s24 or
r1 = r1 + r6 + ((((sel >> 7u) & 1u) != 0u) ? 0xfc2f6d17u : 0x53e74799u); // s25 add
r7 = rotr_var(r7, r6); // s26 rotr
r7 = r7 + r5 + ((((sel >> 27u) & 1u) != 0u) ? 0x787048dcu : 0xb8fae90eu); // s27 add
r4 = r4 ^ r1; // s28 xor
r6 = r6 ^ r1; // s29 xor
r2 = mul_hi(r2, r0); // s30 mulhi
r1 = rotr_var(r1, r4); // s31 rotr
r7 = r7 ^ r4; // s32 xor
r3 = r2 * r6 + r3; // s33 mad
r3 = r3 + r1 + ((((sel >> 12u) & 1u) != 0u) ? 0x9ffd510bu : 0xd2dc42ebu); // s34 add
r4 = r4 + r7 + ((((sel >> 7u) & 1u) != 0u) ? 0xf871ba37u : 0xad8eda6fu); // s35 add
r7 = r7 + r4 + ((((sel >> 3u) & 1u) != 0u) ? 0xd02d30cau : 0xb0cef8f4u); // s36 add
r4 = r3 * r2 + r4; // s37 mad
r5 = r7 * r7 + r5; // s38 mad
r3 = r3 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x82e98a22u : 0x2bd506e2u); // s39 add
r0 = rotl_imm(r0, 21u); // s40 rotl
r1 = r1 | r0; // s41 or
r7 = r7 + r5 + ((((sel >> 28u) & 1u) != 0u) ? 0x6435f6d8u : 0xc0386e49u); // s42 add
r1 = mul_hi(r1, r0); // s43 mulhi
r5 = r5 + r6 + ((((sel >> 12u) & 1u) != 0u) ? 0x1f682c68u : 0x3a8921a4u); // s44 add
r4 = r4 + r5 + ((((sel >> 1u) & 1u) != 0u) ? 0xf246e180u : 0xeeca4334u); // s45 add
r2 = r2 ^ r3; // s46 xor
r2 = r2 ^ r5; // s47 xor
r7 = r4 * r1 + r7; // s48 mad
r2 = r6 * r1 + r2; // s49 mad
r7 = r0 * r7 + r7; // s50 mad
r5 = r5 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x41bd68ccu : 0x745776d8u); // s51 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 1u); r3 = r3 ^ t_; } // s52 shfl
r4 = r4 | r0; // s53 or
r0 = r2 * r4 + r0; // s54 mad
r5 = rotl_imm(r5, 9u); // s55 rotl
r5 = r5 * r7; // s56 mul
r7 = rotl_imm(r7, 27u); // s57 rotl
r7 = r7 - r6; // s58 sub
r2 = rotl_imm(r2, 22u); // s59 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r7 = r7 ^ t_; } // s60 shfl
r4 = r4 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xcba6a161u : 0x60d0ff55u); // s61 add
r1 = r1 * r5; // s62 mul
r7 = mul_hi(r7, r6); // s63 mulhi
r5 = r5 * r0; // s64 mul
r2 = rotr_var(r2, r5); // s65 rotr
r0 = mul_hi(r0, r3); // s66 mulhi
r0 = r0 | r7; // s67 or
r0 = rotl_imm(r0, 19u); // s68 rotl
r0 = rotl_imm(r0, 1u); // s69 rotl
r2 = r2 | r3; // s70 or
r3 = r7 * r5 + r3; // s71 mad
r7 = r0 * r4 + r7; // s72 mad
r4 = r4 | r3; // s73 or
r3 = r3 ^ r1; // s74 xor
r1 = r1 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x8e35924eu : 0x3f4ffea2u); // s75 add
r1 = r1 * r3; // s76 mul
r0 = r3 * r2 + r0; // s77 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 16u); r2 = r2 ^ t_; } // s78 shfl
r1 = mul_hi(r1, r0); // s79 mulhi
r0 = mul_hi(r0, r4); // s80 mulhi
r4 = r4 * r2; // s81 mul
r5 = r5 - r7; // s82 sub
r0 = r2 * r3 + r0; // s83 mad
r7 = r7 - r2; // s84 sub
r1 = r1 ^ r2; // s85 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 16u); r6 = r6 ^ t_; } // s86 shfl
r3 = r0 * r0 + r3; // s87 mad
r0 = rotl_imm(r0, 20u); // s88 rotl
r1 = r1 - r5; // s89 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r6 = r6 ^ t_; } // s90 shfl
r5 = r5 ^ r1; // s91 xor
r5 = rotl_imm(r5, 12u); // s92 rotl
r6 = r1 * r2 + r6; // s93 mad
r2 = rotr_var(r2, r5); // s94 rotr
r0 = r0 | r4; // s95 or
r7 = r7 * r3; // s96 mul
r5 = r5 | r0; // s97 or
r3 = r3 + r1 + ((((sel >> 13u) & 1u) != 0u) ? 0x386bb642u : 0xbcfdd8a7u); // s98 add
r0 = r0 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xa3962d03u : 0xc921a021u); // s99 add
r1 = rotr_var(r1, r0); // s100 rotr
r2 = r2 + r4 + ((((sel >> 18u) & 1u) != 0u) ? 0xc5990c5cu : 0x70da4067u); // s101 add
r2 = rotl_imm(r2, 3u); // s102 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 4u); r1 = r1 ^ t_; } // s103 shfl
r0 = r0 ^ r2; // s104 xor
r4 = r4 + r3 + ((((sel >> 28u) & 1u) != 0u) ? 0xb15aec75u : 0x1a5880cbu); // s105 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 2u); r4 = r4 ^ t_; } // s106 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r7 = r7 ^ t_; } // s107 shfl
r1 = r7 * r3 + r1; // s108 mad
r0 = r2 * r3 + r0; // s109 mad
r2 = r2 | r4; // s110 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 1u); r6 = r6 ^ t_; } // s111 shfl
r2 = r5 * r3 + r2; // s112 mad
r4 = mul_hi(r4, r0); // s113 mulhi
r7 = rotl_imm(r7, 29u); // s114 rotl
r3 = r3 - r7; // s115 sub
r0 = mul_hi(r0, r1); // s116 mulhi
r4 = rotl_imm(r4, 12u); // s117 rotl
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0xc5e98ee5u : 0x24494ad3u); // s118 add
r0 = r0 + r4 + ((((sel >> 4u) & 1u) != 0u) ? 0xa97bc949u : 0x1b2d1c83u); // s119 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 4u); r5 = r5 ^ t_; } // s120 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r3 = r3 ^ t_; } // s121 shfl
r7 = rotl_imm(r7, 3u); // s122 rotl
r4 = rotr_var(r4, r6); // s123 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 1u); r6 = r6 ^ t_; } // s124 shfl
r5 = rotl_imm(r5, 21u); // s125 rotl
r0 = r3 * r1 + r0; // s126 mad
r0 = r0 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0xa7f6bb54u : 0xff14c08du); // s127 add
r7 = r7 ^ r4; // s128 xor
r3 = mul_hi(r3, r5); // s129 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r5 = r5 ^ t_; } // s130 shfl
r6 = mul_hi(r6, r4); // s131 mulhi
r5 = r5 ^ r3; // s132 xor
r0 = rotl_imm(r0, 19u); // s133 rotl
r4 = rotr_var(r4, r3); // s134 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 16u); r1 = r1 ^ t_; } // s135 shfl
r5 = r5 - r2; // s136 sub
r3 = r3 ^ r5; // s137 xor
r0 = r0 - r2; // s138 sub
r3 = r3 * r7; // s139 mul
r5 = r5 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0x2d465ca8u : 0x82ab98f4u); // s140 add
r4 = r4 + r1 + ((((sel >> 11u) & 1u) != 0u) ? 0x237a9d8eu : 0x80594390u); // s141 add
r3 = r7 * r0 + r3; // s142 mad
r0 = r0 | r3; // s143 or
r0 = mul_hi(r0, r1); // s144 mulhi
r6 = r6 ^ r2; // s145 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r7 = r7 ^ t_; } // s146 shfl
r0 = r0 + r1 + ((((sel >> 18u) & 1u) != 0u) ? 0xe68cf57eu : 0x07f15148u); // s147 add
r7 = r7 | r3; // s148 or
r4 = r4 ^ r2; // s149 xor
r7 = r7 ^ r1; // s150 xor
r5 = rotr_var(r5, r2); // s151 rotr
r0 = r0 * r7; // s152 mul
r4 = rotl_imm(r4, 16u); // s153 rotl
r6 = rotr_var(r6, r4); // s154 rotr
r6 = r6 ^ r1; // s155 xor
r6 = r6 | r3; // s156 or
r1 = r1 + r6 + ((((sel >> 19u) & 1u) != 0u) ? 0x84c2a09du : 0x14878c5au); // s157 add
r4 = r4 - r1; // s158 sub
r4 = r6 * r7 + r4; // s159 mad
r1 = r1 * r5; // s160 mul
r4 = r4 | r0; // s161 or
r7 = rotl_imm(r7, 21u); // s162 rotl
r0 = r0 - r1; // s163 sub
r1 = r1 * r0; // s164 mul
r2 = r2 - r1; // s165 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r0 = r0 ^ t_; } // s166 shfl
r0 = r0 - r4; // s167 sub
r1 = rotr_var(r1, r6); // s168 rotr
r7 = rotr_var(r7, r1); // s169 rotr
r3 = r1 * r3 + r3; // s170 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // s171 shfl
r2 = r2 - r1; // s172 sub
r7 = r7 ^ r6; // s173 xor
r4 = rotr_var(r4, r1); // s174 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r4 = r4 ^ t_; } // s175 shfl
r6 = r6 * r2; // s176 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r0 = r0 ^ t_; } // s177 shfl
r6 = r6 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0x509871e6u : 0x4fa43965u); // s178 add
r0 = r0 ^ r6; // s179 xor
r5 = r5 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb95b8a53u : 0xfb3c4bd8u); // s180 add
r6 = r6 * r3; // s181 mul
r7 = rotl_imm(r7, 1u); // s182 rotl
r0 = r0 + r7 + ((((sel >> 11u) & 1u) != 0u) ? 0x7047b7cfu : 0xc448a197u); // s183 add
r3 = r3 * r5; // s184 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 1u); r5 = r5 ^ t_; } // s185 shfl
r0 = r0 * r2; // s186 mul
r4 = mul_hi(r4, r7); // s187 mulhi
r2 = r7 * r2 + r2; // s188 mad
r7 = r7 - r2; // s189 sub
r2 = r2 + r5 + ((((sel >> 19u) & 1u) != 0u) ? 0x5caccc5du : 0x2fceaf49u); // s190 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r1 = r1 ^ t_; } // s191 shfl
r7 = r7 + r1 + ((((sel >> 20u) & 1u) != 0u) ? 0x857bb5feu : 0xba0cee62u); // s192 add
r6 = rotl_imm(r6, 22u); // s193 rotl
r3 = r3 ^ r7; // s194 xor
r7 = r7 * r0; // s195 mul
r3 = r3 ^ r5; // s196 xor
r5 = r5 + r1 + ((((sel >> 29u) & 1u) != 0u) ? 0xeae84577u : 0x8519428cu); // s197 add
r7 = r4 * r4 + r7; // s198 mad
r3 = r3 + r6 + ((((sel >> 8u) & 1u) != 0u) ? 0x0bfdbfa1u : 0x468639d3u); // s199 add
r5 = r3 * r4 + r5; // s200 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r2 = r2 ^ t_; } // s201 shfl
r7 = r7 + r4 + ((((sel >> 23u) & 1u) != 0u) ? 0x53ee8e50u : 0x18ec9a69u); // s202 add
r6 = r6 ^ r0; // s203 xor
r4 = r4 + r5 + ((((sel >> 4u) & 1u) != 0u) ? 0xac63376eu : 0x3e81485bu); // s204 add
r7 = r1 * r4 + r7; // s205 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r1 = r1 ^ t_; } // s206 shfl
r4 = r4 * r0; // s207 mul
r1 = r1 | r6; // s208 or
r6 = r6 + r4 + ((((sel >> 28u) & 1u) != 0u) ? 0x5b745519u : 0x66ccb75du); // s209 add
r1 = rotr_var(r1, r3); // s210 rotr
r5 = r5 - r4; // s211 sub
r4 = r4 ^ r7; // s212 xor
r1 = r1 + r7 + ((((sel >> 8u) & 1u) != 0u) ? 0x1c3dccf7u : 0x0ce0553du); // s213 add
r0 = mul_hi(r0, r1); // s214 mulhi
r3 = r3 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xfadc9205u : 0x96bfec89u); // s215 add
r0 = rotl_imm(r0, 4u); // s216 rotl
r6 = r6 ^ r4; // s217 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r6 = r6 ^ t_; } // s218 shfl
r7 = r0 * r1 + r7; // s219 mad
r4 = r4 * r0; // s220 mul
r2 = r6 * r0 + r2; // s221 mad
r5 = r5 ^ r4; // s222 xor
r0 = r0 * r5; // s223 mul
r2 = r2 + r0 + ((((sel >> 9u) & 1u) != 0u) ? 0x66b15c04u : 0x61495681u); // s224 add
r3 = rotr_var(r3, r2); // s225 rotr
r2 = r3 * r3 + r2; // s226 mad
r6 = r6 ^ r0; // s227 xor
r4 = rotl_imm(r4, 30u); // s228 rotl
r2 = r2 + r3 + ((((sel >> 29u) & 1u) != 0u) ? 0x25bc17c2u : 0x70d05c34u); // s229 add
r1 = rotr_var(r1, r5); // s230 rotr
r1 = r1 + r4 + ((((sel >> 8u) & 1u) != 0u) ? 0x2d8728f3u : 0x32a28384u); // s231 add
r1 = rotl_imm(r1, 6u); // s232 rotl
r2 = r2 + r0 + ((((sel >> 21u) & 1u) != 0u) ? 0x61e81fe6u : 0xcf0949f1u); // s233 add
r4 = rotl_imm(r4, 2u); // s234 rotl
r2 = r2 - r6; // s235 sub
r6 = r6 | r3; // s236 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r7 = r7 ^ t_; } // s237 shfl
r1 = r1 ^ r3; // s238 xor
r2 = rotl_imm(r2, 1u); // s239 rotl
r5 = rotr_var(r5, r2); // s240 rotr
r4 = rotl_imm(r4, 10u); // s241 rotl
r6 = r6 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0x0a67565du : 0xe204fb50u); // s242 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 2u); r1 = r1 ^ t_; } // s243 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r0 = r0 ^ t_; } // s244 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r5 = r5 ^ t_; } // s245 shfl
r4 = r4 ^ r5; // s246 xor
r7 = r7 ^ r2; // s247 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 16u); r0 = r0 ^ t_; } // s248 shfl
r1 = mul_hi(r1, r3); // s249 mulhi
r7 = r7 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x5a79fd6fu : 0x3d6daffdu); // s250 add
r6 = r6 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x6beb28c2u : 0x84334aeau); // s251 add
r7 = r7 - r1; // s252 sub
r5 = rotr_var(r5, r2); // s253 rotr
r2 = mul_hi(r2, r5); // s254 mulhi
r6 = r6 * r3; // s255 mul
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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@ -0,0 +1,382 @@
// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000". Do not edit by hand.
// Header-bound twin of igneum_hash in kernel.cu: the init words come from a kernel argument, not SEEDW.
// Host declarations (also in program_bound.h if present):
// struct IgneumInitWords { uint32_t w[8]; };
// cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
// IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps);
// cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
struct IgneumInitWords { uint32_t w[8]; };
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask, IgneumInitWords iw) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ iw.w[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw.w[1]; }
{ uint32_t x = nonce ^ iw.w[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw.w[2]; }
{ uint32_t x = nonce ^ iw.w[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw.w[3]; }
{ uint32_t x = nonce ^ iw.w[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw.w[4]; }
{ uint32_t x = nonce ^ iw.w[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw.w[5]; }
{ uint32_t x = nonce ^ iw.w[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw.w[6]; }
{ uint32_t x = nonce ^ iw.w[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw.w[7]; }
{ uint32_t x = nonce ^ iw.w[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw.w[0]; }
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r6 = r6 - r3; // 0 sub
r2 = r2 | r6; // 1 or
r4 = r4 + r0 + ((((sel >> 4u) & 1u) != 0u) ? 0x7731324bu : 0x1a579b38u); // 2 add
r3 = r3 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 3 load
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // 4 shfl
r4 = r4 ^ r1; // 5 xor
r3 = r5 * r3 + r3; // 6 mad
r1 = r1 * r6; // 7 mul
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x08000000u) & mask]; // 8 load
r0 = r0 ^ r4; // 9 xor
r0 = r0 + r7 + ((((sel >> 30u) & 1u) != 0u) ? 0xb10fcef8u : 0xee083919u); // 10 add
r0 = __umulhi(r0, r2); // 11 mulhi
r5 = r5 ^ r4; // 12 xor
r7 = r3 * r0 + r7; // 13 mad
r3 = r3 ^ ds[((rotl_imm(r4 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 14 load
r2 = r2 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 15 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 16 shfl
r7 = r7 * r6; // 17 mul
r2 = r3 * r1 + r2; // 18 mad
r5 = rotr_var(r5, r2); // 19 rotr
r5 = r5 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 20 load
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r1 = __umulhi(r1, r2); // 22 mulhi
r6 = r6 ^ r5; // 23 xor
r5 = r2 * r0 + r5; // 24 mad
r6 = r3 * r7 + r6; // 25 mad
r6 = r6 ^ ds[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 26 load
r1 = r5 * r5 + r1; // 27 mad
r0 = r0 ^ ds[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 28 load
r7 = r7 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x0b1f02c7u : 0xd5e6c37cu); // 29 add
r7 = r7 + r0 + ((((sel >> 0u) & 1u) != 0u) ? 0x2d6e8bd1u : 0x4e45ba51u); // 30 add
r0 = r0 ^ r2; // 31 xor
r6 = r6 + r2 + ((((sel >> 13u) & 1u) != 0u) ? 0x351422d2u : 0x1c91b2a1u); // 32 add
r4 = __umulhi(r4, r5); // 33 mulhi
r3 = rotr_var(r3, r5); // 34 rotr
r3 = r3 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 35 load
r4 = rotl_imm(r4, 13u); // 36 rotl
r6 = r6 + r1 + ((((sel >> 7u) & 1u) != 0u) ? 0x64a28251u : 0x3f2970f7u); // 37 add
r2 = r2 * r0; // 38 mul
r3 = r3 + r4 + ((((sel >> 15u) & 1u) != 0u) ? 0x7378c955u : 0x3b7b3317u); // 39 add
r0 = r0 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 40 load
r6 = r6 ^ r5; // 41 xor
r3 = r3 + r0 + ((((sel >> 2u) & 1u) != 0u) ? 0xb31f6a64u : 0x6678b059u); // 42 add
r7 = r7 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & mask]; // 43 load
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 44 shfl
r1 = __umulhi(r1, r5); // 45 mulhi
r0 = rotl_imm(r0, 6u); // 46 rotl
r1 = r1 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 47 load
r4 = r4 + r0 + ((((sel >> 17u) & 1u) != 0u) ? 0x5feccee6u : 0x43095946u); // 48 add
r2 = r2 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 49 load
r2 = r2 - r3; // 50 sub
r7 = r7 + r2 + ((((sel >> 24u) & 1u) != 0u) ? 0x26e2b582u : 0xf45ecdf8u); // 51 add
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & mask]; // 52 load
r6 = r6 ^ ds[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & mask]; // 53 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 54 shfl
r1 = rotr_var(r1, r2); // 55 rotr
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 56 shfl
r5 = rotl_imm(r5, 12u); // 57 rotl
r5 = r5 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x473b1718u : 0x6b4f35e8u); // 58 add
r4 = rotr_var(r4, r1); // 59 rotr
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 60 shfl
r7 = r7 ^ ds[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 61 load
r5 = r5 ^ ds[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & mask]; // 62 load
r4 = r4 * r1; // 63 mul
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint32_t sh = 0u; sh < 27u; ++sh) {
r6 = r6 | r0; // s0 or
r7 = r7 * r3; // s1 mul
r3 = r5 * r5 + r3; // s2 mad
r7 = r7 + r4 + ((((sel >> 6u) & 1u) != 0u) ? 0x38e58a06u : 0x97d3d105u); // s3 add
r6 = r6 + r0 + ((((sel >> 20u) & 1u) != 0u) ? 0x9629673du : 0x29b87b9au); // s4 add
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // s5 shfl
r5 = r3 * r5 + r5; // s6 mad
r3 = rotl_imm(r3, 5u); // s7 rotl
r0 = r0 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0x4a5f55e1u : 0xa7c1fb0fu); // s8 add
r5 = r5 * r7; // s9 mul
r4 = r4 ^ r5; // s10 xor
r6 = __umulhi(r6, r4); // s11 mulhi
r5 = rotl_imm(r5, 13u); // s12 rotl
r0 = r2 * r1 + r0; // s13 mad
r2 = __umulhi(r2, r4); // s14 mulhi
r3 = r3 | r1; // s15 or
r0 = r0 - r5; // s16 sub
r0 = r0 * r6; // s17 mul
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r1, 4); // s18 shfl
r3 = r3 | r4; // s19 or
r6 = r3 * r2 + r6; // s20 mad
r0 = rotl_imm(r0, 11u); // s21 rotl
r3 = rotl_imm(r3, 25u); // s22 rotl
r6 = r6 ^ r4; // s23 xor
r4 = r4 | r2; // s24 or
r1 = r1 + r6 + ((((sel >> 7u) & 1u) != 0u) ? 0xfc2f6d17u : 0x53e74799u); // s25 add
r7 = rotr_var(r7, r6); // s26 rotr
r7 = r7 + r5 + ((((sel >> 27u) & 1u) != 0u) ? 0x787048dcu : 0xb8fae90eu); // s27 add
r4 = r4 ^ r1; // s28 xor
r6 = r6 ^ r1; // s29 xor
r2 = __umulhi(r2, r0); // s30 mulhi
r1 = rotr_var(r1, r4); // s31 rotr
r7 = r7 ^ r4; // s32 xor
r3 = r2 * r6 + r3; // s33 mad
r3 = r3 + r1 + ((((sel >> 12u) & 1u) != 0u) ? 0x9ffd510bu : 0xd2dc42ebu); // s34 add
r4 = r4 + r7 + ((((sel >> 7u) & 1u) != 0u) ? 0xf871ba37u : 0xad8eda6fu); // s35 add
r7 = r7 + r4 + ((((sel >> 3u) & 1u) != 0u) ? 0xd02d30cau : 0xb0cef8f4u); // s36 add
r4 = r3 * r2 + r4; // s37 mad
r5 = r7 * r7 + r5; // s38 mad
r3 = r3 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x82e98a22u : 0x2bd506e2u); // s39 add
r0 = rotl_imm(r0, 21u); // s40 rotl
r1 = r1 | r0; // s41 or
r7 = r7 + r5 + ((((sel >> 28u) & 1u) != 0u) ? 0x6435f6d8u : 0xc0386e49u); // s42 add
r1 = __umulhi(r1, r0); // s43 mulhi
r5 = r5 + r6 + ((((sel >> 12u) & 1u) != 0u) ? 0x1f682c68u : 0x3a8921a4u); // s44 add
r4 = r4 + r5 + ((((sel >> 1u) & 1u) != 0u) ? 0xf246e180u : 0xeeca4334u); // s45 add
r2 = r2 ^ r3; // s46 xor
r2 = r2 ^ r5; // s47 xor
r7 = r4 * r1 + r7; // s48 mad
r2 = r6 * r1 + r2; // s49 mad
r7 = r0 * r7 + r7; // s50 mad
r5 = r5 + r6 + ((((sel >> 26u) & 1u) != 0u) ? 0x41bd68ccu : 0x745776d8u); // s51 add
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r0, 1); // s52 shfl
r4 = r4 | r0; // s53 or
r0 = r2 * r4 + r0; // s54 mad
r5 = rotl_imm(r5, 9u); // s55 rotl
r5 = r5 * r7; // s56 mul
r7 = rotl_imm(r7, 27u); // s57 rotl
r7 = r7 - r6; // s58 sub
r2 = rotl_imm(r2, 22u); // s59 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s60 shfl
r4 = r4 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xcba6a161u : 0x60d0ff55u); // s61 add
r1 = r1 * r5; // s62 mul
r7 = __umulhi(r7, r6); // s63 mulhi
r5 = r5 * r0; // s64 mul
r2 = rotr_var(r2, r5); // s65 rotr
r0 = __umulhi(r0, r3); // s66 mulhi
r0 = r0 | r7; // s67 or
r0 = rotl_imm(r0, 19u); // s68 rotl
r0 = rotl_imm(r0, 1u); // s69 rotl
r2 = r2 | r3; // s70 or
r3 = r7 * r5 + r3; // s71 mad
r7 = r0 * r4 + r7; // s72 mad
r4 = r4 | r3; // s73 or
r3 = r3 ^ r1; // s74 xor
r1 = r1 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x8e35924eu : 0x3f4ffea2u); // s75 add
r1 = r1 * r3; // s76 mul
r0 = r3 * r2 + r0; // s77 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 16); // s78 shfl
r1 = __umulhi(r1, r0); // s79 mulhi
r0 = __umulhi(r0, r4); // s80 mulhi
r4 = r4 * r2; // s81 mul
r5 = r5 - r7; // s82 sub
r0 = r2 * r3 + r0; // s83 mad
r7 = r7 - r2; // s84 sub
r1 = r1 ^ r2; // s85 xor
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 16); // s86 shfl
r3 = r0 * r0 + r3; // s87 mad
r0 = rotl_imm(r0, 20u); // s88 rotl
r1 = r1 - r5; // s89 sub
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // s90 shfl
r5 = r5 ^ r1; // s91 xor
r5 = rotl_imm(r5, 12u); // s92 rotl
r6 = r1 * r2 + r6; // s93 mad
r2 = rotr_var(r2, r5); // s94 rotr
r0 = r0 | r4; // s95 or
r7 = r7 * r3; // s96 mul
r5 = r5 | r0; // s97 or
r3 = r3 + r1 + ((((sel >> 13u) & 1u) != 0u) ? 0x386bb642u : 0xbcfdd8a7u); // s98 add
r0 = r0 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xa3962d03u : 0xc921a021u); // s99 add
r1 = rotr_var(r1, r0); // s100 rotr
r2 = r2 + r4 + ((((sel >> 18u) & 1u) != 0u) ? 0xc5990c5cu : 0x70da4067u); // s101 add
r2 = rotl_imm(r2, 3u); // s102 rotl
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 4); // s103 shfl
r0 = r0 ^ r2; // s104 xor
r4 = r4 + r3 + ((((sel >> 28u) & 1u) != 0u) ? 0xb15aec75u : 0x1a5880cbu); // s105 add
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r0, 2); // s106 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // s107 shfl
r1 = r7 * r3 + r1; // s108 mad
r0 = r2 * r3 + r0; // s109 mad
r2 = r2 | r4; // s110 or
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 1); // s111 shfl
r2 = r5 * r3 + r2; // s112 mad
r4 = __umulhi(r4, r0); // s113 mulhi
r7 = rotl_imm(r7, 29u); // s114 rotl
r3 = r3 - r7; // s115 sub
r0 = __umulhi(r0, r1); // s116 mulhi
r4 = rotl_imm(r4, 12u); // s117 rotl
r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0xc5e98ee5u : 0x24494ad3u); // s118 add
r0 = r0 + r4 + ((((sel >> 4u) & 1u) != 0u) ? 0xa97bc949u : 0x1b2d1c83u); // s119 add
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 4); // s120 shfl
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s121 shfl
r7 = rotl_imm(r7, 3u); // s122 rotl
r4 = rotr_var(r4, r6); // s123 rotr
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // s124 shfl
r5 = rotl_imm(r5, 21u); // s125 rotl
r0 = r3 * r1 + r0; // s126 mad
r0 = r0 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0xa7f6bb54u : 0xff14c08du); // s127 add
r7 = r7 ^ r4; // s128 xor
r3 = __umulhi(r3, r5); // s129 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 8); // s130 shfl
r6 = __umulhi(r6, r4); // s131 mulhi
r5 = r5 ^ r3; // s132 xor
r0 = rotl_imm(r0, 19u); // s133 rotl
r4 = rotr_var(r4, r3); // s134 rotr
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 16); // s135 shfl
r5 = r5 - r2; // s136 sub
r3 = r3 ^ r5; // s137 xor
r0 = r0 - r2; // s138 sub
r3 = r3 * r7; // s139 mul
r5 = r5 + r3 + ((((sel >> 24u) & 1u) != 0u) ? 0x2d465ca8u : 0x82ab98f4u); // s140 add
r4 = r4 + r1 + ((((sel >> 11u) & 1u) != 0u) ? 0x237a9d8eu : 0x80594390u); // s141 add
r3 = r7 * r0 + r3; // s142 mad
r0 = r0 | r3; // s143 or
r0 = __umulhi(r0, r1); // s144 mulhi
r6 = r6 ^ r2; // s145 xor
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s146 shfl
r0 = r0 + r1 + ((((sel >> 18u) & 1u) != 0u) ? 0xe68cf57eu : 0x07f15148u); // s147 add
r7 = r7 | r3; // s148 or
r4 = r4 ^ r2; // s149 xor
r7 = r7 ^ r1; // s150 xor
r5 = rotr_var(r5, r2); // s151 rotr
r0 = r0 * r7; // s152 mul
r4 = rotl_imm(r4, 16u); // s153 rotl
r6 = rotr_var(r6, r4); // s154 rotr
r6 = r6 ^ r1; // s155 xor
r6 = r6 | r3; // s156 or
r1 = r1 + r6 + ((((sel >> 19u) & 1u) != 0u) ? 0x84c2a09du : 0x14878c5au); // s157 add
r4 = r4 - r1; // s158 sub
r4 = r6 * r7 + r4; // s159 mad
r1 = r1 * r5; // s160 mul
r4 = r4 | r0; // s161 or
r7 = rotl_imm(r7, 21u); // s162 rotl
r0 = r0 - r1; // s163 sub
r1 = r1 * r0; // s164 mul
r2 = r2 - r1; // s165 sub
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // s166 shfl
r0 = r0 - r4; // s167 sub
r1 = rotr_var(r1, r6); // s168 rotr
r7 = rotr_var(r7, r1); // s169 rotr
r3 = r1 * r3 + r3; // s170 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // s171 shfl
r2 = r2 - r1; // s172 sub
r7 = r7 ^ r6; // s173 xor
r4 = rotr_var(r4, r1); // s174 rotr
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s175 shfl
r6 = r6 * r2; // s176 mul
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // s177 shfl
r6 = r6 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0x509871e6u : 0x4fa43965u); // s178 add
r0 = r0 ^ r6; // s179 xor
r5 = r5 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb95b8a53u : 0xfb3c4bd8u); // s180 add
r6 = r6 * r3; // s181 mul
r7 = rotl_imm(r7, 1u); // s182 rotl
r0 = r0 + r7 + ((((sel >> 11u) & 1u) != 0u) ? 0x7047b7cfu : 0xc448a197u); // s183 add
r3 = r3 * r5; // s184 mul
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 1); // s185 shfl
r0 = r0 * r2; // s186 mul
r4 = __umulhi(r4, r7); // s187 mulhi
r2 = r7 * r2 + r2; // s188 mad
r7 = r7 - r2; // s189 sub
r2 = r2 + r5 + ((((sel >> 19u) & 1u) != 0u) ? 0x5caccc5du : 0x2fceaf49u); // s190 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // s191 shfl
r7 = r7 + r1 + ((((sel >> 20u) & 1u) != 0u) ? 0x857bb5feu : 0xba0cee62u); // s192 add
r6 = rotl_imm(r6, 22u); // s193 rotl
r3 = r3 ^ r7; // s194 xor
r7 = r7 * r0; // s195 mul
r3 = r3 ^ r5; // s196 xor
r5 = r5 + r1 + ((((sel >> 29u) & 1u) != 0u) ? 0xeae84577u : 0x8519428cu); // s197 add
r7 = r4 * r4 + r7; // s198 mad
r3 = r3 + r6 + ((((sel >> 8u) & 1u) != 0u) ? 0x0bfdbfa1u : 0x468639d3u); // s199 add
r5 = r3 * r4 + r5; // s200 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // s201 shfl
r7 = r7 + r4 + ((((sel >> 23u) & 1u) != 0u) ? 0x53ee8e50u : 0x18ec9a69u); // s202 add
r6 = r6 ^ r0; // s203 xor
r4 = r4 + r5 + ((((sel >> 4u) & 1u) != 0u) ? 0xac63376eu : 0x3e81485bu); // s204 add
r7 = r1 * r4 + r7; // s205 mad
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s206 shfl
r4 = r4 * r0; // s207 mul
r1 = r1 | r6; // s208 or
r6 = r6 + r4 + ((((sel >> 28u) & 1u) != 0u) ? 0x5b745519u : 0x66ccb75du); // s209 add
r1 = rotr_var(r1, r3); // s210 rotr
r5 = r5 - r4; // s211 sub
r4 = r4 ^ r7; // s212 xor
r1 = r1 + r7 + ((((sel >> 8u) & 1u) != 0u) ? 0x1c3dccf7u : 0x0ce0553du); // s213 add
r0 = __umulhi(r0, r1); // s214 mulhi
r3 = r3 + r6 + ((((sel >> 9u) & 1u) != 0u) ? 0xfadc9205u : 0x96bfec89u); // s215 add
r0 = rotl_imm(r0, 4u); // s216 rotl
r6 = r6 ^ r4; // s217 xor
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s218 shfl
r7 = r0 * r1 + r7; // s219 mad
r4 = r4 * r0; // s220 mul
r2 = r6 * r0 + r2; // s221 mad
r5 = r5 ^ r4; // s222 xor
r0 = r0 * r5; // s223 mul
r2 = r2 + r0 + ((((sel >> 9u) & 1u) != 0u) ? 0x66b15c04u : 0x61495681u); // s224 add
r3 = rotr_var(r3, r2); // s225 rotr
r2 = r3 * r3 + r2; // s226 mad
r6 = r6 ^ r0; // s227 xor
r4 = rotl_imm(r4, 30u); // s228 rotl
r2 = r2 + r3 + ((((sel >> 29u) & 1u) != 0u) ? 0x25bc17c2u : 0x70d05c34u); // s229 add
r1 = rotr_var(r1, r5); // s230 rotr
r1 = r1 + r4 + ((((sel >> 8u) & 1u) != 0u) ? 0x2d8728f3u : 0x32a28384u); // s231 add
r1 = rotl_imm(r1, 6u); // s232 rotl
r2 = r2 + r0 + ((((sel >> 21u) & 1u) != 0u) ? 0x61e81fe6u : 0xcf0949f1u); // s233 add
r4 = rotl_imm(r4, 2u); // s234 rotl
r2 = r2 - r6; // s235 sub
r6 = r6 | r3; // s236 or
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // s237 shfl
r1 = r1 ^ r3; // s238 xor
r2 = rotl_imm(r2, 1u); // s239 rotl
r5 = rotr_var(r5, r2); // s240 rotr
r4 = rotl_imm(r4, 10u); // s241 rotl
r6 = r6 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0x0a67565du : 0xe204fb50u); // s242 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r3, 2); // s243 shfl
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s244 shfl
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s245 shfl
r4 = r4 ^ r5; // s246 xor
r7 = r7 ^ r2; // s247 xor
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r6, 16); // s248 shfl
r1 = __umulhi(r1, r3); // s249 mulhi
r7 = r7 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x5a79fd6fu : 0x3d6daffdu); // s250 add
r6 = r6 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x6beb28c2u : 0x84334aeau); // s251 add
r7 = r7 - r1; // s252 sub
r5 = rotr_var(r5, r2); // s253 rotr
r2 = __umulhi(r2, r5); // s254 mulhi
r6 = r6 * r3; // s255 mul
}
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash_bound<<<nonces / block, block>>>(ds, out, baseNonce, mask, iw);
return cudaGetLastError();
}
cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash_bound);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash_bound, (int)(32u * blockWarps), 0);
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000". Do not edit by hand.
// Memory-hard dataset core, the same text that the Mac's Metal kernels and CPU verifier were checked against.
// Included by kernel.cu (device), host.cu (host reference) and proto-opencl/host.c (C99 host reference).
// See proto-metal/MEMHARD.md for the construction. kernel.cl carries the same text in OpenCL C.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#if defined(__CUDACC__)
#define IGNEUM_HD __host__ __device__ __forceinline__
#elif defined(_MSC_VER) && !defined(__cplusplus)
#define IGNEUM_HD static __inline
#else
#define IGNEUM_HD static inline
#endif
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
IGNEUM_HD uint32_t mh_rotl(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
IGNEUM_HD void mh_chacha_block(const uint32_t* x, uint32_t* y) {
for (uint32_t i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint32_t r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint32_t i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
IGNEUM_HD void mh_cache_segment(uint32_t* cache, uint32_t seg) {
uint32_t prev[16]; uint32_t x[16]; uint32_t y[16];
for (uint32_t i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint32_t j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0xe23f9008u ^ prev[4];
x[5] = 0xde33e763u ^ prev[5];
x[6] = 0xc5ba415du ^ prev[6];
x[7] = 0x8ddf6786u ^ prev[7];
x[8] = 0x59f4a4beu ^ prev[8];
x[9] = 0x8a3bc680u ^ prev[9];
x[10] = 0x701b8e40u ^ prev[10];
x[11] = 0x3b59025au ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
uint32_t* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
IGNEUM_HD void mh_mixer(uint32_t* s, uint32_t rk) {
s[0] = (s[0] ^ (0xe5bef5a3u + rk)) * 0xd1d79e7fu;
s[1] = (s[1] ^ (0xdb2a7d90u + rk)) * 0xbcb61f8bu;
s[2] = (s[2] ^ (0xcd1fa7e1u + rk)) * 0x970e91abu;
s[3] = (s[3] ^ (0x30289419u + rk)) * 0xd749d96du;
s[4] = (s[4] ^ (0x0a730d58u + rk)) * 0x143d7339u;
s[5] = (s[5] ^ (0x432f8579u + rk)) * 0x2cde0d69u;
s[6] = (s[6] ^ (0x6ab978a5u + rk)) * 0x12d0a8c1u;
s[7] = (s[7] ^ (0x8c984f49u + rk)) * 0x2d335be9u;
s[8] = (s[8] ^ (0x788c3c9eu + rk)) * 0x80a8aae9u;
s[9] = (s[9] ^ (0x051eef02u + rk)) * 0x7ac896c7u;
s[10] = (s[10] ^ (0x05e77db9u + rk)) * 0x9de23db7u;
s[11] = (s[11] ^ (0x8b3cd4f3u + rk)) * 0xc362827du;
s[12] = (s[12] ^ (0x6948d6cfu + rk)) * 0x5f4cdb5bu;
s[13] = (s[13] ^ (0x0d8677f6u + rk)) * 0xfc6c5097u;
s[14] = (s[14] ^ (0xf9505c8cu + rk)) * 0x6f547f83u;
s[15] = (s[15] ^ (0x4513c163u + rk)) * 0x1ac31b47u;
MH_QR(s[0], s[4], s[8], s[12], 28u, 11u, 18u, 18u) MH_QR(s[1], s[5], s[9], s[13], 28u, 11u, 18u, 18u)
MH_QR(s[2], s[6], s[10], s[14], 28u, 11u, 18u, 18u) MH_QR(s[3], s[7], s[11], s[15], 28u, 11u, 18u, 18u)
MH_QR(s[0], s[5], s[10], s[15], 13u, 28u, 5u, 13u) MH_QR(s[1], s[6], s[11], s[12], 13u, 28u, 5u, 13u)
MH_QR(s[2], s[7], s[8], s[13], 13u, 28u, 5u, 13u) MH_QR(s[3], s[4], s[9], s[14], 13u, 28u, 5u, 13u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
IGNEUM_HD void mh_item(const uint32_t* cache, const uint32_t* leaf, uint32_t t, uint32_t* s) {
s[0] = 0xe23f9008u;
s[1] = 0xde33e763u;
s[2] = 0xc5ba415du;
s[3] = 0x8ddf6786u;
s[4] = 0x59f4a4beu;
s[5] = 0x8a3bc680u;
s[6] = 0x701b8e40u;
s[7] = 0x3b59025au;
s[8] = t * 0xd1d79e7fu + 0xe5bef5a3u;
s[9] = t * 0xbcb61f8bu + 0xdb2a7d90u;
s[10] = t * 0x970e91abu + 0xcd1fa7e1u;
s[11] = t * 0xd749d96du + 0x30289419u;
s[12] = t * 0x143d7339u + 0x0a730d58u;
s[13] = t * 0x2cde0d69u + 0x432f8579u;
s[14] = t * 0x12d0a8c1u + 0x6ab978a5u;
s[15] = t * 0x2d335be9u + 0x8c984f49u;
for (uint32_t i = 0u; i < 16u; ++i) s[i] ^= leaf[i];
for (uint32_t r = 0u; r < 8u; ++r) {
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
const uint32_t* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// Class v5 (docs/design/class-v5-stored-state.md): leaf(t) = leaves[t mod nLeaves], 16 words per leaf (leaves.bin).
IGNEUM_HD const uint32_t* mh_leaf(const uint32_t* leaves, uint32_t nLeaves, uint32_t t) { return leaves + ((t % nLeaves) * 16u); }
// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 1 9 13 14 of w.
IGNEUM_HD uint32_t mh_j(uint32_t w) { return ((w >> 1u) & 1u) | (((w >> 9u) & 1u) << 1) | (((w >> 13u) & 1u) << 2) | (((w >> 14u) & 1u) << 3); }
IGNEUM_HD uint32_t mh_t(uint32_t w) { w = (w & 0x00003fffu) | ((w >> 15u) << 14u); w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x000001ffu) | ((w >> 10u) << 9u); w = (w & 0x00000001u) | ((w >> 2u) << 1u); return w; }
IGNEUM_HD uint32_t mh_addr(uint32_t t, uint32_t j) { uint32_t w = t; w = ((w >> 1u) << 2u) | (w & 0x00000001u) | (((j >> 0u) & 1u) << 1u); w = ((w >> 9u) << 10u) | (w & 0x000001ffu) | (((j >> 1u) & 1u) << 9u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 2u) & 1u) << 13u); w = ((w >> 14u) << 15u) | (w & 0x00003fffu) | (((j >> 3u) & 1u) << 14u); return w; }
// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w).
IGNEUM_HD uint32_t mh_word(const uint32_t* cache, const uint32_t* leaves, uint32_t nLeaves, uint32_t w) { uint32_t s[16]; mh_item(cache, mh_leaf(leaves, nLeaves, mh_t(w)), mh_t(w), s); return s[mh_j(w)]; }

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#include <metal_stdlib>
using namespace metal;
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
inline void mh_chacha_block(const thread uint* x, thread uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
inline void mh_cache_segment(device uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0xe23f9008u ^ prev[4];
x[5] = 0xde33e763u ^ prev[5];
x[6] = 0xc5ba415du ^ prev[6];
x[7] = 0x8ddf6786u ^ prev[7];
x[8] = 0x59f4a4beu ^ prev[8];
x[9] = 0x8a3bc680u ^ prev[9];
x[10] = 0x701b8e40u ^ prev[10];
x[11] = 0x3b59025au ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
device uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
inline void mh_mixer(thread uint* s, uint rk) {
s[0] = (s[0] ^ (0xe5bef5a3u + rk)) * 0xd1d79e7fu;
s[1] = (s[1] ^ (0xdb2a7d90u + rk)) * 0xbcb61f8bu;
s[2] = (s[2] ^ (0xcd1fa7e1u + rk)) * 0x970e91abu;
s[3] = (s[3] ^ (0x30289419u + rk)) * 0xd749d96du;
s[4] = (s[4] ^ (0x0a730d58u + rk)) * 0x143d7339u;
s[5] = (s[5] ^ (0x432f8579u + rk)) * 0x2cde0d69u;
s[6] = (s[6] ^ (0x6ab978a5u + rk)) * 0x12d0a8c1u;
s[7] = (s[7] ^ (0x8c984f49u + rk)) * 0x2d335be9u;
s[8] = (s[8] ^ (0x788c3c9eu + rk)) * 0x80a8aae9u;
s[9] = (s[9] ^ (0x051eef02u + rk)) * 0x7ac896c7u;
s[10] = (s[10] ^ (0x05e77db9u + rk)) * 0x9de23db7u;
s[11] = (s[11] ^ (0x8b3cd4f3u + rk)) * 0xc362827du;
s[12] = (s[12] ^ (0x6948d6cfu + rk)) * 0x5f4cdb5bu;
s[13] = (s[13] ^ (0x0d8677f6u + rk)) * 0xfc6c5097u;
s[14] = (s[14] ^ (0xf9505c8cu + rk)) * 0x6f547f83u;
s[15] = (s[15] ^ (0x4513c163u + rk)) * 0x1ac31b47u;
MH_QR(s[0], s[4], s[8], s[12], 28u, 11u, 18u, 18u) MH_QR(s[1], s[5], s[9], s[13], 28u, 11u, 18u, 18u)
MH_QR(s[2], s[6], s[10], s[14], 28u, 11u, 18u, 18u) MH_QR(s[3], s[7], s[11], s[15], 28u, 11u, 18u, 18u)
MH_QR(s[0], s[5], s[10], s[15], 13u, 28u, 5u, 13u) MH_QR(s[1], s[6], s[11], s[12], 13u, 28u, 5u, 13u)
MH_QR(s[2], s[7], s[8], s[13], 13u, 28u, 5u, 13u) MH_QR(s[3], s[4], s[9], s[14], 13u, 28u, 5u, 13u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
inline void mh_item(device const uint* cache, device const uint* leaf, uint t, thread uint* s) {
s[0] = 0xe23f9008u;
s[1] = 0xde33e763u;
s[2] = 0xc5ba415du;
s[3] = 0x8ddf6786u;
s[4] = 0x59f4a4beu;
s[5] = 0x8a3bc680u;
s[6] = 0x701b8e40u;
s[7] = 0x3b59025au;
s[8] = t * 0xd1d79e7fu + 0xe5bef5a3u;
s[9] = t * 0xbcb61f8bu + 0xdb2a7d90u;
s[10] = t * 0x970e91abu + 0xcd1fa7e1u;
s[11] = t * 0xd749d96du + 0x30289419u;
s[12] = t * 0x143d7339u + 0x0a730d58u;
s[13] = t * 0x2cde0d69u + 0x432f8579u;
s[14] = t * 0x12d0a8c1u + 0x6ab978a5u;
s[15] = t * 0x2d335be9u + 0x8c984f49u;
for (uint i = 0u; i < 16u; ++i) s[i] ^= leaf[i];
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
device const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// Class v5 (docs/design/class-v5-stored-state.md): leaf(t) = leaves[t mod nLeaves], 16 words per leaf (leaves.bin).
inline device const uint* mh_leaf(device const uint* leaves, uint nLeaves, uint t) { return leaves + ((t % nLeaves) * 16u); }
// Era layout (docs/plans/era-layout.md 1.2): dataset word w holds word mh_j(w) of item mh_t(w); j's bits sit at positions 1 9 13 14 of w.
inline uint mh_j(uint w) { return ((w >> 1u) & 1u) | (((w >> 9u) & 1u) << 1) | (((w >> 13u) & 1u) << 2) | (((w >> 14u) & 1u) << 3); }
inline uint mh_t(uint w) { w = (w & 0x00003fffu) | ((w >> 15u) << 14u); w = (w & 0x00001fffu) | ((w >> 14u) << 13u); w = (w & 0x000001ffu) | ((w >> 10u) << 9u); w = (w & 0x00000001u) | ((w >> 2u) << 1u); return w; }
inline uint mh_addr(uint t, uint j) { uint w = t; w = ((w >> 1u) << 2u) | (w & 0x00000001u) | (((j >> 0u) & 1u) << 1u); w = ((w >> 9u) << 10u) | (w & 0x000001ffu) | (((j >> 1u) & 1u) << 9u); w = ((w >> 13u) << 14u) | (w & 0x00001fffu) | (((j >> 2u) & 1u) << 13u); w = ((w >> 14u) << 15u) | (w & 0x00003fffu) | (((j >> 3u) & 1u) << 14u); return w; }
// dataset[w] without the dataset: derive item mh_t(w) and take word mh_j(w).
inline uint mh_word(device const uint* cache, device const uint* leaves, uint nLeaves, uint w) { uint s[16]; mh_item(cache, mh_leaf(leaves, nLeaves, mh_t(w)), mh_t(w), s); return s[mh_j(w)]; }
// One thread per segment (2^16 threads).
kernel void igneum_cache_fill(device uint* cache [[buffer(0)]], uint gid [[thread_position_in_grid]]) {
mh_cache_segment(cache, gid);
}
// One thread per 64-byte item (dataset words / 16 threads).
// Class v5: the window's leaves (leaves.bin, IGNEUM_STATE_LEAVES x 16 words) in buffer 2, their count in buffer 3.
kernel void igneum_build(device const uint* cache [[buffer(0)]], device uint* dataset [[buffer(1)]],
device const uint* leaves [[buffer(2)]], constant uint& nLeaves [[buffer(3)]],
uint gid [[thread_position_in_grid]]) {
uint s[16];
mh_item(cache, mh_leaf(leaves, nLeaves, gid), gid, s);
for (uint i = 0u; i < 16u; ++i) dataset[mh_addr(gid, i)] = s[i];
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000". Do not edit by hand.
// Program metadata for host.cu plus the launch wrappers defined in kernel.cu.
// Also included by proto-opencl/host.c (C99), which defines IGNEUM_NO_CUDA first and reads only the macros.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#ifndef IGNEUM_NO_CUDA
#include <cuda_runtime.h>
#endif
#define IGNEUM_SEED_STRING "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000"
#define IGNEUM_SEED_BYTES_HEX "4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925"
#define IGNEUM_GENERATOR 5
#define IGNEUM_PROGRAM_ATTEMPT 0
#define IGNEUM_PROGRAM_ID 0xe5a4ac5978462156ull
#define IGNEUM_DAY_STRING "bytes:69676e65756d2d6461792ffd50000000000000"
#define IGNEUM_DAY_BYTES_HEX "69676e65756d2d6461792ffd50000000000000"
#define IGNEUM_DAY0 0xe23f9008u
#define IGNEUM_DAY1 0xde33e763u
#define IGNEUM_DATASET_LOG2 28
#define IGNEUM_MASK 0x0fffffffu
#define IGNEUM_LANES 32
#define IGNEUM_ITERATIONS 8
#define IGNEUM_INSTR_COUNT 64
#define IGNEUM_LOADS_PER_HASH 128
#define IGNEUM_WIDE_LOADS_PER_HASH 0
#define IGNEUM_OP_MIX "load=16 add=11 shfl=7 mad=6 xor=6 mul=4 mulhi=4 rotr=4 rotl=3 sub=2 or=1"
// Program class v5 (proof of stored state and of following, docs/design/class-v5-stored-state.md): generator version 5,
// class v4 over a dataset whose every item is keyed by the window's execution state (IGNEUM_STATE_* below, leaves.bin);
// a worker that runs another class refuses this pack, and a job line names the class it wants (class=v5 era=<hex>).
#define IGNEUM_PROGRAM_CLASS "v5"
#define IGNEUM_ERA_SEED_HEX "4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925"
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
#define IGNEUM_LOAD_CLASS "mx8-eraaf3a9139+sh256x27+state"
#define IGNEUM_CLASS_MIXER_MULT 8
#define IGNEUM_CACHE_GROWTH 1 // 1: cache words = 2^(26 + doublings(day)), doublings = floor(log2(1 + day / 1460))
#define IGNEUM_LOAD_SLOTS 16
#define IGNEUM_LOAD_MIX { 100, 0, 0 }
#define IGNEUM_LOAD_WIDTH_COUNTS { 16, 0, 0 } // loads of 4, 16, 64 bytes per program
#define IGNEUM_BYTES_PER_HASH 512
#define IGNEUM_FOLD_ROT 11
#define IGNEUM_FOLD_MUL 0x9e3779b1u
// Class v5 state (docs/design/class-v5-stored-state.md): the window's reference chain block and the state root after it;
// leaves.bin holds IGNEUM_STATE_LEAVES leaves of 16 little-endian words, leaf(t) = leaves[t mod IGNEUM_STATE_LEAVES].
#define IGNEUM_STATE_BLOCK_HEX "4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925"
#define IGNEUM_STATE_BLOCK_NUMBER 0
#define IGNEUM_STATE_ROOT_HEX "7e37a9fb19b154d32daf5bf30a50d339a75029fbc9eec9ea20e95439dba5a311"
#define IGNEUM_STATE_LEAVES 11
#define IGNEUM_STATE_RECORDS 11
#define IGNEUM_STATE_SAMPLED 0
#define IGNEUM_STATE_LEAVES_FNV64 0xf141bfee2a8b11b0ull
#define IGNEUM_STATE_LEAVES_FILE "leaves.bin"
// Era layout (5 October 2026, docs/plans/era-layout.md): NOT the lottery hash. Every dataset load reads
// idx = ((rotl(src * STRIDE_MUL, STRIDE_ROT) & window mask) | window offset) & MASK; the window of a load site is the
// dataset, a half or a quarter of it (IGNEUM_ERA_WINDOWS: site:shrink:offset); dataset word w holds word j(w) of item
// t(w) with j's bits at the INTERLEAVE positions (memhard.h: mh_t, mh_j, mh_addr).
#define IGNEUM_ERA_LABEL "af3a9139"
#define IGNEUM_ERA_SEED_WORDS { 0xaf3a9139u, 0x894db311u, 0xd6173573u, 0xc346bc0fu, 0x2d547cecu, 0xd5634ab8u, 0xb9584827u, 0x305d030eu }
#define IGNEUM_ERA_ALLOWED_WIDTHS { 1, 0, 0 } // words, ascending, 0 = unused; one entry pins the width
#define IGNEUM_ERA_WIDTH_WORDS 1
#define IGNEUM_ERA_STRIDE_MUL 0x2cb18b35u
#define IGNEUM_ERA_STRIDE_ROT 9
#define IGNEUM_ERA_INTERLEAVE { 1, 9, 13, 14 }
#define IGNEUM_ERA_WINDOWS "3:0:0 8:2:2 14:1:0 15:0:0 20:1:1 26:1:1 28:1:1 35:0:0 40:2:3 43:1:0 47:1:1 49:0:0 52:2:3 53:0:0 61:1:1 62:1:1"
// Latency-shadow block (Counter ASIC 3.0 item 8, docs/analysis/latency-shadow-2026-10-06.md): NOT the lottery hash. A block of
// IGNEUM_SHADOW_INSTRS ALU instructions (the ten non-load families) runs IGNEUM_SHADOW_REPS times at the end of every
// iteration; the 16 loads, the acceptance rule and the base program are the class's without the shadow.
#define IGNEUM_SHADOW_INSTRS 256
#define IGNEUM_SHADOW_REPS 27
#define IGNEUM_SHADOW_INSTRS_PER_HASH 55296
#define IGNEUM_SHADOW_OP_MIX "add=45 mad=31 shfl=31 xor=30 rotl=28 mul=22 or=18 mulhi=17 rotr=17 sub=17"
// 0 = closed-form dataset (ds_elem), 1 = memory-hard cache construction (MEMHARD.md, memhard.h)
#define IGNEUM_DATASET_MODE 1
#define IGNEUM_SEEDW_INIT { 0xbe8c5a0cu, 0x7646e626u, 0x508e29d0u, 0xfb8a5b4au, 0x53c50955u, 0x685d62fcu, 0x6065c013u, 0x881096ebu }
#define IGNEUM_KEY_INIT { 0xe23f9008u, 0xde33e763u, 0xc5ba415du, 0x8ddf6786u, 0x59f4a4beu, 0x8a3bc680u, 0x701b8e40u, 0x3b59025au }
#define IGNEUM_CACHE_LOG2_WORDS 26
#define IGNEUM_CACHE_SEGMENT_LOG2_LINES 6
#define IGNEUM_CACHE_SEGMENTS 65536u
#define IGNEUM_ITEM_ROUNDS 8
#define IGNEUM_MIXER_MULT 8 // mixer applications per round and after the last read (class v3, docs/plans/mixer-x4.md)
#define IGNEUM_MIX_ROT_INIT { 28u, 11u, 18u, 18u, 13u, 28u, 5u, 13u }
#define IGNEUM_MIX_MUL_INIT { 0xd1d79e7fu, 0xbcb61f8bu, 0x970e91abu, 0xd749d96du, 0x143d7339u, 0x2cde0d69u, 0x12d0a8c1u, 0x2d335be9u, 0x80a8aae9u, 0x7ac896c7u, 0x9de23db7u, 0xc362827du, 0x5f4cdb5bu, 0xfc6c5097u, 0x6f547f83u, 0x1ac31b47u }
#define IGNEUM_MIX_RC_INIT { 0xe5bef5a3u, 0xdb2a7d90u, 0xcd1fa7e1u, 0x30289419u, 0x0a730d58u, 0x432f8579u, 0x6ab978a5u, 0x8c984f49u, 0x788c3c9eu, 0x051eef02u, 0x05e77db9u, 0x8b3cd4f3u, 0x6948d6cfu, 0x0d8677f6u, 0xf9505c8cu, 0x4513c163u }
#ifndef IGNEUM_NO_CUDA
// Defined in kernel.cu. All launch on the default stream and return cudaGetLastError().
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments);
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, const uint32_t* leaves, uint32_t nLeaves, uint32_t nItems);
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps);
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#endif

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{
"format": "igneum-program-pack-3",
"generator": 5,
"attempt": 0,
"program_id": "0xe5a4ac5978462156",
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
"dataset_mode": "memory-hard",
"seed": "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000",
"seed_bytes": "4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925",
"seed_words": ["0xbe8c5a0c", "0x7646e626", "0x508e29d0", "0xfb8a5b4a", "0x53c50955", "0x685d62fc", "0x6065c013", "0x881096eb"],
"seed_derivation": "seed_words = FNV-1a 64 over seed_bytes (attempt 0) or seed_bytes || attempt_le32 (attempt k >= 1), basis ^ (salt * 0x9E3779B97F4A7C15) for salt 0..3, then h ^= h>>33; h *= 0xff51afd7ed558ccd; h ^= h>>33; words[2*salt] = low 32, words[2*salt+1] = high 32",
"generator_rule": "version 2: exactly 16 load slots drawn first from instructions 1..63 (partial Fisher-Yates), the other 48 ops from the ten non-load weights (sum 75); a load's source is drawn from the registers other than dst written by an earlier instruction and not read by a load since; the candidate must pass the acceptance rule of spec 01 section 1.4.6 (static: no cyclically stale load source, every register has an injecting write; dynamic: 64 units on the seed-keyed closed-form dataset with no constant register bit, no lane-constant load site, under 164 saturated final values, every output bit within 136 of 1024, distinct addresses above 245760), else the next attempt of the seed is tried",
"lanes": 32,
"registers": 8,
"iterations": 8,
"instruction_count": 64,
"loads_per_hash": 128,
"program_class": "v5",
"era_seed_bytes": "4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925",
"state": {
"block": "4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925",
"block_number": 0,
"root": "7e37a9fb19b154d32daf5bf30a50d339a75029fbc9eec9ea20e95439dba5a311",
"leaves": 11,
"records": 11,
"sampled": false,
"leaves_fnv1a64": "0xf141bfee2a8b11b0",
"leaf_derivation": "leaves[i] = Blake2b-512('igneum-sd1/' || root || i_le32 || record_i) as 16 little-endian words; item t XORs leaves[t mod leaves] into its 16 initial words before the first mixer",
"file": "leaves.bin"
},
"load_class": "mx8-eraaf3a9139+sh256x27+state",
"mixer_mult": 8,
"cache_growth": true,
"mixer": "class v3 (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): every mixer application of the item derivation is 8 applications with round keys (r * 8 + j + 1) * 0x9E3779B9, the 8 dependent cache reads per item unchanged; cache growth rule option C: cache words = 2^(26 + doublings(day)), dataset words = 2^(genesis_log2 + doublings(day)), doublings(day) = floor(log2(1 + day / 1460)) for day = days since genesis",
"load_slots": 16,
"load_mix_percent_4_16_64": [100, 0, 0],
"load_width_counts_4_16_64": [16, 0, 0],
"bytes_per_hash": 512,
"wide_load": "read-width experiment (5 October 2026, docs/plans/read-width.md), NOT the lottery hash: a load of W words (width field, 4 or 16) reads dataset[b .. b + W) with b = (src & mask) & ~(W - 1) and folds every word into dst: x = dst ^ w[0]; for j in 1..W: x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]; dst = x; width 1 is the plain load; the width is drawn per instruction from the class mix with one extra below(100) draw after the nine of version 2, and the program id is FNV-1a 64 over 'igneum-program-rw/' || generator_le32 || seed words || attempt_le32 || mix[3] || load_slots",
"era": {
"label": "af3a9139",
"seed_words": ["0xaf3a9139", "0x894db311", "0xd6173573", "0xc346bc0f", "0x2d547cec", "0xd5634ab8", "0xb9584827", "0x305d030e"],
"draw": "docs/plans/era-layout.md 1.1: SplitMix64 seeded with seed_words[0] | seed_words[1] << 32 of seed_words_from_bytes('igneum-era/' || n_le64 || E_n); width = allowed[below(|allowed|)], stride_mul = low32(next()) | 1, stride_rot = 1 + below(31), then four next() draws for a partial Fisher-Yates over positions log2(W)..15 of which 4 - log2(W) are used",
"allowed_widths": [1],
"width_words": 1,
"stride_mul": "0x2cb18b35",
"stride_rot": 9,
"interleave": [1, 9, 13, 14],
"address": "y = rotl(src * stride_mul, stride_rot); k = min(win, D - 26); idx = ((y & (mask >> k)) | ((off & (2^k - 1)) << (D - k))) & mask; a wide load aligns idx down to W words",
"windows": "per instruction, after the width roll: win = below(3), off = low32(next()) & (2^win - 1); used on a load slot (the instruction's win and off fields)",
"dataset_word": "dataset[w] = item(t(w))[j(w)]: j(w) gathers the bits of w at the interleave positions, t(w) is w with those bits removed",
"program_id_suffix": "'era/' || allowed[3] || width_words || stride_mul_le32 || stride_rot_le32 || interleave[4]"
},
"op_mix": {"load": 16, "add": 11, "shfl": 7, "mad": 6, "xor": 6, "mul": 4, "mulhi": 4, "rotr": 4, "rotl": 3, "sub": 2, "or": 1},
"register_init": "for i in 0..7: x = nonce ^ seed_words[i]; x += 0x9e3779b9 * (i+1) (mod 2^32); x = splitmix32(x); r[i] = x ^ seed_words[(i+1) & 7]",
"splitmix32": "x ^= x>>16; x *= 0x7feb352d; x ^= x>>15; x *= 0x846ca68b; x ^= x>>16",
"iteration": "sel = r0 sampled once at the top of each iteration, then all instructions in order",
"output": "lo = r0 ^ rotl(r1,7) ^ rotl(r2,14) ^ rotl(r3,21); hi = r4 ^ rotl(r5,9) ^ rotl(r6,18) ^ rotl(r7,27); out = (hi << 32) | lo",
"op_semantics": {
"add": "dst = dst + src + (bit `bit` of sel ? imm2 : imm)",
"sub": "dst = dst - src",
"mul": "dst = dst * src (low 32)",
"mulhi": "dst = high 32 bits of dst * src",
"xor": "dst = dst ^ src",
"or": "dst = dst | src",
"rotl": "dst = rotl(dst, rot), rot in 1..31",
"rotr": "dst = rotr(dst, src & 31)",
"mad": "dst = src * src2 + dst",
"shfl": "dst = dst ^ (src of lane (lane ^ mask)), mask in {1,2,4,8,16}, within the 32-lane warp",
"load": "dst = dst ^ dataset[src & dataset.mask]",
"wload": "base = (src of lane 0 & dataset.mask) & ~31; dst = dst ^ dataset[base + lane] (warp-coalesced 128-byte load, lever b, only when --wide-frac > 0)"
},
"dataset": {
"log2_words": 28,
"bytes": 1073741824,
"mask": "0x0fffffff",
"day": "bytes:69676e65756d2d6461792ffd50000000000000",
"day_bytes": "69676e65756d2d6461792ffd50000000000000",
"day_words_from": "seed_words_from_bytes(day_bytes)",
"d0": "0xe23f9008",
"d1": "0xde33e763",
"mode": "memory-hard",
"spec": "proto-metal/MEMHARD.md",
"key": ["0xe23f9008", "0xde33e763", "0xc5ba415d", "0x8ddf6786", "0x59f4a4be", "0x8a3bc680", "0x701b8e40", "0x3b59025a"],
"key_derivation": "the 8 words of seed_words_from_bytes(day_bytes); d0, d1 are key[0], key[1]",
"cache": {"log2_words": 26, "bytes": 268435456, "line_words": 16, "segment_lines": 64, "segments": 65536, "block": "ChaCha12 core + feed-forward, rotations 16 12 8 7", "sigma": ["0x61707865", "0x3320646e", "0x79622d32", "0x6b206574"], "tag": ["0x49676e65", "0x756d4d48"], "chain": "in_j = prev_line ^ (sigma[0..3] || key[0..7] || seg || j || tag[0..1]); line_j = block(in_j); prev_0 = 0"},
"mixer": {"draw": "SplitMix64 seeded with key[0] | key[1] << 32: rot[0..7] = 1 + next() % 31, mul[0..15] = low32(next()) | 1, rc[0..15] = low32(next())", "rot": [28, 11, 18, 18, 13, 28, 5, 13], "mul": ["0xd1d79e7f", "0xbcb61f8b", "0x970e91ab", "0xd749d96d", "0x143d7339", "0x2cde0d69", "0x12d0a8c1", "0x2d335be9", "0x80a8aae9", "0x7ac896c7", "0x9de23db7", "0xc362827d", "0x5f4cdb5b", "0xfc6c5097", "0x6f547f83", "0x1ac31b47"], "rc": ["0xe5bef5a3", "0xdb2a7d90", "0xcd1fa7e1", "0x30289419", "0x0a730d58", "0x432f8579", "0x6ab978a5", "0x8c984f49", "0x788c3c9e", "0x051eef02", "0x05e77db9", "0x8b3cd4f3", "0x6948d6cf", "0x0d8677f6", "0xf9505c8c", "0x4513c163"], "round": "for i in 0..15: s[i] = (s[i] ^ (rc[i] + (r+1) * 0x9E3779B9)) * mul[i]; then quarter rounds on columns (0,4,8,12) (1,5,9,13) (2,6,10,14) (3,7,11,15) with rot[0..3] and diagonals (0,5,10,15) (1,6,11,12) (2,7,8,13) (3,4,9,14) with rot[4..7]", "quarter_round": "a += b; d ^= a; d = rotl(d, r1); c += d; b ^= c; b = rotl(b, r2); a += b; d ^= a; d = rotl(d, r3); c += d; b ^= c; b = rotl(b, r4)"},
"mixer_mult": 8,
"item": "s[0..7] = key; s[8+i] = t * mul[i] + rc[i] for i in 0..7; for r in 0..7: for j in 0..7: s = M(s, rk = (r * 8 + j + 1) * 0x9E3779B9); line = s[0] & 0x003fffff; s[i] ^= cache[line * 16 + i]; then for j in 0..7: s = M(s, rk = (64 + j + 1) * 0x9E3779B9); item(t) = s",
"word": "dataset[w] = item(w >> 4)[w & 15]"
},
"shadow": {"instrs": 256, "reps": 27, "instrs_per_hash": 55296, "op_mix": {"add": 45, "mad": 31, "shfl": 31, "xor": 30, "rotl": 28, "mul": 22, "or": 18, "mulhi": 17, "rotr": 17, "sub": 17}, "rule": "Counter ASIC 3.0 item 8 (docs/analysis/latency-shadow-2026-10-06.md): after the 64 base instructions the program stream draws instrs more ALU instructions (the non-load table, nine draws each, the source as on an ALU slot); the block runs reps times at the end of every iteration with the iteration's sel; the acceptance rule interprets the base program only", "program_id_suffix": "'shadow/' || instrs_le16 || reps_le16", "instructions": [
{"i": 0, "op": "or", "dst": 6, "src": 0, "src2": 2, "imm": "0xc1eb1523", "imm2": "0x925958ea", "rot": 14, "bit": 14, "mask": 8},
{"i": 1, "op": "mul", "dst": 7, "src": 3, "src2": 4, "imm": "0xc7044334", "imm2": "0x755566b6", "rot": 19, "bit": 17, "mask": 8},
{"i": 2, "op": "mad", "dst": 3, "src": 5, "src2": 5, "imm": "0x33b52f17", "imm2": "0xcc459a7a", "rot": 5, "bit": 19, "mask": 16},
{"i": 3, "op": "add", "dst": 7, "src": 4, "src2": 4, "imm": "0x97d3d105", "imm2": "0x38e58a06", "rot": 11, "bit": 6, "mask": 1},
{"i": 4, "op": "add", "dst": 6, "src": 0, "src2": 6, "imm": "0x29b87b9a", "imm2": "0x9629673d", "rot": 16, "bit": 20, "mask": 8},
{"i": 5, "op": "shfl", "dst": 6, "src": 2, "src2": 5, "imm": "0xb61f2e77", "imm2": "0x30e3807c", "rot": 1, "bit": 7, "mask": 1},
{"i": 6, "op": "mad", "dst": 5, "src": 3, "src2": 5, "imm": "0x0de66253", "imm2": "0xfdfdd03e", "rot": 4, "bit": 27, "mask": 4},
{"i": 7, "op": "rotl", "dst": 3, "src": 7, "src2": 1, "imm": "0x688514dd", "imm2": "0x139d08b5", "rot": 5, "bit": 1, "mask": 1},
{"i": 8, "op": "add", "dst": 0, "src": 7, "src2": 3, "imm": "0xa7c1fb0f", "imm2": "0x4a5f55e1", "rot": 15, "bit": 12, "mask": 1},
{"i": 9, "op": "mul", "dst": 5, "src": 7, "src2": 2, "imm": "0x1a64de5a", "imm2": "0xe37b0875", "rot": 5, "bit": 27, "mask": 16},
{"i": 10, "op": "xor", "dst": 4, "src": 5, "src2": 3, "imm": "0x750d4f1a", "imm2": "0x2f3d9402", "rot": 3, "bit": 14, "mask": 2},
{"i": 11, "op": "mulhi", "dst": 6, "src": 4, "src2": 5, "imm": "0x2eaa86c6", "imm2": "0x9fd5b22f", "rot": 30, "bit": 10, "mask": 1},
{"i": 12, "op": "rotl", "dst": 5, "src": 2, "src2": 4, "imm": "0x8df50473", "imm2": "0x23d780ce", "rot": 13, "bit": 9, "mask": 1},
{"i": 13, "op": "mad", "dst": 0, "src": 2, "src2": 1, "imm": "0xa956a7e6", "imm2": "0x58dbb356", "rot": 31, "bit": 11, "mask": 8},
{"i": 14, "op": "mulhi", "dst": 2, "src": 4, "src2": 6, "imm": "0x6fbfb145", "imm2": "0x064eb015", "rot": 20, "bit": 2, "mask": 4},
{"i": 15, "op": "or", "dst": 3, "src": 1, "src2": 5, "imm": "0xd313bc27", "imm2": "0x9f0fc235", "rot": 17, "bit": 16, "mask": 1},
{"i": 16, "op": "sub", "dst": 0, "src": 5, "src2": 0, "imm": "0x86cbd336", "imm2": "0x94715167", "rot": 17, "bit": 31, "mask": 8},
{"i": 17, "op": "mul", "dst": 0, "src": 6, "src2": 3, "imm": "0x95911c6b", "imm2": "0x816cea32", "rot": 23, "bit": 1, "mask": 2},
{"i": 18, "op": "shfl", "dst": 5, "src": 1, "src2": 3, "imm": "0xf563dcad", "imm2": "0xb2889856", "rot": 14, "bit": 24, "mask": 4},
{"i": 19, "op": "or", "dst": 3, "src": 4, "src2": 2, "imm": "0x7bb48d19", "imm2": "0xbf95ad6f", "rot": 8, "bit": 30, "mask": 16},
{"i": 20, "op": "mad", "dst": 6, "src": 3, "src2": 2, "imm": "0xeb686a8d", "imm2": "0x8bda9f8a", "rot": 11, "bit": 18, "mask": 1},
{"i": 21, "op": "rotl", "dst": 0, "src": 6, "src2": 0, "imm": "0x0915df51", "imm2": "0xa1365cda", "rot": 11, "bit": 25, "mask": 1},
{"i": 22, "op": "rotl", "dst": 3, "src": 0, "src2": 3, "imm": "0xc09e4cdc", "imm2": "0x50c1369d", "rot": 25, "bit": 31, "mask": 2},
{"i": 23, "op": "xor", "dst": 6, "src": 4, "src2": 1, "imm": "0xce01abec", "imm2": "0x5ff8c52e", "rot": 30, "bit": 19, "mask": 8},
{"i": 24, "op": "or", "dst": 4, "src": 2, "src2": 4, "imm": "0xdacf9e4b", "imm2": "0x086a5684", "rot": 2, "bit": 10, "mask": 2},
{"i": 25, "op": "add", "dst": 1, "src": 6, "src2": 3, "imm": "0x53e74799", "imm2": "0xfc2f6d17", "rot": 8, "bit": 7, "mask": 16},
{"i": 26, "op": "rotr", "dst": 7, "src": 6, "src2": 7, "imm": "0xc89a75a0", "imm2": "0x67813253", "rot": 24, "bit": 13, "mask": 1},
{"i": 27, "op": "add", "dst": 7, "src": 5, "src2": 4, "imm": "0xb8fae90e", "imm2": "0x787048dc", "rot": 26, "bit": 27, "mask": 1},
{"i": 28, "op": "xor", "dst": 4, "src": 1, "src2": 0, "imm": "0x4c90c2ea", "imm2": "0x2ce7865b", "rot": 4, "bit": 7, "mask": 2},
{"i": 29, "op": "xor", "dst": 6, "src": 1, "src2": 6, "imm": "0x6131ab08", "imm2": "0xd1825676", "rot": 4, "bit": 30, "mask": 2},
{"i": 30, "op": "mulhi", "dst": 2, "src": 0, "src2": 1, "imm": "0xbe4a545f", "imm2": "0xdc29e823", "rot": 17, "bit": 5, "mask": 8},
{"i": 31, "op": "rotr", "dst": 1, "src": 4, "src2": 1, "imm": "0x4d2f9cdc", "imm2": "0xdee1cc73", "rot": 5, "bit": 16, "mask": 4},
{"i": 32, "op": "xor", "dst": 7, "src": 4, "src2": 5, "imm": "0x9d277aaa", "imm2": "0xa902fca5", "rot": 11, "bit": 3, "mask": 1},
{"i": 33, "op": "mad", "dst": 3, "src": 2, "src2": 6, "imm": "0x7db09644", "imm2": "0x077bf3d9", "rot": 30, "bit": 19, "mask": 2},
{"i": 34, "op": "add", "dst": 3, "src": 1, "src2": 1, "imm": "0xd2dc42eb", "imm2": "0x9ffd510b", "rot": 17, "bit": 12, "mask": 2},
{"i": 35, "op": "add", "dst": 4, "src": 7, "src2": 0, "imm": "0xad8eda6f", "imm2": "0xf871ba37", "rot": 24, "bit": 7, "mask": 4},
{"i": 36, "op": "add", "dst": 7, "src": 4, "src2": 3, "imm": "0xb0cef8f4", "imm2": "0xd02d30ca", "rot": 22, "bit": 3, "mask": 16},
{"i": 37, "op": "mad", "dst": 4, "src": 3, "src2": 2, "imm": "0x6ed99a66", "imm2": "0x83dc97c0", "rot": 4, "bit": 1, "mask": 4},
{"i": 38, "op": "mad", "dst": 5, "src": 7, "src2": 7, "imm": "0xe24fdd24", "imm2": "0x360f5c8b", "rot": 19, "bit": 9, "mask": 8},
{"i": 39, "op": "add", "dst": 3, "src": 6, "src2": 4, "imm": "0x2bd506e2", "imm2": "0x82e98a22", "rot": 28, "bit": 26, "mask": 1},
{"i": 40, "op": "rotl", "dst": 0, "src": 2, "src2": 1, "imm": "0xdb1faed3", "imm2": "0xf968a20d", "rot": 21, "bit": 30, "mask": 16},
{"i": 41, "op": "or", "dst": 1, "src": 0, "src2": 1, "imm": "0xe6dfe522", "imm2": "0xb75813da", "rot": 10, "bit": 13, "mask": 1},
{"i": 42, "op": "add", "dst": 7, "src": 5, "src2": 7, "imm": "0xc0386e49", "imm2": "0x6435f6d8", "rot": 26, "bit": 28, "mask": 16},
{"i": 43, "op": "mulhi", "dst": 1, "src": 0, "src2": 4, "imm": "0xda497f7d", "imm2": "0xc4b748f4", "rot": 30, "bit": 10, "mask": 4},
{"i": 44, "op": "add", "dst": 5, "src": 6, "src2": 0, "imm": "0x3a8921a4", "imm2": "0x1f682c68", "rot": 12, "bit": 12, "mask": 1},
{"i": 45, "op": "add", "dst": 4, "src": 5, "src2": 6, "imm": "0xeeca4334", "imm2": "0xf246e180", "rot": 26, "bit": 1, "mask": 1},
{"i": 46, "op": "xor", "dst": 2, "src": 3, "src2": 5, "imm": "0x052178c3", "imm2": "0xaab31f10", "rot": 28, "bit": 16, "mask": 8},
{"i": 47, "op": "xor", "dst": 2, "src": 5, "src2": 0, "imm": "0x91fd7273", "imm2": "0xacc42b07", "rot": 22, "bit": 27, "mask": 4},
{"i": 48, "op": "mad", "dst": 7, "src": 4, "src2": 1, "imm": "0x05a2970f", "imm2": "0x14876824", "rot": 10, "bit": 5, "mask": 1},
{"i": 49, "op": "mad", "dst": 2, "src": 6, "src2": 1, "imm": "0x4440d6de", "imm2": "0x352023f9", "rot": 10, "bit": 25, "mask": 8},
{"i": 50, "op": "mad", "dst": 7, "src": 0, "src2": 7, "imm": "0xa6f82633", "imm2": "0x78465772", "rot": 13, "bit": 8, "mask": 4},
{"i": 51, "op": "add", "dst": 5, "src": 6, "src2": 5, "imm": "0x745776d8", "imm2": "0x41bd68cc", "rot": 29, "bit": 26, "mask": 1},
{"i": 52, "op": "shfl", "dst": 3, "src": 0, "src2": 6, "imm": "0x8f94ebac", "imm2": "0xe4a208a0", "rot": 5, "bit": 16, "mask": 1},
{"i": 53, "op": "or", "dst": 4, "src": 0, "src2": 5, "imm": "0x7b1235f3", "imm2": "0x408b4ea9", "rot": 27, "bit": 19, "mask": 8},
{"i": 54, "op": "mad", "dst": 0, "src": 2, "src2": 4, "imm": "0x30114050", "imm2": "0xe71dff8f", "rot": 6, "bit": 30, "mask": 1},
{"i": 55, "op": "rotl", "dst": 5, "src": 1, "src2": 7, "imm": "0x69f92198", "imm2": "0x65496f29", "rot": 9, "bit": 20, "mask": 4},
{"i": 56, "op": "mul", "dst": 5, "src": 7, "src2": 6, "imm": "0x88b884d4", "imm2": "0x041b67f7", "rot": 25, "bit": 8, "mask": 16},
{"i": 57, "op": "rotl", "dst": 7, "src": 5, "src2": 6, "imm": "0x7d1e18bc", "imm2": "0xf54ade27", "rot": 27, "bit": 20, "mask": 1},
{"i": 58, "op": "sub", "dst": 7, "src": 6, "src2": 4, "imm": "0xa457bbab", "imm2": "0x4b05eb29", "rot": 6, "bit": 6, "mask": 4},
{"i": 59, "op": "rotl", "dst": 2, "src": 7, "src2": 7, "imm": "0x4890bdda", "imm2": "0xadcb3d99", "rot": 22, "bit": 26, "mask": 16},
{"i": 60, "op": "shfl", "dst": 7, "src": 1, "src2": 7, "imm": "0xe4da58eb", "imm2": "0x1d50080d", "rot": 22, "bit": 26, "mask": 2},
{"i": 61, "op": "add", "dst": 4, "src": 0, "src2": 5, "imm": "0x60d0ff55", "imm2": "0xcba6a161", "rot": 6, "bit": 7, "mask": 8},
{"i": 62, "op": "mul", "dst": 1, "src": 5, "src2": 1, "imm": "0x0fdc702e", "imm2": "0x6b1bd03a", "rot": 9, "bit": 23, "mask": 4},
{"i": 63, "op": "mulhi", "dst": 7, "src": 6, "src2": 1, "imm": "0xcc44ed62", "imm2": "0x931dd006", "rot": 1, "bit": 0, "mask": 2},
{"i": 64, "op": "mul", "dst": 5, "src": 0, "src2": 7, "imm": "0x448c3aba", "imm2": "0x1136818a", "rot": 23, "bit": 7, "mask": 1},
{"i": 65, "op": "rotr", "dst": 2, "src": 5, "src2": 1, "imm": "0xb520dfb8", "imm2": "0xdce7d8f4", "rot": 22, "bit": 10, "mask": 8},
{"i": 66, "op": "mulhi", "dst": 0, "src": 3, "src2": 4, "imm": "0x19fada48", "imm2": "0x3cc04e0e", "rot": 1, "bit": 24, "mask": 16},
{"i": 67, "op": "or", "dst": 0, "src": 7, "src2": 3, "imm": "0x1c5905b4", "imm2": "0xf896dfb7", "rot": 31, "bit": 30, "mask": 8},
{"i": 68, "op": "rotl", "dst": 0, "src": 1, "src2": 5, "imm": "0xa28511c1", "imm2": "0xbf649695", "rot": 19, "bit": 27, "mask": 1},
{"i": 69, "op": "rotl", "dst": 0, "src": 7, "src2": 5, "imm": "0x22e2fef3", "imm2": "0x468bec9e", "rot": 1, "bit": 28, "mask": 1},
{"i": 70, "op": "or", "dst": 2, "src": 3, "src2": 6, "imm": "0xcb542821", "imm2": "0xe084cf11", "rot": 15, "bit": 5, "mask": 8},
{"i": 71, "op": "mad", "dst": 3, "src": 7, "src2": 5, "imm": "0xf06b8f6a", "imm2": "0x7382e15f", "rot": 6, "bit": 28, "mask": 16},
{"i": 72, "op": "mad", "dst": 7, "src": 0, "src2": 4, "imm": "0x4f64c588", "imm2": "0x47b63ee9", "rot": 8, "bit": 10, "mask": 2},
{"i": 73, "op": "or", "dst": 4, "src": 3, "src2": 2, "imm": "0xff138eea", "imm2": "0x6fd90eda", "rot": 23, "bit": 3, "mask": 16},
{"i": 74, "op": "xor", "dst": 3, "src": 1, "src2": 0, "imm": "0x6011ece1", "imm2": "0x89579f15", "rot": 11, "bit": 2, "mask": 4},
{"i": 75, "op": "add", "dst": 1, "src": 3, "src2": 4, "imm": "0x3f4ffea2", "imm2": "0x8e35924e", "rot": 12, "bit": 15, "mask": 2},
{"i": 76, "op": "mul", "dst": 1, "src": 3, "src2": 7, "imm": "0x15efa846", "imm2": "0xa1c971f1", "rot": 14, "bit": 20, "mask": 1},
{"i": 77, "op": "mad", "dst": 0, "src": 3, "src2": 2, "imm": "0x8660530a", "imm2": "0xa013524b", "rot": 14, "bit": 12, "mask": 8},
{"i": 78, "op": "shfl", "dst": 2, "src": 0, "src2": 0, "imm": "0xcc2e96bd", "imm2": "0xe32c6f87", "rot": 10, "bit": 11, "mask": 16},
{"i": 79, "op": "mulhi", "dst": 1, "src": 0, "src2": 6, "imm": "0x61931e3f", "imm2": "0x86383e7f", "rot": 17, "bit": 3, "mask": 1},
{"i": 80, "op": "mulhi", "dst": 0, "src": 4, "src2": 7, "imm": "0xd9991afc", "imm2": "0xd00e8678", "rot": 24, "bit": 15, "mask": 16},
{"i": 81, "op": "mul", "dst": 4, "src": 2, "src2": 3, "imm": "0x472f70f4", "imm2": "0x9fde4236", "rot": 10, "bit": 5, "mask": 4},
{"i": 82, "op": "sub", "dst": 5, "src": 7, "src2": 6, "imm": "0x55a7acb1", "imm2": "0x9fde8df1", "rot": 30, "bit": 29, "mask": 16},
{"i": 83, "op": "mad", "dst": 0, "src": 2, "src2": 3, "imm": "0x1c487c40", "imm2": "0xd9d9a1c3", "rot": 9, "bit": 5, "mask": 4},
{"i": 84, "op": "sub", "dst": 7, "src": 2, "src2": 4, "imm": "0x515c0a72", "imm2": "0x6df5c83d", "rot": 28, "bit": 21, "mask": 4},
{"i": 85, "op": "xor", "dst": 1, "src": 2, "src2": 4, "imm": "0x917f1174", "imm2": "0x8e72e519", "rot": 9, "bit": 18, "mask": 16},
{"i": 86, "op": "shfl", "dst": 6, "src": 3, "src2": 3, "imm": "0xda856cc2", "imm2": "0x932ae8d8", "rot": 28, "bit": 1, "mask": 16},
{"i": 87, "op": "mad", "dst": 3, "src": 0, "src2": 0, "imm": "0x4ef22321", "imm2": "0x5666ada3", "rot": 4, "bit": 4, "mask": 1},
{"i": 88, "op": "rotl", "dst": 0, "src": 1, "src2": 3, "imm": "0xbb3ec00c", "imm2": "0xffe78937", "rot": 20, "bit": 19, "mask": 4},
{"i": 89, "op": "sub", "dst": 1, "src": 5, "src2": 4, "imm": "0x8f295708", "imm2": "0x6608577f", "rot": 17, "bit": 18, "mask": 16},
{"i": 90, "op": "shfl", "dst": 6, "src": 4, "src2": 5, "imm": "0xd953aa15", "imm2": "0x4ef9f062", "rot": 19, "bit": 9, "mask": 16},
{"i": 91, "op": "xor", "dst": 5, "src": 1, "src2": 5, "imm": "0x6c02cde2", "imm2": "0x118dbd2b", "rot": 2, "bit": 20, "mask": 16},
{"i": 92, "op": "rotl", "dst": 5, "src": 0, "src2": 5, "imm": "0x9f0b0c61", "imm2": "0xe26dbe7a", "rot": 12, "bit": 17, "mask": 2},
{"i": 93, "op": "mad", "dst": 6, "src": 1, "src2": 2, "imm": "0x78a44a91", "imm2": "0x3ce118a9", "rot": 18, "bit": 16, "mask": 16},
{"i": 94, "op": "rotr", "dst": 2, "src": 5, "src2": 3, "imm": "0x02295fcb", "imm2": "0xc3353c64", "rot": 5, "bit": 31, "mask": 16},
{"i": 95, "op": "or", "dst": 0, "src": 4, "src2": 4, "imm": "0x727120c3", "imm2": "0x528f4416", "rot": 6, "bit": 20, "mask": 8},
{"i": 96, "op": "mul", "dst": 7, "src": 3, "src2": 4, "imm": "0x919c42ea", "imm2": "0x87526aa5", "rot": 28, "bit": 1, "mask": 8},
{"i": 97, "op": "or", "dst": 5, "src": 0, "src2": 7, "imm": "0x8a0a100c", "imm2": "0xb2c65cc3", "rot": 13, "bit": 7, "mask": 4},
{"i": 98, "op": "add", "dst": 3, "src": 1, "src2": 1, "imm": "0xbcfdd8a7", "imm2": "0x386bb642", "rot": 8, "bit": 13, "mask": 8},
{"i": 99, "op": "add", "dst": 0, "src": 6, "src2": 7, "imm": "0xc921a021", "imm2": "0xa3962d03", "rot": 31, "bit": 9, "mask": 1},
{"i": 100, "op": "rotr", "dst": 1, "src": 0, "src2": 3, "imm": "0x918c6f69", "imm2": "0x1a125801", "rot": 18, "bit": 29, "mask": 16},
{"i": 101, "op": "add", "dst": 2, "src": 4, "src2": 1, "imm": "0x70da4067", "imm2": "0xc5990c5c", "rot": 3, "bit": 18, "mask": 4},
{"i": 102, "op": "rotl", "dst": 2, "src": 7, "src2": 0, "imm": "0x9048d081", "imm2": "0xc25a9f56", "rot": 3, "bit": 25, "mask": 16},
{"i": 103, "op": "shfl", "dst": 1, "src": 4, "src2": 7, "imm": "0x70ca1427", "imm2": "0x6632093d", "rot": 18, "bit": 28, "mask": 4},
{"i": 104, "op": "xor", "dst": 0, "src": 2, "src2": 0, "imm": "0x0637204c", "imm2": "0x3b1b7f94", "rot": 1, "bit": 12, "mask": 2},
{"i": 105, "op": "add", "dst": 4, "src": 3, "src2": 5, "imm": "0x1a5880cb", "imm2": "0xb15aec75", "rot": 31, "bit": 28, "mask": 1},
{"i": 106, "op": "shfl", "dst": 4, "src": 0, "src2": 4, "imm": "0x7c22cb00", "imm2": "0xc4df7949", "rot": 3, "bit": 15, "mask": 2},
{"i": 107, "op": "shfl", "dst": 7, "src": 0, "src2": 0, "imm": "0xd43c76ca", "imm2": "0x8d5b9751", "rot": 31, "bit": 28, "mask": 4},
{"i": 108, "op": "mad", "dst": 1, "src": 7, "src2": 3, "imm": "0x69879993", "imm2": "0x3c4e18b0", "rot": 19, "bit": 25, "mask": 4},
{"i": 109, "op": "mad", "dst": 0, "src": 2, "src2": 3, "imm": "0x8ce3a4a6", "imm2": "0x1b3f0b74", "rot": 19, "bit": 8, "mask": 2},
{"i": 110, "op": "or", "dst": 2, "src": 4, "src2": 5, "imm": "0xcdbdac98", "imm2": "0x8d0e9f92", "rot": 19, "bit": 13, "mask": 1},
{"i": 111, "op": "shfl", "dst": 6, "src": 1, "src2": 1, "imm": "0xe74157f6", "imm2": "0xf92dead6", "rot": 4, "bit": 14, "mask": 1},
{"i": 112, "op": "mad", "dst": 2, "src": 5, "src2": 3, "imm": "0x200831bc", "imm2": "0x1ee98048", "rot": 29, "bit": 14, "mask": 1},
{"i": 113, "op": "mulhi", "dst": 4, "src": 0, "src2": 7, "imm": "0xd6827ead", "imm2": "0xc0ee1933", "rot": 26, "bit": 23, "mask": 16},
{"i": 114, "op": "rotl", "dst": 7, "src": 2, "src2": 2, "imm": "0x6ae1be2b", "imm2": "0x83216a4e", "rot": 29, "bit": 25, "mask": 16},
{"i": 115, "op": "sub", "dst": 3, "src": 7, "src2": 1, "imm": "0xa1d1646e", "imm2": "0x6fa998ce", "rot": 15, "bit": 29, "mask": 2},
{"i": 116, "op": "mulhi", "dst": 0, "src": 1, "src2": 4, "imm": "0xd7921c15", "imm2": "0x8b2345a7", "rot": 10, "bit": 19, "mask": 4},
{"i": 117, "op": "rotl", "dst": 4, "src": 0, "src2": 4, "imm": "0xc1b1b0ab", "imm2": "0xd19b3f39", "rot": 12, "bit": 16, "mask": 1},
{"i": 118, "op": "add", "dst": 1, "src": 4, "src2": 5, "imm": "0x24494ad3", "imm2": "0xc5e98ee5", "rot": 22, "bit": 7, "mask": 16},
{"i": 119, "op": "add", "dst": 0, "src": 4, "src2": 6, "imm": "0x1b2d1c83", "imm2": "0xa97bc949", "rot": 8, "bit": 4, "mask": 16},
{"i": 120, "op": "shfl", "dst": 5, "src": 4, "src2": 7, "imm": "0xb93015ff", "imm2": "0xc22366cd", "rot": 23, "bit": 16, "mask": 4},
{"i": 121, "op": "shfl", "dst": 3, "src": 2, "src2": 5, "imm": "0xc0aaacdb", "imm2": "0xaaa7d229", "rot": 31, "bit": 29, "mask": 8},
{"i": 122, "op": "rotl", "dst": 7, "src": 1, "src2": 3, "imm": "0xcce6a73f", "imm2": "0x517b6b86", "rot": 3, "bit": 16, "mask": 8},
{"i": 123, "op": "rotr", "dst": 4, "src": 6, "src2": 0, "imm": "0x8e156aca", "imm2": "0x0a894b3e", "rot": 2, "bit": 12, "mask": 2},
{"i": 124, "op": "shfl", "dst": 6, "src": 5, "src2": 2, "imm": "0xd88c8446", "imm2": "0xf49fedf3", "rot": 3, "bit": 23, "mask": 1},
{"i": 125, "op": "rotl", "dst": 5, "src": 2, "src2": 0, "imm": "0xd10b27cf", "imm2": "0x2dde1faa", "rot": 21, "bit": 7, "mask": 2},
{"i": 126, "op": "mad", "dst": 0, "src": 3, "src2": 1, "imm": "0x619e1818", "imm2": "0x62add310", "rot": 26, "bit": 1, "mask": 4},
{"i": 127, "op": "add", "dst": 0, "src": 3, "src2": 6, "imm": "0xff14c08d", "imm2": "0xa7f6bb54", "rot": 25, "bit": 24, "mask": 4},
{"i": 128, "op": "xor", "dst": 7, "src": 4, "src2": 4, "imm": "0x34224086", "imm2": "0x5e9f858e", "rot": 4, "bit": 16, "mask": 8},
{"i": 129, "op": "mulhi", "dst": 3, "src": 5, "src2": 6, "imm": "0x89c3cbdd", "imm2": "0x4e80334c", "rot": 29, "bit": 4, "mask": 1},
{"i": 130, "op": "shfl", "dst": 5, "src": 7, "src2": 1, "imm": "0x37d4c3e2", "imm2": "0xbd54378c", "rot": 14, "bit": 26, "mask": 8},
{"i": 131, "op": "mulhi", "dst": 6, "src": 4, "src2": 3, "imm": "0x4f5fac7c", "imm2": "0x74070028", "rot": 5, "bit": 25, "mask": 8},
{"i": 132, "op": "xor", "dst": 5, "src": 3, "src2": 0, "imm": "0x690eb003", "imm2": "0x8516a581", "rot": 20, "bit": 21, "mask": 2},
{"i": 133, "op": "rotl", "dst": 0, "src": 5, "src2": 7, "imm": "0x42b31885", "imm2": "0x08249acb", "rot": 19, "bit": 6, "mask": 8},
{"i": 134, "op": "rotr", "dst": 4, "src": 3, "src2": 3, "imm": "0x07d729ed", "imm2": "0xf564da8a", "rot": 17, "bit": 9, "mask": 16},
{"i": 135, "op": "shfl", "dst": 1, "src": 2, "src2": 0, "imm": "0x19130ef2", "imm2": "0xf59815e5", "rot": 17, "bit": 12, "mask": 16},
{"i": 136, "op": "sub", "dst": 5, "src": 2, "src2": 5, "imm": "0xdeb56168", "imm2": "0x871104c4", "rot": 13, "bit": 17, "mask": 16},
{"i": 137, "op": "xor", "dst": 3, "src": 5, "src2": 4, "imm": "0x884fc7da", "imm2": "0x83a4a5bf", "rot": 23, "bit": 12, "mask": 4},
{"i": 138, "op": "sub", "dst": 0, "src": 2, "src2": 6, "imm": "0x3e67a6fd", "imm2": "0x844d2039", "rot": 3, "bit": 24, "mask": 4},
{"i": 139, "op": "mul", "dst": 3, "src": 7, "src2": 7, "imm": "0x965933b4", "imm2": "0xf37ef93d", "rot": 6, "bit": 9, "mask": 4},
{"i": 140, "op": "add", "dst": 5, "src": 3, "src2": 3, "imm": "0x82ab98f4", "imm2": "0x2d465ca8", "rot": 11, "bit": 24, "mask": 1},
{"i": 141, "op": "add", "dst": 4, "src": 1, "src2": 7, "imm": "0x80594390", "imm2": "0x237a9d8e", "rot": 14, "bit": 11, "mask": 8},
{"i": 142, "op": "mad", "dst": 3, "src": 7, "src2": 0, "imm": "0xd37861a1", "imm2": "0x2fe70eae", "rot": 2, "bit": 11, "mask": 16},
{"i": 143, "op": "or", "dst": 0, "src": 3, "src2": 5, "imm": "0x1a018e2c", "imm2": "0x301aa5f6", "rot": 15, "bit": 26, "mask": 1},
{"i": 144, "op": "mulhi", "dst": 0, "src": 1, "src2": 5, "imm": "0x69d22dfc", "imm2": "0x4a90cb1e", "rot": 21, "bit": 9, "mask": 16},
{"i": 145, "op": "xor", "dst": 6, "src": 2, "src2": 0, "imm": "0xf3f41f47", "imm2": "0xdf8d33e9", "rot": 22, "bit": 0, "mask": 8},
{"i": 146, "op": "shfl", "dst": 7, "src": 1, "src2": 1, "imm": "0xf8a52377", "imm2": "0x0613ef41", "rot": 24, "bit": 12, "mask": 16},
{"i": 147, "op": "add", "dst": 0, "src": 1, "src2": 3, "imm": "0x07f15148", "imm2": "0xe68cf57e", "rot": 2, "bit": 18, "mask": 4},
{"i": 148, "op": "or", "dst": 7, "src": 3, "src2": 0, "imm": "0xbfd39b49", "imm2": "0xc7f6e97c", "rot": 13, "bit": 27, "mask": 2},
{"i": 149, "op": "xor", "dst": 4, "src": 2, "src2": 7, "imm": "0x47409e43", "imm2": "0x04ef7db9", "rot": 8, "bit": 6, "mask": 4},
{"i": 150, "op": "xor", "dst": 7, "src": 1, "src2": 1, "imm": "0x5d42a156", "imm2": "0xc2f77c48", "rot": 27, "bit": 17, "mask": 4},
{"i": 151, "op": "rotr", "dst": 5, "src": 2, "src2": 7, "imm": "0x7c170030", "imm2": "0xa3102916", "rot": 5, "bit": 6, "mask": 1},
{"i": 152, "op": "mul", "dst": 0, "src": 7, "src2": 5, "imm": "0x16d009af", "imm2": "0x2a89533b", "rot": 26, "bit": 8, "mask": 4},
{"i": 153, "op": "rotl", "dst": 4, "src": 5, "src2": 0, "imm": "0x6e54eb71", "imm2": "0xe2d27256", "rot": 16, "bit": 18, "mask": 1},
{"i": 154, "op": "rotr", "dst": 6, "src": 4, "src2": 5, "imm": "0x128f24a4", "imm2": "0x59888463", "rot": 15, "bit": 17, "mask": 16},
{"i": 155, "op": "xor", "dst": 6, "src": 1, "src2": 2, "imm": "0x34f276ff", "imm2": "0xef5086b4", "rot": 2, "bit": 10, "mask": 4},
{"i": 156, "op": "or", "dst": 6, "src": 3, "src2": 4, "imm": "0x16cc2c2f", "imm2": "0xfae5a09b", "rot": 12, "bit": 31, "mask": 4},
{"i": 157, "op": "add", "dst": 1, "src": 6, "src2": 7, "imm": "0x14878c5a", "imm2": "0x84c2a09d", "rot": 30, "bit": 19, "mask": 8},
{"i": 158, "op": "sub", "dst": 4, "src": 1, "src2": 0, "imm": "0xfe18e4b0", "imm2": "0x239df0cc", "rot": 14, "bit": 20, "mask": 2},
{"i": 159, "op": "mad", "dst": 4, "src": 6, "src2": 7, "imm": "0xbdfcc4e0", "imm2": "0x0870dee8", "rot": 1, "bit": 7, "mask": 8},
{"i": 160, "op": "mul", "dst": 1, "src": 5, "src2": 1, "imm": "0xc837b43d", "imm2": "0x027ac950", "rot": 4, "bit": 22, "mask": 16},
{"i": 161, "op": "or", "dst": 4, "src": 0, "src2": 2, "imm": "0x9c28f8f6", "imm2": "0x3db71fe6", "rot": 11, "bit": 6, "mask": 16},
{"i": 162, "op": "rotl", "dst": 7, "src": 3, "src2": 6, "imm": "0xb6e56f55", "imm2": "0x5fcbd27c", "rot": 21, "bit": 10, "mask": 1},
{"i": 163, "op": "sub", "dst": 0, "src": 1, "src2": 4, "imm": "0x8d95ae70", "imm2": "0xd4f10284", "rot": 15, "bit": 12, "mask": 8},
{"i": 164, "op": "mul", "dst": 1, "src": 0, "src2": 6, "imm": "0xa9bdf99e", "imm2": "0x1f3dceb6", "rot": 21, "bit": 20, "mask": 16},
{"i": 165, "op": "sub", "dst": 2, "src": 1, "src2": 4, "imm": "0xda245058", "imm2": "0x2038e7f6", "rot": 30, "bit": 11, "mask": 2},
{"i": 166, "op": "shfl", "dst": 0, "src": 6, "src2": 3, "imm": "0xbbc8eee8", "imm2": "0xa73472fb", "rot": 23, "bit": 4, "mask": 2},
{"i": 167, "op": "sub", "dst": 0, "src": 4, "src2": 2, "imm": "0x43540d69", "imm2": "0xb3f116ca", "rot": 28, "bit": 2, "mask": 2},
{"i": 168, "op": "rotr", "dst": 1, "src": 6, "src2": 6, "imm": "0x57cea752", "imm2": "0xc1136e71", "rot": 25, "bit": 3, "mask": 8},
{"i": 169, "op": "rotr", "dst": 7, "src": 1, "src2": 5, "imm": "0x4550a465", "imm2": "0x14362935", "rot": 25, "bit": 9, "mask": 16},
{"i": 170, "op": "mad", "dst": 3, "src": 1, "src2": 3, "imm": "0x8c961d80", "imm2": "0x7de2e1db", "rot": 10, "bit": 6, "mask": 4},
{"i": 171, "op": "shfl", "dst": 2, "src": 0, "src2": 0, "imm": "0xda047fca", "imm2": "0x459e17ab", "rot": 22, "bit": 26, "mask": 4},
{"i": 172, "op": "sub", "dst": 2, "src": 1, "src2": 2, "imm": "0xbcc341fd", "imm2": "0x17a3b229", "rot": 8, "bit": 25, "mask": 8},
{"i": 173, "op": "xor", "dst": 7, "src": 6, "src2": 7, "imm": "0x2302b424", "imm2": "0x78780982", "rot": 23, "bit": 7, "mask": 8},
{"i": 174, "op": "rotr", "dst": 4, "src": 1, "src2": 2, "imm": "0xcad6fb5f", "imm2": "0x1807628e", "rot": 8, "bit": 21, "mask": 4},
{"i": 175, "op": "shfl", "dst": 4, "src": 7, "src2": 7, "imm": "0xf5057e8e", "imm2": "0xd14d6cc5", "rot": 3, "bit": 12, "mask": 2},
{"i": 176, "op": "mul", "dst": 6, "src": 2, "src2": 1, "imm": "0xc2926356", "imm2": "0xae74dc32", "rot": 1, "bit": 21, "mask": 8},
{"i": 177, "op": "shfl", "dst": 0, "src": 2, "src2": 7, "imm": "0x8d94d98e", "imm2": "0x7bd6f4dc", "rot": 27, "bit": 14, "mask": 4},
{"i": 178, "op": "add", "dst": 6, "src": 4, "src2": 6, "imm": "0x4fa43965", "imm2": "0x509871e6", "rot": 28, "bit": 21, "mask": 4},
{"i": 179, "op": "xor", "dst": 0, "src": 6, "src2": 6, "imm": "0xe278fe6c", "imm2": "0x75d8a63f", "rot": 21, "bit": 15, "mask": 2},
{"i": 180, "op": "add", "dst": 5, "src": 7, "src2": 7, "imm": "0xfb3c4bd8", "imm2": "0xb95b8a53", "rot": 22, "bit": 0, "mask": 4},
{"i": 181, "op": "mul", "dst": 6, "src": 3, "src2": 2, "imm": "0x5a1347ec", "imm2": "0x3ccc5389", "rot": 27, "bit": 26, "mask": 4},
{"i": 182, "op": "rotl", "dst": 7, "src": 4, "src2": 7, "imm": "0xdc6db2f7", "imm2": "0x7cdff0c6", "rot": 1, "bit": 2, "mask": 4},
{"i": 183, "op": "add", "dst": 0, "src": 7, "src2": 7, "imm": "0xc448a197", "imm2": "0x7047b7cf", "rot": 24, "bit": 11, "mask": 8},
{"i": 184, "op": "mul", "dst": 3, "src": 5, "src2": 0, "imm": "0xa5c0e492", "imm2": "0xaf7d8a86", "rot": 11, "bit": 16, "mask": 8},
{"i": 185, "op": "shfl", "dst": 5, "src": 7, "src2": 1, "imm": "0x5965794b", "imm2": "0x36ddca6b", "rot": 7, "bit": 25, "mask": 1},
{"i": 186, "op": "mul", "dst": 0, "src": 2, "src2": 5, "imm": "0xdfdbcc0f", "imm2": "0xac7b7091", "rot": 11, "bit": 31, "mask": 8},
{"i": 187, "op": "mulhi", "dst": 4, "src": 7, "src2": 5, "imm": "0x3d8999e9", "imm2": "0xf1848db8", "rot": 15, "bit": 21, "mask": 8},
{"i": 188, "op": "mad", "dst": 2, "src": 7, "src2": 2, "imm": "0xda3af48c", "imm2": "0x8e33a97c", "rot": 6, "bit": 30, "mask": 4},
{"i": 189, "op": "sub", "dst": 7, "src": 2, "src2": 4, "imm": "0xa32da8c1", "imm2": "0xf7486d06", "rot": 25, "bit": 16, "mask": 4},
{"i": 190, "op": "add", "dst": 2, "src": 5, "src2": 1, "imm": "0x2fceaf49", "imm2": "0x5caccc5d", "rot": 24, "bit": 19, "mask": 2},
{"i": 191, "op": "shfl", "dst": 1, "src": 2, "src2": 2, "imm": "0x2a71f5e6", "imm2": "0xb9b51e89", "rot": 31, "bit": 25, "mask": 1},
{"i": 192, "op": "add", "dst": 7, "src": 1, "src2": 7, "imm": "0xba0cee62", "imm2": "0x857bb5fe", "rot": 4, "bit": 20, "mask": 2},
{"i": 193, "op": "rotl", "dst": 6, "src": 3, "src2": 3, "imm": "0xc7fe35cf", "imm2": "0x515c1201", "rot": 22, "bit": 7, "mask": 16},
{"i": 194, "op": "xor", "dst": 3, "src": 7, "src2": 4, "imm": "0xe496d1f1", "imm2": "0x11046e3e", "rot": 16, "bit": 9, "mask": 4},
{"i": 195, "op": "mul", "dst": 7, "src": 0, "src2": 2, "imm": "0xc7d5c4c2", "imm2": "0x077e940b", "rot": 23, "bit": 29, "mask": 4},
{"i": 196, "op": "xor", "dst": 3, "src": 5, "src2": 3, "imm": "0xbe6db14a", "imm2": "0xf736da5a", "rot": 19, "bit": 6, "mask": 2},
{"i": 197, "op": "add", "dst": 5, "src": 1, "src2": 5, "imm": "0x8519428c", "imm2": "0xeae84577", "rot": 18, "bit": 29, "mask": 1},
{"i": 198, "op": "mad", "dst": 7, "src": 4, "src2": 4, "imm": "0xb272a029", "imm2": "0x071f6a5c", "rot": 5, "bit": 28, "mask": 8},
{"i": 199, "op": "add", "dst": 3, "src": 6, "src2": 3, "imm": "0x468639d3", "imm2": "0x0bfdbfa1", "rot": 20, "bit": 8, "mask": 16},
{"i": 200, "op": "mad", "dst": 5, "src": 3, "src2": 4, "imm": "0xffba18b7", "imm2": "0xbdcf9e81", "rot": 13, "bit": 31, "mask": 8},
{"i": 201, "op": "shfl", "dst": 2, "src": 7, "src2": 7, "imm": "0xb7533191", "imm2": "0x8d58cc8c", "rot": 7, "bit": 29, "mask": 4},
{"i": 202, "op": "add", "dst": 7, "src": 4, "src2": 6, "imm": "0x18ec9a69", "imm2": "0x53ee8e50", "rot": 12, "bit": 23, "mask": 16},
{"i": 203, "op": "xor", "dst": 6, "src": 0, "src2": 5, "imm": "0x12011ff1", "imm2": "0xfbb57ac6", "rot": 16, "bit": 25, "mask": 16},
{"i": 204, "op": "add", "dst": 4, "src": 5, "src2": 3, "imm": "0x3e81485b", "imm2": "0xac63376e", "rot": 1, "bit": 4, "mask": 1},
{"i": 205, "op": "mad", "dst": 7, "src": 1, "src2": 4, "imm": "0xeb9eee5c", "imm2": "0x3f1daecd", "rot": 19, "bit": 29, "mask": 4},
{"i": 206, "op": "shfl", "dst": 1, "src": 5, "src2": 2, "imm": "0x4fc50d06", "imm2": "0xb5533b31", "rot": 22, "bit": 27, "mask": 16},
{"i": 207, "op": "mul", "dst": 4, "src": 0, "src2": 5, "imm": "0x202d6001", "imm2": "0x50388f85", "rot": 5, "bit": 18, "mask": 16},
{"i": 208, "op": "or", "dst": 1, "src": 6, "src2": 7, "imm": "0x8743c0d4", "imm2": "0x9df69539", "rot": 14, "bit": 16, "mask": 1},
{"i": 209, "op": "add", "dst": 6, "src": 4, "src2": 6, "imm": "0x66ccb75d", "imm2": "0x5b745519", "rot": 28, "bit": 28, "mask": 8},
{"i": 210, "op": "rotr", "dst": 1, "src": 3, "src2": 1, "imm": "0xe9933132", "imm2": "0x6702fe85", "rot": 16, "bit": 19, "mask": 1},
{"i": 211, "op": "sub", "dst": 5, "src": 4, "src2": 4, "imm": "0xfe04b942", "imm2": "0x40dd2ce8", "rot": 24, "bit": 8, "mask": 4},
{"i": 212, "op": "xor", "dst": 4, "src": 7, "src2": 7, "imm": "0x10827878", "imm2": "0xef0de8fc", "rot": 17, "bit": 11, "mask": 8},
{"i": 213, "op": "add", "dst": 1, "src": 7, "src2": 1, "imm": "0x0ce0553d", "imm2": "0x1c3dccf7", "rot": 26, "bit": 8, "mask": 1},
{"i": 214, "op": "mulhi", "dst": 0, "src": 1, "src2": 1, "imm": "0xa71d7581", "imm2": "0xe567c74c", "rot": 2, "bit": 29, "mask": 2},
{"i": 215, "op": "add", "dst": 3, "src": 6, "src2": 2, "imm": "0x96bfec89", "imm2": "0xfadc9205", "rot": 30, "bit": 9, "mask": 16},
{"i": 216, "op": "rotl", "dst": 0, "src": 2, "src2": 5, "imm": "0x947ca474", "imm2": "0xd2a1b650", "rot": 4, "bit": 1, "mask": 1},
{"i": 217, "op": "xor", "dst": 6, "src": 4, "src2": 5, "imm": "0x0b7617de", "imm2": "0xc6c0a9a2", "rot": 31, "bit": 15, "mask": 2},
{"i": 218, "op": "shfl", "dst": 6, "src": 7, "src2": 1, "imm": "0x738f0a8f", "imm2": "0xfc868560", "rot": 2, "bit": 20, "mask": 2},
{"i": 219, "op": "mad", "dst": 7, "src": 0, "src2": 1, "imm": "0x2960f2bc", "imm2": "0x7e9ef9b7", "rot": 21, "bit": 4, "mask": 16},
{"i": 220, "op": "mul", "dst": 4, "src": 0, "src2": 2, "imm": "0x6014d800", "imm2": "0xd19ac7d1", "rot": 1, "bit": 13, "mask": 1},
{"i": 221, "op": "mad", "dst": 2, "src": 6, "src2": 0, "imm": "0x4b558fc2", "imm2": "0x2d48bd3c", "rot": 18, "bit": 31, "mask": 2},
{"i": 222, "op": "xor", "dst": 5, "src": 4, "src2": 6, "imm": "0x0260f3ab", "imm2": "0x8fce22f1", "rot": 21, "bit": 26, "mask": 16},
{"i": 223, "op": "mul", "dst": 0, "src": 5, "src2": 0, "imm": "0xe07ab58f", "imm2": "0x5349a41d", "rot": 20, "bit": 3, "mask": 1},
{"i": 224, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0x61495681", "imm2": "0x66b15c04", "rot": 24, "bit": 9, "mask": 16},
{"i": 225, "op": "rotr", "dst": 3, "src": 2, "src2": 5, "imm": "0x291268bd", "imm2": "0xf046aa79", "rot": 27, "bit": 15, "mask": 4},
{"i": 226, "op": "mad", "dst": 2, "src": 3, "src2": 3, "imm": "0xfd6dfa6c", "imm2": "0x2c0db93d", "rot": 29, "bit": 2, "mask": 16},
{"i": 227, "op": "xor", "dst": 6, "src": 0, "src2": 4, "imm": "0xd4ae1ee2", "imm2": "0xe6a67972", "rot": 26, "bit": 1, "mask": 4},
{"i": 228, "op": "rotl", "dst": 4, "src": 7, "src2": 3, "imm": "0xf6627a9d", "imm2": "0x99078da3", "rot": 30, "bit": 5, "mask": 16},
{"i": 229, "op": "add", "dst": 2, "src": 3, "src2": 7, "imm": "0x70d05c34", "imm2": "0x25bc17c2", "rot": 20, "bit": 29, "mask": 4},
{"i": 230, "op": "rotr", "dst": 1, "src": 5, "src2": 2, "imm": "0xef874bea", "imm2": "0x3bfbfecc", "rot": 17, "bit": 2, "mask": 2},
{"i": 231, "op": "add", "dst": 1, "src": 4, "src2": 5, "imm": "0x32a28384", "imm2": "0x2d8728f3", "rot": 1, "bit": 8, "mask": 8},
{"i": 232, "op": "rotl", "dst": 1, "src": 6, "src2": 3, "imm": "0x877c54ab", "imm2": "0x1d5e5014", "rot": 6, "bit": 24, "mask": 2},
{"i": 233, "op": "add", "dst": 2, "src": 0, "src2": 5, "imm": "0xcf0949f1", "imm2": "0x61e81fe6", "rot": 2, "bit": 21, "mask": 16},
{"i": 234, "op": "rotl", "dst": 4, "src": 5, "src2": 5, "imm": "0x5017c32c", "imm2": "0x1ab34dfe", "rot": 2, "bit": 1, "mask": 2},
{"i": 235, "op": "sub", "dst": 2, "src": 6, "src2": 2, "imm": "0xadbdb811", "imm2": "0x2c2d4f2b", "rot": 30, "bit": 29, "mask": 8},
{"i": 236, "op": "or", "dst": 6, "src": 3, "src2": 4, "imm": "0x700e204f", "imm2": "0x27294e7b", "rot": 13, "bit": 0, "mask": 4},
{"i": 237, "op": "shfl", "dst": 7, "src": 5, "src2": 4, "imm": "0xc39f71ba", "imm2": "0x9a90263d", "rot": 28, "bit": 9, "mask": 4},
{"i": 238, "op": "xor", "dst": 1, "src": 3, "src2": 6, "imm": "0x9f84a5b3", "imm2": "0x95691d15", "rot": 14, "bit": 22, "mask": 1},
{"i": 239, "op": "rotl", "dst": 2, "src": 4, "src2": 0, "imm": "0xa3b79ed5", "imm2": "0x05f568bc", "rot": 1, "bit": 15, "mask": 4},
{"i": 240, "op": "rotr", "dst": 5, "src": 2, "src2": 7, "imm": "0xaaabbb0d", "imm2": "0x71ce4cd6", "rot": 2, "bit": 26, "mask": 4},
{"i": 241, "op": "rotl", "dst": 4, "src": 1, "src2": 7, "imm": "0x8146fbd3", "imm2": "0xde65fc31", "rot": 10, "bit": 9, "mask": 4},
{"i": 242, "op": "add", "dst": 6, "src": 2, "src2": 7, "imm": "0xe204fb50", "imm2": "0x0a67565d", "rot": 5, "bit": 16, "mask": 1},
{"i": 243, "op": "shfl", "dst": 1, "src": 3, "src2": 7, "imm": "0xcb7a3c1b", "imm2": "0x863f002c", "rot": 18, "bit": 1, "mask": 2},
{"i": 244, "op": "shfl", "dst": 0, "src": 1, "src2": 3, "imm": "0x92eb030c", "imm2": "0x3cff4c6d", "rot": 1, "bit": 22, "mask": 16},
{"i": 245, "op": "shfl", "dst": 5, "src": 7, "src2": 6, "imm": "0x046c969c", "imm2": "0xd21d7e76", "rot": 5, "bit": 31, "mask": 2},
{"i": 246, "op": "xor", "dst": 4, "src": 5, "src2": 1, "imm": "0x2e3015f0", "imm2": "0x1b305a5c", "rot": 22, "bit": 16, "mask": 8},
{"i": 247, "op": "xor", "dst": 7, "src": 2, "src2": 0, "imm": "0x8238cf71", "imm2": "0xb7874d94", "rot": 9, "bit": 1, "mask": 2},
{"i": 248, "op": "shfl", "dst": 0, "src": 6, "src2": 7, "imm": "0x437cbc99", "imm2": "0x7fb41fed", "rot": 17, "bit": 1, "mask": 16},
{"i": 249, "op": "mulhi", "dst": 1, "src": 3, "src2": 2, "imm": "0xeb293d88", "imm2": "0xb92f5968", "rot": 3, "bit": 20, "mask": 2},
{"i": 250, "op": "add", "dst": 7, "src": 5, "src2": 3, "imm": "0x3d6daffd", "imm2": "0x5a79fd6f", "rot": 6, "bit": 31, "mask": 2},
{"i": 251, "op": "add", "dst": 6, "src": 0, "src2": 3, "imm": "0x84334aea", "imm2": "0x6beb28c2", "rot": 27, "bit": 28, "mask": 2},
{"i": 252, "op": "sub", "dst": 7, "src": 1, "src2": 6, "imm": "0xe6177638", "imm2": "0x814d3fc5", "rot": 25, "bit": 2, "mask": 2},
{"i": 253, "op": "rotr", "dst": 5, "src": 2, "src2": 7, "imm": "0x95560bac", "imm2": "0xbf8b01a9", "rot": 14, "bit": 5, "mask": 16},
{"i": 254, "op": "mulhi", "dst": 2, "src": 5, "src2": 1, "imm": "0x318956e5", "imm2": "0x7c20b373", "rot": 13, "bit": 30, "mask": 2},
{"i": 255, "op": "mul", "dst": 6, "src": 3, "src2": 3, "imm": "0xe1998e49", "imm2": "0x59353e5a", "rot": 15, "bit": 2, "mask": 4}
]},
"instructions": [
{"i": 0, "op": "sub", "dst": 6, "src": 3, "src2": 3, "imm": "0x77dfbe60", "imm2": "0x404c8b9c", "rot": 24, "bit": 8, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 1, "op": "or", "dst": 2, "src": 6, "src2": 7, "imm": "0xb2e79058", "imm2": "0xc2485073", "rot": 21, "bit": 23, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 2, "op": "add", "dst": 4, "src": 0, "src2": 6, "imm": "0x1a579b38", "imm2": "0x7731324b", "rot": 6, "bit": 4, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 3, "op": "load", "dst": 3, "src": 6, "src2": 0, "imm": "0x683f5bc5", "imm2": "0xc8a218fe", "rot": 25, "bit": 4, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 4, "op": "shfl", "dst": 0, "src": 6, "src2": 4, "imm": "0x4d7cdcbb", "imm2": "0x1a5bf1a4", "rot": 8, "bit": 28, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 5, "op": "xor", "dst": 4, "src": 1, "src2": 0, "imm": "0xa2b86827", "imm2": "0x94a44439", "rot": 21, "bit": 22, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 6, "op": "mad", "dst": 3, "src": 5, "src2": 3, "imm": "0x58a4ea3f", "imm2": "0x467879fa", "rot": 6, "bit": 31, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 7, "op": "mul", "dst": 1, "src": 6, "src2": 1, "imm": "0x31fcc19c", "imm2": "0x176cb88f", "rot": 1, "bit": 11, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 8, "op": "load", "dst": 2, "src": 0, "src2": 3, "imm": "0x89b12386", "imm2": "0x661ed5e5", "rot": 11, "bit": 13, "mask": 2, "width": 1, "win": 2, "off": 2},
{"i": 9, "op": "xor", "dst": 0, "src": 4, "src2": 1, "imm": "0x69150105", "imm2": "0x8e1f04b9", "rot": 3, "bit": 30, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 10, "op": "add", "dst": 0, "src": 7, "src2": 5, "imm": "0xee083919", "imm2": "0xb10fcef8", "rot": 9, "bit": 30, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 11, "op": "mulhi", "dst": 0, "src": 2, "src2": 3, "imm": "0x99ac7c83", "imm2": "0x34eb2845", "rot": 18, "bit": 12, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 12, "op": "xor", "dst": 5, "src": 4, "src2": 0, "imm": "0x97cfc887", "imm2": "0x0458f053", "rot": 28, "bit": 24, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 13, "op": "mad", "dst": 7, "src": 3, "src2": 0, "imm": "0x503e87b4", "imm2": "0x2c5d2617", "rot": 3, "bit": 15, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 14, "op": "load", "dst": 3, "src": 4, "src2": 4, "imm": "0xfae98035", "imm2": "0x6c127281", "rot": 19, "bit": 29, "mask": 4, "width": 1, "win": 1, "off": 0},
{"i": 15, "op": "load", "dst": 2, "src": 5, "src2": 2, "imm": "0x67601ed5", "imm2": "0x3c546ed1", "rot": 28, "bit": 28, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 16, "op": "shfl", "dst": 7, "src": 5, "src2": 6, "imm": "0x7789be79", "imm2": "0x87496b8e", "rot": 22, "bit": 2, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 17, "op": "mul", "dst": 7, "src": 6, "src2": 2, "imm": "0x559099bb", "imm2": "0x6a72e1a6", "rot": 1, "bit": 11, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 18, "op": "mad", "dst": 2, "src": 3, "src2": 1, "imm": "0x4f5bae5e", "imm2": "0x4c8c5762", "rot": 27, "bit": 31, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 19, "op": "rotr", "dst": 5, "src": 2, "src2": 4, "imm": "0x5dc5e6bf", "imm2": "0x36bc207d", "rot": 9, "bit": 4, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 20, "op": "load", "dst": 5, "src": 3, "src2": 7, "imm": "0x4a278885", "imm2": "0xcd1044b0", "rot": 30, "bit": 0, "mask": 4, "width": 1, "win": 1, "off": 1},
{"i": 21, "op": "shfl", "dst": 6, "src": 4, "src2": 3, "imm": "0x48b94ffc", "imm2": "0xd8e14d80", "rot": 2, "bit": 31, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 22, "op": "mulhi", "dst": 1, "src": 2, "src2": 7, "imm": "0x47bd8492", "imm2": "0x28fa8d0b", "rot": 19, "bit": 26, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 23, "op": "xor", "dst": 6, "src": 5, "src2": 1, "imm": "0x4ed6baf4", "imm2": "0xa8c31f74", "rot": 30, "bit": 2, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 24, "op": "mad", "dst": 5, "src": 2, "src2": 0, "imm": "0x6174747d", "imm2": "0xfc912524", "rot": 18, "bit": 29, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 25, "op": "mad", "dst": 6, "src": 3, "src2": 7, "imm": "0x113a6442", "imm2": "0xbe52ec57", "rot": 15, "bit": 15, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 26, "op": "load", "dst": 6, "src": 5, "src2": 1, "imm": "0x9d3eb1cc", "imm2": "0x375c73bb", "rot": 29, "bit": 7, "mask": 8, "width": 1, "win": 1, "off": 1},
{"i": 27, "op": "mad", "dst": 1, "src": 5, "src2": 5, "imm": "0x150088c3", "imm2": "0x7f17e789", "rot": 8, "bit": 25, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 28, "op": "load", "dst": 0, "src": 6, "src2": 3, "imm": "0x4b412223", "imm2": "0x9192ceeb", "rot": 16, "bit": 28, "mask": 1, "width": 1, "win": 1, "off": 1},
{"i": 29, "op": "add", "dst": 7, "src": 4, "src2": 6, "imm": "0xd5e6c37c", "imm2": "0x0b1f02c7", "rot": 2, "bit": 7, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 30, "op": "add", "dst": 7, "src": 0, "src2": 6, "imm": "0x4e45ba51", "imm2": "0x2d6e8bd1", "rot": 7, "bit": 0, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 31, "op": "xor", "dst": 0, "src": 2, "src2": 7, "imm": "0xef601d89", "imm2": "0x805402db", "rot": 7, "bit": 28, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 32, "op": "add", "dst": 6, "src": 2, "src2": 3, "imm": "0x1c91b2a1", "imm2": "0x351422d2", "rot": 1, "bit": 13, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 33, "op": "mulhi", "dst": 4, "src": 5, "src2": 7, "imm": "0x7cf21567", "imm2": "0x1075ee0d", "rot": 26, "bit": 17, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 34, "op": "rotr", "dst": 3, "src": 5, "src2": 6, "imm": "0x60d8f191", "imm2": "0x40523707", "rot": 3, "bit": 10, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 35, "op": "load", "dst": 3, "src": 0, "src2": 5, "imm": "0xb1dc3f6e", "imm2": "0x74440531", "rot": 21, "bit": 10, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 36, "op": "rotl", "dst": 4, "src": 6, "src2": 4, "imm": "0xf0d17569", "imm2": "0xd281fd01", "rot": 13, "bit": 4, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 37, "op": "add", "dst": 6, "src": 1, "src2": 6, "imm": "0x3f2970f7", "imm2": "0x64a28251", "rot": 4, "bit": 7, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 38, "op": "mul", "dst": 2, "src": 0, "src2": 3, "imm": "0x6463770c", "imm2": "0xb85d603f", "rot": 27, "bit": 1, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 39, "op": "add", "dst": 3, "src": 4, "src2": 3, "imm": "0x3b7b3317", "imm2": "0x7378c955", "rot": 28, "bit": 15, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 40, "op": "load", "dst": 0, "src": 7, "src2": 3, "imm": "0xd0fb5982", "imm2": "0x2e4d31a8", "rot": 25, "bit": 27, "mask": 4, "width": 1, "win": 2, "off": 3},
{"i": 41, "op": "xor", "dst": 6, "src": 5, "src2": 0, "imm": "0xe96a9e6e", "imm2": "0x8d73cc3e", "rot": 17, "bit": 11, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 42, "op": "add", "dst": 3, "src": 0, "src2": 6, "imm": "0x6678b059", "imm2": "0xb31f6a64", "rot": 11, "bit": 2, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 43, "op": "load", "dst": 7, "src": 3, "src2": 2, "imm": "0x65a841c5", "imm2": "0x6aae1403", "rot": 9, "bit": 9, "mask": 1, "width": 1, "win": 1, "off": 0},
{"i": 44, "op": "shfl", "dst": 3, "src": 7, "src2": 6, "imm": "0x650ba38d", "imm2": "0x07218508", "rot": 12, "bit": 13, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 45, "op": "mulhi", "dst": 1, "src": 5, "src2": 7, "imm": "0x18736788", "imm2": "0x9f820eed", "rot": 13, "bit": 29, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 46, "op": "rotl", "dst": 0, "src": 1, "src2": 5, "imm": "0x48deba75", "imm2": "0xefc508fa", "rot": 6, "bit": 6, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 47, "op": "load", "dst": 1, "src": 7, "src2": 4, "imm": "0x28a04384", "imm2": "0xc67cb0ac", "rot": 5, "bit": 5, "mask": 2, "width": 1, "win": 1, "off": 1},
{"i": 48, "op": "add", "dst": 4, "src": 0, "src2": 5, "imm": "0x43095946", "imm2": "0x5feccee6", "rot": 22, "bit": 17, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 49, "op": "load", "dst": 2, "src": 0, "src2": 2, "imm": "0x3e78cdd8", "imm2": "0x7c170311", "rot": 10, "bit": 5, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 50, "op": "sub", "dst": 2, "src": 3, "src2": 7, "imm": "0xaff0cdb2", "imm2": "0xde0b7ee0", "rot": 21, "bit": 11, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 51, "op": "add", "dst": 7, "src": 2, "src2": 1, "imm": "0xf45ecdf8", "imm2": "0x26e2b582", "rot": 28, "bit": 24, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 52, "op": "load", "dst": 5, "src": 7, "src2": 7, "imm": "0x67353e69", "imm2": "0xb2d56082", "rot": 27, "bit": 14, "mask": 2, "width": 1, "win": 2, "off": 3},
{"i": 53, "op": "load", "dst": 6, "src": 3, "src2": 1, "imm": "0x5a58c787", "imm2": "0x53a0467b", "rot": 6, "bit": 16, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 54, "op": "shfl", "dst": 7, "src": 5, "src2": 4, "imm": "0x3c237ad5", "imm2": "0xf2681187", "rot": 14, "bit": 26, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 55, "op": "rotr", "dst": 1, "src": 2, "src2": 3, "imm": "0x1c25c077", "imm2": "0x125de1ff", "rot": 13, "bit": 13, "mask": 2, "width": 1, "win": 0, "off": 0},
{"i": 56, "op": "shfl", "dst": 0, "src": 5, "src2": 0, "imm": "0x6465afe2", "imm2": "0x23b41d56", "rot": 31, "bit": 28, "mask": 16, "width": 1, "win": 0, "off": 0},
{"i": 57, "op": "rotl", "dst": 5, "src": 0, "src2": 2, "imm": "0xa427ff6e", "imm2": "0x014a0deb", "rot": 12, "bit": 28, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 58, "op": "add", "dst": 5, "src": 3, "src2": 7, "imm": "0x6b4f35e8", "imm2": "0x473b1718", "rot": 25, "bit": 4, "mask": 8, "width": 1, "win": 0, "off": 0},
{"i": 59, "op": "rotr", "dst": 4, "src": 1, "src2": 3, "imm": "0x66cc96ef", "imm2": "0xcb8c8e56", "rot": 7, "bit": 6, "mask": 4, "width": 1, "win": 0, "off": 0},
{"i": 60, "op": "shfl", "dst": 4, "src": 5, "src2": 5, "imm": "0x461bbf9f", "imm2": "0xc1ffd350", "rot": 19, "bit": 2, "mask": 1, "width": 1, "win": 0, "off": 0},
{"i": 61, "op": "load", "dst": 7, "src": 0, "src2": 1, "imm": "0x4d893571", "imm2": "0x5583e644", "rot": 19, "bit": 19, "mask": 8, "width": 1, "win": 1, "off": 1},
{"i": 62, "op": "load", "dst": 5, "src": 7, "src2": 3, "imm": "0x7a9049b4", "imm2": "0xbb7ebdf8", "rot": 15, "bit": 11, "mask": 8, "width": 1, "win": 1, "off": 1},
{"i": 63, "op": "mul", "dst": 4, "src": 1, "src2": 7, "imm": "0xe7ae8a83", "imm2": "0x1ded64e8", "rot": 21, "bit": 1, "mask": 8, "width": 1, "win": 0, "off": 0}
]
}

View file

@ -0,0 +1,368 @@
#include <metal_stdlib>
using namespace metal;
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0xbe8c5a0cu, 0x7646e626u, 0x508e29d0u, 0xfb8a5b4au, 0x53c50955u, 0x685d62fcu, 0x6065c013u, 0x881096ebu };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
{ uint x = nonce ^ SEEDW[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ SEEDW[1]; }
{ uint x = nonce ^ SEEDW[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ SEEDW[2]; }
{ uint x = nonce ^ SEEDW[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ SEEDW[3]; }
{ uint x = nonce ^ SEEDW[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ SEEDW[4]; }
{ uint x = nonce ^ SEEDW[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ SEEDW[5]; }
{ uint x = nonce ^ SEEDW[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ SEEDW[6]; }
{ uint x = nonce ^ SEEDW[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ SEEDW[7]; }
{ uint x = nonce ^ SEEDW[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ SEEDW[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r6 = r6 - r3; // 0
r2 = r2 | r6; // 1
r4 = r4 + r0 + select(0x1a579b38u, 0x7731324bu, ((sel >> 4u) & 1u) != 0u); // 2
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 3
r0 = r0 ^ simd_shuffle_xor(r6, (ushort)1); // 4
r4 = r4 ^ r1; // 5
r3 = r5 * r3 + r3; // 6
r1 = r1 * r6; // 7
r2 = r2 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 8
r0 = r0 ^ r4; // 9
r0 = r0 + r7 + select(0xee083919u, 0xb10fcef8u, ((sel >> 30u) & 1u) != 0u); // 10
r0 = mulhi(r0, r2); // 11
r5 = r5 ^ r4; // 12
r7 = r3 * r0 + r7; // 13
r3 = r3 ^ dataset[((rotl_imm(r4 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & MASK]; // 14
r2 = r2 ^ dataset[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 15
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)16); // 16
r7 = r7 * r6; // 17
r2 = r3 * r1 + r2; // 18
r5 = rotr_var(r5, r2); // 19
r5 = r5 ^ dataset[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 20
r6 = r6 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r1 = mulhi(r1, r2); // 22
r6 = r6 ^ r5; // 23
r5 = r2 * r0 + r5; // 24
r6 = r3 * r7 + r6; // 25
r6 = r6 ^ dataset[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 26
r1 = r5 * r5 + r1; // 27
r0 = r0 ^ dataset[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 28
r7 = r7 + r4 + select(0xd5e6c37cu, 0x0b1f02c7u, ((sel >> 7u) & 1u) != 0u); // 29
r7 = r7 + r0 + select(0x4e45ba51u, 0x2d6e8bd1u, ((sel >> 0u) & 1u) != 0u); // 30
r0 = r0 ^ r2; // 31
r6 = r6 + r2 + select(0x1c91b2a1u, 0x351422d2u, ((sel >> 13u) & 1u) != 0u); // 32
r4 = mulhi(r4, r5); // 33
r3 = rotr_var(r3, r5); // 34
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 35
r4 = rotl_imm(r4, 13u); // 36
r6 = r6 + r1 + select(0x3f2970f7u, 0x64a28251u, ((sel >> 7u) & 1u) != 0u); // 37
r2 = r2 * r0; // 38
r3 = r3 + r4 + select(0x3b7b3317u, 0x7378c955u, ((sel >> 15u) & 1u) != 0u); // 39
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & MASK]; // 40
r6 = r6 ^ r5; // 41
r3 = r3 + r0 + select(0x6678b059u, 0xb31f6a64u, ((sel >> 2u) & 1u) != 0u); // 42
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & MASK]; // 43
r3 = r3 ^ simd_shuffle_xor(r7, (ushort)4); // 44
r1 = mulhi(r1, r5); // 45
r0 = rotl_imm(r0, 6u); // 46
r1 = r1 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 47
r4 = r4 + r0 + select(0x43095946u, 0x5feccee6u, ((sel >> 17u) & 1u) != 0u); // 48
r2 = r2 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 49
r2 = r2 - r3; // 50
r7 = r7 + r2 + select(0xf45ecdf8u, 0x26e2b582u, ((sel >> 24u) & 1u) != 0u); // 51
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & MASK]; // 52
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 53
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)4); // 54
r1 = rotr_var(r1, r2); // 55
r0 = r0 ^ simd_shuffle_xor(r5, (ushort)16); // 56
r5 = rotl_imm(r5, 12u); // 57
r5 = r5 + r3 + select(0x6b4f35e8u, 0x473b1718u, ((sel >> 4u) & 1u) != 0u); // 58
r4 = rotr_var(r4, r1); // 59
r4 = r4 ^ simd_shuffle_xor(r5, (ushort)1); // 60
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 61
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 62
r4 = r4 * r1; // 63
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r6 = r6 | r0; // s0 or
r7 = r7 * r3; // s1 mul
r3 = r5 * r5 + r3; // s2 mad
r7 = r7 + r4 + select(0x97d3d105u, 0x38e58a06u, ((sel >> 6u) & 1u) != 0u); // s3 add
r6 = r6 + r0 + select(0x29b87b9au, 0x9629673du, ((sel >> 20u) & 1u) != 0u); // s4 add
r6 = r6 ^ simd_shuffle_xor(r2, (ushort)1); // s5 shfl
r5 = r3 * r5 + r5; // s6 mad
r3 = rotl_imm(r3, 5u); // s7 rotl
r0 = r0 + r7 + select(0xa7c1fb0fu, 0x4a5f55e1u, ((sel >> 12u) & 1u) != 0u); // s8 add
r5 = r5 * r7; // s9 mul
r4 = r4 ^ r5; // s10 xor
r6 = mulhi(r6, r4); // s11 mulhi
r5 = rotl_imm(r5, 13u); // s12 rotl
r0 = r2 * r1 + r0; // s13 mad
r2 = mulhi(r2, r4); // s14 mulhi
r3 = r3 | r1; // s15 or
r0 = r0 - r5; // s16 sub
r0 = r0 * r6; // s17 mul
r5 = r5 ^ simd_shuffle_xor(r1, (ushort)4); // s18 shfl
r3 = r3 | r4; // s19 or
r6 = r3 * r2 + r6; // s20 mad
r0 = rotl_imm(r0, 11u); // s21 rotl
r3 = rotl_imm(r3, 25u); // s22 rotl
r6 = r6 ^ r4; // s23 xor
r4 = r4 | r2; // s24 or
r1 = r1 + r6 + select(0x53e74799u, 0xfc2f6d17u, ((sel >> 7u) & 1u) != 0u); // s25 add
r7 = rotr_var(r7, r6); // s26 rotr
r7 = r7 + r5 + select(0xb8fae90eu, 0x787048dcu, ((sel >> 27u) & 1u) != 0u); // s27 add
r4 = r4 ^ r1; // s28 xor
r6 = r6 ^ r1; // s29 xor
r2 = mulhi(r2, r0); // s30 mulhi
r1 = rotr_var(r1, r4); // s31 rotr
r7 = r7 ^ r4; // s32 xor
r3 = r2 * r6 + r3; // s33 mad
r3 = r3 + r1 + select(0xd2dc42ebu, 0x9ffd510bu, ((sel >> 12u) & 1u) != 0u); // s34 add
r4 = r4 + r7 + select(0xad8eda6fu, 0xf871ba37u, ((sel >> 7u) & 1u) != 0u); // s35 add
r7 = r7 + r4 + select(0xb0cef8f4u, 0xd02d30cau, ((sel >> 3u) & 1u) != 0u); // s36 add
r4 = r3 * r2 + r4; // s37 mad
r5 = r7 * r7 + r5; // s38 mad
r3 = r3 + r6 + select(0x2bd506e2u, 0x82e98a22u, ((sel >> 26u) & 1u) != 0u); // s39 add
r0 = rotl_imm(r0, 21u); // s40 rotl
r1 = r1 | r0; // s41 or
r7 = r7 + r5 + select(0xc0386e49u, 0x6435f6d8u, ((sel >> 28u) & 1u) != 0u); // s42 add
r1 = mulhi(r1, r0); // s43 mulhi
r5 = r5 + r6 + select(0x3a8921a4u, 0x1f682c68u, ((sel >> 12u) & 1u) != 0u); // s44 add
r4 = r4 + r5 + select(0xeeca4334u, 0xf246e180u, ((sel >> 1u) & 1u) != 0u); // s45 add
r2 = r2 ^ r3; // s46 xor
r2 = r2 ^ r5; // s47 xor
r7 = r4 * r1 + r7; // s48 mad
r2 = r6 * r1 + r2; // s49 mad
r7 = r0 * r7 + r7; // s50 mad
r5 = r5 + r6 + select(0x745776d8u, 0x41bd68ccu, ((sel >> 26u) & 1u) != 0u); // s51 add
r3 = r3 ^ simd_shuffle_xor(r0, (ushort)1); // s52 shfl
r4 = r4 | r0; // s53 or
r0 = r2 * r4 + r0; // s54 mad
r5 = rotl_imm(r5, 9u); // s55 rotl
r5 = r5 * r7; // s56 mul
r7 = rotl_imm(r7, 27u); // s57 rotl
r7 = r7 - r6; // s58 sub
r2 = rotl_imm(r2, 22u); // s59 rotl
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)2); // s60 shfl
r4 = r4 + r0 + select(0x60d0ff55u, 0xcba6a161u, ((sel >> 7u) & 1u) != 0u); // s61 add
r1 = r1 * r5; // s62 mul
r7 = mulhi(r7, r6); // s63 mulhi
r5 = r5 * r0; // s64 mul
r2 = rotr_var(r2, r5); // s65 rotr
r0 = mulhi(r0, r3); // s66 mulhi
r0 = r0 | r7; // s67 or
r0 = rotl_imm(r0, 19u); // s68 rotl
r0 = rotl_imm(r0, 1u); // s69 rotl
r2 = r2 | r3; // s70 or
r3 = r7 * r5 + r3; // s71 mad
r7 = r0 * r4 + r7; // s72 mad
r4 = r4 | r3; // s73 or
r3 = r3 ^ r1; // s74 xor
r1 = r1 + r3 + select(0x3f4ffea2u, 0x8e35924eu, ((sel >> 15u) & 1u) != 0u); // s75 add
r1 = r1 * r3; // s76 mul
r0 = r3 * r2 + r0; // s77 mad
r2 = r2 ^ simd_shuffle_xor(r0, (ushort)16); // s78 shfl
r1 = mulhi(r1, r0); // s79 mulhi
r0 = mulhi(r0, r4); // s80 mulhi
r4 = r4 * r2; // s81 mul
r5 = r5 - r7; // s82 sub
r0 = r2 * r3 + r0; // s83 mad
r7 = r7 - r2; // s84 sub
r1 = r1 ^ r2; // s85 xor
r6 = r6 ^ simd_shuffle_xor(r3, (ushort)16); // s86 shfl
r3 = r0 * r0 + r3; // s87 mad
r0 = rotl_imm(r0, 20u); // s88 rotl
r1 = r1 - r5; // s89 sub
r6 = r6 ^ simd_shuffle_xor(r4, (ushort)16); // s90 shfl
r5 = r5 ^ r1; // s91 xor
r5 = rotl_imm(r5, 12u); // s92 rotl
r6 = r1 * r2 + r6; // s93 mad
r2 = rotr_var(r2, r5); // s94 rotr
r0 = r0 | r4; // s95 or
r7 = r7 * r3; // s96 mul
r5 = r5 | r0; // s97 or
r3 = r3 + r1 + select(0xbcfdd8a7u, 0x386bb642u, ((sel >> 13u) & 1u) != 0u); // s98 add
r0 = r0 + r6 + select(0xc921a021u, 0xa3962d03u, ((sel >> 9u) & 1u) != 0u); // s99 add
r1 = rotr_var(r1, r0); // s100 rotr
r2 = r2 + r4 + select(0x70da4067u, 0xc5990c5cu, ((sel >> 18u) & 1u) != 0u); // s101 add
r2 = rotl_imm(r2, 3u); // s102 rotl
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)4); // s103 shfl
r0 = r0 ^ r2; // s104 xor
r4 = r4 + r3 + select(0x1a5880cbu, 0xb15aec75u, ((sel >> 28u) & 1u) != 0u); // s105 add
r4 = r4 ^ simd_shuffle_xor(r0, (ushort)2); // s106 shfl
r7 = r7 ^ simd_shuffle_xor(r0, (ushort)4); // s107 shfl
r1 = r7 * r3 + r1; // s108 mad
r0 = r2 * r3 + r0; // s109 mad
r2 = r2 | r4; // s110 or
r6 = r6 ^ simd_shuffle_xor(r1, (ushort)1); // s111 shfl
r2 = r5 * r3 + r2; // s112 mad
r4 = mulhi(r4, r0); // s113 mulhi
r7 = rotl_imm(r7, 29u); // s114 rotl
r3 = r3 - r7; // s115 sub
r0 = mulhi(r0, r1); // s116 mulhi
r4 = rotl_imm(r4, 12u); // s117 rotl
r1 = r1 + r4 + select(0x24494ad3u, 0xc5e98ee5u, ((sel >> 7u) & 1u) != 0u); // s118 add
r0 = r0 + r4 + select(0x1b2d1c83u, 0xa97bc949u, ((sel >> 4u) & 1u) != 0u); // s119 add
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)4); // s120 shfl
r3 = r3 ^ simd_shuffle_xor(r2, (ushort)8); // s121 shfl
r7 = rotl_imm(r7, 3u); // s122 rotl
r4 = rotr_var(r4, r6); // s123 rotr
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)1); // s124 shfl
r5 = rotl_imm(r5, 21u); // s125 rotl
r0 = r3 * r1 + r0; // s126 mad
r0 = r0 + r3 + select(0xff14c08du, 0xa7f6bb54u, ((sel >> 24u) & 1u) != 0u); // s127 add
r7 = r7 ^ r4; // s128 xor
r3 = mulhi(r3, r5); // s129 mulhi
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)8); // s130 shfl
r6 = mulhi(r6, r4); // s131 mulhi
r5 = r5 ^ r3; // s132 xor
r0 = rotl_imm(r0, 19u); // s133 rotl
r4 = rotr_var(r4, r3); // s134 rotr
r1 = r1 ^ simd_shuffle_xor(r2, (ushort)16); // s135 shfl
r5 = r5 - r2; // s136 sub
r3 = r3 ^ r5; // s137 xor
r0 = r0 - r2; // s138 sub
r3 = r3 * r7; // s139 mul
r5 = r5 + r3 + select(0x82ab98f4u, 0x2d465ca8u, ((sel >> 24u) & 1u) != 0u); // s140 add
r4 = r4 + r1 + select(0x80594390u, 0x237a9d8eu, ((sel >> 11u) & 1u) != 0u); // s141 add
r3 = r7 * r0 + r3; // s142 mad
r0 = r0 | r3; // s143 or
r0 = mulhi(r0, r1); // s144 mulhi
r6 = r6 ^ r2; // s145 xor
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)16); // s146 shfl
r0 = r0 + r1 + select(0x07f15148u, 0xe68cf57eu, ((sel >> 18u) & 1u) != 0u); // s147 add
r7 = r7 | r3; // s148 or
r4 = r4 ^ r2; // s149 xor
r7 = r7 ^ r1; // s150 xor
r5 = rotr_var(r5, r2); // s151 rotr
r0 = r0 * r7; // s152 mul
r4 = rotl_imm(r4, 16u); // s153 rotl
r6 = rotr_var(r6, r4); // s154 rotr
r6 = r6 ^ r1; // s155 xor
r6 = r6 | r3; // s156 or
r1 = r1 + r6 + select(0x14878c5au, 0x84c2a09du, ((sel >> 19u) & 1u) != 0u); // s157 add
r4 = r4 - r1; // s158 sub
r4 = r6 * r7 + r4; // s159 mad
r1 = r1 * r5; // s160 mul
r4 = r4 | r0; // s161 or
r7 = rotl_imm(r7, 21u); // s162 rotl
r0 = r0 - r1; // s163 sub
r1 = r1 * r0; // s164 mul
r2 = r2 - r1; // s165 sub
r0 = r0 ^ simd_shuffle_xor(r6, (ushort)2); // s166 shfl
r0 = r0 - r4; // s167 sub
r1 = rotr_var(r1, r6); // s168 rotr
r7 = rotr_var(r7, r1); // s169 rotr
r3 = r1 * r3 + r3; // s170 mad
r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // s171 shfl
r2 = r2 - r1; // s172 sub
r7 = r7 ^ r6; // s173 xor
r4 = rotr_var(r4, r1); // s174 rotr
r4 = r4 ^ simd_shuffle_xor(r7, (ushort)2); // s175 shfl
r6 = r6 * r2; // s176 mul
r0 = r0 ^ simd_shuffle_xor(r2, (ushort)4); // s177 shfl
r6 = r6 + r4 + select(0x4fa43965u, 0x509871e6u, ((sel >> 21u) & 1u) != 0u); // s178 add
r0 = r0 ^ r6; // s179 xor
r5 = r5 + r7 + select(0xfb3c4bd8u, 0xb95b8a53u, ((sel >> 0u) & 1u) != 0u); // s180 add
r6 = r6 * r3; // s181 mul
r7 = rotl_imm(r7, 1u); // s182 rotl
r0 = r0 + r7 + select(0xc448a197u, 0x7047b7cfu, ((sel >> 11u) & 1u) != 0u); // s183 add
r3 = r3 * r5; // s184 mul
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)1); // s185 shfl
r0 = r0 * r2; // s186 mul
r4 = mulhi(r4, r7); // s187 mulhi
r2 = r7 * r2 + r2; // s188 mad
r7 = r7 - r2; // s189 sub
r2 = r2 + r5 + select(0x2fceaf49u, 0x5caccc5du, ((sel >> 19u) & 1u) != 0u); // s190 add
r1 = r1 ^ simd_shuffle_xor(r2, (ushort)1); // s191 shfl
r7 = r7 + r1 + select(0xba0cee62u, 0x857bb5feu, ((sel >> 20u) & 1u) != 0u); // s192 add
r6 = rotl_imm(r6, 22u); // s193 rotl
r3 = r3 ^ r7; // s194 xor
r7 = r7 * r0; // s195 mul
r3 = r3 ^ r5; // s196 xor
r5 = r5 + r1 + select(0x8519428cu, 0xeae84577u, ((sel >> 29u) & 1u) != 0u); // s197 add
r7 = r4 * r4 + r7; // s198 mad
r3 = r3 + r6 + select(0x468639d3u, 0x0bfdbfa1u, ((sel >> 8u) & 1u) != 0u); // s199 add
r5 = r3 * r4 + r5; // s200 mad
r2 = r2 ^ simd_shuffle_xor(r7, (ushort)4); // s201 shfl
r7 = r7 + r4 + select(0x18ec9a69u, 0x53ee8e50u, ((sel >> 23u) & 1u) != 0u); // s202 add
r6 = r6 ^ r0; // s203 xor
r4 = r4 + r5 + select(0x3e81485bu, 0xac63376eu, ((sel >> 4u) & 1u) != 0u); // s204 add
r7 = r1 * r4 + r7; // s205 mad
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)16); // s206 shfl
r4 = r4 * r0; // s207 mul
r1 = r1 | r6; // s208 or
r6 = r6 + r4 + select(0x66ccb75du, 0x5b745519u, ((sel >> 28u) & 1u) != 0u); // s209 add
r1 = rotr_var(r1, r3); // s210 rotr
r5 = r5 - r4; // s211 sub
r4 = r4 ^ r7; // s212 xor
r1 = r1 + r7 + select(0x0ce0553du, 0x1c3dccf7u, ((sel >> 8u) & 1u) != 0u); // s213 add
r0 = mulhi(r0, r1); // s214 mulhi
r3 = r3 + r6 + select(0x96bfec89u, 0xfadc9205u, ((sel >> 9u) & 1u) != 0u); // s215 add
r0 = rotl_imm(r0, 4u); // s216 rotl
r6 = r6 ^ r4; // s217 xor
r6 = r6 ^ simd_shuffle_xor(r7, (ushort)2); // s218 shfl
r7 = r0 * r1 + r7; // s219 mad
r4 = r4 * r0; // s220 mul
r2 = r6 * r0 + r2; // s221 mad
r5 = r5 ^ r4; // s222 xor
r0 = r0 * r5; // s223 mul
r2 = r2 + r0 + select(0x61495681u, 0x66b15c04u, ((sel >> 9u) & 1u) != 0u); // s224 add
r3 = rotr_var(r3, r2); // s225 rotr
r2 = r3 * r3 + r2; // s226 mad
r6 = r6 ^ r0; // s227 xor
r4 = rotl_imm(r4, 30u); // s228 rotl
r2 = r2 + r3 + select(0x70d05c34u, 0x25bc17c2u, ((sel >> 29u) & 1u) != 0u); // s229 add
r1 = rotr_var(r1, r5); // s230 rotr
r1 = r1 + r4 + select(0x32a28384u, 0x2d8728f3u, ((sel >> 8u) & 1u) != 0u); // s231 add
r1 = rotl_imm(r1, 6u); // s232 rotl
r2 = r2 + r0 + select(0xcf0949f1u, 0x61e81fe6u, ((sel >> 21u) & 1u) != 0u); // s233 add
r4 = rotl_imm(r4, 2u); // s234 rotl
r2 = r2 - r6; // s235 sub
r6 = r6 | r3; // s236 or
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)4); // s237 shfl
r1 = r1 ^ r3; // s238 xor
r2 = rotl_imm(r2, 1u); // s239 rotl
r5 = rotr_var(r5, r2); // s240 rotr
r4 = rotl_imm(r4, 10u); // s241 rotl
r6 = r6 + r2 + select(0xe204fb50u, 0x0a67565du, ((sel >> 16u) & 1u) != 0u); // s242 add
r1 = r1 ^ simd_shuffle_xor(r3, (ushort)2); // s243 shfl
r0 = r0 ^ simd_shuffle_xor(r1, (ushort)16); // s244 shfl
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)2); // s245 shfl
r4 = r4 ^ r5; // s246 xor
r7 = r7 ^ r2; // s247 xor
r0 = r0 ^ simd_shuffle_xor(r6, (ushort)16); // s248 shfl
r1 = mulhi(r1, r3); // s249 mulhi
r7 = r7 + r5 + select(0x3d6daffdu, 0x5a79fd6fu, ((sel >> 31u) & 1u) != 0u); // s250 add
r6 = r6 + r0 + select(0x84334aeau, 0x6beb28c2u, ((sel >> 28u) & 1u) != 0u); // s251 add
r7 = r7 - r1; // s252 sub
r5 = rotr_var(r5, r2); // s253 rotr
r2 = mulhi(r2, r5); // s254 mulhi
r6 = r6 * r3; // s255 mul
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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@ -0,0 +1,370 @@
#include <metal_stdlib>
using namespace metal;
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0xbe8c5a0cu, 0x7646e626u, 0x508e29d0u, 0xfb8a5b4au, 0x53c50955u, 0x685d62fcu, 0x6065c013u, 0x881096ebu };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Header-bound variant: the init words come from buffer 3 (bind.rs), not from SEEDW.
kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
constant uint* initw [[buffer(3)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
{ uint x = nonce ^ initw[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ initw[1]; }
{ uint x = nonce ^ initw[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ initw[2]; }
{ uint x = nonce ^ initw[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ initw[3]; }
{ uint x = nonce ^ initw[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ initw[4]; }
{ uint x = nonce ^ initw[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ initw[5]; }
{ uint x = nonce ^ initw[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ initw[6]; }
{ uint x = nonce ^ initw[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ initw[7]; }
{ uint x = nonce ^ initw[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ initw[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r6 = r6 - r3; // 0
r2 = r2 | r6; // 1
r4 = r4 + r0 + select(0x1a579b38u, 0x7731324bu, ((sel >> 4u) & 1u) != 0u); // 2
r3 = r3 ^ dataset[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 3
r0 = r0 ^ simd_shuffle_xor(r6, (ushort)1); // 4
r4 = r4 ^ r1; // 5
r3 = r5 * r3 + r3; // 6
r1 = r1 * r6; // 7
r2 = r2 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x08000000u) & MASK]; // 8
r0 = r0 ^ r4; // 9
r0 = r0 + r7 + select(0xee083919u, 0xb10fcef8u, ((sel >> 30u) & 1u) != 0u); // 10
r0 = mulhi(r0, r2); // 11
r5 = r5 ^ r4; // 12
r7 = r3 * r0 + r7; // 13
r3 = r3 ^ dataset[((rotl_imm(r4 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & MASK]; // 14
r2 = r2 ^ dataset[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 15
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)16); // 16
r7 = r7 * r6; // 17
r2 = r3 * r1 + r2; // 18
r5 = rotr_var(r5, r2); // 19
r5 = r5 ^ dataset[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 20
r6 = r6 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r1 = mulhi(r1, r2); // 22
r6 = r6 ^ r5; // 23
r5 = r2 * r0 + r5; // 24
r6 = r3 * r7 + r6; // 25
r6 = r6 ^ dataset[((rotl_imm(r5 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 26
r1 = r5 * r5 + r1; // 27
r0 = r0 ^ dataset[((rotl_imm(r6 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 28
r7 = r7 + r4 + select(0xd5e6c37cu, 0x0b1f02c7u, ((sel >> 7u) & 1u) != 0u); // 29
r7 = r7 + r0 + select(0x4e45ba51u, 0x2d6e8bd1u, ((sel >> 0u) & 1u) != 0u); // 30
r0 = r0 ^ r2; // 31
r6 = r6 + r2 + select(0x1c91b2a1u, 0x351422d2u, ((sel >> 13u) & 1u) != 0u); // 32
r4 = mulhi(r4, r5); // 33
r3 = rotr_var(r3, r5); // 34
r3 = r3 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 35
r4 = rotl_imm(r4, 13u); // 36
r6 = r6 + r1 + select(0x3f2970f7u, 0x64a28251u, ((sel >> 7u) & 1u) != 0u); // 37
r2 = r2 * r0; // 38
r3 = r3 + r4 + select(0x3b7b3317u, 0x7378c955u, ((sel >> 15u) & 1u) != 0u); // 39
r0 = r0 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & MASK]; // 40
r6 = r6 ^ r5; // 41
r3 = r3 + r0 + select(0x6678b059u, 0xb31f6a64u, ((sel >> 2u) & 1u) != 0u); // 42
r7 = r7 ^ dataset[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x00000000u) & MASK]; // 43
r3 = r3 ^ simd_shuffle_xor(r7, (ushort)4); // 44
r1 = mulhi(r1, r5); // 45
r0 = rotl_imm(r0, 6u); // 46
r1 = r1 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 47
r4 = r4 + r0 + select(0x43095946u, 0x5feccee6u, ((sel >> 17u) & 1u) != 0u); // 48
r2 = r2 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 49
r2 = r2 - r3; // 50
r7 = r7 + r2 + select(0xf45ecdf8u, 0x26e2b582u, ((sel >> 24u) & 1u) != 0u); // 51
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x03ffffffu) | 0x0c000000u) & MASK]; // 52
r6 = r6 ^ dataset[((rotl_imm(r3 * 0x2cb18b35u, 9u) & 0x0fffffffu) | 0x00000000u) & MASK]; // 53
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)4); // 54
r1 = rotr_var(r1, r2); // 55
r0 = r0 ^ simd_shuffle_xor(r5, (ushort)16); // 56
r5 = rotl_imm(r5, 12u); // 57
r5 = r5 + r3 + select(0x6b4f35e8u, 0x473b1718u, ((sel >> 4u) & 1u) != 0u); // 58
r4 = rotr_var(r4, r1); // 59
r4 = r4 ^ simd_shuffle_xor(r5, (ushort)1); // 60
r7 = r7 ^ dataset[((rotl_imm(r0 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 61
r5 = r5 ^ dataset[((rotl_imm(r7 * 0x2cb18b35u, 9u) & 0x07ffffffu) | 0x08000000u) & MASK]; // 62
r4 = r4 * r1; // 63
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r6 = r6 | r0; // s0 or
r7 = r7 * r3; // s1 mul
r3 = r5 * r5 + r3; // s2 mad
r7 = r7 + r4 + select(0x97d3d105u, 0x38e58a06u, ((sel >> 6u) & 1u) != 0u); // s3 add
r6 = r6 + r0 + select(0x29b87b9au, 0x9629673du, ((sel >> 20u) & 1u) != 0u); // s4 add
r6 = r6 ^ simd_shuffle_xor(r2, (ushort)1); // s5 shfl
r5 = r3 * r5 + r5; // s6 mad
r3 = rotl_imm(r3, 5u); // s7 rotl
r0 = r0 + r7 + select(0xa7c1fb0fu, 0x4a5f55e1u, ((sel >> 12u) & 1u) != 0u); // s8 add
r5 = r5 * r7; // s9 mul
r4 = r4 ^ r5; // s10 xor
r6 = mulhi(r6, r4); // s11 mulhi
r5 = rotl_imm(r5, 13u); // s12 rotl
r0 = r2 * r1 + r0; // s13 mad
r2 = mulhi(r2, r4); // s14 mulhi
r3 = r3 | r1; // s15 or
r0 = r0 - r5; // s16 sub
r0 = r0 * r6; // s17 mul
r5 = r5 ^ simd_shuffle_xor(r1, (ushort)4); // s18 shfl
r3 = r3 | r4; // s19 or
r6 = r3 * r2 + r6; // s20 mad
r0 = rotl_imm(r0, 11u); // s21 rotl
r3 = rotl_imm(r3, 25u); // s22 rotl
r6 = r6 ^ r4; // s23 xor
r4 = r4 | r2; // s24 or
r1 = r1 + r6 + select(0x53e74799u, 0xfc2f6d17u, ((sel >> 7u) & 1u) != 0u); // s25 add
r7 = rotr_var(r7, r6); // s26 rotr
r7 = r7 + r5 + select(0xb8fae90eu, 0x787048dcu, ((sel >> 27u) & 1u) != 0u); // s27 add
r4 = r4 ^ r1; // s28 xor
r6 = r6 ^ r1; // s29 xor
r2 = mulhi(r2, r0); // s30 mulhi
r1 = rotr_var(r1, r4); // s31 rotr
r7 = r7 ^ r4; // s32 xor
r3 = r2 * r6 + r3; // s33 mad
r3 = r3 + r1 + select(0xd2dc42ebu, 0x9ffd510bu, ((sel >> 12u) & 1u) != 0u); // s34 add
r4 = r4 + r7 + select(0xad8eda6fu, 0xf871ba37u, ((sel >> 7u) & 1u) != 0u); // s35 add
r7 = r7 + r4 + select(0xb0cef8f4u, 0xd02d30cau, ((sel >> 3u) & 1u) != 0u); // s36 add
r4 = r3 * r2 + r4; // s37 mad
r5 = r7 * r7 + r5; // s38 mad
r3 = r3 + r6 + select(0x2bd506e2u, 0x82e98a22u, ((sel >> 26u) & 1u) != 0u); // s39 add
r0 = rotl_imm(r0, 21u); // s40 rotl
r1 = r1 | r0; // s41 or
r7 = r7 + r5 + select(0xc0386e49u, 0x6435f6d8u, ((sel >> 28u) & 1u) != 0u); // s42 add
r1 = mulhi(r1, r0); // s43 mulhi
r5 = r5 + r6 + select(0x3a8921a4u, 0x1f682c68u, ((sel >> 12u) & 1u) != 0u); // s44 add
r4 = r4 + r5 + select(0xeeca4334u, 0xf246e180u, ((sel >> 1u) & 1u) != 0u); // s45 add
r2 = r2 ^ r3; // s46 xor
r2 = r2 ^ r5; // s47 xor
r7 = r4 * r1 + r7; // s48 mad
r2 = r6 * r1 + r2; // s49 mad
r7 = r0 * r7 + r7; // s50 mad
r5 = r5 + r6 + select(0x745776d8u, 0x41bd68ccu, ((sel >> 26u) & 1u) != 0u); // s51 add
r3 = r3 ^ simd_shuffle_xor(r0, (ushort)1); // s52 shfl
r4 = r4 | r0; // s53 or
r0 = r2 * r4 + r0; // s54 mad
r5 = rotl_imm(r5, 9u); // s55 rotl
r5 = r5 * r7; // s56 mul
r7 = rotl_imm(r7, 27u); // s57 rotl
r7 = r7 - r6; // s58 sub
r2 = rotl_imm(r2, 22u); // s59 rotl
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)2); // s60 shfl
r4 = r4 + r0 + select(0x60d0ff55u, 0xcba6a161u, ((sel >> 7u) & 1u) != 0u); // s61 add
r1 = r1 * r5; // s62 mul
r7 = mulhi(r7, r6); // s63 mulhi
r5 = r5 * r0; // s64 mul
r2 = rotr_var(r2, r5); // s65 rotr
r0 = mulhi(r0, r3); // s66 mulhi
r0 = r0 | r7; // s67 or
r0 = rotl_imm(r0, 19u); // s68 rotl
r0 = rotl_imm(r0, 1u); // s69 rotl
r2 = r2 | r3; // s70 or
r3 = r7 * r5 + r3; // s71 mad
r7 = r0 * r4 + r7; // s72 mad
r4 = r4 | r3; // s73 or
r3 = r3 ^ r1; // s74 xor
r1 = r1 + r3 + select(0x3f4ffea2u, 0x8e35924eu, ((sel >> 15u) & 1u) != 0u); // s75 add
r1 = r1 * r3; // s76 mul
r0 = r3 * r2 + r0; // s77 mad
r2 = r2 ^ simd_shuffle_xor(r0, (ushort)16); // s78 shfl
r1 = mulhi(r1, r0); // s79 mulhi
r0 = mulhi(r0, r4); // s80 mulhi
r4 = r4 * r2; // s81 mul
r5 = r5 - r7; // s82 sub
r0 = r2 * r3 + r0; // s83 mad
r7 = r7 - r2; // s84 sub
r1 = r1 ^ r2; // s85 xor
r6 = r6 ^ simd_shuffle_xor(r3, (ushort)16); // s86 shfl
r3 = r0 * r0 + r3; // s87 mad
r0 = rotl_imm(r0, 20u); // s88 rotl
r1 = r1 - r5; // s89 sub
r6 = r6 ^ simd_shuffle_xor(r4, (ushort)16); // s90 shfl
r5 = r5 ^ r1; // s91 xor
r5 = rotl_imm(r5, 12u); // s92 rotl
r6 = r1 * r2 + r6; // s93 mad
r2 = rotr_var(r2, r5); // s94 rotr
r0 = r0 | r4; // s95 or
r7 = r7 * r3; // s96 mul
r5 = r5 | r0; // s97 or
r3 = r3 + r1 + select(0xbcfdd8a7u, 0x386bb642u, ((sel >> 13u) & 1u) != 0u); // s98 add
r0 = r0 + r6 + select(0xc921a021u, 0xa3962d03u, ((sel >> 9u) & 1u) != 0u); // s99 add
r1 = rotr_var(r1, r0); // s100 rotr
r2 = r2 + r4 + select(0x70da4067u, 0xc5990c5cu, ((sel >> 18u) & 1u) != 0u); // s101 add
r2 = rotl_imm(r2, 3u); // s102 rotl
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)4); // s103 shfl
r0 = r0 ^ r2; // s104 xor
r4 = r4 + r3 + select(0x1a5880cbu, 0xb15aec75u, ((sel >> 28u) & 1u) != 0u); // s105 add
r4 = r4 ^ simd_shuffle_xor(r0, (ushort)2); // s106 shfl
r7 = r7 ^ simd_shuffle_xor(r0, (ushort)4); // s107 shfl
r1 = r7 * r3 + r1; // s108 mad
r0 = r2 * r3 + r0; // s109 mad
r2 = r2 | r4; // s110 or
r6 = r6 ^ simd_shuffle_xor(r1, (ushort)1); // s111 shfl
r2 = r5 * r3 + r2; // s112 mad
r4 = mulhi(r4, r0); // s113 mulhi
r7 = rotl_imm(r7, 29u); // s114 rotl
r3 = r3 - r7; // s115 sub
r0 = mulhi(r0, r1); // s116 mulhi
r4 = rotl_imm(r4, 12u); // s117 rotl
r1 = r1 + r4 + select(0x24494ad3u, 0xc5e98ee5u, ((sel >> 7u) & 1u) != 0u); // s118 add
r0 = r0 + r4 + select(0x1b2d1c83u, 0xa97bc949u, ((sel >> 4u) & 1u) != 0u); // s119 add
r5 = r5 ^ simd_shuffle_xor(r4, (ushort)4); // s120 shfl
r3 = r3 ^ simd_shuffle_xor(r2, (ushort)8); // s121 shfl
r7 = rotl_imm(r7, 3u); // s122 rotl
r4 = rotr_var(r4, r6); // s123 rotr
r6 = r6 ^ simd_shuffle_xor(r5, (ushort)1); // s124 shfl
r5 = rotl_imm(r5, 21u); // s125 rotl
r0 = r3 * r1 + r0; // s126 mad
r0 = r0 + r3 + select(0xff14c08du, 0xa7f6bb54u, ((sel >> 24u) & 1u) != 0u); // s127 add
r7 = r7 ^ r4; // s128 xor
r3 = mulhi(r3, r5); // s129 mulhi
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)8); // s130 shfl
r6 = mulhi(r6, r4); // s131 mulhi
r5 = r5 ^ r3; // s132 xor
r0 = rotl_imm(r0, 19u); // s133 rotl
r4 = rotr_var(r4, r3); // s134 rotr
r1 = r1 ^ simd_shuffle_xor(r2, (ushort)16); // s135 shfl
r5 = r5 - r2; // s136 sub
r3 = r3 ^ r5; // s137 xor
r0 = r0 - r2; // s138 sub
r3 = r3 * r7; // s139 mul
r5 = r5 + r3 + select(0x82ab98f4u, 0x2d465ca8u, ((sel >> 24u) & 1u) != 0u); // s140 add
r4 = r4 + r1 + select(0x80594390u, 0x237a9d8eu, ((sel >> 11u) & 1u) != 0u); // s141 add
r3 = r7 * r0 + r3; // s142 mad
r0 = r0 | r3; // s143 or
r0 = mulhi(r0, r1); // s144 mulhi
r6 = r6 ^ r2; // s145 xor
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)16); // s146 shfl
r0 = r0 + r1 + select(0x07f15148u, 0xe68cf57eu, ((sel >> 18u) & 1u) != 0u); // s147 add
r7 = r7 | r3; // s148 or
r4 = r4 ^ r2; // s149 xor
r7 = r7 ^ r1; // s150 xor
r5 = rotr_var(r5, r2); // s151 rotr
r0 = r0 * r7; // s152 mul
r4 = rotl_imm(r4, 16u); // s153 rotl
r6 = rotr_var(r6, r4); // s154 rotr
r6 = r6 ^ r1; // s155 xor
r6 = r6 | r3; // s156 or
r1 = r1 + r6 + select(0x14878c5au, 0x84c2a09du, ((sel >> 19u) & 1u) != 0u); // s157 add
r4 = r4 - r1; // s158 sub
r4 = r6 * r7 + r4; // s159 mad
r1 = r1 * r5; // s160 mul
r4 = r4 | r0; // s161 or
r7 = rotl_imm(r7, 21u); // s162 rotl
r0 = r0 - r1; // s163 sub
r1 = r1 * r0; // s164 mul
r2 = r2 - r1; // s165 sub
r0 = r0 ^ simd_shuffle_xor(r6, (ushort)2); // s166 shfl
r0 = r0 - r4; // s167 sub
r1 = rotr_var(r1, r6); // s168 rotr
r7 = rotr_var(r7, r1); // s169 rotr
r3 = r1 * r3 + r3; // s170 mad
r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // s171 shfl
r2 = r2 - r1; // s172 sub
r7 = r7 ^ r6; // s173 xor
r4 = rotr_var(r4, r1); // s174 rotr
r4 = r4 ^ simd_shuffle_xor(r7, (ushort)2); // s175 shfl
r6 = r6 * r2; // s176 mul
r0 = r0 ^ simd_shuffle_xor(r2, (ushort)4); // s177 shfl
r6 = r6 + r4 + select(0x4fa43965u, 0x509871e6u, ((sel >> 21u) & 1u) != 0u); // s178 add
r0 = r0 ^ r6; // s179 xor
r5 = r5 + r7 + select(0xfb3c4bd8u, 0xb95b8a53u, ((sel >> 0u) & 1u) != 0u); // s180 add
r6 = r6 * r3; // s181 mul
r7 = rotl_imm(r7, 1u); // s182 rotl
r0 = r0 + r7 + select(0xc448a197u, 0x7047b7cfu, ((sel >> 11u) & 1u) != 0u); // s183 add
r3 = r3 * r5; // s184 mul
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)1); // s185 shfl
r0 = r0 * r2; // s186 mul
r4 = mulhi(r4, r7); // s187 mulhi
r2 = r7 * r2 + r2; // s188 mad
r7 = r7 - r2; // s189 sub
r2 = r2 + r5 + select(0x2fceaf49u, 0x5caccc5du, ((sel >> 19u) & 1u) != 0u); // s190 add
r1 = r1 ^ simd_shuffle_xor(r2, (ushort)1); // s191 shfl
r7 = r7 + r1 + select(0xba0cee62u, 0x857bb5feu, ((sel >> 20u) & 1u) != 0u); // s192 add
r6 = rotl_imm(r6, 22u); // s193 rotl
r3 = r3 ^ r7; // s194 xor
r7 = r7 * r0; // s195 mul
r3 = r3 ^ r5; // s196 xor
r5 = r5 + r1 + select(0x8519428cu, 0xeae84577u, ((sel >> 29u) & 1u) != 0u); // s197 add
r7 = r4 * r4 + r7; // s198 mad
r3 = r3 + r6 + select(0x468639d3u, 0x0bfdbfa1u, ((sel >> 8u) & 1u) != 0u); // s199 add
r5 = r3 * r4 + r5; // s200 mad
r2 = r2 ^ simd_shuffle_xor(r7, (ushort)4); // s201 shfl
r7 = r7 + r4 + select(0x18ec9a69u, 0x53ee8e50u, ((sel >> 23u) & 1u) != 0u); // s202 add
r6 = r6 ^ r0; // s203 xor
r4 = r4 + r5 + select(0x3e81485bu, 0xac63376eu, ((sel >> 4u) & 1u) != 0u); // s204 add
r7 = r1 * r4 + r7; // s205 mad
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)16); // s206 shfl
r4 = r4 * r0; // s207 mul
r1 = r1 | r6; // s208 or
r6 = r6 + r4 + select(0x66ccb75du, 0x5b745519u, ((sel >> 28u) & 1u) != 0u); // s209 add
r1 = rotr_var(r1, r3); // s210 rotr
r5 = r5 - r4; // s211 sub
r4 = r4 ^ r7; // s212 xor
r1 = r1 + r7 + select(0x0ce0553du, 0x1c3dccf7u, ((sel >> 8u) & 1u) != 0u); // s213 add
r0 = mulhi(r0, r1); // s214 mulhi
r3 = r3 + r6 + select(0x96bfec89u, 0xfadc9205u, ((sel >> 9u) & 1u) != 0u); // s215 add
r0 = rotl_imm(r0, 4u); // s216 rotl
r6 = r6 ^ r4; // s217 xor
r6 = r6 ^ simd_shuffle_xor(r7, (ushort)2); // s218 shfl
r7 = r0 * r1 + r7; // s219 mad
r4 = r4 * r0; // s220 mul
r2 = r6 * r0 + r2; // s221 mad
r5 = r5 ^ r4; // s222 xor
r0 = r0 * r5; // s223 mul
r2 = r2 + r0 + select(0x61495681u, 0x66b15c04u, ((sel >> 9u) & 1u) != 0u); // s224 add
r3 = rotr_var(r3, r2); // s225 rotr
r2 = r3 * r3 + r2; // s226 mad
r6 = r6 ^ r0; // s227 xor
r4 = rotl_imm(r4, 30u); // s228 rotl
r2 = r2 + r3 + select(0x70d05c34u, 0x25bc17c2u, ((sel >> 29u) & 1u) != 0u); // s229 add
r1 = rotr_var(r1, r5); // s230 rotr
r1 = r1 + r4 + select(0x32a28384u, 0x2d8728f3u, ((sel >> 8u) & 1u) != 0u); // s231 add
r1 = rotl_imm(r1, 6u); // s232 rotl
r2 = r2 + r0 + select(0xcf0949f1u, 0x61e81fe6u, ((sel >> 21u) & 1u) != 0u); // s233 add
r4 = rotl_imm(r4, 2u); // s234 rotl
r2 = r2 - r6; // s235 sub
r6 = r6 | r3; // s236 or
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)4); // s237 shfl
r1 = r1 ^ r3; // s238 xor
r2 = rotl_imm(r2, 1u); // s239 rotl
r5 = rotr_var(r5, r2); // s240 rotr
r4 = rotl_imm(r4, 10u); // s241 rotl
r6 = r6 + r2 + select(0xe204fb50u, 0x0a67565du, ((sel >> 16u) & 1u) != 0u); // s242 add
r1 = r1 ^ simd_shuffle_xor(r3, (ushort)2); // s243 shfl
r0 = r0 ^ simd_shuffle_xor(r1, (ushort)16); // s244 shfl
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)2); // s245 shfl
r4 = r4 ^ r5; // s246 xor
r7 = r7 ^ r2; // s247 xor
r0 = r0 ^ simd_shuffle_xor(r6, (ushort)16); // s248 shfl
r1 = mulhi(r1, r3); // s249 mulhi
r7 = r7 + r5 + select(0x3d6daffdu, 0x5a79fd6fu, ((sel >> 31u) & 1u) != 0u); // s250 add
r6 = r6 + r0 + select(0x84334aeau, 0x6beb28c2u, ((sel >> 28u) & 1u) != 0u); // s251 add
r7 = r7 - r1; // s252 sub
r5 = rotr_var(r5, r2); // s253 rotr
r2 = mulhi(r2, r5); // s254 mulhi
r6 = r6 * r3; // s255 mul
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000". Do not edit by hand.
// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v5, memory-hard dataset
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#define IGNEUM_VEC_WARPS 3
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
{ // base nonce 0
0xe552166a03298f7full, 0xf526f1c5bbcce3feull, 0xd2599307c7dff26dull, 0x292f1d7c62935cefull, 0x176dd4b8dc247c8eull, 0x916c618e3f222f3cull, 0xc4b4cd32e2b17869ull, 0x083985b4514fdb52ull,
0x471c78fc23623557ull, 0x3ef558f8f91fef48ull, 0xc3a23b4f40a9b42eull, 0xe0cad6d14d62a59eull, 0x23be7de4ce7cde95ull, 0x3eb342c0a40d848aull, 0x93bd93cc7f35be92ull, 0xd468fe59ee140d1aull,
0x242f02aefcdd4907ull, 0x4a0af1c5c1807a38ull, 0x40cc94e1ba07667dull, 0xb20da649934a63f1ull, 0x172560c509523166ull, 0x7608ac11340f39efull, 0x4b401d953c834cbaull, 0x66017b835f9d80e2ull,
0x9150f03bfeac28d3ull, 0xdf54e85028a3591aull, 0x637a68f8ad0a322full, 0x48f87298734fdb52ull, 0x65f3200db1282d59ull, 0x6c48d31c96caa0e4ull, 0x3b06a9d989aa3eb7ull, 0x316f5a49394af8abull
},
{ // base nonce 4096
0xd2d4d57cca870a92ull, 0xc2a46c89e9e8d2e8ull, 0xe9d5a1048e9e357full, 0xa482ea1a68fb0fdfull, 0x9d4c01c50ebafb81ull, 0xe844ac46bf40758aull, 0x4fccaf252c2cbbf7ull, 0x90f96462f44878a4ull,
0x07bad307b27ea868ull, 0xf93fba205fd5a9ccull, 0xc08d0da873abfff4ull, 0x5fcb36b12eabd4b3ull, 0x48cbb9465226c503ull, 0x7281def60f0c6982ull, 0x609c4a01b5ff6b09ull, 0x505e0d5083c5ebfaull,
0x2e6370a4045ee3daull, 0x16df206ad3197bf6ull, 0xb63552c2e683f34aull, 0xb48d70f0f4fe8c3cull, 0xe4f941f4d5cac0bdull, 0xfe43ac9df2145859ull, 0x5964c115d0d9616full, 0xc2fb078d60b1b21cull,
0x663a7905f56d4585ull, 0xfad4000340b1e774ull, 0x0e9cf62f4e5b5fe9ull, 0xa284122fdd4037e3ull, 0x0e24488e1fe86f6eull, 0x563f0ca5d9d78390ull, 0x3b9c6c5bb8ca2771ull, 0xe2dafada40c22022ull
},
{ // base nonce 1000000
0x46d0145d98c681e2ull, 0x2909904cf57e5364ull, 0xb3686f5347a3920dull, 0x48c80e2427513b60ull, 0xae8b429006c2876aull, 0xdfeeddc0b4714cbbull, 0xa839ddb421d4b06bull, 0x77265ae1bde25c0bull,
0x666fda9b8a119724ull, 0x2fba7b9e71ddd3b3ull, 0xc81c4e05c94a23feull, 0x49c52ee7e025f9bbull, 0x7951fad6f47e130dull, 0x9769f514ba0c5527ull, 0xe8cf1f573d573d41ull, 0x5f6c19433ba166d0ull,
0x70806160896dc78bull, 0xbcbd57d0462c2b4full, 0xce880c91f263b526ull, 0x4bd3f39d60e5b6f3ull, 0x065159ea440706f5ull, 0xe4cbee1294943b62ull, 0xa2ce61093e845bdcull, 0xc6195798c0f2cdd0ull,
0x1c4b63a0aea5fd36ull, 0xe5254c6a049e115aull, 0x9bdf1a4ca31ecf17ull, 0x64f8159b9c84ddd4ull, 0x78c6caf1a64a7293ull, 0xe360359048ecdc56ull, 0xf55b82c8ed94c781ull, 0x423ef7066859a0b0ull
}
};
// Dataset self-test: dataset[0..15] and dataset[IGNEUM_MASK] (268435455).
static const uint32_t IGNEUM_DS_HEAD[16] = {
0x0790a3c8u, 0xf061f4c1u, 0xc93a88c3u, 0x0b6b0fb8u, 0x4dc6214au, 0x7e397ebau, 0x62bdca7cu, 0x2cd12c0cu,
0xb8a05ca1u, 0xe4e4e28fu, 0xb8623289u, 0x8244cdd4u, 0x12bb8880u, 0xd8cb0b94u, 0x6c8c05b9u, 0x26fd923bu
};
static const uint32_t IGNEUM_DS_LAST_INDEX = 268435455u;
static const uint32_t IGNEUM_DS_LAST = 0xc5f96c2eu;
// 64 sampled dataset words (index, value) computed on the Mac.
#define IGNEUM_DS_SAMPLES 64
static const uint32_t IGNEUM_DS_SAMPLE_INDEX[IGNEUM_DS_SAMPLES] = {
59471966u, 217795994u, 208353206u, 42483309u, 172547758u, 148076330u, 183853158u, 214389424u, 267488061u, 169781097u, 184093494u, 153880993u, 84977930u, 46426879u, 3093825u, 225364072u, 44593546u, 260713159u, 168250303u, 52384140u, 223401610u, 45554030u, 95410555u, 175039924u, 79171087u, 267580473u, 24168642u, 37981670u, 171551130u, 195559979u, 204611762u, 140997658u, 138925853u, 86637313u, 20736778u, 219665210u, 160430336u, 264654675u, 8013395u, 228945585u, 213884386u, 104419827u, 44185464u, 142737231u, 99284897u, 132475900u, 61861762u, 132056166u, 262388043u, 91878046u, 117353561u, 124768597u, 71352993u, 190698941u, 46055428u, 55281366u, 165145231u, 106810753u, 171985651u, 232085256u, 159510492u, 40072060u, 209107596u, 39023794u
};
static const uint32_t IGNEUM_DS_SAMPLE_VALUE[IGNEUM_DS_SAMPLES] = {
0x9dead642u, 0x94ef5e4au, 0x74892075u, 0xbc8466d3u, 0x5da3db7au, 0x5f7d336cu, 0xdb6e2d4bu, 0x707871e4u, 0xab1a8c26u, 0x095645e2u, 0x009e1047u, 0x0e043163u, 0x7f7a83f7u, 0xc80d8368u, 0x5c82379du, 0x6f040f0au, 0x9c15d89bu, 0x2e8158f1u, 0x899eb1dbu, 0x6b7b78ceu, 0x87c98f2du, 0x9bf58c2cu, 0xfe7c3758u, 0x135eb1c6u, 0x2241ea1cu, 0x58a5f34bu, 0x96891cc6u, 0xf3e92116u, 0xca2b5299u, 0xc48760fbu, 0xbfc8e6ecu, 0xf10dbadfu, 0x19672a34u, 0x2b38c7f0u, 0x2cc23ef9u, 0x732c2e9au, 0xa733b519u, 0xb4f99cc9u, 0xe0f2ceddu, 0xe405baa6u, 0x2515e05eu, 0xb5fe054eu, 0x62e77ca0u, 0x18a85e70u, 0x8c0deaf1u, 0x42a2f9c8u, 0x06e2ad43u, 0x14a20999u, 0x1d817d84u, 0x3493d381u, 0xc60d470bu, 0x6366a26bu, 0xfa46d099u, 0xa3d3c90eu, 0xcc73ca26u, 0x3ed2d84eu, 0xfca19a4fu, 0xa43b015eu, 0x1f5203b5u, 0x3bfb700cu, 0x1cb4554cu, 0x4c45d8afu, 0x271554b7u, 0xfb3d3fb8u
};
// Cache self-test (memory-hard mode): cache[0..15], the last 16 words, and FNV-1a 64 over all 2^26 words.
static const uint32_t IGNEUM_CACHE_HEAD[16] = {
0x47e15959u, 0xf138e163u, 0x4fc0aa19u, 0xbe50897cu, 0xddcc43a9u, 0xfbecd8bau, 0x3be5e048u, 0xc330cb77u,
0xc00ff902u, 0x62eb64d7u, 0x825ef196u, 0x9bd34544u, 0x84c52834u, 0x6f7303eau, 0x5546e71fu, 0x3f0b835cu
};
static const uint32_t IGNEUM_CACHE_LAST[16] = {
0xfe146921u, 0x0d972fc0u, 0xa5383d3eu, 0xf751aaf9u, 0x52509092u, 0x447ad742u, 0x18253e5cu, 0x15dae1fbu,
0xff5b8c7du, 0x8914179bu, 0xdfec91fau, 0x80d3d462u, 0xec0a5caeu, 0xa8af9a8bu, 0x1b7935a6u, 0x1026962fu
};
static const uint64_t IGNEUM_CACHE_FNV64 = 0x7334fa46e5d972ebull;

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{
"seed": "igneum-epoch/4020cb4382e3fe4b281c817c02582e147d8f851f566ae9172b28912b8e68b925/day/69676e65756d2d6461792ffd50000000000000",
"day": "bytes:69676e65756d2d6461792ffd50000000000000",
"dataset_mode": "memory-hard",
"dataset_log2_words": 28,
"mask": "0x0fffffff",
"lanes": 32,
"source": "igneum-pow (Rust) CPU interpreter, generator v5, memory-hard dataset",
"warps": [
{"base_nonce": 0, "expected": [
"0xe552166a03298f7f", "0xf526f1c5bbcce3fe", "0xd2599307c7dff26d", "0x292f1d7c62935cef", "0x176dd4b8dc247c8e", "0x916c618e3f222f3c", "0xc4b4cd32e2b17869", "0x083985b4514fdb52",
"0x471c78fc23623557", "0x3ef558f8f91fef48", "0xc3a23b4f40a9b42e", "0xe0cad6d14d62a59e", "0x23be7de4ce7cde95", "0x3eb342c0a40d848a", "0x93bd93cc7f35be92", "0xd468fe59ee140d1a",
"0x242f02aefcdd4907", "0x4a0af1c5c1807a38", "0x40cc94e1ba07667d", "0xb20da649934a63f1", "0x172560c509523166", "0x7608ac11340f39ef", "0x4b401d953c834cba", "0x66017b835f9d80e2",
"0x9150f03bfeac28d3", "0xdf54e85028a3591a", "0x637a68f8ad0a322f", "0x48f87298734fdb52", "0x65f3200db1282d59", "0x6c48d31c96caa0e4", "0x3b06a9d989aa3eb7", "0x316f5a49394af8ab"
]},
{"base_nonce": 4096, "expected": [
"0xd2d4d57cca870a92", "0xc2a46c89e9e8d2e8", "0xe9d5a1048e9e357f", "0xa482ea1a68fb0fdf", "0x9d4c01c50ebafb81", "0xe844ac46bf40758a", "0x4fccaf252c2cbbf7", "0x90f96462f44878a4",
"0x07bad307b27ea868", "0xf93fba205fd5a9cc", "0xc08d0da873abfff4", "0x5fcb36b12eabd4b3", "0x48cbb9465226c503", "0x7281def60f0c6982", "0x609c4a01b5ff6b09", "0x505e0d5083c5ebfa",
"0x2e6370a4045ee3da", "0x16df206ad3197bf6", "0xb63552c2e683f34a", "0xb48d70f0f4fe8c3c", "0xe4f941f4d5cac0bd", "0xfe43ac9df2145859", "0x5964c115d0d9616f", "0xc2fb078d60b1b21c",
"0x663a7905f56d4585", "0xfad4000340b1e774", "0x0e9cf62f4e5b5fe9", "0xa284122fdd4037e3", "0x0e24488e1fe86f6e", "0x563f0ca5d9d78390", "0x3b9c6c5bb8ca2771", "0xe2dafada40c22022"
]},
{"base_nonce": 1000000, "expected": [
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"0x666fda9b8a119724", "0x2fba7b9e71ddd3b3", "0xc81c4e05c94a23fe", "0x49c52ee7e025f9bb", "0x7951fad6f47e130d", "0x9769f514ba0c5527", "0xe8cf1f573d573d41", "0x5f6c19433ba166d0",
"0x70806160896dc78b", "0xbcbd57d0462c2b4f", "0xce880c91f263b526", "0x4bd3f39d60e5b6f3", "0x065159ea440706f5", "0xe4cbee1294943b62", "0xa2ce61093e845bdc", "0xc6195798c0f2cdd0",
"0x1c4b63a0aea5fd36", "0xe5254c6a049e115a", "0x9bdf1a4ca31ecf17", "0x64f8159b9c84ddd4", "0x78c6caf1a64a7293", "0xe360359048ecdc56", "0xf55b82c8ed94c781", "0x423ef7066859a0b0"
]}
],
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}