From acd113d9632f98f93da4b3e36e5aaf6a8236f4d9 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 18:01:55 +0000 Subject: [PATCH] Igneum 2.0 register: the nine review rows (A01 to A09, main's dispatch) and the 19:0x coverage; the registry's times read UK on master's current copy (the enforced-proving and steward rows kept); Counter ASIC 3.0 status: the registry approved and on master, ECO-05's FAIL under P12 and main's three rulings, build-5 green as a Cloud ccx53, the 18:57 kill by name and its re-runs, the pairing rule for 291ee6ae, the lanes' clocks Rule 26: the registry edit is the time strings only (BST to UK) on master's copy as it stands after 94c265568 and 2160acf1; nothing of any lane's fields is dropped. Co-Authored-By: Claude Fable 5.1 --- docs/plans/counter-asic-3-status.md | 10 +- docs/plans/igneum-2.0-register.md | 12 +- docs/plans/igneum-2.0-test-registry.json | 264 +++++++++++------------ 3 files changed, 152 insertions(+), 134 deletions(-) diff --git a/docs/plans/counter-asic-3-status.md b/docs/plans/counter-asic-3-status.md index f75812550..db3c40eaa 100644 --- a/docs/plans/counter-asic-3-status.md +++ b/docs/plans/counter-asic-3-status.md @@ -465,7 +465,15 @@ Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of | 1,200 | 133.80 | 305.1 | 0.439 | 129.54 | 215.7 | 0.601 | 1,192 | | 1,100 | 122.43 | 287.3 | 0.426 | 118.70 | 209.4 | 0.567 | 1,087 | -The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. THE FAST-TIME GATE ON THE RE-CUT: SUMMARY PASS (cross-0324-c9e385eb) at 22:49:32Z (23:49 BST) on the shipped 0.3.24 re-cut c9e385eb (igneumd 7a841b20..., igneum-miner 1e209b9e..., igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 22:36:25Z to 22:49:32Z, every check green: rung 1 by signal at epoch 6 (22:42:54Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (22:44:54Z, 4 of 4, 9,985 bps), 11 of 11 ids equal to the CPU verifier's, the stale node 86 of 86 refused with 0 accepted after the first refresh, the restart step across the boundary on a kept datadir resynced in 28.1 s with the catch-up done after 10 s and 0 of its own blocks during it, four sinks equal at 660, honest nodes 0 PoW rejections; record on v5-fasttime 76276be6, docs/design/class-v5-harness/fasttime/cross-0324-c9e385eb.json. The 0.3.24 move's gates left (the shipper's correction of this record): not F9 and F1's full 10^5 PASS (landing about 00:40 BST, too close to the 00:52 ceiling) but an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, max attempt 25), any non-zero holding the move, the full 10^5 the record line after; the minute named by the fleet on the last FETCHED plus ten once the build-server lane's c9e385eb pairs land. THE 61-ROW ERA READING (the v5 lane, box 2, 23:4x to 23:5x BST, docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log): 0 of 61 refused by the 0.995 floor at the table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), every class v5 draw on the class v4 attempt; era-drawn-28 (id 5e9eb01efbbf653e, attempt 6, R 15, the worst of adv-cache-2's census at 1.7451x) reads its biased site 15 at 0.9969, over the floor by 0.0019; era-drawn-25 (1.3571x, R 21) site 11 at 0.9994; the eight over 1.2x span 0.9965 to 0.9997 while the eight few-item hot sets sat 0.003 to 0.013 under the line. Main's sentence opens AP-F8-6 and section 14 verbatim with the two-instrument reading under it. THE CLASS V5 ATTEMPTS CENSUS for 1.4.7 (1,000 f8 seeds through the chain draw, v5-attempts-census-1000.log, the crypto lane's form): 3,219 candidates, 2,219 rejected, per-candidate rejection 0.6893 (sub-version 3: 0.68), accepted attempt mean 2.219, 0 exhaustions, P(256 consecutive) 4.4e-42; first failing part (a') 83.4 percent of rejections, (a) 10.7, (b) 3.0, (c'') 1.2, (c''') 1.0 (0.7 percent of candidates, one in 140: the floor's own share, 0.045 on the attempt mean), (c) 0.7 together, (c') none; the 5.14 percent of class v3 that 1.4.6 quotes is the audit lane's to replace. Both on class-v5 at 3b1dffd6 with main's sentence (891dd008), the mirror's master merged (e0471019: AP-F8-1's update and AP-F8-4 taken, the program-id recipe form with the state tag, no conflict), the design page's pre-public scrub (the founder's name six times, gone), M35's status word and the regenerated public ledger; the push waits on the full gate and the pinned-packs test on the merged tree (the proof that e5a4ac5978462156 and the other ids still derive under master's recipe form). THE 00:00 BST READINGS (the crypto lane; the verified roll-up of all nine lanes in section 13 of in-house-pass.md on crypto-engage, every branch tip read from the mirror and igneum-pow identical to 017e7037 on each). adv-accept, tip a7c49399 (about 5.5 box-hours, 0 pod-hours): 182,646 distinct accepted programs drawn (18 percent of the 10^6); eight pass every part of the frozen rule and flag the live hot-set test at 2^24 (X at 0.1 percent +0.102 to +0.221, 1.54x to 2.24x), all in the lowest 34 stand-in-ratio seeds against 0 in 20 random; each about 1 MB of items holding 0.26 to 0.41 percent of reads, 1.002x at the largest; the mechanism a near-saturated source at one site mapped by the era stride to one fixed item (plus two lesser shapes); the exemplar reads the same under the class v5 dataset. Against the class v5 floor: 8 of 8 refused; 3 mild residuals missed (adv-cache-2's rotation class, a load_index question not a floor question); 6 clean programs refused among the 9 deepest (the 2.4 percent). Q2 BOUND (54 programs plus 17 reads, 0 disagreements). Row 90: 0.6787 per candidate, (a') 83.3 percent, 0 exhaustions, P 8e-44. Partial named: 18 percent of seeds, 54 live rows, row 90 at half; a longer pass adds rows of the same shapes, not a different answer, unless a seed reads a hot set over 1 percent of reads, which 182,646 draws did not produce. THE PER-LOAD CLASS CLOSED (the research lane, for main; clock readings UTC): the per-load shadow fix held for distinctness and then met the value-level requirement from adv-cache-2, and the construction did not survive it; the per-load 16 x 27 class is dead as a chain class. 22:44 the attempt verdicts on four seeds (igneum-genesis 0 of 32 accepted); 22:47 the 64-seed census under the full rule (duplicate lanes at a load row plus the one-count of every index bit per site over the 64 units, 6-sigma band): 22 of 1,621 candidates accepted (1.4 percent), 42 of 64 seeds exhaust the chain's 32 attempts (an epoch without a program); the first failing test per candidate: biased index bit 775, duplicate lanes 643, the base rule 110, (b) 43, (a) 28; candidate 0 of the class carries index bit 0 set in 40 of 1,024 addresses (z 29.5); 22:52 the suite green (64 + 5 + 7 + 4 + 19 + 2 + 7); the acceptance rule with BiasedIndexBit for this class and the tests pushed as the record, the file's 20.2a closed. The structural reason: 27 passes of a 16-instruction map right before a load is an iterated small function and collapses or biases the load's address register before any base instruction re-randomises it; the class v4 shape has 64 base instructions and 16 loads between its block and every load. Both exports were accepted only because the rule did not model the placement; their PC 1 rows stay as an energy reading of the placement, labelled unsound. Rank 4 and the USD 200 M capex row rest on a construction not shown to exist (chip model 5.11's clause marked so in this landing); the sound form is one pass of a 432-instruction sub-block per load (a program segment, not an iterated map), a new class to draw, accept and measure, not tonight's. Replicated by a second instrument: the class v4 shape on this pre-amendment generator carries the adv-cache-2 product bit at address bit R exactly in 14 of 17 drawn eras (one-count 250 or 780 of 1,024, z 15 to 19), 0 duplicate pairs across the eras. What stands from the two prototypes: the tile block (bit-exact on the Metal reference, the AVX2 verifier at 0.047 us per tile, the Apple emulation cost 35 to 78 percent) awaiting its 5090 rows; the per-load placement closed. THE SPEC REWRITE ON MASTER (the site audit lane, 8b834634 at 23:56 BST; gate GREEN on 64e2a91b, 71 checks; the igneum-pow suite green on the box for that commit with derivation.rs and spec_readback.rs): spec 01 sections 1.4.3 and 1.4.6.1 to 1.4.6.6 rewritten to 017e7037 with the 20-row constants table (ACCEPT_TAG, the window-cap literal, MAX_SATURATED as the first refused count with the 163 message noted) and the 6-row pinned-ids table with Devnet 3's full genesis hex; the shadow block in 1.7; the ninth era draw in 1.13.1; tools/ci/spec-constants-check.mjs in the gate (known-failed first, every Constant | Value | Where table, pending rows skipped while absent); igneum-pow/tests/spec_readback.rs (ids derived through the crate, each class v4 row drawn to its attempt); ledger AP-F8-5 after AP-F8-4; the ledger-page fix (both heading forms, the pass as its own section, known-failed self-test in the gate; AP-F8-1, AP-F8-4 and AP-F8-5 render on /ledger); the fud-ledger's two prize clauses and "paid independent cryptanalysis" removed at the source so the regenerated page carries neither (commit 90424d5a, merge 64e2a91b). A HARDWARE FACT IN DISPUTE, for main: tonight's 5080 efficiency rows came from PC 1 jobs (run-ca3-pc1-v4-eff-5080-20261007-b and -c), the audit lane's record reads the RTX 5080 and the Arc B580 on PC 1, the hash lane's 22:09Z device list on PC 1 shows the 5090, the 9070 XT and the 4070 only, and main places the 5080 and the B580 on PC 2; identity-check.sh's "PC 2" substitution text names cards and is left card-free until the PC 2 job's own --list settles which cards sit where. THE IDENTITY CHECK'S PC 2 TEXT (the CI steward, 00:05 UK on 8 October): tools/ci/identity-check.sh rewrites "PC 2" card-free as "the second Windows rig" (commit 40f2be54, merge 0d2cf334, gate GREEN 71 checks, identity grep 0 hits over 306 export files and 52 served pages); line 69's PC 1 list untouched; the reason recorded in a bash comment above the perl call. THE 32,400 FLOOR LOST (the node lane, 00:0x UK on 8 October): dn3-g1's chain read DAA 25,126 at 23:52:03Z and 25,169 at 23:52:38Z, so the publish DAA passed 25,200 at about 23:53:09Z with no 0.3.24 move made (build-1's three Devnet 3 nodes last restarted about 21:31Z on the 0.3.23 move; the old seed holds 38 peers on ba75bf6f; no move minute was named). The next boundary is 36,000 (epoch 10), about 02:52Z on 8 October (03:52 BST) at 1.0 DAA/s, holding for a publish up to DAA 28,800 (about 00:53Z, 01:53 BST). Two routes put to the shipper and main: the same re-cut script on release-0.3.24-node (program_class_v5_activation_daa 36,000, nothing else, the same gate set, about 20 minutes to the pin line), or the fleet names its minute first and the floor is cut from it in one go (publish DAA plus 7,200 to the next 3,600) instead of a fourth chase; the pin c9e385eb stands meanwhile. THE FLOOR RE-CUT FROM A NAMED MINUTE (the shipper, 00:1x BST on 8 October, under the slip rule main set with the object commit): the floor re-cuts once more to 39,600 (epoch 11, about 04:52 BST) from a move minute the shipper named: 02:00 BST on 8 October, or the fleet's last FETCHED plus ten if later but before 02:53 BST (DAA 32,400, the ceiling); the node lane's pin line in about 20 minutes with the new Devnet 3 digest; the F9/F1 interim read at 01:55 BST; the publish minute equals the move minute (the apps' entries at or after it); the fast-time SUMMARY PASS reruns on the new pin as part of its gate set; the cause of the lost floor named: the c9e385eb pairs and the two PC jobs unreported for forty minutes, so the fleet had nothing to point its move file at. "slot closed" on PC 1 still waits on the host job's exit. THE 0.3.24 NODE PIN AT 39,600 (the node lane): dfbd1e10 on release-0.3.24-node (both mirrors, 23:54:13Z) = c9e385eb with program_class_v5_activation_daa 39,600 (epoch 11), nothing else; pairing igneum-pow 1c420786; every gate green at 00:01:52Z (build 23:56Z rc 0 at gate priority, igneumd 4870ccf2..., igneum-miner aa8c2978..., /srv/artefacts/0324-dfbd1e10/node-lane; pow 19, consensus 134, p2p-flows 38, exec 47, core 175, miner 28); the Devnet 3 canary set (23:56:33Z to 23:58:13Z): digest b1ba78229b069dc395fa666638a686a66615eb760d251798adfa6a654a415f82 on igneum-devnet-3 from ba75bf6f, object version 6 stamped (block version 1538), the override file refused, shutdown 2,015 ms, two empty nodes handshaking on it, the shared-devnet dialler rejected, a 2720d8d2 node refused on the digest both ways; the testnet canary b2e856ed unchanged (byte 7, a live old-object testnet node refused). The cut's read: dn3-g1 at DAA 25,169 at 23:52:38Z (1.0 DAA/s), the publish DAA at the named minute 01:00Z about 29,211, plus 7,200 = 36,411, the boundary 39,600 about 03:53:09Z on 8 October (04:53 BST), holding for a publish up to DAA 32,400 (about 01:53:09Z, 02:53 BST). The one gate running: the fast-time pair on dfbd1e10 (about 13 minutes from its start). c9e385eb is void as a pin; the F9/F1 interim read armed at 00:55Z. THE TWO PC QUEUES AT 01:03 BST (the hash lane): PC 1's "slot closed" has not come (the shipper's 0.3.24 host job, the build-server lane's, took the slot at 22:13Z for an expected two to three minutes; nothing reported in 110 minutes); nothing of the hash lane's has run on PC 1 since 22:09:25Z; the v5 kit fetch and the 9070 XT v5 bench are prepared and unpublished (tools/ca3-v4-amend/pc1-publish-20261007.sh, steps v5-kit and v5-amd), so no 9070 XT class v5 fingerprint exists yet; the lock protocol holds unless main says the lock-free pair goes ahead of the silent host job. PC 2's "clear" has not come either (the 0.3.23 take 3 smoke and the scheduler proof unreported by either lane); the Intel job is prepared and unpublished. THE HARDWARE FACT, read from tonight's PC 1 lines: nvidia-smi on PC 1 lists GPU 0 RTX 5090 (bus 01:00.0) and GPU 1 RTX 5080 (bus 0D:00.0); its OpenCL list carries the RX 9070 XT (gfx1201) and the integrated gfx1036 and no Intel platform; so the 5080 is on PC 1 (the audit lane's record right, the 22:09Z device-list summary short by one card) and the Arc B580 is not, which agrees with main's word that it is PC 2's eGPU; the kits row, the bench notes and identity-check's card-free PC 2 text stand on that. The locked PC 1 jobs stay parked (the 5080 full grid, the third 5090 pass, SM-sparse, the microbench and packs knee states, the two Ember tunes, the hot-table ldcs rows); the lock-free CA4 rows queue after the v5 bench on the same "slot closed". THE 00:00 BST READINGS, THE OTHER THREE (read by the crypto lane from each branch's report on the mirror at 01:03 BST; the roll-up section 13 of in-house-pass.md at crypto-engage c84ba51b with adv-accept's reading at 1b4e07ff; all nine branch tips read back from the mirror and igneum-pow IDENTICAL to 017e7037 on every one: adv-mixer d2ba3134, adv-mixer-2 2a632579, adv-mixer-3 4ebe2455, adv-cache 555c3e42, adv-cache-2 9384ee09, adv-cache-3 9452c0bf, adv-accept a7c49399, adv-accept-2 92168536, adv-accept-3 0c150e3c). adv-accept-3 (exhaustion or steering of the draw), tip 0c150e3c, every sweep ended 23:05 BST, about 3.3 box-hours, 0 pod-hours: Q1 exhaustion BOUND (per attempt accept 0.323, reject 0.677 ((a') 0.568, (a) 0.079, (b) 0.022, dynamic parts about 0.009), geometric histogram, P(exhaust) 0.677^256 = 4.6e-44, 0 of 16,337 seeds at the cap); Q1b the last resort FINDING (correctness; the mirror fired at cap 256 byte-identically; of 3,000 last-resort programs the real rule rejects 271, 9.0 percent: 251 by (a), 14 by (b), 6 by (c) distinct sum; handed out unchecked; unreachable; closed in class v5 by 8ca66afa, AP-F8-3); Q2 steering BOUND (45 of 48 planted rows fired, the real rule rejects every effective plant by (a'); 975 seeds at the first part, min ratio 0.998, 18 of 18 chain re-draws equal); Q2b the price of a seed property at 1 in 10^6 tries is a shadow block with 38 multiplies of 256 against a mean 74, about 2 to 3 percent of the f = 1 chip's energy per hash, the load critical path worth nothing at the memory activate ceiling; Q2c the 256-unit ratio is noise as a selector; Q3 program id FINDING (documentation: the "sub/" || 3_le16 suffix omitted from program.json and spec 1.4.6; a text-derived implementation computes 30956569d8f3d8d7 for Devnet 3 against the pack's fce15bf61030be57; 0 collisions over 10^7 pairs; fixed as AP-F8-4 at da2fc101); Q4 determinism DONE (the (c'') f64 compare never disagrees with the integer rule on any of the 2^20 + 1 values, margins 0.32 to 0.44 counts; a second interpretation agrees on 5,748 of 5,748 verdicts of 1,792 seeds); Q5 the era lever BOUND (400 eras, no stride under NAF weight 7, all 31 rotations, 354 distinct interleaves; epoch 0's accepted attempt is 3 under every era, so the era moves the address map, not the program). Partial named: the steering sweep at 975 of a planned 10^5 seeds (about 8 box-hours more at 32 cores). adv-cache-2 (the hot-set attack), tip 9384ee09 at 23:52 BST, about 2.2 box-hours by wall times threads over 96 (the boxes at load 400 to 600 for the first two hours), 0 pod-hours; two shards still queued at 00:00 (lines-2e30-s2c, warps-devnet-2e25-v2), named partial: Q1 the line index PASS (pooled 16 days; segments max +4.84 sigma against a control's +4.24, lines +5.61 against +5.35, chi2/dof 0.99937, top 0.1 and 1 percent of lines 1.0003x and 1.0002x of control; the 2^35 + 3 x 2^33 census all PASS; 0 mirror mismatches); Q2a the real programs PASS on the hot-set test (devnet at 2^26 1.0002x; Devnet 3 at 2^26 items 1.0071x, lines 1.0000x) with the FINDING at Devnet 3 site 0; Q2b all 64 programs done, every one clear on the hot-set test (items 0.9993x to 1.0075x of the windowed control) but the site class as recorded above (13 of 27 drawn-era over 1.04x, 8 over 1.2x, worst 1.7451x; the v5 floor refuses 0 of 61; AP-F8-6); Q3(1) steering by t PASS (worst cell 3.95 sigma in 2 x 2,112 cells); Q3(2) the weak-day scan PASS over 16,384 days (2^30 derivations in 707 s; worst per-day max bucket +8.13 sigma against the control's +7.78; the plant fired at +1,090); Q3(3) the window layer: the exact distribution matches the 4,096-program census to four digits (top quarter mean 0.3382, top half 0.5811), with a FINDING against the chip model's table: the f = 0.25 and f = 0.5 partial-store rows overstate the recompute share by up to 1.8x at f = 0.5, the full-store (f = 1) verdict unchanged (a correction owed in chip-model-v3's partial-store rows; no served number rests on f under 1); Q4 the prices: the only measured excess over f is the window layer's and the line reference multiplicity (a hottest-lines half store hits 57.8 percent instead of 50 at a higher miss cost than the stride). adv-mixer-3 (the statistical distinguisher and round margin), tip 4ebe2455 at 00:41 BST, still RUNNING at 01:03 (Q3 and Q4 at k = 8 on day 20729, queue 07 in the pool, the SAT ladder at k = 3 timed out; the total box-hours the lane's to give): Q1 the exhaustive round-0 line-index census over all 2^32 t PASS to k = 8 on days 20729 and 20733 and at k = 2, 3, 4, 8 on 20730 (z within 1.5); Q2 single-bit avalanche FINDING at k = 1 (354 and 266 holes, 130,000 cells beyond 6 sigma, the known one-application diffusion), PASS from k = 2 at 2^24 (0 holes, worst z under 5.3 through k = 8); Q2b the t-bit avalanche the same shape; Q3 differential multiplicity over 576 low-weight differences FINDING at k = 1 (695 and 537 deterministic output bits), PASS k = 2 through 7, k = 8 running; Q4 and Q4b linear correlations PASS from k = 1 (worst c 0.00046 to 0.00062, z under 5.1); Q5 rotational-XOR PASS from k = 1; Q6 SAT: k = 1 SATISFIABLE in 137 s (t = 0x49880000 verified through the real code), k = 2 and 3 TIMEOUT at the one-hour cap. The round margin as it stands: no statistic survives 2 of the 8 applications between reads; a chip gets nothing from the k = 1 findings because every read sits behind 8. The lanes' own lines go into section 13.1 as they arrive. THE LANES' OWN 00:00 LINES (adv-accept-3 and adv-mixer-3, 01:0x BST, in section 13.1 of in-house-pass.md): adv-accept-3's P(exhaust) refined to 1.0e-43 per epoch seed from 62,240 full-rule candidates plus 3.0e6 static candidates; Q2 steering BOUND over 19,975 full-rule and 1e6 static seeds, no property buying over about 1.03x at 1 in 1e6 tries; a second documentary FINDING: an implementation written from the spec text (not the code) at 017e7037's spec differs on 264 of 400 epoch programs, the same text-against-code gap as the id suffix (the audit lane's rewrite 8b834634 with spec_readback.rs is the fix; the proof that it closes this is a re-run of the text-derived implementation against the rewritten text, asked); a plant note: the floor-0.97 known-failed variant did not fire because the (c'') ratios are bimodal (accepted 0.989 to 0.999, rejected 0.814 to 0.966), replaced by a single-pass (a) variant that did; 3.3 box-hours, nothing running. adv-mixer-3: about 3.0 wall-hours of sweep plus 4 single-core CaDiCaL hours; the round margin stated as 6 of 8 applications between reads and 70 of 72 per item on every measured statistic, the k = 1 effects one mechanism (the lowest-set-bit trail through one application, dead once both addends carry a difference), nothing saving one application against 9,360 ops per item; still running at 4 cores on build-1 (2^27 and 2^28 avalanche rows, finish about 03:00 BST) and the day-20733 SAT ladder on build-2 (about 03:45 BST); not attempted: multi-bit linear masks and a MILP trail bound. adv-cache-2's own line still owed. ADV-CACHE-2'S OWN LINE (01:05 BST, tip 3f50d6c4; section 13 of in-house-pass.md now carries every lane's reading in its own words plus the verified roll-up): the drawn-era prevalence read on the SAME 32 base programs is 2 of 32 under the devnet era against 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), the mechanism carried by rotl(x times M, R) into the item index unless R is 29 or 30 (2 of 31 rotations), with a sub-class of warp-uniform sources once in 16,000 warps; the window layer's price restated: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the chip model's partial-store rows overstate the recompute share by up to 2.3x on these programs, the f = 1 verdict unchanged (the correction to chip-model-v3's partial-store rows is the coordinator's next commit); partial named (the drawn-era windows census of 4,096 and one line shard in the pool); the longer-pass line: the biased-site rate per era in closed form (the R in {29, 30} rate 2 in 31) and a 2^28 read of the worst site. Nothing of the pass stands between the pool and a higher-class job except two pre-emptable shards on box 2. THE SPEC-TEXT RE-DERIVATION ORDERED (01:06 BST): adv-accept-3 re-derives its 400 epoch programs from the rewritten spec text alone at master 8b834634 (1.4.3 to 1.4.6 grown from 79 to 198 lines with the constants and pinned-ids tables), lease pool 16 --min 8 class adv, row Q4c in its report; the expected reading 0 of 400, any non-zero naming the diverging sentence to the audit lane; the proof that AP-F8-5 closed the text-against-code gap. THE CHIP MODEL'S PARTIAL-STORE ROWS carry a second correction (section 5, 8 October 2026) from adv-cache-2's window-layer reading: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the uniform-store rows overstate the recompute share by up to 2.3x; the f = 1 row, the SRAM column and the full-store verdict unchanged, no served number on f under 1. THE CLASS V5 PACKS TEST ON THE MERGED TREE (the v5 lane, 01:0x UK): the job ran on box 2 the minute two adv-accept holders ended (65 cores; no lease fault, plain starvation before); 19 passed, 1 FAILED: v5_pack_is_the_v4_program_over_the_state_leaves (tests/packs.rs:977), the byte-for-byte compare of every pinned pack file with the crate's export. The ids are EQUAL (v4-genesis exports a217c7f698880830 as pinned; the state tag rides in master's recipe form unchanged); what differs is the program_id_derivation TEXT in program.json, which master's export (the hash lane's AP-F8-4 read-back form) now writes as "... || attempt_le32 || 'sub/' || sub_version_le16" for generator 4 while the pinned packs carry the pre-suffix wording. Disposition: the three pinned packs re-exported from the merged crate (text only; the ids, kernel texts, leaves and the fingerprint 82b19cbde8557ea5 must come out byte-identical, proved by the same test); the CLI rebuilding on build-1 from 51aa5bc4, the export from the box's IGSD1 streams, the packs test and the full suite on box 2 at 16 cores, then the push; readiness about 01:35 UK. The 0.3.24 kit zip (packs-ca3-v5-20261007T221001Z.zip) carries the old derivation text in its program.json files: a text field only, no id, kernel or fingerprint change, so the kit stands for 0.3.24 and the shipper is told; the re-exported packs go in the next kit. THE ONE 0.3.24 KIT, NAMED for the shipper (01:1x BST): packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 the pin pairs with; the fleet keeps placing it. The 23:11 zip packs-ca3-v5-20261007T221001Z.zip (sha256 4aaf9b9e..., /srv/artefacts/packs/ on build-1, from class-v5 7f58af97) carries the same packs, ids, kernels, leaves, fingerprint and derivation text and differs only in the merged kit host code and scripts beside the packs; it is the bench lanes' kit for the fingerprint jobs. The coordinator's earlier line naming 4aaf9b9e as the 0.3.24 kit was wrong and is corrected here. THE SPEC-TEXT READ-BACK RUNNING (adv-accept-3's Q4c, 01:11 BST on build-2, lease pool 16 --min 8 class adv): the same 400 epoch seeds re-derived from the spec text at master 8b834634 alone (1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7, 1.13.1; a fresh text interpretation), compared field for field with the chain draw; the count about 01:21. One sentence already named divergent before the count: 1.4.6 part (c) cites dataset_elem(idx, S[0], S[1]) "of verify.rs" without stating its six operations, so part (c) cannot be computed from the text alone and the derivation takes that one function from the crate; the audit lane is to state the closed form's six operations in the text or the constants table, else 1.4.6 stays code-dependent on that line. A NINTH LIVE HOT SET (adv-accept, 01:12 BST): seed 228763 (id 2c4be0f6dc44c423, stand-in 0.9820) at 2^24 (X at 0.1 percent +0.118, 1.82x the window model), its single hottest item 0xe2cc96 at 1,218,380 reads, 0.057 percent of ALL reads, the largest single item of the pass (40x 100767's), from a NON-saturated source r0 at site 9 (the sel register), saturated-source share 0.000: the third shape at scale, a value-level concentration neither (c') nor a saturation test can see by construction; its 2^20 ratio against the 0.995 floor lands in minutes and decides whether the floor's instrument reaches it (if missed, the exemplar for the next class's non-saturated case). 638990 reads 1.51x beyond the gate with one item at 0.027 percent (r0, no saturation), no hot set; 623492 clean. Tally: 9 hot sets in 37 tail seeds against 0 in 20 random, 269,250 programs drawn; the price unchanged at 1.002x (0.27 percent of reads on 1 MB; one item 64 bytes). The public sentence's "eight of eight" moves to "nine of nine" or gains the first miss when the ratio reads. THE FLOOR REACHES THE NON-SATURATED SHAPE (adv-accept gap-tail3, 01:13 BST): seed 228763 reads minimum site 9 at 0.9809 at the 2^20 sample, the lowest of the pass, REFUSED; 638990 site 2 at 0.9872, REFUSED; 623492 (clean live) site 0 at 0.9922, REFUSED, a seventh false refusal. Final tally over everything the lane read at 2^20: 9 of 9 live hot sets refused (0.9809 to 0.9919), both single-item programs refused, 7 clean-live programs refused and 1 passed among the 12 deepest 256-unit seeds, 3 mild residuals missed at about 1.0004x. The reading: the distinct-index ratio reads any few-item concentration whatever its source, saturated or not, and misses only the diffuse era-stride excess; the class v5 floor closes the hot-set class entire at the 2.4 percent clean-rejection cost; the next class's value-level test is for the diffuse class alone. The public sentence reads "nine of nine hot sets refused" from here (the v5 lane's follow-up cfce57ea rides its push; AP-F8-1 on master updates with the next record commit). THE FAST-TIME GATE ON dfbd1e10: SUMMARY PASS (cross-0324-dfbd1e10) at 00:12:57Z on 8 October (01:13 BST), the shipped re-cut's binaries (igneumd 4870ccf2..., igneum-miner aa8c2978..., igneum-pow 1c420786), build-1 under lease pool class v5, 23:58:56Z to 00:12:57Z, every check green: rung 1 by signal at epoch 6 (00:05:37Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (00:07:46Z, 4 of 4, 9,985 bps), 12 of 12 ids equal to the CPU verifier's, the stale node 95 of 95 refused, the restart step across the boundary on a kept datadir resynced in 36.2 s with the catch-up done after 11 s (4 IsInIBD refusals of its own miner during it, 0 of its blocks accepted), four sinks equal at 661, 0 PoW rejections on the honest nodes; record on v5-fasttime 0a09eb78, docs/design/class-v5-harness/fasttime/cross-0324-dfbd1e10.json. Every gate on the pin is green; the move waits on the pairs on the dl host, the last FETCHED plus ten, and the F9/F1 interim read. THE RE-EXPORT READ (the v5 lane, box 1 with the merged crate ac285733): the three pinned packs' only difference was program.json's program_id_derivation text (generator 4 now "|| 'sub/' || sub_version_le16", generator 5 the class recipe "igneum-program-rw/ ..."); ids, kernel texts, leaves.bin, vectors and the fingerprint 82b19cbde8557ea5 byte-identical; the pinned packs carry the merged text; the full gate and the full igneum-pow suite with the packs test and spec_readback running on that tree, the push and commit string about 01:45 UK; main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2 at class-v5 b5d6368d (nothing with eight of eight reached the mirror). AP-F8-1's two eight-of-eight lines on master move to nine in this record commit. THE MOVE'S SOURCE (the shipper's ruling at 01:05 BST, corrected to this record at 01:1x): the 02:00 BST move does not wait on the build-server lane's pairs; that lane is dark (nothing published since 23:05 BST, nothing answered since 00:17), so the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair at /srv/artefacts/0324-dfbd1e10/node-lane on build-1 (igneumd 4870ccf2, igneum-miner aa8c2978, the pair every gate ran on, native glibc 2.39 on every fleet box), the way dn3-g1 and g2 moved at 22:30; the fleet's puller fetches from build-1, not the dl host. The move waits on the fleet publishing the dfbd1e10 move file and naming the minute (asked 01:05) and the F9/F1 interim at 01:55. The hive and the Windows pairs are the dark lane's loss for tonight unless main gives the shipper the word to build them (asked 01:06); the Mac entry publishes at the minute regardless; if the fleet has not published the move file by 01:40 BST, main and the coordinator hear it with the clock. THE PC 1 LOCK VOID, THE V5 AMD BENCH PUBLISHED (the hash lane, 01:1x BST): the shipper's 0.3.24 host job was never published to the jobs file, so the slot was void (the shipper's "slot void" at 01:05 BST); the v5 kit fetch landed on both PCs at 00:12:06Z (919,273 bytes, sha256 ok); run-ca3-pc1-v5-amd-bench-20261007 published 00:14:19Z (the 9070 XT by name, about 3 minutes, lock-free), its start line printing app_version, so the 0.3.20 or 0.3.23 reading of PC 1's app comes with the fingerprint; PC 2's Arc job needs only the shipper's "PC 2 clear". PC 1's app had NOT taken the 0.3.23 kit as of the last reads (every job log through 21:46Z app_version 0.3.20; the install folder's exe igneum-app 0.3.20, mtime 12:24:42Z, sha256 0443ae17...). The update-return lane (a22d765a2e0355a9f) last spoke at 23:0x BST: the helper workaround for 0.3.20 scripts (truncate cmd.txt, restart the task, wait for helper.alive, then write; or four leading " dev " padding lines), the locked jobs held as they are, power-helper-24 b9a72b9b merged into release-0.3.24 (daa7427b: a silent change becomes a logged line, the helper writes its exit reason), install-close-23 4ad6c199 for 0.3.23's take 3, the re-probe job when PC 1's app has taken the 0.3.23 kit; nothing since. THE SPEC-TEXT READ-BACK PASS (adv-accept-3 Q4c, 01:11 to 01:15 BST on build-2 at 16 cores; report section 6.5 on build/adv-accept-3, log 983-textderive-8b834634.tsv, pushed): the spec text at master 8b834634, implemented fresh without the crate's generator or rule, reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences (every instruction, the chosen attempt, the id, the rejection sequence); the 264-of-400 divergence against the text at 017e7037 is closed, so AP-F8-5 reads fixed on a measurement. The one remaining gap: 1.4.6.4 names dataset_elem "of verify.rs" without its six operations, so parts (c), (c') and (c'') still take that function from the crate; the audit lane's one-sentence closed form (asked 01:1x) closes it, and the read-back re-runs on the new text. THE AMD CLASS V5 FINGERPRINT (PC 1's RX 9070 XT, gfx1201, beside the miners, lock-free): 82b19cbde8557ea5 at 01:16:14 BST, equal to the kit e6c088bb's on Metal, Apple OpenCL and CUDA, self-test PASS, the v4-genesis control 892b6d55a7ddcfcb PASS; the 0.3.24 kit stands on four platforms; Intel waits on PC 2 (held until main's word, since the 0.3.23 take 3 never ran there); PC 1's queue continues with the CA4 unlocked rows. The kits row reads: Metal, Apple OpenCL, CUDA, AMD equal; Intel not measured tonight. THE UPDATE-RETURN LANE'S THREE READINGS (01:17 BST, from the live manifest and the intake): (1) 0.3.23 take 3 (install-close-23 4ad6c199) never reported; the live manifest igneum-app-latest.json reads 0.3.23 published 20:37:44Z with platforms = {mac} only, NO Windows entry, so neither PC has anything to take through its update path; PC 2's app run is still take 1's relaunch from 21:08:43Z (997 uploads, last 00:16Z); (2) PC 1 will not take 0.3.23 unattended tonight for want of a Windows entry; its run win-ae432dc7-20261007-160110 (0.3.20) never restarted (2,376 uploads, last 00:16Z), mining 18.96 MH/s on the 9070 XT; when a Windows entry is published the 0.3.20 engine's OTA takes it with no hand; the 21:41:32Z helper.ps1 write was not the prompt path (0.3.20 writes that file unconditionally), so no screen is owed in the morning for it; (3) the re-probe job (relay/playbooks/pc1-helper-reprobe.ps1 on power-helper-24 69f3c733) waits only on PC 1's exe becoming 0.3.21 or later; the 0.3.20 workaround is cleared to run tonight as a lock-free job so the locked grids go ahead: per grid job, before the first command, empty sweep\cmd.txt, Stop-ScheduledTask and Start-ScheduledTask 'Igneum Power Helper', wait until helper.alive is within 4 s, then write the lines with climbing sequences (in 0.3.20 the skip is the line count at the helper's start, fixed for its life); the helper idle-exits 20 minutes after its last command and the next start must begin over an empty file again; never pad after a command. The coordinator's order to the hash lane on it: the locked grids proceed in the earlier order (the 5080 full grid, the third 5090 pass to the driver's floor, SM-sparse, the two Ember tunes, the hot-table ldcs rows), each with its restore step, under the no-prompt rule; a Start-ScheduledTask that reads the 0x800710E0 refusal again stops the job and reports, nothing escalates. THE LOCKED GRIDS UNDER THE WORKAROUND (the hash lane, 01:2x BST; commit 24f9858e on the mirror): the three lock scripts carry the cleared sequence (empty sweep\cmd.txt, Stop- then Start-ScheduledTask 'Igneum Power Helper', helper.alive within 4 s with a 60 s cap, then dev + command with climbing sequences; repeated before any write when helper.alive is older than 10 s; a refused start 0x800710E0 or no heartbeat stops the lock path with the text on RESULT lines, nothing escalates; no padding; each grid job ends with rgc through the same sequence and the applications clock read back). PC 1's app_version on the v5 bench's start line: 0.3.20 (no Windows 0.3.23 published, nothing to take). The CA4 SM-sparse job run-ca4-pc1-ca4sparse-5090-20261007 runs since 00:20:40Z on the earlier padded script (unlocked rows first, then its 1,300 knee attempt; about 25 to 50 minutes); then in order on the shipper's acks: the 5080 full grid as run-ca3-pc1-v4-eff-5080-20261007-d, the third 5090 pass (1,100 MHz down), the microbench and the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the 5080 grid's knee and best points to the site audit lane for row 17 as read. THE ATTEMPTS CENSUS COMPLETE (adv-accept row 90, 01:34 BST, 20,000 seeds, closing the partial named at 00:00): 42,711 rejected candidates; (a') 83.5 percent, (a) 11.6, (b) 3.0, (c'') 1.1 (459 candidates), constant bit 0.4, saturated 0.3, (c') 0.05, distinct 0.04, lane-constant and bias 0; per-candidate rejection 0.681, flat across attempts 0 to 3 (the halves agree to a tenth of a percent); accepted-attempt mean 2.136, max 28; 0 exhaustions; P(256 consecutive rejections) 2e-43 per seed. The number for spec 1.4.6: under sub-version 3 the per-candidate rejection is 68.1 percent and the expected attempt 2.1. adv-accept's shards run on in the pool's gaps under the mechanical yield; the box-hours cross 8 later tonight. CLASS-V5 LANDED ON BOTH MIRRORS (the v5 lane, 091a0758 at 01:40 UK): the full pre-push gate GREEN at 71 checks (stamp on 48d38493, the last code change); the igneum-pow suite on box 2 (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs byte-identical to the merged crate's export, so e5a4ac5978462156, 7c54302b487340a1, a217c7f698880830 and 82b19cbde8557ea5 hold under master's recipe form, recheck 2, scratch 7, spec_readback 2); spec-constants 28 rows agreeing; identity grep 0 hits. Carried since 61588347: main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2; the 61-row era reading and the class v5 attempts census on the spec, the page and the ledger; AP-F8-3; spec 1.4.7 and 1.8.6 with the constants and id tables; the AMD fingerprint row; the kits branch and master merged; two corrections the proofs found: master's program_id_derivation text lacked the class v5 rung-0 arm (the v5 packs' text named the class recipe while the id was the plain form; the arm added to the TEXT, re-exported, ids unchanged; a post-freeze change on the class-v5 line, so 0.3.25's pairing, never 1c420786's), and the public-export scrub (the founder's name six times on the page, the zone name in three files; gone). Incoming to the page: the Arc fingerprint, F9 and F1. THE MOVE FILE NOT PUBLISHED (the shipper, 01:41 BST): build-1's /fleet/move.json still names commit 2720d8d2 with the 22:30 BST minute; no FETCHED count, no named minute; the fleet lane (ac055d60427caab99) has answered nothing since its 22:4x report (asks at 01:05, 01:16 and 01:41; its task output last written 22:21 BST, its last action a hand read of dn3-g1's proven share), the second dark lane beside the build-server lane (last written 22:36 BST). So 02:00 BST cannot hold; the 02:53 BST ceiling (DAA 32,400) stands only if a signed move file lands at once and the 34 pullers fetch inside forty minutes; main has the clock line with the two options (wake or replace the fleet lane; or a fourth re-cut from a morning minute, the Mac entry standing down with it). The publish record's shape stands: the Mac entry at the minute (staged, DMG 1aa301cc, both folders, armed); the hive and the Windows pairs on main's word; the pairing 1c420786, 091a0758 0.3.25's. Every other gate on dfbd1e10 green and recorded. THE RUNG-0 ARM CONFIRMED (the v5 lane, 01:4x UK): 987e90e8 touches only Program::program_id_derivation, the text in program.json; Program::program_id untouched (the v5 rung-0 plain-form branch since the freeze); the crate at 091a0758 and 1b5684ec (master 35602b30 merged, pushed 01:41 UK) derives every pinned id byte for byte (packs 20 on box 2 comparing all three pinned packs' files including program_id and leaves.bin; spec_readback 2); the shipper told 091a0758 and 1b5684ec are 0.3.25's pairing, 0.3.24 on 1c420786. THE SM-SPARSE JOB (run-ca4-pc1-ca4sparse-5090-20261007, exit 0 at 00:41:53Z, 1,171 s, the 5090 alone, every fingerprint matched, the Power Helper answering every command on the padded write, the card left unlocked at 2,855 MHz): the SM-sparse reading does NOT exist; the research lane's worker ran its base kernel on every variant row (its race line "race 0 ms variant base" on all 48 rows, no NVRTC compile text), so --bench never honoured --variant sp-w32; the sparse rows equal base in rate and drift in watts with the card's heat only; the rerun waits on the research lane's exe honouring the flag. What stands: a repeat of the efficiency pass at two states, 32 s rows, the card alone: v4 unlocked 137.07 MH/s at 465.5 W (0.294 MH/W), at 1,300 MHz 134.26 at 309.9 W (0.433; 155.6 W back for 2.05 percent of rate); v3 unlocked 136.71 at 331.6 W (0.412), at 1,300 134.03 at 219.4 W (0.611; 112.2 W back for 1.97 percent); the v4 premium 133.9 W unlocked, 90.5 W at the knee; the three power fields agree within 0.2 W on every row (power.draw = instant = average on driver 617.14), which settles the field question on PC 1's side and leaves the 5080's 110 W gap to the fleet's rented card's sampler. Next on the shipper's ack: the 5080 full grid (-d) through the cleared helper sequence, the third 5090 pass, the microbench, the seven packs, the two tunes, the hot-table ldcs rows (kit and job at 292fcc75). THE --variant FAULT FIXED (the research lane, counter-asic-4, UTC clocks on 8 October): 00:44 the fix (a --bench with --variant runs the pinned race and installs the named kernel; the RESULT line carries variant=, sparse_blocks=, block_warps=; a served kernel other than the requested one prints variant_not_installed); 00:46 the known-failed test on build-1 against the real class v4 pack, no card (base: race off, 524,288 blocks of 32, "variant base"; sp43-w32: race on, 43 sparse blocks of 32 warps, the rewritten kernel with the nonces argument and the unit function, 43 blocks of 1,024; PASS; before the fix both read the base shape); 00:46 the Windows exe igneum-worker-cuda-ca4sparse3.exe sha256 0ba97edcd5c46a302a7ff5ddd1bbb1e493ca15f64d0757820ed645972df3bb56, mingw exit 0; the commit after 2d0013d1; the hash lane has the sha, the test's lines and the rerun's job shape (the same 48 rows, the race line per row); the op-mix re-weight stays behind the SM-sparse reading, the served 3.4x standing; the clean efficiency repeat in the file's 20.3a (6.6 pJ per counted op). THE SPEC'S LAST CRATE-DEPENDENT SENTENCE CLOSED (the site audit lane, master 56eebc0d at 01:49 BST, gate GREEN on c2c92eab, 71 checks; spec_readback now 3 tests): 1.4.6.4 states dataset_elem in full (the eight operations, the three constants, 32-bit wrapping) with two pinned vectors (dataset_elem(0x00000fed, 0x9E3779B9, 0x7F4A7C15) = 0x5c7dabd2; dataset_elem(0x0fffffff, 0, 0) = 0x7662c1ec) that spec_readback.rs reads from the text and checks against the crate, so part (c) computes from the text alone (34845c47); 1.4.6.5 names the class v2 figures as class v2's and carries the shipped rule's own census sentence (20,000 seeds, 68.1 percent rejected per candidate, the per-part shares, mean attempt 2.1, max 28, 0 exhaustions, 2e-43). The text-derived re-run on this text is the proof it is sufficient end to end (asked of adv-accept-3). THE MOVE FILE STAGED (the shipper, 01:5x BST): id mdfbd-1, commit dfbd1e10, want_digest b1ba7822, both pair slots on build-1's served tarball dfbd1e10-node-lane.tgz (e59ed0e6), at_epoch 0, signed with the fleet key on the Mac and verified against the fleet's public key in the puller's namespace; the read-back on placing it: the served file's id by curl and the first FETCHED on the relay intake; the 34 pullers fetch inside their one-minute timers (27 MB from build-1), the last FETCHED about five minutes after the file, the earliest minute ten after that. THE REAL LATEST-PUBLISH CLOCK: the file alone halts every miner on the restart, because each box's pack gate PAIR_MINER_SHA16 lacks aa8c2978 and the puller does not carry the file's miner sha into the restart environment; so route (A) also needs one ssh line on each of the 34 boxes before the minute with the fleet's tooling (the fleet lane's, or the shipper's on main's word). Absent main's word by 02:15 BST the shipper stands the Mac entry down under the ceiling rule (no app alone on b1ba7822) and 0.3.24 becomes a morning minute with a fourth re-cut. ROUTE (A) STAGED TO ONE COMMAND (the shipper, 01:5x BST): the gate script r0324/move/pair-gate-aa8c2978.py in its scratch (dry run by default, apply on the literal argument, the fleet's own Box helper and label list, nothing restarted); the dry run read 33 of 35 boxes, every one carrying the old gate list with fb147dd1 last and aa8c2978 absent, no env-last override; unreachable dn3-relay and p2-4090-1b (dead Vast proxies; they fall off at the move and rejoin by the pull); the apply about 90 s for the 33 with each gate read back and counted. THE F9/F1 INTERIM (the attack-pass lane, read at 01:5x BST): 71,292 seeds, 0 exhausted, 0 panics, max attempt 30; F1 0 failures at 2 h 23 min; the move's gate reads clear. On main's (A): apply 02:00, the file placed 02:02, the last FETCHED about 02:05, the minute 02:15 BST; main has the clock. Nothing applies before the word. THE SPEC TEXT SUFFICIENT END TO END (adv-accept-3 Q4d, 01:52 to 01:57 BST on build-2 at 16 cores; report section 6.6 on build/adv-accept-3, log 984-textderive-56eebc0d.tsv, every row equal to its Q4c row): the spec text at master 56eebc0d, implemented with nothing from the crate (text.rs: 0 igneum_pow imports; dataset_elem from 1.4.6.4, its two pinned vectors checked at start), reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences on every field; no sentence of the generator or acceptance sections needs the crate; the documentary finding (AP-F8-4, AP-F8-5) closed in full on two measurements; the lane at its end, 3.35 box-hours in all. F9 AND F1 AT 00:59Z (class v5 at 1c420786, pairing e5a4ac5978462156, build-1): F9 73,691 of 100,000 chain-shaped seeds written, 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; the attempt histogram 23,119 / 15,981 / 10,805 / 7,547 / 5,181 / 3,415 / 2,439 / 1,653 / 1,119 / 744 / 529 / 389 / 258 / 152 / 113 / 72 / 54 / 40 / 31 / 14 / 15 / 5 / 2 / 6 / 2 / 4 / 1 at 26 / 1 at 30, r about 0.69; the 10^5 about 01:30Z (02:30 BST). F1: the 10^5 redundancy census at 2 h 28 min under its lease with no end marker (18 minutes on an idle box; under tonight's load no minute named); its panic path live and empty, 0 failures the honest reading. Both land as record lines, then the board's close per item on sub-version 3 and class v5. AP-F8-5 ON TWO MEASUREMENTS (the site audit lane, commit 116e6055, master 5c77a7ac at 02:05 BST, gate GREEN 71 checks): the row carries Q4c (8b834634, 0 of 400 with one crate function, section 6.5, log 983) and Q4d (56eebc0d, 0 of 400 with no crate import, section 6.6, log 984); the public ledger and the ledger page regenerated; nothing open in the spec or the ledger on the audit lane's side. THE 5080 FULL GRID (run-ca3-pc1-v4-eff-5080-20261007-d, exit 0 at 01:54:00Z, 4,118 s; PC 1's dock card alone, driver 617.14, app 0.3.20, mem 14,801 MHz throughout; every lock through the cleared helper sequence, every command answered first time, every fingerprint matched, clocks reset and read back): the knee as a reading: the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes (v4 71.19 of 71.41 MH/s; v3 71.11 of 71.28) and falls 5.2 percent at 900 MHz on v4 (67.66), where the 75-minute budget ended the grid (v3's 900 and below not taken; the drift check skipped); so the 5080's knee sits between 1,000 and 900 MHz, a third of its 2,963 MHz boost, lower than the 5090's 1,300 (84 SMs at 2,960 MHz have more compute headroom per unit of its 960 GB/s than the 5090's 170 SMs per unit of 1,792 GB/s; the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: v4 at 1,100 MHz, 71.20 MH/s at 146.6 W (0.486 MH/W; 106.5 W recovered for 0.29 percent of rate); v3 at 1,000 MHz, 71.11 at 103.7 W (0.686; 66.0 W for 0.25 percent). The v4 premium 83.4 W unlocked (253.1 against 169.7), 41 W at the best points (146.6 against 105.6 at 1,100). Per tier: a 5080 owner on class v4 locked near 1,100 MHz draws 147 W instead of 253 for 0.3 percent less rate (MH/W up 72 percent) and the shadow's residual cost is 41 W. Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 71.41/253.1/0.282 ; 71.28/169.7/0.420 (sm 2,963/2,977); 2850 71.41/229.5/0.311 ; 71.29/155.3/0.459; 2700 71.41/209.6/0.341 ; 71.29/149.2/0.478; 2550 71.41/193.0/0.370 ; 71.29/134.4/0.531; 2400 71.41/176.0/0.406 ; 71.29/128.7/0.554; 2250 71.41/165.6/0.431 ; 71.28/117.3/0.608; 2100 71.38/157.7/0.453 ; 71.28/112.3/0.635; 1950 71.37/154.0/0.463 ; 71.26/111.6/0.639; 1800 71.35/150.3/0.475 ; 71.24/113.4/0.628; 1650 71.33/151.4/0.471 ; 71.22/109.7/0.649; 1500 71.30/149.2/0.478 ; 71.19/110.6/0.644; 1400 71.27/149.6/0.476 ; 71.16/107.0/0.665; 1300 71.24/147.9/0.482 ; 71.14/107.7/0.661; 1200 71.20/149.4/0.477 ; 71.12/104.4/0.681; 1100 71.20/146.6/0.486 ; 71.11/105.6/0.673; 1000 71.19/149.0/0.478 ; 71.11/103.7/0.686; 900 67.66/137.8/0.491 ; not taken. Throttle reason 0x400 (the power governor) on every row, never the clock lock, so the draw floor of about 147 W (v4) and 104 W (v3) from 1,500 MHz down is the memory system plus idle, not the SMs: the clock lever is spent by 1,500 MHz on this card. The three power fields agree within 0.2 W on every row. The site audit lane has the knee and best points for row 17; the bench table's 5080 row takes "71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", class v4 cost "+83 W unlocked, +41 W at the best points", hive core 1100 (the mem clock unchanged) once the fleet's rented-5080 sampler question is closed. Next on the shipper's ack: the third 5090 pass, the SM-sparse rerun on the fixed exe, the microbench, the packs, the two tunes, the hot table. THE NIGHT'S MOVE OUTCOME (the shipper, 02:58 BST): main's word on (A), (A') or (B) did not come (asked 01:41, 01:50, 01:53, 01:56 by the shipper and 01:42, 01:52, 01:5x, 02:00 by the coordinator); the gate script not applied (the dry run's 33 of 35 the only read); the move file not placed (build-1's /fleet/move.json serves m2720-1, 2720d8d2, the 22:30 minute, by curl at 02:56); no move minute; the stand-down under the ceiling rule holds from 02:15 (the shipper's stand-down line at 02:15 was not sent, its miss, the state unchanged); the Mac entry standing, not published (staged on DMG 1aa301cc in both folders, the live manifest at 0.3.23). A FINDING: build-1's Devnet 3 seed (the process on 26631 with JSON RPC 27632, the node lane's DAA reader) is DOWN (no such process; node1-dn3 26671 and the observer 26651 run on 2720d8d2; the node lane's 0.3.24 reader on 28690 runs but answers no DAA by the envelope tried), so the node lane's DAA reads since 25,169 at 00:52:38 BST may have stopped with it; at 1.0 DAA/s the DAA passed 32,400 at about 02:53 BST, the 39,600 floor is lost, and the fourth re-cut is from a morning minute main names (before 12:50 BST, or the three heights move with the floor). Every Devnet 3 node is on the 0.3.23 pin 2720d8d2, digest ba75bf6f (the 22:30 move; dn3-j1 behind its proxy unverified since); nothing of 0.3.24 is on any box or in any manifest. The night's 0.3.24: every gate green on dfbd1e10, the kit on four platforms, the move unmade for want of one word and two dark lanes. THE ATTACK-PASS BOARD'S CLOSE (lane (d), 01:58Z on 8 October; record docs/analysis/attack-pass-2026-10.md on the mirror's attack-pass; box-hours approximate: build-2 about 7 h, build-1 about 9 h plus about 6 h of F6 batches and F2 solvers earlier in the day). F9 so far: 89,301 of 100,000 chain-shaped seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 20: 20, 21: 6, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1; r about 0.69), three chunks on their cores to about 02:20Z; F1 the 10^5 redundancy census at 3 h 22 min on 17 threads, healthy, no end marker, 0 failures on its live panic path. The board: F1 shadow redundancy PASS on sub-version 3 (max 5.078 percent at honest-compiler parity; AP-F1-1 on the v5 list at 3.0 percent), running on v5; F2 mixer round margin PASS effort-bounded (no trail under weight 20 to 24 at 2 applications, 29 to 35 at 3, 39 to 47 at 4), not re-run on v5 (the mixer unchanged); F3 chained cache j+1 PASS, not re-run; F4 weak-day census PASS on v4 on the DSP-bound metric with AP-F4-1 reconciled with adv-mixer-2 (median 226, 15 days a century, worst 2050-04-28 at 1.113x), on v5 PASS at 8ca66afa (0 of 2^24 days over 1.1x on both metrics, AP-F4-1 FIXED-AND-PASSED); F5 chip-model sweep FIXED-AND-PASSED (the F2 hour skipped by decision), not re-run; F6 verifier worst case PASS (worst of 10^5 at 8.708 ms half-core; O-1.14 closed, i7-9700K 6.334 ms), not re-run; F7 era draw PASS on all three (0 of 6 re-rolls), not re-run; F8 uniformity FIXED-AND-PASSED on sub-version 3 (60 of 64 under 1.2x; AP-F8-1, 2, 3 closed), PASS on v5 (61 of 64, worst 1.50x, the residue p4, p8, p10; p34 under); F9 edges, hot set, grinding PASS on sub-version 3 (34 of 105,064 edges bounded; grinding +0.004 percent), the exhaustion count running on v5; F10 ladder signal PASS, not re-run (node rule). Findings of the pass, all in-house: AP-F1-1, AP-F4-1, AP-F5-1 (the X9), AP-F8-1, AP-F8-2, AP-F8-3; two operating hazards fixed (AP-H1 the box clean, AP-H2 the shared binary path). The open tail (p4, p8, p10, and p34 on sub-version 3) is named in the public report; no outside party holds it (the attack-pass lane's close wrote "disclosed to the firms", stale wording from before the in-house ruling; its record file is to say "named in the public report"). THE SEED'S DEATH AND THE DAA NOW (the node lane, 03:0x BST): build-1's Devnet 3 seed log /home/build/dn3seed.log ends at 01:09:05Z at DAA 29,732 mid-stream with no stop, shutdown or panic line, so it was killed abruptly (it ran under nohup from a shell, not a unit; no journal names the killer; the OOM record needs sudo the lane lacks); its datadir /home/build/dn3seed/igneum-devnet-3/datadir is intact (13 GB) and it stays down until the shipper says; the lane's reads 25,169 at 23:52:38Z and 28,906 at 00:55:09Z came from it while it lived. The DAA now from node1-dn3 on 28670: 32,659 at 01:57:50Z (the observer 32,660), both on 2720d8d2; the chain passed 32,400 at about 01:53Z, 39,600 lost. The fourth cut in one line: the script on release-0.3.24-node reads the DAA from 28670, sets the floor to the morning minute's publish DAA plus 7,200 rounded up to the next 3,600, commits, pushes both mirrors and dispatches the gate set (about 20 minutes to the pin line, then the fast-time pair about 14); the latest minute before the three heights move with the floor is about 11:50Z (12:50 BST), where the floor reaches 79,200; nothing is cut until main names the minute. A morning item for the box owner: a process on build-1 was killed at 01:09:05Z without a log line while the box carried a load of 400 to 600; the killer (OOM or a sweep's cleanup) is to be read from the journal with sudo before anything long-lived runs there again under nohup. THE BENCH LOG ENTRY (the hash lane): docs/bench-log.md "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080" (both cards' full tables, the knee per card, the best MH per watt points, the premiums at the lock, the lever's limits, the job ids and clocks, the rented-5080 watts note) on the mirror's master as merge 773b93a8 at 02:04:47Z (commit 11c698ad); the audit lane writes row 17's sentence from it. PC 1: the third 5090 pass run-ca3-pc1-v4-eff-5090-floor2-20261007 (1,100 MHz down to 300) since 01:57:03Z, about 28 minutes; then the SM-sparse rerun. ROW 17 AND THE 5080 BENCH ROW (the site audit lane, master 2c5c7f52 at 03:19 BST, gate GREEN on 6eb6fd9b, 71 checks): docs/evidence.md row 17 carries both cards' efficiency passes from the bench-log entry (the 5090's knee, best points and premium; the 5080's 71.41 MH/s at 253.1 W unlocked, 71.20 at 146.6 W at 1,100 MHz, v3 at 1,000 MHz 103.7 W, the premium 83.4 W to 41 W, the knee between 1,000 and 900 MHz, the per-tier reading, the Ember Tune lever), a what-moved table for 8 October, /evidence rebuilt (865a0a5e); site/miner-bench.json's RTX 5080 row states the team's pass as the card's figure ("71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", "+83 W unlocked, +41 W at the best points", hive core 1100 with the memory stock, driver 617.14, the bench-log entry as the source) and keeps the rented-fleet sampler reading with its 110 W gap as the open question; /miners rebuilt at 35 rows (6eb6fd9b); 0 identity hits; nothing deployed, the deploy the morning hand-off. The design pass on ca3-coord (015cc839) now sits behind this master and rebases onto it before its own landing on main's word. THE DESIGN PASS REBASED (the coordinator, 03:2x BST): ca3-coord rebased onto master 2c5c7f52 as the three site commits only (f5b7140c the design pass, 8cc4cbc6 the phone grid, 9ad3fdc9 the six-column row; the two commits already landed through the record branch skipped), site/miners.html rebuilt at each from the merged miner-bench.json so the page carries the 5080's new row ("71.4 stock (71.2 tuned)") under the design; the diff against master is build.mjs and miners.html only; pushed to the mirror (pre-push GREEN); it lands on main's word after the captures, one gate run. ADV-MIXER-3's LINE (read from its report at tip e02297ae, 03:18 BST): queue 17 finished on build-1 at 01:3x BST; Q2 single-bit avalanche at 2^27, k = 2 and 3 on day 20729: 0 holes, 0 cells beyond 6 sigma at band 0.00026, PASS (the k = 1 finding stands as the single-application diffusion); Q2b t-bit avalanche on day 20733 at 2^28: 0 cells beyond 6 sigma at band 0.00018, PASS (k = 2, 3, 4 on 20729 at 2^28 the same); Q3 at k = 8 NOT run (killed at 20:20 BST under the lease rule, not re-queued; k = 2 to 7 clean with 0 deterministic bits on both days), named partial; Q6 the day-20733 SAT ladder: k = 2 and 3 TIMEOUT at the one-hour cap, k = 4 on one build-2 core since 03:05 BST, its cap about 04:05; one pre-emption in its ledger (23:58 BST, 21 minutes of a 2^27 row lost, re-queued); box-hours about 3.0 wall-hours of sweep (build-1 1.9, build-2 1.1) plus about 4 single-core CaDiCaL hours, about 7 with the 20733 ladder. The pass's close with the per-lane table and totals at about 04:05 BST; section 13 on crypto-engage (docs only) merging the current master and going through the gate to the mirror's master so the record cites a master commit. Box 2 at 03:20: adv-accept 87 cores in four shards with three waiting, adv-mixer-3 one core; build-1 load 34, no adv lease. THE DESIGN PASS'S OVERLAP ON THE BOX (the CI steward, 03:33 BST): the 1440 and 390 dark captures of /miners from ca3-coord 9ad3fdc9 taken on build-2 under lease pool 4 (Playwright chromium 1194, the recorded feed; /srv/artefacts/captures/ca3-coord-9ad3fdc9/miners-1440-dark.png 1440 x 4280 and miners-390-dark.png 390 x 9779); the overlap sweep on the same checkout, 390 to 1600 px, light and dark: RED, 3 findings on the change itself: at 1280 px dark and 1600 px light and dark the date span in the lead cell's class v4 line is COVERED by the rate cell (4 of 5 sample points under td.big); 390 to 1024 pass. Cause: the branch's last gate ran on the Mac, which has no browser, so the sweep skipped and read GREEN; on the page the row rule's white-space:nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell from 1280 px up. FIXED at ca3-coord 2ca45001 (the lead cell's rule at the row rule's specificity, max-width 360 px, the class v4 line wrapping with overflow-wrap), rebuilt, pushed; the sweep and the captures re-run on the box before main's word. THE IN-HOUSE PASS'S PATH TO MASTER (the crypto lane, 03:2x BST): adv-accept's box-hours crossed 8 before 02:00 BST and sit near 10 (87 cores in four shards; it sweeps on under the mechanical yield, its reading unchanged); crypto-engage merged master 56eebc0d at 342b6730 (one conflict in funding.md, the pre-public scrub against the rewrite, resolved to the in-house pass with the scrub applied; the founder never named in in-house-pass.md or funding.md), the full gate running, merge-to-master on GREEN; section 13.3: master's igneum-pow moved after the freeze in four files (src/emit.rs and src/generator.rs, the derivation string and its recipe helpers, ids unchanged; tests/derivation.rs and tests/spec_readback.rs), none the hash, so the object the pass bounded is unchanged in every operation the hash performs. THE PASS IN ONE LINE (the crypto lane, 03:2x BST): eight of nine lanes closed, adv-mixer-3 on one SAT timeout (about 04:05 BST), adv-accept sweeping to its 16 box-hour line (9.2 now, the reading saturated at the 1.002x class), adv-cache-2 on one line shard; no break of class v4 sub-version 3; the acceptance's hot-set class closed by the class v5 floor (9 of 9) and its diffuse era-stride class routed to the next class; the weak-day FPGA tail reconciled and closed by a measured redraw rule; the attempts census complete; the spec text proven sufficient by two read-backs; one pod at USD 0.33 in the whole pass, none originated by the lane. THE THIRD 5090 PASS BELOW THE KNEE (run-ca3-pc1-v4-eff-5090-floor2-20261007, running at 02:34Z on its 500 MHz step; the steps lengthen as the rate falls since the batch count was sized from the unlocked rate, about 155 s at 500 against 60 at 1,100; the helper answering every command on the cleared sequence, every fingerprint matched, the 5090 alone). Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 137.09/456.7/0.300 ; 136.79/320.0/0.428 (sm 2,858/2,862); 1100 120.98/275.9/0.439 ; 117.32/198.6/0.591; 1000 110.03/254.9/0.432 ; 106.73/180.2/0.592; 900 97.43/232.7/0.419 ; 94.33/174.5/0.541; 800 86.00/216.3/0.398 ; 83.41/166.6/0.501; 700 75.98/202.7/0.375 ; 73.58/156.4/0.470; 600 65.30/178.2/0.366 ; 63.25/153.3/0.413; 500 53.03/166.5/0.319 ; v3 running. Reading: below the knee the rate falls about 10 percent per 100 MHz on both classes (compute-bound: the shadow and the base program no longer fit the memory wait) and MH per watt falls with it from 1,100 down, so the best point stays where the second pass put it (v4 at 1,200, v3 at 1,300); the driver took every lock down to 500 (the SM clock within 10 MHz), so the floor is below 500 MHz and is not where the optimum lives; the v4 premium below the knee 77 W at 1,100, 75 at 1,000, 58 at 900, 50 at 800, 46 at 700, 25 at 600 (the ALU work shrinking with the clock as the rate does). The exit line, the 400 and 300 rows, the drift check and the restore at its close; then the SM-sparse rerun on the fixed exe (each sparse row reading served= and sparse_blocks=, marked variant_row=FAILED if served as base). F9 AND F1 AT 02:34Z (class v5 at 1c420786, build-1): F9 98,945 of 100,000 seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 18: 39, 19: 19, 20: 24, 21: 8, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1); the last three chunks within minutes of their ends; F1 at 4 h 02 min under its lease, no end marker, 0 on its panic path. The pass record's wording fixed on the mirror's attack-pass at 9474cea8 ("named in the public report"; no "firm", "firms", "escrow", "prize", "paid review" or "Lot" line in the pass record or the ten row records; identity grep 0 hits); the section's merge to master after the two record lines, through the full gate in a detached worktree. THE SECOND SWEEP ON THE DESIGN PASS (the CI steward on 2ca45001, 03:38 BST): the desktop widths pass; RED at 390 px dark only, three findings on the lead cell (the card name and the class v4 line covered by the rate cell), the cause the new 360 px max-width on the phone grid; FIXED at ca3-coord 5158276c (the lead-cell width rule scoped to widths above 1,100 px, the phone grid's lead cell with no max-width), rebuilt, pushed; the sweep and captures re-run on it. F9 PASS ON CLASS V5 (the attack-pass lane, class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, the last chunk written 02:34:54Z): 100,000 of 100,000 seeds drawn through the chain path (era-composed class), 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; histogram 0: 31,454, 1: 21,460, 2: 14,660, 3: 10,263, 4: 7,047, 5: 4,701, 6: 3,297, 7: 2,256, 8: 1,532, 9: 1,027, 10: 702, 11: 509, 12: 365, 13: 216, 14: 153, 15: 103, 16: 80, 17: 56, 18: 39, 19: 20, 20: 24, 21: 9, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1 (first-draw acceptance 0.3145; the mean attempt index 2.185, so 3.185 draws per seed on average; 4,862 seeds, 4.86 percent, at index 8 or above and 255, 0.255 percent, at 16 or above; the 256-attempt cap and the deterministic last resort never reached; the lane's first line read 1.993, a slip it corrected); the exhaustion gate holds for the 0.3.24 move; record docs/analysis/attack-pass/f9-grind.md and the lane (d) section on the mirror's attack-pass. F1 still running (4 h 05 min, 16 cores, 0 on its panic path, no end marker). F9's record on the mirror's attack-pass at 2bcb7e08 (the lane (d) row and f9-grind.md section (d); feature gate GREEN); F1 the one open item before the lane (d) merge to master. THE DESIGN PASS GREEN ON THE BOX (the CI steward on ca3-coord 5158276c, 03:4x BST; build-2 under lease pool 4): the overlap sweep 390 to 1600 px, light and dark, GREEN, 0 findings (the known-failed fixture fired first); the 390 px capture byte-identical to 9ad3fdc9's (the phone shape that passed before), the desktop widths carrying the wrap at 4,640 px tall; the four dark whole-page captures on build-1 under /srv/artefacts/captures/ca3-coord-5158276c/: miners-390-dark.png (sha256 9eec8f27..., 509,158 bytes), miners-1280-dark.png (1b6e636d..., 438,541), miners-1440-dark.png (87387e14..., 445,402), miners-1600-dark.png (d53973cd..., 448,545); the run log /srv/builds/bs-ci-steward/cap-out/run-5158276c.log on build-2. The branch's gate record: a full gate on the Mac skips the sweep (no browser), so the box line is the sweep's verdict for 5158276c; the branch waits on main's word on the look and lands in one gate run. THE IN-HOUSE PASS'S RECORD ON MASTER (the crypto lane): crypto-engage dab0c89f (gate GREEN, 71 checks) landed through merge-to-master.sh --remote build at 03:50 BST as master 00b8cd1b: docs/plans/cryptanalysis/in-house-pass.md section 13 (the roll-up, every lane's reading, the frozen-object note) and funding.md's in-house row and brief, scrubbed under founder-strings-check.sh. AN EXCEPTION OWNED (03:39 to 03:50 BST): the lane's first merge call used the tool's default path, which reads CI on GitHub with gh run list; GitHub is suspended and the rule says never poll it; the tool polled 21 times (each 403, nothing pushed, nothing read); the run's process outlived the task stop and the lane ended it by its pid at 03:50 BST, then used --remote build; the breach is the tool's default against the rule and the lane's for not passing the switch; no state moved on GitHub's side. The coordinator's order on it: merge-to-master.sh's default remote must refuse GitHub while the suspension stands (the CI steward, a gate-side fix with a known-failed self-test), so the rule does not rest on every lane remembering the switch. THE THIRD 5090 PASS CLOSED BY ITS CAP (run-ca3-pc1-v4-eff-5090-floor2-20261007, ended by the 45-minute cap at 02:42:05Z during the 300 MHz step, exit -1, its own finally block never ran; every row taken matched its fingerprint, the 5090 alone): the 500 row's v3 side 51.37 MH/s at 136.4 W (0.377); 400: v4 42.62/152.5/0.280, v3 41.32/131.3/0.315 (sm 390); 300 not taken; no unlocked-end drift check; the driver took every lock down to 400 (the SM clock within 10 MHz), so the floor is at or below 400 MHz. The reading: below 1,300 the rate falls about 10 percent per 100 MHz on both classes and MH per watt falls from 1,100 down (v4 0.439 at 1,100 to 0.280 at 400; v3 0.592 at 1,000 to 0.315), so the optimum stays at the second pass's points (v4 1,200 MHz, v3 1,300) and nothing below 1,100 is worth the knob's time; the v4 premium below the knee shrinks with the clock (77 W at 1,100, 46 at 700, 21 at 400). AN EXCEPTION OWNED: the 5090 sat at the 400 lock (390 MHz, 127 W mining) for four minutes until run-ca3-pc1-clocks-restore-20261008 (02:45:20 to 02:46:30Z, exit 0) started the helper over an empty cmd.txt and sent rgc ("All done"), the card reading 2,880 MHz after; the cause the batch count per step sized from the unlocked rate, so the low steps ran 2.5x longer than planned; the fix in the scripts: the budget check ends the grid with the restore inside the cap, and a probe dev line answered in helper.log counts as the helper up when its heartbeat file stays stale (the restore answered at once with helper.alive stale past 60 s). THE SM-SPARSE RERUN: fetch-ca4-sparse3-exe-20261008 landed 02:49:57Z (sha256 0ba97edc...), run-ca4-pc1-ca4sparse-5090-20261008 published 02:51:15Z on the hash lane's own order (the shipper's acks were for the void host slot); each sparse row reads served= and sparse_blocks= and is marked variant_row=FAILED if served as base; the close about 03:15Z (04:15 BST). THE STEP-BUDGET FIX ON MASTER (the hash lane, merge 9fd8b1d8 at 03:02:03Z on 8 October, commit 0b00c42e, the full gate GREEN): the efficiency pass keeps four minutes of its cap for the restore (every step and lock guarded by the deadline minus four minutes) and sizes each step's batch count from the last rate read for the pack, so a 60 s step stays 60 s as the rate falls; a probe dev line answered in helper.log counts as the helper up when the heartbeat file stays stale (all four lock scripts); the gate check tools/ci/pc1-step-budget-check.sh with the known-failed case first (under the old rule a lengthening grid ends on the cap with no restore; under the new it ends with the restore at 1,500 s of 2,700), wired into pre-push.sh and checks.txt (74 checks). The 5080 Ember tune, the 9070 XT tune pass and the hot-table ldcs rows publish behind the SM-sparse rerun, the microbench and the packs. THE SM-SPARSE RERUN FAILS THE SAME WAY, NOW NAMED (run-ca4-pc1-ca4sparse-5090-20261008, the fixed exe ca4sparse3, started 02:52:48Z): every sparse row served=base sparse_blocks=0 variant_row=FAILED, the worker's own line "RESULT variant_not_installed requested=sp43-w32 served=base race=... variants 1 base only, no race (no other variant named)", no "compile:" text, so NVRTC never saw a rewritten kernel: the variant name is parsed into the request but never added to the race's variant table in this exe; the research lane's emulation test checked resolve and rewrite, not the race list the bench builds (a test of the wrong layer; the known-failed case must be the bench's own race line reading "variants 2"). The rows are base runs; no reading. The queue goes on: the microbench at the rerun's exit (about 03:15Z), the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the SM-sparse question's fourth row stays with the research lane, an exe whose card-free check shows "variants 2" in its race line getting the slot within the minute. CLASS-V5'S F9 ROW PUSHED (the v5 lane, class-v5 1d5e5d23 on both mirrors at 04:04 UK): the page's F9 row (100,000 seeds, 0 exhausted, max index 30, first-draw acceptance 0.3145, mean index 2.185, F9 PASS, the record file named), F1 stated as running with 0 failures (its own commit to follow), the Intel row not measured tonight; master merged twice (2c5c7f52 gated at 5f5e0a5c, full gate GREEN 71 checks at 03:45 UK; 9fd8b1d8 auto-merged and pushed on the hook's light gate, the full gate running on 1d5e5d23); the generated ledger files and the spec-constants check clean on the tree. THE THIRD --variant FIX (the research lane, 03:04Z on build-1 under lease, with the hash lane): the cause of the 02:52Z rows: the race's push looked the pinned name up in the empty order list through the variant lookup, whose on-demand sp path answers for any list, so the sparse variant was "found" and never pushed; the order is now a pure function with membership by name; --list-race prints, with no device, the race order the worker's own option handling builds and whether the rewrite applies: with the job's exact flags "variants=2 names=base,sp43-w32" and "sparse_blocks=43 block_warps=32 rewrite=applied bytes=22261 nonces_arg=1 unit_fn=1" (before the fix variants=1); exe igneum-worker-cuda-ca4sparse4.exe sha256 84846396559004a8df61881c15ecb42fa3fc1010ad99074e0c0b53e81bb1ca3b, the commit on the mirror after 7e9d52a6; the third rerun on the hash lane's queue at the next slot; the two failed runs stay the night's SM-sparse state, the op-mix re-weight held, the served 3.4x standing. THE GITHUB GUARD ON MASTER (the CI steward, tip 2f702735 at 04:05 UK; merges 53773860 and 2f702735, full gate GREEN 71 checks each): fa7e98fe adds the tracked marker tools/ci/github-suspended (suspended-since 2026-10-07T17:02:00Z, removed by main at the cut-over) and two refusals: merge-to-master.sh refuses a GitHub remote (origin by default, or any remote whose URL carries github.com) with one line naming the switch and exit 2 before any gh or git call; the pre-push hook refuses any push to a GitHub remote the same way (the hook reads the remote URL, so a bare git push origin is refused too); known-failed first in both self-tests; the live read on the Mac: merge-to-master.sh --remote origin exits 2, nothing contacted; two follow-ups (9484b988, a08423d4) fix the tool's own --self-test under the real marker. The rule no longer rests on any lane remembering the switch. F1 READ AT 03:05:58Z (the attack-pass lane; the census process itself, not the lease wrapper): state S with 17 threads, 15 cores busy over 45 s, 2 d 19 h of CPU banked over 4 h 30 min of wall, RSS 0.8 to 1.0 GB; computing, not hung. No rows can exist before the end: the harness collects every Report in memory under thread::scope and writes census.csv in one go at the end (no progress print), named as a harness gap in the record. Why fifteenfold against the v4 reference: under class v5 every candidate draw runs the (c''') distinct-index floor over 2^20 (about 1.8 core-s per candidate under the night's load, times 3.2 draws per program, about 5.8 core-s per program before the analysis), so 10^5 programs at 15 busy cores is about 10.7 h of wall, the end about 09:00Z (10:00 BST), nearer the early side as the load fell to 21. Ruling: not killed (a kill loses 4 h 30 min with nothing on disk); the lane (d) section merges to the mirror's master now with F9 and the F1 row reading "running, 03:06Z reading, projected end about 09:00Z", F1's record line in a second merge when it writes; the harness gains a progress line before its next 10^5 run. THE IN-HOUSE ADVERSARIAL PASS CLOSED (04:08 BST on 8 October; an internal adversarial pass, not an independent review; section 14 of in-house-pass.md at crypto-engage c099e818 landing on master through --remote build; every tip read from the mirror at 04:07 with igneum-pow identical to 017e7037 on all nine). Per lane (tip; box-hours; verdict; partial): adv-mixer d2ba3134, about 0.6 plus 1.8 single-core SAT hours, the algebraic structure BOUND, none; adv-mixer-2 2a632579, 0.31, BOUND for every chip, GPU and the verifier with the FPGA LUT-area FINDING (2^-10.8 of days, 15 a century, worst 2050-04-28 at 1.113x) closed by the measured redraw rule, none; adv-mixer-3 981bfff2, about 5.0 wall-hours plus 8 single-core SAT hours, Q1 BOUND (2^32 t uniform at k = 1 to 8, both days and 8 random days), Q2 and Q2b FINDING at k = 1 only and BOUND from 2 to 8 at 2^24 to 2^28, Q3 FINDING at k = 1 and BOUND 2 to 7, Q4 and Q5 BOUND from k = 1, Q6 SAT BOUND (k = 1 in 137 s, k = 2 to 4 timeout), the round margin 70 of 72 per item, partial Q3 at k = 8 not run, multi-bit masks and a MILP bound not attempted, GPU blocked; adv-cache 555c3e42, 0.55, the recompute shortcut BOUND on every row, none; adv-cache-2 91ca5ce1, about 2.25, the line census PASS at 2^35 + 3 x 2^33, the real programs PASS with the Devnet 3 site-0 FINDING, the diffuse era-stride class named (16 of 32 base programs biased under drawn eras against 2 of 32 under R = 29, 8 over 1.2x, worst 1.75x, under 0.1 percent of reads per site, 0 of 61 refused by the v5 floor, AP-F8-6), steering and the 16,384-day scan PASS, the window layer exact and the chip model's partial-store rows overstated up to 2.3x with the verdict unchanged, partial the line shard s2c waiting on build-1 since 23:09 BST; adv-cache-3 9452c0bf, 0.23, the chain-break or skip BOUND on every row with the pebbling optimum under the hold-every-k curve, none; adv-accept c8a98e46, about 9.2 at 03:25 BST running to its 16-hour line, the bypass FINDING confirmed and bounded (9 few-item hot sets in the tail of 408,067 accepted programs, 0 in 20 random, 1.002x at the largest; all 9 refused by the class v5 floor, 7 clean programs falsely refused among the 12 deepest, 3 mild residuals missed), the stand-in gap BOUND, distinguishers BOUND, the attempts census complete, partial the sweep at 408,067 of 10^6; adv-accept-2 92168536, about 9.0 core-hours and 0.3 pod-hours (the one pod), header grinding BOUND by card measurement (+0.09 percent on an A6000) and by tail (3e-7), one 0.1 percent repeat class for the rule's owners, none; adv-accept-3 7826d2b2, 3.3, exhaustion BOUND (P 1.0e-43), the last-resort path FINDING (correctness, unreachable; closed in class v5), steering BOUND (no property over 1.03x at 1 in 1e6 tries), the program id BOUND with the derivation-string FINDING (fixed on master and in the packs), determinism BOUND, the spec text proven sufficient by two read-backs, the era lever BOUND, partial the steering sweep at 975 of 10^5 full-rule seeds. Totals: about 30.4 box-hours of run across the nine lanes (lease waits excluded) plus about 9.8 single-core SAT hours; pod-hours 0.3 on one RunPod A6000, USD 0.33 in all, rented and destroyed by the fleet lane. The verdict: no lane broke the frozen object; the acceptance rule admits two residual classes of address concentration, both under 1.002x to a chip: the few-item hot sets, closed entire by the class v5 floor (9 of 9) at a 2.4 percent clean-rejection cost, and the diffuse era-stride excess the floor does not reach, routed to the next class with its lever; the weak-day FPGA tail reconciled and closed. Already changed by the pass: the derivation string in the shipped packs, spec 1.4.3 to 1.4.6 rewritten and proven text-sufficient, the chip model's partial-store and pebbling baselines corrected, the last-resort path flagged and closed in class v5. Still to come: adv-cache-2's s2c row and adv-accept's final count, appended when they land. CLASS-V5 GATED (the v5 lane): the full gate on 1d5e5d23 GREEN, 72 checks in 347 s (04:1x UK); class-v5 4a162aba on both mirrors at 04:12 UK with the page's F1 line stating the 04:06 reading (computing, not hung; census.csv only at its end; projected end about 10:00 UK); nothing of the lane's pending on a box or a watch. THE LANE (d) MERGE ON MASTER (the attack-pass lane, 399f8c4d at 03:16:35Z, 04:17 BST; attack-pass 4150f66d, full gate GREEN 45 checks on the branch): F9 PASS on 1c420786 (row and f9-grind.md section (d)), the F1 row as ruled (running, the 03:06Z reading, projected end about 09:00Z, 0 on its live panic path, the harness gap named), the in-house wording kept through a conflict with master's older copy, one founder-strings scrub the gate caught on the pass record (the attribution now "The founder's word"). The harness item: the progress line every 1,000 programs and the flushed partial census.csv (temp file and rename) committed on attack-v5-frozen at 18a9c04a, built on box 2, its known-failed test (a 4,000-program census killed by pid at the 2,000 line, 2,000 rows expected) running under lease pool class adv; the verdict and the push follow. THE SM-SPARSE QUESTION, THE THIRD RUN (run-ca4-pc1-ca4sparse-5090-20261008-b on ca4sparse4, 03:23:45 to 03:48:45Z, exit 0): the card-free check on the card's own exe listed the sparse variant (variants=2 names=base,sp43-w32, rewrite=applied), the race ran it, and NVRTC refused the rewritten kernel on every sparse row: "kernel_bound.cu(370): error: identifier "d" is undefined | igneum_hash_bound_unit(d, ou, baseNonc, mas, i, gid);" (the same for sp170, sp85, sp21, sp11), so the race installed base and every sparse row reads served=base variant_row=FAILED. The hash lane's reading to the research lane: the wrapper's call carries the kernel's parameter names cut by one character (d, ou, baseNonc, mas for ds, out, baseNonce, mask), which points at the rewrite's name capture against the PC's CRLF pack text (the Linux check reported a different byte count for the rewritten kernel): the first card test of the rewrite, the finding kept. The base rows a third repeat of the knee pass (v4 137.06 MH/s at 449.7 W unlocked, 134.23 at 301.4 W at 1,300; v3 136.79 at 329.8, 134.05 at 218.0), the card restored each time. The slot returns to the research lane on an exe whose card-free check compiles the rewritten text through nvrtc for sm_120 (on CRLF input). The queue: the microbench run-ca4-pc1-microbench-5090-20261007 since 03:52:14Z (20 probes of 60 s unlocked, then at the 1,300 lock; about 50 minutes), then the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. THE CLOSE'S MASTER COMMIT (the crypto lane, sent 04:55 BST for a 04:14 landing, the forty-minute gap its own): crypto-engage c099e818 (full gate GREEN, 71 checks) landed as the mirror's master 2882352c at 04:14:50 BST; the record cites the roll-up and every lane's reading at 00b8cd1b and the close (section 14) at 2882352c; further landings only for adv-accept's final count and adv-cache-2's s2c row. THE FOURTH --variant FIX (the research lane, 03:55Z on build-1 under lease): the cause was not the line endings: the rewrite's parameter capture wrote the substring length as end minus start where the last index needs plus one, so every argument lost its last character on any input; CRLF would have missed the anchors entirely; the rewrite now strips \r first (the same rewritten bytes from LF and CRLF, 22,266 on both) and the capture is right; the card-free check through NVRTC on LF and a CRLF copy, identical lines: variants=2 names=base,sp43-w32; rewrite=applied; call="igneum_hash_bound_unit(ds, out, baseNonce, mask, iw, gid)" params=6 args=6 names_match=1; nvrtc=libnvrtc.so.12 arch=sm_120 compiled=1 image_bytes=36256; the failed case the 03:23Z card line. Exe igneum-worker-cuda-ca4sparse5.exe sha256 a4550202b301faf22f5329c2ab4fa1c0aa6695dbdaf31c974f316dca2524d7d6, with the hash lane; the commit on the mirror after 3ac5d20a; the slot after the microbench and the packs. The three failures gave three repeats of the knee pass (the v4 premium 133.9 to 145.3 W unlocked, 90.5 W at 1,300 MHz) in the file's 20.3a. ADV-ACCEPT OFF BUILD-1 (04:5x BST, the coordinator's placement rule): adv-accept runs on to its 16-hour line (about 10:15 BST, 10.6 box-hours at 04:54, the reading saturated) in box 2's gaps under the mechanical yield, its build-1 shard ended at the frontier and its waiter withdrawn, so F1's census keeps build-1 (its 10:00 BST projection assumed load 21) until census.csv writes; adv-cache-2's four-minute s2c shard the one exception. Confirmed by lease status at 04:57 BST: build-1 holds F1 (release, 16 cores) and adv-cache-2's s2c (32 cores, its last shard) and nothing of adv-accept's; adv-accept's four holders and waiters on box 2, where the attack-pass lane's flush test waits at 1 free behind them (the same class, no yield case); the coordinator's placement rule: one adv-accept holder ends at its frontier for the flush test (a 4,000-program census, minutes), since adv-accept's reading is saturated and the harness fix gates the morning's F1 rerun class. Done at 04:59 BST: adv-accept's sweep-s05b ended at its frontier at 04:58:50 (46,460 rows kept) and the flush known-failed test took the 16 cores at 04:58:55; the shard re-queued behind it. ADV-CACHE-2 CLOSED (05:0x BST): its last shard s2c ran 04:56 to 04:59 on build-1 (PASS at 2^33 reads, control-level), so the line census totals 2^36 reads over 464 chain days with every statistic at the control's values; final box-hours 2.35 of run (0.08 a duplicate windows run by its build-1 drain, recorded), pod-hours 0; tip bfc3746c on build/adv-cache-2, igneum-pow identical to 017e7037; the biased-site class (AP-F8-6) and the window-layer pricing stand; section 14's row updated on crypto-engage, landing with adv-accept's final count. Eight of nine lanes at their end; adv-accept alone runs to its 16-hour line about 10:15 BST. THE CENSUS HARNESS'S PROGRESS LINE (the attack-pass lane, attack-v5-frozen 18a9c04a on the mirror): the attack-f1 census prints a progress line every 1,000 programs (count, elapsed, running failure count) and flushes a partial census.csv at the same cadence through a temp file and rename; the known-failed test on box 2 under lease pool class adv (binary 14180ef4...): a 4,000-program census killed by pid at the 2,000 line at 04:08:27Z (05:08 BST), census.csv holding exactly 2,000 rows, no tmp file, lease exit 143; PASS (the old harness's known fail zero rows); record f1-shadow.md section 12 on the mirror's attack-pass at c99f147f (riding the F1 record merge); a side reading: 1,000 programs per 286 s on 16 cores, about 4.6 core-s per program, confirming F1's build-1 projection of about 09:00Z (10:00 BST); the running 10^5 census stays on the old binary, every census after it on the new. F1 PASS ON CLASS V5 (the attack-pass lane; class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, 16 cores; census.csv written 04:20Z, 05:20 BST, after 20,774 s of census, 5 h 46 min, earlier than the 09:00Z projection as build-1 emptied): 100,000 of 100,000 programs through the string-seed draw with the (c''') floor; instructions saved min 0.000 percent, mean 0.623, max 4.688 (the worst seed attack-f1/95060: 6,912 to 6,588); chip-view ops saved mean 0.520, max 4.783; programs over 5 percent 0, over 10 percent 0; soundness: differential mismatches 0 of 100,000 (8 random states each), verifier mismatches 0 of 100,000; 0 panics; the histogram of saved in 0.5 percent bins from 0: 55,241, 20,597, 11,762, 9,851, 1,484, 656, 259, 133, 13, 4, 0, 0. Against the v4 10^5 (max 5.078, the AP-F1-1 letter miss): the v5 tip's worst program sits 0.39 points under the 5 percent letter and the top two bins are empty. F1 PASS on 1c420786 by the letter and at honest-compiler parity; the redundancy gate holds for the 0.3.24 move; AP-F1-1's v5 half FIXED-AND-PASSED at this count; record f1-shadow.md section 13 and the lane (d) row, merged to master next. The attack board on class v5 is complete: F4 PASS (8ca66afa), F8 PASS, F9 PASS, F1 PASS; the rest not re-run by rule. CLASS-V5'S F1 ROW (the v5 lane, class-v5 1095eaa8 on both mirrors at 05:24 UK): the page's attack row reads F8 PASS with the known residue, F4 PASS, F9 PASS, F1 PASS on the full 10^5, the rest not re-run by rule; the full gate running on 1095eaa8; nothing else of the lane's open tonight. THE CA4 PACKS ON THE 5090 (run-ca4-pc1-packs-5090-20261008-b, exit 0 at 04:22:54Z, 579 s; the 5090 alone through the installed worker, the lock and reset through the helper, every self-test PASS at both states): the int8 mma tile prototypes' inline PTX compiles under NVRTC 12.8 on sm_120 and matches the CPU reference (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1, mm1430 8e9b7066239d35d1), as do both per-load exports (404cad3b3399f9b3, ee5d7c71180e5ea7), sh256x27 (3d2e8245cc084d07) and the mx8-genesis control (7c28cfb06c5c65a9). Rows (MH/s / W / MH/W), unlocked then at the 1,300 lock: mx8-genesis 137.54/311.0/0.442 then 127.32/213.0/0.598; sh256x27 137.51/462.2/0.298 then 126.93/295.8/0.429; shl256x27 (unsound, an energy reading only) 158.62/472.8 then 145.65/299.4; shl256x27_v2 (unsound) 135.90/448.3 then 126.04/282.9; mm128 137.45/332.9/0.413 then 127.01/217.8/0.583; mm512 137.50/369.4/0.372 then 127.07/235.4/0.540; mm1430 137.45/457.7/0.300 then 126.87/284.5/0.446. Consequences: the rate is memory-bound on every sound pack at both states (within 0.5 percent of the control); the tile premium over mx8 is 21.9 / 58.4 / 146.7 W unlocked for 128 / 512 / 1,430 tiles (0.103 W per tile, linear) and 4.8 / 22.4 / 71.5 W at the lock (0.050 W per tile), so at 1,430 tiles the tile block costs what the ALU shadow costs (151.2 W unlocked, 82.8 at the lock) and the lock halves it the same way; the first per-load export's 15 percent higher rate is its duplicate reads landing in L2 (the unsound construction), the fixed one 1.2 percent under the control. The research lane has the rows for 20.3 and 20.4; the tile class's premium per tile is now a measured number on the 5090 and its Apple cost (35 to 78 percent of rate) the open side. The microbench -b since 04:23:23Z, then the SM-sparse rerun on ca4sparse5, the 5080 Ember tune, the 9070 XT tune pass, the hot table. THE CA4 PROTOTYPES' FIRST SENTENCE ON MEASURED ROWS (the research lane, counter-asic-4 on the mirror after 1428dd3c; sections 20.3 and 20.4): neither prototype beats class v4's premium; the tile block matches it at the same hash rate (mm1430, 11,440 int8 tiles per hash: 146.7 W over class v3 against the ALU shadow's 151.2 W unlocked, 71.5 against 82.8 W at the 1,300 lock, the rate memory-bound within 0.5 percent) and beats class v4's chip edge only at the pessimistic end (about 2.2x against 3.5x), not at k = 1 (2.2x either way), because the 5090's measured cost per int8 MAC (0.091 pJ unlocked, 0.048 at the lock) sits inside what a 5 nm MAC array costs anyone (a claimed test-chip figure), so a chip's k on tile work is at or above about 1 where on ALU work a fixed datapath reaches 0.3 to 0.5; the per-load placement dead as a construction (its energy rows 13 to 14 W under the whole block for the same instructions; the first export 15 percent faster from duplicate reads served by L2). Against the tile block as a class: the verifier (AVX2 0.047 us per tile per unit; mm1430 10.14 ms with the sibling loaded on the box's core, a 0.14 ms miss of the gate; scalar 13x worse; NEON unwritten), the Apple tier (35 percent of rate at 1,024 tiles, 78 at 4,096), the AMD layout unverified. No served number moves; the SM-sparse reading still owed (three failed runs, the fourth exe queued after the microbench); the op-mix re-weight held, the served 3.4x standing. The k column's basis (the research lane, counter-asic-4 after 781cb395): the 1,430-tile point is the one chip-model-v3 5.11's tensor-tile k column was priced at (15.2 set R about 1,430 from the 4090's 0.056 pJ per MAC to carry the ALU shadow's 0.654 microjoules; 11,440 tiles per hash), and the 5090 reads 0.091 pJ per MAC unlocked and 0.048 at the 1,300 lock there, so the column (2.1x at k = 1, 1.6x at k = 1.5) has its GPU-side cost measured at the premium it was priced for (1.067 microjoules unlocked, 0.564 at the lock, against the ALU shadow's 1.10 and 0.652); the Apple cost the open side; nothing served moves. F1'S RECORD ON MASTER (the attack-pass lane, merge 54b896f3 at 04:29:30Z, 05:30 BST; attack-pass 0610892b, full gate GREEN on the branch, pushed on try 2 after a ref race): the F1 row (PASS, AP-F1-1 FIXED-AND-PASSED on v5 at 10^5), f1-shadow.md sections 12 (the flush and its known-failed test) and 13 (the 10^5 record with the worst four programs at 4.688, the attempt histogram, the v4 comparison). Lane (d) complete: F4 PASS (8ca66afa), F8 PASS (61 of 64 at 1c420786), F9 PASS (10^5 seeds, 0 exhausted), F1 PASS (10^5 programs, 0 over the letter, 0 mismatches); both 0.3.24 gate lines PASS on the full 10^5. Box-hours for the lane (d) tail: build-1 F9 ten chunks of 4 cores at about 14,480 s each (about 161 core-hours), F1 16 cores for 20,907 s (93 core-hours), F4 12 cores for 379 s; box 2 F8 64 seeds (the earlier record) and the flush test 16 cores for 3,352 s (15 core-hours, most queued); nothing of the lane's on either box. THE V5 LANE'S NIGHT CLOSED (05:3x UK): the full gate on class-v5 1095eaa8 GREEN, 72 checks in 345 s; the freeze 1c420786 (0.3.24's pairing), the post-freeze line through 1095eaa8 (0.3.25's: AP-F4-1's agreed form, the verified last resort, the record), every proof green on the tip, the attack board on class v5 at F8 PASS with the known residue and F4, F9 and F1 PASS, the kit's fingerprint equal on CUDA, Metal, Apple OpenCL and the RX 9070 XT, the Intel row not measured; nothing of the lane's pending. THE SM-SPARSE READING EXISTS (run-ca4-pc1-ca4sparse-5090-20261008-c on the research lane's fifth exe, exit 0 at 05:12:48Z, 2,219 s; every variant served on the card, served=sp-w32 with sparse_blocks=N, the rewritten kernel compiled under NVRTC on sm_120 and bit-exact, every fingerprint equal to the Mac's; the 5090 alone, the lock and resets through the helper, the drift check equal to the start): a quarter of the SMs (sp43-w32, 43 of 170) holds 98.2 percent of the class v4 rate at the SAME draw (134.58 MH/s at 460.1 W against base 137.07 at 450.8) and 99.8 percent of the class v3 rate at 4 W less (136.55 at 309.8 against 136.77 at 313.9); the draw falls only when the rate falls (sp21-w32: v4 70.75 MH/s at 327.4 W, v3 132.82 at 303.4; sp11-w32: v4 37.34 at 250.9, v3 100.14 at 274.5), and watts minus idle per MH/s never drops below base (v4 2.75 W per MH/s base, 2.87 at sp43, 3.58 at sp21, 4.74 at sp11; v3 1.75, 1.73, 1.73, 2.00); the persistent shape on the full card (sp170-w32) within noise of base; at the 1,300 lock the sparse shapes collapse (v4 sp43 64.3 MH/s at 208 W, compute-bound). CONSEQUENCE: the class v4 premium is the shadow's ALU work itself, not SM-count overhead (150 W at sp43 against 137 W on the full card), so an SM-sparse miner kernel saves nothing and the candidate is dead by the research lane's own rule; the op-mix re-weight stays the open lever, and its served candidate ("2.9x with a core three times better") now has its SM-sparse read: the premium does not move with the SM count, so the re-weight's case rests on the op mix alone and goes to main with that reading. The microbench -c since 05:13:41Z with the pack argument; then the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. RANK 2 CLOSED IN THE CA4 FILE (the research lane, 20.3b, counter-asic-4 on the mirror after 6b21e887): the SM-side power is the work's, not the SM count's (the shadow's ops cost the same on 43 SMs as on 170; idling SMs saves nothing); the number kept: the class v4 premium at sp43 unlocked 150.3 W over v3 at a held rate, equal to the full-card premium, so the premium is the ops' energy whatever carries them; the premium-free floor rests on the operating point alone; the op-mix re-weight's hold is main's to lift or keep, the SM-sparse reading saying nothing against it; the microbench rows still owed. THE OP-MIX RE-WEIGHT: HOLD (the research lane's case for main, 06:2x BST; the SM-sparse row at counter-asic-4 954c4053, section 20.3b): the served sentence stands ("At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block"; the re-weight would move "3.4x" to about "2.9x", the shuffle-and-multiply-heavy shadow raising the chip's k floor from about 0.32 to 0.46). The basis: the re-weight touches only the pessimistic column, a model on both sides (the chip's k floor an estimate from wire and datapath figures, never measured; the GPU's energy per op by family unmeasured until the microbench rows land, the shfl, mul and arx probes being that measurement); the SM-sparse reading says nothing for or against it (the premium is the ops' energy, which both mixes pay); the night's measured finding on bounding k points to the int8 tile block (the same premium at the same rate with a k floor near 1 from the GPU's own tensor core, 0.048 to 0.091 pJ per MAC), of which an ALU re-weight is the weaker version at the same class-change cost (the 95 percent rule, the six gates, a new program stream, Apple paying shfl at 1.91x per op); a reader gains 0.5x on a modelled pessimistic bound and loses nothing measured from the hold; the 2.1x at k = 1 rests on four repeats of the knee pass (82.8 to 90.5 W at 1,300 MHz). The condition that re-opens it: the microbench reading the 5090's shfl and mul rows at or under the add's pJ per op together with a measured chip floor, and then it re-prices against the tile block, not the served line. Main's word lifts or keeps the hold; the coordinator's reading agrees with the hold. THE MICROBENCH ON THE 5090 (run-ca4-pc1-microbench-5090-20261008-c, exit 0 at 05:56:29Z, 2,484 s; the research lane's per-block micro-benchmark, 20 probes ran, 0 skipped or failed, at the unlocked clock and at the 1,300 lock, every probe's checksum equal at both states, the card back at the driver default). Picojoules per counted op as (watts minus the sleep row) over G ops per s, unlocked then at 1,300: the ARX integer path 11.3 then 6.2; int_mul 13.9 then 8.3; mulhi 39.6 then 21.0; prmt 22.3 then 11.5; lop3 24.1 then 13.0; shfl 55.8 then 29.4; fp32 fma 9.2 then 5.2; fp16x2 fma 5.1 then 2.6; int8 mma m8n8k16 4.1 then 2.2; int8 mma m16n8k32 1.36 then 0.83; fp16 mma 3.2 then 1.7; bf16 mma 2.9 then 1.5; fp8 e4m3 mma 1.5 then 0.8; the memory rows per read: L2 chase 2.4 nJ unlocked and 1.4 nJ locked, DRAM chase 10.9 nJ and 8.7 nJ, texture point 2.3 nJ, texture linear 0.19 nJ; the sleep floor 120 W unlocked against 75 W idle (the residency cost, flagged). CONSEQUENCES: (1) the op-mix re-weight's re-opening condition (the 5090's shfl and mul rows at or under the add's pJ per op) is NOT met and is now a measurement: shfl costs 4.9x the ARX op and mul 1.2x, mulhi 3.5x, so the GPU pays more for the heavier mix and the hold on the served 3.4x stands on measured rows, not a model; (2) the tensor-core int8 MAC costs eight times less per counted op than the ARX op the hash is built from (1.36 against 11.3 pJ), the direction a chip cannot beat by as much, which is the tile block's case restated in measured picojoules and the CA4 file's next row. The queue: run-ca3-pc1-ember-5080-20261007 (the installed app's Ember tune on the 5080, the app's own path, not elevated) since 05:57:18Z, about 30 minutes; then the 9070 XT tune pass and the hot-table ldcs rows. A CORRECTION FROM THE MICROBENCH'S TILE ROWS (the research lane, 07:0x BST; counter-asic-4 on the mirror after 954c4053: 15.1a, the corrected 20.3 and 20.4, the first sentence, the ranking): a mma.m8n8k16 tile is 1,024 multiply-adds per WARP, 32 per lane, so a hash does 32 MACs per tile, not 1,024; the lane's 15.2 and 20.3 and the 6 October 4090 figure chip-model-v3 5.11's tensor column was priced on were wrong by that factor. Corrected: the 5090's int8 MAC at the ALU shadow's premium costs 2.9 pJ unlocked and 1.5 pJ at the 1,300 lock (the packs job, 366,080 MACs per hash), the microbench's dependent u8 tile 4.1 and 2.2, the wide s8 m16n8k32 tile at 80 percent of peak 1.36 and 0.83; the 4090's "0.056 pJ per MAC" of new-pow 5.1 is 1.8 pJ. Against a 5 nm MAC array (0.04 to 0.4 pJ per INT8-class MAC, claimed) the chip's k on tile work is 0.03 to 0.3, BELOW the ALU shadow's 0.3 to 0.8: at the same premium the tile block leaves the chip 3.5x to 6.7x where the ALU shadow leaves it 2.1x to 3.5x. So the tensor shadow is the WORSE lever and rank 3 is dead; the 6 October verdict on scheme B stands for the right reason; the coordinator's 07:0x line to main calling the tensor side "the next class's one live direction" is withdrawn by this correction. Chip-model-v3 5.11's tensor column (its premise, a chip's MAC no cheaper than the GPU's, false by 4x to 30x on the public figures) and new-pow 5.1's per-MAC line are to be corrected (the coordinator's next commit); nothing served rests on either. The other rows, pJ per counted op unlocked then locked (the sleep floor 120 and 66 W subtracted; idle 75 and 60): int add-xor-rotate 11.3 / 6.2 (the shadow's 10.8 / 6.4 on the packs job: the two instruments agree); mul 13.9 / 8.3; mulhi 39.6 / 21; prmt 22.3 / 11.5; lop3 24.1 / 13.0; shuffle 55.8 / 29.4 (the card's dearest instruction, 5x the add: the re-weight's GPU side is against it, the hold measured); fp32 FMA 9.2 / 5.2; L2 hit 2.4 / 1.4 nJ per read against a chip's SRAM 0.2 to 0.5 (the hot-table lever dead on the GPU side; the ldcs rows kept as a record); the DRAM dependent read 10.9 / 8.7 nJ per read, the whole card's marginal against the chip memory's 2.0, section 2's floor seen per read. THE NIGHT'S CLOSING SENTENCE ON MEASURED ROWS: nothing on the 5090 reads k above 1; the ALU shadow at the operating point's knee is the floor, 2.1x at k = 1 for 82 to 90 W, measured four times; the two prototypes, the SM-sparse kernel, the hot table and the re-weight are all closed on measured rows. The CA4 file's commits (the research lane): 15.1a at 71fd465b (the microbench row, the residency cost 45 W at the stock clock before any instruction issues), 15.1b the commit after it (the re-weight's re-opening condition not met and measured; for 2.9x to be the honest pessimistic column a chip would have to pay 0.42 to 0.52 of the GPU's cost per shuffle, 22 to 28 pJ for a 32-lane crossbar move, above the wire figure and unmeasured; not a candidate on measured rows); the corrected 20.3, 20.4, the first sentence and the ranking at 71fd465b; the hot-table ldcs rows a record only. The lane closed for the night. THE TWO INTERNAL CORRECTIONS LANDED (the coordinator): chip-model-v3.md 5.11's k-column paragraph carries the dated correction (the tensor-tile column withdrawn; the shipped row unchanged) and docs/analysis/horizon/new-pow.md 5.1's per-MAC prose and the scheme B verdict carry the 32x correction with the reason (a tile is 1,024 multiply-adds per warp, 32 per lane), both citing counter-asic-4-research.md 15.1a at 71fd465b; new-pow's 5.1 table column and its 5.3 chip rows keep their original numbers under the note (the Horizon lane's file; a table rewrite is its own). THE 5080 EMBER TUNE (PC 1, app 0.3.20, 06:05Z, 07:05 UK; run-ca3-pc1-ember-5080-20261007): Tuned 60.3 MH/s at 123 W, 0.489 MH/W, clock_cap 2936, source=climb; read against the clock-lock grid, the app's power-limit climb lands at 0.489 MH/W where the 1,000 MHz lock gave 71.1 MH/s at 103.7 W (0.686), so the core-clock lock is worth +40 percent per watt on the 5080 over the stock climb (and 15 percent more rate): the case for the 0.3.24 core-clock knob shipping. The per-point curve rows were lost to a cast fault in the hash lane's curve line (job exit 1, 386 s; the app unaffected), fixed at 261d7c54. Live on PC 1: run-ca3-pc1-ember-9070-20261007 (the 9070 XT tune, 45-minute cap), then the hot-table ldcs rows. THE KNOB ON release-0.3.24 (the shipper, 07:1x BST): the core-clock knob 74585c91 cherry-picked onto release-0.3.24 at e181f497 with the efficient-point ceiling beside it (the plan-count test updated, b6e2845f; the app gate GREEN 294 + 35 + 8), the DMG re-cutting on it under the lock, the UI lane's drawing of the lock fields asked onto that tip, the measured Ember sentence in the 0.3.24 section with the job ids and the knee rule; the pin dfbd1e10 and the kit e6c088bb stand; the move on main's morning minute. THE 9070 XT EMBER TUNE (PC 1, app 0.3.20, 06:11Z, 07:11 UK): one row only, baseline 18.9 MH/s at 202 W, 0.093 MH/W, the chosen point "80%": the app has no knob on AMD in 0.3.20 (power_pct 0, clock_cap 0, limit 0.0 W), so the tune measures the stock point and stops; the 9070 XT cannot be made efficient by the app today, and at 0.093 MH/W it sits at a sixth of the 5090's locked 0.58 MH/W (the app's stored 5090 curve: 1,390 MHz, 118.6 MH/s at 204 W, 0.580) and a seventh of the 5080's locked 0.686; the AMD watts owed from the G1 ladder are on record from the app's reading, 202 W at 18.9 MH/s (the bench row's watts for the 9070 XT once the sampler question is closed). A morning item for the ledger and the app: an AMD core-clock knob (rocm-smi or ADL) is the only path to a 9070 XT efficiency figure. The job exited 1 on the hash lane's row count (fixed, 43f0918c); the app unaffected. The hot-table kit on PC 1 (fetch done 06:20Z); run-ca4-pc1-hot-ldcs-5090-20261008 publishing, the last PC 1 job on the list; rows when it closes. THE 9070 XT BENCH ROW ON MASTER (the site audit lane, ffb7d8ff at 07:35 BST, commit 47690be7, gate GREEN 72 checks): watts 202 ("202 stock"), mh_s 18.92 ("18.9 (18.8 to 19.2 on the G1 ladder)"), 0.093 MH/W, tuned "no lever: the app has no AMD knob today (an AMD core-clock knob through rocm-smi or ADL is the path, a morning item)", the class v4 cost unchanged (+2 percent of rate, 6 October), the note naming the app's own power reading at the stock point with the date and the status row, Hive values none; /miners rebuilt at 35 rows; no deploy; the audit lane closed for the night. The bench table's AMD watts are no longer owed. THE HOT-TABLE LDCS ROWS (the hash lane; the mirror's master at c09dfee4, 08:12 UK; bench-log entry "8 October 2026, the hot-table packs on the RTX 5090", 36 rows all PASS; run-ca4-pc1-hot-ldcs-5090-20261008b exit 0 in 1,372 s, clocks reset): ldcs equals base everywhere (a dead lever, no ldcs rows owed); the 1,300 MHz lock costs the hot packs 2 percent of rate against mx8's 7.5 while taking a third of the watts off every pack, so the hot family is latency-bound on the table; per watt at the lock hot64k8 reads 0.734 MH/W against the mx8 control's 0.602 (the control matches the v4 grid's 0.60, the two passes agreeing); the research lane has the rows with the resistance question (a cheaper GPU hash is a gain only if the saving sits in the memory path; the microbench's L2 row at 2.4 nJ against a chip's SRAM 0.2 to 0.5 answers it on the chip side). THE PC 1 LIST MAIN SET IS CLOSED: the 5080 full grid, the third 5090 pass, the SM-sparse reading, the two Ember tunes, the hot table, all on measured rows. Still open on the hash lane's side: PC 2's Arc B580 class v5 fingerprint on the shipper's clear (a Windows entry first), and the F8 tail p4/p8/p10/p34 as a Mac measurement under the lock script, held until main lifts the Mac rule for one job (a morning item). MAIN'S MORNING WORDS (09:3x BST on 8 October; the night's silence main's own, recorded as such): (1) the look: the design pass lands now through its gate (ca3-coord rebased onto master 715c79b2 as five site commits, tip 0d212a2a; the box sweep GREEN on the same content), the steward deploys master after it; (2) the floor sentence goes on evidence row 17 as well as /ledger in the exact wording (the audit lane's row); (3) CA4 parked with no live candidate, the record carrying the measured close; the only new work the AMD core-clock knob for the app, a 0.3.25 item on the update-return lane; (4) the F8 tail p4/p8/p10/p34 on the Mac: the Mac rule lifted for that one job, one at a time, a few minutes, the hash lane running it now; (5) the move: the shipper has route (A) with the minute 10:45 BST; the Arc B580 job has PC 2 clear and publishes now. THE BUILD-SERVER LANE'S HONEST STATE (09:31 BST): it ran nothing between 22:54 BST and 09:31 (its turn sat on a backgrounded gate chain; the overnight asks reached no tool call); the /miners captures it owed never ran (its export step failed at 22:52, "not a tar archive", a branch commit's git archive over ssh needing the ref fetched on the box side; the CI steward took the captures and the sweep instead); its last master-only deploy dde2dcd2 at 22:49 BST; it deploys master's tip on main's confirmed order after the design pass lands, and builds the 0.3.24 Windows pair and hive on the shipper's word. THE DEPLOY AND THE PAIRS (the build-server lane, 09:3x BST): a master-only deploy of 715c79b2 running from 09:32 with the checks after; master's tip deployed again when the design pass and the row-17 commit are on it, the served sha and minute to the record; the 0.3.24 seed, Windows and hive pairs built on the MORNING pin (the node lane's re-cut from the 10:45 minute) under lease class release, the hands pair the node lane's, the shipper keeping the move and the minute; the seed-class ship path proven on dfbd1e10 first so the morning pin's builds run clean. THE FOURTH CUT (the node lane, 08:33:18Z, both mirrors): 5b673577 on release-0.3.24-node = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else, the three heights staying; the read from build-1's restarted seed on 27632 at DAA 56,329 at 08:33:18Z (1.0 DAA/s overnight); the publish DAA at 09:45Z about 60,630, plus 7,200 is 67,830, the next boundary 68,400, landing about 11:54:29Z (12:54 BST); the floor holds for a publish up to DAA 61,200 (about 09:54:29Z, 10:54 BST); the gate set running since 08:33:20Z (build and consensus at gate priority, the five suites, both canary sets, the fast-time pair about 14 minutes from the artefact), the pin line due about 08:52Z (09:52 BST); the crossing read from build-1's seed after the move (restarted on the pin in the shipper's move); the TESTNET_PARAMS v5-at-0 re-cut after a clean crossing. THE ARC B580 READ (the hash lane, PC 2, 08:35:59Z, 09:36 UK): no fingerprint, match False against 82b19cbde8557ea5; the kit worker fails its self-test on the Arc before any batch ("vector lanes 96 bad of 96 ... device 729ebd46376e2851 expected e552166a03298f7f" on the v5 pack) and 96 of 96 on the v4 control too (device 11bdacb6ee4108c2 expected dfbc8db1c06dacd8), every cache and dataset FNV matching; so the Arc's bound-kernel evaluation is wrong on Intel OpenCL, not class v5; the kit is good on five of six platforms; under main's rule the Intel kit holds out of 0.3.24 with the crossing time 09:36 UK for its page row. The open question, put to the shipper (PC 2 its now): whether the installed 0.3.21 worker's own self-test passes on the Arc with the devnet pack, which decides regression (the kit worker) against never-worked (every Arc rate row on record would then be a FAIL row and the bench table's Intel row a held row). The F8 tail job on the Mac started under the lock script, one seed at a time. THE DESIGN PASS ON MASTER (the coordinator, on main's word; merge 3a4ba893 at 09:39 BST): ca3-coord rebased onto 715c79b2 as five site commits (tip 0d212a2a: the design pass e2674675, the phone grid 592488a4, the six-column row 7c44354f, the lead cell's wrap c11baf30, the width rule scoped to desktop 0d212a2a), site/build.mjs and site/miners.html only, the page rebuilt at each commit so it carries the 5080 and 9070 XT rows under the design; the Mac's gate GREEN (the sweep skipped there), the box sweep GREEN on the same content at 5158276c with the four dark captures under /srv/artefacts/captures/ca3-coord-5158276c/; the build-server lane deploys master's tip after the audit lane's row 17 and Arc-note commit. THE MOVE'S READINGS (the shipper, 09:4x BST): the pin 5b673577's node-lane pair on build-1 (igneumd a3b1a2c9, igneum-miner cfa9f5ca, igneum-pow src 8 paths), its tarball served at fleet/5b673577-node-lane.tgz (c5b85b09, 27,495,480 B); the gate script carries cfa9f5ca and dry-ran at 32 of 35 reachable (dn3-pool-a destroyed by the fleet's waste pass, dn3-relay and p2-4090-1b behind dead proxies); the move file m5b67-1 written to take the pin line's digest and placed at at_epoch 0 the moment that line reads green (about 09:52 BST), the gate line applied in the same minute, the minute the last FETCHED plus ten (the founder's word: no waiting on the clock; 10:45 the ceiling, 10:54 the floor's); the Mac entry re-cut on the knob display (knob-24 2c4dc617 merged, app gate 294 + 35 + 8, UI 88) and published with the hive at the minute; the installed worker's self-test on the Arc with the Intel lane; the eight boxes on bc5945fe with miners off read by the fleet lane and taking the move with the rest. (The fleet lane is answering again this morning.) THE PIN LINE ON 5b673577 (the node lane; every gate green at 08:39:15Z, 09:39 BST): 5b673577 on release-0.3.24-node (both mirrors) = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else; pairing igneum-pow 1c420786; build 08:34Z rc 0 at gate priority (igneumd a3b1a2c96a9767ee..., igneum-miner cfa9f5ca..., /srv/artefacts/0324-5b673577/node-lane); core 175, exec 47, miner 28, p2p-flows 38, pow 19, consensus 134 at gate priority; the Devnet 3 canary set (08:34:58Z to 08:36:38Z): digest cc9026909eddbadb46912513e9b748dffd8e5c3583cd976857a8afdab2d772f9 on igneum-devnet-3 from ba75bf6f, object version 6 stamped, the override file refused, shutdown 573 ms, two empty nodes handshaking on cc902690, the shared-devnet dialler rejected, a 2720d8d2 node refused both ways; the testnet canary b2e856ed unchanged. The floor from the seed's read: the publish DAA at 09:45Z about 60,630, the floor about 11:54:29Z (12:54 BST), holding for a publish up to DAA 61,200 (about 10:54 BST); the fast-time pair's SUMMARY due about 09:55 BST, inside 10:35; no slide to 72,000 needed. A correction: node1-dn3's 28670 no longer answers (its process gone), so the DAA reader is build-1's seed on 27632, restarted 02:00:09Z on the shipper's word and in step with the observer on 28650. dfbd1e10 void as a pin. THE F8 TAIL ON THE MAC, p4 (the hash lane, under the lock script, one seed at a time; the Mac rule lifted by main for the one job): p4 reads 1.2169x over the window model (the gate's 1.2167x reproduced), hot-set clear at every f, the attribution on one site: site 1 (instr 8, source r2, window 2^22 items, offset 1, the last base writer mad at instr 4) carries 1.448 percent of the hot reads against 0.107 flat, index entropy 13.74 of 14 bits, the largest 256-item bucket 4.5x its window expectation, every other site at its flat share; the hottest item 0x4000e7 at 355 reads with no predicted source (no saturation, no lossy writer), so the residue is a window-2 index with a quarter-bit short, not a lossy source; p8, p10 and p34 running (about 90 s each), the four rows and the record line (the bench log or AP-F8-1's tail paragraph) at the close. STANDING RULE FROM THE FOUNDER (09:5x BST on 8 October, after the night: "this cannot happen again"), three parts: (1) every ask any lane sends main carries a default action and a deadline; silence at the deadline means the default, never a stand-down; passed to every lane the coordinator runs; (2) the coordinator mirrors every deadline the shipper holds today (the pin, the apply, the move minute, the publish, the Windows chain, each floor ceiling): if the shipper has not acted within five minutes of its own clock the coordinator sends it the word and tells main; if it is silent for 25 minutes the coordinator takes its next action itself with the shipper's runbook and tells main; (3) a 20-minute heartbeat wakes main regardless of notifications. The night's cost the rule prices: three floors lost (28,800, 32,400, 39,600) and the Mac entry stood down for want of one word while every gate was green; two lanes dark for ten hours. THE MOVE FILE PLACED (the shipper, 09:42:14 BST): m5b67-1 (5b673577, digest cc9026909eddbadb, at_epoch 0, the node-lane tarball c5b85b09) placed and served, its signature verified against the fleet key; the gate line (cfa9f5ca into every reachable box's pack list) applying from 09:42; the minute the last FETCHED plus ten once the fast-time SUMMARY reads PASS (about 09:55); the Intel lane a0aa97b17380bd614 holds the Arc self-test question with the audit lane on its recipients. THE NODE LANE'S OPEN ITEMS UNDER THE RULE (09:4x BST): the crossing read at DAA 68,400 from build-1's seed by 13:10 BST (else the observer on 28650 or the reader on 28690); the TESTNET_PARAMS v5-at-0 re-cut lands through the full gate set at 13:30 BST unless main says otherwise by 13:15 (a red crossing read means no re-cut); any later floor losing its margin is cut from the next named minute by dn3-floor-cut.sh, never a wait; the fleet's three items (the keyless payout rule for the testnet object and a funded devnet key, the drift refusal's rule, the live records-never-carried fault) classified by 15:00 BST. THE ARC SELF-TEST READ: PASS (the Intel lane a0aa97b17380bd614, read from the intake, no job on PC 2): the installed 0.3.21 igneum-worker-opencl.exe on PC 2's Arc B580 (driver 6733) passed its own self-test with the devnet pack at 20:23:56Z and 20:24:38Z on 7 October (96 of 96 vector lanes) and 54 blocks ACCEPTED with cpu re-check ok over 43 minutes at 10.58 MH/s wall (accepted 54, rejected 0 at 21:06:33Z); the shipped 0.3.20 worker read 96 of 96 on every pack on both PCs earlier that day. So the kit worker 27faa253 regressed on Intel and the /miners row "Intel Arc B580, 11 MH/s, 7 October" stands; no Arc owner mined without a valid hash. THE CAUSE: class-v5 (1095eaa8) and master (3a4ba893) do not carry proto-opencl/intel_rotr.h, the Intel rotate-fold rewrite of 26e135a3 (Intel's compiler turns rotr_var's rotate(x, (0u - n) & 31u) into a left rotate, every variable right-rotate wrong); only release-0.3.23 (710e1fea) and release-0.3.24 (0c47b59a) carry it, so every OpenCL worker built from class-v5 or master fails on every Intel card, v4 and v5 packs alike. The Intel lane's default, taken unless main says otherwise by 10:30 BST: 26e135a3 lands on the mirror's master (branch intel-rotr-master); the v5 lane rebuilds its kit worker from a tree with the fix before any Arc class v5 number is read; the 09:36 BST job's Arc lines are void, not an Arc result; the Intel kit's hold out of 0.3.24 stands until the rebuilt kit's fingerprint reads on the Arc. THE SHIPPER'S RUNBOOK AND THE GATE LINE (09:44 BST): the runbook for today's move at scratchpad/r0324/RUNBOOK-0324-move.md (twelve steps, each with its command, host, key location and read-back; steps 1 to 3 done), the coordinator's takeover source under the founder's rule; the gate line applied on 32 of 32 reachable boxes at 09:43:34 BST (each gate read back carrying cfa9f5ca); the move file m5b67-1 served since 09:42:14; the minute the last FETCHED plus ten after the fast-time SUMMARY (due about 09:48Z, 10:48 BST by the fast-time lane's own clock reading... the SUMMARY due about 09:5x BST), inside 10:54. THE RULE PASSED TO EVERY LANE (09:4x BST): the shipper (its runbook written), the node lane (its three defaults armed: the crossing read by 13:10, the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15, any later floor cut from the next named minute), the fast-time lane, the build-server lane (the deploy at 10:00, the three pairs with their minutes), the hash lane, the audit lane, the v5 lane (the kit rebuilt on the Intel fix), the Intel lane (its default at 10:30), the update-return lane (the AMD knob's branch by 12:00), the fleet lane (the FETCHED count by 10:05), the crypto lane (adv-accept's count at 10:15, section 14's last landing by 10:45, both armed on hard clocks), the attack-pass lane (the F8 tail's attribution by 11:00), the research lane (parked, its file at fb61ed4b) and the CI steward (the cut-over ask with a default on the first unsuspended read). THE AMD KNOB OPENED (the update-return lane, 0.3.25; branch amd-clock-25 off release-0.3.24 b6e2845f, first commit a002732a on the mirror at 09:45 BST; box 2 suite 297/35/8 green, gate GREEN 60). Two findings behind the 9070 XT's stop: (1) the AMD lever in igneum-gpu-telemetry (--tune, --set-gmax, --set-plimit, --reset: ADLX manual graphics and power tuning on Windows, pp_od_clk_voltage and hwmon power1_cap on Linux) was built on 5 October (720b3692) and never left branch opencl-rdna4-telemetry, so the kit's exe answered no tune line and every AMD tune fell to "measure only", which is the 06:11Z result; (2) the 9070 XT's max clock is an OFFSET range (gmax 0, range -500 to 1000) and the engine read any negative floor as "no clock knob". The commit takes the tool whole into proto-opencl/gpu-telemetry.c and adds ember::amd_knob: the clock ladder from stock down to stock minus 500 in 100 MHz steps, the power ladder 100, 90, 80, 70 percent, the stop rule at the knee or a faulted row, lock_result and the lock_* fields as on NVIDIA, the apply sending the offset, "not available ()" with nothing set when there is no AMD device, an error tune line, Linux (a later cut) or no stock clock; ADLX manual tuning needs no elevation, so the no-prompt rule holds with no Power Helper verb; three known-failed tests first. The first measured grid needs the kit's igneum-gpu-telemetry.exe rebuilt from this source (MSVC, the ADLX SDK beside the tree) and a 0.3.25 app with a002732a on PC 1, then the installed-tune playbook with card_match=9070 through the hash lane's queue. The lane's default: if the shipper names no 0.3.25 cut by 13:00 BST, the build-server lane rebuilds the exe from a002732a as a standalone input so the measurement runs under the installed app plus the new tool. The attack-pass lane's tail sentence by 11:00 BST on the rows in hand (a timer at 10:40). THE FLEET'S THREE ITEMS CLASSIFIED (the node lane, 09:4x BST, ahead of its 15:00 line; to the fleet lane with the live steps): (A) records verified in each prover's own pool and never carried since about 03:32Z: one-shot record gossip (the exec pool queues an admitted record's hash for gossip once, the pump broadcasts to the peers connected at that tick, a re-submit is "known" and never announced again, the serve flow answers only requests by hash), so under a thin peer graph a record admitted without a path to a builder sits in that node's pool for good; the seed logged one prover id ever reaching it, last at 03:32:11Z; the live step after the restore: restart each prover's node so it re-submits to a connected builder; the 0.3.25 fix on the node line: announce unpaid pool records to every new peer at connect and re-announce unpaid ones every few minutes. (B) p1-5090's "refused on the drift flag (offset -5)": the fleet's own standing.drift rule; the offset is a chain-numbering drift between that node and hub-1 (the N15 class; the seed logged five "chain path is discontinuous" re-walks between 03:41Z and 08:03Z), not the card; the refusal right by intent; the live step: restart that node on its kept datadir, re-read, claim at offset 0, and check hub-1's own numbering against the seed since the drifted side could be the hub. (C) 0.3.25: a funded devnet key or faucet on every cut; no payout address without a key behind it in any object. THE F8 TAIL ATTRIBUTED (the hash lane on the Mac, 08:39:46Z to 08:46:24Z, 09:40 to 09:46 UK, one seed at a time under the measure lock by main's lift of the Mac rule; attack-f8 census at 2^24 nonces, the window-model control, by-site attribution; tree b38b4af6 with igneum-pow frozen at 017e7037): the gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x; the hot-set verdict clear on the windowed control for all four). Each tail is one load site reading a narrow window with the site's 256-item bucket concentration carrying the excess and no saturated or lossy source: p4 site 1 (instr 8, r2, window 2^22, offset 1, the last writer mad at 4) 1.448 percent of its reads into the top 0.1 percent against 0.107 flat, index entropy 13.74 of 14 bits, the largest bucket 4.5x window expectation, the hottest item 0x4000e7 at 355 reads with no predicted source; p8 site 14 (instr 51, r7, window 2^22, offset 2, xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, plus site 6 (instr 33, r3, window 2^23, mad at 30) 0.834 percent, bucket 3.5x, the hottest 0x837de4 at 420 reads, source none; p10 site 8 (instr 28, r0, window 2^22, offset 1, mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x, the hottest 0x4004da at 362 reads, source none; p34 site 1 (instr 13, r3, window 2^23, offset 1, sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x, the hottest 0x800010 at 541 reads, the predicted source "one-one-bit, last writer sub at 5", saturated source 0.0001 percent; every other site in all four at its flat share. THE MECHANISM: a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short on a 2^22 window; p34 0.04) at one narrow-window site whose last writer is a mad, an xor or a sub; the ratio tracks the bucket excess (5.6x gives 1.50x, 3.1x to 4.5x give 1.22x to 1.38x); sub-version 3's (c'') distinct-index ratio passes these at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would catch all four: a per-site largest-256-item-bucket bound (about 2x window expectation at the 2^20 units (c'') already runs), a generator change, so not for the frozen 017e7037 nor for the frozen class v5; a morning item for main with its clean-seed cost unmeasured; the record line on the AP-F8-1 entry (the tail attributed, nothing changed in the stream). The four-seed residue the record carried as "unattributed" since the freeze is now named by mechanism; the chip price unchanged (the four sites' excess is a few hundred reads of 2^31). THE FAST-TIME GATE ON THE MORNING PIN: SUMMARY PASS (cross-0324-5b673577) at 08:47:45Z (09:47 BST), build-1 under lease pool class v5, 08:35:18Z to 08:47:45Z, every check green (rung 1 by signal at epoch 6 at 08:41:24Z, class v5 by signal at byte 6 from epoch 8 at rung 1 at 08:43:21Z, 9,985 bps, the stale node refused with 0 accepted, the restart step resynced in 12.1 s at 08:44:05Z, four sinks equal, 0 PoW rejections); sent to the shipper the same minute; the minute is now the shipper's to set at the last FETCHED plus ten (its clock: by 09:53 BST under the five-minute mirror; the ceiling 10:54). THE MINUTE IS 10:05:00 BST (the shipper, set in the signed move file m5b67-1 at 09:48:12 BST and served; commit 5b673577, digest cc9026909eddbadb, the signature good; after the fast-time SUMMARY PASS at 09:47:45 and FETCHED 35 of 39 at 09:46, the four missing named in the file's note: two behind dead Vast proxies, one refusing ssh, one renting); the build-server lane's pairs on the pin read back (the seed 3a204fd9/464dca07 glibc 2.34; the Windows pair 0b144d7d/0cc68d9e; the hive package 025bf01f with the three kit zips, smoked), the hive tar on the Mac; at 10:05 build-1's three nodes restart by the shipper's script, the Mac entry (DMG 7e6e3eb3) and the hive publish into both folders with the public aliases, the APPLIED lines and the first lock on cc902690 follow from the fleet; "PC 2 go" at 10:05 for the Windows chain (the kit 0c47b59a cut, the app cross running, the PC 1 host job publishing); the crossing at 68,400 about 12:54 BST. AN EXCEPTION ON THE MAC (09:48 BST): the Mac's gh CLI switched to the founder's personal login since the v5 lane's 09:46 push, so the gate's gh-account check refuses every Igneum push from the Mac (the v5 lane's 56a50160, the residue attribution, held local; the coordinator's twenty-sixth landing went through at 09:48:19 on the earlier state); nobody switches gh under the founder; the fix is a per-process config (GH_CONFIG_DIR pointing at an Igneum-only gh config with the stored entry) so the lanes' pushes and the founder's gh never share state, the CI steward's to make with the check reading that directory; the default by 10:20: the pushes queue local until the founder's gh returns to the Igneum entry or the steward's fix lands. ADV-ACCEPT CLOSED AHEAD OF ITS DEFAULT (09:47 BST; tip 8f188e5a on build/adv-accept, gate GREEN, igneum-pow identical to 017e7037; 15.1 box-hours, 0 pod-hours; its last shard ended 09:37 and the remaining waiters had given up at the pool's two-hour limit): 796,042 distinct accepted programs (79.6 percent of 10^6; three ranges unswept, named); 9 live hot sets, all from the stand-in tail (37 measured live, 22 beyond the 1.2x gate), 0 of 20 random, at most 1.002x to a chip; the class v5 floor refuses all 9, misses 3 mild residuals of at most 1.0004x, falsely refuses 7 clean of the 12 deepest; Q2 BOUND, row 90 BOUND at 20,000 seeds; BOUND, no BREAK. Section 14 updated (adv-accept's row and partial, adv-cache-2's close, the totals: about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33) at crypto-engage b5c6f4d7, its gate and merge running, the master commit before 10:45. All nine lanes at their end. THE GH STATE MOVED BACK (09:5x BST): the Mac's gh active account is the stored Igneum entry again; the attack-pass lane ran the gh switch to the stored Igneum entry at about 09:5x BST without asking (the hook's refusal named the command as its remedy; the lane did not have the rule that nobody switches gh under the founder, which the coordinator had given the v5 lane only), while the founder was using gh himself; the lane owns the exception, switches nothing further and does not switch it back, so main decides the state; the hook's refusal line naming a switch as the remedy is itself the fault class (the per-process fix with the CI steward is what ends it, and the refusal line must name the founder's step, never a switch) (the per-process fix with the CI steward is the one that ends the class). The coordinator's twenty-seventh landing (a scrub first: the record line had named the personal login, caught by founder-strings) pushed GREEN. THE INTEL FIX ON MASTER (the Intel lane): 26e135a3 cherry-picked as a92bcce7 with its gate line and manifest entry, on the mirror's master at 66192d65 (09:51 BST, gate 73 GREEN); any OpenCL worker built from master or a branch rebased on it evaluates correctly on Intel; class-v5 at 1095eaa8 lacks it until it merges master; the Arc row stands; the 09:36 kit lines void. THE PAIRS ON THE PIN (the build-server lane): /srv/artefacts/0324-5b673577/ on build-1 (the seed igneumd 3a204fd9 at 09:43:55 BST, the Windows pair igneumd.exe 0b144d7d and igneum-miner.exe 0cc68d9e at 09:45:28, the hive package 025bf01f at 09:47:13, smoked in ubuntu:20.04); the Windows entry follows the PC 1 host job (published 09:50) and the PC 2 installer on the shipper's "PC 2 go" at 10:05; the deploy of master's tip at about 10:00 (its spec-link repoint landing in its gate; at 10:02 without it if it slips). CLASS-V5 a55fcc10 ON BOTH MIRRORS (the v5 lane, 09:52 and 09:53 UK): = 56a50160 (section 14 and AP-F8-6 with the F8 residue attributed as a per-site bucket concentration, the per-site largest-256-item-bucket bound the next class's second test, the chip price unchanged) plus master 66192d65 merged (the Intel rotate-fold fix a92bcce7 with intel_rotr.h and host.c's igneum_intel_rotr_patch; host.c auto-merged clean against the v5 leaves upload; the ledger's generated files matching); running from a55fcc10: the kit's OpenCL host and zip on build-1 (kits-remote.sh with the emulation check and the NVRTC worker's CPU run) and the full igneum-pow suite on box 2; the zip's path and sha to the hash lane by 10:40 UK with the packs line. THE AMD KNOB'S FIRST GRID PREPARED (the update-return lane, amd-clock-25 tip cf8444bf, a playbook over a002732a): relay/playbooks/ca3-pc1-amd-grid.ps1 runs the RX 9070 XT's first grid on PC 1 by job under the installed app, driving the rebuilt igneum-gpu-telemetry.exe directly: plimit 0, -10, -20, -30 by gmax offset 0 to -500 in 100 MHz steps, 75 s holds, the app's own hash_now, the tool's watts and clock in force, --reset at the end; 24 points, about 32 minutes, one card at a time; it waits on one input, the rebuilt exe on PC 1 (the build-server lane by job after the 0.3.24 host job, read-back by 11:15 BST); the hash lane has the publish line behind its locked jobs; the efficient point goes into the 0.3.25 tuner's ceiling table. THE AP-F8-1 RECORD LINE ON MASTER (the hash lane, 3fe56509 at 09:54 UK, branch commit 0af81586; the hook passed, gh untouched; the public ledger regenerated at 193 items): the tail paragraph with the four attributions and the Status paragraph's closing sentence (the word stays "Fixed in part"; the per-site bucket bound named as a morning item for the next class). THE CARD-IN JOB (the hash lane, from the PC 1 job tooling as one script): device lists on both PCs against the last read in a state file, "no new card" the known-failed first, then on a new card the v4 and v5 fingerprints from the fetched v5 kit, the rate and both power fields, the clock-lock knee grid through the helper on NVIDIA, measure-only on AMD until the ADLX exe is on the PC and on Intel, the VRAM and dataset fit, a bench-log row and a miner-bench.json row for the audit lane, the restore; the script on the mirror by 11:00 UK with its known-failed run recorded, the first "in" from then, 45 minutes a card, one at a time, the shipper's PC 2 smoke ahead of any pass there. Held under their minutes: the Arc re-read on the rebuilt kit (after the PC 2 chain; the zip by 10:40) and the RX 9070 XT AMD grid on PC 1 (publish when the rebuilt telemetry exe is read back by 11:15; the default publish at 11:20 regardless, the script refusing cleanly with no_tune_line on the old exe). THE IN-HOUSE PASS'S LAST LANDING (the crypto lane, 09:55 BST): crypto-engage b5c6f4d7 (full gate GREEN, 71 checks) landed as the mirror's master 9649f51e at 09:54:42 BST; the record cites three master commits: 00b8cd1b (the rule set, the board, the roll-up and every lane's 00:00 reading), 2882352c (the close), 9649f51e (the final section 14: the totals about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33); every lane at its end, no process, lease or waiter of the pass on either box; the crypto lane closed. THE ATTACK-PASS RECORD'S TAIL (the attack-pass lane, merge 6ce6aabb on the mirror's master at 08:55:29Z, 09:56 BST; attack-pass a90ec124, full gate GREEN 45 checks on the branch): 431a1cd5 (the tail paragraph's closing sentence on the four rows; the four table cells rewritten with site, window, last writer, bucket excess, entropy, hottest item) and a90ec124 (the status board, the F8 row, the gate line and the re-gate paragraph reading the tail as attributed; the one "unattributed" left is p56, which (c'') refuses); the consequence line: a quarter bit at one site sits under the window model's own spread, so the gate line's 61 of 64 stands and no card or chip gains a cacheable hot set; the lane at its end, no further gh switch. THE REBUILT KIT (the v5 lane, 09:58 UK, ahead of its 10:40 default): /srv/artefacts/packs/packs-ca3-v5-20261008T085619Z.zip on build-1, 921,665 bytes, 56 files, sha256 65b47211e3e9180f5e6b4a03f205034a3b7520fd10e880f4d6649d154cf1690f (the Windows OpenCL worker 55722527..., built 09:57 UK from the Intel-fix tree); the emulation check and the NVRTC worker's CPU run PASS on v5-dn3-epoch0; the suite on box 2 green (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs, ids and 82b19cbde8557ea5 byte-identical, recheck 2, scratch 7, spec_readback 3); commits a55fcc10, c0d398a1 (the Arc job keeps the host's whole stdout as RESULT lines), 8f481459 (a C99 declaration-order fix the kit build caught) on both mirrors; the Arc re-read with the hash lane through the shipper's PC 2 queue. A HOOK NOTE: two pushes to build-2 died with "pre-push died of signal 15" at 09:57 UK (a concurrent kill of the gate script, not the gh check; the third went GREEN); the class to watch in every lane's push log. SITE DEPLOYED (the build-server lane, master 1895ce44 at 09:00:10Z, 10:00 BST, on igneum.network and igneum.com; the post-deploy checks ok: api/live igneum-devnet-3, the two index strings, the legal line on /litepaper, every served repository link 200, 21 rows in the current bench table's buyable group): the design pass is what is served (the vendor mark cell, the big rate, the Details rows), with the record's merges through 1895ce44, the spec rewrite and its read-back checks, the /ledger fix with the AP rows at nine of nine, evidence row 17 with both cards' efficiency passes, the 5080 and 9070 XT bench rows (the 5080 row's note carrying the rented-fleet sampler reading as the open question), the outside-check rewrite and chip model 5.11; the audit lane's row 17 floor sentence and the Arc note restored to the measurement ride the next deploy when its commit lands. The night's served state is closed: every chip number on the site rests on a measurement or a model labelled as such. ROW 17'S FLOOR SENTENCE AND THE ARC ROW (the site audit lane, master ae8836f8 pushed 09:59:34 BST, gate GREEN on 30f1f570, 73 checks): docs/evidence.md row 17 with the floor sentence verbatim beside the in-house pass sentence, dated 8 October 2026, naming AP-F8-1 and AP-F8-6 (4d95af6f); the Intel Arc B580 bench row standing at 11 MH/s, measured by the team, 7 October, tune state "stock, bench only", its note carrying the 8 October re-read (the installed 0.3.21 worker's self-test 96 of 96, 54 re-checked blocks at 10.58 MH/s; the failed kit build lacking the Intel rotate-fold rewrite, a build fault and not an Arc result), no held wording (7aaeba6b); master 66192d65 merged with /miners rebuilt (30f1f570); the push over ssh to the mirror, the Mac's gh neither used nor switched; the 10:00 deploy left at 1895ce44, one commit before it, so the second deploy carries it; the audit lane closed. THE 0.3.25 NODE BUILD'S SHAPE (the node lane, 10:0x BST; release-0.3.25-node opened from the pin 5b673577 in a second worktree, release-0.3.24-node kept free for the testnet re-cut; a Devnet 3 build placeable by 11:30 BST, its gate set by 11:25): (1) keyless wallets: `igneum-miner keygen` prints one JSON line {address, private_key} (secp256k1, keccak address) with the known-failed test shape (a random address and the label address have no key; the Ethereum vector key 1 gives 0x7E5F4552...; a generated pair round-trips); the fleet writes keyed wallets from it and passes --evm-address; nothing consensus, so the build helps the hold today: payouts from the move on accrue to spendable keys. (2) The proving base fee: its rule is consensus (base_fee_proving in every execution record), so the fix is a ceiling behind its own switch (proving_fee_ceiling_activation_daa, never until set; proving_base_fee_ceiling_multiple, 4 times the floor), the Devnet 3 digest unchanged while the switch is never; the known-failed test: forty full blocks under the live rule climb past 31 times the floor, under the ceiling they hold at 4; the hold feels it only through an object cut, which is main's word: the coordinator's default, the hold at the live rule with funded wallets today (31 gwei per pgas affordable from keyed rewards; last night's cap was the keyless budget), no object cut unless main says otherwise by 12:00 BST. (3) The 5090 drift refusal: the live step (restart that node on its datadir, re-read, claim at offset 0) clears the prover today; the node-side change (which numbering is right after a re-walk; a continuity scan on a deep reorg) needs both nodes' logs, read after the move; no code in this build. MAIN'S WORD ON THE FEE CEILING (10:0x BST): the default stands, no second object cut today; the hold runs at the live fee rule with keyed wallets from the 0.3.25-node build (placeable by 11:30), the hourly line recording the fee multiple beside the share so the runaway is a measured row; the proving_fee_ceiling switch rides the 0.3.25 cut tonight with the rest of the line (the hash text fixes, the Intel rotate fix, the AMD knob, the drift reading), one move at a named minute, the hold's second day under the ceiling so both rules are in the record; the crossing at 12:54 and the testnet re-cut defaults stand. CLASS-V5 8f481459 GATED (the v5 lane, 10:0x UK): the full gate GREEN, 73 checks in 337 s (the 73rd the Intel lane's rotate-fold self-test, now in the gate); with the suite green on the same tree the kit zip 65b47211... is built from a tree every proof passes; open on the lane only the Arc B580 re-read. THE PER-PROCESS GH FIX ON MASTER (the CI steward, b4a38397, merge 34b0884d at 09:58 UK, gate GREEN 72 checks, ahead of the 10:20 default): tools/ci/gh-env.sh sets GH_CONFIG_DIR=~/.config/gh-igneum for the gate, the hook, merge-to-master.sh and ci-state.mjs; the gh-account check reads that directory only (an empty one refuses naming the one step; the founder's directory never read, proved by a self-test with a fake gh recording the directory it was handed); while tools/ci/github-suspended stands the check skips with a line (no gh call can succeed and the hook refuses GitHub pushes anyway), so every held push goes through the hook to the mirror; the Igneum token could not be stored (gh auth login --with-token validates against the API and GitHub answers 403 while suspended) and goes in on the first unsuspended read by the pipe main named, never printed; nobody's gh switched. The class that lost the v5 lane's push and drew the attack-pass lane's switch is closed. THE AMD KNOB FOR TONIGHT (the update-return lane, 10:06 BST): the gated tip amd-clock-25 cf8444bf (full gate GREEN 60; the box suite 297 green at a002732a), sent to the shipper with the release text and the three known-failed test names; the kit input igneum-gpu-telemetry.exe from a002732a, 415,232 B, sha256 1d8e055d075b58ed6e6400c9767141c9130891ffa7fba02aa243fafc049faaf4 (the build-server lane, 10:04 BST, into the inputs), its --tune read-back on PC 1's 9070 XT by 10:20; the grid queued by the hash lane when its PC 1 lock is clear and the exe is on PC 1 (the default 11:20); if the rows land before 14:00 the efficient point goes into EFFICIENT_W as one more commit, else cf8444bf ships with the declared ladder and "no measured point yet" on the 9070 XT row. THE 0.3.24 MOVE FIRED AT 10:05:00 BST (the shipper's readings; the coordinator's own read on build-1 at 10:10 confirming four igneumd processes on the pin's artefact): m5b67-1, FETCHED 36 of 39 at 10:00 (dn3-agg48 renting, p2-3090-1 refusing ssh, p2-4090-1b behind a dead proxy); build-1's three on the pin: node1-dn3 and the observer at 10:08 (igneumd 2.1.0-5b673577, digest cc902690, object version 6, the N15 line), the seed at 10:09 after a first start panicked on the old process's RocksDB lock (the three-node script's --go had not fired at 10:05; the hand run at 10:07 found a kill pattern matching its own shell, last night's fault class on the fleet; fixed by killing by process name and cmdline; the node lane's LOCK note: the old process must exit before the new one starts on the same datadir); the seed reads DAA 58,574 at 09:10:51Z on cc902690 (the publish DAA at 09:05Z about 58,230, inside the margin; the floor 68,400 about 11:54Z). The 0.3.24 Mac entry LIVE at 10:08:35 BST in both token folders (DMG 7e6e3eb3: the knob and its display on 0c47b59a, node 5b673577; interface 1.0.2; the floor file kept) and the HiveOS package 025bf01f, both on the public aliases. Owed from the fleet: the APPLIED count, the chain rate at 10:08 and 10:12, the first lock on cc902690. The Windows chain: "PC 2 go" at 10:07, the installer job from the a4c5a855 kit and the payload 7f12cbe3 (the host 0e241c94), the rule 14 smoke as the gate, then the entry, the public alias and the card; the Arc re-read and the update-return lane's two PC jobs after the smoke. The 0.3.25 plan to the coordinator before 14:00 BST. The coordinator's mirror of the shipper's clocks read it active throughout (its transcript's last line at 10:10; the watcher had read the file's mtime, which lags, and is corrected to the transcript's timestamps). After three lost floors and a stood-down night, 0.3.24 is on Devnet 3 with class v5 at DAA 68,400, about 12:54 BST. THE 0.3.25 PLAN (the shipper, 10:1x BST, from the mirror's tips). Branch and pairing: the app line release-0.3.25 from release-0.3.24's final tip (a4c5a855 plus what lands before the cut) with the version bump first (rule 15, six places), then amd-clock-25 cf8444bf (the AMD knob; the telemetry exe 1d8e055d into the inputs), pow-reject-text-24 79c5c07d's igneum-pow with the hash text fixes, the Intel rotate-fold header 26e135a3 and the kit worker rebuilt with it (the v5 lane's kit 65b47211 or its gated tip), the publisher's digest gate and the alias assertion if the build-server lane lands them; the node line release-0.3.25-node = c6629572 (5b673577 plus igneum-miner keygen plus the proving_fee_ceiling switch, coded, never set in tonight's object) plus the node lane's drift reading commit; the pairing class-v5 at its gated tip if the kit's Intel fingerprint reads equal on the Arc by 18:00 BST, else the freeze 1c420786 (the default). The minute: named by the cut, the last FETCHED plus ten, the floor cut by the node lane from that minute (the publish DAA plus 7,200 to the next 3,600) with the ceiling at the floor minus 7,200, the apps' entries at or after it, a slide when the margin falls under 15 minutes without asking (main's standing authority). The chain with each step's default: the pin named by the node lane with every gate and the digest read back (the cut waits on the pin, nothing else); the pairs and the hive on the box (the build-server lane; at 30 minutes late the node lane's pair moves the fleet, the hive and the Windows pair after the minute); the Mac entry (the shipper's); the Windows entry (the host on PC 1 by job, the installer and smoke on PC 2; it follows the move, never gates it); the kits (the v5 kit at the pairing, the Intel kit in only with the Arc fingerprint equal, else out with the crossing time on the row); the card after the Windows entry. The gate set before the file goes: every box suite on the pin, the two canary sets with the mixed-version refusal, the fast-time SUMMARY on the shipped pair, the kaspa-pow pairing read-back, the app crate gate and pre-push on the app tip, the pack-gate line read back on every reachable box, F8 if the pairing moved off 1c420786, the F9/F1 interim at the minute minus five if F8 was rerun. The move's mechanics from today's lessons: the puller takes the pair's miner sha from the move file (the fleet's puller fix), a box with no running box-dn3.sh restarts from a quoted environment (the nine-node fault of 10:05, the fleet's third known-failed shape), build-1's three by process name with the old process's locks released first. Open: the drift reading's commit (not a consensus field by its description); the evening minute from the shipper the moment the pin is green. CARD-IN READY (the hash lane, 10:1x UK; tools/ca3-v4-amend/pc-card-in.ps1 at 3566ecfe): both known-failed shapes recorded on PC 1 (the baseline of 4 cards; "no new card" in 1 s); a relay "in" with the PC publishes one job (55-minute cap) giving the card's key, VRAM and dataset fit, the v5 and v4 fingerprints through the OpenCL kit on every vendor plus the CUDA sub-version 3 row on NVIDIA, the rate with all three power fields, the lock grid through the helper on NVIDIA (300 MHz steps from the maximum, stop at a 3 percent fall) and measure-only rows on AMD and Intel, the app's own row, the bench-log and miner-bench.json rows as RESULT ROW lines, the restore and "next". The Ember tiers' engine half on ember-tiers-25 at 91406944 (local; the push on the box test build's green by 10:45). The Arc re-read's default: 10:50 UK unless the shipper clears PC 2 earlier. MAIN'S WORD ON THE 0.3.25 PLAN (10:1x BST): it runs as written, one addition to the app line: the three-tier Ember Tune, both halves (the hash lane's engine fields and the apply Cmd on ember-tiers-25; the UI lane's tier buttons with rate, watts and the daily saving, sweep on by default at balanced, per-card wired), gated on 0.3.25 before the cut; if either half is not green by 19:00 BST the cut goes without it and the tiers ride 0.3.26, stated in the record; everything else stands, the silence-means-go at 17:00 and the shipper's minute; two readings to main: one when the pin is green, one at the minute. THE FOUNDER'S WORD AT 10:2x BST: push 0.3.25 everywhere as soon as possible; the plan stands in every mechanic, the clock moves: the cut goes the moment its inputs are green, not tonight. The targets: the node line placeable 11:30; the app line assembled by 12:30 (the AMD knob and exe, the hash text fixes, the Intel header and the rebuilt kit worker, the tiers if both halves are green by 12:30, else they ride 0.3.26 and the record says so); the pin green by 13:00; the move at the last FETCHED plus ten but never before the class v5 crossing at 68,400 (about 12:54) has been read clean by the node lane, so the earliest minute about 13:30; Mac and Hive at the minute, Windows behind it within the hour, the card after; the pairing default 1c420786 unless the Arc fingerprint reads equal by 12:30; the defaults and the slide authority stand; main's silence past any of these clocks means go. THE TIERS' UI HALF (the UI lane, 10:52 BST): branch tiers-25 off release-0.3.24 a4c5a855 = the UI commit e6571f60 plus the merge of the hash lane's ember-tiers-25 3408db40 (d3d0704a); the UI tests known-failed first then 73 green on build-2; mock captures of the three states (the measured 5090 and 5080 at Balanced; the install's first minutes with nothing measured and Ember Tune on at Balanced; the M5 Max with no lever as Stock alone with the reason) under ~/Desktop/igneum-previews-2026-10-08/tiers/; the app crate gate and the full pre-push gate running on the merged tip, the gated tip by about 11:15, inside the 12:30 default; tiers-25 fast-forwards onto release-0.3.25 when the shipper opens it from a4c5a855; the live tier numbers come from the engine's own search, not from any table. THE BUILD-SERVER LANE'S CLOCKS (10:1x BST): the 0.3.25 pairs the moment the pin is named (the start script parameterised on the pin); the publisher's digest gate (publish-manifest.sh --node-bin, --network-digest, --move-clock; tools/digest-read.sh) landing on master before 12:30 and riding the app line (the alias assertion not its own); the telemetry exe's --tune read-back on PC 1 DONE at 09:07Z (the 9070 XT tune line: gmax 0 range -500 to +1000, plimit 0 range -30 to +10, factory 1); the second master-only deploy started 10:15 BST on master's tip. A FAULT: PC 2's 0.3.24 Windows installer failed at ISCC because release-0.3.24's .iss still carries the TDateTime line the 0.3.23 fix removed; the one-line fix with the shipper and the update-return lane, the republish on their tip (the Windows entry's default: it follows the move, never gates it). A SPEND TO SURFACE: two new Hetzner boxes provisioning (build-3 HEL1 32 threads, build-4 FSN1 96 threads, in the pool by 10:45), reported by the build-server lane; ordered on the founder's own word in chat ("re order", about 09:5x BST, after he added the credit himself; main clicked the order in his Chrome profile); the standing rule on purchases held; they stay. SITE DEPLOYED AGAIN (the build-server lane, master f98e8e7c at 09:15:33Z, 10:15 BST, on igneum.network and igneum.com; the checks ok): the tip carries ae8836f8 (row 17's floor sentence, the Arc row restored to its measurement) and the record through the twenty-eighth landing; the served state now carries every served change of the night and morning. THE 0.3.25 NODE LINE PLACEABLE (the node lane, 10:1x BST, ahead of 11:30): release-0.3.25-node = c6629572 on both mirrors (the pin 5b673577 plus igneum-miner keygen and the proving-fee ceiling switch coded and never set), pairing igneum-pow 1c420786; every gate green at 09:16:28Z (build 09:13Z rc 0, igneumd 3fadca49..., /srv/artefacts/0325-c6629572/node-lane; consensus 134, pow 19, miner 29 with the keygen test, p2p-flows 38, exec 48, core 177 at gate priority after a first run on a stale file on the box); the Devnet 3 canary (09:13:25Z to 09:15:04Z): digest cc902690 unchanged, byte 6, the override refused, two empty nodes handshaking, the shared-devnet dialler rejected, and the 0.3.24 pin's node handshaking with this build both ways, so the mixed fleet runs through the placement; the testnet canary b2e856ed unchanged. The keygen read-back from the artefact printed an address and a key (the key elided in every transcript and record; a printed private key never enters a message, a log the relay carries, or this file); the fleet writes keyed wallets from it. The defaults: the line's tip at 13:30 BST is c6629572 plus the drift reading's commit only if both nodes' logs reach the node lane by 12:30, else without it; the ceiling-switch field set in the 0.3.25 object from the shipper's minute by the one-go script (the digest moves then; the hold's second day under the ceiling, as main ruled; a re-cut without asking under a 15-minute margin); the crossing line the moment the DAA passes 68,400, a red first; the TESTNET_PARAMS v5-at-0 re-cut at 13:30 unless main says otherwise by 13:15. THE AMD KNOB'S GATED TIP MOVED (the update-return lane, 10:15 BST): amd-clock-25 e2962b89 (full gate GREEN 60, the box suite 298 green) in place of cf8444bf, with the shipper; from the exe's read-back on PC 1: the integrated Radeon's tune line carries every range as a dash and the knob had read it as an offset knob with a one-MHz ladder; it now reads "not available (the driver exposes no tuning interface for this card)", and the 9070 XT's real line (gmax 0, range -500 to 1000; plimit 0, range -30 to 10; stock 3,292 MHz under load) is the test's second half: the ladder 3,192 down to 2,792, the power 70 to 110 percent, offsets on the apply; the grid by 11:20, the efficient point into EFFICIENT_W before 12:30 or the declared ladder ships. THE MOVE'S READ-BACK (the fleet lane, late against its 10:20 minute): APPLIED on the relay at 09:07Z: 24 MATCH by the puller (igneumd 2.1.0-5b673577, digest cc9026909eddbadb, synced; dn3-g1 at peers 24), p1-3080 on cc902690 by 09:10Z; 2 FAILED (dn3-r01, dn3-r02: no saved environment, hand-started yesterday) moved by hand at 09:10:27Z; 9 MISMATCH with no node after the puller's restart (hub-1, dn3-g2, dn3-q04, dn3-q05, dn3-r04, dn3-p02, dn3-p04, dn3-p05, dn3-relay): the saved environment line NET_ARGS=--devnet --devnet-suffix=3 unquoted, so sourcing it ran "--devnet-suffix=3" as a command and the start never reached box-dn3.sh; all nine moved by hand 09:11:58Z to 09:12:24Z with every value quoted, the puller now quoting every value (redeployed 09:16Z on 34 boxes); so 36 of 36 fetched are on 5b673577 and cc902690 by 09:12:24Z (10:12 BST). The first lock on cc902690: checkpoint 1931, block 63510971..., blue score 57,930, at 09:06:32Z on dn3-g1 (4,803 signed, 69.8 percent of active, 66.7 of total); hub-1 logged the same checkpoint at 09:11:43Z after its hand restart and checkpoint 1944 (blue 58,321) at 09:12:39Z. The chain rate: hub-1 read 0 blocks a minute at 09:07Z because hub-1 was one of the nine down; from 09:12Z the tip moves at about 0.4 chain blocks a second as before, and paidShards moves again (11,821, frozen since 03:32Z, to 12,012 at 09:19Z, pool entries 47): carrying resumed with the move, the node lane's one-shot-gossip class confirmed. The proven share at 09:19Z 0.465 cumulative (the hour's own 0.000, the hour being the move); the proving fee 10,000 gwei per pgas last, 50,566 max over 60 blocks (1.0x and 5.1x the floor), the field now on the hourly line. The unfetched: dn3-agg48 (the L40S in its bring-up, applying at its first tick), p2-3090-1 (ssh refused since 21:48Z yesterday, on 2720d8d2 with 4 old-digest peers), p2-4090-1b (its Vast proxy dead, its node down); dn3-relay fetched at 08:48Z and is on cc902690. The eight "bc5945fe" boxes: no such binary (that sha was the reader's own shell); those boxes had no node at all (dn3-g2 dead since 22:49Z, dn3-g1 since 00:46Z, the others overnight, no panic or OOM on any), restarted 08:43Z to 08:53Z, took the move with the rest, and mine where they mine. The keyed-wallet write not started (the 0325 artefact's first mention to the lane at 10:20; box by box after the launch fleet's first boxes are up; the rent running since 09:16Z). p1-5090's drift reads offset -5 again at 09:21Z; hub-1's numbering against build-1's node the next read. Three fault classes for the record from one move: the unquoted environment line (fixed in the puller), the two hand-started boxes with no saved environment, and the eight boxes that had silently lost their nodes overnight with no panic (a watch for a node absent while its box is up is the fleet's next check). THE TIERS GATED FOR THE CUT (the UI lane, 10:20 BST by the Mac's clock): tiers-25 at d3d0704a on the mirror (the UI commit e6571f60 plus the engine half 3408db40 merged, both off release-0.3.24 a4c5a855, a fast-forward onto release-0.3.25): the app crate gate GREEN 299 + 35 + 8 on build-2, the full pre-push GREEN 60 checks with the stamp, the UI tests 73 green known-failed first, the push gate GREEN; the captures under ~/Desktop/igneum-previews-2026-10-08/tiers/; sent to the shipper; two hours inside the 12:30 default; a rebase and re-gate inside the hour if 0.3.25 opens from a later tip. Both halves of the three-tier Ember Tune are in the cut. THE 0.3.25 APP TIP (the shipper, 10:29 BST, two hours ahead of the 12:30 target): e0d4425f on release-0.3.25 (the box gate green): amd-clock-25 e2962b89, tiers-25 d3d0704a (both halves), the Intel header via 9088293a, the node-source pin c6629572; the node pin candidate c6629572 with the digest cc902690 unchanged; the cut list r0325-cut-list.md: the pin named by 13:00, the move no earlier than 13:30 after the 68,400 crossing reads clean; the pairing 1c420786 unless the Arc reads equal by 12:30, the Intel kit on that read. THE 0.3.25 NODE LINE'S TIP MOVED (the node lane, 7bd2940f on both mirrors at 09:24:03Z, every gate green at 09:29:48Z): c6629572 plus the one-shot gossip fix (unpaid proof records re-announced every 120 s; the class confirmed on the live chain after the 09:05Z move); nothing consensus, the Devnet 3 digest cc902690 unchanged on its canary, the 0.3.24 pin's node handshaking both ways, the testnet digest unchanged; build 09:26Z rc 0 (igneumd 16dee9f1..., /srv/artefacts/0325-7bd2940f/node-lane), exec 49, pow 19, core 177, p2p-flows 38, miner 29, consensus 134 at gate priority; it replaces c6629572 as the placeable keygen build and as the tip the ceiling-field cut lands on; the shipper has the line. The drift item is off this line: the fleet's reads were shared-devnet reads (hub-1's node on 26790 at chain block about 190,900; Devnet 3 at 25,900; both answering chain id 4463 below the floor), p1-5090 a shared-devnet prover, and the three numberings at one hash are the snapshot-inherited class (build-1's node1 itself resumed from a snapshot); the fleet rents a fresh-walk node under its standing ceiling to settle which numbering is right, hub-1's restart held until then, the loader change (re-number the resumed range against the DAG) after that read. THE 0.3.25 PAIRS ON 7bd2940f (the build-server lane, from 10:33:11 BST on build-1 under lease class release, /srv/artefacts/0325-7bd2940f/: the seed about 10:36, the Windows pair about 10:38, the hive package with the three kit zips about 10:41, each minute to the shipper and the coordinator); the c6629572 pairs already built (seed f913e3e7, win 42d0dd57, hive 14d86245) stand in their own folder and are not the cut; the publisher's digest gate on master since 10:17, riding the 0.3.25 app line. THE RE-POINTED APP TIP (the shipper): 92f004f1 on release-0.3.25 (e0d4425f plus the node-source pin to 7bd2940f), the push gate GREEN at 10:32 BST, the box gate GREEN at 10:33:25 (303 + 35 + 8); the cut list's pin candidate 7bd2940f; the kit re-cut from 92f004f1 and the pairs on 7bd2940f's artefact with the build-server lane; the Mac node pair and the DMG rebuilding on 7bd2940f under the lock from 10:32:31; the 13:00 pin and the 13:30 earliest minute standing. The 0.3.25 inputs are all green at 10:33 bar the pin's own gate set and the crossing. A SWEEP FINDING FROM MAIN (10:4x BST): on a rented, power-capped RTX A4000 (114 W cap) class v5 reads 26.0 MH/s against v4's 31.4, 17 percent under, the fingerprint equal; the A100 1.3 percent under; every uncapped consumer card level: v5 costs more compute per hash and a compute-limited card pays, which is what a knee lock makes of a card. Two orders with readings by 12:30: (1) the hash lane sends the 5090's v5 pack rows at the 1,300 lock against v4 at the same lock, and the 5080's if they exist; if v5 at the knee loses more than 2 percent, the knee is re-found under v5 and the tiers table says so; (2) the tiers' engine half: a class change (the chain's program class flipping) invalidates the stored tiers and re-runs the search within ten minutes of the crossing, the first-run line saying why; known-failed first (tiers stored under v4 must read "re-measuring for class v5" after the flip, never apply as if current); on 0.3.25 if it fits by the cut, else 0.3.26 with the record saying the v4 tiers may be off by the measured percentage until the re-tune. Per tier: a locked card may lose a few percent of rate at the class v5 crossing until Ember re-tunes; the number is the 5090 row. THE ORDERS PLACED (the coordinator, 10:4x BST): the hash lane's two readings by 12:30 (the 5090's v5 rows at the 1,300 lock against v4 at the same lock, the 5080's if they exist; the knee re-found under v5 if the loss is over 2 percent; the default if the PC 1 queue cannot run it: the A4000's 17 percent stated for a capped card and "unmeasured at the knee on the 5090"; and ember-tiers-25's class key: a class change invalidates the stored tiers and re-runs the search within ten minutes, known-failed first), the UI lane's class-flip state ("re-measuring for class v5", v4 tiers never applied as current after the flip) and knee note by 12:30, the shipper's cut list carrying both on 0.3.25 only if green by the pin at 13:00, else 0.3.26 with the record's sentence that the v4 tiers may be off by the measured percentage until the re-tune. THE 0.3.25 PAIRS ON build-1 (the build-server lane, /srv/artefacts/0325-7bd2940f/): the seed pair at 10:34:44 BST (igneumd c7fc542b, igneum-miner 4494ecc4, glibc 2.34), the Windows pair at 10:36:13 (igneumd.exe 5d1dea23, igneum-miner.exe eee7bdfa), the hive package igneum-hive-0.3.25-7bd2940f.tar.gz at 10:37:49 (sha d977797f..., the three kit zips, smoked in ubuntu:20.04); the kit re-cut from 92f004f1 (sha 676240f6, 424,540 B) staged in both folders, the PC 1 host from it bc8d4f79 (in host.sha256 at the shipper's 24680e1d), the 0.3.25 Windows payload from 24680e1d cutting. Every pair of the cut exists by 10:38; the pin's gate set and the crossing are the only waits. FOUR NEW LANES ON THE FOUNDER'S ORDER (11:00 BST, "build all this today to close this gap"), mirrored by the coordinator as the shipper's clocks are: the explorer (a5ef1d5801084005b; explorer.igneum.network by 16:00), the canonical DEX and the Sepolia certificate verifier (a74a8267813d6ea34; the AMM by 14:00, the swap UI by 17:00, the verifier by 20:00), the builder pages, faucet and grants (adb29da59baf27898; /build and /grants by 15:00, the faucet by 16:00), three reference apps that only work on a proven chain (a2060899d2a27d31c; /light by 16:00, /receipt by 18:00, the Sepolia oracle demo by 21:00); the build-server lane stands up rpc.devnet.igneum.network by 12:00; they do not touch the 0.3.25 cut, the crossing or the fleet, sharing the boxes' lease pools (class measure) and the master-only deploy; a lane silent past 25 minutes gets the word from the coordinator and then main. THE FAST-TIME GATE ON THE 0.3.25 PAIR: SUMMARY PASS (cross-0325-39f127a1) at 09:54:40Z (10:54 BST) on the pair 39f127a1 (the node code and object byte for byte e0644958's; igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 09:42:25Z to 09:54:40Z, every check green (rung 1 by signal at epoch 6, class v5 by signal at byte 6 from epoch 8 at rung 1 at 9,985 bps, the stale node refused, the restart step resynced in 8 s, four sinks equal, 0 PoW rejections); the ceiling's two new fields absent from the 60x file so the ceiling stayed at never there (the node lane's note); to the shipper the same minute; the pin line names e0644958 and its gates. THE FOUNDER'S WORD AT 11:0x BST ("can we add in any more layers? class rotating? things that would render an ASIC useless as soon as it dropped"): the class v6 design opens today as a rotating family, the research lane and the hash lane under the coordinator, the design doc docs/design/class-v6-rotating-family.md by 18:00 BST with the chip-model rows beside each layer (what it does to k and capex for a fixed-function chip and to the per-joule edge for a GPU-like chip; what it costs every GPU tier, Apple included): (1) per-era draws of the class parameters now fixed by release (the mixer round count within the tested margin, the op-mix weights within the measured safe band, the read width, the program length, the shadow placement), drawn from chain state like the program; (2) the state-derived dataset's size tracking chain-state growth with a floor, so fixed-memory silicon ages out; (3) scheduled family epochs by height (every 180 days by default) with no release; (4) the (c''') acceptance floor and the F8-form uniformity test generalised to each era's parameter draw, redraw on failure, so layers 1 and 3 need no per-era cryptanalysis. Per layer: the gate it needs (the family analysed as a family: the attack board's shape over the testnet period), the known-failed test, an honest line on what a fully general chip still gets. No consensus code this week; the document, the numbers and the gate plan. Per tier for the founder tonight: what each layer does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE ARC RE-READ IN ITS CHAIN (the hash lane, 10:57 UK): no clear came from the shipper, so the default ran at 10:50: the rotate-fold kit's fetch (sha 65b47211) published to PC 2 at 10:51:41, the run (run-ca3-pc2-v5-intel-bench-20261008, the v5 lane's script c0d398a1) in the publish chain behind another lane's publish-jobs.sh sign --deploy from the build-server worktree (the publisher serialises); the fingerprint line by 11:15 if the publisher frees inside ten minutes, else the blocking process named by 11:10. Queued on PC 1 behind the same publisher: run-ca3-pc1-v5lock-5090-20261008 (class v5 against v4 at unlocked, 1,300 and 1,200 MHz, the v5 kit's CUDA packs), its rows by 12:30; the AMD grid after it from about 11:25. The class-key work on ember-tiers-25 started; the v6 cost rows by 16:00 taken. THE TIERS' CLASS-FLIP STATE, THE UI HALF (the UI lane, 10:57 BST): tiers-class-25 at d949e274 on the mirror, off release-0.3.25's tip 24680e1d (the shipper having merged tiers-25 d3d0704a into release-0.3.25 at 111dae69), the crate gate GREEN 303 + 35 + 8 on build-1, the full pre-push GREEN 60, the UI tests 74 green known-failed first (the v4 tiers stayed on the buttons after the flip on d3d0704a); after the flip the table reads "re-measuring for class v5" on every button with the start minute or "queued (within ten minutes of the crossing)", the v4 watts never current, the strip's sentence naming the crossing; the knee note under the table when knee_loss_pct is over 2 percent; the captures tiers-flip-dark.png and -light.png; the fields tiers_class, program_class, tiers_remeasure_at, knee_loss_pct (the shape sent to the hash lane at 10:4x; the engine sha by 12:30); the default: the display rides 0.3.25 inert if the engine half is late and lights up on 0.3.26. THE FOUNDER'S WORD AT 11:1x BST: class v6 is DECLARED with the four layers as its spine (per-era parameter draws, the dataset tracking chain state, scheduled family epochs by height, the acceptance floor generalised to parameters), and deep past-and-future research opens now under the coordinator with serious resources ("see if anything can be optimised, added or invented"; reading public research is in-house, nothing paid or asked of anyone outside): four research lanes today, (A) history (every ASIC-resistant proof-of-work and how it fell or held: Ethash and the E3 and Linzhi chips, ProgPoW's review, RandomX and its chip analyses, Cuckoo, Equihash and the Z9, Argon2 and Scrypt and the Litecoin chips, KawPow, Autolykos, Octopus, kHeavyHash's chips; the exact mechanism each chip used and what the design missed, each mapped to Igneum's layers with "does v6 close it" as a sentence and a number), (B) the hardware future five years out (PIM and processing-near-memory, HBM3e and HBM4, LPDDR6, 3D DRAM, CXL memory pools, wafer-scale, chiplets, FPGA with HBM; for each the chip-model k band against a state-sized dataset and dependent random reads, and the one layer that would blunt it), (C) invention (layers beyond the four, each a paragraph, a known-failed test and a chip-model row: data-dependent program graphs, latency-bound dependent reads tied to the shard proof, randomised memory topology per era, VRAM-size ratchets, proof-carrying hashes sampled by the pool, time-locked parameter commitments, and what the lane invents; rejecting what costs GPUs more than chips), (D) the family gate (how a parameter family is cryptanalysed as a family: sampling bounds, coverage, the F8-form and (c''') tests over the parameter space, the attack board's shape over the testnet period, so layers 1, 3 and 4 can be automatic with a proof of what was tested). Resources: all four boxes under lease class measure, PC 1 by job for card rows, the rented fleet for one-shot measurements inside the ceiling. Deliverables: a first synthesis in docs/design/class-v6-rotating-family.md by 20:00 BST (the four layers priced, every finding from A to D with its number, a ranked list of what v6 adds beyond the four, the honest line on what a fully general chip still gets), the full report by 09:00 tomorrow, one line to main per lane as each lands; per tier at 20:00: what v6 does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE 0.3.25 APP TIP AND PIN CANDIDATE (the shipper, 10:58 BST): the app tip 9b93e649 (push gate GREEN; the crate unchanged from e0d4425f; the node-source pin to e0644958 and host.sha256 bc8d4f79); the pin candidate the node lane's ceiling cut e0644958 (digest 1b37cb9d, every gate green 10:53, the fast-time SUMMARY PASS 10:54, the floor at DAA 82,800 about 16:53 BST, a publish up to 14:53 without a second cut); the tiers' class-key halves: the UI lane's tiers-class-25 d949e274 green and inert alone, merged with the hash lane's engine sha the moment it lands (12:30), gated as a pair on the release tip, riding only if green by the 13:00 pin; the 0.3.24 Windows take 2 failed at a new place (Inno stopped the app and copied nothing); the update-return lane owns the fix on release-0.3.25 by 12:30, the default the 0.3.25 Windows entry waiting for a clean take 3 while Mac and HiveOS move at the minute. THE FOUR CLASS V6 RESEARCH LANES SPAWNED (the coordinator, 11:0x BST, each with its worktree, its box resources under lease class measure, its clocks and the rules): lane A history (a603a938582c43ab5; the first cut docs/analysis/class-v6/history.md by 15:00), lane B the hardware future (a4f73e2a6f2d1b757; hardware-future.md by 16:00), lane C invention (a5dfe95ee8c47cd0f; invention.md by 17:00), lane D the family gate (a07a99a3788566af2; family-gate.md by 17:00); each feeds the research lane's synthesis docs/design/class-v6-rotating-family.md by 20:00 (its outline by 13:00; the hash lane's per-tier rows by 16:00); the full reports by 09:00 tomorrow; the coordinator's lane mirror carries their clocks. A HELD PUSH AND ITS CAUSE (11:00 BST): the hash lane's push of ca3-v4-amend was refused at 10:58 by the gh-account hook reading the founder's gh (his personal login active again; nothing switched by any lane); the cause is the branch's own hook, which predates the per-process fix (34b0884d): the hook runs the branch's tools/ci, so every branch older than 09:58 must merge the mirror's master before its next push, under which the check reads Igneum's own gh directory and skips under the suspension marker; the rule to every lane. Live: the Arc re-read on PC 2 (published 10:59:47) and the v5lock job on PC 1 (published 10:53, about 12 minutes). THE CLASS V6 OUTLINE ON THE MIRROR (the research lane, docs/design/class-v6-rotating-family.md on counter-asic-4, the commit after fb61ed4b, pushed 10:5x UTC, two hours ahead of 13:00): section 0 the founder's table (per layer, what it does to a fixed-function chip and to a GPU-like chip on its release day, and the 5090, 5070 Ti and M5 Max columns, measured where the night's rows exist, the 5070 Ti scaled until the hash lane's row); the honest frame on top: the four layers render a FIXED-FUNCTION chip useless on the first era its wired value leaves (one tape-out lives one era) and move nothing for the stored-dataset chip with a programmable core except the core's size and the N5 project it forces; that chip keeps 3.6x at zero premium and 2.1x at k = 1 on a 5090 at its knee. The layer table (sections 1 and 2) names the bands each draw takes and the measured rows that set them: the mixer in {4, 8, 16} (x16 open), the op-mix weights within B = 4 with shuffle and mulhi capped (shfl 55.8 pJ per op), the read width in {1, 4} words (w64 excluded by the 5 October rows), the block shape 64 to 256 (never 1,024), N left to the ladder's signal (an unconditional draw retires the Apple tier at 200,000). Open numbers asked of the hash lane with defaults at 16:00: the 5070 Ti row (the rented 5070 scaled), the x16 mixer's verifier and build (the chip model's estimate), two re-weighted shadow packs for the op-mix band (the microbench arithmetic). Layers 2 to 4 and the gate plan are skeletons with their sources named, filling by 18:00 with the four research lanes' cuts, the synthesis by 20:00. THE FOUNDER'S WORD AT 11:2x BST ("all builders are idle, load them up"): build-1 to build-4 filled now and kept above 80 percent all day under the lease pool, class measure behind the release gates, in this order of value: (1) the class v6 family gate's sampling runs for lane D (the F8-form census and the (c''') floor over the parameter bands: the mixer {4, 8, 16}, the op-mix weights within B = 4 with shuffle and mulhi capped, the read width {1, 4}, the block 64 to 256; thousands of drawn eras, the uniformity and bucket tests on each, so the family document carries measured coverage tonight); (2) the attack families at scale on the 0.3.25 pin candidate's igneum-pow (F8 to 256 seeds, F9 and F1 to 10^6 on the frozen 1c420786, the day-key scan to 2^28) as the record's strengthening lines; (3) the invention lane's candidate layers measured as packs as fast as it writes them; (4) the full suite matrix of the 0.3.25 pin on every box as the pre-pin check; (5) the Windows and hive cross builds and the sweep's reruns; the lease tool's pre-emption giving release-class work the cores when the pin's gates need them; one line to main at 12:00 with the load on each box and what runs there, then hourly only if a box drops idle. THE DRIFT CLASS SETTLED (the node lane, from the fleet's fresh-walk node, a shared-devnet node synced from an empty datadir to 191,441 chain blocks at 10:03:45Z): hub-1 and five standing boxes number the fresh chain exactly; seven boxes carry numbering inherited from an exec snapshot taken on a chain that later re-walked (+2: p1-4090, p1-a5000, pool-1, build-1's node1; +3: p2-3090-2; +4: p2-3090-4; +5: p1-5090 and p2-3090-3), and a restart on the kept datadir does not re-walk (p1-5090 at 09:22Z stayed +5); the cost: a prover on drifted numbering signs statements the hub vetoes, so the seven earn nothing from proving until they re-walk, the drift refusal stopping the waste. The node lane's word to the fleet: p1-5090 first, both snapshot files moved aside so the executor re-walks from the DAG, the re-walk timed and read against the fresh node, then the other six in series, hub-1 untouched, build-1's node1 after the 12:40Z move; if the re-walk reads over two hours the six wait for the node-side fix on the next node line (the loader re-numbering a resumed range against the DAG before serving). THE 0.3.25 PIN CANDIDATE CONFIRMED (the node lane): e0644958 on both mirrors (keygen, the re-announce, the ceiling switch at 82,800 in the Devnet 3 object, digest 1b37cb9d, the 0.3.24 pin refused both ways), every gate green at 09:53:01Z, the fast-time SUMMARY PASS at 09:54:40Z on the same object; the publish ceiling DAA 75,600 (14:53 BST); waiting only on the 68,400 crossing reading clean (about 12:54; the node lane's line the moment the DAA passes it); the shipper names the pin at 13:00; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. LANE C'S FIRST PACK (the invention lane, 11:0x BST by the Mac's clock; its own line read "12:1x", a clock to correct): build-1 takes the igneum-pow build from counter-asic-4 at 5984ffab, then the per-load shadow in its sound form (mx8+shl6912x1: 16 sub-blocks of 432, one pass, the form 20.2a named and never drew) as the first candidate: the acceptance census over 64 seeds and 16 drawn eras against the 16x27 form and the class v4 shape, the pack export, the F8 read at 2^24 and the verifier bench on a leased core, the first read by 13:30; build-2 next for the second candidate (warp-uniform data-dependent block selection); the candidates with no pack form (the VDF commitment, the VRAM ratchet, the pool-sampled witness, the state-tied reads) stay modelled and the 17:00 cut says so; the worktree igneum-wt-v6-invention on class-v6-invention. THE WINDOWS INSTALLER CLASS AND THE 0.3.25 TIP (the shipper, 11:08 BST): the app tip 139c147a (9b93e649 plus install-detach-25 52a34111, packaging/windows and tools/ci only, the crate unchanged; push gate GREEN); the 0.3.24 take 2 class: an installer started under the app's job runner is a child of the engine, and the engine's kill_tree on quit ended it between PrepareToInstall and the copy; the fix re-launches the installer as a one-shot scheduled task outside the job's tree; the 0.3.24 Windows entry skipped; the rule-14 take on PC 2 is the 0.3.25 installer over the running 0.3.21 app, queued ahead of the Arc re-read; the pin candidate e0644958, the DMG 501ba293 staged, the 13:00 pin and the 13:40 provisional minute standing. THE ATTACK FAMILIES AT SCALE (the attack-pass lane, cores held at 11:08 BST, every run under lease pool class measure): box 2 (88 cores): F8 seeds p66 to p257 (192 new, 256 with the gate's p2 to p65) at 2^24 on class v5 at the freeze 1c420786 (the gated binary 0f5c98dc, pairing e5a4ac5978462156; the leaves re-run on 8f481459 if the kit pairing flips), the window-model control, by-site, as three thirds of 64 seeds; box 4 (80 cores held, 16 asked): F9 to 10^6 on 1c420786 (seeds 100,000 to 999,999 in six chunks of 150,000 at 8 threads, four running), F1 to 10^6 class v5 programs on 1c420786 (one census at 40 threads with the progress line and flushed partials, re-drawing the record's first 10^5 on the way as a reproduction check), the F4 day-key scan to 2^28 on 8ca66afa's redraw rule at 8 threads; nothing on build-1 or build-3 (lane D's); the projections: F4 about 2 to 3 hours, F8's 192 seeds about 9 hours, F9's 900,000 and F1's 10^6 about 30 hours each, so the 17:00 default is partials for those two with the lane (d) rows carrying counts so far; any pre-emption by release-class work reported. THE RPC AND THE 0.3.25 PAIRS ON THE PIN CANDIDATE (the build-server lane, 11:0x BST): rpc.devnet.igneum.network up since 11:08 BST (the first of the founder's builder clocks, 52 minutes ahead); the 0.3.25 pairs on e0644958 running on build-1 since 11:06 (the app tip 139c147a), the Windows and hive crosses on build-2, build-3 and build-4 as reproducibility rows at class release by about 12:40; the sweep reruns' list not held by the lane, the default at 12:30: last night's sweep logs on build-1 read for rows that ended without a result line and those rerun at class measure. THE SWEEP RERUNS' LIST (the fleet lane to the build-server lane, 11:1x BST): the fleet ran nothing under the build boxes' lease pool last night (every fleet bench a rented GPU one-shot), so the rows the lease kills cut short are the hash and class lanes' and the build-server lane's default read on build-1 is the right one; the fleet's own rows without a result (A10, A40, A100 40 GB, H100 NVL, H100 PCIe, MI250, RTX 3050, RX 7800 XT, 7900 XT, 7900 XTX, 6900 XT) are provider gaps needing a GPU host, rerun the moment a provider lists one. THE CLASS-FLIP TIERS, BOTH HALVES (the UI lane, 11:13 BST by the Mac's clock, 1 h 47 min inside the 13:00 pin): tiers-class-25 at 081b3ba7 (the display d949e274 plus the hash lane's ember-tiers-25 0a838072, on release-0.3.25's 9b93e649; the field names matched exactly): the crate gate GREEN 305 + 35 + 8 on build-1, the pre-push GREEN 60, the UI tests 78 green known-failed first, the push gate GREEN; with the shipper. A RED ON THE RELEASE TIP, for the shipper and the update-return lane: release-0.3.25's 139c147a is red on one crate test (ota::return_tests::no_relaunch_while_an_installer_runs_and_a_relaunch_when_it_clears, 304 of 305): install-detach's 0c588b09 reshaped the installer's clear step into a multi-line block while the test asserts the one-line literal at app/igneum-app/src/ota.rs:1348; 9b93e649 passes; the fix is the test's literal on the install-detach line; the UI lane built on 9b93e649 so its tip is green alone. A RED FROM THE PIN MATRIX (the CI steward, 11:13 UK): the core suite fails on the pair (the node e0644958 with the app tree 9b93e649): config::params::tests::fast_time_60x_file_is_the_devnet_at_60x panics "override-60x.json lacks the field base_unit_decimals"; the field was added by 0e4ec18a on ca3-v4-node yesterday at 21:45 UK and reached neither master, release-0.3.25 nor the app tip while the node line's test demands it; so every box reads red on core, and the fix is one line on release-0.3.25 (the cherry-pick of 0e4ec18a, or "base_unit_decimals": 8 in infra/fast-time/override-60x.json); sent to the shipper; green so far pow and app on build-1 and build-3; the two new boxes' toolchains read the same as build-1 (Ubuntu 24.04.5, glibc 2.39, the pinned rustc, sccache and lease, no nvcc). The founder's fourth load item paid in its first ten minutes: a red no single-box gate had read. MAIN'S WORD ON THE TWO REDS (11:1x BST): the install-detach fix belongs in 0.3.25 if it can make it, since a Windows install by any path that lets the engine's job runner kill the installer mid-copy is the plug-tune-play fault class (an update a user repairs by hand); the default order: the update-return lane fixes the ota.rs literal by 12:00; if 139c147a plus the fix is green on the crate gate by 12:15 the cut goes from it, else from 9b93e649 with the detach on 0.3.26 and the record saying Windows installs by job stay unreliable until then; the missing 60x field: the CI steward lands the one-line field on master and the release line by 11:45; the pin slides under the shipper's authority inside 14:53. THE DAY-KEY SCAN TO 2^28 (the attack-pass lane; class-v5 8ca66afa's redraw rule, build-4 under lease pool 8 class measure, 379.2 s, census-2p28.md at 10:15Z, 11:15 BST): days with any gain over 1.1x: 0 of 268,435,456 on M1 (median 226), 0 against the mean, 0 on M2, 0 on ROT and RC; the M1 cost mean 225.791, sd 6.073, min 206 (day 27,016 at 1.0971x, the redraw rule's floor: no day under 206 in 2^28), max 258; every weak class on its analytic expectation (ROT any pair summing to 32: 160,354,008 against 161,256,979; RC any zero: 1 against 1.0, at cost 234, no gain; RC with rk = 0: 87 against 72, 1.8 sigma; the two cells under expectation the rule's own refusals). PASS: no chip buys a weak day in the first 735,000 years of days; at most 1.097x on the best day. The row and f4-weakday.md section 10 committed on attack-pass at eabb4b0e, the push held by the branch's old hook (the fix: merge master, under which the check reads Igneum's own gh directory and skips under the suspension marker). THE SWEEP RERUNS' READ (the build-server lane, 11:18 BST): build-1's records hold no hash-lane or v5-lane run the pool cut short (preempt.log: three TERMs all night, every one to an adv-class holder pre-empted by a release gate, not reruns by rule; no reaped.log; builds.jsonl for 18:00Z to 09:00Z 150 rows with no signal end, the non-zero rows the fast-time gate's designed failed cases and build errors; the census and fingerprint suites leaving no builds.jsonl row and no output directory ending without its result); live at 11:17Z the family gate's v5_attempts_census holding 24 cores on build-1 at class measure; the default at 12:30 if neither lane names a run: no reruns, the boxes carrying the e0644958 reproducibility crosses (build-3's Windows pair already read: igneumd.exe 4b0c3aeb, igneum-miner.exe b3da4088) and the gates. The founder's fifth load item is therefore the crosses, not reruns. The attack-pass branch merged master and pushed (460fd9fa, the F4 2^28 row and f4-weakday.md section 10 on the mirror; the hook skipping the gh read with its suspended line; nothing switched). THE FAMILY GATE'S FIRST COVERAGE (lane D, 11:2x BST by the Mac's clock; its own line read "11:3x"): the harness live on build-1 under lease pool class measure (scripts and pinned binaries under /srv/builds/_adv-family-gate/): (1) the base control v5_attempts_census on the shipped class v5 draw over f8-label seeds 1,000 to 11,000, 24 cores since 11:16; (2) the family harness family_gate_era_census (branch family-gate-v5 = class-v5 8f481459 plus the harness, never a chain path; the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE): one drawn era per seed, every layer-1 parameter from the era's own stream (the shadow block {64, 128, 256} x {108, 54, 27}, the mixer {4, 8, 16} recorded, the read width over {1, 4} words, the ten weights within B = 4 with shfl and mulhi never raised), the chain draw through the real rule with every candidate's first failing part, then on the accepted program at the rule's own 2^20 sample the (c'')/(c''') ratio, the largest 256-item bucket per site (ratio and sigma), the index-bit bias per site in sigma; the 16-era smoke run PASSED at 11:21 (about 10 core-seconds per era; 10,000 eras about 28 core-hours). THE WORST READINGS IN THE 16: (a) the index-bit bias read fires HARD on 7 of 16 eras, |z| 130 to 511 at one site, every one at address bit R (the era's stride rotation) or R+1 (era 15 with R = 25 bit 25 z -511 at P(bit) 0.25, a product's bit 0; era 7 R = 17 z -468; era 5 R = 26 z -440; era 13 R = 1 bit 2 z -255, a product's bit 1 at 3/8; era 1 R = 6 z -224; era 12 R = 5 bit 6 z -130; era 6 R = 18 z +256, an or-shaped source at 5/8), the other 9 under |z| 3.8: adv-cache-2's era-stride class measured at the acceptance's own sample on class v5 accepted programs: not diffuse at the bit level, a 25 percent bias on one address bit of one site in about 40 percent of drawn eras, which (c''') does not see (min ratios 0.9954 to 1.0000); a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50, about 1.6 percent of a hash's reads at f = 1/2 for one site, which does not move the f = 1 verdict but is an auditor's flag on "uniform random reads"; the lever is load_index's form (fold the product's low bits before the rotation), not a floor (a 6-sigma refusal would redraw about 40 percent of epochs): a class v6 design row. (b) The (c'') ratio min 0.9954 (era 7), the rest 0.9965 to 1.0000. (c) Attempts: 14 of 16 accepted at attempt 0 or 1; era 9 (shape 64, width 4, mul 11 and or 8 of 75) took 24 candidates: the lossy corner raises r, the exhaustion number to read per stratum. (d) The largest 256-item bucket: ratios 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets, +4.4 sigma), so the F8-tail bound must be stated in sigma, not ratio (the sigma column in the rebuild). Next: the random stratum (10,000 eras) and the corner strata (the lossy cap, width 4, shape 64, 3,000 each) on build-1's free 64 cores, then build-3 and build-4; the first cut of family-gate.md drafted, the measured coverage table in at 16:xx for the 17:00 cut. THE OTA TEST LITERAL FIXED (the update-return lane, 11:23 BST, ahead of both clocks): ota-test-25 off release-0.3.25 139c147a, tip 53cb2f73 on the mirror, one test-only commit (the test reading the installer's clear step as the begin/end block the detach made it; the detach's behaviour kept), the box 2 crate suite 303 + 35 + 8 passed, 0 failed, the full gate GREEN 60; the shipper's cut tip 139c147a plus this commit, so the install-detach rides 0.3.25 and the PC 2 rule-14 take runs on it. THE 60x FILE, THE WHOLE FILE NOT ONE FIELD (the CI steward, 11:25 UK): the test names the first missing key in key order; with base_unit_decimals in it named emission; the file on master and release-0.3.25 lacks six keys the 0.3.25 node line's OverrideParams has (base_unit_decimals, pool_split_activation_daa, program_class_v5_activation_daa, proving_base_fee_ceiling_multiple, proving_fee_ceiling_activation_daa, subsidy_per_block_activation_daa); ca3-v4-node's copy (81 keys, master's 75 plus those six, no shared value differing) passes on build-3 by hand; release-0.3.25 got the one-field commit 907fdaf4 at 11:23 and the whole-file commit follows through the hook's gate, master the whole file behind the one-field landing; the known-failed on record on all four boxes; the green from the core re-runs in the 12:30 matrix; the risk named to the shipper: an older daemon reading the file with deny_unknown_fields. THE INDEX FOLD AS A CLASS V6 DESIGN ROW (the research lane, docs/design/class-v6-rotating-family.md on the mirror, the commit after 206e81e1): load_index folds a product's low bits before the stride rotation so no era's R lands a biased bit on an address bit (a design row, not a draw and not a floor); the evidence lane D's 7 of 16 drawn eras at |z| 130 to 511 on address bit R or R+1 with the (c''') ratio blind to it; the chip row 1.6 percent of a hash's reads at f = 1/2 for one site and zero at f = 1; the cost 0 on every card (one xor-rotate on the address path); the known-failed test lane D's 7 of 16 reading 0 of 16 with the fold; the value-level bias test in layer 4 ordered after the fold as its guard; the F8 tail's largest-bucket bound restated in sigma against its own window's Poisson expectation. The 60x commits: the one-field commit on both lines (master 7be52d76 at 11:24, release-0.3.25 907fdaf4 at 11:23), the whole-file commits in their gates behind it (release cbbaa8c4 pushing, master's queued). CLASS V5 AT THE KNEE ON THE 5090 (the hash lane, run-ca3-pc1-v5lock-5090-20261008-b, 11:09 to 11:21 UK, the 5090 alone, the v5 kit's CUDA worker on the rotate-fold build 8f481459, 60 s rows, the cleared helper sequence; an hour ahead of main's 12:30 clock): the same genesis seed, class v4 against class v5: unlocked v4 135.82 MH/s at 458.3 W (0.296 MH/W), v5 135.90 at 474.3 W (0.287); at 1,300 MHz v4 125.92 at 294.0 W (0.428), v5 125.93 at 299.8 W (0.420); at 1,200 MHz v4 115.69 at 273.3 W (0.423), v5 115.87 at 278.6 W (0.416); the Devnet 3 epoch-0 v5 pack (another seed, the fingerprint 82b19cbde8557ea5 matched on every row): unlocked 136.94 at 494.4 W, 1,300 134.10 at 315.6 W (0.425), 1,200 128.51 at 302.2 W (0.425). THE READING: at the knee class v5 loses 0.0 percent of rate against class v4 and costs 2.0 percent in watts (1.9 percent per hash), under main's 2 percent line, so the v4 knee stands, the tiers table says the class v5 rows are within it, and the UI lane's knee note stays off (knee_loss_pct 0 on the 5090); the A4000's 17 percent is a capped card's number: the 5090 at 1,200 MHz holds v5 level with v4 too, so the loss appears only where the power cap, not the clock, is the limit. Per tier for the founder: a 5090 or 5080 owner on a knee lock loses nothing at the class v5 crossing; a power-capped card (a datacentre card at its cap) loses up to 17 percent until its cap is raised or its class re-tuned. The 5080's rows after the v6 packs job if wanted; the AMD grid live on PC 1 since 11:25 (24 points, about 32 minutes). LANE B'S FIRST READING, RELAYED BY MAIN (11:2x BST), WHICH CHANGES THE CHIP MODEL AND LEADS THE 20:00 SYNTHESIS: a 2 GiB SRAM full store on one N2 die (about USD 500 of silicon, an N2 project of USD 100 M to 500 M) reads 13x to 17x the 5090 per joule at zero shadow and 2.7x to 4.8x with the shadow at the measured k band; layer 2 (the dataset tracking chain state) moves its capex, not its joules; the custom HBM4E base die (2027 to 2028) 6.5x to 14x, untouched by the four layers; PIM structurally blind to dependent random reads; and the M5 Max at 3.1x the 5090 per joule is the honest denominator. MAIN'S ORDERS: (1) chip-model-v3 gains the SRAM-store row and the HBM4E base-die row with lane B's figures and their claimed or measured marks; (2) the synthesis states the per-joule edge against the SRAM store honestly (3x to 5x with the shadow) and against the M5 Max, and prices the one layer that answers it: a dataset floor that grows on a schedule faster than SRAM cost falls, with the cost to a 12 GB and a 16 GB GPU and to 16 GB unified Apple memory stated; (3) the served chip line ("2.1x per joule at the knee") is reviewed at 20:00 with the measured basis for each clause; no served text changes before the synthesis, and if the SRAM-store reading stands the line becomes the honest range with the project cost and the clock beside it. THE SHIPPER'S THREE READINGS (11:2x BST): (1) override-60x.json: every reader in the tree is the fast-time harness, the sims and CI; no daemon on the fleet loads it; the app manifest's consensus.override is a separate 16-key object carried from the live manifest and untouched by the cut; the live chain's object is the digest's (1b37cb9d on e0644958); the harness's file only, the cut stands. (2) The cut tip cbbaa8c4 on release-0.3.25 (907fdaf4 plus the steward's whole-file commit; the crate and packaging trees byte-identical to 907fdaf4's, whose crate gate read 305 + 35 + 8 at 11:24; override-json-check passing): amd-clock-25 e2962b89, tiers-25 d3d0704a, the Intel header, the tiers class-flip pair 081b3ba7, install-detach-25 52a34111 with its test fix, the node-source pin e0644958, the host bc8d4f79, the fast-time file; the Mac DMG on it afa7f527 (45,766,741 B, the node pair 556926b1/d2dfe966), staging. (3) The knee note off on the 5090 rows. The pin at 13:00 on e0644958 and the 13:40 provisional minute standing; the matrix on cbbaa8c4 and e0644958 the steward's by 12:30. LANE B'S FIRST CUT ON MASTER (34f63b3c at 11:25 UK, four hours and thirty-five minutes ahead of its 16:00 clock): docs/analysis/class-v6/hardware-future.md with the three findings and the k bands (with the research lane, into the synthesis's section 7a on counter-asic-4 at ad37a50c); lane B's four decisions in its section 7 with defaults (the draw bounds by 20:00 via the synthesis; the dataset schedule unchanged; the M5 Max as the reference joule; the clock unchanged); nothing built or benchmarked, gh untouched; the full report by 09:00 adds detail only, no k band moving. LANE A'S FIRST CUT ON MASTER (docs/analysis/class-v6/history.md, 300 lines, merge 4c58ad65 at 11:26 UK, three and a half hours ahead of its 15:00 clock; the full gate GREEN 73 checks; primary documents read from the PDFs: the Least Authority and Bob Rao audits, Kik, EIP-1057, the RandomX design and v2, Tromp's README, the Fudan Equihash solver, Percival's lookup-gap note): 21 chip rows by mechanism (what each chip specialised, the miss, the timeline, the v6 layer, closed or not, the per-joule number), the in-depth sections (Ethash, ProgPoW, RandomX, Cuckoo, Equihash, Scrypt and Argon2, the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows), the four layers against the history layer by layer, the tier consequences. THE HONEST VERDICT WITH THE NUMBER: the chip that stores the dataset (class C: every Ethash chip, the E3 at 1.0x, the Linzhi at 2.1x, the Jasminer X4 at 5.1x via DRAM hybrid-bonded onto a 40 nm logic die, the E9 Pro at 4.1x) is NOT closed by any of the four layers, every per-era draw and family epoch being firmware to it; v6 inherits 5.1x per joule on GDDR7 at zero premium (3.6x at the 5090's knee, 2.1x with the class v4 shadow at k = 1), USD 2.8 against 14.7 per MH/s; classes A, B, D's governance half and E are closed, mostly since v2 and v3. THE THREE LESSONS THAT BIND: (1) the stored-dataset chip is firmware-immune to every draw; only joules and memory growth move it; (2) automatic change beats the human fork only where it costs the chip a redesign, and the one such parameter is the memory: layer 2 as declared is not an anti-chip rate (a 32 GB board lasts 60 years at 0.5 GiB a year; the 8 GB card is out at year 12; the E3 the only chip a growth rule ever killed, 20 to 27 months after shipping, at the fleet's own 4 GB limit), so its floor and a per-tier ceiling are the numbers to fix, not the rate; (3) a steered address pattern is always found after launch unless the test lives in the acceptance rule, and every drawn parameter changes layer 4's null, so the census re-derives per era (2.2 s per candidate). CORRECTIONS TO THE 5 OCTOBER FILE: the Antminer X9 withdrawn May 2026 with zero units (not "July 2026 delivery"); RandomX v2 released 25 March 2026 with activation pending (not "no fork"); CryptoNight's secret chips at about 33 months, not 43; Vorick's "survives forks at under 5x" and "13 months for a startup" on no fetched page, marked unverified. Two asks with defaults: layer 2's ceiling (if no word by 20:00 the full report drafts it as GB per tier per year keyed to card-lifetime-2026-10-05.md, with the flag that a dataset tracking state literally outgrows every card inside a decade if state grows as Ethereum's did); the hardware file cross-cited, not repeated. The lane's web-search budget spent (200 of 200); further additions by direct fetch. LANE D'S STATE (11:2x BST by the Mac's clock; its own line read "11:5x"): the first cut committed on class-v6-family-gate at 55c0dc6a with the full gate running; the census at 640 random eras, 298 lossy-cap, 327 width-4 on build-1 and about 500 shape-64 on build-3, the two build-4 corners queued behind a full pool; the landing on the gate's GREEN, the measured coverage table in the 17:00 cut. THE SNAPSHOT DIGEST STAMP (the node lane, 11:2x BST; a wip on release-0.3.25-node under its suites since 10:28Z): every snapshot a node writes carries its consensus digest as a new last field (the day-streams field's fallback shape, so 0.3.24 files decode with no stamp); a node with its digest set refuses a snapshot stamped under another digest ("re-executing from genesis") and one with no stamp ("written by a node before 0.3.25"), the follower starting at genesis; the daemon sets the digest from its params; the tests known-failed first (another digest refused, an unstamped file refused, nothing loaded; a matching stamp resumes, the written file carries the stamp, a digest-less process resumes as before, the wire round-trips); if the suites read green the full gate set runs and it is in the pin at 13:00 BST. THE CONSEQUENCE FOR THE MOVE: every Devnet 3 node restarted on 0.3.25 re-executes from genesis (no file written before 0.3.25 carries a stamp), so the restart takes the chain's re-execution time, which a fresh 0.3.25 node on build-1 since 10:24Z measures now (about 30,000 chain blocks; the rate in the pin line). TWO READINGS BESIDE THE CAUSE: (a) build-1's three nodes differ at 26247 (node1 0x3f53a7b9, the seed 0x717e7dc8, the observer 0x4548c319), and the seed and node1 differ at block 0 already (0x275b0cce against 0x7e37a9fb), which the ba75bf6f file alone does not explain (both resumed their own files across the same restart; the seed also restarted at 02:00Z on 2720d8d2 from a 0.3.22 file); the fresh node's genesis root and its first divergence from each decide whether a second class (an older-object file on the seed, or the resume itself) is in play; (b) the fleet asked for the roots at 26247 and 15611 on hub-1's Devnet 3 node, dn3-g1 and every prover by 12:30 BST with each node's resume line. The loud status for a vetoed node (a veto counter, the last veto's line on the explorer's status, "state not fresh") on the same line if the suites leave time, else 0.3.26, the node lane's word at 12:30. MAIN'S WORD ON LANE A'S ASK (11:2x BST): the default stands (the GB-per-tier-per-year table keyed to the card-lifetime file, with the flag), and one schedule to price beside it so the 20:00 reading carries a decision: a dataset floor of 6 GiB at the v6 epoch (every 8 GB card keeps mining with its cache; the 6 GB 2060 tier drops), 10 GiB two years on (the 8 GB tier drops), 14 GiB at four years (12 GB drops; 16 GB and Apple 16 GB unified hold), each step by height like a class epoch, the schedule itself a consensus field, with the cost per tier stated as the year each falls off and the share of today's measured cards that is; against the chips: the hybrid-bonded DRAM chip sized at launch (the E3 class) dies at the first step it cannot carry, the SRAM store pays capex only, both said. Lane A's corrections to the 5 October file go into the record and the served texts tonight. MAIN'S WORD ON THE STAMP AND THE GENESIS CLASS (11:3x BST): the stamp rides the pin; the re-execution time goes in the pin line and the move plan per tier; the fleet staggers the restarts in thirds so the proving share never reads zero, and the hourly line says "re-executing" with the count until the last prover is back. The second class is a GATE, not a note: the seed and node1 differing at block 0 means one of them runs a different execution genesis, and a hub node on a wrong genesis is worse than any snapshot drift; the pin is not named until the node lane says which file each of build-1's three nodes and hub-1 loaded at genesis, which root is the network's (the fleet's roots at 26247 and 15611 decide it), and the wrong one is corrected or re-walked; if that is not read by 13:00 the pin waits inside the 14:53 ceiling and the shipper slides by its authority. The vetoed-node status rides 0.3.25 if green, else 0.3.26. THE 60x FILE LANDED (the CI steward, 11:31 UK, ahead of 11:45): release-0.3.25 cbbaa8c4 (the whole 81-key file on 907fdaf4, the hook gate GREEN 60) and master e295c0d5 (the same file, the gate GREEN 73); known-failed to green on record: core RED on the one test on all four boxes before, core GREEN on the fixed pair on build-1, build-3 and build-4 after, build-2's re-run running; the full matrix by 12:30. A NEW GATE ON THE PIN (main, 11:3x BST, from the reference-apps lane's read): node1-dn3 and the re-executed observer diverge from chain block 26294 at DAA 60,578, the 10:05 move minute; node1 executed a block the selected chain later dropped and never unwound it, so its numbering runs one high and its state and records diverge; that is the drift class and the likely cause of last night's proving collapse after a move; the stamp does not cure it. The node lane's order: a known-failed reorg test under the exec follower, the fix on release-0.3.25-node if green by 13:30, else the move with the mitigation (every node re-executes from genesis after the minute, the vetoed-node status loud) and the fix as 0.3.26 tonight; plus the roots census to count stale nodes for the fleet's re-walk before the minute; the shipper's slide authority covers the pin inside 14:53; if the fix needs past 14:53, the floor re-cuts from the next minute by the same authority; the explorer lane reads block numbers from the observer node only (the chain the certificates follow) until the fix is live. THE FAMILY GATE'S 12:00 COVERAGE (lane D, 11:3x BST by the Mac's clock, ahead of its clock): 4,900 drawn eras through the per-era tests on three boxes (build-1 random 1,444 and lossy cap 663 at 10 core-seconds per era; build-3 shape 64 at 2,162; build-4's two lossy corners queued behind a full pool); the full gate on the first cut GREEN (73 checks, 381 s), the landing on one re-gate after a merge conflict on export-exclude.txt with the research lane's line (resolved, both kept). THE WORST ERA PER TEST: (1) THE EXHAUSTION BOUND BREAKS AT THE LOSSY CORNER: with or, mul and mulhi all at +4 points (30 of 75 lossy against the table's 18), r per candidate is 0.956 (the table's 0.681) and 8 of 663 eras EXHAUST the 256-attempt cap (mean attempt 18.6, max 252), so 1.2 percent of epochs at that corner would take the last-resort program, which adv-accept-3 showed fails rule (a) in 9 percent of seeds; B = 4 with the lossy ops free to rise is therefore outside the band; the random stratum at B = 4 (every weight drawn, lossy ones included) reads r = 0.718, max attempt 107 and 0 exhaustions in 1,444, but 107 attempts is 4x the shipped max of 28; the ring-A rule the cut carries: the sum or + mul + mulhi at most the table's 18 plus B, so r stays under 0.85 (r^256 under 1e-18); the default by 17:00: B = 4 on the injecting families only, the lossy families capped at their base. (2) THE ERA-STRIDE CLASS AT THE BIT LEVEL ON THOUSANDS OF ERAS: 52 to 58 percent of accepted programs in EVERY stratum carry one site whose address bit R (or R+1, R+2) is biased at over 6 sigma at 2^20, 33 to 40 percent at over 100 sigma, the worst z 1,024 at bit 7 of a site under R = 7 (a product's bit 0 at P = 1/4 landing at bit R): adv-cache-2's mechanism at half the family's epochs on programs (c''') passes (min ratios 0.9950 to 1.0000); the chip price per site about 1.6 percent of a hash's reads at f = 1/2 against the partial-store curve's 1.26x ops cost: the f = 1 verdict stands, the "uniform random reads" sentence does not; the catch structural (the index fold in load_index before the rotation, the class v6 design row), not a floor. (3) The largest-256-item-bucket excess: clean full-window sites +4.4 sigma; the worst eras +94 to +128 sigma at one site (the F8 tail's quarter-bit class at scale, the same mechanism: the bucket at the biased bit); the bound in sigma from the clean spread in the 17:00 cut. (4) The (c''') refuse rate per stratum: random 2.56 percent of candidates, shape 64 3.41, lossy 0.42 (the lossy rejections earlier at (a')); 0 accepted programs under 0.995 anywhere. (5) VOID and rerun: the width-4 stratum ran at width 1 (the era's one-entry allowed set redrawing to the base's width; fixed, the harness rebuilt, restarted at 11:5x with its own label space); the first corner strata sharing the random stratum's label space coincide with its draw a third of the time; the reruns use per-stratum labels; both stated in the cut. Coverage by 17:00 at about 1,000 eras per hour per 16 cores: random 10,000, shape 64 3,000, lossy cap 3,000, width 4 3,000 plus the two build-4 corners; the rule-of-three line for the random stratum at 10,000 eras a failing fraction under 3e-4 at 95 percent for every ring-B test. THE V6 COST ROWS (the hash lane, 11:4x BST by the Mac's clock, its own line reading "12:4x"; four hours ahead of 16:00): with the research lane at scratch v4/ca4-v6-cost-rows.md, every row labelled measured or modelled; the layer-2 headlines: VRAM 3.2, 5.4 and 9.9 GiB at the floor, 2x and 4x; a 12 GB card falls off at about 9.5 GiB (year 15), a 16 GB GPU at 13.5 GiB (year 23), a 16 GB unified Mac at 8 GiB (year 12), the 5090 at 29 GiB (year 54); the DRAM-read cost per hash size-independent (the 5090's 1.11 microjoules of 2.29), so the layer moves capex not joules, and the card rows allow a floor of 4 GiB in year 1 and 8 GiB by year 4 without retiring a 12 GB card (main's schedule of 6, 10 and 14 GiB at the epoch, two and four years sits above that: the 12 GB tier drops at 14 GiB, the 16 GB holds); the measured size rows (the v3 pack at 2, 4 and 8 GiB on the 5090, unlocked and at 1,300) ride the v6 packs job after the AMD grid. The AMD grid: the first run refused in 2 s at no_tune_line (the old installed exe, as designed); the rebuilt exe on PC 1 by the update-return lane's fetch at 11:33, the rerun from amd-clock-25 572c3ee0 live since 11:39 (about 32 minutes, the rows about 12:15). The class key on the mirror (ember-tiers-25 0a838072 in tiers-class-25 081b3ba7, with the shipper since 11:13, inside the 12:30 reading). The Arc read waits on the shipper's PC 2 take; the 12:30 default "no Arc read" stands unless it starts before. THE DRIFT CLASS READ FROM THE LOG (the node lane, 11:4x BST): at 09:42:09Z node1-dn3 accepted 0x6aa6 (DAA 60,578) and at 09:42:10Z 0xb708 (the same DAA and blue score 60,265, both children of 0x0fed at 26293: a tie at one height); its follower executed 0x6aa6 as chain block 26294 (28 transactions) and 1.1 s later 0xb708 as 26295 (the same 28 skipped as already included), with no reorg line between; every consensus view now (the seed, node1 itself, the observer) has 0xb708 as the chain block with the selected parent 0x0fed and 0x6aa6 off the chain, so node1's records hold an orphan at 26294 and number everything after it one high, and its state root diverged from there (the observer, re-executed from genesis, agrees with node1 to 26293). THE GAP: the 0.3.22 continuity rules (ledger N15) check the first appended block's selected parent against the tip at append time and scan the whole record set against the DAG's selected parents ONCE per state generation (a restart or a loaded snapshot); a break landing after that scan, as this one did ten minutes after node1's restart, is never looked for again until the next restart; the fleet's +2 on four shared-devnet boxes is the same gap. THE FIX on release-0.3.25-node (a wip under the exec suite since 10:41Z): the self-check runs every 30 s over the ring (the last 2,000 records) against the DAG's selected parents and in full on a generation change, a break handing the records above it to the reorg unwind (the existing branch restoring the ring state at the fork and re-walking); the test known-failed first on node1's exact shape; on the same commit the snapshot digest stamp (exec 51 of 51 green on its wip) and the vetoed-node status (vetoes counted on the status with the last veto's line, stateFresh false while any stands, on igneum_getNodeInfo and the status RPC); the exec suite's green about 11:46 BST, then the named commit, the full gate set, both canaries (the digest 1b37cb9d unchanged: nothing consensus) and the fast-time pair, the gated tip by about 12:30, inside 13:30. What the fix does not do: name why the tie-break flipped under node1 at 09:42Z (its DAG now reads 0xb708's parent as 0x0fed and the path at the time must have read otherwise; the second "PoW accepted 0xb708" line 0.4 s after the append says the block was processed twice), a reading for the record after the pin. The fresh 0.3.24-object node on build-1 past IBD and executing from genesis; its root at 26247, its rate and its memory peak in the pin line. MAIN'S WORD AT 11:4x BST: (1) lane D's band default stands (B = 4 on the injecting families only, or, mul and mulhi at base, the ring-A lossy-sum rule), and the index fold before the rotation with the bias test as its guard is layer 1's rule; (2) the served sentence "uniform random reads" is corrected today, not at the review: the audit lane rewrites it to the measured statement (reads spread over the whole dataset; a bit-level bias at one site appears in about half of epochs; it prices about 1.6 percent of reads to a chip storing half the dataset and nothing to a full store; the next class folds it out), through the gate and the master-only deploy, with the ledger row; (3) layer 2's table splits Apple by memory size (16 GB unified at its 8 GiB limit, 32 GB and 64 GB Macs holding every step), the M5 Max being the honest best per joule and the Mac tier a large audience; the schedule decision at 20:00 is the founder's with that column in front of him. THE EXPLORER'S SOURCE (the explorer lane, 11:4x BST): it reads one endpoint and always has, the Devnet 3 observer node on build-1 (the execution RPC on loopback 26850 through tools/observer/explorer-indexer.mjs, the observer's own dn3_ tables on 28650); it has never read node1-dn3, so there was no switch; the indexer on 26850 since 10:04 UTC with a full refill from genesis at 10:33 UTC after the root equality read at block 26,247; the pages now name the observer node as the one source, the chain the certificates follow (on explorer-dn3, in the gate; the merge and deploy follow). THE GENESIS GATE'S ANSWER ON build-1 (the shipper, 11:43 BST): the seed was the odd node (its block 0 from the 0.3.22 binary; the rule change for the node lane's record), re-walked from genesis at 11:35:30 by the shipper's hand (the evm moved aside, the same binary and flags, the kept datadir) and reading population A's roots at 11:43:00 (0x47983bd9 at 15611, 0x3f53a7b9 at 26247, head 26,478). THE MEASURED RE-EXECUTION: 26,478 chain blocks in 7 minutes 30 seconds (about 59 a second over the walk; 100 at the start, 30 past 15,000), RSS 5.5 GB; so the move plan's per-tier line: a prover's node is back about 8 to 10 minutes after its restart on 0.3.25 (30,000 blocks at the minute), a Mac or HiveOS app node the same at its update hour, miners unaffected; with the hub and the seed at the minute and the provers in two thirds at +0 and +25, the proving share never reads zero and the last prover is back about 35 minutes after the minute. The node lane's gated tip (the ring check, the stamp and the vetoed-node status in one commit, the digest 1b37cb9d unchanged) by 12:30; the pin after it and the fleet's census; the minute about 14:10 at the earliest if the fix rides, inside 14:53. LANE A'S SCHEDULE SECTION (history.md 4.2a, master 59963461 at 11:45 UK, five hours ahead of its 17:00 clock; three landings today: 4c58ad65, b645762d with the synthesis lane's six items folded in, 59963461): ONE FLAG on main's schedule with the number: under the standing budget rule (the working set under 6 GB on an 8 GB card, the 75 percent reading) a 6 GiB floor does not fit the 8 GB tier (6,398 to 6,744 MiB, 78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent); 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2 (not the 8 GB tier alone); 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above. The schedule that drops the tiers in the order main named, priced beside it: 5.5 GiB at the v6 epoch (6 GB falls, 3 percent of the 32 measured consumer cards), 8 GiB at two years (8 GB falls, 22 percent, with the 10 GB RTX 3080 and Apple 16 GB; 12 GB holds at 69 to 72 percent), 11 GiB at four years (12 GB falls, 22 percent; 16 GB holds at 70 to 73 percent); 24 GB and above hold throughout. Against the chips: the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 of GDDR7 on a USD 470 part); the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. So the schedule is a fleet-retirement rule with a USD 0 to 160 chip tax, killing only a chip whose maker ignores the field. The default by 20:00: the full report carries both schedules and recommends 5.5 GiB as the floor that keeps the 8 GB tier inside the rule. Owed: the fleet's hashrate-weighted card census (the shares are by count of the bench table's 32 measured consumer cards). LANE A'S CORRECTIONS SERVED (the site audit lane, master 2119e4f3 at 11:46 BST, gate green on 78166c6c, commit 14ad1a33; seven hours ahead of 19:00): every served "no chip shipped" and "seven years without a shipped chip" sentence (the litepaper's precedents row, the chip-model paragraph, the vs RandomX lead and its track-record row, the limits section; /claims and /randomx following) now carries the Antminer X5 (September 2023, 1.46x per joule over a desktop CPU, silicon believed mining privately from about 2021) and RandomX v2 released 25 March 2026 with its mainnet activation pending; the ledger rows X34 and C2 corrected with lane A's file cited, the pins moved, the public ledger and page regenerated; the X9 sentence already matched lane A's row (sales opened 26 December 2025, shipping scheduled July 2026, withdrawn mid-May with zero units), the precedents and track-record cells now reading "withdrawn in May 2026 with zero units"; the 43-month, 13-month and Vorick figures on no served page; the commit also carrying main's governance line beside the class v5 sentence and six class v4 watts rows; the "random reads" correction with its AP-F8 row next by 13:30; the build-server lane deploys on main's word. LANE C'S FIRST CUT ON MASTER (docs/analysis/class-v6/invention.md at a9f03598, 11:48 BST by the Mac's clock, five hours ahead of 17:00, with the census script under tools/attack/v6-invention/ and its two TSVs): build-1 ran the per-load acceptance census (11 forms x 256 seeds, twice: no era and drawn eras, 80 s each on 48 leased cores) and the verifier benches; the two packs exported and with the hash lane for PC 1; the second candidate (warp-uniform block selection) has no pack form without a generator change, which the no-code rule holds this week, so its row stays modelled. A CORRECTION TO THE CA4 FILE'S VERDICT, FOUND BY LANE C: the counter-asic-4 crate's per-load acceptance (BiasedIndexBit) counts the era window's fixed top index bits 26 and 27 as biased, so under any drawn era it refuses every per-load program (0 of 256 on every form today, 5,536 of 7,862 bias rejections naming those two bits); 20.2a-close's "1.4 percent accepted, 42 of 64 seeds exhaust" (the per-load class's death at 00:0x) was read across drawn eras and so measured the instrument on most rows; on the no-era census the sound form (16 x 256 x 1) reads 0.927 rejection per candidate and 234 of 256 seeds accepted, the iterated 16 x 27 form 0.989 and stays dead; the one-line instrument fix (skip bits at or above 28 minus the site's k_off) is a research-crate change, made today as a research-only change behind the pack by the coordinator's order, and the sound per-load form's verdict is REOPENED as a measured candidate (its energy and rate rows on the 5090 through the hash lane; chip-model-v3 5.11's note on the per-load closure to be re-worded when the re-read lands). THE REOPENING APPLIED (the research lane, 11:5x BST): the reopened wording in counter-asic-4-research.md (20.2a-close and rank 4), class-v6-rotating-family.md (section 7c as layer 5) and chip-model-v3.md 5.11's note, with one precision: the 22:5x UTC census ran the bare class with no era, so its 0.986 is the iterated form's own no-era figure (lane C's 0.989 agrees the 16 x 27 form is dead); the artefact in any drawn-era read before the fix; the fix already on counter-asic-4 as of 10:5x UTC (BiasedIndexBit judging only the bits inside each site's window mask through verify::window, per site), uncommitted until the suite's line lands (the box-2 slot since 10:31Z), so lane C re-reads on that branch once pushed, not making the change twice; the chip-model 5.12 rows (the SRAM store, the base die, PIM's blindness, the M5 Max denominator) in the same tree, riding the same commit before 15:00. A MIRROR NOTE (11:52 BST): lane B read silent 25 minutes by the mirror; its first cut landed at 11:25 and its next clock is the full report by 09:00 tomorrow, so the silence is its finished state, not a fault; the mirror now skips lanes whose clocks are done. A MASTER-ONLY DEPLOY AT 11:53 BST (the build-server lane, on main's own builder-programme landing d86ea00a: /build, /grants, /faucet, /swap asserted; the served sha a9f03598, master's tip; the checks ok; 38 miners rows): it carried the audit lane's 2119e4f3 (the RandomX history correction with the Antminer X5 and RandomX v2, the governance line, the first six class v4 watts rows), which main ordered served tonight and the audit lane cleared for the next scheduled deploy; the "random reads" sentences not yet corrected as served; the coordinator's trigger stands for the 13:30 correction. LANE C'S KNOWN-FAILED TEST FOR THE INSTRUMENT (11:5x BST): igneum-pow/tests/v6_window_bits.rs, the sound form (16 x 256 x 1) accepting on at least 4 of 8 seeds under drawn eras 0 to 7 with 0 window-bit refusals (0 of 8 before the fix), the no-era bit-0 refusal on seed 3 standing; 2 passed, 0 failed on build-1 against a local overlay of the same nine lines, the overlay reverted, the test file an offer to the research lane's suite; the re-read on the research lane's commit by 15:00; meanwhile build-1 runs the lane's uniformity read at 2^20 nonces on 64 seeds for the two sound per-load forms and the class v4 shape (the F8-form top-0.1-percent item share against a uniform control, the per-site distinct ratio) on a harness over the crate's trace_load_indices (the master F8 tool mirroring class v4's execution order), about 20 minutes on 24 leased cores. THE RANDOM-READS CORRECTION ON MASTER (the site audit lane, bf54b08d at 11:54 BST, gate green on db038279; an hour and a half ahead of 13:30): the litepaper's lead reads "dependent reads spread over a multi-gigabyte dataset that changes daily", the table row "the dependent reads are", the "chain of random reads into a table too big for a chip to carry" sentence standing with the measured clause after it (the 0.995 floor on every accepted program over 4,900 drawn eras; about half of epochs with one load site biased at the era's stride rotation bit; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold before the rotation in the next class); evidence row 18 with lane D's family-gate.md and adv-cache-2's section 2.3 as sources; the ledger row AP-F8-7 (AP-F8-6 taken on class-v5): "Open, priced: 1.6 percent at f = 1/2, nothing at f = 1; the served sentence corrected 8 October 2026", the disposition class v6 layer 1's fold with the bias test as guard; the public ledger and page regenerated; no pinned sentence touched; the fud-ledger's quoted history standing; the build-server lane deploys bf54b08d. BUILD-1 AT 11:55 BST (the coordinator's own read): load 107.6 on 96 cores; the lease table: the family gate 32 cores (the random stratum, 10,000 seeds), 16 (the lossy cap, 3,000), 16 (width 4, 3,000, restarted), lane C's uniformity read 24 of 48; 88 of 96 cores held, none waiting, no pre-emptions in the last ten minutes. THE 11:55 BST LOAD LINE (the build-server lane, all four boxes at the minute): build-1 (96 threads) load 113.7, the pool holding 32 for the family gate's random stratum plus 16 and 16 for its corners and 24 for lane C's uniformity read (88 of 96 held), the release and v5 builds outside the pool; build-2 (96) load 81.3, the pool holding 32 for the attack-pass F8 census (the thirds); build-3 (32) load 25.1, the pool holding 16 for the family gate's lossy-base stratum and 2 for the hash lane's x16 rows; build-4 (96) load 89.0, the pool holding 4 x 8 for the attack-pass F9 chunks 0 to 3 plus F1's 40 and F4 done; no release-class waiter on any box; the builders loaded, none idle. The founder's order at 11:2x is met at the minute: every box above 80 percent of its threads bar build-3 at 78 percent of 32, which the two queued build-4 corners and the next v6 pack take. The build-server lane's deploy of bf54b08d served at 11:56 BST, two minutes after the landing: the post-deploy checks ok (api/live igneum-devnet-3, the index strings, the legal line, 38 miners rows, the four builder pages 200), and the litepaper's lead sentence read back from the served page carries the corrected wording (wide parallel integer maths, warp shuffles, dependent reads spread over a multi-gigabyte dataset that changes daily, the program waiting on memory latency); the old "random reads over a multi-gigabyte" is absent. The CI steward's 0.3.25 pre-pin matrix with the shipper at 11:59 BST, 31 minutes inside its 12:30 clock: seven suites on four boxes, every cell green but the one known core red on the pair before the fast-time file (the same single test on all four boxes, the six missing keys), and core green on the fixed tree on build-1, build-3 and build-4 (170 passed each); build-2's re-run queued behind three lanes' suites and lands on its own; counts identical across boxes (pow 113, app 346, exec 49, miner 29, p2p-flows 38, consensus 134); the Mac's full gate on the 9b93e649 tree GREEN, 60 checks; build-3 and build-4 toolchains read as build-1. The matrix worktree sits at cbbaa8c4 (81 keys, igneum-pow identical to the pin's tree); the second matrix waits on the node lane's gated tip (by 12:30), the line by 13:15. The RX 9070 XT's first measured grid on the AMD knob (job run-ca3-pc1-amd-grid-9070-20261008-b on PC 1, 11:40 to 12:10 BST, 24 of 24 rows ok, the card reset to factory at the end): the rate flat at 18.93 to 18.98 MH/s on every point, the knob moving watts only; stock 3,292 MHz 195.8 W (0.097 MH/W); the clock offset alone to 2,924 MHz 159.2 W at -400 (0.119), clamping about 2,920 at -500; the power limit alone does nothing until -30 (184.4 W); best -500 MHz with -30 percent: 2,921 MHz, 149.3 W, 18.96 MH/s, 0.127 MH/W, a 24 percent saving at the same rate. Per tier: a 16 GB AMD home card gains a quarter of its electricity cost at no rate loss once 0.3.25's knob ships; it stays 3.5x behind the 5090's 0.43 MH/W at the lock, so last night's AMD reading stands (the read path, not the clock, is AMD's cost). The v6 packs job live on the 5090 since 12:11 BST (eleven packs including the three dataset sizes, unlocked and at 1,300, about 40 minutes). The Arc re-read not started on PC 2 (the shipper's take holds the box); at 12:30 the default "no Arc read" stands, the pairing 1c420786. The Ember priors committed on ember-tiers-25 at 1e966170 with known-failed tests, its suite queued behind build-2's slots since 11:46; the sha to the UI lane and the shipper on its green; if not run by 12:45 the suite moves to build-1 through a lease. Two master-only deploys from the builder stream, checks ok (38 miners rows, the six asserted pages 200): 0c64b24f at 12:07 BST, the explorer landing (explorer.igneum.network, /proving, /tx/, the dn3_ APIs reading "Devnet 3"; the explorer indexer unit moved to the master checkout and restarted, reading the observer only as main set), and 3355c098 at 12:16 BST (site/vercel.json only: the explorer host's root 307 to /explorer, read live). No chip text changed in either. Still in the stream: the reference-apps lane's /light, /receipt and /oracle (its gate since 11:50, the 13:00 default) and the audit lane's watts rows 11 and 12. A third master-only deploy from the builder stream: f0418c8d at 12:19 BST (main's word via the explorer lane: EXPLORER_EVM_RPC on the production env, so /api/explorer balances read live from rpc.devnet.igneum.network; checks ok, 38 miners rows, six pages); the public RPC's allow list tightened the same minute to igneum_get* (the two igneum_submit* writes refused), reported to main. No chip text changed. The /build lane DONE with every clock beaten: landed on master as d86ea00a (11:47 BST), deployed as a9f03598 at 11:53; /build, /grants, /faucet (the Devnet 3 faucet page) and /swap serving in the nav's Build group; faucet.igneum.network/api/faucet live on build-1 behind Caddy, funded 2,000 IGN by the fleet lane (11:01 BST), the first drip 11:17 BST, 1,989.99 IGN left; the walkthrough PASS through the public RPC and faucet (a contract deployed at block 27055, 24 s end to end, Foundry 1.8.5, docs/build/first-contract.md); the RPC list read from the node in docs/build/rpc.md; the audit's four wording lines in. One open fact to the fleet lane: build-1's Devnet 3 seed at 27810 re-executing from genesis while the faucet reads the observer's 26850 (the re-execution class measured at 7 min 30 s this morning). Lane D's coverage at 12:2x BST, every launched stratum complete (the runs beat the 1,000-per-hour estimate once the pools freed): random 10,000 eras (0 exhausted), lossy cap 3,000 (37 at the 256 cap, 1.2 percent), width 4 at the fixed harness 3,000 (0), width 4 plus lossy cap 2,000 (24, 1.2 percent), shape 64 3,000 (0), the lossy-base band (B = 4 on the injecting families, or/mul/mulhi never raised) 3,000 (0); 24,000 drawn eras through the per-era ring-B tests on build-1 and build-3; build-4's shape-64-lossy and shape-256 strata still queued behind the attack pass's F9 chunks and not needed for the cut. The exhaustion finding confirmed at scale: 61 of 5,000 eras at the lossy corner reach the last resort against 0 of 19,000 everywhere else, so the band rule (lossy families capped at their base) stands on measured rows. The 17:00 clock holds; the cut (coverage table, per-axis table, union-bound arithmetic, harness patch series) likely lands by 14:30 BST. The node lane's gated tip missed its 12:30 clock: the combined wip (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the reorg-unwind fix on the same commit) sat in build-2's queue from 11:41 BST at normal priority behind a Counter ASIC 4 suite holding a slot since 11:31, found at 12:21 and moved to build-1 at gate priority; the exec suite about 12:25, the named commit on green, the full gate set (build and consensus at gate priority, five suites, both canaries, digest 1b37cb9d unchanged) about 12:50, the fast-time pair about 13:05, inside the 13:30 clock. The coordinator's default revised and taken by the lane and the steward: the second matrix starts on the named commit the minute its sha exists; no sha by 12:50 and the matrix runs on e0644958, the stamp and vetoed status slide to 0.3.26. The pin reads about 13:15 to 13:30 rather than 13:00; the minute about 14:10 holds if the fix rides; reported to main at 12:29. The seed's re-walk read equal to population A at 11:43 BST (0x47983bd9 at 15611, 0x3f53a7b9 at 26247; 26,478 blocks in 7 min 30 s, about 59 a second, RSS 5.49 GB); the fresh node on build-1 executing from genesis since 11:42:34 at about 100 a second at the start, its roots to follow. The lesson for the record: a release gate is dispatched at gate priority or it waits behind research suites; the node lane's wips were not. Main's correction at 12:3x BST on the fleet default: the 10:12 FETCHED count is not a census of state. If the stamp rides the pin, every node re-executes from genesis at the minute and the census is not a gate; if the stamp slides to 0.3.26, the census (block 26294's hash and the 26247 root on every prover) is a gate and the stale nodes re-walk before the minute. The fleet lane silent since 11:31: a one-shot at 12:36 starts a fresh fleet-move lane from the fleet root to take the census, the re-walks, the stagger and the pullers if it has not answered by then; the old lane keeps the hold and the hourly line. The 9070 XT reading goes to the audit lane for its row. Build-2's queued cell landed at 12:24 BST: core GREEN on the fixed tree (177 passed), so the first 0.3.25 matrix is green on every suite on all four boxes. The steward's gate-priority stream for the second matrix written (every suite at gate priority, its own results file), waiting on the node lane's sha with the 12:50 fallback armed; the line by 13:15. The AMD knob closed for the cut before 12:30: the 9070 XT grid's rows in and the efficient point in EFFICIENT_W as 149 W (both floors: clock offset -500 at about 2,920 MHz where ADLX clamps, power limit -30; 149.3 W at 18.96 MH/s, 0.127 MH/W, 24 percent under stock at the same rate); the rate flat over the whole ladder, so the knob is a watts lever only and the knee rule reaches the floor; amd-clock-25's gated tip 1be99aa0 (full gate GREEN 60, suite 298 green) with the shipper as the cut tip, the release section reading measured. The 5090 comparison carries two denominators, both real: 0.43 MH/W at the v4 1,200 MHz lock (133.8 MH/s at 305 W), 0.58 to 0.60 at the 1,300 knee (134.6 at 223 W); the 9070 XT at its floors is 3.5x behind the first and about a fifth of the second; a served row names its point. The Arc default taken at 12:30 BST: no B580 re-read reached the v5 lane, so the pairing line went to the shipper as the FREEZE 1c420786 (0.3.24's, as published) with the kit zip 65b47211 (packs-ca3-v5-20261008T085619Z.zip; its packs, ids and 82b19cbde8557ea5 byte-identical to 1c420786's by the packs test on both trees) and the Intel worker held out; 8f481459 (gate 73 GREEN, suite green, the Intel fix in) stands behind it and becomes the pairing with the Intel kit the minute an equal Arc read lands, with the page's Intel row moved. Nothing else of the v5 lane's in the cut. The shipper at 12:33 BST: (1) the 0.3.25 app tip is 89e83df2 (cbbaa8c4 plus amd-clock-25's gated tip 1be99aa0: the 9070 XT's efficient point 149 W at 18.96 MH/s in the ceiling table, the grid playbook; crate gate GREEN 12:28, 305+35+8, inside the 12:30 app window); the second matrix uses it with the node lane's sha. (2) On the node lane's hint, build-1's Devnet 3 seed and node1-dn3 were found dead since 12:06 and 11:54 BST (logs ending mid-line, no panic, no OOM; the observer and the fresh node lived): the network's seed was down 24 minutes; both restarted at 12:30 on their kept datadirs (the seed resumed its clean re-walk snapshot, node1-dn3 re-walking from genesis). Two reads before the pin: the build-server lane by 12:50 on whether any build-1 run kills igneumd by name (a cleanup that does so reaches the seed at the minute); the node lane by 13:00 on whether the line can die silently under the finality route flood the seed's log shows (a million drops on one peer). (3) The pairing the freeze 1c420786, kit 65b47211, the Intel kit out (PC 2 dark, no Arc read today); the genesis class closed on the fresh node's roots; the pin after the node lane's gate set, the matrix and the census; the minute inside 14:53. The hash lane at 12:4x BST: (1) the Ember search priors on the mirror as ember-tiers-25 1e966170, app suite green (307 + 35 + 8), with the UI lane and the shipper; the cut default stated to the shipper (in by the 13:00 pin or 0.3.26). (2) The v6 packs job on the 5090 (since 12:13): the four packs made on the box or pinned ran PASS unlocked (mx8-genesis 137.65 MH/s at 312.2 W; mx8_sh256x27 137.62 at 464.6; the invention lane's mx8_shl4096x1 135.99 at 428.6; mx8_shl2304x3 135.85 at 483.6; the 1,300 rows follow); the seven exported on the Mac this morning (today's x8 and x16, the two re-weighted, the three dataset sizes) were refused by the worker's seed check in 0 s ("IGNEUM_SEEDW_INIT is not attempt 0 of the epoch seed"): the string-seed export form derives different seed words from the byte-seed form the pinned packs use; re-exported in the byte form (the x8 reproduces the pinned id 73bcbfe8 and seed words exactly; the three sizes too; the x16 pair and the two re-weighted packs on generator 2 differing only in the era, the multiplier or the weight table); kit b and one more PC 1 job of those seven follow the running job's close, about 13:00 to 13:45, rows to the research lane, the invention lane and the coordinator. The invention lane's reading so far: the sound per-load form at class v4's instruction count (shl2304x3, 55,296 shadow ops) costs 483.6 W against sh256x27's 464.6 W unlocked, 19 W more, not under; the one-pass form (shl4096x1, 32,768 ops) 428.6 W; the lock rows decide the per-load candidate's GPU side. The export-form lesson for the record: packs for the worker are exported in the byte-seed form, never the string-seed form. Main's load order at 12:5x BST: lane D's two remaining strata (shape-64-lossy, shape-256) move from build-4's queue (behind the attack pass's pool) to build-3, idle after lane D's strata; build-3 kept fed with lane C's packs and the family census's next corners; nothing new on build-1 (load 142) until the pin is named, its gates at gate priority. Sent to lanes D and C with the 13:05 default. The node lane's two readings at 12:4x BST on the combined tip: (1) the build-1 deaths were the OOM killer (the build-server lane read the kernel ring: the seed at 44.6 GB anon-rss at 12:06:07 BST, node1 the same class at 11:54, two 31 GB attack binaries beside them); what grows is the proof pool's in-memory proof map: since the late-join rule (0.3.17) every proof a node receives is held by hash in memory and never removed (the entries leave the 600-block record window and the on-disk archive drops below the pruning point, the map did not); about 1.2 MB a proof, 14,107 proofs on the observer after a day (17 GB on disk, 13.6 GB RSS), the seed at 128 inpeers took the relays fastest; older than 7bd2940f; the fix (a proof leaves the map and the verdict cache with its record at the window's end unless another live entry names it; carried proofs served from the archive; known-failed test) on the tip under its exec suite at gate priority since 12:35:55. (2) The ring check's known-failed test on node1's shape green (exec 53 of 53 at 12:34:53 before the pruning went in). The named commit (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the proof-map window, over 7bd2940f's re-announce and keygen and the ceiling switch) follows the exec line about 12:40, inside the 12:50 fallback; the full gate set at gate priority on both boxes, both canaries (digest 1b37cb9d unchanged) and the fast-time pair after it. The fleet's census (12:31 BST): 36 nodes on population A, the network's genesis root 0x7e37a9fb; 21 stale nodes, each with a genesis root of its own, re-walking from 12:35 in thirds; dn3-g1 died a third time at 11:55:47 (the same OOM class on a rented box the likely reading; the fleet's hourly RSS per node with a restart above 32 GB is the guard until every node is on the tip). Lane D on main's order, done 12:36 BST: build-4's two entries cancelled before running; build-3 carries four strata on the fg6 harness (42f2c77f), 8 cores each under class measure: shape256 (3,000) and w4lossybase (3,000) running, shape64lossy (2,000) and w4shape64 (3,000) queued behind them on the 24-core pool; the lossy band at B = 4 across the injecting families is the complete lossy-base stratum (3,000 eras, 0 exhausted, r = 0.595). Build-1's queued attack-f8 rebuild chain cancelled (the point-B live census moves to build-3); what remains there started before the order (four lossy-share strata at +1 to +4 points, 16 cores each, about 900 of 3,000 eras; the point-A live census at 2^24 on 32 cores). The 17:00 cut committed at 2a595e1b with the 24,000-era coverage, its gate re-running. A shared-Mac fault class found at 12:3x to 12:4x BST: the class-v5 lane's shell command ran pkill -f "tools/ci/pre-push.sh" before its own gate, which killed every lane's gate on the Mac: the record's merge gate three times, the invention lane's landing twice (d6955381), the family gate's once (exit 144). The kill-by-name class the 6 October rule bans in scripts (kill-by-name-check.sh), applied by hand on a command line. The word to the lane: kill only your own gate by its pid; gates on the Mac do not share a lock. Reported to main. The research lane's commit 0ab27582 on counter-asic-4 (the mirror, 12:4x BST, ahead of the 15:00 clock; the crate suite green on the committed tree, 116 passed, 0 failed, build-2 12:38, master's new derivation test among them). It carries: (1) chip-model-v3.md section 5.12, the two chips with lane B's figures and marks (the 2 GiB SRAM store on one N2 reticle: 17x at zero shadow, 8x to 30x on the read band, 2.7x at k = 1 and 4.8x at k = 0.5 with the class v4 shadow, 3.7x and 2.0x at the card's whole shadow, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M and 18 to 24 months, a break-even cap of about USD 330 M to 1.7 B on the mission lane's model; layer 2 moving its capex, two dies at 4 GiB 15x and four at 8 GiB 13x; the custom HBM4E base die 6.5x to 14x untouched by the four layers; PIM structurally blind, 1.6 percent of reads in-bank at 2 GiB; the M5 Max at 0.78 microjoules the honest denominator, 3.1x the 5090) and 5.11's per-load note in the reopened wording; (2) the merge of master (the sub-version 3 line, the derivation recorder, the re-exported packs) and the per-load bias test's fix (judging only the bits inside each site's window mask; lane C re-reads on this id); (3) the class v6 document through section 9: the lead on the SRAM store, the per-tier schedule table with lane A's checked steps (6 GiB does not fit the 8 GB tier under the 75 percent rule; 5.5 / 8 / 11 GiB drops the tiers in the named order, about a quarter of today's measured consumer cards per step), the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB, the one card that pays rate for a larger working set), lane D's rings and band, the index fold as a layer-1 rule, the 5070 Ti pair, the x16 mixer at 11.4 ms loaded by the right method (admissible false on the measurement), lanes B, A and C taken in 7a to 7c, and section 9's served-line review with the wording proposed for the 20:00 word. Owed for 20:00: the 5090 size rows (the hash lane's v6 job), lane C's 15:00 re-read, lane D's 17:00 table, the two re-weighted packs' rows; each lands as a row with its label, or its default. Main's word at 12:5x BST on the kill class: the rule "no kill by name on the Mac, pid file only, ad-hoc shell lines included" lands in the agents' standing text with this record landing; the steward makes it a gate check that refuses pattern kills in scripts and logs the sender of every TERM a gate receives. The class-v5 lane's own line: the four pkill lines (12:3x to 12:37) stopped its own superseded gate runs as its tip moved under them; nothing of its uses a name or pattern kill again, its background gate started with its pid recorded and ended by that pid only; its current run (gate 17 on class-v5 79799452, 12:39) runs to its end. The census and the four-item pin taken by main; the clock as the shipper set it. Lane D's interim at 12:5x BST for the 09:00 report, the lossy-share curve at 1,000 to 1,300 eras per point: r rises 0.80, 0.88, 0.92, 0.96 as or, mul and mulhi go +1 to +4 points each; exhaustion appears at +3 (2 of 1,029) and reaches 1.4 percent at +4 (14 of 994); every exhausted era's class v5 last-resort scan passes at its first or second candidate (k = 256 or 257), so the band's edge is between +2 and +3 points of lossy weight and the scan does its job at the corner. Its cut 2a595e1b under the gate, then the mirror landing and the send to the research lane. The attack pass's F8 to 256 seeds landed at 12:37 BST: seeds p66 to p257 (192 new) at 2^24 on the freeze 1c420786 (binary 0f5c98dc, pairing e5a4ac5978462156), the window-model control, build-2 under class measure, validation 0 mismatches (hash_warp agreement on 37,440 warps). 184 of 192 within 1.2x at the top 0.1 percent (mean 1.023); 8 over (p110 1.3527x, p66 1.3403x, p234 1.3156x, p145 1.2750x, p77 1.2664x, p225 1.2457x, p248 1.2188x, p89 1.2065x), each with its hottest item at 263 to 432 reads of 2^31 and the hot-set verdict clear on the windowed control (largest excess X_f/f +0.60). Over all 256: 245 within (95.7 percent), 11 over; the rate at 256 (4.3 percent) is the gate's at 64 (4.7 percent) and the worst fell (1.3527x against p10's 1.5047x). The 6-sigma largest-bucket line flags 57 of 192 (p110 +61.67 sigma): the AP-F8-1 tail mechanism at its rate. Two seeds carry a predicted source, one-one-bit through a load, both passed by (c''') on the frozen tip: p212 (1.1915x, attempt 4, site instr 7, r5, last writer load at 2) and p225 (1.2457x, attempt 0, site instr 37, r5, last writer load at 36), to the hash lane for by-site attribution as the gate's tail was. Verdict PASS at the gate's reading: no card or chip gains a cacheable hot set on any of 256 epochs. The row and f8-uniform.md section (e) on the mirror's attack-pass. Still running: build-4's F9 (six chunks) and F1 (10^6), partials at 17:00. The node lane's named commit inside the 12:50 clock: 42ce0f07 on release-0.3.25-node, both mirrors, 12:39:37 BST, the sha with the steward and the shipper. Content: e0644958 (keygen, the record re-announce, the ceiling switch at 82,800; digest 1b37cb9d) plus four node fixes, nothing consensus: the ring self-check every 30 s over the last 2,000 records with the full scan on a generation change (node1's class, its known-failed test green); the snapshot digest stamp (a snapshot under another object or none refused, the node re-executing from genesis); the vetoed-node status (the count and the last veto on the status RPC and igneum_getNodeInfo, "stateFresh" false while any stands); the proof map's window (a proof leaves memory with its record at the 600-block window's end, the OOM class). Green before the squash on the same tree: exec 54 of 54, the kaspad check. The full gate set at gate priority on both boxes from 12:39:44 (every line by about 12:52), both canaries reading the Devnet 3 digest back at 1b37cb9d, the fast-time pair by about 13:00; the crossing watch at 68,400 on the seed from 12:50; the pin line after the last of those; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. The invention lane at 12:5x BST: the hash lane's 5090 rows for the two sound per-load packs reverse the GPU-side sign of rank 1: at class v4's own instruction count the per-load form costs the card 19 W MORE than the whole block unlocked (483.6 against 464.6 W) and 6.6 W more at the 1,300 lock, rate 1.3 percent under, 15 to 20 percent more per shadow instruction (19.7 to 20.8 pJ against 17.2); the dead 16 x 27 export's 13 to 14 W saving does not carry (a 16-instruction loop against a 144- or 256-instruction straight segment). Rank 1 keeps its place by the file's own rule (the chip's project cost about 2x against the card's 2 to 4 percent of watts) with the honest sign: the card pays, not saves. The second cut landed at 4315e992, the third (these rows) under the gate. The drawn-era re-read on 0ab27582 built on build-3 but starved (build-3's 16-core pool under lane D's three 24-core leases since 12:38): the coordinator moved it to build-4 at once through the lease pool under class measure (build-1 closed until the pin is named); the 15:00 numbers from build-4, the box named in the row. The class v5 lane's full gate on class-v5 79799452 (the tip on both mirrors) GREEN, 73 checks in 463 s at 12:47 BST, left to run to its end: 0.3.25's pairing row on the page (the freeze 1c420786, kit 65b47211 with the Intel worker held, the Arc read to 0.3.26 with the second PC dark), master merged through its latest (the 60x file taken whole from master after the merge reordered seven keys and duplicated three, values equal), the generated ledger files matching. Nothing of the lane's pending; the one future item the Arc B580 re-read on kit 65b47211 when the second PC is back, which moves the Intel row and sends the 0.3.26 upgrade line. 42ce0f07 reads every gate green at 12:48:10 BST: build 12:42 rc=0 (igneumd 8e17a60b, /srv/artefacts/0325-42ce0f07/node-lane), pow 19, consensus 134, core 177, miner 29, p2p-flows 38, exec 54, all at gate priority; the Devnet 3 canary set with digest 1b37cb9d unchanged, byte 6, the override refused, the 0.3.24 pin refused on the digest both ways; the testnet canary b2e856ed unchanged. The shipper has the line; the steward's matrix runs on it. Two inputs before the pin: the fast-time SUMMARY on 42ce0f07's artefact (about 13:00) and the 68,400 crossing on build-1's seed (the chain passes it about 12:54, the watch from 12:50). The reorg-unwind fix's 13:30 clock met at 12:48 on the same commit. The attack pass at 12:5x BST, the ends brought in: F1's 10^6 was one 40-thread census on build-4 (35 h); the harness now takes --start (attack-v5-frozen ebdb7d4a, smoke-tested: a 20-program census from index 5 writes rows 5 to 24), so the census is split by index range: build-4 keeps indices 0 to 349,999 (its running census, stopped by pid when its progress line reads 350,000; the flushed census.csv holds the lower range) and build-2 runs 350,000 to 999,999 at 80 threads under class measure (binary 42ee04c7, held since 12:48:40 BST after waiting 362 s for the pool to free on its own, no pre-emption). Both halves end about 23:30 BST. F9's six chunks hold on build-4 (48 cores); when build-2's F1 ends tonight the F9 remainder re-splits onto build-2 by seed range (rows keyed by seed, nothing lost), bringing F9's end from about 17:00 BST tomorrow to about 06:00 BST. Cores held: build-2 80 (F1 upper range), build-4 88 (F9 48, F1 40); build-1 and build-3 untouched. Partials at 17:00. RED, a first, at 12:48 BST: Devnet 3 STALLED AT THE CLASS V5 FLOOR. The seed's virtual DAA read 68,403 at 12:49:11, 12:50:23 and 12:51:09 with one sink (07055360), the last block accepted at DAA 68,399 as class v4 at 12:48:14; nothing at 68,400 or above reached the seed, node1 or the observer, no node logged a PoW rejection: no miner found an epoch-19 block on a chain that ran one a second. The nodes held epoch 19's state (the seed installed the streams for epochs 18 and 19 from its snapshot at 12:30). The cause (the fleet lane, 12:52): every miner's --worker is the hive package's igneum-worker-cuda, which runs generators 2, 3 and 4 only; the class v5 kit's worker (82b19cbde8557ea5, the one every v5 gate ran on) was never on any miner's worker path, only its packs were placed; the prepare of epoch 19 fails and the miner sits at 0 MH/s while the templates flow. The fast-time harness crossed this boundary green four times on pairs, which tests the node and the CPU engine, not the fleet's GPU workers or kits. The fleet places the kit worker on every box now; the 0.3.25 hive package and Windows payload rebuild with the kit's workers by 13:30 (the build-server lane); the Mac Metal worker's generator-5 read with the v5 lane by 13:10. The pin and the minute wait on the chain moving and the rebuilt packages; the 42ce0f07 gate set green, the matrix running, the ceiling cut's publish limit (DAA 75,600) standing still while the chain does. GATE RULE for the next cut (the record's and release-rules'): a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; the packs' presence and the kit's own tests never stand for it. The 0.3.24 move's read-back ("36 of 36 FETCHED on the pin") was a node reading; no reading of a worker preparing class v5 existed before the floor. The research lane at 12:5x BST: section 10 ("the floor") open in the class v6 document (counter-asic-4 after 91117093) with each floor lane's term, what the document holds measured for it, the default at 19:30 and the row owed; two measured rows the floor lanes start from rather than re-derive: the SM-sparse lane from 20.3b (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw, 460 against 451 W; 99.8 percent of class v3 at 4 W less; watts minus idle per MH/s never below base; the sparse shapes collapsing at the 1,300 lock; its new work the breakdown of the 99 W an idle SM does not save and whether an occupancy shape at full SM count moves it; the worker variants sp-w and the card-free --list-race check on counter-asic-4); the k lane from 15.1a (the GPU side measured per counted op: ARX 11.3 / 6.2 pJ, mul 13.9 / 8.3, mulhi 39.6 / 21.0, prmt 22.3 / 11.5, lop3 24.1 / 13.0, shfl 55.8 / 29.4, fp32 FMA 9.2 / 5.2, the int8 tile 1.4 to 4.1 per MAC; only the chip side claimed; the mix that maximises k priced against the GPU's own per-family cost, the shuffle 4.9x the add on the card). The thirty-ninth landing on master at 12:54 BST (26a3cbe6): the standing rule in CLAUDE.md. The node lane at 12:5x BST on the stall: the worker's refusal line is "program pack generator 5 is not a generator version this worker runs (2, 3 or 4)", faulting at 0 MH/s from the first epoch-19 template; the kit's class v5 worker was benched on 24 cards this morning and never placed on any miner's --worker path; the nodes read 0 PoW rejections and hand the right template (the CPU id-read from build-1 confirms epoch 19 as class v5). The fleet places the kit worker and its pack on every mining box, w-target first; the chain moves when the first card prepares. The record's lesson: a worker that cannot run the next class must refuse at the pack prepare, loudly, hours before the boundary (the plug, tune, play rule), and no hive tar ships without the class the object names. A second bug read off the stall: the pool admits at the next block's DAA (chain id 4464 past the floor) while eth_chainId answered the executed tip's id (4463 with the tip stalled at 68,399); the fix (eth_chainId and net_version answer the id a transaction sent now must carry, the status carrying both ids, the known-failed test on the stall's shape) a wip under its exec suite at gate priority since 12:54:27, landing as the SECOND commit on release-0.3.25-node over 42ce0f07 (nothing consensus, digest 1b37cb9d unchanged), its full gate set and fast-time pair by about 13:15; that commit the pin's node sha, 42ce0f07 if it reads red. THE CROSSING READS CLEAN. The first class v5 block (epoch 19, epoch seed a75c5624) was accepted on build-1's seed at 12:57:40 BST, 9 minutes 26 seconds after the last class v4 block, the minute the fleet's first kit worker prepared; then 13, 14, 71, 165 and 78 blocks a minute (the backlog clearing, the rate settling), DAA 68,547 at 13:01:37; seven stale-pack attempts refused between 12:59:24 and 13:01:10 (the harness's known-failed shape), none since; no state-wait, catch-up, stale-dataset or digest line on the seed, node1 or the observer; no honest block refused. Devnet 3 runs class v5 at byte 6 as the 0.3.24 object names (the v5 signal share 1,407 bps at the floor; the seed's template at 13:1x: epoch 19, class 5, version 1538, era the genesis, day 20,734; the executor serving epoch 19's stream, 869 records, root 0x1fd55139...4561). The pairing check holds three ways: the kit's igneum-pow (8f481459's tree, the freeze's hash object) names attempt 2, program id 3d375a55029e7e60 for epoch 19; the node lane's 0.3.24 pin miner (igneum-pow 1c420786) read the same id live at 12:56; the DMG's Metal worker on the Mac prepared epoch 19 against the live seed with the same id (869 leaves, 26 MH/s). The stall's two causes, both miner-side, neither in the object: every fleet miner's worker was the hive package's CUDA worker (generators 2, 3 and 4; it refuses a generator-5 pack with a line, the miner at 0 MH/s retrying, loud in the log and the plug-tune-play fault only on the dashboard), the DMG's Metal worker from the freeze's tree the same (the v5 worker path is the v5-kits lane's 5c9ed959, in class-v5 from e208dfea on; the freeze is the hash object, not the hosts); and a miner not told its node's exec RPC port cannot prepare class v5 at all, so every fleet loop needs --exec-rpc. The fix: the kit's workers (zip 65b47211) and --exec-rpc on every box; the hive, Windows and Mac packages from the kit tree (the hive and Windows payload carrying d84b1b6c / be23bc68 and e1bfd582 / 55722527 on the worker path; the Mac side closed on release-0.3.25 44d1815a, proto-metal from class-v5 79799452). The stall's cost: 9.5 minutes of blocks and every prover's share for that span. The standing rules from it (release rules 16 and 17 on ship-docs-0321 cb570365): the kit worker and --exec-rpc on every miner loop before any class boundary; a worker that cannot run the object's next class refuses at the pack prepare, hours ahead; a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; memory against the container's cap. All of it on the class v5 page's section 0 at class-v5 2494f3f8 (both mirrors 12:59, master merged, its full gate running by pid). The second node commit 5f316c21 on release-0.3.25-node (both mirrors 12:56:22 BST) = 42ce0f07 plus the chain-id answer (eth_chainId and net_version return the id the pool admits at, the next block's DAA, 4464 past the floor; the status carrying both ids; the known-failed test on the stall's shape), nothing consensus, digest 1b37cb9d unchanged; EVERY GATE GREEN at 13:04:05 BST (build 12:58 rc=0, igneumd 3812b2a2, /srv/artefacts/0325-5f316c21/node-lane; consensus 134, exec 54, core 177, pow 19, p2p-flows 38, miner 29, all at gate priority; the Devnet 3 canary with digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged). 5f316c21 IS THE PIN'S NODE SHA. The one input before the pin line: the fast-time SUMMARY on 42ce0f07's artefact (the run waited 796 s for build-1's pool, 88 of 88 leased at or above v5, nothing to pre-empt; running since 12:55:54, v5 from epoch 8 at 13:04:19, the line about 13:10), a run on 5f316c21 after it. The shipper's close: the app tip 9a71e784 (crate 89e83df2), the DMG 43cd8c94 staged, the tarball 1ae1810d, move id m5f31-1; the pin about 13:25 after the SUMMARY, the matrix and the hive; the minute about 14:00 to 14:20 inside 14:53. The TESTNET_PARAMS v5-at-0 re-cut's default moved under the rule by the node lane: it lands through its full gate set on release-0.3.24-node 30 minutes after the seed reads the first ten class v5 blocks accepted clean, so at 13:32 BST unless main says otherwise before then; a red crossing would have meant no re-cut. The audit lane's 9070 XT row on master at f37f497b (12:55 BST, gate green on 33b0ad06), ahead of 13:30: 18.96 MH/s, watts "149.3 with the 0.3.25 knob (195.8 stock)", 0.127 MH per watt, the tuned text with the 24 points' flatness and the date, the source the status row with the job id; the note carries the grid's stock point beside the app's 202 W reading of 7 October, the two single-lever points, and names both 5090 denominators (3.5x behind at the class v4 1,200 MHz lock, 0.43; about a fifth at the 1,300 knee, 0.60); the qualifier drops when the cut serves. With f37f497b: the complete class v4 watts rerun (22 rows), the /income calculator, the /economics page, the governance line, the two served-text corrections with their ledger rows. The build-server lane has it to deploy. The hash lane's kit b on the 5090 (12:49 to 12:58 BST, all PASS; with the research lane and the floor lane): the mixer multiplier x8 against x16 costs the GPU nothing (137.73 against 137.72 MH/s, 320.2 against 320.1 W unlocked; 127.44 against 127.46, 212.0 against 211.7 W at 1,300), so the verifier's 1.86x per doubling is the whole cost of that draw; the shuffle-heavy table on the base program moves 7 W unlocked and nothing at the lock (a 2 percent term); the pinned class v3 program at 2, 4 and 8 GiB costs a tuned 5090 5, 11 and 14 percent of rate at the 1,300 lock (4, 8 and 10 percent per hash) and 3 to 4 percent unlocked, which corrects the layer 2 line: the size term is real at the knee (the page-walk cost the latency-bound regime exposes). Kit c (the multiply-heavy table) running; kit d (both tables inside the shadow block, the row layer 1 needs) exports on build-2 and runs after, about 13:45. W = 8 for the floor lane: the crate's width set is three fixed word widths (1, 4, 16; WIDTH_WORDS, the mix arrays, the emitters for CUDA, OpenCL and Metal, the verifier's fold), so a 32-byte load needs a generator and emitter change before any pack exists (two to three hours of crate work on the readwidth line plus the PC 1 row); the ask to main with its default: say so by 14:00 and the lane starts it on the readwidth branch (a research class, no consensus object); silence means W = 4 pins and the floor lane hears so at 17:30. The F8-256 attribution runs for p212 and p225 on build-3 (the attack-pass crate d08e1e0f built there at 13:01), rows by 16:00. Main's ids for the floor lanes, for the record: SM-sparse af65f8187569666d0, shadow k a3c9601a6d4686fe1, SRAM and dataset floor acecab7195ea66621, honest denominator a4d39e20a0762646d, invention a734c5330f17be3c2; the research lane delivered the two starting rows to each with their 19:30 defaults. Two more master-only deploys from the builder stream, checks ok (38 miners rows, 18 asserted pages, the checkpoint API and the explorer stats API): d28cf8fc at 12:50 BST (the explorer wording c4ca746f, the audit lane's ace5c294 with /economics, the /income calculator and the class v4 watts rows, the DEX lane's 9126e4d6 and 825d19bd) and f37f497b at 13:04 BST (the reference-apps b7f1e0d7 with /oracle's BLS-verified root, the 9070 XT knob row on /miners). No chip text changed beyond the audit lane's own landings. The fortieth landing on master at 13:14 BST (90b180f2). Main's word on W = 8 at 13:1x: start it, research class with no consensus object; the order on the hash lane: the 0.3.25 lock rows and kit b first, then the readwidth generator and emitter, the PC 1 row by 17:30; a miss means W = 4 pins, the floor lane told, the W = 8 row later as a v6 sub-version check. The 13:32 testnet re-cut on its default. A RED THE MOVE ITSELF WOULD TRIGGER, read on build-1 at 13:05 BST by the node lane: a node re-executing from genesis (the fleet's 21 re-walks now; every node at the move under the snapshot stamp rule) has its executor thousands of blocks below the chain, so its pool admits at the executor's next DAA, names the old chain id 4463 below the floor, refuses every relayed transaction signed with 4464 as a state-free fault and disconnects the relayer as misbehaving ("wrong chain id: expected 4463, got Some(4464)" on the seed and node1 from peers at 13:05); for the length of its walk, about 8 minutes, it drops every peer that relays a transaction, and at the move every node would do it to every other: a partition. The fix, a wip under its exec suite at gate priority since 13:08:06: the admission height is the larger of the executor's next DAA and the chain's virtual DAA plus one (eth_chainId, net_version, eth_sendRawTransaction and the relay read it), and a mismatch between the network's own two ids is a refusal, never a strike; the known-failed test is the re-walk's shape. It lands as the line's third commit over 5f316c21 (nothing consensus, digest 1b37cb9d), the full gate set and the fast-time pair on it by about 13:35; the pin waits on it. The second thing in those logs is the stale class, not a bug: the 21 nodes with a divergent execution state compute a divergent class v5 dataset, refuse every honest v5 block as invalid PoW and ban build-1's seed for an hour ("Reject(BlockInvalid)" on the fleet's side), cured by their re-walks in progress; a node that cannot check a v5 header for want of the epoch's state holds off, as designed. The crossing is clean on the honest side; the chain runs. The fast-time crossing on the 0.3.25 pair 42ce0f07 (12:55:54 to 13:08:50 BST) read green on every claim (rung 1 at 13:02:22, v5 at byte 6 from epoch 8 at 13:04:19, 12 of 12 ids equal to the CPU verifier's, the stale node refused, the restart step resynced in 19.1 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); its SUMMARY read FAIL on one harness check: the final epoch's row held one miner's line when the run ended at that epoch's boundary (the id equal to the CLI's); not a node finding; the check now reads the final row by its id (v5-fasttime 130562a2); the clean rerun on the same artefact from 13:1x, SUMMARY about 14 minutes after its lease. Lane D's 17:00 cut LANDED on master at 238100b0 (13:13 BST), gate GREEN (73 checks, 355 s) on 2a595e1b, four hours early; the research lane has the layer-4 line; docs/analysis/class-v6/family-gate.md carries the measured coverage (24,000 drawn eras, per stratum and per axis, the bound arithmetic), the rows, logs, scripts and the harness diff under docs/analysis/class-v6/logs/. Build-3: w4lossybase done (3,000, 0 exhausted), shape256 1,910 of 3,000, shape64lossy 1,895 of 2,000, w4shape64 queued, then the point-B live census on the family attack-f8 build (74784428); build-1 the four lossy-share strata near done and the point-A live census. The class v5 lane's full gate on class-v5 2494f3f8 (the crossing row, master merged) GREEN, 73 checks in 407 s at 13:06, run to its end by pid, nothing killed. The third node commit inside the shipper's 13:20 clock: d5b68fae on release-0.3.25-node, both mirrors, 13:14:12 BST = 5f316c21 plus the admission fix (a transaction admitted at the larger of the executor's next DAA and the chain's virtual DAA plus one on the relay, eth_chainId, net_version, eth_sendRawTransaction and the status; a mismatch between the network's own two chain ids a refusal, never a strike; the known-failed test on the re-walk's shape), nothing consensus, digest 1b37cb9d unchanged, pairing 1c420786; exec 54 of 54 and the kaspad check green on the same tree before the squash. The full gate set at gate priority from 13:14:19, every line by about 13:26; the fast-time pair asked on it; the 42ce0f07 rerun's SUMMARY (about 13:24) the gate's record on the same object. The pin's node sha d5b68fae if green, else 5f316c21. The steward's 0.3.25 matrix at 13:17 BST: node 5f316c21 with app tree 89e83df2 GREEN on all seven suites on build-2, build-3 and build-4 (no RED); 42ce0f07 complete green on the same three; build-1 out; at 13:21 the third sha d5b68fae core and exec GREEN on the three boxes, six of six: the pre-pin suite read closed. d5b68fae reads every gate green at 13:22:43 BST (build 13:15 rc=0, igneumd b0e7b8b5, /srv/artefacts/0325-d5b68fae/node-lane; p2p-flows 38, pow 19, consensus 134, exec 54, core 177, miner 29 at gate priority; the Devnet 3 canary digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged): THE PIN'S NODE SHA IS d5b68fae. The fast-time SUMMARY PASS (cross-0325-42ce0f07-2) at 13:22:57 BST on the 0.3.25 pair 42ce0f07 (13:10:07 to 13:22:57 on build-1 under class v5: rung 1 at 13:16:33, v5 at byte 6 from epoch 8 at 13:18:43, the stale node refused, the restart step resynced in 11 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); the d5b68fae pair running side by side since 13:16:13 on its own cores and port base, SUMMARY about 13:30, the last input before the pin line. The reading behind the fleet's partition line at 13:17 BST (hub-1 at one sink, dn2-1 alone on its own branch, w-poison a third, dn3-g2 and dn3-q03 stuck at DAA 68,403 refusing every v5 block): epoch 19's class v5 dataset derives from the execution state after the epoch's reference block, the last chain block below the cut 19 x 3,600 - 600 = DAA 67,800: chain block 28,462, hash a75c5624 (the epoch seed), state root 0x1fd551393d (build-1's seed, node1-dn3 and the fresh node agree; the kit's stream names the same root). Any divergence of state OR numbering between 26,294 and 28,462 puts a node in a cluster that refuses the other clusters' proof of work and bans their relayers for an hour; root-equal at 26,247 was not the gate. The census now reads hash and root at 28,462 on every box (epoch 20's height moves to the last block at DAA at most 71,399); every cluster but the one on a75c5624 / 0x1fd55139 re-walks; build-1's observer node, the explorer's only source, is one of the drifted (its 28,462 another hash at DAA 67,787: the orphan-append class during its 11:22 re-walk, so the explorer's numbers are off by a few; the shipper has it). The cure is the move itself: every node restarted on the pin's binary re-executes from genesis under the snapshot stamp with the ring self-check running and lands on the one state; the gate on the minute is the fleet's census at 28,462 after the re-walks (31 boxes on the one state at 13:19:44, the rest the numbering class the move cures), with an unban of every held address per box once its root reads equal, since bans persist on disk across restarts; a box whose root there differs after a re-walk on the pin's binary is a new class and a stop. Lane D's measured correction at 13:2x BST for the full report: the lossy-corner exhaustion is a shape-256 interaction, not corner-wide: at the lossy cap the per-candidate rejection is 0.877 at shape 64 x 108 (0 of 2,000 and 0 of 1,000 eras exhaust), 0.923 at 128 x 54 (1 of 1,010), 0.980 at 256 x 27 (36 of 990, 3.6 percent; 24 of 670 at width 4); at r = 0.98 the independent-attempt figure is 0.98^256 = 0.6 percent, so the per-era correlation is about 6x, not the 1,000x the mixed-shape average suggested; the band rule stands either way (lossy families never raised), and the cheapest shape for the draw is also the fastest on the cards. The hash lane's attribution: run 2 (the attack-pass branch's own crate) reproduces p225's 1.2452x but not p212's (1.57x against the gate's 1.19x, a different draw, the crate differing from 1c420786); run 3 on the 1c420786 crate is the authoritative one, running. The W = 8 pow suite on build-2; the three state-term packs (w4, w32, w64 on +sh256x27+state, the node1 state file, --era-widths 4/8/16) export on its green; the read-width kit (those three, the v5-genesis pack, the two 5 October packs, which are string-seed class v2 packs the worker accepted on 5 October, no re-export) runs on PC 1 after kit d; the L2::64B hint variant is not in the worker exes, so it is lane 5's kernel line, nothing to build. STANDING RULE from the founder relayed by main at 13:2x BST, applied to every lane the coordinator runs and every default clock: work as fast as possible; anything doable in 30 minutes to 2 hours gets a clock inside that window, never a target hours out; fan work out (one pod per point, one box per variant) rather than queue it. The floor close is 15:45 BST. The coordinator's re-read of the 16:00, 16:30, 17:00 and 19:30 lines: the F8 attribution rows 14:00 (run 3 running, three minutes a census); lane C's drawn-era numbers 14:00 (an 80-s census on build-4) and its cut 15:00; the class v6 per-tier cost rows and layer 4's tests 14:30 (kit d about 13:45); the W = 8 PC 1 row 15:30 (the crate work fanned: the suite on build-2, the exports on build-2's slot, PC 1 the moment kit d closes); the floor lanes' rows 15:30 for the 15:45 close; the synthesis and the served-line review table 16:30; lane D's full report 16:30 with every stratum fanned across build-2's and build-4's free cores rather than queued on build-3; the DEX lane's swap UI 15:00 and the Sepolia verifier 16:00; the reference apps already served (b7f1e0d7 at 13:04). Main's word at 13:2x BST to every lane: while GitHub is suspended, landings go to the box mirror's master through the gate, never to Forgejo master, which is a rewritten copy replaced at cut-over by the box mirror's final tip; pushing a branch to Forgejo for safekeeping is fine, landing there is not. Relayed to every lane with the pulled clocks. The SRAM and dataset floor lane's row is complete at 13:18 BST, two hours inside its pulled 15:30 clock: the full row at 7bc9de4b and the clock references at 8e9588de on the box mirror's branch class-v6-floor-sram (safekeeping, no master landing), gate green on every push, all arithmetic on build-3; docs/analysis/class-v6/floor/sram-and-floor.md. What the 15:45 close carries: the capex wall on the corrected project floor (no chip project below about USD 23 M a year of miner revenue, IGN 0.03, USD 62 K a day; every DRAM-board project at a third of the network above about USD 340 M a year, IGN 0.44, USD 0.93 M a day, where the SRAM project also starts); the read width as the only wire lever on the SRAM die (66x at the hash's 4-byte width at zero shadow, 44x at W = 4, 31x at W = 8, 19x at W = 16 if the 5090 passes the PC 1 job, 36x at the measured w64 row); the shadowed die at 6x to 10x at the honest cards' whole latency shadow on the k lane's synthesised core, kept beside the k lane's sequencer-core row as the floor-k worst case, never under 2x by any shadow; the floor as a ticket lever (5.5 / 8.5 / 11.5 GiB = 3, 5, 6 reticles, USD 1,500 / 2,500 / 3,000; USD 5,000 per store is 20 GiB and retires every card under 32 GB; the 5090 pays 4 / 8 / 10 percent per hash at its knee and the M5 Max 12 / 20 / 22 percent of rate at 2 / 4 / 8 GiB, both measured); the four other candidates (per-era and per-block re-fill, straddling atoms, a second hot table) dead with numbers. Amendments after the close, each labelled with its time: the W = 8 or W = 16 PC 1 row (the hash lane), the k lane's shuffle row and its re-fold, the Apple rate curve past 8 GiB. The DEX lane closed with every clock met before the pull, all on the box mirror's master through the gate: the AMM live on Devnet 3 at 12:0x BST; the swap UI serving at igneum.network/swap since 11:36 with the Igneum Wallet bridge live from the 12:50 deploy; the Sepolia certificate verifier live at 13:3x (0xAf74f3F512081291D663Bb1d6b6d37E99e37D744, suite 10 of 10 on build-3, Devnet 3 checkpoint 2127 recorded final and one Devnet 3 balance proven on it); the one named gap: no on-chain link from checkpoint to state root yet (docs/bridge/light-client-bridge.md); final master 825d19bd. The forty-first landing on master at 13:35 BST (937cc82ae); during its branch push the hook "died of signal 15" once more (the merge's own gate ran green and landed), so a kill by name on the Mac still reached a gate at 13:3x: the steward's TERM-sender log is the read. STOP ON THE PIN d5b68fae at 13:29 BST, the fast-time pair: SUMMARY FAIL (cross-0325-d5b68fae), the failing check v5_ids_equal_the_cli_v5_id, a node finding: on epoch 9's attempt-3 seed ec0a8cf9 the d5b68fae miner and nodes drew program id 65b57e3b847d362e (its nodes accepting 4 of 4 on it) while the freeze CLI 1c420786 and the ab6f980b CLI both draw ebf64b32e2d84c5b, state or no state; the three other v5 epochs agree with the CLI. A node on the freeze's igneum-pow would refuse that epoch's blocks: a split on the first divergent seed, a chain split class. The 42ce0f07 and 39f127a1 PASSes met no such seed, so they do not clear it. The cause from the box's build log: the d5b68fae, 42ce0f07 and 5b673577 pairs were built "pairs_with": "igneum 05b21835 (detached) with uncommitted igneum-pow changes", not against the freeze 1c420786 (39f127a1 and c8f9b383 were, against ca3-v4-node commits 4c24903e and 0e4ec18a); every 0.3.25 node binary embeds "igneum-pow-v5/src", not the freeze's crate; rule 7's pairing broken in the node lane's build path. The orders: the node lane folds the freeze pairing (a clean rebuild from the freeze's exact igneum-pow, the build row's pairs_with read before any lease) and the ceiling re-cut to 90,000 into one commit (sha by 14:05, the gates and a new digest by 14:20, the SUMMARY with the seed in the set by 14:35); the build-server and fleet lanes read the live 0.3.24 miners' pairing path by 14:00 (if the live network carries the same divergence, the move is its cure before the first attempt-3 seed; 5b673577 is the live pin); the artefacts rebuild on the new sha; the pin about 14:35, the minute about 14:55 to 15:10 BST. The coordinator's order to the v5 lane: the pairing read-back on the rebuilt pair by 14:30 (the freeze CLI against the new sha's miner on ec0a8cf9 and the three other v5 epochs, id for id, and the live miner's path the same way). The record's rule for the pairing gate: the fast-time set carries an attempt-3 seed on every run (the epoch seeds of a run are its block hashes, so the divergent seed cannot be forced; the pairing row is the check that reads first); a pair's build row names its igneum-pow commit, and "uncommitted changes" in pairs_with is a refusal before any lease. Lane D's fan-out at 13:4x BST, one stratum per lease, class measure (every box's pool read 0 free at submission, each waiting in the measure class ahead of adv work): build-2 w1band (width 1 under the band, 3,000 eras, the fg7 harness with the refused-ratio column) at 16 cores, and the mixer verifier rows mx4m4g, mx4m8g, mx4m16g with the 256 x 27 shadow, one core each (the x16 row); build-4 w4shape64 (3,000) at 16 cores; build-3 the point-B live census (64 seeds at 2^24, shape 64 x 108 with a band era's weights) at 24 of 64 seeds PASS, and w4band (width 4 under the band, fg7) at 8 cores, 179 of 3,000; shape256 (3,000) and shape64lossy (2,000) COMPLETE; build-1 untouched (the point-A live census at 31 of 64 PASS, no test fired; the four lossy-share strata complete at 3,000 each); build-3's queued copies killed and their partial rows marked PARTIAL. The full report by 16:30 on the mirror's master through the gate; what has not finished by 16:00 goes in as a partial with its count. The corrected line for main: at the lossy cap r = 0.877 at shape 64 x 108 (0 of 3,000 across the strata), 0.923 at 128 x 54 (1 of 2,000), 0.980 at 256 x 27 (3.3 to 3.6 percent of eras in three strata). The hash lane's clocks at 13:4x BST: p225 reproduces on the 1c420786 crate (1.2452x against the gate's 1.2457x, by-site rows in hand, the close by 14:00); p212 does not: the tool at d08e1e0f over the 1c420786 crate draws a program at 1.5715x with a hot set ("site instr 5, r7, one-one-bit, last writer add at 4"), not the gate's 1.1915x attempt-4 program, because the gate ran a chain path (class v5 with the dn3 state) the pushed tool has no flag for; the attack-pass lane's exact command asked by 13:50, default: p212 reported as unreproduced on the pushed tool, labelled so. Kit d: the first two exports hung on a build-2 slot (a stale lock of the lane's own run, cleared); take 3 direct and bounded, packs about 13:45; PC 1 held by floor lane 1's two jobs, so kit d's job starts the minute the card frees and closes 8 minutes later (rows by 14:00 only if PC 1 frees by 13:50, else PC 1's free minute plus 10, inside 15:30; past 15:30 the microbench arithmetic stands). The per-tier cost rows and layer 4's tests delivered at 12:0x (scratch v4/ca4-v6-cost-rows.md), the kit b and c numbers folded in at 14:15. W = 8: the suite on build-2 (restarted 13:23 after a slot wait); the three state-term exports follow it on the same box; the PC 1 read-width job after kit d; the 15:30 row holds if the suite is green by 14:00 and PC 1 frees by 14:30, else W = 4 pins. The explorer lane's correction at 13:4x BST: the explorer's source is no longer the drifted observer: the build-server lane re-pointed the indexer unit, the observer and the public RPC at node1-dn3 (EVM 26870) at 13:25, and the three indexer tables were wiped and refilled from node1-dn3 from chain block 0 at 13:27 (about 3 min); balances, receipts and accounts are node1-dn3's, the DAG tables the observer process's reading of node1-dn3 since 13:25. The notice landing by 14:00: the header names node1-dn3 as the source since 13:25 BST, the observer drifted at DAA 67,787 and re-executes from genesis, a block list read before 13:27 may differ by a few blocks until the move; the same line on /block and /tx. eth_chainId on node1-dn3 answers 4464 since the floor, so the explorer's chain id is read from the node; every page printing 4463 as a fixed string (/build, /swap, /metamask, the nav's title) is one off, told to the build-server lane at 13:28. The attack pass's split under the fan-out rule, running from 13:30 BST, every lease class measure: F9 (900,000 seeds left on 1c420786) as twelve chunks: build-4 keeps the lower 85,000 of each of its six 150,000-seed ranges, restarted from each chunk's lowest missing seed (rows keyed by seed, a merge dedupes), six leases of 8 cores; build-2 takes the upper 65,000 of each range, six leases of 6 cores. F1 (10^6 class v5 programs): build-4 keeps indices 0 to 349,999 at 40 threads (at 76,000 at 13:19; stopped by pid at the 350,000 line), build-2 393,662 to 999,999 at 52 threads (its first 47,000 rows from 350,000 kept, merged by idx at the end). Cores held at 13:36: build-4 72 (F1 40, four F9 chunks of 8; two chunks waiting on lane D's 16-core w4shape64 lease there), build-2 24 (four F9 chunks of 6; F1's 52 and two chunks waiting): build-2 contested (lane D's w1band 16, the invention lane's per-load acceptance census on 0ab27582 48, the hash lane's attribution at class adv, the hash lane's igneum-pow suite at class release for 88 cores, which pre-empts every measure lease there when it starts; the class order decides). Ends at the measured rates if every lease holds: F9 build-4 halves about 04:45 BST, build-2 halves about 07:00; F1 build-4 range about 23:20, build-2 range about 05:40; the build-2 ends slip by their waits. The 15:30 reading carries the counts and re-stated ends. THE EXPOSURE READ at 13:50 BST (the node lane's fingerprints, the shipper's correction): THE LIVE NETWORK IS ON THE FREEZE. The igneum-pow tree each binary linked is the untracked igneum-pow-v5 copy beside its release worktree (the .cargo/config.toml paths override); every copy fingerprinted against git archive 1c420786 igneum-pow by two methods (the node lane's: find src -name '*.rs' | sort | xargs sha256sum | sha256sum; the build-server lane's: find . -name '*.rs' | sort | xargs cat | sha256sum | cut -c1-12): the freeze reads cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 and 29106189ca1e; the 0.3.24 line's worktree (vendor/igneum-node-0321, where 5b673577 and every 0.3.24 pin was built, the gate pair a3b1a2c9/cfa9f5ca, build-1's seed, node1 and the observer) reads the same on the Mac and both boxes; the fleet's shipped pairs the same (29106189ca1e); the kit workers on the freeze (the freeze CLI built at exactly 1c420786 on build-1, binary sha256 7ba781db, names Devnet 3's epoch 19 as attempt 2, program id 3d375a55029e7e60, equal to the 0.3.24 miner's live read). So no live node or worker diverges, no attempt-3 seed can part them, epochs 20, 21 and 22 are safe, no hub-side holding action; the shipper's 13:45 line to main withdrawn and corrected. What diverged: the 0.3.25 line's worktree (vendor/igneum-node-v5) carried a pre-freeze copy (fingerprint e01ea128fab1: accept.rs without the (c''') per-site distinct-index floor, MIN_DISTINCT_RATIO_V5 0.995 and its HotItemSite refusal; generator.rs and memhard.rs older); every 0.3.25 gate artefact c6629572 through d5b68fae was built on it, none shipped; on an attempt-3 seed it draws attempt 2's id where the freeze goes to attempt 3, the fast-time FAIL; replaced by the freeze's tree on the Mac and both boxes at 13:34 (fingerprints equal). The builds.jsonl pairs_with rows name the parent repo's HEAD, not the override copy, so they never said which tree was linked; the fingerprint is the only reading. The predictability: an epoch's attempt and program id are a deterministic function of its epoch seed, fixed 600 DAA (ten minutes) before the epoch starts, so any two trees compare ahead on every seed by both CLIs; across the freeze and the pre-freeze tree the hash lane's census puts the share of seeds that differ at 2.4 percent (112 of 4,600), a per-epoch roll that only matters where a pre-freeze binary is live, and none is. The boundaries at 1.0 DAA/s from the 13:01:37 read: epoch 20 at DAA 72,000 about 13:59 BST (seed fixed 13:49), epoch 21 at 75,600 about 14:59, epoch 22 at 79,200 about 15:59. RULE 19 and the rebuilt sha inside the shipper's 14:05 clock: 6ccaf9e9 on release-0.3.25-node, both mirrors, 13:41:28 BST = d5b68fae plus rule 19's build-time half (consensus/pow/build.rs fingerprints the linked igneum-pow tree by the shell's method and refuses the build unless it equals packaging/pow-freeze.txt, "cbc5bd0a… 1c420786 class-v5-freeze 2026-10-07", unless IGNEUM_POW_FREEZE_CHECK=0; IGNEUM_POW_FINGERPRINT in every binary's strings, on igneumd's start lines and igneum-miner's engine line; the handshake field on the next commit with its own gate) and the Devnet 3 ceiling re-cut to 90,000 (the publish limit DAA 82,800, about 16:53 BST; the digest moves, named by the canary). The wip's check, pow and core suites read "igneum-pow fingerprint cbc5bd0aa10585c8 (the freeze)" at 13:40. The full gate set at gate priority from 13:41:35 (the build on build-1 with the fingerprint strings read back from both binaries, six suites on build-2, both canary sets), every line by about 13:55; rule 19's known-failed case on build-2 beside it (the pre-freeze copy under the override must fail the build); the fast-time lane's watcher fires on the artefact (about 13:45), reads the fingerprint string before its lease, its SUMMARY with the attempt-3 seed about 14:05; the v5 lane's flip case (the harness taking POW_BIN, the freeze CLI, beside FORK_BIN) reads every v5 epoch's id on the pair against the freeze CLI, 13 minutes a case, within 15 minutes of the sha. The testnet v5-at-0 re-cut landed by its default at 13:32 as 3ffcf83b on release-0.3.24-node (its pairing the freeze), its gate set from 13:40:39, its digest from its canary. The pin line follows 6ccaf9e9's last gate and the SUMMARY. The v5 page's section 0 carries the STOP and the pairing rule's new line at 3b894a4d. The counter-asic-4 documents landed on the box mirror's master at 13:35 BST as 868fea52 (full gate GREEN 73, the stamp on c21f1f38): docs/analysis/counter-asic-4-research.md, docs/design/class-v6-rotating-family.md (the branch's text at 08641162), docs/analysis/chip-model-v3.md (5.12 and the capex correction), tools/ci/export-exclude.txt (+4); igneum-pow/src, igneum-pow/tests and proto-cuda stay on counter-asic-4; no served page changed. The research-landing lane's next: floor-sram (8e9588de) about 13:55 from the Mac on its green stamp (the full gate RED 5 of 73 on build-3, all box-environment classes, the steward told as owner: the gate is the Mac-side script that reaches the boxes from inside), floor-k with tools/chip-model/rtl about 15:45, floor-sm documents by 15:30, the denominator and invention lanes on their words. The 6a5fa763 deploy at 13:42 BST (the explorer's source notice and chain id from the node, b092fa17; /swap reading eth_chainId at load, 46eb9e4b; /metamask on 0x1170 and the public RPC, the nav pill, /faucet and /build on 4464 with the floor dated): Devnet 3's eth_chainId moved from 4463 to 4464 at the floor; checks ok, 19 asserted pages. Lane C's 14:00 numbers: the no-era half in hand on 0ab27582 (the sound form 0.927, 234 of 256, unchanged on the fixed instrument; the control sh256x27 now reads sub-version 3's own 0.682 because the merge brought master's (a') pass to that spelling, so the two sit on one instrument); the era sweep on build-2 on the first free cores; the 15:00 cut after it. The attack pass at 13:46 BST: build-4's F1 lower range stopped by its pid file (83,000 distinct rows kept from indices 0 to 349,999) and restarted at 8 threads from its lowest missing index 78,082 (the 4,900 interleaved rows above it redone and deduped by idx at the merge), freeing 32 cores for the census lane; at 15:30 the shard restarts at 40 threads the same way; its end moves from about 23:20 to about 00:15 BST. A print-only move of the sha at 13:45 BST: c9ad753a on release-0.3.25-node, both mirrors = 6ccaf9e9 plus igneum-miner embedding the full IGNEUM_POW_FINGERPRINT=<64 hex> string on its engine line (igneumd carried it; the miner's binary had only the sixteen-character start-line form, so the pair's read-back on both binaries failed on the miner); no code path, object or digest change. The Devnet 3 digest on the pin: 2066aa57505e5ecbd585d061364abb0032d5b5b29cc41c54f4b38cb81c2ba6eb (the ceiling at 90,000; the publish limit DAA 82,800, about 16:53 BST); the fingerprint cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 (the freeze); the 0.3.24 pin refused both ways on its canary. Its full gate set at gate priority from 13:45:59 (every line by about 14:00, both binaries' strings read back in the build log); 6ccaf9e9's own gate set and rule 19's known-failed self-test by about 13:55; the fast-time SUMMARY on 6ccaf9e9 (the same node code and object) about 13:59 stands as the gate's record; the v5 lane's flip case on the pair follows; the pin line after the last of those. The forty-second landing on master at 13:54 BST (c340a9d4a). The shipper's pin candidate: c9ad753a on release-0.3.25-node (d5b68fae plus rule 19's build fingerprint against the freeze, the ceiling re-cut to 90,000, the miner's full fingerprint line; digest 2066aa57; the publish limit DAA 82,800 about 16:53 BST; the fingerprint cbc5bd0aa10585c8 in both binaries' strings); the app tip b5be4edf (crate 89e83df2); the gate set on c9ad753a by about 14:00; the fast-time SUMMARY on 6ccaf9e9 (the same node code and object) about 13:59; the matrix cells on 6ccaf9e9 stand; the v5 lane's read-back on the 6ccaf9e9 pair stands for c9ad753a; the fleet's binary the build-server lane's seed pair on c9ad753a (the freeze's crate, 29106189ca1e); move id m9ad7-1; the pin about 14:35, the minute about 14:55 to 15:10. PC 1's queue at 13:5x BST: floor lane 1's two jobs (floor-pc1-build-2 "build patched sp1-gpu-server", floor-pc1-restore) hold the card since 13:06; queued behind them, published and signed: kit d's fetch and run (9 minutes) then the read-width run (W = 4, 8 and 16 under the class v5 state term, each its own draw on generator 5 with the era and the node1 state, plus the v5-genesis reference and the 5 October w4 and w64; the W = 8 pack exported at 13:48 on the w8-v5 branch, efb68fce on the mirror, suite green; about 20 minutes). The coordinator's order: floor lane 1 names its end minute by 14:10; an end past 14:30 means its job yields the card at 14:30 (pid file, state restored first), kit d and the read-width run take 30 minutes, its job resumes after; so kit d's rows and the W = 8 row by 15:00 at the latest, inside the 15:30 close. The F8-256 attribution rows at 14:00 BST. p225 (the gate's 1.2457x): reproduced on build-3 with the attack-f8 tool at d08e1e0f over the pow crate at 1c420786 exactly, 1.2452x over the window model at 2^24 nonces, the hot-set verdict clear on both controls, the hottest item 0xb7e000 at 332 reads with no saturated or lossy source. By site: the excess sits at site 4 (instr 23, source r7, window 2^23 items, offset 1, last base writer mad at 21), 1.30 percent of its reads into the top 0.1 percent of items against 0.103 flat (12.6x), with site 9 (instr 37, r5, window 2^22, offset 2, last writer load at 36; the gate's predicted one-one-bit source) second at 0.38 percent (3.7x); every other site at its flat share. Both sites read full index entropy (15 of 15 and 14 of 14 bits) and a largest 256-item bucket at its window expectation, so unlike the morning's tail (a bucket concentration) p225's residue is a value-level concentration on specific items from a mad-written index, the class the gate's one-one-bit prediction names, carried mainly by the mad site and a quarter by the load site it predicted. p212 (the gate's 1.1915x, attempt 4): not reproduced; the pushed tool has no class, state or day flag, so its default path draws a different program for seed 212 (1.5715x with a hot set, the string-seed class v4 draw); the run on the gate's own line (its binary, day 20733, class v5, the dn3 state) on build-2 never started (0 of 12 cores free 13:29 to 13:54 with a higher class ahead; build-1 closed); the attack-pass lane runs p212 with --diag 1 on its own harness when its lease frees; default, p212 stays "predicted source only" in the record. No consensus object moves. THE PIN IS NAMED AT 14:08 BST: release-0.3.25-node = c9ad753a (the 0.3.24 pin 5b673577 plus igneum-miner keygen, the proof-record re-announce, the proving-fee ceiling switch at DAA 90,000 in the Devnet 3 object, the ring self-check every 30 s, the snapshot digest stamp, the vetoed-node status, the proof map's window, eth_chainId and the admission at the chain's height with the network's other id a refusal, rule 19's fingerprint, the testnet re-cut beside it); pairing the class v5 freeze 1c420786, fingerprint cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 read back in both binaries; Devnet 3 digest 2066aa57505e5ecbd585d061364abb0032d5b5b29cc41c54f4b38cb81c2ba6eb; the app tip b5be4edf. Every gate green at 14:01:14 BST (build 13:47 rc=0, igneumd 68526b25, igneum-miner d4f4c98d, /srv/artefacts/0325-c9ad753a/node-lane; miner 29, core 177, exec 54, pow 19, consensus 134, p2p-flows 38 at gate priority; the Devnet 3 canary with the digest, byte 6, override refused, the 0.3.24 pin refused both ways; the testnet canary b2e856ed). On the same node code and object (6ccaf9e9): every gate green at 14:00:56; the fast-time SUMMARY PASS (cross-0325-6ccaf9e9) at 13:57:35 with the pairing read before the lease as the freeze fingerprint on both binaries (13:44:45 to 13:57:35 on build-1: rung 1 at 13:51:10, class v5 by signal at byte 6 from epoch 8 at 13:53:28, 12 of 12 ids equal to the freeze CLI's, the stale node 73 of 73 refused, the restart step resynced in 10 s with the catch-up done after 5 s and nothing of its own mined during it, four sinks equal at 662, 0 PoW rejections and 0 submit timeouts); the v5 lane's read-back PASS id for id on epochs 8 to 10 (13a54a0dd793ca79 attempt 2, d35cd0e9cb186d00 attempt 1, 6104176723170d72 attempt 2, miners 3 of 3 against the freeze CLI at exactly 1c420786); the matrix green on build-3 (build-4's consensus cell unreadable under load 510, the steward's clean run once the load is under 96, its line by 14:25). The FAIL seed re-read: on ec0a8cf9 with the FAIL run's era, day and epoch-9 stream, igneum-pow at exactly 1c420786 draws attempt 3, program id 1f1cf82877f46ee6 (8f481459 the same), so NEITHER id in the FAIL was the freeze's ("cli v5 ebf64b32" came from the release worktree's pre-freeze copy, the pin miner's 65b57e3b from igneum-pow-v5/src); the fingerprint pairing is the gate that catches both; the miner's side of that seed cannot be re-read offline (igneum-miner reads ids from a node's template only), so the pin rests on the fingerprint equality and the record says the attempt-3 seed's miner id was not re-read. The ceiling lands at 90,000 (epoch 25) about 18:53 BST, the publish limit 82,800 about 16:53. The re-execution reading: 27,000 chain blocks in about 8 minutes, RSS peak 12.6 GB on IBD plus walk. The fleet fetches m9ad7-1; THE MINUTE = the last FETCHED plus ten, about 14:30 to 14:40 BST; the Mac and HiveOS entries at it; Windows on PC 2's return; the card after the Windows entry. The minute's gate on the fleet's side: the census at 28,462 (a75c5624 / 0x1fd55139) after the re-walks, the unban per box once equal, the first checkpoint lock after it. The attempt-3 rule's shape: the miner's half of a seeded read did not exist; today it is the v5 lane's kaspa-pow program-id binary on its fork branch (class-v5-node 22920380, the template prepare's own path); igneum-miner program-id with the same flags and output line is the first item on the next node line, after which the harness points at the miner. The testnet v5-at-0 re-cut, landed by the default and amended once for its pinned digest constant: 0d05e795 on release-0.3.24-node, every gate green at 14:03:47 (pow 19, exec 47, miner 28, consensus 134, p2p-flows 38, core 175; the testnet canary with digest 1da30c10e164784ffbf5bf216ef3bf84a2d5da212317b1e535c9850fe14aba2f, byte 6 from genesis, the old-object seeds refused; the Devnet 3 canary on that line cc902690 unchanged); the rows with the testnet lane, with the note that the go seeds should run the 0.3.25 pin's node code with that object (one merge commit onto c9ad753a and its gates after the move's read-backs). Rule 19's known-failed self-test waits on build-2's pool cores (it pre-empted the attack pass's F1 upper range at 14:03 by the class order, 48 cores, 2,023 s in, 4,000 fresh rows kept; re-queued from index 397,292 holding 52 cores; cost about 25 core-hours, the build-2 F1 end about 06:30 BST). The attack pass's p212 run alone on the gate's exact line with --diag 1 --by-site (build-4, 8 threads, 13:56 to 14:01; binary 0f5c98dc, day 20733, class v5, the dn3 state): ratio reproduced 1.1917x (the gate's 1.1915x); hot-set verdict clear; 6-sigma buckets64 flagged at +91 sigma. The excess is one site: site 9 (instr 35, src r6, k_off 2 offset 0, window 2^22) carries 1.789 percent of its reads into the top 0.1 percent, 16.4x its flat share, index entropy 13.981 of 14 bits, the largest 256-item bucket 1.75x the window expectation, saturated source 0; the eight hot positions are site 9 in iterations 0 to 7; every other site at full entropy and its bucket at expectation; the predicted-source site (site 1, instr 7, r5, one-one-bit through a load at 2) reads 0.237 percent, the ordinary 2x of a 2^23 window, so the prediction is not the excess; the hottest items (0x000010 at 296 reads, 0x00000d, 0x00000e, 0x3c001f, 0x18001a) low addresses near the window base. Verdict: p212 is the AP-F8-1 tail class (a per-site bucket concentration at one narrow-window site, 0.019 bits short), not a lossy source (the log at /srv/builds/igneum-wt-attack-v5/p212-diag/p212.log on build-4). The hash lane's reading of both: p212 the bucket class, p225 the value-level class the one-one-bit prediction names; in both the predicted-source line points at the wrong site, so the prediction stays a hint and the by-site histogram is the attribution. The consequence for class v6's layer 4 (to the research lane): the per-site bucket bound at about 2x that would refuse the morning's four refuses neither of these (1.75x and none); the value-level test catches p225; a bucket bound near 1.5x would take p212 at a clean-seed cost nearer 3 to 6 percent. The AP-F8-1 ledger paragraph amended with it on the hash lane's next gate run (ordered). The research-landing lane's landings: floor-sram documents on master as de3d32af (13:55 BST; the lane's text at 8e9588de; full gate GREEN 73, the light gate on the merge; the gate pid rule kept) and floor-invention documents as d28a7656 (14:03; the lane's text at 033ff8d8; full gate GREEN 73): docs/analysis/class-v6/floor/sram-and-floor.md and invention.md; waiting on floor-sm (15:30), floor-k (15:45, with tools/chip-model/rtl), floor-denominator (no word yet), then the counter-asic-4 close follow-up after 15:45. Two more deploys from the builder stream, checks ok (21 asserted pages): 9a029677 at 13:50 BST (/metamask reads eth_chainId at load, 0x1170 pinned as the fallback, read back equal to the public RPC's answer) and 7902e235 at 13:55 (/build's networks table and /faucet name 4464 since the class v5 floor; the faucet signs with the node's chain id); the build-server lane's lease-pool memory rule in its gate (a lease declares its GB, the box ceiling 100 GB with the hands' residents counted; the shipper's order after the 12:06 OOM kill of the seed). Lane C's drawn-era re-read on 0ab27582 at 14:0x BST, run on build-2 (build-4's pool never freed, the waiter withdrawn, named in the row): the sound per-load form (16 x 256 x 1) accepts 254 of 256 seeds under drawn eras at 0.819 rejection per candidate, mean accepted attempt 4.3 (no-era on the same binary 234 of 256 at 0.927); the form at class v4's count (16 x 144 x 3) 254 of 256 at 0.811; every sub-block of 36 instructions or longer 0.80 to 0.84 under eras; the iterated 16 x 27 form 66 of 256 at 0.991 under eras and 128 of 256 at 0.979 no-era, dead on both instruments; the class v4 shape through the same binary reads sub-version 3's own 0.666 and 0.682. So the per-load prototype's verdict of 00:0x was an instrument artefact as the record reopened it, and the sound form stands at 0.82 to 0.93 per candidate with the dataflow rule in execution order as the named fix. The cut with these rows and the 5090 rows lands by 15:00. Floor lane 1 (SM-sparse) at 14:00 BST: its PC 1 jobs are run-ca4-pc1-floorsm-5090-20261008 (the ladder at the 1,300 lock, since 13:07, a 66-minute cap, the card free by 14:13) and the memory-clock ladder at the lock (about 20 minutes); floor-pc1-build-2 and floor-pc1-restore are the prover-floor lane's; every rented pod of lane 1's destroyed (spend USD 27); the stock rows, the decomposition and the self-tune in docs/analysis/class-v6/floor/sm-sparse.md at ccafd9a4 on the mirror; the lock and memory-clock ladders the two rows owed for 15:30. The coordinator's PC 1 order at 14:12: floorsm to 14:13, kit d to about 14:22, the read-width run to about 14:42, memclk to about 15:05 (republished behind them), the 7600 card-in at 15:05 (the hash lane: any Thunderbolt housing on any PC 1 port, the job keys on the new card against the 10:04 baseline; the pass about 50 minutes, rows by 16:00: detect and VRAM, 8 GB: the 1 GiB prototype dataset and the genesis 2 GiB floor fit, 4 GiB fits at about 5.4 GiB needed, 8 GiB does not; the class v5 and v4 fingerprints and the stock bench on the OpenCL kit worker; the app's own rate and watts; the AMD knob grid as on the 9070 XT; the Efficiency, Balanced and Maximum rows; the dataset rows at 2 and 4 GiB from the class v3 packs ds29b, ds30b; the 5.5 GiB row by interpolation, labelled, since the exporter takes power-of-two datasets only; a 5.5 GiB pack is a crate change for tomorrow unless main wants it today, default not today). The founder's order through main at 14:4x BST: Devnet 3 comes back first, the users' cut second. The sink-age guard has no switch (service.rs:1131 hardcoded), so the node lane cuts the hotfix now; the fleet, hub-1 and build-1's four nodes move onto it by a +0 file on the fast-time PASS alone (about 15:00), the full gate set and both canaries running behind for the node-only 0.3.26, a re-move if the set finds a red (nothing risked, the chain being dead). release-0.3.26 open at 822f8767 (the version bump only, the app crate unchanged); its DMG, hive and Windows entries re-cut on the hotfix sha and published at a minute after the network is back. PC 2 back and mining as of 14:4x: its queued jobs run on logon (the 0.3.25 install take first, the sign.ps1 self-test, the UI lane's two, the hash lane's Arc read); the 0.3.25 Windows entry on a clean take, the 0.3.26 one on its own. The DEX lane's /swap fix in its gate at 14:4x (the pools table 640 px wide at 768 px with no overflow, the sentence in a wrapping line under the table). The record's forty-fourth landing's merge gate killed by signal 15 at 14:4x BST on the Mac, a second kill since the rule landed; the steward's TERM-sender log is the read; the merge re-run. THE HOTFIX landed at 14:42:44 BST as f8da7515 on release-0.3.25-node (cold_start_replays: Err only for a node that synced nothing or whose retention root is above genesis; a node holding the chain from genesis replays with a stale sink, one line said; the known-failed test cold_restart_tests::a_node_holding_the_chain_from_genesis_replays_whatever_the_sinks_age; nothing consensus, digest 2066aa57 unchanged); the guard was 10 * 60 * 1000 hard-coded at exec/src/service.rs:1131 with no env, flag or config field; the shipper's prepared 4831c372 dropped. release-0.3.26 = 602bce8c (the bump plus the pin f8da7515; the app crate unchanged). The clock: the seed pair and tarball about 14:52, the fleet fetching from then, the fast-time PASS about 15:27, the fleet, hub-1 and build-1's four on it at about 15:35, the gate set and canaries behind for 0.3.26, a re-move on a red; the users' 0.3.26 entries after the network is back; the testnet go cut re-cut on f8da7515 after. The first block's time to main from the shipper. The 1.5x test's measured row ahead of 15:30 (the fleet hand on RunPod secure cloud, 14:28 to 14:39 BST, pods destroyed, USD 0.62 of the 60 incl. a re-rent loop fault that rented five extra 4090s for 14 pod-minutes, all destroyed by 14:36): the class v5 base (v5-genesis) against knob 3 (hl-k3-sh1024: the 1,024-instruction shadow block at 27 passes, 4x the shadow ops, a class v5 research pack on generator 5), the kit worker d84b1b6c, --batches 250 --batch-log2 24 --block-warps 1, watts the mean of nvidia-smi power.draw over the busy window. RTX 5090 (driver 595.91.07, sm_120): base 140.83 MH/s at 442.7 W (3.14 µJ per hash, fingerprint ae74193ddad19e19 equal to PC 1's), knob 3 111.07 MH/s at 551.1 W (4.96 µJ; at the full 60 s it sits on the 575 W limit at 110.0 MH/s, 5.23 µJ), fingerprint d0d9eccde24b30af. RTX 4090 (driver 570.195.03, sm_89): base 62.41 at 279.3 W (4.48 µJ), knob 3 62.64 at 439.2 W (7.01 µJ), the same fingerprints. Reading: knob 3 costs the card 1.58x the energy per hash (5090) and 1.57x (4090), the same on both architectures; on the 5090 it is power-bound and reads as 21 percent fewer MH/s, on the 4090 the rate holds and the watts climb 61 percent; per shadow instruction the long block costs 0.40x the 256-block's (the per-pass overhead amortised); the 4090/5090 rate ratio 0.44 on the base, 0.56 on knob 3. For the founder's 1.5x: the GPU pays 1.58x for this knob while the k lane's chip-side figure for the same knob is its row; knobs 1, 2 and 4 not benched today (2 has no GPU knob, the k lane agrees; 1 and 4 are new ISA, priced by the microbench until a generator line exists). Logs under the scratchpad's 1p5x/fb-1p5x-5090 and -4090. The DEX lane's /swap fix committed on dex-devnet3 (the syncing and no-answer sentences out of the pools table into a wrapping line under it; both tables fixed layout and normal white space; the row reads "RPC syncing" or "no answer"), checked at 768 px with the public RPC at block 0: no overflow; its first landing's full gate killed at 14:4x by another lane's pkill -f tools/ci/pre-push.sh (the kill-by-name class again), the landing re-running, on master before 15:00 unless killed a third time. The record's forty-fourth landing's re-run merge gate read RED at 14:5x on that same /swap clip at 1600 px dark (the sweep renders the live page while the RPC re-executes), so the record lands after the DEX fix is on master. The forty-fourth landing on master at 14:5x BST (e694030f, after the DEX lane's /swap wrap 92b6da6f reached master at 14:48 and cleared the sweep's red). THE INTEL ROW CLOSES at 14:46 BST: the Arc B580 on the second PC reads the rebuilt kit 65b47211 EQUAL at its logon turn (run-ca3-pc2-v5-intel-bench-20261008: v5 fingerprint 82b19cbde8557ea5 = expected, match True, check PASS, 10.794 MH/s quiet; the v4 control 892b6d55a7ddcfcb PASS at 10.718; both self-tests 96 of 96; the host's "rotr_var rewritten to the shift form before the build" line present, sub-group size 32 with sub_group_shuffle_xor), so the rotate fold was the whole Intel fault, the sub-group patch stays unapplied, and the class v5 kit reads one fingerprint on six platforms: CUDA (RTX 4090), Metal and Apple OpenCL (M5 Max), AMD (RX 9070 XT), Intel (Arc B580), the CPU verifier. The page's Intel row at class-v5 916925f5 (both mirrors 14:51); the 0.3.26 line to the shipper by its rule: the post-freeze class-v5 line with the Intel kit in, 0.3.25 on 1c420786 as published; the shipper carries the Intel kit into the first app cut after 0.3.26. PC 1 at 14:50 BST: no job taken since 14:13 (kit d, the read-width run, the memclk ladder, the card-in detect all "no uploads"), the default ran at 14:48: the signed restart job kind for the app (restart-app-pc1-20261008-cardin); if the app is polling it restarts itself and the queue drains in order; if it is hung or gone only the founder's hand at PC 1 brings the runner back (the ask with main since 14:36). At 15:00 with no job started: kit d's rows and the W = 8 row miss the 15:30 close (the op mix the microbench arithmetic, W = 4 pins), the 7600 pass and the 5.5 GiB rows move to PC 1's return. Floor lane 1's close row to main and the research lane at 14:50 with the memclk ladder labelled owed; its file complete at 32132943. Floor lane 2 (shadow k), the design sweep at 14:5x BST (synthesis-only, 8 lanes, ASAP7 TC 0.70 V, gate-level random-input VCD at two run lengths with the steady state solved; k absolute at N3 against the 5090's 6.2 pJ at the 1,300 lock, 11.3 at stock, the M5 Max 6.9): base (32 regs, 256 imem) 186k cells, 6.9 pJ per lane-op (2.4 clocking), N3 3.5, N2 2.5, k 0.31 / 0.56 / 0.50 (stock / lock / M5 Max); (1) the 64-register file (40-bit word) 268k, 9.7 pJ, N3 4.8, k 0.43 / 0.78 / 0.70, a new ISA on the GPU side (in energy about free on NVIDIA, 255 registers per thread; rate paid only when occupancy drops below the latency-hiding point); (3) the 1,024-instruction imem as built (a flop array) 325k, 12.0 pJ, N3 6.0, k 0.53 / 0.97 / 0.87, measured on the GPU at 1.58x energy per hash for 4x the shadow instructions; (3) with the imem as a 4 KB SRAM macro (2 to 4 pJ per 32-bit read, shared by the lanes) about 7.2 pJ, k about 0.32 / 0.58 / 0.52; (4) the drawn select tree 187k, 6.85 pJ, k 0.30 / 0.55 / 0.50, nothing on either side; (2) 32 lanes and (2') 32 lanes at 16 regs in sim, clock 15:30; (5) all four together in ABC on build-3, clock about 16:00. The reading: the 64-register window is the one robust knob (+0.22 of k at the lock, per lane, not amortisable); the long block adds little once the imem is SRAM; the select tree adds nothing; (1) + (3) as built reaches k about 1.2 at the lock but a chip maker builds the imem as shared SRAM, bringing it to about 0.81 (0.45 at stock), and wider SIMD amortises the fetch further; k 0.85 is not reached by any knob a chip maker cannot amortise away; the DRAM board under 2x at the lock needs the register window AND the long block AND the honest card at its knee, and holds only if the chip's imem cost stays unamortised, which it does not. The node column (claimed from TSMC's headlines: N7 to N5 x0.70, N5 to N3E x0.72, N3E to N2 x0.72; the 5090 and 4090 on 4N, N5 class; the M5 Max N3): base 6.9 ASAP7 / 4.8 N5 / 3.5 N3 / 2.5 N2, k at the lock 0.78 / 0.56 / 0.40, the GDDR7 board at the lock 2.4x / 2.8x / 3.2x; the 64-register core 9.7 / 6.8 / 4.9 / 3.5, k 1.09 / 0.78 / 0.56, the board 2.0x / 2.4x / 2.8x. The one line: of the 2.8x at k 0.56, the N5-to-N3 node step is worth 0.4x (a factor 1.17, claimed); the rest is the memory system (3.6x at zero shadow at the lock) less what the class v4 shadow takes back on the card's own node; on the card's own node the base core sits at k 0.78 and the 64-register core at 1.09, so "near 0.9" is reached node-for-node by the window alone; what it does not survive is the node step a chip project buys (an N3 core gives back the 0.4x, an N2 core 0.8x). The placed 8-lane core in detailed route on build-4 at nice 19 (about 16:00). Branch class-v6-floor-k. The hash lane's reading of the 64-register window: not exportable inside 20 minutes: eight registers fixed in four places that must agree bit for bit (the generator's operand draw modulo 8 and the register init from one seed word each; the three kernel texts r0 to r7 selected by (i + 1) & 7; the CPU verifier's register array; the warp's hash fold over the eight), a 64-entry window needing an init rule for the 56 extra registers (a design choice) and a fold rule for the output, then the emitters, the verifier and the vector check: a half-day line; the GPU-side figure modelled: 64 live registers a lane on top of the kernel's forty-odd puts a thread at about 110 of its 255 registers, occupancy to about half, the rate expected to hold under the latency-bound read chain (the 5090 hides about 330,000 ops a hash, chip-model-v3 5.7), the energy per hash to move little, the per-lane register traffic the unmeasured term; the half-day line can start after the 7600 pass if main wants it tonight (default not tonight). The research-landing lane: class-v6-floor-denominator at fc265d8d landed on master as d461e365 (14:50 BST; denominator.md plus the three app/igneum-app/tiers files; full gate GREEN 73); floor-sm (32132943, sm-sparse.md only, 717 lines; the worker patch on the branch) in its gate, landing about 15:03; k by 15:45; the close rows within 30 minutes of 15:45. Two deploys at 14:53 BST, checks ok (21 asserted pages): d461e365 (the DEX lane's 92b6da6f: /swap's RPC-syncing and no-answer lines under the pools table, both tables wrapping) and c8ce4b52 (the UI lane's site-fee-words on main's order: the dev fee as the fixed 1% fee with the app's Settings sentence on /miner and /dev-fee, "switch" and "switchable" gone from the fee card, the "Off with" row and the description metas; no "switch" string served on /miner). No chip text changed. The hotfix f8da7515's full gate set and both canaries read green at 14:50 BST (exec 55 with the dead-chain test, the mixed-version step HANDSHAKE on the unchanged digest), so THE SECOND MINUTE IS 15:05:00 BST, named on the gates rather than waiting for the fast-time pair: every box at +0 (81 of 97 fetched at 14:57, the rest by the pull), hub-1 and build-1's four by hand; the fleet's tarball 29f11d85 (igneumd 07a522f3, the miner unchanged eead4d0c, both fingerprints the freeze's). The merge default taken: 33 solo miners stopped at 14:53 to 14:57 (the fastest branch 122 under the epoch 21 cliff at 75,600, past which branches never merge); they restart with the move and the branches merge inside epoch 20. The 0.3.25 Windows entry skipped for good (a 0.3.25 Windows node would deadlock); the Windows line lands with 0.3.26 (602bce8c; the installer's copy-step fix on that tree by 15:30). The next readings: the first block on the rejoined chain, the replay rate, the first lock. Floor-sm (32132943, sm-sparse.md only) landed on master as 69335fc1 at 14:58 BST (full gate GREEN 73); the landings today: 868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1; open: floor-k by 15:45 with tools/chip-model/rtl, the design document's close rows within 30 minutes of 15:45. PC 1 is back: kit d closed on the 5090 (run-ca4-pc1-v6d-packs-5090-20261008, 14:51 to 15:0x BST, all PASS; rows with the research lane and floor lane 5), the runner's stall 38 minutes (14:13 to 14:51, the founder's hand or the restart job). The op-mix row inside the shadow block: against the same worker's w4 base (119.95 MH/s at 308.2 W unlocked; 100.55 at 190.5 W at 1,300), the shuffle-heavy table costs the block 155.5 W unlocked and 80.6 W at the lock (level with the stock table's 152 and 84 this morning), the multiply-heavy table 104.6 W and 62.0 W (31 and 26 percent less), the rate flat within 0.4 percent: the weight table is a 30 percent lever on the block's watts on Blackwell, with the sign the microbench gave for the multiply end and smaller magnitudes than its arithmetic on both ends. Floor lane 5's hinted w64-l2: 92.35 MH/s at 369.1 W unlocked (23 percent under w4, 1.56x its energy per hash) and 37.59 at 164.1 W at the lock (2.3x), dead at the knee as at stock. PC 1's queue: the read-width run (the W = 8 row about 15:30), floor lane 1's memclk ladder, the 7600 detect about 15:5x and its pass (the first 7600 row about 16:00, the stall's slip); the register-window hand for 16:30; the 5.5 GiB kit from the worker lane at 16:00 with the rented 5090 row behind it. Lane D at 15:1x BST, every stratum COMPLETE: w1band 3,000 (build-2), w4band 3,000 (build-3), w4shape64 3,000 (build-4), shape256 3,000 and shape64lossy 2,000 (build-3), the four lossy-share points 3,000 each (build-1), the F8 label space's p2 to p65 and p212 to p225 through the sigma form (build-2); point A DONE on build-1 (64 seeds: 45 PASS, 3 beyond 1.2x, 2 hot sets p38 and p54, both REFUSED by the class v5 floor at 0.9932 and 0.9945 in the floor read on build-3); point B at 54 of 64 on build-3; the x4/x8/x16 verifier rows resubmitted on build-3's free cores after waiting on build-2's pool since 14:5x; 38,000 drawn eras in all today, about 90 core-hours; the 16:30 report holds with sections 6.4 (the lossy curve per shape), 6.5 (the width-4 floor decision), 6.6 (point A), 6.8 (the seven known-failed seeds through the sigma form, the bucket bound retired into the bit read) in the tree; point B and the verifier rows by 16:00, as partials if not. The floor-invention knee-row amendment (3951528d) landed as 66c3401e at 15:12 BST (full gate GREEN 73); the landings today: 868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1, 66c3401e. The fast-time SUMMARY PASS (cross-0325-f8da7515-2) at 15:17:51 BST on the hotfix f8da7515 (the freeze fingerprint on both binaries read before the lease; 15:04:51 to 15:17:51 on build-1: rung 1 at 15:11:28, class v5 by signal at byte 6 from epoch 8 at 15:13:20, 12 of 12 ids equal to the freeze CLI's, the stale node 78 of 78 refused, the restart step resynced in 6 s with the catch-up done after 3 s, four sinks equal at 662, 0 PoW rejections); the first run on the same artefact (15:03:21) read the crossing green too, its FAIL line the late joiner's wait letting two epochs past the observation window into the id rows (harness scope, fixed); the cold-restart class is the node lane's unit test, the pair cannot read it. The shipper's preview 1 at 15:1x BST: preview-26-1 at 57476931 on the mirror = the coordinator's f2781776 plus app-ia-26 e4773cf0 (item 4, the Tune page), release-0.3.26 f44baa25 (602bce8c plus install-detach-26 b39d5dd5, the take-3b copy-step fix) and the preview mark (state.preview from IGNEUM_PREVIEW at build time, appended after the version on the About line and the footer, empty on a public cut; no constant on any branch); the build-server lane cuts the kit, the cross with the env, the payload with the f8da7515 Windows pair and PC 1's host (host-0326 ahead in PC 1's queue), the install takes on PC 1 and PC 2; the Mac DMG by the Mac chain and the install over the founder's app by the shipper's hand; each machine's version and time to main. One red on e4773cf0: ui/heat-region.test.mjs:137 (a resting card's wording), the UI lane's by 15:35; the preview ships with it named, the public 0.3.26 app cut waits on green; take 3c (the public 0.3.26 Windows entry) on f44baa25 behind the preview takes. PC 1 at 15:14 BST: the founder's restart of the app at 15:06 ended the read-width run at 194 s (exit -1, "script was ended") after its three stock rows landed: v5-genesis 118.83 MH/s at 423.5 W, W = 4 under the state term 117.54 at 430.9 W, W = 8 117.54 at 451.5 W; so THE W = 8 ROW EXISTS AT STOCK (the rate equal to 0.01 MH/s, 4.8 percent more energy per hash; with floor lane 3 and the research lane); the 1,300 lock rows and the W = 16 state-term row owed from a republished run (run-ca3-pc1-readwidth-5090-20261008-b, behind the detect and the memclk ladder, about 16:30). The runner had already resumed at 14:51 on the signed restart job (kit d 14:51 to 15:02, the read-width run from 15:03), so the founder's hand restarted an app that was polling; no harm beyond the lost rows. PC 1's queue: the 7600 detect, the ds55 kit fetch, the memclk ladder (about 25 minutes), the read-width run b, the shipper's host preview build, then the 7600 pass (the OpenCL bench with --cards-off on the new key, the grid, the tier rows, the 5.5 GiB rows on the 7600 and the 5090). A caveat on every PC 1 row since 14:2x: the 5090 reads about 13 percent under the morning on the same packs and worker (v5-genesis 118.8 against 135.9), a host-side change with the eGPU swap; the next job's card line reads the PCIe link, the first suspect. The 5.5 GiB kit done (the worker lane, ds55-v5 at b57045fb, the emulated worker's self-test PASS on the 5.5 GiB pack; the kit on build-1, sha 2d7f55e8) and with the fleet lane for the rented 5090 row. The forty-fifth landing on master at 15:27 BST (6ae577e40). THE CLASS V6 FLOOR CLOSED at 15:28 BST, 17 minutes ahead of the 15:45 clock on the ship-on-green rule, every lane's last row in, on the mirror's counter-asic-4 (docs/design/class-v6-rotating-family.md section 10; the tip 725d2945 at 15:27; the full gate green on the branch; the landing on master by 16:30). THE TABLE (10.0 with 10.0e), the honest tier's measured class v4 joules per hash over the chip's modelled joules, the chip's core the k lane's synthesised sequencer core with the 64-register window (10.0c: the one knob a chip maker cannot amortise, k 0.78 at the lock at N3; the card's window cost modelled, labelled) and the per-unit floor (k 0.18) beside it as the worst case: the RTX 5090 at its 1,300 MHz knee (2.33 µJ): GDDR7 board 2.4x (2.8x without the window; 4.0x at the unit floor), HBM3 stack 2.9x, SRAM die at the genesis width 4.3x; the RTX 5080 at its 1,100 MHz lock, the honest NVIDIA floor (2.06, measured; lane 4's finding that the floor is the 16 GB Blackwell card, not the 5090): 2.2x, 2.5x, 3.8x; the Apple M5 Max (1.40): 1.5x, 1.7x, 2.6x; stock rows: the 5090 3.5x / 4.1x / 6.2x, the 4090 and H100 in 10.0. The node row: 2.0x against a chip on the GPU's own node, 2.4x a node ahead, 2.8x two nodes ahead (node-for-node the window core is k 1.09); the honest tier moves to the next node with every GPU generation while a chip must re-tape-out. SM-sparse: no change on any card (measured on the 5090, 4090, H100: 1.3 to 3.9 percent at best; the residual the clock domain). W = 16 killed on measured energy on four cards at stock and at the 5090's knee (+25 to +34 percent per hash on the card against the chip's +33). STATED PLAINLY: the GPU-tier floor is about 2.2x to 2.4x per joule at the knee against the chip anyone can build, under 2x only against the Apple tier; Monero's RandomX measured 1.0x to 1.5x beside it. THE CAPEX WALL (10.3): no rational chip project of any kind below about USD 23 M a year of miner revenue (IGN 0.03); every DRAM-board project at a third of the network above about USD 340 M a year (IGN 0.44); the project cost moves the threshold 5x, the chip's edge 1.4x. THE SERVED LINE in two units: under 3x per joule at the knee (2.2x to 2.4x with the window), under 1x per hash over its 180-day class life only above about USD 300 M a year of miner revenue (10.0a). THE FOUR CLASS V6 CHANGES: (1) the op mix stays class v4's with the lossy families capped at base (0 of 3,000 eras exhausted under the band; a multiply-heavy table lowers the card's premium a quarter but the chip's further, mul and mulhi k 0.03 to 0.08; the shuffle weight costless to the card and can rise inside B = 4 if the chip's butterfly k reads high); (2) no SM-sparse default (--sm-sparse auto off, on in Efficiency and Balanced at its measured 1 to 2.5 percent); (3) the dataset schedule 5.5 / 8.5 / 11.5 GiB (the 5.5 GiB step measured on a rented 5090 at stock: 3.5 percent of rate, about 4 percent of energy, the non-power-of-two mapping no cliff on sm_120, safe to adopt at the v6 epoch; about 9 percent at the knee, interpolated) with the read width pinned at 4 words (8 measured not free at +4.8 percent of the card's energy for 0.2x of the die's shadowed edge, 16 never); (4) the 64-register window per lane as the core shape, its GPU side modelled until measured. The rotation schedule adopted (10.0d): hourly 8,766 / weekly 52.18 / family 2.03 / vote at most 2.03 extra boundaries a year, the 6 h vote window. Precedents sourced (10.0b): RandomX 46 months to a chip at 1.0x to 1.5x; Ethash 36 months to a chip worse than a GPU, 14x today; Kaspa 21 months, 167x to 725x. MISSING AT THE CLOSE, each with its default in the document and owed as an amendment with its own minute: the k lane's 32-lane rows and placed core (about 16:00; the +30 percent placement and the register-file gating roughly cancel, provisional); the card's measured window cost (a half-day generator line); lane 1's memory-clock ladder; the W = 8 lock row (16:30) and the RX 7600 8 GB-tier row at 5.5 GiB (16:00 to 16:30); lane D's full report 16:30; lane C's drawn-era F8-form read. THE 5.5 GiB ROW measured two hours ahead of 17:30 (the fleet hand on a rented secure 5090, 15:19 to 15:23 BST, USD 0.32, the pod destroyed; the kit igneum-ca3-ds55-kit-20261008.zip sha 2d7f55e8 with its own worker d43be462, program id 73bcbfe8ccf988f1 in both packs): the pinned class v3 program at 1 GiB 141.48 MH/s at 325.6 W (2.30 µJ, fingerprint 90f794dd556f7a3b, the pin, 1,914 MiB used) against 1,476,395,008 words (92,274,688 items, not a power of two: loads are (src * words) >> 32) 136.56 MH/s at 305.3 W (327.6 steady; 2.24 to 2.40 µJ), fingerprint 23ced07a4d28b465 (the new pin, stable over two passes), the self-test PASS 96 of 96 lanes, 6,522 MiB used; the --batches 500 passes 141.38 and 136.54 with the same fingerprints. So the genesis floor costs a 5090 3.5 percent of its rate at stock, about 4 percent of energy per hash, no cliff from the mapping, on the 2 and 4 GiB stock rows where the interpolation put it. Caveat: that host capped the card at 328 W on both packs (the 1p5x 5090 on another host pulled 443 to 575 W), so the µJ figures are capped-card numbers; the rate and fingerprints stand. The emulated worker's known-failed counterpart reads 96 of 96 bad lanes on the old mapping. The 7600's 8 GB reading and the 5090's knee rows at 5.5 GiB from PC 1 after its queue, as amendments. The attack pass's 15:30 reading (counts at 15:21 BST), two non-zeros sent at once: F9 to 10^6 on 1c420786: 135,836 of the 900,000 new seeds drawn (build-4 99,456 across its six lower chunks, build-2 36,380 across its six upper), 0 exhausted, 0 panics, max attempt index 32: one seed, 718097 (build-4 chunk 4), accepted at index 32, past the record's "0 past 31" line but nowhere near the 256-attempt cap; the histogram tail 24: 5, 25: 2, 26: 2, 27: 1, 28: 1, 32: 1, the geometric tail at its rate (one in 136,000 at 32 against the 10^5 record's one at 30); not a finding: the exhaustion gate is the cap and the deterministic last resort, both untouched; the record carries the max as read. F1 to 10^6 class v5 programs: 172,310 distinct programs done (build-4 83,000 of its 350,000 lower range, build-2 89,310 of the upper on four 13-core parts), differential mismatches 0, verifier mismatches 0, 0 panics, programs over 5 percent: ONE, attack-f1/392513 (attempt 0, 6,912 to 6,561 per iteration, 5.0781 percent, 13 of 256 per pass), the same saving to the digit as the v4 10^5 letter miss attack-f1/37341 (AP-F1-1); the next worst 369298 at 4.6875, 373345 at 4.2969. Under the ruling on AP-F1-1 (gate (1) re-worded to compressible beyond the honest compiler's own simplification; a letter miss at honest-compiler parity is a PASS) a letter miss to be read at parity: the section 7.3 and 7.4 readings (explain, emit-c, the compiler pass) running, the parity verdict within the hour; if the compiler does not find the same 13 it is a finding on the v5 bound (AP-F1-1's v5 half reopens). Ends: F1 about 05:00 BST (build-4's lower range back at 40 threads from 15:30, about 01:30; build-2's parts about 04:40); F9 about 11:30 BST tomorrow (build-4's lower halves at 3,400 seeds per hour per chunk the long pole; build-2's upper halves about 08:30, taking more of build-4's range when F1's parts free their cores). Two pre-emptions on build-2, none on build-4. The shipper at 15:2x BST: the founder's Mac runs preview 1 since 15:21:53 (the DMG 94327b68 from preview-26-1 57476931, installed over 0.3.24 by the engine's own helper, the state reading version 0.3.26 preview "preview 1", the node on the f8da7515 pair replaying); PC 1 and PC 2 follow through the job runner once PC 1's host-0326 lands. Build-1's seed and node1 replayed on f8da7515 from 15:06:39 to the sink at 15:13:47 (7 min 8 s), 94 peers, the sink advertised again; the chain stands at 72,001 until one miner runs; the one-miner word to the fleet lane at 15:23 (the heaviest branch's box, the rest as their sinks converge; dn3-q03 and dn3-relay to a wipe and resync, their branch mined past the floor under the old rule). The 0.3.26 public stage complete (DMG 6f717c78, hive e3e4482c); its minute after the first block. MAIN'S CLASS V6 BUILD ORDER at 15:3x BST (the close 725d2945 in; the no-consensus-code hold lifted by the order), five lanes fanned under the founder's clock rule, each sent with its default: (1) the hash lane, the generator: the 64-register window per lane with its init and fold rule, the index fold (layer 1's remedy for the era-stride bit; the known-failed set p4, p8, p10, p15, p34, p212, p225), the op-mix re-weight table (13,11,6,10,8,8,7,2,6,4) behind the fold, W = 4 unchanged, the ds55 mapping as the dataset form; four packs (window, fold, re-weight, all together) exported by 21:00; (2) the census lane re-spawned on the four packs through the sub-version 3 harness on build-3 and build-4, PASS or FAIL by 22:30, a dry PASS on the freeze's pack by 18:00 as its readiness line; (3) the node lane, the object: the class v6 object with the dataset schedule 5.5 / 8.5 / 11.5 GiB tied to state at the era cut, the family bank's first entries as admissible flags, the floor DAA on Devnet 3, the digest, the worker-smoke rule and the fast-time crossing with the cold-restart and template cases, by 23:30; (4) the shipper, the cut: 0.3.27 as the class v6 line, the pin tomorrow morning on the gates, the Devnet 3 flip at a floor at least 90 minutes after the pin, the fleet on the kit workers first, Mac, HiveOS and Windows at the minute, the card after; release-0.3.27 opened tonight after 0.3.26's minute; (5) the audit lane, the served chip page rewritten to the close's sentence and the node column, the harness and the scoring rules published with it, on master by 17:30 (the 20:00 hold lifted by the order). The first packs and the census verdict to main with their times. Floor lane 2's remaining sweep rows at 15:2x BST (synthesis-only, ASAP7, N3 claimed, GPU measured; absolute k at the 1,300 lock): (2) 32 lanes, 32 registers: 5.55 pJ per lane-op ASAP7, 3.9 N5, 2.8 N3, 2.0 N2; k 0.63 / 0.45 / 0.32; the GDDR7 board at the lock 2.7x / 3.1x / 3.5x; (2') 32 lanes, 16 registers: 4.2 / 2.9 / 2.1 / 1.5, k 0.47 / 0.34 / 0.24. The register-file cost is linear in its entries (16 to 32 entries +1.35 pJ, 32 to 64 +2.8 pJ per lane-op at ASAP7), the one term a chip cannot amortise; the imem and sequencer amortise 1.35 pJ from 8 to 32 lanes. The shuffle (routed): 1.24 pJ per lane-op ASAP7 against the card's 29.4 at the lock, k 0.021, the lowest drawn family. The mix optimiser over the layer-1 band lifts the unit-floor k_eff from 0.097 to 0.137 (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0) and the core's k by about 15 percent. (5) all four together in ABC on build-3 (about 16:15); the placed 8-lane core in detailed route on build-4 (about 16:00); the crossbar, scratch and int8 tile rows after them. Amendment 1 to the class v6 floor close (15:3x BST, counter-asic-4 after 725d2945): the k lane's routed 32-lane butterfly reads k 0.011 to 0.021 (the card pays 29.4 pJ at the lock for a move the chip does for 0.63), the lowest of every drawn family, and its mix optimiser over lane D's band puts the best genesis table at add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0 (+42 percent of k_eff on the unit floors, +15 percent on the core: 0.56 to about 0.64, the window core 0.78 to about 0.9); change (1) moves from "the op mix held at class v4's" to "the band's best mix as the genesis table", subject to one acceptance pass through lane D's harness (ordered by 18:00; the census lane's neighbouring table at 256 of 256 both ways the fallback); the edge moves about 0.1x in the card's favour at the knee (2.4x to about 2.3x with the window); the core32 row in (k 0.45 at the lock at N3). The coordinator's default to the hash lane: the re-weight pack on the amended table unless main says otherwise by 17:00, both tables exported if free. The shipper took lane 4: release-0.3.27 opens tonight after 0.3.26's first block and minute (the bump only; the node line release-0.3.27-node from the object cut); the runbook at scratch r0327/RUNBOOK-0327.md: 0.3.25's twelve steps plus the worker smoke per platform and the attempt-3 read before the pin, the fleet on the kit workers first, the root gate off for a move after which executors start from nothing, every node with --unsaferpc, rules 16 to 19 in their places; tomorrow's pin clock stated as a time on the three inputs (packs 21:00, census 22:30, object 23:30), the flip's floor at least 90 minutes after it. The forty-sixth landing on master at 15:38 BST (3ce4fd7e5). MAIN'S AMENDMENTS to the class v6 build order at 15:5x BST, from two external reviews the founder accepted: (1) the generator's 64-register window carries the liveness rule (the fold forming each load address consumes all 64 registers; the result depends on the whole window; a liveness tool is an acceptance test beside the census) and the op-mix target is the k lane's optimiser split (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0); (2) the served chip text does NOT take the 725d2945 sentence: the close is amended by 17:00 into three separate statements, energy, economic and response capability, with the lifetime claim and the USD 300 M / 340 M safety-boundary wording withdrawn (a programmable chip survives epochs on firmware), and the audit lane serves the amended text by 18:00; (3) three research lanes beside the build (connected state a4d3518190ad011fc, mixed FP32 aa943688eaa06c538, multi-family adversary a1a9876a88f5a72fc) with rows from 18:30, feeding v7 not tonight's cut unless the connected-state row passes its gate before the object closes at 23:30. Relayed to the audit, research and hash lanes with the clocks. The five lanes' takes: lane 1 (the hash lane) fanned at 15:50: hand A (the window) on reg64-v5 off w8-v5 with the amended spec (the address fold consuming all 64 registers, the end fold over the whole window; ptxas registers, occupancy and spills on the 5090 and 4090 beside rate and watts for the k lane by 18:00), hand B on class-v6-fold off ds55-v5 (the index fold before the stride rotation with the known-failed seven as the per-site index-bit test; the re-weight on the k lane's split, 16,14,4,12,4,11,10,2,10,0 in draw order, sum 83, as hl-v6-rw, the census lane's 13,11,6,10,8,8,7,2,6,4 as hl-v6-rw2 if cheap, hl-v6-foldrw on the k lane's table; the suites on build-3; the packs byte-seed on the node1 state with a drawn era, generator 5, to build-1, the fold pack first); hand A's hl-v6-win and the all-together pack by 21:00. Lane 2 (the census lane afb2fb655385dc259) at 15:4x: per pack (1) the sub-version 3 acceptance with the (c''') per-site floor and the bit-level era-stride read (lane D's fg7 harness, the class v5 crate plus the family-gate diff), (2) attack-f8 at 2^24 on 64 seeds with the window control by site against the pack's state, the hot-set verdict and the known-failed set (p212 and p225 added for the fold pack), (3) the attempts census over the pack's epoch stream; fanned one pack per box, class v5; the f8 point the long pole (45 to 100 core-hours per 64-seed point, about 90 minutes on 48 cores; four packs on two boxes fit 21:00 to 22:30 only with 48 free cores each, which build-4 under the attack pass's 88 and build-3's 24-core pool do not give now); the dry PASS on the freeze's pack by 18:00 as the readiness line, the clock stated when it lands. Lane 3 (the node lane) at 15:4x: the object on the fork branch class-v6-node off release-0.3.25-node at 6e04f7fc (carrying the cold-restart and genesis-stream fixes), program-id first (lifted from the v5 lane's kaspa-pow bin as igneum-miner program-id by 19:00); the fields, each with its own digest arm entered only when set and a key in override-60x.json: program_class_v6_activation_daa (the floor; Devnet 3's value set tomorrow by the floor cut at the pin's publish minute + 7,200 rounded up, at least 90 minutes after the pin; tonight u64::MAX on every network, the devnet-suffix profile for the crossing at 60x), class_v6_dataset_steps ((height, GiB) pairs 5.5 / 8.5 / 11.5 with the state rule's constants: 64 bytes a record, the era-cut read, the genesis ceiling; the item count derived by the ds55 mapping's rule), class_v6_family_flags (a bitset: bit 0 the window, bit 1 the fold, bit 2 the re-weight, bit 3 the lossy band at base; off means not drawable), the class signal byte 7 (CLASS_SIGNAL_V6) stamped from the floor, packaging/pow-freeze.txt as a per-class list with the class v6 entry, tools/ci/worker-smoke.sh for the worker rule (reads the object's fields from the node binary, refuses a cut without one PASS line per platform), the fast-time crossing by the fast-time lane with the --cold and template-at-boundary cases (in its harness since 336639b1); its three questions to the hash lane by 21:00 with defaults (items = floor(GiB x 2^30 / 64); the four bits as listed; the freeze = the last green commit on ds55-v5 at 23:00, class-v6-freeze). The 6e04f7fc go-cut pair landed at 15:33 (the testnet lane's thread). Lane 4 (the shipper): release-0.3.27 opens after 0.3.26's minute; the runbook r0327/RUNBOOK-0327.md. Lane 5 (the audit lane): the old sentence's anchors on every served page staged (home, the litepaper's chip model and table, /miner, evidence row 17, the X35 and X36 ledger rows and pins), the 10.0 scoring definition (whole-card joules per hash over whole-chip joules per hash, the card measured under class v4 with the shadow on, the chip's memory modelled, the chip's shadow priced on the synthesised core and on the per-unit floor), the class v5 harness links to the class-v5 branch's sections 14, 13 and 0 on the git host (moving to master's path on a merge); waiting on the research lane's amended text by 17:00, the landing by 18:00. The register window's first measured row ahead of 17:00 (the hash lane's hand on a rented secure 5090, 16:1x BST): the pinned class v3 base 141.74 MH/s at 303.1 W (2.139 µJ, 30 registers a thread, 24 blocks per SM) against the arithmetic-only window pack hl-reg64 (two interleaved 32-register programs, twice the work per hash by construction) 80.38 MH/s at 308.6 W (3.839 µJ), 96 registers a thread by ptxas and the worker, 0 B spill, 20 blocks per SM (3,400 of 4,080 resident warps, 83 percent). Per unit of work the card is level with the base (160.8 base-equivalent MH/s against 141.7; 15.0 nJ a load against 16.7; the watts level): on Blackwell the 64-entry window costs no energy, no spill, and the 17 percent occupancy loss does not reach the rate under the latency-bound chain; the "half occupancy" model was pessimistic. The 4090 row and the full-chain form on both cards (the address fold over all 64 registers, hl-reg64c) before 17:00. The build-server lane's lease-pool memory rule on master as 5636a0d4 (15:36 BST) and installed on the four boxes at 15:37 (lease sha 82cc0564): a lease declares its resident memory (--mem N or "about N GB" in the label, default 8), the pool waits rather than take the box past 100 GB with the hands' residents counted, the holder line carries the figure; the cause the 12:06 OOM kill of the seed under a 31 GB attack binary. THE REGISTER WINDOW'S MEASURED SET, complete at 15:45 BST on the hash lane's rented secure 5090 and 4090 (the lane's own stamps read CEST; the record carries BST; USD 1.22, the pods destroyed): the 5090 arithmetic-only window pack hl-reg64 (two interleaved 32-register programs, twice the work per hash by construction) 80.38 MH/s at 308.6 W (3.839 µJ), 96 registers a thread, 0 B spill, 20 of 24 blocks per SM (83 percent occupancy), against the pinned class v3 base 141.74 at 303.1 W (2.139 µJ, 30 registers): per unit of work level (160.8 base-equivalent MH/s against 141.7; 15.0 nJ a load against 16.7; the watts level); the 4090: base 62.67 at 208.9 W (3.333 µJ, 29 registers) against the window 31.57 at 210.3 W (6.663 µJ), 104 registers, 0 B spill, 16 of 24 blocks (67 percent), per unit of work level to the digit (63.1 against 62.7; 26.0 nJ a load on both); the 5090 full-chain liveness form hl-reg64c (every load's address mixes all 64 registers, id 3deee2320e70e1bf, fingerprint 4e7cc25967eba280, PASS, on build-1): 70.96 MH/s at 320.3 W, 4.513 µJ, 88 registers, 0 B spill, 20 of 24 blocks; against the arithmetic-only window the 2,016 extra ALU ops an iteration cost 12 percent of rate and 4 percent of watts (the mix in the load latency shadow); against the base the loads a second level (18.2 against 18.1 G) at 17.6 nJ a load against 16.7; the 4090 full chain 31.38 MH/s at 216.5 W, 87 registers, 0 B spill, 20 of 24 blocks, fingerprint equal. THE SINGLE NUMBER THE SERVED LINE TURNS ON: the GPU loses at most 5 percent per load to the liveness window (5 percent on Blackwell, 4 on Ada) and no rate per unit of work, no spill, the occupancy cut (83 and 67 percent) never reaching the throughput; the "half occupancy" model was pessimistic; the 2.0x or 2.4x is the chip side's k, which the k lane holds. The sound class form (+reg64c, the full chain, the only form the liveness rule passes) exports as hl-v6-win on build-3 with its acceptance test in the suite. PC 1 at 15:44: the runner on floor lane 1's memclk ladder (from about 15:20, 25 minutes), the shipper's host-0326 preview build next, then the 7600 detect (about 16:10), the ds55 kit fetch and the read-width run b; the first 7600 row about 16:30, the grid 17:10, the ds55 rows after. Floor-k (bfccc26ed) landed on master as cc49bc6e at 15:39 BST (shadow-k.md plus tools/chip-model/rtl, 78 files; full gate GREEN 73): ALL FIVE FLOOR DOCUMENTS ARE ON MASTER (868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1, 66c3401e, cc49bc6e). The 15:45 close landing dropped by the research-landing lane: nothing from 725d2945 lands; the close rows land as a documents-only delta from the research lane's amended "complete " by 17:00, replayed from 08641162 onward. Lane C's drawn-era F8-form row on master at 5cd69d3d (15:41 BST; invention.md section 3.5): under drawn eras the sound per-load form (16 x 256 x 1, 64 seeds, 2^20 nonces, build-2) is NOT the clean row the no-era read gave: 7 of 64 seeds carry a load site under the (c''') floor of 0.995 (min 0.940 at seed 50; seed 27 at 0.956 with one item at 1,938 reads, 67x the uniform control's maximum), the few-item hot-set class and the era-stride class the in-house pass bounded for class v4 at the same order, structurally because the per-load class as built runs neither (c'') nor (c'''); the share column against a uniform control (median 1.15x, max 1.49x) is the window layer, labelled so. Consequence: layer 5 must take the (c''') floor with the dataflow rule, layer 4's generalisation and nothing new; G5-draw's pass line now "0 of 64 seeds with a site under 0.995 under drawn eras" with the seven seeds as the known-failed case; the acceptance figures (0.819 under eras, 0.927 no-era) stand as the pre-floor rate; the chip model does not move (a 1 MB hot set at 0.3 percent of reads is the in-house pass's 1.002x). Lane C closed: five landings (a9f03598 to 5cd69d3d), the harnesses under tools/attack/v6-invention/, six TSVs; owed at 09:00: the Apple footprint of the 4,096-line block, the 4070 and 9070 XT rows, the F8 read under eras against the window-model null. LANE D'S FULL REPORT LANDED on master at 81b90128d (15:46 BST, gate GREEN 73; a first landing de184157a at 15:39 lacked the point-B row by an edit fault), 44 minutes ahead of 16:30: family-gate.md with every row measured and its log. The rows since 13:13: (1) the lossy-share curve per shape at 3,000 eras a point: the exhaustion a 256 x 27 interaction (3.3 percent of its eras at the +4 corner, r = 0.98, about 6x the independent-attempt figure; 0 of 5,015 shape-64 eras at any share), the band's edge at +2; every exhausted era passed class v5's last-resort scan at k = 256 to 258. (2) The width-4 floor: with W = 4 pinned at genesis, (c''') at 0.995 stays at its measured cost (14.6 percent of the candidates reaching the 2^20 pass, +0.3 attempts an epoch), because the width-4 pre-floor spread has a real tail (10 percent under 0.991 against 2 percent at width 1) no single floor removes at the width-1 cost, and the floor refused both hot sets of the live point-A census. (3) Ring C, 128 live epochs of the band at 2^24: point A (shape 256, a band table) 2 hot sets (p38, p54), both refused by the class v5 floor at 0.9932 and 0.9945; point B (shape 64, a band table) 0 hot sets, 5 over 1.2x (the shipped class's own tail seeds), the floor refusing 1 of 64; the bit-R bucket class on 36 of 128 live epochs against the shipped class's 4 of 64. (4) The seven known-failed seeds through the sigma form: p4, p8, p10, p212, p225 all at z = -511 to -567 at address bit R (the product's bit 0, z = -512 exactly), the bucket bound seeing only the three on narrow windows above bit 12; one value-level test ships (the per-site index-bit read as a per-era record and the structural fix's known-failed set), the bucket bound retired into it; a refusal band of 300 sigma catches five of seven at 16 percent of epochs redrawn, 6 sigma would redraw half. (5) The verifier rows on one build-3 core: x4 3.73 ms, x8 4.12, x16 7.13 per warp (1.73x), so x16 scales over the 10 ms gate on the 2019-class core and the half-core proxy: the mixer band is {4, 8}. (6) Bounds: 9,000 band eras with 0 exhaustions and 0 under the floor bound the failing fraction at 3.3e-4 at 95 percent; the floor's miss rate on hot sets under 0.27 on 11 of 11 cases. Running for the 18:00 amendment on build-3: the best-mix genesis table (renormalised 14,13,4,11,3,10,9,2,9,0) through attack-f8 at 2^20 on 64 seeds (16 cores) and the attempts census with the refused-ratio column at widths 4 and 1 (1,500 eras each, after the fg8 build; the fg7 harness could not hold a fixed non-base table at B = 0). Lane 5's served text at 15:4x BST on branch spec-accept-23 be21940f5, read by the coordinator (the IGN-price lines held out by the standing rule; one verb queried, "retains" against "adopts"; the landing by 18:00). The sentence from 10.0h, on the home line, the litepaper abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Beside it on /litepaper#chip-model: the labels paragraph (2.2x to 2.4x modelled; the GPU side measured, the RTX 5080 at its 1,100 MHz lock 2.06 µJ per hash, the 5090 at 1,300 2.33, class v4, 8 October 2026; the chip side claimed, the synthesised 8-lane sequencer core with the window, ASAP7 scaled to N3 on the foundry's headline factors, the window's k synthesis-derived and not a lower bound; the memory modelled; 2.0x node for node modelled, k 1.09; the 32-lane rows pending); the three-row table (energy resistance 2.2x to 2.4x a node ahead, 2.0x own node, 2.8x two nodes ahead on the 8-lane core, the honest tier moving with every GPU generation while a chip must tape out again; economic resistance on development cost, deployment economics and productive hardware lifetime, the first cut: the price at which a project pays scales as project cost over share times discounted life and moves by under 5 percent with the per-joule edge, a fixed-lane chip under rotation needing 4x the price a programmable one needs, "stated as the conditions under which development is attractive, not as a forecast"; response capability: a passed boundary proves the rotation works, not that hardware dies; the schedule hourly / weekly / 180-day family / emergency vote); the measured cost paragraph unchanged; the precedents as 10.0b sources them (the Antminer X5 46 months after the fork at 6.37 J per kH at the wall, "an observed comparison, not a ceiling"; the X9 pre-order, withdrawal, no benchmark; RandomX v2 released 25 March 2026, activation pending; Ethash 36 months, the iPollo V2H about 14x; Kaspa 21 months, 167x to 725x; the commodity cohort = discrete GPUs, the Apple row beside, never the headline); the scoring rule (min over workloads of max over free adversarial designs of E_GPU over E_adversary under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness, hardware accessibility; the rejected long program, select tree, wide read and scratchpad as negative controls with their rows; the next programme: connected state, mixed integer and FP32, the multi-family programmable adversary); the links to the close on master and the class-v5 branch's sections 14, 13 and 0. Struck from every served page: the 2.1x/3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x rung row, the USD 100 M pay-back row, the k about 0.33 column, the "band Igneum's model sits in" sentence; never served: the lifetime claim, USD 300 M/340 M, any chip-arrival probability, the 725d2945 sentence, W = 8. Evidence row 17, ledger X35/X36 and the ledger-text-check pins move with it; docs/plans/counter-asic-3-public-text-2026-10-07.md section 1 superseded on the served pages (the coordinator's to amend). The hash lane's clock corrected at 15:49 BST (its afternoon stamps about fifty minutes fast, the hands' and the box's CEST copied in; every minute read off TZ=Europe/London date from here). Its open minutes: the 7600 detect about 16:10 (PC 1's runner on the shipper's host-0326 preview build; the memclk ladder closed done at 15:4x), the first 7600 row about 16:30, the grid 16:40 to 17:10 with the tier rows, the ds55 rows on the 7600 and the 5090 by 17:40, the read-width lock rows between them; hand A's hl-v6-win and hand B's fold pack about 17:00, the re-weight packs by 18:00, the class-v6 merge, the all-together pack and the freeze sha to the node lane by 21:00. The forty-seventh landing on master at 15:58 BST (022bc52bd), the 7 October public-text file marked superseded. THE PUBLIC 0.3.26 CUT: release-0.3.26 = 1f4904e0 (app-ia-26 ebb20c46 whole, the audit's PASS, the detach fix, the node pin f8da7515; the preview mark empty; the push gate green 15:50; the crate gate green on d1edf2ad at 314+35+8 and running on 1f4904e0 on build-3). THE MINUTE for Mac and HiveOS is 16:00:00 BST on the founder's "push now" (the DMG building on the tip, the hive e3e4482c staged); Windows host-less by main's word about 16:15 (the PC 2 installer build on 1f4904e0), PC 1 and PC 2 by their update checks. The founder's Mac runs preview 2 (a96efbab = effc48e9 whole + the mark) since 15:40:22. The node side: the snapshot short-capture class (the node lane's read at 15:48: every converging node refused its own epoch's blocks after a mid-epoch resume) cured on the fleet by the snapshot-aside restarts running now (24-minute replays; the first hub block about 16:10), its fix acaf08b0 under gates for the fleet's +0 move and the users' next node-only OTA; 0.3.26 ships on f8da7515 since an updating user replays from genesis. release-0.3.27 opens after the 16:00 minute. THE FIRST TWO CLASS V6 PACKS on build-1 and with the census lane at 15:58 BST, an hour ahead of the 17:00 line: hl-v6-fold (id 482dc0dad937135b; the seven failing seeds fire at -58 to -567 sigma on the plain address and read under 3.5 sigma with the fold, the same attempt accepted both ways) and hl-v6-rw (id 30628f8adcf6035e, the k lane's table, the op counts within 0.1 point of the table over 1,000 draws, the plain path byte-identical to the pinned pack); hl-v6-foldrw and hl-v6-rw2 next, hl-v6-win from the window hand on its suite's green. THE CENSUS LANE'S READINESS LINE met at 15:53 BST, seven minutes inside 18:00: a dry PASS on the freeze's class v5 pack (v5-dn3-epoch0, program id e5a4ac5978462156 re-drawn from the pack's own seeds, class and era) through the whole pack harness on build-4, the known-failed set reproducing the record to three places. The harness (branch class-v6-census-fg at 3602d4ad on build-3 and build-4; ds55-v5 b57045fb plus lane D's family-gate diff 3dc3117c plus a sitestats command and the attack pass's f8 tool with a --load-class path; binaries pinned on both boxes, byte-identical): per pack (A) the program re-drawn and judged by the whole rule with (c'''), then per site over 2^20 evaluations the distinct ratio, the 256-item bucket sigma and the index-bit era-stride sigma (4 s on one core); (B) the attempts census over 256 chain-shaped seeds of the pack's class under its era and state (16 cores, 2 minutes); (C) the F8 census on the live state-keyed dataset: the known-failed set at 2^24 one program per 8-core job (4 to 5 minutes each) and 16 seeds at 2^22 on 16 cores (about 30 minutes); class v5, nice 19, pid files under /srv/builds/v6-census/pids/. The dry rows: (A) accepted, min site ratio 0.99923, bucket sigma max +5.5, one site at bit 9 at -448 sigma (the era-stride class on today's load_index, the record's own); (B) 256 of 256, 0 exhausted, r 0.716, (c''') 1.66 percent of candidates; (C) p4 1.2163x FLAGGED (+67.7 sigma bucket), p8 1.3787x, p10 1.5052x, p212 1.1917x (+91 sigma) FLAGGED, p225 1.2457x BEYOND the 1.2x gate, p15 and p34 PASS at 0.9999x, the hot set clear on all seven; the 16 seeds 2 of 16 done, both PASS, max 1.0064x. The per-pack pass line: (A) accepted with every site clear of 0.995; (B) 0 exhausted of 256 and r under 0.90; (C) every seed within 1.2x over the window model and no 6-sigma bucket outside the known-failed set, the known-failed set reading as it does here (the fold pack expected to move p212 and p225). Per pack one box, the next pack the other. Two defaults: the all pack's F8 point at 1,476,395,008 words needs the hash lane's DatasetGeom threaded through the tool (at 2^28 today), threaded after the three single-feature packs or named owed at 22:30; the 64 x 2^24 point per pack (45 to 100 core-hours) owed in every case, the 16 x 2^22 plus the known-failed set standing in. THE RX 7600 READ (the card-in run on PC 1, 15:46 to 15:50 BST; the detect script of 10:10 still switched the card through /api/cards before the morning's fix, so it ran the whole pass at once): the new key amd:gfx1102 "AMD Radeon RX 7600", 8,176 MB, discrete, the 9070 XT gone, the OpenCL device [1] gfx1102 on AMD-APP 3683.0 (a duplicate [3] on the older 3652.0 platform hidden); the class v5 and v4 fingerprints MATCH on the kit worker; the stock bench 13.88 MH/s at 113 W quiet (0.123 MH/W); the app's own row 13.4 MH/s at 113 W mining; the 1 GiB dataset fits. Per tier: an 8 GB AMD card at 0.123 MH/W sits level with the 9070 XT's 0.097 stock and 0.127 tuned, a quarter of a 5090's per watt; the knob grid (IGNEUM_GRID_CARD=7600) and the 2, 4 and 5.5 GiB rows follow on PC 1 behind the read-width run b (the grid about 16:50, the sizes and the ds55 rows by 17:40); the tier rows from the grid, to the denominator and UI lanes. Lane 5's landing state at 15:5x BST: the gate green on be21940f5; the "retains" verb with the research lane (the default: the review's text verbatim at 17:15; "adopts" re-gated as one word and landed by 18:00); the served link to the close points at the design document on master, so the landing waits for the research lane's master sha (its 17:00 line) and falls back at 17:30 to the branch path. The review's manifest order on the next branch (release-manifest-8, its gate running): site/release-manifest.json served at /release.json with the chain id (4464, 4463 below the floor), the node commit f8da7515 with the pin c9ad753a and acaf08b0 pending, igneum-pow 1c420786 with the freeze fingerprint, the mining class (v5 since DAA 68,400, v4 at genesis, the ladder at rung 0), the dataset parameters, finality rule v3 (two thirds of active and two thirds of total, the frozen table from checkpoint DAA 0), the SP1 program ids from the ELF manifest, the verifier off per P21, the fee schedule, the versions per platform with SHA-256, every block labelled; /build, /economics, /miner, /evidence and the litepaper's Devnet 3 line read from it at build (held by a new gate check); /light, /receipt and the light client now say two thirds of total weight; 4463 marked historical in spec 07 and six older docs; every dated /bench entry with a "Historical record of " line; the evidence page's sixth label "activated" and the reference-repository wording; landing after lane 5, before 19:30; the economics "who pays for proving" section by 21:00. The floor-sm amendment (66bc6ca7, the memory-clock ladder) landed as b1b8d833 at 15:57; the denominator amendment 6d0f11e5 about 16:07. THE AMENDED CLASS V6 CLOSE LANDED on master at 16:12 BST as cbf5aa46 (the merge of counter-asic-4 0c8a0625, full gate green 73, pushed to all three box mirrors), 48 minutes inside the 17:00 clock: docs/design/class-v6-rotating-family.md section 10: 10.0 the table; 10.0a the lifetime unit marked superseded; 10.0b the precedents sourced with the RandomX wording; 10.0c the sweep; 10.0d the rotation schedule; 10.0e the window with the card's cost MEASURED (within 5 percent per load, no spill, on a rented 5090 and 4090); 10.0f the first review's five corrections with lane 3's profitability surface; 10.0g the second review's seven; 10.0h the served text, the one word made honest with the audit lane ("Class v6 adopts the 64-register window and retains it across every rotation"); 10.0i the adversary's re-optimised core and the bracket the served figures sit in until the k lane's placed gated rows (17:30; the audit lane holds for them and serves once, 18:30 if late). The coordinator's earlier copy of the design file on master superseded in the merge. An amendment after the landing, on the branch for the next landing: the multi-family adversary lane's first core puts the 64-register window in a macro at k 0.40 node-for-node for the whole draw and reads that the window knob buys the card nothing against a macro file; the k lane's own SRAM-banked model says the opposite (8.5 to 10.5 pJ, not cheaper than its gated flops); carried as a disagreement the two lanes' placed rows settle (17:30 and 18:30), the served window line read as: measured cost under 5 percent, about 0.13 of k against a flop-file adversary, possibly nothing against a macro-file one. The multi-family adversary lane's first rows at 16:4x BST (synthesis only, ASAP7 TC, random-input gate-level VCD; the SRAM macro term modelled; node factors claimed): one in-order SIMD core with the 64-register window in an SRAM macro per 8 lanes and the imem in two macros, every unit operand-isolated, a 5-phase single-port slot, every bank entry as firmware (fold constants, select tree, shapes, W = 4, atoms as programs). The genesis-only variant (10 families, 8 lanes, 66,973 cells plus 3 macros) on the class v4 draw: 5.9 pJ per lane-op at ASAP7 (5.1 to 7.7), 4.1 at N5, 3.0 at N3; against the card's measured 10.3 pJ per op on the same draw at the 1,300 lock, k = 0.40 node-for-node (N5) and 0.29 a node ahead (N3); at stock 0.22 / 0.16. Per family at the lock (k N5 / N3): add, sub, xor, rotl, rotr 0.45 / 0.33; or 0.36 / 0.26; mul 0.32 / 0.23; mad 0.55 / 0.40; mulhi 0.12 / 0.09; shfl 0.083 / 0.060; the load with the fold 0.43 / 0.31. The whole-hash shadow at 102,612 ops: 0.42 µJ at N5, 0.31 at N3, so the GDDR7 board with this core reads 2.33 / (0.466 + 0.42) = 2.6x against the 5090 at its lock node-for-node (2.9x a node ahead), the 5080 at its lock 2.3x / 2.6x. Meaning: the adversary's re-optimised core (SRAM state, port time-multiplexing, operand isolation) sits 15 percent under the k lane's 32-register flop core and 40 percent under its 64-register flop core at the same node, so the 64-register window is not the robust knob it read as; the review's rule 5 holds. The full 18-family variant (95,678 cells, +43 percent) in the power step, the placed 8-lane core at CTS, the 32-lane cores in synthesis; six rented hosts, USD 1.2 an hour. The connected-state lane at 16:55 BST (class cs64s27x16, research, behind --class, never a chain class; branch class-v6-connected 69649ab45): a 64-register window per lane; per step a 4-byte load from a window register, then a block of 27 distinct instructions run 16 passes, the next address from the block's last instruction on a fresh spine, the result folding all 64 registers; 128 loads + 55,296 ALU per hash (v5: 128 + 55,680); text 448 per iteration (v5: 320). Liveness (seed igneum-v6c/0): 63 of 64 registers necessary for a later address at every one of the 128 addresses until the last iteration's tail, the result reading 64; per step an address depends on 1 to 15 registers of the previous address point (mean 11.2): the chain narrow per step, the whole window necessary over the hash; each block touches 16 to 24 registers, every register read 384 to 3,208 times and written 128 to 1,664 times per hash; a specialist must hold 64 x 32 bits live per lane and can bank them (about 20 hot per step, the set moving with the text). Census (the sub-version 3 harness, (c''') on): no era 256 of 256 accepted, 0 exhausted, 0.28 rejections per candidate (the control mx8+sh256x27 0.67), mean attempt 0.39 (control 2.0); eras 0 to 7 at 32 seeds each with the window-bit refusal on: 256 of 256, 0 exhausted, mean attempt 1.7 (control 4.9), 306 window-bit refusals (control 218): the product-bit class the layer-1 index fold removes, present as in v5; F8 form at 16 seeds x 2^20: the top 0.1 percent share 0.999 to 1.002 of the uniform control. GPU at stock on a rented 5090 at its 575 W cap (the class v5 nvcc harness, 250 batches of 2^24, both packs minutes apart): cs64 64.93 MH/s at 574.8 W against v5-genesis 65.30 at 574.8 W, energy per hash +0.6 percent (8.85 against 8.80 µJ in this harness); ptxas 80 registers per thread (v5 48), 0 spills, 24 resident blocks per SM; fingerprints cs64 ad0cec2a42c84aff, v5-genesis ae74193ddad19e19, vectors 3 of 3 PASS. Meaning: the window costs the card under 1 percent of energy per hash at stock, far inside the 10 percent budget, and a chip a 64-entry live file per lane. The 4090 row by 17:15, the PC 1 lock row owed (the bound emitter building); the k lane's score and KEEP or KILL at 18:00; connected-state.md with every row by 17:45. The 0.3.26 Windows entry live at 16:11:04 BST (installer 8e674bd5 from 1f4904e0, host-less, both folders and the public alias, read back live): EVERY PLATFORM ON 0.3.26 (Mac and HiveOS 16:02:53, Windows 16:11:04), the PCs by their update checks. The network: dn3-g1 refused dn2-1's branch at 16:06:55 with a genuine InvalidPoW after its full replay (dn2-1 sat in the held group and mined on 5b673577's object through the stall, so its branch's state past e1f65284 and its epoch 21 reference are foreign to every f8da7515 node); the fleet's default taken at 16:12: the chain is p1-4090's branch (sink 486a7cb6, mined on c9ad753a's object from 14:50, under the epoch 21 line), its miner at its sink, the rest by IBD, the hubs as they converge, dn2-1 wiped after. The rule candidate for the next line (the node lane's reading asked): a held box never mines on the old object past a digest-moving minute. The denominator RX 7600 delta (29df04cf, denominator.md plus class-v5-tiers.json at 31 classes) landed as c3911a8c at 16:12; twelve research landings today. The class v5 lane's ask at 16:4x: no class v6 order had reached it (the shipper's relay named its items second-hand); the coordinator sent the order's text at 16:45 with the lane's item: the class v6 kit, the six-platform fingerprint read on the hash lane's class-v6 merge on the all-together pack, the known-failed case first (the plain-address pack reading a different id from the fold pack on every worker), the kit zip on build-1 with its sha by 23:00, the Arc and the AMD through the PC job runners, the Mac by the Mac chain; a miss means the kit ships tomorrow morning on the merge's last green commit with the platforms read so far named, and 0.3.27's pin waits on six equal reads. The enforced-proving lane (ledger P21) at 16:15: the test set and the full crate suites green on build-2 ahead of 18:30 (igneum-exec 64/64, kaspa-consensus 138/138, kaspa-consensus-core 171/171): a valid SP1 proof a condition of payment in consensus behind the named switch verifier_in_consensus, false on every compiled object (the live Devnet 3 object unchanged; igneum-testnet-1 gains the payment rule on its DAA floor 0; the class v6 object carries the switch true); six consensus-side and seven executor-side tests named per refusal, known-failed first; branches enforced-proving (b6a538b65: docs/spec/proving-enforcement.md, the P21 and P22 rows, the 60x switch listing, infra/fast-time/proving-enforcement.mjs) and enforced-proving-node (the fork, edf45887 plus one import fix, off acaf08b0 with f8da7515). The coordinator's word at 17:00: the main-repo branch lands on master through the gate now; the node commits take release-0.3.27-node, the line the node lane cuts from the class v6 object tonight, the branch tip and its suite lines to the node lane for the merge under the object's gate set; the verify-cost row by 20:00 (the stated 0.26 to 0.53 s cold verify per record labelled stated if no core by 19:00). The record's forty-ninth landing's merge gate killed by signal 15 twice more at 16:1x BST on the Mac (rule 4 refuses the class in scripts; a hand command still reaches it); the third run in the background. The three gate kills at 16:14:24, 16:17:20 and 16:18:15 BST found by the coordinator in the lanes' transcripts: the site audit lane's shell ran pkill -f "tools/ci/pre-push.sh" in its spec-accept-23 scratch tree each time, the kill-by-name class the CLAUDE.md rule forbids since 12:5x; the lane told to end its own gate by its pid file only; the record's forty-ninth landing re-run a fourth time. The steward at 16:33: the class v6 matrix on the node lane's first sha 617cb441 (class-v6-node, app tree 89e83df2, the class v5 freeze tree linked, the parent's 60x file at bf2c878d's three keys) started 16:33 on build-2 and build-3 at gate priority, seven suites each, the line by 16:55; the object commit's matrix the same way the minute its sha lands. IGNEUM 2.0, decided by the founder (main's relay stamped 17:45 and 18:2x to 18:3x on a clock two hours ahead of the Mac; the Mac read 16:28 to 16:36 BST): "this is now Igneum 2.0, Miner v2.0.0, the testnet is scrapped (the go ran, nothing mined, seeds stopped and held), Devnet 3 is the network", then at 16:3x everything off and the network restarting as the Igneum 2.0 devnet (igneum-devnet-4, node 2.0.0, fresh genesis, enforced proving from block zero; the shipper leads, the fleet and build-server lanes execute); the reference docs/plans/igneum-2.0-reference.txt with the pins in docs/plans/igneum-2.0.md ("This is your reference, always, do not stray"), landed on the box mirror's master as the first act by the build-server lane (72a5f9bd on build-server; the coordinator's own landing of the same two files failed its gate on the site sweep's live /swap render and was dropped). The plan's objective: durable GPU competitiveness, not chip destruction; the positioning line on every served page: "A GPU-secured network for Ethereum-compatible applications and verifiable computation"; the three boundaries wherever the proof architecture is explained; the standing rules carried in (more layers is not more resistance; rejected knobs stay out as regression controls; the adversary re-optimised after every change, synthesis k never a lower bound, placed rows score; the 10 percent GPU-cost budget set before results; "every chip dies within a family epoch" out of the baseline economic model, no chip-arrival percentages; no ASIC detection, whitelists, attestation, quotas or self-reported bonuses; rotation optional to the security argument; energy, economic and response capability reported separately, the cohort = the discrete-GPU population; mining resistance, proving competitiveness and system stability three questions). D1 the frozen reproducible baseline (the coordinator with the hash and node lanes; the pass: an independent operator reproduces it from the served kit alone); D2 two experiments (a) CLOSED by the connected-state lane's KILL (1.10x against the 1.25x gate; window width the one robust knob; rearranging the same ops moves nothing) and (b) memory sharing, recomputation and data-local execution against v6 (the adversary lane); D3 the programmable survivor chip (the adversary and k lanes; placed rows, the three-year life, the next-generation matrix, the dataset schedule scored per step, state coupling justified or dropped; 1.5x energy a research goal, not the pass); D4 the five-year coexistence model replacing the capex wall (the research lane; the sunk-dev-cost case mandatory; miners react; the tip-share discrepancy resolved); D5 the no-rescue network exercise (the node and build-server lanes on the three ex-testnet seeds; enforced proving the prerequisite); pools, architecture and product, versioning (Miner v2.0.0 from the 0.3.26 line; node 2.0.0 once enforced proving is on the network), the leadership tests (benchmarks against Ravencoin KAWPOW, Ergo and Firo's reference miner; the ranking ceiling "serious contention for the top of the GPU-mining space on engineering and operator proposition"), and the site reset (the served site starts at 2.0; site-pre-2.0 tagged; the facts page wiped; the FUD ledger written fresh with every entry naming its pin). THE DRAIN at 16:37 to 16:50 BST (the Mac's clock), ordered by the founder ("have we pulled all current jobs from all builders and boxes? and spinning up 2.0 work?"), read-back to main at 16:50 and accepted. Stopped by pid file: the attack pass's ten leases on build-2 (five F9 upper chunks, three F1 parts, the chunk-5 and parity waiters) and seven on build-4 (six F9 lower chunks, the F1 lower-range waiter), rows kept (F9 135,836 seeds, max attempt 32, 0 exhausted; F1 172,310 programs, one letter miss at 5.0781 percent, parity unread), the partial landing on attack-pass as lane (d) rows; the build-server lane's two bs0322 zigbuilds on build-2; the node lane's Devnet 3 monitors on build-1; the steward's 617cb441 matrix; the shipper's host-0326 preview on PC 1 and the 0.3.25 takes on PC 2; the acaf08b0 move withdrawn; release-0.3.27 superseded; every rented pod of the hash, size, knob, connected-state and mixed FP32 lanes destroyed. One reversal by main: the finality-boundary lane's two build-3 runs (the v3.mjs split50 harness and the N1B/N2B sim), which the coordinator stopped by pid at 16:39 under the drain's default, are KEPT under D5's partition row; the lane restarted them at 16:40 (pids 866903 and 866905, class measure, pool 4) with rule v4 and the measured N1 to N6 on branch finality-boundary (286cb43e8). Kept with pin: D1 on build-1 (the node lane's object checks and crossing), build-2 (the hash lane's window suite and re-exports, the enforced-proving crossing on local nodes), build-3 (the census's rw2 points, lane D's best-mix acceptance at widths 1 and 4), build-4 (the census's control and foldrw points), PC 1 (the read-width lock rows as controls, the 7600 grid, sizes and ds55 rows); D2(b)/D3 the adversary's six hosts; D3 the k lane's pods; the enforced-proving suites on 74803660 (the devnet-4 cut). Started with pin: release-2.0.0-node (the node lane, devnet-4), the seven-refusal re-run on the cut sha, the D2(b) harness on build-2's freed cores, the 2.0.0 matrix on release-2.0.0, the coexistence harness on build-4. The pool vote-key commitment design doc assigned by main to the attack-pass seat (a first complete draft by 20:00); the second-prover pin held (no box work tonight). The consolidated map to main at 16:58. The afternoon's rows under the new pins. The census sheet (D1): hl-v6-fold PASS (the program accepted, min site ratio 0.99986, bucket +5.25 sigma, worst free index bit 2.84 sigma, no site over 6 sigma against the class v5 control's -448 at one site's bit 9; the attempts census 256 of 256, 0 exhausted, r 0.701, mean attempt 2.34, max 14, (c''') 0.35 percent; F8 at 2^22 on p18 to p33 16 PASS at most 1.0455x; the known-failed set at 2^24: p4 1.0057x from 1.2163x, p8 1.1663x within the gate with a +6.58 sigma bucket from 1.3787x, p10 1.1868x from 1.5052x, p15 PASS, p212 1.0411x with a +27.3 sigma bucket from 1.1917x, p225 1.2414x BEYOND the gate unmoved (the value-level class, not an address bit), p34 1.0486x with a +11.9 sigma bucket the fold creates, the one regression): the fold does what it was drawn for, the four tail ratios fall from 1.22 to 1.50x into 1.01 to 1.19x, the stride-bit bias gone from the address, and against the class v5 control on the same 16 seeds (5 of 16 flagged on the 6-sigma windowed bucket) the fold's 0 of 16 is a measured gain. hl-v6-rw PASS (accepted, min ratio 0.99990, r 0.117, the lowest per-candidate rejection ever measured on the family, 256 of 256, 0 exhausted, max attempt 2, (c''') 0.34 percent; F8 at most 1.1526x; its 4 of 16 bucket flags at the control's own rate of 5 of 16). foldrw (accepted, min ratio 0.99993, no biased bit, r 0.117) and rw2 (accepted, min ratio 0.99990, two sites with the stride bit at -64 sigma as expected without the fold, r 0.410, (c''') 1.15 percent) with their F8 points queued; hl-v6-win not yet on build-1; the all pack's 5.5 GiB geometry in the f8 tool, untested. The hash lane's D1 line: the window hand's suite and the hl-reg64c and hl-v6-win re-exports on build-2; PC 1 in order the read-width run b, the 7600 knob grid, the 7600's 2 and 4 GiB sizes, the 5.5 GiB rows on the 7600 and the 5090 (the 5090's 1,300 MHz row at 5.5 GiB = the PC 1 lock row), then the cs64 row at the tail. The research lane's third close landing d6bee526 at 16:38 BST (10.0m the adversary's whole-machine rows; coexistence-model.md as its own file, the sunk case first: the GDDR7 board passes all six conditions at a one to three year life, the N2 SRAM die fails five once built, the only condition holding it that nobody pays to build it; 10.0n the three statements re-read: energy whole-machine per tier, economic from the model with capex per accepted hash the main term, response capability as versatility not life), its second landing fc1f9b62 at 16:26 (10.0l the objective and the claim statement), and 10.0o on the branch: the mixed FP32 candidate KILLED (determinism bit-exact on CUDA and the CPU across three cards; the determinism tax the whole economics: +14.8 percent energy per hash for fp12 on the 5090, +19.0 on the 4090, +26.5 for fp24, against about 7 percent of chip edge, the operand confinement integer work at integer k; the exponent-byte bias on address bits 23 to 30 a new instrument reading worth a layer-4 rule; FP32 a negative control; docs/analysis/class-v6/mixed-fp32.md on class-v6-mixedfp 255be026). The app window audit lane: the window rebuild ebb20c46 already an ancestor of release-2.0.0 b891444f and 0.3.26's 1f4904e0, so the v2.0.0 clock starts from b891444f; its record on master at c86a7e23. The site audit lane: spec-accept-23 and release-manifest-8 landed as 2966599e at 16:33 (the chip serve with the claim statement and the bracket, /release.json, the economics proving section) and tagged site-pre-2.0 at 16:35, the pre-reset state closed; the reset on three branches (site-2.0-lite, site-2.0-pages, site-2.0-facts) on main's clocks: the wipe 17:15, the facts and ledger 17:45, the litepaper and positioning 18:00; its gate moved to build-2 under /srv/builds/_site-gate; the Devnet 3 manifest regeneration and the 2.1x placed-row swap stopped as superseded. The shipper: the copy pass its own hand (the session's concurrent-subagent cap of twenty reached, so no opus hand spawns from any lane until one closes): the About and footer positioning line, proving on NVIDIA against mining on AMD and Apple, "the Igneum 2.0 devnet" wherever the app names the chain, the engine's network move to igneum-devnet-4 with the testnet choice gone, on release-2.0.0 by 17:05; the readiness clock to main at 17:00 on the UI lane's network step 17:10, the update-return lane's prover-host install 17:20, the devnet-4 node artefact 17:15, the chain about 70 minutes behind the last. The attack pass's partial on the mirror's attack-pass at d7943c8a (feature gate GREEN, 16:4x BST): F9 206,980 new seeds (306,980 with the record), 0 exhausted, 0 panics, max attempt index 37 (seed 421302; 718097 at 32); F1 217,310 programs, 0 mismatches, TWO letter misses at 5.0781 percent (attack-f1/392513 and 865158, both 13 of 256, the v4 miss's exact saving; rate 9e-6, the v4 rate), parity owed and not made, both named for the D1 harness on the class v6 generator; both boxes clear of its leases; the seat takes the pool vote-key commitment design doc (docs/design/pool-vote-key-commitment.md on master by 18:30, the sha and the surviving attack to main). Main's three additions to the map at 17:1x: D1 includes the spec (docs/spec/01-lottery-hash.md at 0.2 of 4 October, generator v2; the node lane re-cuts section 01 to the frozen object with the five digests in the 23:30 landing); the pool lane's 0.3.20 branches rebase whenever that lane next answers; the second-prover pin held; the finality lane's two D5 leases wait on build-3's pool, and at 17:30 the census's lowest-priority F8 run moves to build-4 to free them. Every active lane mapped and told by 17:16: the hash lane D1, the census lane D1, the node lane D1 and devnet-4, lane D D1 (the acceptance) with the rotation prototype paused, the k lane D3, the adversary lane D2(b) and D3, the research lane D4, the enforced-proving lane the devnet-4 cut, the steward the 2.0.0 gates, the site audit lane the site reset on main's three clocks, the reference-apps lane compatibility, the attack-pass seat the pool design, the finality lane D5, the shipper versioning and the devnet-4 move, the build-server lane execution and deploys. A BOX FAULT at 16:40 BST (the Mac's clock): build-3 (62.238.91.43) answers neither ssh nor ping (it answered at 16:37 with load 83 and 24 held cores; lane D lost its ssh at 16:4x); it carried the census's rw2 F8 points, lane D's exact-table acceptance (466 and 401 of 1,500 eras) and the finality lane's two D5 leases (restarted 16:40, pids 866903 and 866905); the build-server lane reading the Hetzner console with a hard reset as the default; lane D's two runs queued on build-2 as the fallback; the box out of the pool for tonight if not back by 17:00, the lanes re-queuing on build-2 and build-4. THE DEVNET-4 CUT on both node mirrors at 16:42 BST: release-2.0.0-node c04674fe (acaf08b0 plus the enforced-proving lane's two commits plus node 2.0.0: igneum-devnet-4 with its own genesis 7c36b83374a673e9 stamped 2026-10-08T15:00:00Z, digest 08aae61c0dc8cc1d1fa35f8cc776a924f3ec9d231ac2d15a53cf030191d378b9, every switch at 0, class v5 with byte 6 from genesis, verifier_in_consensus with proof_rule_active_from() 0 and the embedded ids pinned, chain id 4465, base unit 10^18, igneumd/2.0.0, the mid-epoch resume rule; the class v5 freeze pairing unchanged); the artefact, suites and canaries (with a devnet-4 step) running, the pair on build-1 by 17:05; none of the node lane's gates needs a live chain. Lane D under the pause: nothing to stop (every stratum, the lossy curve, both live censuses, the sigma reads and the verifier rows complete in 81b90128d); the or-floored copy of the best-mix acceptance complete (3,000 eras at width 4, 1,500 at width 1); the exact-table acceptance (add 14, xor 13, mul 4, mad 11, shfl 3, rotl 10, sub 9, mulhi 2, rotr 9, or 0; fg9) PASS so far on the F8 census (2^20 x 64 seeds, 0 hot sets, 0 over 1.2x), the attempts rows as the verdict by 18:00 from whichever box answers. Two v7 documents on master through the research-landing lane: multi-family-adversary.md as f6bab871 (16:36 BST; tools/chip-model/mf on the branch) and connected-state.md with its logs as 3919d430 (16:44; igneum-pow on the branch), both full gates GREEN 73; fourteen research landings today. The reference-apps lane's pin line at 16:52: /light, /receipt and /oracle serve as the network's (84c33a4f); the read service and the eth_getProof reader on build-1 re-point to devnet-4 the minute the pin and genesis are named (the reader rebuilt on c04674fe, the service an environment change); the pages re-run against devnet-4 once block one and a paid segment record exist; the oracle's Devnet 3 certificates kept as a record; the compatibility pin served as /compatibility from docs/build/compatibility.md plus a results file from a runner (tools/reference-apps/compat/run.mjs executing every row against the devnet RPC with a funded sender; a row a landed test with its evidence or "untested" with the reason): representative contracts, wallet fee estimation, indexing, failed transactions, receipts, application assumptions, and the measured differences (coinbase the including block's miner; prevrandao's source; the two-dimensional fee fields); nothing of its mines, votes or holds weight; the draft on master by 20:00 with the rows run on devnet-4 from 18:00. The fiftieth landing on master at 16:50 BST (f29dae620: the decision, the drain, the map); the plan and reference files were not on master (the build-server lane's 72a5f9bd chain never arrived), so the fifty-first landing carries them from the Mac checkout, byte-identical. The census sheet at 16:50: hl-v6-foldrw PASS (accepted, min site ratio 0.99993, largest bucket +5.75 sigma, worst free bit 3.49 sigma; 256 of 256, 0 exhausted, r 0.117, mean attempt 0.13, max 2, (c''') 0.34 percent; F8 at 2^22 15 PASS, 1 flagged (p18, against the control's 5 of 16), ratio at most 1.0932x; the known-failed set every ratio within the gate: p4 1.0002x, p8 1.0138x, p10 1.0100x, p15 1.0088x, p34 1.0121x, p212 1.1111x, p225 1.0000x, buckets flagged on p15 (+9.3) and p212 (+24.5)): with the fold in front the table's programs carry no address-bit class and the tail reads as the fold pack's; the sheet fold PASS, rw PASS, foldrw PASS; rw2's F8 points stranded on build-3; hl-v6-win placed (program f42d4a743ce7d4fa), its harness build waiting on reg64-v5's sha. The steward at 16:45: build-3 unreachable from the Mac and from build-2 inside Hetzner (the host or its network, not a load state); its half of the 2.0.0 matrix on c04674fe died on the first suite, the matrix on build-2 alone, the verdict by 17:40 from build-2's seven; the GitHub poll stopped. The fast-time lane's rule (f) on the class v6 object 617cb441 (16:24 to 16:48 BST, the freeze fingerprint on both binaries): every reading green: v5 by floor at epoch 8, class v6 from epoch 9 at its floor with the object line on every node, byte 8 on every block from genesis, 12 of 12 ids equal to the CLI's, the template at every boundary, the stale node refused under v6, the restart step resynced in 8 s, the cold restart on 4 of 4 nodes (660 s stopped, snapshots removed, each restarted on its kept datadir with the cold-restart line, no wait line, one sink 15 s later, every miner accepted after); the known-failed shape (a 60 s wait) FAILED as it must; the SUMMARY's four harness-scope FAILs (counts and a read window the cold restart moved) fixed, the clean PASS from the rerun about 17:25; the object fact: with the v6 floor set the node stamps byte 8 from genesis, so v5 cannot flip by signal on a v6-enabled file and comes by its floor; the c04674fe pair's run armed on its artefact path. The k lane at 16:5x: the placed gated core8r64g slipped to about 18:30 (floorplan timing repair on the pod), the five other cores by 21:00; the row serving meanwhile on the synthesised gated 64-register core, the GDDR7 board against the 5090 at the lock 2.6x node-for-node, 3.0x a node ahead, 3.4x two nodes ahead, the placed figures expected at 2.1x to 2.4x and 2.5x to 2.8x with the placement uncertainty (+30 to +65 percent on the chip's pJ per lane-op), the served bracket tightening to its lower half. The research lane's D4 tip-share resolution written (counter-asic-4 1e183dc0: docs/design/proving-payment.md, spec 5.1 to 5.3, O-5.7 closed): the tip stays whole to the block (80 percent to the producer, 20 to the developer registrations), no part reaching the provers; the provers paid by the explicit user-funded congestion-priced proving payment (f_p times pgas used), 90 percent to the block's proving pool per shard by consensus proving cost and 10 percent burned instead of burned whole; the burn listed in one place; the hard cap and no development tax untouched; the one code pin (executor.rs at the proving base fee debit, behind an activation constant) assigned by the coordinator to the enforced-proving lane on a branch off release-2.0.0-node, never on devnet-4's object tonight, by 21:00; the served form of the coexistence result in four sentences (the IGN clause held out by the standing rule); the five-year run with miners reacting and the operator simulation on floor lane 3 (20:15 and 20:30), landed by 21:00. The adversary lane's jobs at 16:5x: six Vast hosts on D3 (adv-b the placed and routed 8-lane 18-family core plus its 29-tag power run; adv-e the placed 8-lane genesis core; adv-f the placed 32-lane 18-family core; adv-a and adv-d the 32-lane synthesis-only rows; adv-c idle, kept for the D2(b) harness's compute); the D2(b) harness to build-2 through the lease pool when its trace tool is cut, the first row by 19:00. The rotation lane's run 5 refused a build-2 window tonight (the run-4 results the control; run 5 tomorrow's amendment). The site audit lane: the wipe branch site-2.0-wipe df465d47 in the site gate on build-2, landing about 17:00; one fault of its own: a test push of release-manifest-8 ran the full gate on the Mac once (16:37 to 16:44, checks only); the 6.1 GiB and 7.5 GiB peak fact not served (no record); the research lane's four coexistence sentences and the k lane's tightened figures on the landing after the wipe. Correction at 16:5x BST: the 6.1 GiB miner and 7.5 GiB proof fact HAS a record, docs/analysis/class-v6/coexist-rows.md at 11653ece (the coexistence rows lane, landed 16:48): the RTX 3060 12 GB at 26.82 MH/s with 6,129 MiB resident and the compressed shard at 13.2 s with a 7,525 MiB peak (13,654 MiB against 12,288), the RTX 4060 8 GB at 6,116 MiB and 7,532 MiB, 8.2 s, both with the miner paused; the 3060's 8.9 GB row of 6 October stands as a 1 GiB-dataset row (1.4 + 7.5), reconciled in the file's section 4; it serves on the site lane's follow-up landing: 16 GB to mine and prove together at the 5.5 GiB floor, 8 and 12 GB time-share. The served chip figures are 10.0h's on master at the follow-up gate (the research lane's 17:5x form "2.5x to 3.0x, 2.1x to 2.6x on the GPU's own node" on the branch now). The v2.0.0 cut tip: release-2.0.0 a9e2df26 (b891444f plus the network move and the copy pass by the shipper's hand, net-20 775c6d87 whole with the blank-step fix, prove-host-20 2368dd7f, the 16 GB proving line), every push gate green, the crate gate on build-1; the window copy checked by the app audit lane PASS at 16:5x (two follow-ups after the cut: the positioning sentence twice, the one-card network step); rule (2) rides v2.0.0 as proving OFF by default under 16 GB with the switch labelled ("mining and proving together need a 16 GB card; this card does one at a time, mining continues"), the finer claim rule v2.0.1, rule (1) the node lane's 2.0.x queue; the floor lane's packer guard and sidecar in the build-server lane's packers; the shipper's clock: the node artefact 17:05, its gates 17:25, the hub-1 canary 17:30, block one about 17:40, Mac and HiveOS entries about 17:50, the RPC and explorer 18:00, Windows 18:05 host-less or 18:20 with PC 1's host. Enforced proving landed on master at 16:59 BST as 5423b3277 (the merge of enforced-proving 3d2c7b41, gate green; mirrored to build-2 and build-4, build-3 down); the node side on release-2.0.0-node under c04674fe; the fast-time crossing's fourth run on build-2 (the third observed the finding below the floor, then its ssh died). THE D4 CODE PIN built by the enforced-proving lane on branch proving-payment off release-2.0.0-node c04674fe: Params::proving_payment_activation_daa (u64::MAX on every object, in the digest once set, in the 60x file); the executor's two proving-charge sites split by proving_payment_split (off: the whole burn as today; on: 90 percent to PROVING_POOL_ADDRESS and the block's proving_pool_credit, so the per-shard payout of 5.3 carries it; 10 percent burned, the rounding wei to the burn); the receipt's proving_payment and burned_proving; the known-failed test the_proving_payment_burns_whole_below_the_floor_and_credits_90_percent_to_the_pool_from_it and the params test the_proving_payment_floor_is_never_on_every_compiled_object; suites on build-2 from 16:56. THE CONSEQUENCE FOR MAIN before any height is named: the shard guest (proving/igneum-prove/core/src/executor.rs lines 290 and 318) burns the whole proving charge exactly as the node did, so with the node's floor set and the guest unchanged every shard proof's post-root differs from the node's statement past the floor and no record verifies; the guest needs the same split behind the same switch in its fixture env, which changes the ELF and the pinned shard program id, before any object sets the floor; the node pin is safe at never until the guest ships with it. The pool vote-key commitment design doc on master at 637e508b (16:54 BST; branch pool-vote-key 611e9bf5, full gate GREEN): the header's vote_key_hash is under the pre-PoW hash already (header.rs:174), the reveal IGNK in the coinbase, weight reads headers, pool v0 names the member's key and pays the pool's IGNA, the open pool pays the window by IGNW with no operator; the litepaper's "vote keys stay with the pool" the one line contradicting the code (O-9.1, G6); the design keeps the commitment in the header (proof of work binds it, one 32-byte compare) and adds vote_key_hash to the job and the share so a pool cannot credit work on any other key; payment aggregation the pool's IGNA (operated) or the block's split (open), both verifiable; twelve attacks, the survivor A5 custody by consent (a pool's terms plus a client fork), answered by the refused-by-default custodial mode, one key per pool address on the explorer's concentration page, and the market; costs 0 new header bytes, 64 characters on share and job, one comparison per block; migration: the pool branches rebase onto release-2.0.0 first (pool-finish-22 1 ahead 112 behind, pool-finish 11 ahead 572 behind, pool-v0-rebase 4 ahead 925 behind); six open questions for main. The attack pass closed (its report: F4 PASS at 2^28 days, F8 PASS at 256 seeds, F9 and F1 partials; one exception of its own: a gh auth switch to the founder's personal login at about 10:0x BST under the hook's remedy, against the rule, reported). CLASS-V6 GREEN AND ON THE MIRROR at 17:0x BST: 3f25a8305 (the merge 6db297da1 of class-v6-fold 7880bc96 and reg64-v5 198d171d, one brace fix; build-2's suite 136 passed, 0 failed, 8 ignored); one class string carries every flag: mx8+sh256x27+state+reg64c+fold+rw; hl-v6-all exporting on build-2 at log2 28 (1 GiB; a state class refuses --dataset-words, the 5.5 GiB form the ds55 lane's, non-state). The D1 gap: reg64c has CUDA kernel text only (the OpenCL text a refusal stub, Metal the same), so hl-v6-all cannot read on AMD, Intel, Apple OpenCL or Metal tonight; the honest kit line "all pack: CUDA and CPU equal; the partner hl-v6-foldrw: six equal (fold f6c34aa6e87bf211, foldrw 5a6ad122a71a888f, rw 964ce3ba78b92a32 on the emulation, Metal and Apple OpenCL); the window texts owed"; the hash lane ordered to emit the window's OpenCL and Metal texts after hl-v6-all by 23:00. THE D2(b) FIRST ROW at 17:3x BST (modelled on the mf core's synthesised rows at N5, the record's memory figures and adv-cache-2's measured window-layer hit rates; harness tools/chip-model/mf/flow/d2b.py on the lane's rented host, build-2's pool full): the served convention, the 5090 at its lock over the chip machine on its own GDDR7 board: the baseline 1.82x (1.52 to 2.06); the bracket MOVES by one combination: the hottest half of the items in 1 GiB of SRAM beside the DRAM serves 72 percent of reads (the per-program hot set, refilled in 2 ms per epoch), so the activate-bound board runs 3.6x the hashes on the same devices: 2.69x per joule (2.20 to 3.03) and USD 1.88 per MH/s (8.5x the card per dollar) for USD 250 of SRAM (claimed); the uniform-store lower bound 2.30x (1.90 to 2.59) and USD 3.34; the hottest three quarters 3.10x; a node ahead 3.33x and 3.96x; moving nothing: data-local execution (2,112 bits of live state against an 80-bit read, 26x on every medium), memory sharing, recomputation (0.78x), selective participation (9 percent spread across 2,000 era draws; the best-half specialist gains 2 percent of ratio for half its revenue); the line: the served floor against a chip on the same node is the stored-half hybrid at 2.3x to 2.7x, not the DRAM board's 1.8x; the record's partial-store curve missed it by pricing the rest as recomputed. THE HOT-SET RECONCILE (the hash lane, 17:4x): both instruments right, different layers, the 72 one program not the mean: the per-program hot set is the era layout's layer 8 by design (era-layout.md 1.4: each of the 16 load sites reads the whole dataset, an aligned half or quarter at a drawn offset; the read set the union); inside a window the reads are uniform (the measured quarter shares equal the closed form to four digits), which F8 reads per site inside the window; the 72 percent is the Devnet 3 epoch 0 program alone (its top aligned half 0.71875 over 2^31 reads); over the draw the top-half share: median 0.5625, mean 0.5811, p90 0.6562, p99 0.75, max 0.875 (the closed form over 74,613 compositions; 4,096 drawn programs under 4,096 eras match at 0.5808), so Devnet 3's program sits at about p98 and the D2(b) row priced the hybrid on it; at the mean hit rate 0.58 the hybrid reads about 2.44x (linear interpolation; the exact row one rerun of d2b.py at hit 0.581); the rule that flattens it: win = 0 on every load site (layer 8 off; every window the whole dataset), exactly 0.50 at every program, GPU cost zero against the budget (a window is a mask and an offset in the text; the random footprint already the whole dataset beyond every card's cache); what it trades: layer 8 was written against an SRAM-only mirror, and against a DRAM-backed SRAM refilled per epoch the windows hand the attacker 8 points of hit rate at the mean and 22 at the tail; named as a D2 experiment "layer 8 off" for the v6 object (measured on the 5090 and 4090 at stock and the knee against the pinned pack; the chip side at hit 0.50); not a reopened knob (it removes a draw); nothing in it touches the 21:00 freeze. THE PLACED ROW (the adversary lane, 17:5x; the 8-lane genesis core placed and routed on ASAP7 with its SRAM macros, SPEF, gate-level VCD; the full core's routed run 38 of 58 tags): placement and the clock tree add 32 percent to the class v4 draw (7.78 pJ per lane-op routed against 5.91 synthesised at ASAP7; 5.44 against 4.13 at N5), inside the k lane's +20 to +40 band; node-for-node k 0.53 at the lock (0.38 a node ahead) for the genesis core, 0.59 and 0.42 for the full core scaled; the complete GDDR7 machine at the placed energy 1.6x the 5090 at its lock per joule node-for-node (1.4x to 1.8x), 1.9x a node ahead (1.5x to 2.1x); 1.4x / 1.7x the 5080; 2.5x / 2.9x the cohort; USD 4.84 per MH/s unchanged; the N2 SRAM die 2.4x / 3.3x; the stored-half hybrid about 2.4x / 2.9x; placement takes a tenth off every per-joule ratio and nothing off the per-dollar ones; THE HONEST BRACKET against a same-node chip 1.6x to 2.4x per joule (the DRAM board to the stored-half hybrid) and 3x to 9x per dollar; the served 2.0x same-node line sits inside it; the 32-lane genesis core (synthesis) 3.70 pJ at N5, k 0.36; the document 2b30cfd0 with sections 11 to 13 (the data-local cost model, the dataset comparison with the five-line recommendation, D2(b)), "complete" about 18:15. The build-server lane at 17:01 to 17:05: build-1's Devnet 3 nodes stopped by the shipper's pids at 16:34, the observer, the explorer indexer, the faucet and the RPC proxy by unit at 16:38 (rpc.devnet answering 503 "Igneum 2.0 devnet starting"), the light reader at 16:42; the artefacts kept; build-3 still dark at 17:05 (the Hetzner Robot console in the browser pane stuck on its "Security Check" page, no Robot API credential on the Mac); its 72a5f9bd landing of the plan files RED on the site sweep's overlap check from master's served content, so the coordinator lands them (the fifty-first landing, in its gate); the deploys 84c33a4f (16:30) and 5423b327 (17:00: the chip text serve and /release.json, /compatibility and the positioning line, under SITE_TRANSITION=1 with the chain-keyed checks skipped until the devnet-4 feeds exist). The census lane at 16:53: rw2's F8 chain and its acceptance read re-queued on build-4 at 16:54 (the 17:30 move taken early); hl-v6-win's harness building on reg64-v5 198d171d on build-4. THE PLAN ON MASTER at 17:02 BST: b943c0476 (docs/plans/igneum-2.0.md and igneum-2.0-reference.txt from the Mac checkout, byte-identical; the fifty-first landing); the complete 37-page PDF (docs/plans/igneum-2.0-plan.pdf with its text) lands beside it by 17:30 from the landing hand, and its pins sit in the plan's "Addendum from the complete plan": evidence classes and the wording ladder, the never-published list, the release evidence packet, the extra excluded knobs and the one acceptance rule, accepted work's definition, the bring-forward mechanism and seed-boundary behaviour, the adversary transition matrix, the evidence standard and the lifetime rule, the market-structure axis and the sensitivity workbook, operator experience with explicit update acceptance, the six negative proof tests, the D5 scenario table and the four user-facing states, the verification labels, the one machine-readable release manifest, reproducible builds and the signing-key procedure, the spend order (proof enforcement and finality boundaries first while the v6 evidence packet closes; hardware research and one narrow paid pilot in parallel; broad ecosystem expansion waits) and the mainnet prerequisites, the acceptance scorecard as a checklist, the brand kit. Mapped by the coordinator to owners with clocks and sent to main at 17:20 (the site lane 18:00 to 21:00; the hash and census lanes 23:00; the finality lane with the node lane 21:00; the adversary lane 21:30; the research lane 21:00; the shipper v2.0.1 and the manifest 19:30; the enforced-proving lane's map done at 17:06; the reference-apps lane 20:00; the node and fast-time lanes 21:00; the spend order and the prerequisites the coordinator's). The rotation lane closed with its control doc b0e7ba8c; run 5 tomorrow's amendment. THE SIX NEGATIVE TESTS mapped at 17:06 (the tree 019a12b1 on the 0.3.25 line, on release-2.0.0-node as dd84ed6a and f6cd2f00, green on build-2 at 16:15): (1) a correct statement with an invalid proof: enforced_a_record_whose_proof_fails_to_verify_invalidates_the_block and enforced_an_unverified_proof_pays_nothing_and_the_verified_honest_record_pays_once; (2) a wrong program or verifier identity: enforced_a_proof_for_another_program_id_invalidates_the_block, a_real_proof_verifies_and_a_wrong_statement_is_refused, the_embedded_keys_match_the_manifest, plus the daemon's start refusal (exit 3) when the embedded keys are not the object's; (3) wrong chain, epoch or statement binding: enforced_a_record_signed_for_another_network_pays_nothing, enforced_a_replayed_record_pays_nothing_the_second_time, assignment_follows_the_window_and_records_check_against_native_execution; (4) a changed payout identity: enforced_an_altered_payout_address_pays_nothing; (5) a duplicate proof reward: enforced_a_duplicate_of_a_paid_record_by_another_key_pays_nothing; (6) incorrect rewards or consensus inputs, the derivation authenticated: PENDING in the plan's sense, the native-veto test enforced_a_statement_over_altered_rewards_or_payouts_is_vetoed_native_derivation_is_the_check on build-2 (branch proving-payment), the proof-side closure P22's stages 1 to 3, the served label PENDING until stage 3; the boundary sentence in docs/spec/proving-enforcement.md's new section 3a and the P22 row. The node lane's two reads at 17:1x: the manifest block partly served today (igneum_getNodeInfo and the daemon's start lines); node 2.0.1 adds igneum_getManifest (one JSON block printed at start and served on the exec RPC, a test that both are the same bytes) by 20:30, and the four-word transaction state (included, executed, proven, finalised, plus paused with its reason; today igneum_getTransactionStatus hard-wires proven false and reports no pause) by 22:00 with the known-failed test asserting the pre-fix shape; both ride the D1 freeze entry's "what 2.0.1 adds" line. A FAULT: c04674fe's devnet-4 chain (born 16:59:53 BST) is dead by the node lane's re-cut 4cdcc488: its emission literal was Devnet 3's 8-decimal one in an 18-decimal unit, one ten-billionth of the schedule; the emission is in the digest, so be5f4068 replaces 08aae61c on the same genesis; the pair by 17:20, the fleet and build-1 restarting from wiped datadirs on the shipper's word, the first block again about 17:30 to 17:45. Build-3 out for the night (the Hetzner Robot console looping on its security check, no API credential on the Mac; the desk's one-line reset if wanted); the k lane's all-four synthesis relaunched on its pod. hl-v6-all on build-1 at 17:02 BST (the lane's "18:04" stamp wrong): /srv/artefacts/packs/hl-v6-all.tgz sha256 3fc7f75b0eefedd1845d914715c1d6d448bf716d0132a1dba8535e26281d36fe, 50,046 bytes; program id 0x9d40978601a7df2a; class string mx8-erad810f22d+sh256x27+state+reg64c+fold+rw; generator 5; the same era as hl-v6-foldrw (label d810f22d), era widths 4 bytes; state node1 (block 159357, root 1c583d35, 93 leaves); dataset log2 28 (1 GiB, the AND-mask path); program.h IGNEUM_REG64 1, IGNEUM_REG64_ADDRESS_MIX 1, IGNEUM_ERA_INDEX_FOLD 16, IGNEUM_OP_WEIGHTS_TABLE 1; program.json carries the reg64 object (64 registers, the window full chain, 128 statements per iteration, 256 loads per hash) and op_weights (rw1, sum 83); kernel.cu and kernel_bound.cu full (83 KB), the .cl and .metal texts the 169-byte refusal stub; branch class-v6 3f25a8305; the window's OpenCL and Metal texts start on class-v6 after the partner read-back, by 23:00. PC 1: the runner has taken nothing since the 15:50 app restart (the update-return lane has it with a default). The mixed FP32 lane's chip score at 17:1x BST (the k lane's synthesised rows, section 6.1 of mixed-fp32.md at class-v6-mixedfp e6d52e19): the FMA lane 3.4 pJ at N3, k 0.65 on the unit alone, 0.15 at the lock blended with the operand rule (which the chip does in wires and the card in instructions) against ARX's 0.18; the score under fp12 3.2x node-for-node, 3.5x a node ahead; KILL stands on the GPU budget and the full board; the Metal and AMD OpenCL rows owed, labelled; the lane closed on the spend order, its two v7 candidates named in the record (the exponent-fold injection form, the F8-form max-item rule), the document landing through the research-landing lane. The fifty-second landing on master at 17:15 BST (9ac9c195a). THE COMPLETE PLAN landed at 17:12 BST as 7b11fc7f (Merge igneum-2.0-plan-docs 2fb7a476; full gate GREEN 74): docs/plans/igneum-2.0-plan.pdf (257,211 bytes), igneum-2.0-plan.txt (2,292 lines), igneum-2.0.md (202 lines with the addendum); the research-landing lane's other landings: proving-pipeline-2026-10-08.md 8c5da92f (17:06), paid-pilot.md 1cd07adb (16:45), coexist-rows.md 11653ece (16:48); the D4 documents about 17:25 and mixed-fp32 e6d52e19 about 17:35 behind them. THE CENSUS SHEET at 18:1x on the lane's clock (about 17:1x on the Mac's): hl-v6-rw2 (the census lane's own table 13,11,6,10,8,8,7,2,6,4; program 09e91b0dcd458c77; run on build-4 after build-3 went down, about 70 minutes lost) FAIL on the F8 line: (A) accepted, min site ratio 0.99990, two sites with the era-stride bit at -64 sigma (no fold); (B) 256 of 256, 0 exhausted, r 0.410, (c''') 1.15 percent; (C) seed p30 1.3111x over the window model (the class v5 control on the same seed 1.0004x, its worst 1.0698x; hl-v6-rw's worst 1.1526x), beyond the 1.2x gate; the known-failed seeds under this table's draw p8 1.2507x (+42.8 sigma), p10 1.5044x (+100.9), p225 1.4049x beyond the gate, p34 +70.7 and p15 +13.2 sigma buckets: the table that keeps or at 4 and mul at 6 keeps the lossy writers F8's tails come from and adds weight to mad in front of them; the k lane's table (rw1: or never drawn, mul 4) is the one that reads clean; the re-weight is sound in the rw1 form only, rw2 is out. The sheet: fold PASS, rw PASS, foldrw PASS, rw2 FAIL, win and all in progress on build-4 (the 22:30 clock holds). An instrument finding on hl-v6-win (program f42d4a743ce7d4fa, reg64-v5 198d171d, the harness class-v6-census-reg64 1b676975): (A) and (B) read the class v5 control's rows on the same seeds to the digit (min ratio 0.99923, bucket +5.5, one site at bit 9 at -448; 256 of 256, r 0.716, mean attempt 2.52, (c''') 1.66 percent), because the window does not enter the draw and the acceptance's dynamic test interprets the eight-register program: the reg64 window changes the address path (src xor the rotate-xor chain over the other 63 registers) and neither the acceptance's run_unit nor the attack-f8 mirror models it; so (A) and (B) on the win and all packs say the base program under the rule, class v5's own verdict, and the window's address stream is read only through the crate's interpreter: a load-index trace on the reg64 liveness probe (verify::Probe, every load's index per lane; the reg64 line 3345f045e, the class-v6 line 1e6ffa6f9) and the F8-form uniform tool on it (per site the distinct ratio, the item histogram's top-0.1-percent share against a flat control, 16 seeds at 2^22, the era laid over, the closed-form dataset) building on build-4; the win and all packs' (C) from it, the known-failed set not applicable to the window (different addresses), the live-dataset f8 point owed for both; hl-v6-all (harness class-v6-census-all d7d441be, the id reproduced) steps A and B on build-4, its B rows 33 of 256 at r 0.154. THE CLASS V6 KIT at 17:14 BST: /srv/artefacts/packs/packs-class-v6-20261008T160432Z.zip on build-1, sha256 2c56bd063f1a8f60599c5a546c3e38bdf7b00c65adaa6852a0755fe641f0ec3b (847,590 bytes, 42 files), from class-v6 3f25a830 through the kit tree class-v6-kits d731991a (the Metal hosts sizing by the ds55 defines, the v6 kit script, the PC job scripts 6887a0cf); hl-v6-all (9d40978601a7df2a) reads on the CPU verifier (check PASS, 96 of 96 lanes) and on CUDA (the fleet hand's one-shot RTX 4090, 17:09 BST, USD 0.018: check PASS, cache FNV-1a 448274a57f508cbc, fingerprint 59e6708e46f1e87c at 31.4 MH/s, 87 registers, 20 of 24 blocks per SM) and REFUSES on Metal and Apple OpenCL by the stub, so AMD, Intel, Metal and Apple OpenCL wait on the window texts; the partner hl-v6-foldrw (605d06cabc489f94) reads 5a6ad122a71a888f on CUDA (62.6 MH/s, 27 registers), Metal and Apple OpenCL, three equal (the 7600 and the Arc through the PC queues after 21:15); the known-failed shape holds on every platform read; the page's class v6 row at class-v5 2cfe8513. A HAZARD found by the page push: master's counter-asic-4 merge at 6666e199 carries CA4's research changes to igneum-pow/src (the +mm tile and +shl classes, the AP-F4-1 constants in their OLD form, 163 and four rotations; 817 lines against class-v5's post-freeze igneum-pow), so a merge of master into class-v5 conflicts in generator.rs and memhard.rs and would put CA4's code into the class v5 hash object (the 0.3.26 pairing line); the lane aborted it and pushed the page alone; the coordinator's order: the research-landing lane reverts the igneum-pow/src, tests and proto-cuda changes on master from 6666e199 through the gate by 18:30 (the code stays on counter-asic-4), and until then class-v5 and class-v6 take no master merge touching igneum-pow/src. THE NEGATIVE TEST (6) green at 17:10 BST: proving::tests::enforced_a_statement_over_altered_rewards_or_payouts_is_vetoed_native_derivation_is_the_check, commit 421bb852 on proving-payment (on the D4 pin eaddbf83 off c04674fe), igneum-exec 67 passed on build-2 (the first cut failed on the lane's own reading: it altered the record's state root; the shard statement takes the plan's shard roots, so the test alters those); the six-test map and the boundary sentence on master at 17:13 as a6d3ead1d (docs/spec/proving-enforcement.md section 3a, the P22 row); the fourth fast-time run lost twenty minutes behind a worktree lock a dead ssh left on build-2 (its three nodes killed by the harness's pid file at 17:15), running, the result about 17:30. The steward at 17:13: class v6 380cd4eb (app tree 89e83df2, the freeze tree) all seven GREEN on build-2 at gate priority; release-2.0.0-node 4cdcc488's five node-side suites GREEN on build-4 with the miner side on the cut tip 7d82b71e (its pow and app cells green on both boxes, final); build-2's 4cdcc488 column from 17:12, the verdict by 17:28; c04674fe's record all seven green on build-2 and build-4. THE ADVERSARY LANE'S FINAL PLACED ROW at 17:1x BST ("complete 10b901a46" to the landing lane): the placed 18-family core (8 lanes, routed, SPEF, 58 tags) 9.36 pJ per lane-op on the class v4 draw at ASAP7 (8.6 to 11.1), 6.55 at N5, 4.72 at N3; placement +42 percent on this core, +32 on the genesis core, so the bank's placed cost is 20 percent of energy and 41 percent of cells; k 0.64 node-for-node, 0.46 a node ahead; the machine: the GDDR7 board 1.5x per joule node-for-node (1.3 to 1.7), 1.8x a node ahead (1.5 to 2.0), USD 4.84 per MH/s; the stored-half hybrid at the reconciled mean hit 0.581 1.93x (1.65 to 2.12) and USD 2.80, at the p98 hit 0.72 2.09x and USD 1.88, a node ahead 2.40x and 2.65x; the N2 SRAM die 2.3x / 3.1x; THE HONEST SAME-NODE BRACKET 1.5x to 1.9x per joule (the DRAM board to the stored-half hybrid), 1.8x to 2.4x a node ahead, 3x to 6x per dollar; the served 2.0x same-node line sits at its top and reads better as "1.5x to 2x"; the mm8 correction (the card's tile 32 MACs, the chip's op 4: the tile family at 4 points costs the chip +35 percent of lane-ops and +29 percent of energy, the card +29 percent of premium; the ratio holds, credit zero); THE TRANSITION MATRIX (section 14, six rows with bands and labels): firmware -9 to +1 percent per transition, emulation 1.3x to 1.45x while live (slower, not unprofitable), memory USD 0 on the 32 GB board through year 4 (24 Gb once at USD 1,000), the companion host +0.85 W and USD 15 per machine with the proving GPU on its own line, favourable-period mining 2 to 5 percent for 50 to 90 percent of revenue, a revision inside the bank refresh's 360-day notice; no row loses competitiveness, the three-year life holds; pending: the 32-lane full core synthesis (19:30) and placed (21:00), the k lane's crossbar and tile rows. THE RESEARCH LANE'S RE-SCORE at the final placed energies (the board 1.5x / 1.8x, the hybrid 1.93x / 2.4x at USD 2.80 per MH/s, the die 2.3x / 3.1x at USD 2.94): NO VERDICT MOVES: the board passes all seven conditions; the hybrid coexists only in a growing chain at cheap GPU electricity; the die fails once sunk; what moved is condition (b) (hardware per MH/s not under a quarter of the GPU entrant's): on the corrected tickets the hybrid (0.34 of the entrant's) and the die (0.36) now pass it, so the dollar condition no longer fails them; the fleet-cost condition (c) (a third of the chain USD 7 to 54 M against USD 12 to 400 M a year of revenue) and the margin condition (f) on flat and shrinking paths hold the verdicts, the die also failing (a); THE SERVED ENERGY SENTENCE now 1.5x to 3.1x as complete machines, 1.5x to 2.3x on the GPU's own node (10.0t); D4 complete on counter-asic-4 after 9402050e: lane 3's hybrid scoring with the sunk case, the market-structure axis (the board holds under every structure in growing and flat paths with no single supplier above 24 percent; the die under none but private supply in a growing chain), the sensitivity workbook (171 rows, every threshold with its assumptions, none served), the operator simulation, the proving-payment resolution with its code pin; the 21:00 landing at about 20:45. The update-return lane's restart-kind fix green and with the shipper as a v2.0.0 candidate (restart-kind-20 off release-2.0.0, tip da212ee2, suite 317 green, gate GREEN 60, 17:13: under the window host a remote app restart is the host's ladder after a plain EXIT, no helper racing it); the PC 1 desk ask standing with its 18:45 default. The pool design's cost line: the pool's per-share check 0.441 ms per 32-lane group on an M5 Max core, 1.35 to 2.1 ms on a rented 2 vCPU box, one BLS proof-of-possession check per key on its reveal block. The site audit lane's wipe in its gate on build-2 (site-2.0-wipe b9d4aa80 from 17:05; the first box run found a real 24 px padding fault on /light, /oracle and /receipt, the second its own half-fix; the landing inside 17:15 on the GREEN line). THE DIE TICKET PIN at 17:3x BST: at the adversary lane's final rows one coexistence verdict moves on a number two lanes price 5x apart: the N2 SRAM die's machine ticket, lane B and the chip model at USD 0.6 per MH/s (USD 0.25 to 0.4 of silicon plus the board), the adversary lane's complete machine at USD 2.94 (2.14 at the smaller ticket); the joules agree (2.3x to 3.3x per joule at the honest knee). At USD 0.6 the die fails conditions (a), (b), (c), (f) everywhere (a sunk USD 10 M fleet is 16 TH/s, 50 to 70 percent of the chain on landing, 100 percent of a flat chain by year 5); at USD 2.94 it passes (a) at 1.24x of the best GPU owner, (b) at 0.27 of the GPU entrant's hardware and (e), failing (c) (a third of the chain USD 9 M against USD 40 M a year at IGN 0.10) and (f): the hybrid's verdict, coexistence under private supply in a growing chain (16 / 14 / 8 percent of the chain, 13 to 16 GPU classes above water) and failure on flat or shrinking paths by year 5. The coordinator's ruling under the plan's evidence standard ("complete-board overhead"): the model's ticket is the complete-machine figure (USD 2.94), lane B's USD 0.6 row kept in the workbook labelled the silicon floor; the adversary lane asked for the one-line reconciliation of what its ticket includes by 18:30; the served form until then the range ("a sunk USD 10 M die fleet holds 16 to 70 percent of the chain on landing depending on whether its machine costs USD 3 or 0.6 per MH/s, and takes a flat or shrinking chain by year 5 at either"); the board's (c) tips to a fail at the final USD 4.84 ticket (six of seven), its coexistence rows unchanged (coexistence-model.md section 12b on class-v6-floor-sram 954db053, the rows in coexistence-workbook.md). THE IGNEUM 2.0 DEVNET IS BORN on the re-cut: block one f3dc319c83766310bbe7911252e6de6e357cdc9f280420ee8ce9dcc91ffaddc8 at DAA 0, mined by hub-1 at 17:14:21.531 BST on release-2.0.0-node 4cdcc488 (digest be5f406802cec1227a5ef50d42181ab42444f79af170775b22c85cb9a917273b, genesis 7c36b833, chain id 4465, every switch on from block zero, class v5 with byte 6 from genesis, enforced proving from block zero with the ids 0x2b1a81cb and 0x474678f3, base unit 10^18, the launch emission 31,688,087,810,000,000,000 base units a DAA second), accepted on build-1's seed at 17:17:40 with blocks two and three behind it; hub-1 311 blocks by 17:19:53; build-1's seed and hand on the chain with dn4-seed as a permanent peer, lp-4090-02 synced, lp-4090-01 up about 17:32; the first checkpoint lock when the 7,200-DAA window fills (about two hours at one block a second); c04674fe's chain of 16:59 dead with its datadirs. RULE 25 from main at 17:3x: the observer dropped every 2.0 block because the subsidy in wei (9,522,644,482,386,090,276) is past int64 (widened to numeric at 17:25): every wei-bearing column, field or JSON number is numeric, u128 or a decimal string, never i64 or a JavaScript Number; the sweep by 19:00 with owners named: the explorer indexer and API, the hub's hourly feed and the Discord webhook (the build-server lane), /api/live and the live page's JavaScript (the site lane), the relay's earnings feeds (the update-return lane), the app's earnings tab and the wallet's balances (the shipper, v2.0.0 if a Number sits in the path), the fleet tooling's tallies (the fleet lane). MASTER'S CRATE BROKEN since the testnet lane's landing 74254eb2 at 17:07 (lib.rs line 39 re-exports v5_class_at, v5_rung_reps, GENERATOR_VERSION_V5, V5_CLASS, defined only on class-v5's generator; the landing hand's proof: the untouched master 9ac9c195 fails cargo check on the box with that one error, independent of CA4's code); main's two orders: the fix is to land class-v5's generator onto master as its own gated commit by 18:30, not to delete the re-export (the class v5 object is the live network's object and master lagging it is the fault): the hash lane lands class-v6 c245d50b9 (the class v5 generator plus the window's OpenCL and Metal texts and one test fix; suite 136 passed on build-2 at 17:21, no counter-asic-4 merge in its history; the node lane's recommendation, the superset: master's igneum-pow becomes the D1 generator and the served kit and master read one fingerprint, a65e4c5ac0541095a01db9cbdc08e4cad8a07fe24efef3df736f41770acef6b1 as consensus/pow/build.rs computes it, the line already in the object's pow-freeze.txt and d1-freeze.txt), after the landing hand's ca4-code revert, with cargo check and the crate suite green on the box; the node lane lands it itself by 19:00 if the hash lane cannot; and a gate rule (RULE 24): any landing touching a .rs, Cargo.toml or build file runs cargo check and the crate suite on the box, documents-only landings excepted only when the diff is under docs/ and site/: the steward's tools/ci/rule24-crate-gate.sh (510740e0 on ci-rule24: every .rs, Cargo.toml, Cargo.lock, build.rs or .cargo/config in the diff mapped to its crate, cargo check then the crate suite on the box at gate priority; docs/ and site/ alone run nothing; merge-to-master.sh runs it against the merge base, the hook on a push of master or release-*; self-tested on a fixture repo), landing by 17:45. THE CA4 CODE REVERT (branch ca4-code-revert on master, one commit reverse-applying cbf5aa46's non-document diff, a clean three-way apply): igneum-pow/src accept.rs, emit.rs, generator.rs, lib.rs, verify.rs restored and mm8.rs removed; igneum-pow/tests ca4_trace.rs and v6_window_bits.rs removed, scratch.rs restored; proto-cuda/nvrtc cuda_api.h and worker.cpp restored, emu/list-race-stubs.cpp and emu/variant-test.cpp removed; proto-cuda/packs-ca4 (six packs, 72 files) removed; 85 files, 33,040 deletions; of the four direct counter-asic-4 merges on master (cbf5aa46 16:12, fc1f9b62 16:25, d6bee526 16:37, 6666e199 17:03) only cbf5aa46 carried anything outside docs/; the revert lands at the 17:35 default on its tree gate; the rule for the record: research landings are documents only, through the landing hand, never a direct merge; a lane that needs code on master lands it as its own gated commit named in the map. THE CUTS VERIFIED CLEAN by the steward (read, not argued): for every parent its matrices shipped (b891444f, a9e2df26, 7d82b71e and their 60x commits for 2.0.0; 89e83df2 and its 71e4786d, 01d2036b for class v6) cbf5aa46 is not an ancestor, none of its twelve paths exists in the tree, and igneum-pow/src is byte-identical across all seven (the class v5 freeze, fingerprint cbc5bd0a, rule 19 checking it at build time); the node forks (4cdcc488, c04674fe, 380cd4eb, 617cb441) carry no igneum-pow of their own and linked that tree; the D1 object on class-v6-node links the override copy from class-v6 (merge base with master f37f497b3, below 6666e1991). The window's OpenCL and Metal texts on class-v6 at c245d50b9 (17:22 BST; one schedule, one init, one full-chain mix line and one fold from shared helpers in the three dialects; the stub gone); hl-v6-all re-exported with them (sha256 22c64fa5a753b38206442fa42136956f10378e76c2d289f0e38d8c28c69976d4, 91,013 bytes; the same id; kernel.cl 93,248 bytes, program.metal 81,201; the stub pack kept as hl-v6-all-stub.tgz); the second kit zip packs-class-v6-20261008T162324Z.zip sha256 098e64c3e0dc1dc727c4ded34d16a31d1ae2802b76f9c09c06b2bea9720fa108 (891,160 bytes; class-v6-kits a9ea072d): THE ALL PACK READS 59e6708e46f1e87c ON FOUR PLATFORMS (the CPU verifier, CUDA on the fleet's 4090, Metal and Apple OpenCL on the M5 Max at 17:24, 12.6 and 8.9 MH/s), the partner 5a6ad122a71a888f on three; both known-failed pairs distinct on every platform read; the two remaining platforms per pack AMD (PC 1's RX 7600, stalled until the desk) and Intel (PC 2's Arc, about 18:30); the page's row at class-v5 7f4e1039; the 23:00 line six of six if the PCs answer, else four of six on the all pack with the two PC reads the morning's. The hot-set reading confirmed by the census lane: the bit read per site inside the window; the F8 verdict per item over the whole dataset against the window-model null; the flat-control ratio 1.1 to 1.7x on every pack, the adversary's number; the "layer 8 off" D2 experiment stands. The hash lane's clock correction: the stub all pack landed at 17:03, the merge line at 17:02 (its "18:04" and "17:4x" copied the box's CEST). THE DIE TICKET RECONCILED (the adversary lane's section 15 at d3ad15493; floor lane 3's 12c at 7b894eaf; the research lane's commit after 346c24c0): the gap was two machines, not two prices: lane B's USD 0.6 per MH/s is the 2 GiB die at zero shadow (2,100 MH/s at 300 W, no shadow core); the 2.94 the same die carrying the class v4 shadow on the placed core (13x the die's energy per hash) held at 270 W, 383 MH/s; the adversary raises the power budget until the power train and the core silicon bind: on the placed core 852 / 1,420 / 2,130 MH/s at 600 W / 1 kW / 1.5 kW, USD 1.63 / 1.20 / 0.98 per MH/s, with a pipelined core and an organic package 1.07 / 0.73 / 0.56 (the die USD 500, 400 to 600, claimed; the core silicon USD 0.11 to 0.55 per MH/s; the package USD 60 to 200; the board USD 150 plus USD 0.15 per W of PSU and cooling; the host USD 15); RECONCILED at about USD 1.0 per MH/s (0.5 to 1.6) at 1 to 1.5 kW, the joules unchanged (2.3x node-for-node, 3.1x a node ahead); a maker's first batch of 1,000 dies pays the project (1 to 2 TH/s several times the chain: USD 50 to 250 per MH/s of NRE) plus first-yield losses. Floor lane 3's re-run at it: THE DIE FAILS (a) at 2.06x of the best GPU owner, (b) at 0.09 of the GPU entrant's hardware, (c) by 12.6x at IGN 0.10, and (f), at the centre and both ends, passing only (d), (e) and (g); the 12b pass of (a) and (b) was the 300 W artefact; a sunk USD 10 M fleet (10 TH/s, 6 to 20) holds 42 percent of a growing chain and 62 of a flat one on landing (27 to 93 across the band) and 100 percent of every flat or shrinking chain by year 3 to 5; the one coexistence-shaped cell private supply in a growing chain at 24 percent by year 5 with 16 classes above water, the conditions still failing; the die's economics are project economics (NRE USD 47 to 352 per MH/s against USD 1 of unit cost; p* 0.50 / 1.24 / 2.48 at a third for C_dev 100 / 250 / 500 M); the board (six of seven at USD 4.84) and the hybrid (coexistence only in a growing chain at cheap electricity) unchanged; the site lane has the die sentence's final served form. The finality lane at 17:25: the D5 partition row complete, both build-4 runs in (cores released 16:16 and 17:20): branch finality-boundary 7d129358e with docs/spec/finality-guarantees.md (rule v4: the anchored table plus the majority-continuity recovery, safety and liveness with arguments, what is not guaranteed, seeds during a pause, the four words), the pointers in 03-finality.md, O-3.20 and the O-4.3 close, sim/finality_v2.py (rule v4, scenario N), the "Rule v4" section of sim/results_v2.md, and in the plan under D5 the partition row as the chain's behaviour, the six-scenario table mapped to the evidence with gaps and clocks, the bring-forward and seed pipeline pins, the user-facing rule; the rows: v3 known-failed reproduced (sim and real nodes), v4 pause 0 conflicts everywhere, v4 recovery 0 conflicts without an equivocator mining on both sides, the bound measured (2,800 to 2,889 conflicts at day 30.00 with one), silence, departure, bought and stolen keys, the heal; the word to land on the box mirror's master after the revert; the founder's one-switch choice (recovery as written, recommended, or pause only) open in section 6.5, the default at 20:00 the document as it stands; the node lane's 2.0.1 queue takes rule v4 by 22:00 (frozen_table without its time drop, continuity_met behind finality_v4_activation_daa, never on every network, both variants behind the one switch). The enforced-proving lane's fast-time crossing PASS at 17:22 BST on build-2 (local nodes, floor DAA 240): below the floor H1 paid the attacker's forged record (the finding observed); at the floor nothing paid, nothing of the attacker's carried, four new REFUSED verdicts on each honest node (0.000 to 0.003 s each from the relay-time cache); the attacker's trusting pool carried five of the seven shapes, its own unmodified pool refused the other two (wrong network id, altered payout); the amendment on enforced-proving 896ef93ab in the gate; row 6's served label moves from PENDING to team-tested for what the native-veto test holds, the proof-side part PENDING until P22's stage 3, on master by 17:50; the shard guest's mirror of the 90/10 split: the enforced-proving lane's, on proving-payment-guest, green by 10:00 tomorrow, the re-pinned ELF and program id in elf/manifest.json by 12:00 on a build box; proving_payment_activation_daa at never until then. The site lane's wipe on master at 9b432c97 (17:22 BST), the follow-up (the final chip sentence, the first block at 17:14 with the badge live, the labels, the tip-share rows) by 18:00. The node lane's 2.0.1 queue on release-2.0.0-node: the manifest block and igneum_getManifest by 20:30; rule v4 by 22:00; the four-state transaction RPC with the pause word by 23:00; the five-together integration harness as the fast-time lane's case by the morning's first cut; the D1 object by 23:30 after the revert and the generator landing. The mixed-fp32 document on master at 690b7c70 (17:21). The update-return lane's PC 1 reading: stalled since the 15:50 restart (the restart kind's relaunch race lost twice on 0.3.20); the desk brings it back; the restart-kind fix da212ee2 a v2.0.0 candidate. THE CA4 CODE REVERT ON MASTER at 17:2x BST: 4ee346303 (Merge ca4-code-revert 98976b31, the gate green); reported to main at 17:31 with the cuts' clean read and the rule. The finality lane's landing follows it (its merge running, MERGE_REMOTE=build, documents, sim and the plan only; section 9 of docs/spec/finality-guarantees.md "The four interface words" the site lane's link; the user-facing rule under D5 in the plan). The fifty-third landing on master at 17:37 BST (68b889ee2). The 2.0.0 pair's gates: every line green since 17:30 (build-2 at gate priority: igneum-exec 65, kaspa-consensus-core 180, kaspa-consensus 140, igneum-miner 30, kaspa-p2p-flows 38, kaspa-pow 19, 0 failed; build-1's devnet-4 canary on the pair, igneumd 60f45b65, printing digest be5f4068 on two empty nodes, the enforced-proving line with the two ids, eth_chainId 0x1171, the handshake); the fast-time SUMMARY PASS (cross-200-4cdcc488) at 17:29:58 BST (17:14:20 to 17:29:58 on build-1 under class v5, the freeze fingerprint on both binaries: rung 1 at 17:20:38, class v5 by signal at byte 6 from epoch 8 at 17:22:33, 12 of 12 ids equal to the freeze CLI's, the stale node 140 of 140 refused, the restart step resynced in 9 s with the catch-up done after 5 s, four sinks equal at 853, 0 PoW rejections and 0 submit timeouts); the mixed-version refusal between the two devnet-4 objects read on the live chain (build-1's seed refused the c04674fe light reader "local be5f4068 remote 08aae61c" at 17:18:33; hub-1 refused the old seed three times 17:13 to 17:15); the canary gains a devnet-4 mixed-version node for the next cut; the shipper's 17:50 fleet minute and the apps' entries ride 4cdcc488's pair (/srv/artefacts/200-4cdcc488/node-lane: igneumd 60f45b653bbb8ab0, igneum-miner c19913b5ea380054). The class v6 clean rerun SUMMARY PASS (cross-v6-617cb441-3) at 17:30:44 BST (every check green incl. the cold restart on 4 of 4 after 660 s; the known-failed shape FAILED as it must; v5-fasttime 92bf6a7f); the missing case: the dataset schedule's size step, unreadable until the v6 generator pairs. RULE 24 ON MASTER at 17:34 BST as 7f8177cf (on build-2 and build-4): the hash lane's c245d50b9 landing its first real crate-touching run. The 2.0.1 manifest item in ahead of 20:30: release-2.0.0-node d5981514 (4cdcc488 plus one commit): the node prints one "Manifest: {...}" line after its start lines and serves the same bytes on igneum_getManifest (the network id, consensus digest and genesis; the version string and source commit; the pow engine with the igneum-pow fingerprint and freeze status; the object byte and the mining class at genesis; the dataset parameters; the finality rule with its activation and window parameters; the verifier block with the shard and aggregator ids, the proof rule's activation DAA, the prover version, inConsensus; every switch by name with its activation DAA or null; the fee schedule; the blockrate; the listen addresses; the D1 baseline line empty until the class v6 line's d1-freeze.txt rides the 2.0 line); the test the_manifest_printed_and_served_are_the_same_bytes; 4cdcc488 stays the live pair until the shipper names 2.0.1's cut; the steward's matrix on d5981514 behind. Rule v4 into release-2.0.0-node from section 6.2 at 7d129358e: the anchored table never expiring by time (Q5's expiry clause removed from frozen_table, the two-thirds-of-T_f test while daa(C_i) < daa(C_f) + 2,592,000), the majority-continuity recovery (past a full window with no certificate a lock needs Q3 both tests AND 2 x signed_f > total_f), C_f an ancestor of C_i, a recovery lock re-anchoring T_f with finality_reason "recovered", no anchored table before the first certificate; behind Params::finality_v4_activation_daa (never on every object, the digest arm once set, the 60x key) with finality_v4_recovery: bool (true = items 1 to 5, false = the pause-only variant), so the founder's 20:00 choice sets the flag on the object that first activates it; the known-failed tests first; the commit by 22:00; the finality lane asked for its two test names and the v4 harness line by 20:00. THE FINALITY LANE'S LANDING ec9ea053d at 17:35:32 BST (Merge finality-boundary 9926d6ca; the full gate green, 74 checks; "docs/, sim/ and docs/plans only; no .rs, Cargo or build file; igneum-pow and proto-cuda equal master's after the revert"): docs/spec/finality-guarantees.md (section 6 rule v4, section 8 the seed answer, section 9 "The four interface words"), the pointers, O-3.20 and O-4.3, sim/finality_v2.py and the "Rule v4" tables, the D5 block in the plan; the lane closed with its report (the node change, the v4 harness line after it, the paused-epoch program-id read, the two 8 October regressions as harness rows and the five-together harness owed to the node and fast-time lanes). RULE 25's sweep: the build-server lane: the observer FIXED (0f5ee875: subsidy_sompi and paid_sompi numeric(40,0), the insert cast ::numeric; the box copy widened 17:25:27, the dn4_ observer inserting since), the explorer indexer CLEAN (value_wei, balance_wei, gas_price, effective_gas_price text columns through hexBig; hexInt's Number(BigInt) only on block numbers, nonces, gas, status and timestamps), the explorer API CLEAN (strings; the 24 h sums in SQL cast ::text; the 80 percent share BigInt), the live API CLEAN (payout_wei text through BigInt, IGN to four places), the hourly feed and the Discord webhook CLEAN (Number() on counts, weights and the scaled IGN floats); a naming note: the observer's columns still called *_sompi while the 2.0 chain writes wei; the site lane: CLEAN on /api/live, /api/explorer, /api/supply, the live page, the explorer strip, /address, /tx, /proving (every money field through ignFromWei, a BigInt divide by 10^18) and /income; ONE FAULT of its own: /block formats the coinbase through ign(), a BigInt divide by 10^8, so on the 18-decimal chain it shows the coinbase 10^10 too large; the fix (the 18-decimal formatter) in the 20:00 sweep; its follow-up on master at 3511bbca (17:31). The site lane's scorecard plan: /scorecard as a checklist page (page 25's twelve gates, the evidence required, "do not substitute") with every row's status read from the facts page's rows and labels, no completion mark; the release evidence packet on every facts row; the four-deliverable table (D1 to D5 with the evidence file beside each) on the litepaper's roadmap section by its 19:00 default (a /mission page only on the founder's word). The class v5 lane's full gate on class-v6-kits a9ea072d RED on one check, 72 of 73 (the /swap status cell's live-render clip again, "block 749 of at least 26,972" at 768 to 1280 px; the DEX lane's cell; the kit tree touches no site/ file; one master merge and one full gate each close class-v5 and class-v6-kits once the revert and the /swap fix are on master). The research lane's D4 documents on master at 859b3daa (17:34; coexistence-model.md, operator-simulation.md, proving-payment.md, 10.0h to 10.0r, spec 05 and 06); the commits since on counter-asic-4 at 884e4313 for the 21:00 landing (the sensitivity workbook, the market-structure axis, the die's reconciliation and 12c, the final placed energies, the block-one emission figure, the FP32 rows); the adversary amendment 10b901a46 on master as e59bc3bda (17:28); twenty research landings through 859b3daa. Rule 25 on the miner app: FIXED, aa354ed5 on release-2.0.0 (in the Mac v2.0.0 entry live since 17:37:09 BST, in the Windows payload to come): every wei field the engine holds is u128 serialised as a decimal string (paid_wei, segment_paid_wei, earned_all_wei, the window rows, balance_wei from the hex read); the window turned three into a JavaScript Number for the IGN figure (the proving paid line, the segment paid line, the wallet balance), the fault; the IGN figure now cut from the string (whole units and four decimals), no wei value in a Number anywhere; the earnings card's figures already Rust u128 to IGN; the fleet and relay paths report on their own; the block-one emission 3.168808781 IGN exact to main. MAC v2.0.0 LIVE at 17:37:09 BST. BUILD-3'S SILENCE EXPLAINED from the founder's inbox at 17:4x BST: Hetzner's switch fault hel1-dc12-sw_99, the outage identified at 16:44 BST on AX102-1 #3084968 (62.238.91.43); no reset; the box returns when Hetzner fixes the switch; the lanes stay on build-2 and build-4 and nothing re-queues back until it answers for ten minutes. RunPod reports a server issue on pods 6ly14yf2b9b7lw and ks8dx9r4wdiugt: the k lane's fk-adv and fk-tm are not them and answer (the core8r64g placement alive in CTS timing repair; the 18:30 row stands); the adversary lane asked by 18:00; a pod not answering by 18:15 is destroyed by its pid-file rule. RULE 26 from main for the gate (the steward, by 19:00): two landings today (the og lane's 16b3e140, the release-manifest 6fc57381) reverted the reference-apps lane's files on master (receipt.html, then all of site/lc), restored by its own merges: a landing that touches a path another lane has landed since the branch point must be a merge with master's copy, never a replace; the merge tool refuses a landing whose diff deletes or reverts lines on any site/ or docs/ path changed on master after the branch's merge base unless the landing's message names the path as intentional. For the node lane's record: on the 2.0 devnet a plain transfer's receipt gasUsed reads 21,000 against a quote of 59,650, so the proving dimension is not in gasUsed for a transfer; /compatibility serves it as a measured difference. THE D1 GENERATOR ON MASTER at 17:45 BST: 9ba4e0e43 = the merge of class-v6 13885e16f (c245d50b9 plus the merge of master 4ee346303 after the revert plus one fix dropping master's second copy of DatasetSource's leaves methods); igneum-pow on master byte-identical to c245d50b9's tree, so the class-v6-freeze fingerprint a65e4c5ac0541095a01db9cbdc08e4cad8a07fe24efef3df736f41770acef6b1 stands and master reads it; before the merge the build-2 suite on 13885e16f 136 passed, 0 failed, 8 ignored, the pre-push gate green on the branch and the merge; the conflicts resolved on the branch: igneum-pow memhard.rs, main.rs and tests/packs.rs kept class-v6's text (class v5's mixer-draw rule in the agreed AP-F4-1 form, cost 205 with w32, where master carried the first form, NAF sum 163; the ds55 and reg64 arms of epoch_of; the window tests), site/litepaper.html master's, docs/ledger-public.md and site/ledger.html regenerated from the merged fud-ledger-2.0.md; rule 24's crate gate ran on it as the first real diff; the mirrors build-2 and build-4 took it, build-3 down. The node lane's D1 close: master at 07e5fa680 with 9ba4e0e43 below; git diff --stat c245d50b9 master -- igneum-pow empty; proto-cuda on master the post-revert tree (98 files, 25,242 lines removed against 6666e1991); the D1 entry names the generator at class-v6 c245d50b9 = master 9ba4e0e43's igneum-pow, fingerprint a65e4c5a, no counter-asic-4 code path in the object; the parent-side landing (spec 01, the D1 section) cuts off 07e5fa680 by 23:30. RULE V4 ON release-2.0.0-node at bee41b5e (both mirrors, 17:45 BST, the 22:00 clock met four hours early): frozen_table never expiring by time, FinalityManager::anchored_test at the three sites (two thirds inside the window; past it strictly more than half with the recovery, nothing without), the recovery lock logged and reported "recovered" for one window and re-anchoring as the next lock, Params::finality_v4_activation_daa (never on every compiled object) and finality_v4_recovery (compiled true, the recommendation; the founder's choice by 20:00 sets the object that activates, default recovery), both in the digest once the floor is set, the manifest's switches carrying both, the 60x file's two keys (parent d9e15a2ae); the finality lane's two tests green with the known-failed line first (kaspa-consensus 142, consensus-core 180): rule_v4_the_anchored_table_never_expires_by_time (the M3 shape; A alone never locks past the window under the pause; a hand-built A-only certificate refused; B's return locks at once) and rule_v4_the_majority_continuity_recovery_locks_after_a_full_window_and_re_anchors (A at 60 percent locks at the first index a window past C_f, stamped recovered, the table re-anchoring; exactly half fails and 51 of 100 passes; an off-chain recovery certificate refused; a key under dust at C_i signs nothing); the four harness lines (split50 v3 known-failed, v4 pause, v4 recovery; split70 past the expiry where the recovery fires once; the same v3.mjs command with SPLIT=420 and the override JSON carrying finality_v3_activation_daa 0, finality_v4_activation_daa 0 and finality_v4_recovery false or true) under the lease pool on build-2 the minute bee41b5e's pair builds; the simulator has no --rule flag (scenario N runs rule_v3, rule_v4 and rule_v4r itself). The shard guest's mirror of the D4 split ahead of its clock: proving-payment-guest 6dbd5d2f8 (off master f29dae620), green on build-2 at 17:44 and 17:46 (fee_switch_tests 5 passed with the known-failed test the_proving_payment_flag_moves_90_percent_of_the_charge_to_the_pool; the core and host suites 8 and 10 passed): FixtureEnv::proving_payment_to_pool (serde default false), the split at both charge sites of core/src/executor.rs with the node's arithmetic, the exporter reading the node's segment JSON (provingPaymentToPool, from the receipts; proving-payment 930b6322 on the fork, igneum-exec 67 passed at 17:38); not done: the ELF, verifying key and program id re-pin (pin-guests.sh on a build box with the Succinct toolchain, by 12:00 tomorrow; the re-pin on build-1 running at 17:5x with a pid-file kill at 18:40 if it overruns); the rule stands: proving_payment_activation_daa at never on every object until the new id is pinned. The served 2.0 ledger's D5 row on master at 17:46 as 07e5fa680 (proofs as a condition of payment: fixed in the node behind verifier_in_consensus, team-tested, awaiting the live read on igneum-devnet-4, the "was" line kept); master's enforced-proving landings today 5423b3277, a6d3ead1d, 1beab15ed, e8d8067e, 07e5fa680. Rule 25 on the relay: CLEAN (every Number() in relay/lib/parse.mjs and relay/api/console.mjs on a count or an id; the relay's tables stamps, text and jsonb; the relay never reads a subsidy, balance, reward or payout). PC 1 BACK: the engine at 17:23 BST, the 0.3.26 engine at 17:26 after the queued update-install (run win-ae432dc7-20261008-162603, installed 0.3.26); the signed-jobs queue fetched again (the read-width job took first, then the kit fetch; the queue not strictly file order); the relay agent zip for PC 1 live at the tokened URL; the one-exe-per-PC bake to the shipper by 18:10. MAIN'S SESSION CRASHED AND RESTARTED at about 17:5x BST; the shipper lane stopped and resumed by main; the coordinator's roll call to every lane by 18:05, every lane alive bar the shipper, the list to main at 18:09. RULE 26 ON MASTER at 17:58 as d49d3f68 (tools/ci/rule26-no-revert.sh in merge-to-master.sh after rule 24: for every site/ or docs/ path master changed since the branch's merge base that the branch also touched, every line master added must be present in the branch's copy; a deleted path counts as every line lost; a commit message naming the path lets it through; self-tested on the fixture: a replace and a deletion refused, a merged branch, a disjoint path and a named path pass); bee41b5e's node-side suites five of five green on build-2 at 17:57. LANE D'S GENESIS-TABLE VERDICT at 18:00: PASS on the or-floored copy (add 13, xor 13, mul 4, mad 11, shfl 3, rotl 10, sub 9, mulhi 2, rotr 9, or 1) at both widths and on the exact table's F8 census: width 4, 2,497 eras: r = 0.329 per candidate (the band 0.62, the shipped draw 0.68), mean attempt 0.49, max 10, 0 past 31, 0 exhausted, (c''') refusing 15.6 percent of the candidates reaching the 2^20 pass, the accepted draw's minimum ratio p1 0.9960; width 1, 1,500 eras: r = 0.191, mean attempt 0.24, max 4, 0 exhausted, (c''') 1.0 percent; the index-bit read over 6 sigma in 40.5 percent of eras at width 4 (51.1 at width 1), over 300 sigma 9.3 (22.6): the bit-R mechanism unchanged by the table; attack-f8 at the exact table (or = 0) on 64 seeds at 2^20 on the Devnet 3 state: 0 hot sets, 0 over 1.2x (worst 1.103x), 12 of 64 on the bucket class; the table halves the draw's cost (the lossy share 6 of 75 cuts (a') from 76 to 58 percent of rejections), keeps the floors' costs at the width's level, adds no hot set; owed: the exact-table attempts rows at both widths (466 and 401 of 1,500 on build-3 at the outage, the build-2 fallback 70 minutes on a full pool; they differ from the or-floored copy by one point of or, 1.3 percent of instructions); section 6.9 landing by 18:10. THE CENSUS LANE'S FINAL SHEET at 17:55 (the lane closed): hl-v6-win PASS (A: accepted, min site ratio 0.99923, bucket +5.5 sigma, the base program's one stride-bit site at -448 sigma, no fold in this pack; B: 256 of 256, 0 exhausted, r 0.716, mean attempt 2.52, max 15, (c''') 1.66 percent, the window not entering the draw; C: the window's own address stream through the crate's interpreter under a tracing probe, 16 seeds at 2^22, all 32 sites of the interleaved schedule: the per-site distinct ratio 1.0026 to 1.0027, every site clear of 0.98 and 0.995, the item histogram's top-0.1-percent share 1.0645 to 1.5624x of a flat control against the control's 1.0738 to 1.5074x, paired by seed 0.968 to 1.036x: the layer-8 hot half the null and the window adding at most 3.6 percent to it); hl-v6-all PASS (A: accepted, min site ratio 0.99993, bucket +5.75 sigma, worst free bit 3.49 sigma, no site over 6 sigma; B: 256 of 256, 0 exhausted, r 0.117, mean attempt 0.13, max 2, (c''') 0.34 percent; C: per-site distinct ratio 1.0026 to 1.0027, the item share paired 1.004 to 1.035x of the foldrw control): the window changes nothing the rule or the F8 form sees at 2^22 on the closed form and carries the fold's and the table's rows unchanged; what it buys is the chip-side cost. THE FINAL SHEET: fold PASS, rw PASS, foldrw PASS, rw2 FAIL, win PASS, all PASS; owed on the window packs: the live-dataset F8 point at 2^24 (the attack-f8 mirror interprets eight registers; a two-window interpreter four to six hours) and the 64 x 2^24 point every pack owes; the record docs/analysis/class-v6/census-packs.md on class-v6-census-all 25098c1a2 (the six-pack sheet, the harness and its pinned digests, the exact commands, the four instrument faults found and fixed, the owed items) with the logs under docs/analysis/class-v6/logs/census-packs/, landing about 18:40; the harness branches for the freeze's digest: class-v6-census-fold 5b3486f0, class-v6-census-reg64 b29e690d2, class-v6-census-all 25098c1a2. THE D1 OP-MIX TABLE NAMED by the coordinator at 18:09: rw1 as exported in hl-v6-all (add 16, xor 14, mul 4, mad 12, shfl 4, rotl 11, sub 10, mulhi 2, rotr 10, or 0; sum 83, or never drawn), the k lane's optimiser split, the census PASS on rw, foldrw and all, lane D's acceptance PASS on the same mix in its or-floored and exact forms at both widths; lane D's renormalised sum-75 form differing by one shfl point, not a second table; the node and hash lanes told. THE READ-WIDTH LOCK ROWS on PC 1's 5090 (the read-width b job, closed green; PCIe gen 4 x16 since the eGPU swap, every row about 13 percent under the morning), the 1,300 lock: v5-genesis 132.7 MH/s at 314.8 W (2.37 µJ); rw-w4 (W = 4, the era class) 140.7 at 322.8 W (2.29 µJ); rw-w32 (W = 8 words) 119.1 at 303.7 W (2.55 µJ, +11 percent per hash); rw-w64 (W = 16) 67.7 at 277 W (4.09 µJ, +78 percent; 4 warps per block 64.5 at 269.5 W); the class v2 controls rw5-w4 133.9 at 221.3 W (1.65 µJ) and rw5-w64 48.7 at 206.2 W (4.24 µJ); unlocked: W = 4 141.3 at 471.9 W, W = 8 140.2 at 494.4 W (+5.6 percent per hash), W = 16 78.9 at 448.4 W (+70 percent); the w64 lane count 1 to 8 warps per block moving the rate under 3 percent; W = 8 and W = 16 stay out as regression controls, the lock widening the gap. THE 5.5 GiB ROWS on PC 1's 5090 (run-ca3-pc1-ds55-5090-20261008, closed 17:50; the pinned class v3 program at both sizes, the fingerprints PASS and equal to the rented card's): the 1,300 lock: 1 GiB 137.0 MH/s at 218.2 W (1.59 µJ); 5.5 GiB 116.5 at 212.1 W (1.82 µJ): +14.3 percent energy per hash, 15 percent less rate; unlocked: 1 GiB 140.7 at 316.3 W (2.25 µJ); 5.5 GiB 135.8 at 320.1 W (2.36 µJ): +4.8 percent: THE 5.5 GiB DATASET FAILS THE 10 PERCENT BUDGET ON THE 5090 AT THE KNEE while passing at stock. The research lane's 10.0u (the dataset schedule scored per step, in the 21:00 landing): the commodity burden at 5.5 GiB +14.3 percent at the Blackwell knee (over the budget), the 12 GB tier's loss of mine-and-prove co-residence, the 8 GB tier on 1.8 GB of headroom, Apple about -18 percent of rate; the adversary burden nothing on the pure DRAM board, 1.2x the hybrid's ticket (USD 250 to 690 of SRAM), about 1.5x to 1.7x the die's, no chip's joules moving; no coexistence verdict moves; the 5.5 GiB knee row sits 10 percent above the 8 GiB power-of-two row, so part of the cost is the non-power-of-two mapping's multiply in the dependent chain, which the lock exposes (the control: a 4 GiB power-of-two row beside a 5.5 row on the same card); change (3) revised to 4 GiB at genesis (+8 percent measured at the knee) with the 5.5 / 8.5 / 11.5 steps retired to the workbook as the costed alternative, later steps only when the chain's state outgrows them; the site's sentence sent; what would reverse it: a power-of-two-mapped 5.5 GiB control inside the budget at the knee. The coordinator's ask to main with its default: class_v6_dataset_steps is a consensus field, main's word by 20:00, the default 4 GiB at genesis with the ds55 mapping kept in the generator as the costed path; the node lane holds the field. THE 7600 OPENCL JOBS: the three (card-in, ds55, the class v6 kit) exited in 1 s on "no device matching 7600" (the RX 7600 reports as gfx1102; the scripts matched 7600, gfx1200 or gfx1201); fixed at a9f8c6fb8 and republished (run-ca3-pc1-amd-cardin-20261008T1649, run-ca3-pc1-ds55-7600-20261008T1649, run-ca3-pc1-v6all-7600-20261008-b); the 7600 knob grid failed on card_not_mining (the app has the 7600 enabled at hash 0.0, mining off under the Devnet 3 off order), its rows the morning's after the PC mines on the 2.0 devnet. "LAYER 8 OFF" assigned by the coordinator as a D2 experiment to the hash lane with the adversary lane on the chip side, clock 12:00 tomorrow (the 5090 and 4090 rows at stock and the knee against the pinned pack, the chip-side d2b.py rerun at hit 0.50, the acceptance on the draw with the layer removed through lane D's harness; the pass rule the one acceptance rule); tonight's object unchanged. THE GUEST RE-PIN done tonight ahead of the 12:00 clock: proving-payment-guest afd952e89, re-pinned on build-1 at 17:49 with the build-server lane's SP1 6.8.1 toolchain under lease pool 16 at nice 19, the host's pinned tests 10 passed; the new shard program id 0x282dcfce483565a358268a6228b32beb1c48f4ee58095950364f9e5e6f5122b4, the aggregator id 0x3fd721e8482357780fd55904101cbdc316a5a7ec07c0dac47040696d57a328bd; the rule now a two-step: an object may set proving_payment_activation_daa only when it also pins the new shard id and every prover and verifier runs the node and host built from this elf/ (a node release, not a flag); nothing landed on master from the branch, the crate landing under rule 24 by 19:00 through the landing hand. The fleet lane at 17:5x: 99 of 99 boxes on digest be5f4068 at 17:54, 36 miners, 12 miner keys on hub-1's chain in the last ten minutes, hub-1 RSS 694 MB at 2,478 blocks; the two RunPod pods: 6ly14yf2b9b7lw was ln-node-07, a bring-up that never completed (no puller, no devnet-4 node), destroyed at 17:55 by its id (USD 0.13/h stopped); ks8dx9r4wdiugt is ln-node-10, a devnet-4 voter on the new digest, restarted by pid after a double start, kept; RunPod's flag not seen from inside. The update-return lane: the one-exe-per-PC bake delivered to the shipper at 17:50 (the baked PC 1 and PC 2 agent folders with their own secrets, the silent install entry on agent-install-20 072b2e71, relay tests 65 green; the PC 2 exe folder on the dl site with no-store); PC 1 on 0.3.26 since 17:26 with both channels up (the relay agent polling since 17:45, its logon task registered 17:48); PC 2 on 0.3.21 with its relay agent polling; restart-kind-20 da212ee2 merged into v2.0.0 at 297a2662 by the shipper at 17:16 (the DMG re-cut on it). The reference-apps lane: /compatibility with 20 of 20 rows PASSED on igneum-devnet-4 (real transactions, 17:31 to 17:34) on master since 17:42 (merge 8e947c3b, tip aa01681d) with the labels, the proof boundary and the data-availability paragraph on /light, /receipt and /oracle; deploying; the oracle redeployed on Sepolia for chain id 4465 at 17:53 (0xbb3450049926da3572e6b67cb94df312fe349e34); the devnet-4 re-run rows at the chain's first finality lock and first paid segment (finality not active at 17:53, tipDaa 2,554). The build-server lane: devnet-4 on build-1's own public node (rpc.devnet.igneum.network, /ws, /light, the faucet funded, the dn4_ observer and explorer indexer since 17:22); the site at 3511bbca keyed on igneum-devnet-4 (/api/live reading dn4_ since 17:47); the observer's numeric fix on master as ec9ea053; the Windows 2.0.0 payload on aa354ed5 at 18:05, PC 2's installer by 18:15. The fast-time lane: nothing in flight; the "five-together integration case" read as the 617cb441 run (the ladder's rung step, the v5 crossing, the v6 object's crossing at its floor, the restart step across the boundary and the cold restart on every node, plus the stale node, in one 60x network), its PASS at 17:30:44 the line unless a different five is named by 18:30. The site lane: one landing about 18:05 (b45bf6d4 on site-2.0-followup, gated on build-2) carrying the litepaper and positioning items, the labels and the ladder, the rule-25 /block fix, the four-words sweep with section 9 linked, the die sentence, the coinbase row, the Mac first-open notice, /scorecard as a checklist with the do-not-substitute column, the evidence packet on every facts row, the five deliverables on the roadmap. The fifty-fourth landing on master at 18:00 BST (c6959010c, after two races with master moving under it). THE FOUNDER'S TWO ORDERS at 18:2x BST ("you need to build 2.0 leaving no feature out and no straying"): (1) COMPLETENESS: docs/plans/igneum-2.0-register.md, one numbered row per checkbox in the plan (the pins, the addendum, the finish line's ten missed pins) with the plan page, the owner lane, the clock, the status (open, in flight, landed, passed with its evidence file) and the pass condition; every row owned by 19:30, none blank; landed through the landing hand; the coverage line to main at 19:30 and every two hours after and on every landing that closes a row; nothing finished while a row is open; (2) NO STRAYING: every lane brief names the register row it closes; work naming no row stops and names a row or drops; a mechanism outside the plan refused unless it closes a row and passes the one acceptance rule; served text follows the wording ladder and the never-published list. The register built by the coordinator at 18:3x on the Mac's clock from the plan's 103 checkboxes: 103 pins, 103 owned, open 35, in flight 34, landed 29, passed 5; on the mirror as ca3-coord-record c1aa45bde, the landing hand landing it (the plan file merged three-way over master so the D5 block is kept under rule 26; the plan file about 18:20, the register about 18:32); confirmed to main at 18:17 with the ten missed pins' owners and clocks: (1) the reference population and cost-per-accepted-unit table (the research lane, IN HAND: reference-population.md at 2db4fe34 on counter-asic-4 for the 21:00 landing, every cell labelled: the plan's population as block 1, the other eleven classes plus the H100 and A100 as block 2; the floor and stock energy, the rate, MSRP / street / used, resale, the two tests at 0.06 / 0.12 / 0.25 per kWh; the cheapest honest owner the 5070 Ti at its knee at 156 / 263 / 493 micro-USD per accepted MH/s-hour, the cheapest entrant the same card at MSRP at 412 / 519 / 749; the RX 7600 owner 2.6x and entrant 1.4x at street, the B580 4x and 1.5x; the H100, A100 and the Mac never enter as entrants; the GDDR7 machine at 3 years and 0.06 between the Blackwell entrant at MSRP and at street and above every owner; owed: the 7600's ADLX grid and dataset rows, the Arc's metered watts, the Ada and Ampere knees; the site serves by 12:00 tomorrow); (2) the formal memory model (the adversary lane, 12:00 tomorrow); (3) the cryptographic review of the template, nonce, work and result binding (the attack seat with the hash lane, docs/analysis/binding-review-2026-10.md by 15:00 tomorrow); (4) the disclosure prize live (the site lane, /prize by 12:00 tomorrow; the terms from the coordinator: a placed or measured adversary beating the served bracket under the one acceptance rule, or a reproduced shortcut on the served harness; no confirmations, no synthesis-only rows, nothing outside the budget or on the excluded list; judged in-house with the finding served whatever the verdict; the amount the founder's line, served only when set); (5) the home-connection penalty (the fleet lane with PC 1 or PC 2 through the relay, a residential Vast box the stand-in until v2.0.0 is on a PC, 15:00 tomorrow); (6) published optimisations, compiler settings and tuning logic (the hash lane, docs/build/tuning.md by 15:00 tomorrow, served under /miner); (7) negative test six's proof side, P22 stage 3 (the enforced-proving lane, 18:00 tomorrow); (8) the proving benchmark with p50 and p99 per stage (the fleet lane, 15:00 tomorrow; the collector running against hub-1's devnet-4 node from block zero); (9) reproducible builds and the signing-key incident procedure (the shipper with the build-server lane, 15:00 tomorrow); (10) the maintenance plan and the committed-funding line (the founder's). THE 2.0.1 QUEUE COMPLETE on release-2.0.0-node at 18:02 BST: 9fc9f42a adds "state" to igneum_getTransactionStatus (absent, included, executed, proven, finalised: the highest reached; "proven" and "locked" computed, no longer hard-wired false) and "paused" with its cause whenever the executor is blocked, re-executing, vetoing a proven record or more than two blocks behind the sink; the finality lane's third test in (a recovery certificate off the certified chain refused, the re-anchor at the recovery lock, a key under dust absent from the bitmap); igneum-exec 67, kaspa-consensus 143; no params, object or digest change; the manifest d5981514, rule v4 bee41b5e, the four states 9fc9f42a: the shipper names 2.0.1's paired cut; the rule v4 harness on bee41b5e's pair on build-2 since 17:58 (four lines of about 15 minutes, the tables into sim/results_v2.md by about 19:15). Lane D's amendment 494fb9810 on master at 18:02 (section 6.9 with the PASS verdict and the owed exact-table line). THE GUEST CRATE LANDING's red at 18:02 and its split: tools/ci/release-manifest-check.mjs keeps site/release-manifest.json's proof ids equal to proving/igneum-prove/elf/manifest.json, and the served page names the ids the running release embeds (v2.0.0: 0x2b1a81cb, 0x474678f3), so landing the re-pinned elf/ tonight would make the served manifest claim ids no running node carries; the split taken and ruled: proving-payment-guest-src 69ddd5112 (the guest sources with the D4 split behind the fixture flag, the exporter flag, the known-failed test; elf/ at the served release's pin, every fixture reproducing its roots with the flag off) runs rule 24's crate gate and lands on master on green, so 2.0.1 cuts from a master that compiles the new guest; the re-pinned elf/ (afd952e89: shard 0x282dcfce, aggregator 0x3fd721e8) rides the node 2.0.1 and miner v2.0.1 paired cut with the served manifest's move to the new ids in one commit by the node lane (or pin-guests.sh re-run on build-1 at cut time, 90 s); the landing hand's manifest edit never made. The explorer's public name ruled: "the Igneum 2.0 devnet" on every served page (never "Devnet 4", never "Devnet 3"), the explorer deriving it from the node's network name with a map, landing by 19:00; the live APIs read the dn4_ tables since 17:01 (network igneum-devnet-4, chain id 4465). The kit on PC 1's 5090 (unlocked, 250 x 2^24): hl-v6-foldrw 140.6 MH/s at 440 W (3.13 µJ), fingerprint 5a6ad122a71a888f; hl-v6-all 70.5 MH/s at 409.1 W (5.80 µJ), fingerprint 59e6708e46f1e87c; both equal the CPU, CUDA pod, Metal and Apple OpenCL readings: THE ALL PACK AT FIVE PLATFORMS, the partner at four; the window halves the hash rate at 7 percent less card power (a window hash twice the work: 128 statements, 32 loads), so per unit of work the card is level with the partner; the 7600's class v5 fingerprint 82b19cbde8557ea5 matched at 15.83 MH/s and v4 892b6d55a7ddcfcb at 15.75, the card quiet; the sizes rows republished (run-ca3-pc1-amd-cardin-20261008T1703, run-ca3-pc1-ds55-7600-20261008T1703). "Layer 8 off" taken by the hash lane with lane D (its fg harness by 12:00) and the adversary lane: a class flag on class-v6 tonight (the window draw forced to win = 0 and off = 0 on every site, the stream still consuming its two draws so the base program's instructions are unchanged, the id carrying it) and the 5090 and 4090 rows at stock and the knee. The research lane's mapping control for the genesis floor (the 4 GiB mask path, 2^30 minus 2^16 words on the multiply-shift, 5.5 GiB again, the 5090 at the lock) exporting on build-2, clock 20:15. The adversary lane's 32-lane 18-family core synthesis row at 18:02: 393,036 cells and six macros, 5.73 pJ per lane-op on the class v4 draw at ASAP7 (5.09 to 7.20), 4.01 at N5, 2.89 at N3, k 0.39 same-node / 0.28 a node ahead at the lock, 13 percent under the 8-lane full core; the bank's cost at 32 lanes 8 percent of energy and 50 percent of cells; with the measured 8-lane placement factor 1.42 about 5.7 pJ at N5 placed (k 0.55 same-node), so the machine ratios move up about a sixth: the GDDR7 board about 1.6x same-node (1.4 to 1.9), 2.0x a node ahead; the stored-half hybrid about 2.1x and 2.6x; per dollar unchanged; the same-node honest bracket 1.5x to 2.1x across the lane-count choice (document 0be29c224); adv-a destroyed at 18:01, adv-f the one rented host left (USD 0.20 an hour), its placed 32-lane row by 21:00 or the morning's. The site lane at 18:01: the tip 58355893 (b45bf6d4's items plus the dataset policy sentence and the section 9 link) in its gate on build-2 since 17:59; the finality wording for the new chain ("not yet active, first lock expected about 23:00 UK" on every page mentioning finality, the badge "Devnet live") on the landing after, by 18:30, since the strip and the explorer would read "paused" before the first lock, which the D5 rule forbids. The five-together case ruled: the record names the 617cb441 run with the gap stated ("proof queues and seed transitions not exercised in the same network as the crossing and the finality attack; owed to the next harness commit, the fast-time lane's morning item"). THE RE-PIN RULING put to main by 19:00 (the node lane's reading, the enforced-proving lane agreeing): the re-pinned guest elf cannot ride node 2.0.1 as a node-only cut: on igneum-devnet-4 verifier_in_consensus is on from block zero and a node pins the ids it embeds (the daemon exits 3 when the embedded keys differ from pinned ids; with devnet-4's ids empty it pins its own), so a 2.0.1 node on the new elf and the 4cdcc488 population would verify different statements, each refusing the other's records, payments and the body rule diverging on one chain: a consensus change needing the next devnet genesis or a key-succession field in the object (a digest move with a minute); the default on silence: node 2.0.1 node-only on 9fc9f42a with the live keys and no manifest change; the re-pinned guest (afd952e89), its ids, the served manifest's proving block and any object setting proving_payment_activation_daa wait for the next genesis or the succession field; the miner v2.0.1 pairs with 9fc9f42a's node; what moves no key lands tonight: proving-payment-guest-src 69ddd5112 (the sources with the split behind a fixture flag no fixture sets, elf/ byte-for-byte the served pin) under rule 24, and proving-payment 930b6322 on the fork while the floor is never; the landing hand's guest landing branch 7f15312aa dropped (a fresh worktree's vendor/ path fact recorded: proving/igneum-prove/core's path dependency igneum-evm-types at ../../vendor/igneum-node-exec is gitignored, so a crate landing from a fresh worktree needs the vendor copy). The register row for negative test six's proof side on enforced-proving 610f07c01, landing. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | +The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's `--variant ldcs` (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. THE FAST-TIME GATE ON THE RE-CUT: SUMMARY PASS (cross-0324-c9e385eb) at 22:49:32Z (23:49 BST) on the shipped 0.3.24 re-cut c9e385eb (igneumd 7a841b20..., igneum-miner 1e209b9e..., igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 22:36:25Z to 22:49:32Z, every check green: rung 1 by signal at epoch 6 (22:42:54Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (22:44:54Z, 4 of 4, 9,985 bps), 11 of 11 ids equal to the CPU verifier's, the stale node 86 of 86 refused with 0 accepted after the first refresh, the restart step across the boundary on a kept datadir resynced in 28.1 s with the catch-up done after 10 s and 0 of its own blocks during it, four sinks equal at 660, honest nodes 0 PoW rejections; record on v5-fasttime 76276be6, docs/design/class-v5-harness/fasttime/cross-0324-c9e385eb.json. The 0.3.24 move's gates left (the shipper's correction of this record): not F9 and F1's full 10^5 PASS (landing about 00:40 BST, too close to the 00:52 ceiling) but an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, max attempt 25), any non-zero holding the move, the full 10^5 the record line after; the minute named by the fleet on the last FETCHED plus ten once the build-server lane's c9e385eb pairs land. THE 61-ROW ERA READING (the v5 lane, box 2, 23:4x to 23:5x BST, docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log): 0 of 61 refused by the 0.995 floor at the table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), every class v5 draw on the class v4 attempt; era-drawn-28 (id 5e9eb01efbbf653e, attempt 6, R 15, the worst of adv-cache-2's census at 1.7451x) reads its biased site 15 at 0.9969, over the floor by 0.0019; era-drawn-25 (1.3571x, R 21) site 11 at 0.9994; the eight over 1.2x span 0.9965 to 0.9997 while the eight few-item hot sets sat 0.003 to 0.013 under the line. Main's sentence opens AP-F8-6 and section 14 verbatim with the two-instrument reading under it. THE CLASS V5 ATTEMPTS CENSUS for 1.4.7 (1,000 f8 seeds through the chain draw, v5-attempts-census-1000.log, the crypto lane's form): 3,219 candidates, 2,219 rejected, per-candidate rejection 0.6893 (sub-version 3: 0.68), accepted attempt mean 2.219, 0 exhaustions, P(256 consecutive) 4.4e-42; first failing part (a') 83.4 percent of rejections, (a) 10.7, (b) 3.0, (c'') 1.2, (c''') 1.0 (0.7 percent of candidates, one in 140: the floor's own share, 0.045 on the attempt mean), (c) 0.7 together, (c') none; the 5.14 percent of class v3 that 1.4.6 quotes is the audit lane's to replace. Both on class-v5 at 3b1dffd6 with main's sentence (891dd008), the mirror's master merged (e0471019: AP-F8-1's update and AP-F8-4 taken, the program-id recipe form with the state tag, no conflict), the design page's pre-public scrub (the founder's name six times, gone), M35's status word and the regenerated public ledger; the push waits on the full gate and the pinned-packs test on the merged tree (the proof that e5a4ac5978462156 and the other ids still derive under master's recipe form). THE 00:00 BST READINGS (the crypto lane; the verified roll-up of all nine lanes in section 13 of in-house-pass.md on crypto-engage, every branch tip read from the mirror and igneum-pow identical to 017e7037 on each). adv-accept, tip a7c49399 (about 5.5 box-hours, 0 pod-hours): 182,646 distinct accepted programs drawn (18 percent of the 10^6); eight pass every part of the frozen rule and flag the live hot-set test at 2^24 (X at 0.1 percent +0.102 to +0.221, 1.54x to 2.24x), all in the lowest 34 stand-in-ratio seeds against 0 in 20 random; each about 1 MB of items holding 0.26 to 0.41 percent of reads, 1.002x at the largest; the mechanism a near-saturated source at one site mapped by the era stride to one fixed item (plus two lesser shapes); the exemplar reads the same under the class v5 dataset. Against the class v5 floor: 8 of 8 refused; 3 mild residuals missed (adv-cache-2's rotation class, a load_index question not a floor question); 6 clean programs refused among the 9 deepest (the 2.4 percent). Q2 BOUND (54 programs plus 17 reads, 0 disagreements). Row 90: 0.6787 per candidate, (a') 83.3 percent, 0 exhaustions, P 8e-44. Partial named: 18 percent of seeds, 54 live rows, row 90 at half; a longer pass adds rows of the same shapes, not a different answer, unless a seed reads a hot set over 1 percent of reads, which 182,646 draws did not produce. THE PER-LOAD CLASS CLOSED (the research lane, for main; clock readings UTC): the per-load shadow fix held for distinctness and then met the value-level requirement from adv-cache-2, and the construction did not survive it; the per-load 16 x 27 class is dead as a chain class. 22:44 the attempt verdicts on four seeds (igneum-genesis 0 of 32 accepted); 22:47 the 64-seed census under the full rule (duplicate lanes at a load row plus the one-count of every index bit per site over the 64 units, 6-sigma band): 22 of 1,621 candidates accepted (1.4 percent), 42 of 64 seeds exhaust the chain's 32 attempts (an epoch without a program); the first failing test per candidate: biased index bit 775, duplicate lanes 643, the base rule 110, (b) 43, (a) 28; candidate 0 of the class carries index bit 0 set in 40 of 1,024 addresses (z 29.5); 22:52 the suite green (64 + 5 + 7 + 4 + 19 + 2 + 7); the acceptance rule with BiasedIndexBit for this class and the tests pushed as the record, the file's 20.2a closed. The structural reason: 27 passes of a 16-instruction map right before a load is an iterated small function and collapses or biases the load's address register before any base instruction re-randomises it; the class v4 shape has 64 base instructions and 16 loads between its block and every load. Both exports were accepted only because the rule did not model the placement; their PC 1 rows stay as an energy reading of the placement, labelled unsound. Rank 4 and the USD 200 M capex row rest on a construction not shown to exist (chip model 5.11's clause marked so in this landing); the sound form is one pass of a 432-instruction sub-block per load (a program segment, not an iterated map), a new class to draw, accept and measure, not tonight's. Replicated by a second instrument: the class v4 shape on this pre-amendment generator carries the adv-cache-2 product bit at address bit R exactly in 14 of 17 drawn eras (one-count 250 or 780 of 1,024, z 15 to 19), 0 duplicate pairs across the eras. What stands from the two prototypes: the tile block (bit-exact on the Metal reference, the AVX2 verifier at 0.047 us per tile, the Apple emulation cost 35 to 78 percent) awaiting its 5090 rows; the per-load placement closed. THE SPEC REWRITE ON MASTER (the site audit lane, 8b834634 at 23:56 BST; gate GREEN on 64e2a91b, 71 checks; the igneum-pow suite green on the box for that commit with derivation.rs and spec_readback.rs): spec 01 sections 1.4.3 and 1.4.6.1 to 1.4.6.6 rewritten to 017e7037 with the 20-row constants table (ACCEPT_TAG, the window-cap literal, MAX_SATURATED as the first refused count with the 163 message noted) and the 6-row pinned-ids table with Devnet 3's full genesis hex; the shadow block in 1.7; the ninth era draw in 1.13.1; tools/ci/spec-constants-check.mjs in the gate (known-failed first, every Constant | Value | Where table, pending rows skipped while absent); igneum-pow/tests/spec_readback.rs (ids derived through the crate, each class v4 row drawn to its attempt); ledger AP-F8-5 after AP-F8-4; the ledger-page fix (both heading forms, the pass as its own section, known-failed self-test in the gate; AP-F8-1, AP-F8-4 and AP-F8-5 render on /ledger); the fud-ledger's two prize clauses and "paid independent cryptanalysis" removed at the source so the regenerated page carries neither (commit 90424d5a, merge 64e2a91b). A HARDWARE FACT IN DISPUTE, for main: tonight's 5080 efficiency rows came from PC 1 jobs (run-ca3-pc1-v4-eff-5080-20261007-b and -c), the audit lane's record reads the RTX 5080 and the Arc B580 on PC 1, the hash lane's 22:09Z device list on PC 1 shows the 5090, the 9070 XT and the 4070 only, and main places the 5080 and the B580 on PC 2; identity-check.sh's "PC 2" substitution text names cards and is left card-free until the PC 2 job's own --list settles which cards sit where. THE IDENTITY CHECK'S PC 2 TEXT (the CI steward, 00:05 UK on 8 October): tools/ci/identity-check.sh rewrites "PC 2" card-free as "the second Windows rig" (commit 40f2be54, merge 0d2cf334, gate GREEN 71 checks, identity grep 0 hits over 306 export files and 52 served pages); line 69's PC 1 list untouched; the reason recorded in a bash comment above the perl call. THE 32,400 FLOOR LOST (the node lane, 00:0x UK on 8 October): dn3-g1's chain read DAA 25,126 at 23:52:03Z and 25,169 at 23:52:38Z, so the publish DAA passed 25,200 at about 23:53:09Z with no 0.3.24 move made (build-1's three Devnet 3 nodes last restarted about 21:31Z on the 0.3.23 move; the old seed holds 38 peers on ba75bf6f; no move minute was named). The next boundary is 36,000 (epoch 10), about 02:52Z on 8 October (03:52 BST) at 1.0 DAA/s, holding for a publish up to DAA 28,800 (about 00:53Z, 01:53 BST). Two routes put to the shipper and main: the same re-cut script on release-0.3.24-node (program_class_v5_activation_daa 36,000, nothing else, the same gate set, about 20 minutes to the pin line), or the fleet names its minute first and the floor is cut from it in one go (publish DAA plus 7,200 to the next 3,600) instead of a fourth chase; the pin c9e385eb stands meanwhile. THE FLOOR RE-CUT FROM A NAMED MINUTE (the shipper, 00:1x BST on 8 October, under the slip rule main set with the object commit): the floor re-cuts once more to 39,600 (epoch 11, about 04:52 BST) from a move minute the shipper named: 02:00 BST on 8 October, or the fleet's last FETCHED plus ten if later but before 02:53 BST (DAA 32,400, the ceiling); the node lane's pin line in about 20 minutes with the new Devnet 3 digest; the F9/F1 interim read at 01:55 BST; the publish minute equals the move minute (the apps' entries at or after it); the fast-time SUMMARY PASS reruns on the new pin as part of its gate set; the cause of the lost floor named: the c9e385eb pairs and the two PC jobs unreported for forty minutes, so the fleet had nothing to point its move file at. "slot closed" on PC 1 still waits on the host job's exit. THE 0.3.24 NODE PIN AT 39,600 (the node lane): dfbd1e10 on release-0.3.24-node (both mirrors, 23:54:13Z) = c9e385eb with program_class_v5_activation_daa 39,600 (epoch 11), nothing else; pairing igneum-pow 1c420786; every gate green at 00:01:52Z (build 23:56Z rc 0 at gate priority, igneumd 4870ccf2..., igneum-miner aa8c2978..., /srv/artefacts/0324-dfbd1e10/node-lane; pow 19, consensus 134, p2p-flows 38, exec 47, core 175, miner 28); the Devnet 3 canary set (23:56:33Z to 23:58:13Z): digest b1ba78229b069dc395fa666638a686a66615eb760d251798adfa6a654a415f82 on igneum-devnet-3 from ba75bf6f, object version 6 stamped (block version 1538), the override file refused, shutdown 2,015 ms, two empty nodes handshaking on it, the shared-devnet dialler rejected, a 2720d8d2 node refused on the digest both ways; the testnet canary b2e856ed unchanged (byte 7, a live old-object testnet node refused). The cut's read: dn3-g1 at DAA 25,169 at 23:52:38Z (1.0 DAA/s), the publish DAA at the named minute 01:00Z about 29,211, plus 7,200 = 36,411, the boundary 39,600 about 03:53:09Z on 8 October (04:53 BST), holding for a publish up to DAA 32,400 (about 01:53:09Z, 02:53 BST). The one gate running: the fast-time pair on dfbd1e10 (about 13 minutes from its start). c9e385eb is void as a pin; the F9/F1 interim read armed at 00:55Z. THE TWO PC QUEUES AT 01:03 BST (the hash lane): PC 1's "slot closed" has not come (the shipper's 0.3.24 host job, the build-server lane's, took the slot at 22:13Z for an expected two to three minutes; nothing reported in 110 minutes); nothing of the hash lane's has run on PC 1 since 22:09:25Z; the v5 kit fetch and the 9070 XT v5 bench are prepared and unpublished (tools/ca3-v4-amend/pc1-publish-20261007.sh, steps v5-kit and v5-amd), so no 9070 XT class v5 fingerprint exists yet; the lock protocol holds unless main says the lock-free pair goes ahead of the silent host job. PC 2's "clear" has not come either (the 0.3.23 take 3 smoke and the scheduler proof unreported by either lane); the Intel job is prepared and unpublished. THE HARDWARE FACT, read from tonight's PC 1 lines: nvidia-smi on PC 1 lists GPU 0 RTX 5090 (bus 01:00.0) and GPU 1 RTX 5080 (bus 0D:00.0); its OpenCL list carries the RX 9070 XT (gfx1201) and the integrated gfx1036 and no Intel platform; so the 5080 is on PC 1 (the audit lane's record right, the 22:09Z device-list summary short by one card) and the Arc B580 is not, which agrees with main's word that it is PC 2's eGPU; the kits row, the bench notes and identity-check's card-free PC 2 text stand on that. The locked PC 1 jobs stay parked (the 5080 full grid, the third 5090 pass, SM-sparse, the microbench and packs knee states, the two Ember tunes, the hot-table ldcs rows); the lock-free CA4 rows queue after the v5 bench on the same "slot closed". THE 00:00 BST READINGS, THE OTHER THREE (read by the crypto lane from each branch's report on the mirror at 01:03 BST; the roll-up section 13 of in-house-pass.md at crypto-engage c84ba51b with adv-accept's reading at 1b4e07ff; all nine branch tips read back from the mirror and igneum-pow IDENTICAL to 017e7037 on every one: adv-mixer d2ba3134, adv-mixer-2 2a632579, adv-mixer-3 4ebe2455, adv-cache 555c3e42, adv-cache-2 9384ee09, adv-cache-3 9452c0bf, adv-accept a7c49399, adv-accept-2 92168536, adv-accept-3 0c150e3c). adv-accept-3 (exhaustion or steering of the draw), tip 0c150e3c, every sweep ended 23:05 BST, about 3.3 box-hours, 0 pod-hours: Q1 exhaustion BOUND (per attempt accept 0.323, reject 0.677 ((a') 0.568, (a) 0.079, (b) 0.022, dynamic parts about 0.009), geometric histogram, P(exhaust) 0.677^256 = 4.6e-44, 0 of 16,337 seeds at the cap); Q1b the last resort FINDING (correctness; the mirror fired at cap 256 byte-identically; of 3,000 last-resort programs the real rule rejects 271, 9.0 percent: 251 by (a), 14 by (b), 6 by (c) distinct sum; handed out unchecked; unreachable; closed in class v5 by 8ca66afa, AP-F8-3); Q2 steering BOUND (45 of 48 planted rows fired, the real rule rejects every effective plant by (a'); 975 seeds at the first part, min ratio 0.998, 18 of 18 chain re-draws equal); Q2b the price of a seed property at 1 in 10^6 tries is a shadow block with 38 multiplies of 256 against a mean 74, about 2 to 3 percent of the f = 1 chip's energy per hash, the load critical path worth nothing at the memory activate ceiling; Q2c the 256-unit ratio is noise as a selector; Q3 program id FINDING (documentation: the "sub/" || 3_le16 suffix omitted from program.json and spec 1.4.6; a text-derived implementation computes 30956569d8f3d8d7 for Devnet 3 against the pack's fce15bf61030be57; 0 collisions over 10^7 pairs; fixed as AP-F8-4 at da2fc101); Q4 determinism DONE (the (c'') f64 compare never disagrees with the integer rule on any of the 2^20 + 1 values, margins 0.32 to 0.44 counts; a second interpretation agrees on 5,748 of 5,748 verdicts of 1,792 seeds); Q5 the era lever BOUND (400 eras, no stride under NAF weight 7, all 31 rotations, 354 distinct interleaves; epoch 0's accepted attempt is 3 under every era, so the era moves the address map, not the program). Partial named: the steering sweep at 975 of a planned 10^5 seeds (about 8 box-hours more at 32 cores). adv-cache-2 (the hot-set attack), tip 9384ee09 at 23:52 BST, about 2.2 box-hours by wall times threads over 96 (the boxes at load 400 to 600 for the first two hours), 0 pod-hours; two shards still queued at 00:00 (lines-2e30-s2c, warps-devnet-2e25-v2), named partial: Q1 the line index PASS (pooled 16 days; segments max +4.84 sigma against a control's +4.24, lines +5.61 against +5.35, chi2/dof 0.99937, top 0.1 and 1 percent of lines 1.0003x and 1.0002x of control; the 2^35 + 3 x 2^33 census all PASS; 0 mirror mismatches); Q2a the real programs PASS on the hot-set test (devnet at 2^26 1.0002x; Devnet 3 at 2^26 items 1.0071x, lines 1.0000x) with the FINDING at Devnet 3 site 0; Q2b all 64 programs done, every one clear on the hot-set test (items 0.9993x to 1.0075x of the windowed control) but the site class as recorded above (13 of 27 drawn-era over 1.04x, 8 over 1.2x, worst 1.7451x; the v5 floor refuses 0 of 61; AP-F8-6); Q3(1) steering by t PASS (worst cell 3.95 sigma in 2 x 2,112 cells); Q3(2) the weak-day scan PASS over 16,384 days (2^30 derivations in 707 s; worst per-day max bucket +8.13 sigma against the control's +7.78; the plant fired at +1,090); Q3(3) the window layer: the exact distribution matches the 4,096-program census to four digits (top quarter mean 0.3382, top half 0.5811), with a FINDING against the chip model's table: the f = 0.25 and f = 0.5 partial-store rows overstate the recompute share by up to 1.8x at f = 0.5, the full-store (f = 1) verdict unchanged (a correction owed in chip-model-v3's partial-store rows; no served number rests on f under 1); Q4 the prices: the only measured excess over f is the window layer's and the line reference multiplicity (a hottest-lines half store hits 57.8 percent instead of 50 at a higher miss cost than the stride). adv-mixer-3 (the statistical distinguisher and round margin), tip 4ebe2455 at 00:41 BST, still RUNNING at 01:03 (Q3 and Q4 at k = 8 on day 20729, queue 07 in the pool, the SAT ladder at k = 3 timed out; the total box-hours the lane's to give): Q1 the exhaustive round-0 line-index census over all 2^32 t PASS to k = 8 on days 20729 and 20733 and at k = 2, 3, 4, 8 on 20730 (z within 1.5); Q2 single-bit avalanche FINDING at k = 1 (354 and 266 holes, 130,000 cells beyond 6 sigma, the known one-application diffusion), PASS from k = 2 at 2^24 (0 holes, worst z under 5.3 through k = 8); Q2b the t-bit avalanche the same shape; Q3 differential multiplicity over 576 low-weight differences FINDING at k = 1 (695 and 537 deterministic output bits), PASS k = 2 through 7, k = 8 running; Q4 and Q4b linear correlations PASS from k = 1 (worst c 0.00046 to 0.00062, z under 5.1); Q5 rotational-XOR PASS from k = 1; Q6 SAT: k = 1 SATISFIABLE in 137 s (t = 0x49880000 verified through the real code), k = 2 and 3 TIMEOUT at the one-hour cap. The round margin as it stands: no statistic survives 2 of the 8 applications between reads; a chip gets nothing from the k = 1 findings because every read sits behind 8. The lanes' own lines go into section 13.1 as they arrive. THE LANES' OWN 00:00 LINES (adv-accept-3 and adv-mixer-3, 01:0x BST, in section 13.1 of in-house-pass.md): adv-accept-3's P(exhaust) refined to 1.0e-43 per epoch seed from 62,240 full-rule candidates plus 3.0e6 static candidates; Q2 steering BOUND over 19,975 full-rule and 1e6 static seeds, no property buying over about 1.03x at 1 in 1e6 tries; a second documentary FINDING: an implementation written from the spec text (not the code) at 017e7037's spec differs on 264 of 400 epoch programs, the same text-against-code gap as the id suffix (the audit lane's rewrite 8b834634 with spec_readback.rs is the fix; the proof that it closes this is a re-run of the text-derived implementation against the rewritten text, asked); a plant note: the floor-0.97 known-failed variant did not fire because the (c'') ratios are bimodal (accepted 0.989 to 0.999, rejected 0.814 to 0.966), replaced by a single-pass (a) variant that did; 3.3 box-hours, nothing running. adv-mixer-3: about 3.0 wall-hours of sweep plus 4 single-core CaDiCaL hours; the round margin stated as 6 of 8 applications between reads and 70 of 72 per item on every measured statistic, the k = 1 effects one mechanism (the lowest-set-bit trail through one application, dead once both addends carry a difference), nothing saving one application against 9,360 ops per item; still running at 4 cores on build-1 (2^27 and 2^28 avalanche rows, finish about 03:00 BST) and the day-20733 SAT ladder on build-2 (about 03:45 BST); not attempted: multi-bit linear masks and a MILP trail bound. adv-cache-2's own line still owed. ADV-CACHE-2'S OWN LINE (01:05 BST, tip 3f50d6c4; section 13 of in-house-pass.md now carries every lane's reading in its own words plus the verified roll-up): the drawn-era prevalence read on the SAME 32 base programs is 2 of 32 under the devnet era against 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), the mechanism carried by rotl(x times M, R) into the item index unless R is 29 or 30 (2 of 31 rotations), with a sub-class of warp-uniform sources once in 16,000 warps; the window layer's price restated: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the chip model's partial-store rows overstate the recompute share by up to 2.3x on these programs, the f = 1 verdict unchanged (the correction to chip-model-v3's partial-store rows is the coordinator's next commit); partial named (the drawn-era windows census of 4,096 and one line shard in the pool); the longer-pass line: the biased-site rate per era in closed form (the R in {29, 30} rate 2 in 31) and a 2^28 read of the worst site. Nothing of the pass stands between the pool and a higher-class job except two pre-emptable shards on box 2. THE SPEC-TEXT RE-DERIVATION ORDERED (01:06 BST): adv-accept-3 re-derives its 400 epoch programs from the rewritten spec text alone at master 8b834634 (1.4.3 to 1.4.6 grown from 79 to 198 lines with the constants and pinned-ids tables), lease pool 16 --min 8 class adv, row Q4c in its report; the expected reading 0 of 400, any non-zero naming the diverging sentence to the audit lane; the proof that AP-F8-5 closed the text-against-code gap. THE CHIP MODEL'S PARTIAL-STORE ROWS carry a second correction (section 5, 8 October 2026) from adv-cache-2's window-layer reading: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the uniform-store rows overstate the recompute share by up to 2.3x; the f = 1 row, the SRAM column and the full-store verdict unchanged, no served number on f under 1. THE CLASS V5 PACKS TEST ON THE MERGED TREE (the v5 lane, 01:0x UK): the job ran on box 2 the minute two adv-accept holders ended (65 cores; no lease fault, plain starvation before); 19 passed, 1 FAILED: v5_pack_is_the_v4_program_over_the_state_leaves (tests/packs.rs:977), the byte-for-byte compare of every pinned pack file with the crate's export. The ids are EQUAL (v4-genesis exports a217c7f698880830 as pinned; the state tag rides in master's recipe form unchanged); what differs is the program_id_derivation TEXT in program.json, which master's export (the hash lane's AP-F8-4 read-back form) now writes as "... || attempt_le32 || 'sub/' || sub_version_le16" for generator 4 while the pinned packs carry the pre-suffix wording. Disposition: the three pinned packs re-exported from the merged crate (text only; the ids, kernel texts, leaves and the fingerprint 82b19cbde8557ea5 must come out byte-identical, proved by the same test); the CLI rebuilding on build-1 from 51aa5bc4, the export from the box's IGSD1 streams, the packs test and the full suite on box 2 at 16 cores, then the push; readiness about 01:35 UK. The 0.3.24 kit zip (packs-ca3-v5-20261007T221001Z.zip) carries the old derivation text in its program.json files: a text field only, no id, kernel or fingerprint change, so the kit stands for 0.3.24 and the shipper is told; the re-exported packs go in the next kit. THE ONE 0.3.24 KIT, NAMED for the shipper (01:1x BST): packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 the pin pairs with; the fleet keeps placing it. The 23:11 zip packs-ca3-v5-20261007T221001Z.zip (sha256 4aaf9b9e..., /srv/artefacts/packs/ on build-1, from class-v5 7f58af97) carries the same packs, ids, kernels, leaves, fingerprint and derivation text and differs only in the merged kit host code and scripts beside the packs; it is the bench lanes' kit for the fingerprint jobs. The coordinator's earlier line naming 4aaf9b9e as the 0.3.24 kit was wrong and is corrected here. THE SPEC-TEXT READ-BACK RUNNING (adv-accept-3's Q4c, 01:11 BST on build-2, lease pool 16 --min 8 class adv): the same 400 epoch seeds re-derived from the spec text at master 8b834634 alone (1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7, 1.13.1; a fresh text interpretation), compared field for field with the chain draw; the count about 01:21. One sentence already named divergent before the count: 1.4.6 part (c) cites dataset_elem(idx, S[0], S[1]) "of verify.rs" without stating its six operations, so part (c) cannot be computed from the text alone and the derivation takes that one function from the crate; the audit lane is to state the closed form's six operations in the text or the constants table, else 1.4.6 stays code-dependent on that line. A NINTH LIVE HOT SET (adv-accept, 01:12 BST): seed 228763 (id 2c4be0f6dc44c423, stand-in 0.9820) at 2^24 (X at 0.1 percent +0.118, 1.82x the window model), its single hottest item 0xe2cc96 at 1,218,380 reads, 0.057 percent of ALL reads, the largest single item of the pass (40x 100767's), from a NON-saturated source r0 at site 9 (the sel register), saturated-source share 0.000: the third shape at scale, a value-level concentration neither (c') nor a saturation test can see by construction; its 2^20 ratio against the 0.995 floor lands in minutes and decides whether the floor's instrument reaches it (if missed, the exemplar for the next class's non-saturated case). 638990 reads 1.51x beyond the gate with one item at 0.027 percent (r0, no saturation), no hot set; 623492 clean. Tally: 9 hot sets in 37 tail seeds against 0 in 20 random, 269,250 programs drawn; the price unchanged at 1.002x (0.27 percent of reads on 1 MB; one item 64 bytes). The public sentence's "eight of eight" moves to "nine of nine" or gains the first miss when the ratio reads. THE FLOOR REACHES THE NON-SATURATED SHAPE (adv-accept gap-tail3, 01:13 BST): seed 228763 reads minimum site 9 at 0.9809 at the 2^20 sample, the lowest of the pass, REFUSED; 638990 site 2 at 0.9872, REFUSED; 623492 (clean live) site 0 at 0.9922, REFUSED, a seventh false refusal. Final tally over everything the lane read at 2^20: 9 of 9 live hot sets refused (0.9809 to 0.9919), both single-item programs refused, 7 clean-live programs refused and 1 passed among the 12 deepest 256-unit seeds, 3 mild residuals missed at about 1.0004x. The reading: the distinct-index ratio reads any few-item concentration whatever its source, saturated or not, and misses only the diffuse era-stride excess; the class v5 floor closes the hot-set class entire at the 2.4 percent clean-rejection cost; the next class's value-level test is for the diffuse class alone. The public sentence reads "nine of nine hot sets refused" from here (the v5 lane's follow-up cfce57ea rides its push; AP-F8-1 on master updates with the next record commit). THE FAST-TIME GATE ON dfbd1e10: SUMMARY PASS (cross-0324-dfbd1e10) at 00:12:57Z on 8 October (01:13 BST), the shipped re-cut's binaries (igneumd 4870ccf2..., igneum-miner aa8c2978..., igneum-pow 1c420786), build-1 under lease pool class v5, 23:58:56Z to 00:12:57Z, every check green: rung 1 by signal at epoch 6 (00:05:37Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (00:07:46Z, 4 of 4, 9,985 bps), 12 of 12 ids equal to the CPU verifier's, the stale node 95 of 95 refused, the restart step across the boundary on a kept datadir resynced in 36.2 s with the catch-up done after 11 s (4 IsInIBD refusals of its own miner during it, 0 of its blocks accepted), four sinks equal at 661, 0 PoW rejections on the honest nodes; record on v5-fasttime 0a09eb78, docs/design/class-v5-harness/fasttime/cross-0324-dfbd1e10.json. Every gate on the pin is green; the move waits on the pairs on the dl host, the last FETCHED plus ten, and the F9/F1 interim read. THE RE-EXPORT READ (the v5 lane, box 1 with the merged crate ac285733): the three pinned packs' only difference was program.json's program_id_derivation text (generator 4 now "|| 'sub/' || sub_version_le16", generator 5 the class recipe "igneum-program-rw/ ..."); ids, kernel texts, leaves.bin, vectors and the fingerprint 82b19cbde8557ea5 byte-identical; the pinned packs carry the merged text; the full gate and the full igneum-pow suite with the packs test and spec_readback running on that tree, the push and commit string about 01:45 UK; main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2 at class-v5 b5d6368d (nothing with eight of eight reached the mirror). AP-F8-1's two eight-of-eight lines on master move to nine in this record commit. THE MOVE'S SOURCE (the shipper's ruling at 01:05 BST, corrected to this record at 01:1x): the 02:00 BST move does not wait on the build-server lane's pairs; that lane is dark (nothing published since 23:05 BST, nothing answered since 00:17), so the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair at /srv/artefacts/0324-dfbd1e10/node-lane on build-1 (igneumd 4870ccf2, igneum-miner aa8c2978, the pair every gate ran on, native glibc 2.39 on every fleet box), the way dn3-g1 and g2 moved at 22:30; the fleet's puller fetches from build-1, not the dl host. The move waits on the fleet publishing the dfbd1e10 move file and naming the minute (asked 01:05) and the F9/F1 interim at 01:55. The hive and the Windows pairs are the dark lane's loss for tonight unless main gives the shipper the word to build them (asked 01:06); the Mac entry publishes at the minute regardless; if the fleet has not published the move file by 01:40 BST, main and the coordinator hear it with the clock. THE PC 1 LOCK VOID, THE V5 AMD BENCH PUBLISHED (the hash lane, 01:1x BST): the shipper's 0.3.24 host job was never published to the jobs file, so the slot was void (the shipper's "slot void" at 01:05 BST); the v5 kit fetch landed on both PCs at 00:12:06Z (919,273 bytes, sha256 ok); run-ca3-pc1-v5-amd-bench-20261007 published 00:14:19Z (the 9070 XT by name, about 3 minutes, lock-free), its start line printing app_version, so the 0.3.20 or 0.3.23 reading of PC 1's app comes with the fingerprint; PC 2's Arc job needs only the shipper's "PC 2 clear". PC 1's app had NOT taken the 0.3.23 kit as of the last reads (every job log through 21:46Z app_version 0.3.20; the install folder's exe igneum-app 0.3.20, mtime 12:24:42Z, sha256 0443ae17...). The update-return lane (a22d765a2e0355a9f) last spoke at 23:0x BST: the helper workaround for 0.3.20 scripts (truncate cmd.txt, restart the task, wait for helper.alive, then write; or four leading " dev " padding lines), the locked jobs held as they are, power-helper-24 b9a72b9b merged into release-0.3.24 (daa7427b: a silent change becomes a logged line, the helper writes its exit reason), install-close-23 4ad6c199 for 0.3.23's take 3, the re-probe job when PC 1's app has taken the 0.3.23 kit; nothing since. THE SPEC-TEXT READ-BACK PASS (adv-accept-3 Q4c, 01:11 to 01:15 BST on build-2 at 16 cores; report section 6.5 on build/adv-accept-3, log 983-textderive-8b834634.tsv, pushed): the spec text at master 8b834634, implemented fresh without the crate's generator or rule, reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences (every instruction, the chosen attempt, the id, the rejection sequence); the 264-of-400 divergence against the text at 017e7037 is closed, so AP-F8-5 reads fixed on a measurement. The one remaining gap: 1.4.6.4 names dataset_elem "of verify.rs" without its six operations, so parts (c), (c') and (c'') still take that function from the crate; the audit lane's one-sentence closed form (asked 01:1x) closes it, and the read-back re-runs on the new text. THE AMD CLASS V5 FINGERPRINT (PC 1's RX 9070 XT, gfx1201, beside the miners, lock-free): 82b19cbde8557ea5 at 01:16:14 BST, equal to the kit e6c088bb's on Metal, Apple OpenCL and CUDA, self-test PASS, the v4-genesis control 892b6d55a7ddcfcb PASS; the 0.3.24 kit stands on four platforms; Intel waits on PC 2 (held until main's word, since the 0.3.23 take 3 never ran there); PC 1's queue continues with the CA4 unlocked rows. The kits row reads: Metal, Apple OpenCL, CUDA, AMD equal; Intel not measured tonight. THE UPDATE-RETURN LANE'S THREE READINGS (01:17 BST, from the live manifest and the intake): (1) 0.3.23 take 3 (install-close-23 4ad6c199) never reported; the live manifest igneum-app-latest.json reads 0.3.23 published 20:37:44Z with platforms = {mac} only, NO Windows entry, so neither PC has anything to take through its update path; PC 2's app run is still take 1's relaunch from 21:08:43Z (997 uploads, last 00:16Z); (2) PC 1 will not take 0.3.23 unattended tonight for want of a Windows entry; its run win-ae432dc7-20261007-160110 (0.3.20) never restarted (2,376 uploads, last 00:16Z), mining 18.96 MH/s on the 9070 XT; when a Windows entry is published the 0.3.20 engine's OTA takes it with no hand; the 21:41:32Z helper.ps1 write was not the prompt path (0.3.20 writes that file unconditionally), so no screen is owed in the morning for it; (3) the re-probe job (relay/playbooks/pc1-helper-reprobe.ps1 on power-helper-24 69f3c733) waits only on PC 1's exe becoming 0.3.21 or later; the 0.3.20 workaround is cleared to run tonight as a lock-free job so the locked grids go ahead: per grid job, before the first command, empty sweep\cmd.txt, Stop-ScheduledTask and Start-ScheduledTask 'Igneum Power Helper', wait until helper.alive is within 4 s, then write the lines with climbing sequences (in 0.3.20 the skip is the line count at the helper's start, fixed for its life); the helper idle-exits 20 minutes after its last command and the next start must begin over an empty file again; never pad after a command. The coordinator's order to the hash lane on it: the locked grids proceed in the earlier order (the 5080 full grid, the third 5090 pass to the driver's floor, SM-sparse, the two Ember tunes, the hot-table ldcs rows), each with its restore step, under the no-prompt rule; a Start-ScheduledTask that reads the 0x800710E0 refusal again stops the job and reports, nothing escalates. THE LOCKED GRIDS UNDER THE WORKAROUND (the hash lane, 01:2x BST; commit 24f9858e on the mirror): the three lock scripts carry the cleared sequence (empty sweep\cmd.txt, Stop- then Start-ScheduledTask 'Igneum Power Helper', helper.alive within 4 s with a 60 s cap, then dev + command with climbing sequences; repeated before any write when helper.alive is older than 10 s; a refused start 0x800710E0 or no heartbeat stops the lock path with the text on RESULT lines, nothing escalates; no padding; each grid job ends with rgc through the same sequence and the applications clock read back). PC 1's app_version on the v5 bench's start line: 0.3.20 (no Windows 0.3.23 published, nothing to take). The CA4 SM-sparse job run-ca4-pc1-ca4sparse-5090-20261007 runs since 00:20:40Z on the earlier padded script (unlocked rows first, then its 1,300 knee attempt; about 25 to 50 minutes); then in order on the shipper's acks: the 5080 full grid as run-ca3-pc1-v4-eff-5080-20261007-d, the third 5090 pass (1,100 MHz down), the microbench and the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the 5080 grid's knee and best points to the site audit lane for row 17 as read. THE ATTEMPTS CENSUS COMPLETE (adv-accept row 90, 01:34 BST, 20,000 seeds, closing the partial named at 00:00): 42,711 rejected candidates; (a') 83.5 percent, (a) 11.6, (b) 3.0, (c'') 1.1 (459 candidates), constant bit 0.4, saturated 0.3, (c') 0.05, distinct 0.04, lane-constant and bias 0; per-candidate rejection 0.681, flat across attempts 0 to 3 (the halves agree to a tenth of a percent); accepted-attempt mean 2.136, max 28; 0 exhaustions; P(256 consecutive rejections) 2e-43 per seed. The number for spec 1.4.6: under sub-version 3 the per-candidate rejection is 68.1 percent and the expected attempt 2.1. adv-accept's shards run on in the pool's gaps under the mechanical yield; the box-hours cross 8 later tonight. CLASS-V5 LANDED ON BOTH MIRRORS (the v5 lane, 091a0758 at 01:40 UK): the full pre-push gate GREEN at 71 checks (stamp on 48d38493, the last code change); the igneum-pow suite on box 2 (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs byte-identical to the merged crate's export, so e5a4ac5978462156, 7c54302b487340a1, a217c7f698880830 and 82b19cbde8557ea5 hold under master's recipe form, recheck 2, scratch 7, spec_readback 2); spec-constants 28 rows agreeing; identity grep 0 hits. Carried since 61588347: main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2; the 61-row era reading and the class v5 attempts census on the spec, the page and the ledger; AP-F8-3; spec 1.4.7 and 1.8.6 with the constants and id tables; the AMD fingerprint row; the kits branch and master merged; two corrections the proofs found: master's program_id_derivation text lacked the class v5 rung-0 arm (the v5 packs' text named the class recipe while the id was the plain form; the arm added to the TEXT, re-exported, ids unchanged; a post-freeze change on the class-v5 line, so 0.3.25's pairing, never 1c420786's), and the public-export scrub (the founder's name six times on the page, the zone name in three files; gone). Incoming to the page: the Arc fingerprint, F9 and F1. THE MOVE FILE NOT PUBLISHED (the shipper, 01:41 BST): build-1's /fleet/move.json still names commit 2720d8d2 with the 22:30 BST minute; no FETCHED count, no named minute; the fleet lane (ac055d60427caab99) has answered nothing since its 22:4x report (asks at 01:05, 01:16 and 01:41; its task output last written 22:21 BST, its last action a hand read of dn3-g1's proven share), the second dark lane beside the build-server lane (last written 22:36 BST). So 02:00 BST cannot hold; the 02:53 BST ceiling (DAA 32,400) stands only if a signed move file lands at once and the 34 pullers fetch inside forty minutes; main has the clock line with the two options (wake or replace the fleet lane; or a fourth re-cut from a morning minute, the Mac entry standing down with it). The publish record's shape stands: the Mac entry at the minute (staged, DMG 1aa301cc, both folders, armed); the hive and the Windows pairs on main's word; the pairing 1c420786, 091a0758 0.3.25's. Every other gate on dfbd1e10 green and recorded. THE RUNG-0 ARM CONFIRMED (the v5 lane, 01:4x UK): 987e90e8 touches only Program::program_id_derivation, the text in program.json; Program::program_id untouched (the v5 rung-0 plain-form branch since the freeze); the crate at 091a0758 and 1b5684ec (master 35602b30 merged, pushed 01:41 UK) derives every pinned id byte for byte (packs 20 on box 2 comparing all three pinned packs' files including program_id and leaves.bin; spec_readback 2); the shipper told 091a0758 and 1b5684ec are 0.3.25's pairing, 0.3.24 on 1c420786. THE SM-SPARSE JOB (run-ca4-pc1-ca4sparse-5090-20261007, exit 0 at 00:41:53Z, 1,171 s, the 5090 alone, every fingerprint matched, the Power Helper answering every command on the padded write, the card left unlocked at 2,855 MHz): the SM-sparse reading does NOT exist; the research lane's worker ran its base kernel on every variant row (its race line "race 0 ms variant base" on all 48 rows, no NVRTC compile text), so --bench never honoured --variant sp-w32; the sparse rows equal base in rate and drift in watts with the card's heat only; the rerun waits on the research lane's exe honouring the flag. What stands: a repeat of the efficiency pass at two states, 32 s rows, the card alone: v4 unlocked 137.07 MH/s at 465.5 W (0.294 MH/W), at 1,300 MHz 134.26 at 309.9 W (0.433; 155.6 W back for 2.05 percent of rate); v3 unlocked 136.71 at 331.6 W (0.412), at 1,300 134.03 at 219.4 W (0.611; 112.2 W back for 1.97 percent); the v4 premium 133.9 W unlocked, 90.5 W at the knee; the three power fields agree within 0.2 W on every row (power.draw = instant = average on driver 617.14), which settles the field question on PC 1's side and leaves the 5080's 110 W gap to the fleet's rented card's sampler. Next on the shipper's ack: the 5080 full grid (-d) through the cleared helper sequence, the third 5090 pass, the microbench, the seven packs, the two tunes, the hot-table ldcs rows (kit and job at 292fcc75). THE --variant FAULT FIXED (the research lane, counter-asic-4, UTC clocks on 8 October): 00:44 the fix (a --bench with --variant runs the pinned race and installs the named kernel; the RESULT line carries variant=, sparse_blocks=, block_warps=; a served kernel other than the requested one prints variant_not_installed); 00:46 the known-failed test on build-1 against the real class v4 pack, no card (base: race off, 524,288 blocks of 32, "variant base"; sp43-w32: race on, 43 sparse blocks of 32 warps, the rewritten kernel with the nonces argument and the unit function, 43 blocks of 1,024; PASS; before the fix both read the base shape); 00:46 the Windows exe igneum-worker-cuda-ca4sparse3.exe sha256 0ba97edcd5c46a302a7ff5ddd1bbb1e493ca15f64d0757820ed645972df3bb56, mingw exit 0; the commit after 2d0013d1; the hash lane has the sha, the test's lines and the rerun's job shape (the same 48 rows, the race line per row); the op-mix re-weight stays behind the SM-sparse reading, the served 3.4x standing; the clean efficiency repeat in the file's 20.3a (6.6 pJ per counted op). THE SPEC'S LAST CRATE-DEPENDENT SENTENCE CLOSED (the site audit lane, master 56eebc0d at 01:49 BST, gate GREEN on c2c92eab, 71 checks; spec_readback now 3 tests): 1.4.6.4 states dataset_elem in full (the eight operations, the three constants, 32-bit wrapping) with two pinned vectors (dataset_elem(0x00000fed, 0x9E3779B9, 0x7F4A7C15) = 0x5c7dabd2; dataset_elem(0x0fffffff, 0, 0) = 0x7662c1ec) that spec_readback.rs reads from the text and checks against the crate, so part (c) computes from the text alone (34845c47); 1.4.6.5 names the class v2 figures as class v2's and carries the shipped rule's own census sentence (20,000 seeds, 68.1 percent rejected per candidate, the per-part shares, mean attempt 2.1, max 28, 0 exhaustions, 2e-43). The text-derived re-run on this text is the proof it is sufficient end to end (asked of adv-accept-3). THE MOVE FILE STAGED (the shipper, 01:5x BST): id mdfbd-1, commit dfbd1e10, want_digest b1ba7822, both pair slots on build-1's served tarball dfbd1e10-node-lane.tgz (e59ed0e6), at_epoch 0, signed with the fleet key on the Mac and verified against the fleet's public key in the puller's namespace; the read-back on placing it: the served file's id by curl and the first FETCHED on the relay intake; the 34 pullers fetch inside their one-minute timers (27 MB from build-1), the last FETCHED about five minutes after the file, the earliest minute ten after that. THE REAL LATEST-PUBLISH CLOCK: the file alone halts every miner on the restart, because each box's pack gate PAIR_MINER_SHA16 lacks aa8c2978 and the puller does not carry the file's miner sha into the restart environment; so route (A) also needs one ssh line on each of the 34 boxes before the minute with the fleet's tooling (the fleet lane's, or the shipper's on main's word). Absent main's word by 02:15 BST the shipper stands the Mac entry down under the ceiling rule (no app alone on b1ba7822) and 0.3.24 becomes a morning minute with a fourth re-cut. ROUTE (A) STAGED TO ONE COMMAND (the shipper, 01:5x BST): the gate script r0324/move/pair-gate-aa8c2978.py in its scratch (dry run by default, apply on the literal argument, the fleet's own Box helper and label list, nothing restarted); the dry run read 33 of 35 boxes, every one carrying the old gate list with fb147dd1 last and aa8c2978 absent, no env-last override; unreachable dn3-relay and p2-4090-1b (dead Vast proxies; they fall off at the move and rejoin by the pull); the apply about 90 s for the 33 with each gate read back and counted. THE F9/F1 INTERIM (the attack-pass lane, read at 01:5x BST): 71,292 seeds, 0 exhausted, 0 panics, max attempt 30; F1 0 failures at 2 h 23 min; the move's gate reads clear. On main's (A): apply 02:00, the file placed 02:02, the last FETCHED about 02:05, the minute 02:15 BST; main has the clock. Nothing applies before the word. THE SPEC TEXT SUFFICIENT END TO END (adv-accept-3 Q4d, 01:52 to 01:57 BST on build-2 at 16 cores; report section 6.6 on build/adv-accept-3, log 984-textderive-56eebc0d.tsv, every row equal to its Q4c row): the spec text at master 56eebc0d, implemented with nothing from the crate (text.rs: 0 igneum_pow imports; dataset_elem from 1.4.6.4, its two pinned vectors checked at start), reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences on every field; no sentence of the generator or acceptance sections needs the crate; the documentary finding (AP-F8-4, AP-F8-5) closed in full on two measurements; the lane at its end, 3.35 box-hours in all. F9 AND F1 AT 00:59Z (class v5 at 1c420786, pairing e5a4ac5978462156, build-1): F9 73,691 of 100,000 chain-shaped seeds written, 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; the attempt histogram 23,119 / 15,981 / 10,805 / 7,547 / 5,181 / 3,415 / 2,439 / 1,653 / 1,119 / 744 / 529 / 389 / 258 / 152 / 113 / 72 / 54 / 40 / 31 / 14 / 15 / 5 / 2 / 6 / 2 / 4 / 1 at 26 / 1 at 30, r about 0.69; the 10^5 about 01:30Z (02:30 BST). F1: the 10^5 redundancy census at 2 h 28 min under its lease with no end marker (18 minutes on an idle box; under tonight's load no minute named); its panic path live and empty, 0 failures the honest reading. Both land as record lines, then the board's close per item on sub-version 3 and class v5. AP-F8-5 ON TWO MEASUREMENTS (the site audit lane, commit 116e6055, master 5c77a7ac at 02:05 BST, gate GREEN 71 checks): the row carries Q4c (8b834634, 0 of 400 with one crate function, section 6.5, log 983) and Q4d (56eebc0d, 0 of 400 with no crate import, section 6.6, log 984); the public ledger and the ledger page regenerated; nothing open in the spec or the ledger on the audit lane's side. THE 5080 FULL GRID (run-ca3-pc1-v4-eff-5080-20261007-d, exit 0 at 01:54:00Z, 4,118 s; PC 1's dock card alone, driver 617.14, app 0.3.20, mem 14,801 MHz throughout; every lock through the cleared helper sequence, every command answered first time, every fingerprint matched, clocks reset and read back): the knee as a reading: the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes (v4 71.19 of 71.41 MH/s; v3 71.11 of 71.28) and falls 5.2 percent at 900 MHz on v4 (67.66), where the 75-minute budget ended the grid (v3's 900 and below not taken; the drift check skipped); so the 5080's knee sits between 1,000 and 900 MHz, a third of its 2,963 MHz boost, lower than the 5090's 1,300 (84 SMs at 2,960 MHz have more compute headroom per unit of its 960 GB/s than the 5090's 170 SMs per unit of 1,792 GB/s; the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: v4 at 1,100 MHz, 71.20 MH/s at 146.6 W (0.486 MH/W; 106.5 W recovered for 0.29 percent of rate); v3 at 1,000 MHz, 71.11 at 103.7 W (0.686; 66.0 W for 0.25 percent). The v4 premium 83.4 W unlocked (253.1 against 169.7), 41 W at the best points (146.6 against 105.6 at 1,100). Per tier: a 5080 owner on class v4 locked near 1,100 MHz draws 147 W instead of 253 for 0.3 percent less rate (MH/W up 72 percent) and the shadow's residual cost is 41 W. Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 71.41/253.1/0.282 ; 71.28/169.7/0.420 (sm 2,963/2,977); 2850 71.41/229.5/0.311 ; 71.29/155.3/0.459; 2700 71.41/209.6/0.341 ; 71.29/149.2/0.478; 2550 71.41/193.0/0.370 ; 71.29/134.4/0.531; 2400 71.41/176.0/0.406 ; 71.29/128.7/0.554; 2250 71.41/165.6/0.431 ; 71.28/117.3/0.608; 2100 71.38/157.7/0.453 ; 71.28/112.3/0.635; 1950 71.37/154.0/0.463 ; 71.26/111.6/0.639; 1800 71.35/150.3/0.475 ; 71.24/113.4/0.628; 1650 71.33/151.4/0.471 ; 71.22/109.7/0.649; 1500 71.30/149.2/0.478 ; 71.19/110.6/0.644; 1400 71.27/149.6/0.476 ; 71.16/107.0/0.665; 1300 71.24/147.9/0.482 ; 71.14/107.7/0.661; 1200 71.20/149.4/0.477 ; 71.12/104.4/0.681; 1100 71.20/146.6/0.486 ; 71.11/105.6/0.673; 1000 71.19/149.0/0.478 ; 71.11/103.7/0.686; 900 67.66/137.8/0.491 ; not taken. Throttle reason 0x400 (the power governor) on every row, never the clock lock, so the draw floor of about 147 W (v4) and 104 W (v3) from 1,500 MHz down is the memory system plus idle, not the SMs: the clock lever is spent by 1,500 MHz on this card. The three power fields agree within 0.2 W on every row. The site audit lane has the knee and best points for row 17; the bench table's 5080 row takes "71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", class v4 cost "+83 W unlocked, +41 W at the best points", hive core 1100 (the mem clock unchanged) once the fleet's rented-5080 sampler question is closed. Next on the shipper's ack: the third 5090 pass, the SM-sparse rerun on the fixed exe, the microbench, the packs, the two tunes, the hot table. THE NIGHT'S MOVE OUTCOME (the shipper, 02:58 BST): main's word on (A), (A') or (B) did not come (asked 01:41, 01:50, 01:53, 01:56 by the shipper and 01:42, 01:52, 01:5x, 02:00 by the coordinator); the gate script not applied (the dry run's 33 of 35 the only read); the move file not placed (build-1's /fleet/move.json serves m2720-1, 2720d8d2, the 22:30 minute, by curl at 02:56); no move minute; the stand-down under the ceiling rule holds from 02:15 (the shipper's stand-down line at 02:15 was not sent, its miss, the state unchanged); the Mac entry standing, not published (staged on DMG 1aa301cc in both folders, the live manifest at 0.3.23). A FINDING: build-1's Devnet 3 seed (the process on 26631 with JSON RPC 27632, the node lane's DAA reader) is DOWN (no such process; node1-dn3 26671 and the observer 26651 run on 2720d8d2; the node lane's 0.3.24 reader on 28690 runs but answers no DAA by the envelope tried), so the node lane's DAA reads since 25,169 at 00:52:38 BST may have stopped with it; at 1.0 DAA/s the DAA passed 32,400 at about 02:53 BST, the 39,600 floor is lost, and the fourth re-cut is from a morning minute main names (before 12:50 BST, or the three heights move with the floor). Every Devnet 3 node is on the 0.3.23 pin 2720d8d2, digest ba75bf6f (the 22:30 move; dn3-j1 behind its proxy unverified since); nothing of 0.3.24 is on any box or in any manifest. The night's 0.3.24: every gate green on dfbd1e10, the kit on four platforms, the move unmade for want of one word and two dark lanes. THE ATTACK-PASS BOARD'S CLOSE (lane (d), 01:58Z on 8 October; record docs/analysis/attack-pass-2026-10.md on the mirror's attack-pass; box-hours approximate: build-2 about 7 h, build-1 about 9 h plus about 6 h of F6 batches and F2 solvers earlier in the day). F9 so far: 89,301 of 100,000 chain-shaped seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 20: 20, 21: 6, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1; r about 0.69), three chunks on their cores to about 02:20Z; F1 the 10^5 redundancy census at 3 h 22 min on 17 threads, healthy, no end marker, 0 failures on its live panic path. The board: F1 shadow redundancy PASS on sub-version 3 (max 5.078 percent at honest-compiler parity; AP-F1-1 on the v5 list at 3.0 percent), running on v5; F2 mixer round margin PASS effort-bounded (no trail under weight 20 to 24 at 2 applications, 29 to 35 at 3, 39 to 47 at 4), not re-run on v5 (the mixer unchanged); F3 chained cache j+1 PASS, not re-run; F4 weak-day census PASS on v4 on the DSP-bound metric with AP-F4-1 reconciled with adv-mixer-2 (median 226, 15 days a century, worst 2050-04-28 at 1.113x), on v5 PASS at 8ca66afa (0 of 2^24 days over 1.1x on both metrics, AP-F4-1 FIXED-AND-PASSED); F5 chip-model sweep FIXED-AND-PASSED (the F2 hour skipped by decision), not re-run; F6 verifier worst case PASS (worst of 10^5 at 8.708 ms half-core; O-1.14 closed, i7-9700K 6.334 ms), not re-run; F7 era draw PASS on all three (0 of 6 re-rolls), not re-run; F8 uniformity FIXED-AND-PASSED on sub-version 3 (60 of 64 under 1.2x; AP-F8-1, 2, 3 closed), PASS on v5 (61 of 64, worst 1.50x, the residue p4, p8, p10; p34 under); F9 edges, hot set, grinding PASS on sub-version 3 (34 of 105,064 edges bounded; grinding +0.004 percent), the exhaustion count running on v5; F10 ladder signal PASS, not re-run (node rule). Findings of the pass, all in-house: AP-F1-1, AP-F4-1, AP-F5-1 (the X9), AP-F8-1, AP-F8-2, AP-F8-3; two operating hazards fixed (AP-H1 the box clean, AP-H2 the shared binary path). The open tail (p4, p8, p10, and p34 on sub-version 3) is named in the public report; no outside party holds it (the attack-pass lane's close wrote "disclosed to the firms", stale wording from before the in-house ruling; its record file is to say "named in the public report"). THE SEED'S DEATH AND THE DAA NOW (the node lane, 03:0x BST): build-1's Devnet 3 seed log /home/build/dn3seed.log ends at 01:09:05Z at DAA 29,732 mid-stream with no stop, shutdown or panic line, so it was killed abruptly (it ran under nohup from a shell, not a unit; no journal names the killer; the OOM record needs sudo the lane lacks); its datadir /home/build/dn3seed/igneum-devnet-3/datadir is intact (13 GB) and it stays down until the shipper says; the lane's reads 25,169 at 23:52:38Z and 28,906 at 00:55:09Z came from it while it lived. The DAA now from node1-dn3 on 28670: 32,659 at 01:57:50Z (the observer 32,660), both on 2720d8d2; the chain passed 32,400 at about 01:53Z, 39,600 lost. The fourth cut in one line: the script on release-0.3.24-node reads the DAA from 28670, sets the floor to the morning minute's publish DAA plus 7,200 rounded up to the next 3,600, commits, pushes both mirrors and dispatches the gate set (about 20 minutes to the pin line, then the fast-time pair about 14); the latest minute before the three heights move with the floor is about 11:50Z (12:50 BST), where the floor reaches 79,200; nothing is cut until main names the minute. A morning item for the box owner: a process on build-1 was killed at 01:09:05Z without a log line while the box carried a load of 400 to 600; the killer (OOM or a sweep's cleanup) is to be read from the journal with sudo before anything long-lived runs there again under nohup. THE BENCH LOG ENTRY (the hash lane): docs/bench-log.md "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080" (both cards' full tables, the knee per card, the best MH per watt points, the premiums at the lock, the lever's limits, the job ids and clocks, the rented-5080 watts note) on the mirror's master as merge 773b93a8 at 02:04:47Z (commit 11c698ad); the audit lane writes row 17's sentence from it. PC 1: the third 5090 pass run-ca3-pc1-v4-eff-5090-floor2-20261007 (1,100 MHz down to 300) since 01:57:03Z, about 28 minutes; then the SM-sparse rerun. ROW 17 AND THE 5080 BENCH ROW (the site audit lane, master 2c5c7f52 at 03:19 BST, gate GREEN on 6eb6fd9b, 71 checks): docs/evidence.md row 17 carries both cards' efficiency passes from the bench-log entry (the 5090's knee, best points and premium; the 5080's 71.41 MH/s at 253.1 W unlocked, 71.20 at 146.6 W at 1,100 MHz, v3 at 1,000 MHz 103.7 W, the premium 83.4 W to 41 W, the knee between 1,000 and 900 MHz, the per-tier reading, the Ember Tune lever), a what-moved table for 8 October, /evidence rebuilt (865a0a5e); site/miner-bench.json's RTX 5080 row states the team's pass as the card's figure ("71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", "+83 W unlocked, +41 W at the best points", hive core 1100 with the memory stock, driver 617.14, the bench-log entry as the source) and keeps the rented-fleet sampler reading with its 110 W gap as the open question; /miners rebuilt at 35 rows (6eb6fd9b); 0 identity hits; nothing deployed, the deploy the morning hand-off. The design pass on ca3-coord (015cc839) now sits behind this master and rebases onto it before its own landing on main's word. THE DESIGN PASS REBASED (the coordinator, 03:2x BST): ca3-coord rebased onto master 2c5c7f52 as the three site commits only (f5b7140c the design pass, 8cc4cbc6 the phone grid, 9ad3fdc9 the six-column row; the two commits already landed through the record branch skipped), site/miners.html rebuilt at each from the merged miner-bench.json so the page carries the 5080's new row ("71.4 stock (71.2 tuned)") under the design; the diff against master is build.mjs and miners.html only; pushed to the mirror (pre-push GREEN); it lands on main's word after the captures, one gate run. ADV-MIXER-3's LINE (read from its report at tip e02297ae, 03:18 BST): queue 17 finished on build-1 at 01:3x BST; Q2 single-bit avalanche at 2^27, k = 2 and 3 on day 20729: 0 holes, 0 cells beyond 6 sigma at band 0.00026, PASS (the k = 1 finding stands as the single-application diffusion); Q2b t-bit avalanche on day 20733 at 2^28: 0 cells beyond 6 sigma at band 0.00018, PASS (k = 2, 3, 4 on 20729 at 2^28 the same); Q3 at k = 8 NOT run (killed at 20:20 BST under the lease rule, not re-queued; k = 2 to 7 clean with 0 deterministic bits on both days), named partial; Q6 the day-20733 SAT ladder: k = 2 and 3 TIMEOUT at the one-hour cap, k = 4 on one build-2 core since 03:05 BST, its cap about 04:05; one pre-emption in its ledger (23:58 BST, 21 minutes of a 2^27 row lost, re-queued); box-hours about 3.0 wall-hours of sweep (build-1 1.9, build-2 1.1) plus about 4 single-core CaDiCaL hours, about 7 with the 20733 ladder. The pass's close with the per-lane table and totals at about 04:05 BST; section 13 on crypto-engage (docs only) merging the current master and going through the gate to the mirror's master so the record cites a master commit. Box 2 at 03:20: adv-accept 87 cores in four shards with three waiting, adv-mixer-3 one core; build-1 load 34, no adv lease. THE DESIGN PASS'S OVERLAP ON THE BOX (the CI steward, 03:33 BST): the 1440 and 390 dark captures of /miners from ca3-coord 9ad3fdc9 taken on build-2 under lease pool 4 (Playwright chromium 1194, the recorded feed; /srv/artefacts/captures/ca3-coord-9ad3fdc9/miners-1440-dark.png 1440 x 4280 and miners-390-dark.png 390 x 9779); the overlap sweep on the same checkout, 390 to 1600 px, light and dark: RED, 3 findings on the change itself: at 1280 px dark and 1600 px light and dark the date span in the lead cell's class v4 line is COVERED by the rate cell (4 of 5 sample points under td.big); 390 to 1024 pass. Cause: the branch's last gate ran on the Mac, which has no browser, so the sweep skipped and read GREEN; on the page the row rule's white-space:nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell from 1280 px up. FIXED at ca3-coord 2ca45001 (the lead cell's rule at the row rule's specificity, max-width 360 px, the class v4 line wrapping with overflow-wrap), rebuilt, pushed; the sweep and the captures re-run on the box before main's word. THE IN-HOUSE PASS'S PATH TO MASTER (the crypto lane, 03:2x BST): adv-accept's box-hours crossed 8 before 02:00 BST and sit near 10 (87 cores in four shards; it sweeps on under the mechanical yield, its reading unchanged); crypto-engage merged master 56eebc0d at 342b6730 (one conflict in funding.md, the pre-public scrub against the rewrite, resolved to the in-house pass with the scrub applied; the founder never named in in-house-pass.md or funding.md), the full gate running, merge-to-master on GREEN; section 13.3: master's igneum-pow moved after the freeze in four files (src/emit.rs and src/generator.rs, the derivation string and its recipe helpers, ids unchanged; tests/derivation.rs and tests/spec_readback.rs), none the hash, so the object the pass bounded is unchanged in every operation the hash performs. THE PASS IN ONE LINE (the crypto lane, 03:2x BST): eight of nine lanes closed, adv-mixer-3 on one SAT timeout (about 04:05 BST), adv-accept sweeping to its 16 box-hour line (9.2 now, the reading saturated at the 1.002x class), adv-cache-2 on one line shard; no break of class v4 sub-version 3; the acceptance's hot-set class closed by the class v5 floor (9 of 9) and its diffuse era-stride class routed to the next class; the weak-day FPGA tail reconciled and closed by a measured redraw rule; the attempts census complete; the spec text proven sufficient by two read-backs; one pod at USD 0.33 in the whole pass, none originated by the lane. THE THIRD 5090 PASS BELOW THE KNEE (run-ca3-pc1-v4-eff-5090-floor2-20261007, running at 02:34Z on its 500 MHz step; the steps lengthen as the rate falls since the batch count was sized from the unlocked rate, about 155 s at 500 against 60 at 1,100; the helper answering every command on the cleared sequence, every fingerprint matched, the 5090 alone). Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 137.09/456.7/0.300 ; 136.79/320.0/0.428 (sm 2,858/2,862); 1100 120.98/275.9/0.439 ; 117.32/198.6/0.591; 1000 110.03/254.9/0.432 ; 106.73/180.2/0.592; 900 97.43/232.7/0.419 ; 94.33/174.5/0.541; 800 86.00/216.3/0.398 ; 83.41/166.6/0.501; 700 75.98/202.7/0.375 ; 73.58/156.4/0.470; 600 65.30/178.2/0.366 ; 63.25/153.3/0.413; 500 53.03/166.5/0.319 ; v3 running. Reading: below the knee the rate falls about 10 percent per 100 MHz on both classes (compute-bound: the shadow and the base program no longer fit the memory wait) and MH per watt falls with it from 1,100 down, so the best point stays where the second pass put it (v4 at 1,200, v3 at 1,300); the driver took every lock down to 500 (the SM clock within 10 MHz), so the floor is below 500 MHz and is not where the optimum lives; the v4 premium below the knee 77 W at 1,100, 75 at 1,000, 58 at 900, 50 at 800, 46 at 700, 25 at 600 (the ALU work shrinking with the clock as the rate does). The exit line, the 400 and 300 rows, the drift check and the restore at its close; then the SM-sparse rerun on the fixed exe (each sparse row reading served= and sparse_blocks=, marked variant_row=FAILED if served as base). F9 AND F1 AT 02:34Z (class v5 at 1c420786, build-1): F9 98,945 of 100,000 seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 18: 39, 19: 19, 20: 24, 21: 8, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1); the last three chunks within minutes of their ends; F1 at 4 h 02 min under its lease, no end marker, 0 on its panic path. The pass record's wording fixed on the mirror's attack-pass at 9474cea8 ("named in the public report"; no "firm", "firms", "escrow", "prize", "paid review" or "Lot" line in the pass record or the ten row records; identity grep 0 hits); the section's merge to master after the two record lines, through the full gate in a detached worktree. THE SECOND SWEEP ON THE DESIGN PASS (the CI steward on 2ca45001, 03:38 BST): the desktop widths pass; RED at 390 px dark only, three findings on the lead cell (the card name and the class v4 line covered by the rate cell), the cause the new 360 px max-width on the phone grid; FIXED at ca3-coord 5158276c (the lead-cell width rule scoped to widths above 1,100 px, the phone grid's lead cell with no max-width), rebuilt, pushed; the sweep and captures re-run on it. F9 PASS ON CLASS V5 (the attack-pass lane, class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, the last chunk written 02:34:54Z): 100,000 of 100,000 seeds drawn through the chain path (era-composed class), 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; histogram 0: 31,454, 1: 21,460, 2: 14,660, 3: 10,263, 4: 7,047, 5: 4,701, 6: 3,297, 7: 2,256, 8: 1,532, 9: 1,027, 10: 702, 11: 509, 12: 365, 13: 216, 14: 153, 15: 103, 16: 80, 17: 56, 18: 39, 19: 20, 20: 24, 21: 9, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1 (first-draw acceptance 0.3145; the mean attempt index 2.185, so 3.185 draws per seed on average; 4,862 seeds, 4.86 percent, at index 8 or above and 255, 0.255 percent, at 16 or above; the 256-attempt cap and the deterministic last resort never reached; the lane's first line read 1.993, a slip it corrected); the exhaustion gate holds for the 0.3.24 move; record docs/analysis/attack-pass/f9-grind.md and the lane (d) section on the mirror's attack-pass. F1 still running (4 h 05 min, 16 cores, 0 on its panic path, no end marker). F9's record on the mirror's attack-pass at 2bcb7e08 (the lane (d) row and f9-grind.md section (d); feature gate GREEN); F1 the one open item before the lane (d) merge to master. THE DESIGN PASS GREEN ON THE BOX (the CI steward on ca3-coord 5158276c, 03:4x BST; build-2 under lease pool 4): the overlap sweep 390 to 1600 px, light and dark, GREEN, 0 findings (the known-failed fixture fired first); the 390 px capture byte-identical to 9ad3fdc9's (the phone shape that passed before), the desktop widths carrying the wrap at 4,640 px tall; the four dark whole-page captures on build-1 under /srv/artefacts/captures/ca3-coord-5158276c/: miners-390-dark.png (sha256 9eec8f27..., 509,158 bytes), miners-1280-dark.png (1b6e636d..., 438,541), miners-1440-dark.png (87387e14..., 445,402), miners-1600-dark.png (d53973cd..., 448,545); the run log /srv/builds/bs-ci-steward/cap-out/run-5158276c.log on build-2. The branch's gate record: a full gate on the Mac skips the sweep (no browser), so the box line is the sweep's verdict for 5158276c; the branch waits on main's word on the look and lands in one gate run. THE IN-HOUSE PASS'S RECORD ON MASTER (the crypto lane): crypto-engage dab0c89f (gate GREEN, 71 checks) landed through merge-to-master.sh --remote build at 03:50 BST as master 00b8cd1b: docs/plans/cryptanalysis/in-house-pass.md section 13 (the roll-up, every lane's reading, the frozen-object note) and funding.md's in-house row and brief, scrubbed under founder-strings-check.sh. AN EXCEPTION OWNED (03:39 to 03:50 BST): the lane's first merge call used the tool's default path, which reads CI on GitHub with gh run list; GitHub is suspended and the rule says never poll it; the tool polled 21 times (each 403, nothing pushed, nothing read); the run's process outlived the task stop and the lane ended it by its pid at 03:50 BST, then used --remote build; the breach is the tool's default against the rule and the lane's for not passing the switch; no state moved on GitHub's side. The coordinator's order on it: merge-to-master.sh's default remote must refuse GitHub while the suspension stands (the CI steward, a gate-side fix with a known-failed self-test), so the rule does not rest on every lane remembering the switch. THE THIRD 5090 PASS CLOSED BY ITS CAP (run-ca3-pc1-v4-eff-5090-floor2-20261007, ended by the 45-minute cap at 02:42:05Z during the 300 MHz step, exit -1, its own finally block never ran; every row taken matched its fingerprint, the 5090 alone): the 500 row's v3 side 51.37 MH/s at 136.4 W (0.377); 400: v4 42.62/152.5/0.280, v3 41.32/131.3/0.315 (sm 390); 300 not taken; no unlocked-end drift check; the driver took every lock down to 400 (the SM clock within 10 MHz), so the floor is at or below 400 MHz. The reading: below 1,300 the rate falls about 10 percent per 100 MHz on both classes and MH per watt falls from 1,100 down (v4 0.439 at 1,100 to 0.280 at 400; v3 0.592 at 1,000 to 0.315), so the optimum stays at the second pass's points (v4 1,200 MHz, v3 1,300) and nothing below 1,100 is worth the knob's time; the v4 premium below the knee shrinks with the clock (77 W at 1,100, 46 at 700, 21 at 400). AN EXCEPTION OWNED: the 5090 sat at the 400 lock (390 MHz, 127 W mining) for four minutes until run-ca3-pc1-clocks-restore-20261008 (02:45:20 to 02:46:30Z, exit 0) started the helper over an empty cmd.txt and sent rgc ("All done"), the card reading 2,880 MHz after; the cause the batch count per step sized from the unlocked rate, so the low steps ran 2.5x longer than planned; the fix in the scripts: the budget check ends the grid with the restore inside the cap, and a probe dev line answered in helper.log counts as the helper up when its heartbeat file stays stale (the restore answered at once with helper.alive stale past 60 s). THE SM-SPARSE RERUN: fetch-ca4-sparse3-exe-20261008 landed 02:49:57Z (sha256 0ba97edc...), run-ca4-pc1-ca4sparse-5090-20261008 published 02:51:15Z on the hash lane's own order (the shipper's acks were for the void host slot); each sparse row reads served= and sparse_blocks= and is marked variant_row=FAILED if served as base; the close about 03:15Z (04:15 BST). THE STEP-BUDGET FIX ON MASTER (the hash lane, merge 9fd8b1d8 at 03:02:03Z on 8 October, commit 0b00c42e, the full gate GREEN): the efficiency pass keeps four minutes of its cap for the restore (every step and lock guarded by the deadline minus four minutes) and sizes each step's batch count from the last rate read for the pack, so a 60 s step stays 60 s as the rate falls; a probe dev line answered in helper.log counts as the helper up when the heartbeat file stays stale (all four lock scripts); the gate check tools/ci/pc1-step-budget-check.sh with the known-failed case first (under the old rule a lengthening grid ends on the cap with no restore; under the new it ends with the restore at 1,500 s of 2,700), wired into pre-push.sh and checks.txt (74 checks). The 5080 Ember tune, the 9070 XT tune pass and the hot-table ldcs rows publish behind the SM-sparse rerun, the microbench and the packs. THE SM-SPARSE RERUN FAILS THE SAME WAY, NOW NAMED (run-ca4-pc1-ca4sparse-5090-20261008, the fixed exe ca4sparse3, started 02:52:48Z): every sparse row served=base sparse_blocks=0 variant_row=FAILED, the worker's own line "RESULT variant_not_installed requested=sp43-w32 served=base race=... variants 1 base only, no race (no other variant named)", no "compile:" text, so NVRTC never saw a rewritten kernel: the variant name is parsed into the request but never added to the race's variant table in this exe; the research lane's emulation test checked resolve and rewrite, not the race list the bench builds (a test of the wrong layer; the known-failed case must be the bench's own race line reading "variants 2"). The rows are base runs; no reading. The queue goes on: the microbench at the rerun's exit (about 03:15Z), the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the SM-sparse question's fourth row stays with the research lane, an exe whose card-free check shows "variants 2" in its race line getting the slot within the minute. CLASS-V5'S F9 ROW PUSHED (the v5 lane, class-v5 1d5e5d23 on both mirrors at 04:04 UK): the page's F9 row (100,000 seeds, 0 exhausted, max index 30, first-draw acceptance 0.3145, mean index 2.185, F9 PASS, the record file named), F1 stated as running with 0 failures (its own commit to follow), the Intel row not measured tonight; master merged twice (2c5c7f52 gated at 5f5e0a5c, full gate GREEN 71 checks at 03:45 UK; 9fd8b1d8 auto-merged and pushed on the hook's light gate, the full gate running on 1d5e5d23); the generated ledger files and the spec-constants check clean on the tree. THE THIRD --variant FIX (the research lane, 03:04Z on build-1 under lease, with the hash lane): the cause of the 02:52Z rows: the race's push looked the pinned name up in the empty order list through the variant lookup, whose on-demand sp path answers for any list, so the sparse variant was "found" and never pushed; the order is now a pure function with membership by name; --list-race prints, with no device, the race order the worker's own option handling builds and whether the rewrite applies: with the job's exact flags "variants=2 names=base,sp43-w32" and "sparse_blocks=43 block_warps=32 rewrite=applied bytes=22261 nonces_arg=1 unit_fn=1" (before the fix variants=1); exe igneum-worker-cuda-ca4sparse4.exe sha256 84846396559004a8df61881c15ecb42fa3fc1010ad99074e0c0b53e81bb1ca3b, the commit on the mirror after 7e9d52a6; the third rerun on the hash lane's queue at the next slot; the two failed runs stay the night's SM-sparse state, the op-mix re-weight held, the served 3.4x standing. THE GITHUB GUARD ON MASTER (the CI steward, tip 2f702735 at 04:05 UK; merges 53773860 and 2f702735, full gate GREEN 71 checks each): fa7e98fe adds the tracked marker tools/ci/github-suspended (suspended-since 2026-10-07T17:02:00Z, removed by main at the cut-over) and two refusals: merge-to-master.sh refuses a GitHub remote (origin by default, or any remote whose URL carries github.com) with one line naming the switch and exit 2 before any gh or git call; the pre-push hook refuses any push to a GitHub remote the same way (the hook reads the remote URL, so a bare git push origin is refused too); known-failed first in both self-tests; the live read on the Mac: merge-to-master.sh --remote origin exits 2, nothing contacted; two follow-ups (9484b988, a08423d4) fix the tool's own --self-test under the real marker. The rule no longer rests on any lane remembering the switch. F1 READ AT 03:05:58Z (the attack-pass lane; the census process itself, not the lease wrapper): state S with 17 threads, 15 cores busy over 45 s, 2 d 19 h of CPU banked over 4 h 30 min of wall, RSS 0.8 to 1.0 GB; computing, not hung. No rows can exist before the end: the harness collects every Report in memory under thread::scope and writes census.csv in one go at the end (no progress print), named as a harness gap in the record. Why fifteenfold against the v4 reference: under class v5 every candidate draw runs the (c''') distinct-index floor over 2^20 (about 1.8 core-s per candidate under the night's load, times 3.2 draws per program, about 5.8 core-s per program before the analysis), so 10^5 programs at 15 busy cores is about 10.7 h of wall, the end about 09:00Z (10:00 BST), nearer the early side as the load fell to 21. Ruling: not killed (a kill loses 4 h 30 min with nothing on disk); the lane (d) section merges to the mirror's master now with F9 and the F1 row reading "running, 03:06Z reading, projected end about 09:00Z", F1's record line in a second merge when it writes; the harness gains a progress line before its next 10^5 run. THE IN-HOUSE ADVERSARIAL PASS CLOSED (04:08 BST on 8 October; an internal adversarial pass, not an independent review; section 14 of in-house-pass.md at crypto-engage c099e818 landing on master through --remote build; every tip read from the mirror at 04:07 with igneum-pow identical to 017e7037 on all nine). Per lane (tip; box-hours; verdict; partial): adv-mixer d2ba3134, about 0.6 plus 1.8 single-core SAT hours, the algebraic structure BOUND, none; adv-mixer-2 2a632579, 0.31, BOUND for every chip, GPU and the verifier with the FPGA LUT-area FINDING (2^-10.8 of days, 15 a century, worst 2050-04-28 at 1.113x) closed by the measured redraw rule, none; adv-mixer-3 981bfff2, about 5.0 wall-hours plus 8 single-core SAT hours, Q1 BOUND (2^32 t uniform at k = 1 to 8, both days and 8 random days), Q2 and Q2b FINDING at k = 1 only and BOUND from 2 to 8 at 2^24 to 2^28, Q3 FINDING at k = 1 and BOUND 2 to 7, Q4 and Q5 BOUND from k = 1, Q6 SAT BOUND (k = 1 in 137 s, k = 2 to 4 timeout), the round margin 70 of 72 per item, partial Q3 at k = 8 not run, multi-bit masks and a MILP bound not attempted, GPU blocked; adv-cache 555c3e42, 0.55, the recompute shortcut BOUND on every row, none; adv-cache-2 91ca5ce1, about 2.25, the line census PASS at 2^35 + 3 x 2^33, the real programs PASS with the Devnet 3 site-0 FINDING, the diffuse era-stride class named (16 of 32 base programs biased under drawn eras against 2 of 32 under R = 29, 8 over 1.2x, worst 1.75x, under 0.1 percent of reads per site, 0 of 61 refused by the v5 floor, AP-F8-6), steering and the 16,384-day scan PASS, the window layer exact and the chip model's partial-store rows overstated up to 2.3x with the verdict unchanged, partial the line shard s2c waiting on build-1 since 23:09 BST; adv-cache-3 9452c0bf, 0.23, the chain-break or skip BOUND on every row with the pebbling optimum under the hold-every-k curve, none; adv-accept c8a98e46, about 9.2 at 03:25 BST running to its 16-hour line, the bypass FINDING confirmed and bounded (9 few-item hot sets in the tail of 408,067 accepted programs, 0 in 20 random, 1.002x at the largest; all 9 refused by the class v5 floor, 7 clean programs falsely refused among the 12 deepest, 3 mild residuals missed), the stand-in gap BOUND, distinguishers BOUND, the attempts census complete, partial the sweep at 408,067 of 10^6; adv-accept-2 92168536, about 9.0 core-hours and 0.3 pod-hours (the one pod), header grinding BOUND by card measurement (+0.09 percent on an A6000) and by tail (3e-7), one 0.1 percent repeat class for the rule's owners, none; adv-accept-3 7826d2b2, 3.3, exhaustion BOUND (P 1.0e-43), the last-resort path FINDING (correctness, unreachable; closed in class v5), steering BOUND (no property over 1.03x at 1 in 1e6 tries), the program id BOUND with the derivation-string FINDING (fixed on master and in the packs), determinism BOUND, the spec text proven sufficient by two read-backs, the era lever BOUND, partial the steering sweep at 975 of 10^5 full-rule seeds. Totals: about 30.4 box-hours of run across the nine lanes (lease waits excluded) plus about 9.8 single-core SAT hours; pod-hours 0.3 on one RunPod A6000, USD 0.33 in all, rented and destroyed by the fleet lane. The verdict: no lane broke the frozen object; the acceptance rule admits two residual classes of address concentration, both under 1.002x to a chip: the few-item hot sets, closed entire by the class v5 floor (9 of 9) at a 2.4 percent clean-rejection cost, and the diffuse era-stride excess the floor does not reach, routed to the next class with its lever; the weak-day FPGA tail reconciled and closed. Already changed by the pass: the derivation string in the shipped packs, spec 1.4.3 to 1.4.6 rewritten and proven text-sufficient, the chip model's partial-store and pebbling baselines corrected, the last-resort path flagged and closed in class v5. Still to come: adv-cache-2's s2c row and adv-accept's final count, appended when they land. CLASS-V5 GATED (the v5 lane): the full gate on 1d5e5d23 GREEN, 72 checks in 347 s (04:1x UK); class-v5 4a162aba on both mirrors at 04:12 UK with the page's F1 line stating the 04:06 reading (computing, not hung; census.csv only at its end; projected end about 10:00 UK); nothing of the lane's pending on a box or a watch. THE LANE (d) MERGE ON MASTER (the attack-pass lane, 399f8c4d at 03:16:35Z, 04:17 BST; attack-pass 4150f66d, full gate GREEN 45 checks on the branch): F9 PASS on 1c420786 (row and f9-grind.md section (d)), the F1 row as ruled (running, the 03:06Z reading, projected end about 09:00Z, 0 on its live panic path, the harness gap named), the in-house wording kept through a conflict with master's older copy, one founder-strings scrub the gate caught on the pass record (the attribution now "The founder's word"). The harness item: the progress line every 1,000 programs and the flushed partial census.csv (temp file and rename) committed on attack-v5-frozen at 18a9c04a, built on box 2, its known-failed test (a 4,000-program census killed by pid at the 2,000 line, 2,000 rows expected) running under lease pool class adv; the verdict and the push follow. THE SM-SPARSE QUESTION, THE THIRD RUN (run-ca4-pc1-ca4sparse-5090-20261008-b on ca4sparse4, 03:23:45 to 03:48:45Z, exit 0): the card-free check on the card's own exe listed the sparse variant (variants=2 names=base,sp43-w32, rewrite=applied), the race ran it, and NVRTC refused the rewritten kernel on every sparse row: "kernel_bound.cu(370): error: identifier "d" is undefined | igneum_hash_bound_unit(d, ou, baseNonc, mas, i, gid);" (the same for sp170, sp85, sp21, sp11), so the race installed base and every sparse row reads served=base variant_row=FAILED. The hash lane's reading to the research lane: the wrapper's call carries the kernel's parameter names cut by one character (d, ou, baseNonc, mas for ds, out, baseNonce, mask), which points at the rewrite's name capture against the PC's CRLF pack text (the Linux check reported a different byte count for the rewritten kernel): the first card test of the rewrite, the finding kept. The base rows a third repeat of the knee pass (v4 137.06 MH/s at 449.7 W unlocked, 134.23 at 301.4 W at 1,300; v3 136.79 at 329.8, 134.05 at 218.0), the card restored each time. The slot returns to the research lane on an exe whose card-free check compiles the rewritten text through nvrtc for sm_120 (on CRLF input). The queue: the microbench run-ca4-pc1-microbench-5090-20261007 since 03:52:14Z (20 probes of 60 s unlocked, then at the 1,300 lock; about 50 minutes), then the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. THE CLOSE'S MASTER COMMIT (the crypto lane, sent 04:55 BST for a 04:14 landing, the forty-minute gap its own): crypto-engage c099e818 (full gate GREEN, 71 checks) landed as the mirror's master 2882352c at 04:14:50 BST; the record cites the roll-up and every lane's reading at 00b8cd1b and the close (section 14) at 2882352c; further landings only for adv-accept's final count and adv-cache-2's s2c row. THE FOURTH --variant FIX (the research lane, 03:55Z on build-1 under lease): the cause was not the line endings: the rewrite's parameter capture wrote the substring length as end minus start where the last index needs plus one, so every argument lost its last character on any input; CRLF would have missed the anchors entirely; the rewrite now strips \r first (the same rewritten bytes from LF and CRLF, 22,266 on both) and the capture is right; the card-free check through NVRTC on LF and a CRLF copy, identical lines: variants=2 names=base,sp43-w32; rewrite=applied; call="igneum_hash_bound_unit(ds, out, baseNonce, mask, iw, gid)" params=6 args=6 names_match=1; nvrtc=libnvrtc.so.12 arch=sm_120 compiled=1 image_bytes=36256; the failed case the 03:23Z card line. Exe igneum-worker-cuda-ca4sparse5.exe sha256 a4550202b301faf22f5329c2ab4fa1c0aa6695dbdaf31c974f316dca2524d7d6, with the hash lane; the commit on the mirror after 3ac5d20a; the slot after the microbench and the packs. The three failures gave three repeats of the knee pass (the v4 premium 133.9 to 145.3 W unlocked, 90.5 W at 1,300 MHz) in the file's 20.3a. ADV-ACCEPT OFF BUILD-1 (04:5x BST, the coordinator's placement rule): adv-accept runs on to its 16-hour line (about 10:15 BST, 10.6 box-hours at 04:54, the reading saturated) in box 2's gaps under the mechanical yield, its build-1 shard ended at the frontier and its waiter withdrawn, so F1's census keeps build-1 (its 10:00 BST projection assumed load 21) until census.csv writes; adv-cache-2's four-minute s2c shard the one exception. Confirmed by lease status at 04:57 BST: build-1 holds F1 (release, 16 cores) and adv-cache-2's s2c (32 cores, its last shard) and nothing of adv-accept's; adv-accept's four holders and waiters on box 2, where the attack-pass lane's flush test waits at 1 free behind them (the same class, no yield case); the coordinator's placement rule: one adv-accept holder ends at its frontier for the flush test (a 4,000-program census, minutes), since adv-accept's reading is saturated and the harness fix gates the morning's F1 rerun class. Done at 04:59 BST: adv-accept's sweep-s05b ended at its frontier at 04:58:50 (46,460 rows kept) and the flush known-failed test took the 16 cores at 04:58:55; the shard re-queued behind it. ADV-CACHE-2 CLOSED (05:0x BST): its last shard s2c ran 04:56 to 04:59 on build-1 (PASS at 2^33 reads, control-level), so the line census totals 2^36 reads over 464 chain days with every statistic at the control's values; final box-hours 2.35 of run (0.08 a duplicate windows run by its build-1 drain, recorded), pod-hours 0; tip bfc3746c on build/adv-cache-2, igneum-pow identical to 017e7037; the biased-site class (AP-F8-6) and the window-layer pricing stand; section 14's row updated on crypto-engage, landing with adv-accept's final count. Eight of nine lanes at their end; adv-accept alone runs to its 16-hour line about 10:15 BST. THE CENSUS HARNESS'S PROGRESS LINE (the attack-pass lane, attack-v5-frozen 18a9c04a on the mirror): the attack-f1 census prints a progress line every 1,000 programs (count, elapsed, running failure count) and flushes a partial census.csv at the same cadence through a temp file and rename; the known-failed test on box 2 under lease pool class adv (binary 14180ef4...): a 4,000-program census killed by pid at the 2,000 line at 04:08:27Z (05:08 BST), census.csv holding exactly 2,000 rows, no tmp file, lease exit 143; PASS (the old harness's known fail zero rows); record f1-shadow.md section 12 on the mirror's attack-pass at c99f147f (riding the F1 record merge); a side reading: 1,000 programs per 286 s on 16 cores, about 4.6 core-s per program, confirming F1's build-1 projection of about 09:00Z (10:00 BST); the running 10^5 census stays on the old binary, every census after it on the new. F1 PASS ON CLASS V5 (the attack-pass lane; class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, 16 cores; census.csv written 04:20Z, 05:20 BST, after 20,774 s of census, 5 h 46 min, earlier than the 09:00Z projection as build-1 emptied): 100,000 of 100,000 programs through the string-seed draw with the (c''') floor; instructions saved min 0.000 percent, mean 0.623, max 4.688 (the worst seed attack-f1/95060: 6,912 to 6,588); chip-view ops saved mean 0.520, max 4.783; programs over 5 percent 0, over 10 percent 0; soundness: differential mismatches 0 of 100,000 (8 random states each), verifier mismatches 0 of 100,000; 0 panics; the histogram of saved in 0.5 percent bins from 0: 55,241, 20,597, 11,762, 9,851, 1,484, 656, 259, 133, 13, 4, 0, 0. Against the v4 10^5 (max 5.078, the AP-F1-1 letter miss): the v5 tip's worst program sits 0.39 points under the 5 percent letter and the top two bins are empty. F1 PASS on 1c420786 by the letter and at honest-compiler parity; the redundancy gate holds for the 0.3.24 move; AP-F1-1's v5 half FIXED-AND-PASSED at this count; record f1-shadow.md section 13 and the lane (d) row, merged to master next. The attack board on class v5 is complete: F4 PASS (8ca66afa), F8 PASS, F9 PASS, F1 PASS; the rest not re-run by rule. CLASS-V5'S F1 ROW (the v5 lane, class-v5 1095eaa8 on both mirrors at 05:24 UK): the page's attack row reads F8 PASS with the known residue, F4 PASS, F9 PASS, F1 PASS on the full 10^5, the rest not re-run by rule; the full gate running on 1095eaa8; nothing else of the lane's open tonight. THE CA4 PACKS ON THE 5090 (run-ca4-pc1-packs-5090-20261008-b, exit 0 at 04:22:54Z, 579 s; the 5090 alone through the installed worker, the lock and reset through the helper, every self-test PASS at both states): the int8 mma tile prototypes' inline PTX compiles under NVRTC 12.8 on sm_120 and matches the CPU reference (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1, mm1430 8e9b7066239d35d1), as do both per-load exports (404cad3b3399f9b3, ee5d7c71180e5ea7), sh256x27 (3d2e8245cc084d07) and the mx8-genesis control (7c28cfb06c5c65a9). Rows (MH/s / W / MH/W), unlocked then at the 1,300 lock: mx8-genesis 137.54/311.0/0.442 then 127.32/213.0/0.598; sh256x27 137.51/462.2/0.298 then 126.93/295.8/0.429; shl256x27 (unsound, an energy reading only) 158.62/472.8 then 145.65/299.4; shl256x27_v2 (unsound) 135.90/448.3 then 126.04/282.9; mm128 137.45/332.9/0.413 then 127.01/217.8/0.583; mm512 137.50/369.4/0.372 then 127.07/235.4/0.540; mm1430 137.45/457.7/0.300 then 126.87/284.5/0.446. Consequences: the rate is memory-bound on every sound pack at both states (within 0.5 percent of the control); the tile premium over mx8 is 21.9 / 58.4 / 146.7 W unlocked for 128 / 512 / 1,430 tiles (0.103 W per tile, linear) and 4.8 / 22.4 / 71.5 W at the lock (0.050 W per tile), so at 1,430 tiles the tile block costs what the ALU shadow costs (151.2 W unlocked, 82.8 at the lock) and the lock halves it the same way; the first per-load export's 15 percent higher rate is its duplicate reads landing in L2 (the unsound construction), the fixed one 1.2 percent under the control. The research lane has the rows for 20.3 and 20.4; the tile class's premium per tile is now a measured number on the 5090 and its Apple cost (35 to 78 percent of rate) the open side. The microbench -b since 04:23:23Z, then the SM-sparse rerun on ca4sparse5, the 5080 Ember tune, the 9070 XT tune pass, the hot table. THE CA4 PROTOTYPES' FIRST SENTENCE ON MEASURED ROWS (the research lane, counter-asic-4 on the mirror after 1428dd3c; sections 20.3 and 20.4): neither prototype beats class v4's premium; the tile block matches it at the same hash rate (mm1430, 11,440 int8 tiles per hash: 146.7 W over class v3 against the ALU shadow's 151.2 W unlocked, 71.5 against 82.8 W at the 1,300 lock, the rate memory-bound within 0.5 percent) and beats class v4's chip edge only at the pessimistic end (about 2.2x against 3.5x), not at k = 1 (2.2x either way), because the 5090's measured cost per int8 MAC (0.091 pJ unlocked, 0.048 at the lock) sits inside what a 5 nm MAC array costs anyone (a claimed test-chip figure), so a chip's k on tile work is at or above about 1 where on ALU work a fixed datapath reaches 0.3 to 0.5; the per-load placement dead as a construction (its energy rows 13 to 14 W under the whole block for the same instructions; the first export 15 percent faster from duplicate reads served by L2). Against the tile block as a class: the verifier (AVX2 0.047 us per tile per unit; mm1430 10.14 ms with the sibling loaded on the box's core, a 0.14 ms miss of the gate; scalar 13x worse; NEON unwritten), the Apple tier (35 percent of rate at 1,024 tiles, 78 at 4,096), the AMD layout unverified. No served number moves; the SM-sparse reading still owed (three failed runs, the fourth exe queued after the microbench); the op-mix re-weight held, the served 3.4x standing. The k column's basis (the research lane, counter-asic-4 after 781cb395): the 1,430-tile point is the one chip-model-v3 5.11's tensor-tile k column was priced at (15.2 set R about 1,430 from the 4090's 0.056 pJ per MAC to carry the ALU shadow's 0.654 microjoules; 11,440 tiles per hash), and the 5090 reads 0.091 pJ per MAC unlocked and 0.048 at the 1,300 lock there, so the column (2.1x at k = 1, 1.6x at k = 1.5) has its GPU-side cost measured at the premium it was priced for (1.067 microjoules unlocked, 0.564 at the lock, against the ALU shadow's 1.10 and 0.652); the Apple cost the open side; nothing served moves. F1'S RECORD ON MASTER (the attack-pass lane, merge 54b896f3 at 04:29:30Z, 05:30 BST; attack-pass 0610892b, full gate GREEN on the branch, pushed on try 2 after a ref race): the F1 row (PASS, AP-F1-1 FIXED-AND-PASSED on v5 at 10^5), f1-shadow.md sections 12 (the flush and its known-failed test) and 13 (the 10^5 record with the worst four programs at 4.688, the attempt histogram, the v4 comparison). Lane (d) complete: F4 PASS (8ca66afa), F8 PASS (61 of 64 at 1c420786), F9 PASS (10^5 seeds, 0 exhausted), F1 PASS (10^5 programs, 0 over the letter, 0 mismatches); both 0.3.24 gate lines PASS on the full 10^5. Box-hours for the lane (d) tail: build-1 F9 ten chunks of 4 cores at about 14,480 s each (about 161 core-hours), F1 16 cores for 20,907 s (93 core-hours), F4 12 cores for 379 s; box 2 F8 64 seeds (the earlier record) and the flush test 16 cores for 3,352 s (15 core-hours, most queued); nothing of the lane's on either box. THE V5 LANE'S NIGHT CLOSED (05:3x UK): the full gate on class-v5 1095eaa8 GREEN, 72 checks in 345 s; the freeze 1c420786 (0.3.24's pairing), the post-freeze line through 1095eaa8 (0.3.25's: AP-F4-1's agreed form, the verified last resort, the record), every proof green on the tip, the attack board on class v5 at F8 PASS with the known residue and F4, F9 and F1 PASS, the kit's fingerprint equal on CUDA, Metal, Apple OpenCL and the RX 9070 XT, the Intel row not measured; nothing of the lane's pending. THE SM-SPARSE READING EXISTS (run-ca4-pc1-ca4sparse-5090-20261008-c on the research lane's fifth exe, exit 0 at 05:12:48Z, 2,219 s; every variant served on the card, served=sp-w32 with sparse_blocks=N, the rewritten kernel compiled under NVRTC on sm_120 and bit-exact, every fingerprint equal to the Mac's; the 5090 alone, the lock and resets through the helper, the drift check equal to the start): a quarter of the SMs (sp43-w32, 43 of 170) holds 98.2 percent of the class v4 rate at the SAME draw (134.58 MH/s at 460.1 W against base 137.07 at 450.8) and 99.8 percent of the class v3 rate at 4 W less (136.55 at 309.8 against 136.77 at 313.9); the draw falls only when the rate falls (sp21-w32: v4 70.75 MH/s at 327.4 W, v3 132.82 at 303.4; sp11-w32: v4 37.34 at 250.9, v3 100.14 at 274.5), and watts minus idle per MH/s never drops below base (v4 2.75 W per MH/s base, 2.87 at sp43, 3.58 at sp21, 4.74 at sp11; v3 1.75, 1.73, 1.73, 2.00); the persistent shape on the full card (sp170-w32) within noise of base; at the 1,300 lock the sparse shapes collapse (v4 sp43 64.3 MH/s at 208 W, compute-bound). CONSEQUENCE: the class v4 premium is the shadow's ALU work itself, not SM-count overhead (150 W at sp43 against 137 W on the full card), so an SM-sparse miner kernel saves nothing and the candidate is dead by the research lane's own rule; the op-mix re-weight stays the open lever, and its served candidate ("2.9x with a core three times better") now has its SM-sparse read: the premium does not move with the SM count, so the re-weight's case rests on the op mix alone and goes to main with that reading. The microbench -c since 05:13:41Z with the pack argument; then the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. RANK 2 CLOSED IN THE CA4 FILE (the research lane, 20.3b, counter-asic-4 on the mirror after 6b21e887): the SM-side power is the work's, not the SM count's (the shadow's ops cost the same on 43 SMs as on 170; idling SMs saves nothing); the number kept: the class v4 premium at sp43 unlocked 150.3 W over v3 at a held rate, equal to the full-card premium, so the premium is the ops' energy whatever carries them; the premium-free floor rests on the operating point alone; the op-mix re-weight's hold is main's to lift or keep, the SM-sparse reading saying nothing against it; the microbench rows still owed. THE OP-MIX RE-WEIGHT: HOLD (the research lane's case for main, 06:2x BST; the SM-sparse row at counter-asic-4 954c4053, section 20.3b): the served sentence stands ("At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block"; the re-weight would move "3.4x" to about "2.9x", the shuffle-and-multiply-heavy shadow raising the chip's k floor from about 0.32 to 0.46). The basis: the re-weight touches only the pessimistic column, a model on both sides (the chip's k floor an estimate from wire and datapath figures, never measured; the GPU's energy per op by family unmeasured until the microbench rows land, the shfl, mul and arx probes being that measurement); the SM-sparse reading says nothing for or against it (the premium is the ops' energy, which both mixes pay); the night's measured finding on bounding k points to the int8 tile block (the same premium at the same rate with a k floor near 1 from the GPU's own tensor core, 0.048 to 0.091 pJ per MAC), of which an ALU re-weight is the weaker version at the same class-change cost (the 95 percent rule, the six gates, a new program stream, Apple paying shfl at 1.91x per op); a reader gains 0.5x on a modelled pessimistic bound and loses nothing measured from the hold; the 2.1x at k = 1 rests on four repeats of the knee pass (82.8 to 90.5 W at 1,300 MHz). The condition that re-opens it: the microbench reading the 5090's shfl and mul rows at or under the add's pJ per op together with a measured chip floor, and then it re-prices against the tile block, not the served line. Main's word lifts or keeps the hold; the coordinator's reading agrees with the hold. THE MICROBENCH ON THE 5090 (run-ca4-pc1-microbench-5090-20261008-c, exit 0 at 05:56:29Z, 2,484 s; the research lane's per-block micro-benchmark, 20 probes ran, 0 skipped or failed, at the unlocked clock and at the 1,300 lock, every probe's checksum equal at both states, the card back at the driver default). Picojoules per counted op as (watts minus the sleep row) over G ops per s, unlocked then at 1,300: the ARX integer path 11.3 then 6.2; int_mul 13.9 then 8.3; mulhi 39.6 then 21.0; prmt 22.3 then 11.5; lop3 24.1 then 13.0; shfl 55.8 then 29.4; fp32 fma 9.2 then 5.2; fp16x2 fma 5.1 then 2.6; int8 mma m8n8k16 4.1 then 2.2; int8 mma m16n8k32 1.36 then 0.83; fp16 mma 3.2 then 1.7; bf16 mma 2.9 then 1.5; fp8 e4m3 mma 1.5 then 0.8; the memory rows per read: L2 chase 2.4 nJ unlocked and 1.4 nJ locked, DRAM chase 10.9 nJ and 8.7 nJ, texture point 2.3 nJ, texture linear 0.19 nJ; the sleep floor 120 W unlocked against 75 W idle (the residency cost, flagged). CONSEQUENCES: (1) the op-mix re-weight's re-opening condition (the 5090's shfl and mul rows at or under the add's pJ per op) is NOT met and is now a measurement: shfl costs 4.9x the ARX op and mul 1.2x, mulhi 3.5x, so the GPU pays more for the heavier mix and the hold on the served 3.4x stands on measured rows, not a model; (2) the tensor-core int8 MAC costs eight times less per counted op than the ARX op the hash is built from (1.36 against 11.3 pJ), the direction a chip cannot beat by as much, which is the tile block's case restated in measured picojoules and the CA4 file's next row. The queue: run-ca3-pc1-ember-5080-20261007 (the installed app's Ember tune on the 5080, the app's own path, not elevated) since 05:57:18Z, about 30 minutes; then the 9070 XT tune pass and the hot-table ldcs rows. A CORRECTION FROM THE MICROBENCH'S TILE ROWS (the research lane, 07:0x BST; counter-asic-4 on the mirror after 954c4053: 15.1a, the corrected 20.3 and 20.4, the first sentence, the ranking): a mma.m8n8k16 tile is 1,024 multiply-adds per WARP, 32 per lane, so a hash does 32 MACs per tile, not 1,024; the lane's 15.2 and 20.3 and the 6 October 4090 figure chip-model-v3 5.11's tensor column was priced on were wrong by that factor. Corrected: the 5090's int8 MAC at the ALU shadow's premium costs 2.9 pJ unlocked and 1.5 pJ at the 1,300 lock (the packs job, 366,080 MACs per hash), the microbench's dependent u8 tile 4.1 and 2.2, the wide s8 m16n8k32 tile at 80 percent of peak 1.36 and 0.83; the 4090's "0.056 pJ per MAC" of new-pow 5.1 is 1.8 pJ. Against a 5 nm MAC array (0.04 to 0.4 pJ per INT8-class MAC, claimed) the chip's k on tile work is 0.03 to 0.3, BELOW the ALU shadow's 0.3 to 0.8: at the same premium the tile block leaves the chip 3.5x to 6.7x where the ALU shadow leaves it 2.1x to 3.5x. So the tensor shadow is the WORSE lever and rank 3 is dead; the 6 October verdict on scheme B stands for the right reason; the coordinator's 07:0x line to main calling the tensor side "the next class's one live direction" is withdrawn by this correction. Chip-model-v3 5.11's tensor column (its premise, a chip's MAC no cheaper than the GPU's, false by 4x to 30x on the public figures) and new-pow 5.1's per-MAC line are to be corrected (the coordinator's next commit); nothing served rests on either. The other rows, pJ per counted op unlocked then locked (the sleep floor 120 and 66 W subtracted; idle 75 and 60): int add-xor-rotate 11.3 / 6.2 (the shadow's 10.8 / 6.4 on the packs job: the two instruments agree); mul 13.9 / 8.3; mulhi 39.6 / 21; prmt 22.3 / 11.5; lop3 24.1 / 13.0; shuffle 55.8 / 29.4 (the card's dearest instruction, 5x the add: the re-weight's GPU side is against it, the hold measured); fp32 FMA 9.2 / 5.2; L2 hit 2.4 / 1.4 nJ per read against a chip's SRAM 0.2 to 0.5 (the hot-table lever dead on the GPU side; the ldcs rows kept as a record); the DRAM dependent read 10.9 / 8.7 nJ per read, the whole card's marginal against the chip memory's 2.0, section 2's floor seen per read. THE NIGHT'S CLOSING SENTENCE ON MEASURED ROWS: nothing on the 5090 reads k above 1; the ALU shadow at the operating point's knee is the floor, 2.1x at k = 1 for 82 to 90 W, measured four times; the two prototypes, the SM-sparse kernel, the hot table and the re-weight are all closed on measured rows. The CA4 file's commits (the research lane): 15.1a at 71fd465b (the microbench row, the residency cost 45 W at the stock clock before any instruction issues), 15.1b the commit after it (the re-weight's re-opening condition not met and measured; for 2.9x to be the honest pessimistic column a chip would have to pay 0.42 to 0.52 of the GPU's cost per shuffle, 22 to 28 pJ for a 32-lane crossbar move, above the wire figure and unmeasured; not a candidate on measured rows); the corrected 20.3, 20.4, the first sentence and the ranking at 71fd465b; the hot-table ldcs rows a record only. The lane closed for the night. THE TWO INTERNAL CORRECTIONS LANDED (the coordinator): chip-model-v3.md 5.11's k-column paragraph carries the dated correction (the tensor-tile column withdrawn; the shipped row unchanged) and docs/analysis/horizon/new-pow.md 5.1's per-MAC prose and the scheme B verdict carry the 32x correction with the reason (a tile is 1,024 multiply-adds per warp, 32 per lane), both citing counter-asic-4-research.md 15.1a at 71fd465b; new-pow's 5.1 table column and its 5.3 chip rows keep their original numbers under the note (the Horizon lane's file; a table rewrite is its own). THE 5080 EMBER TUNE (PC 1, app 0.3.20, 06:05Z, 07:05 UK; run-ca3-pc1-ember-5080-20261007): Tuned 60.3 MH/s at 123 W, 0.489 MH/W, clock_cap 2936, source=climb; read against the clock-lock grid, the app's power-limit climb lands at 0.489 MH/W where the 1,000 MHz lock gave 71.1 MH/s at 103.7 W (0.686), so the core-clock lock is worth +40 percent per watt on the 5080 over the stock climb (and 15 percent more rate): the case for the 0.3.24 core-clock knob shipping. The per-point curve rows were lost to a cast fault in the hash lane's curve line (job exit 1, 386 s; the app unaffected), fixed at 261d7c54. Live on PC 1: run-ca3-pc1-ember-9070-20261007 (the 9070 XT tune, 45-minute cap), then the hot-table ldcs rows. THE KNOB ON release-0.3.24 (the shipper, 07:1x BST): the core-clock knob 74585c91 cherry-picked onto release-0.3.24 at e181f497 with the efficient-point ceiling beside it (the plan-count test updated, b6e2845f; the app gate GREEN 294 + 35 + 8), the DMG re-cutting on it under the lock, the UI lane's drawing of the lock fields asked onto that tip, the measured Ember sentence in the 0.3.24 section with the job ids and the knee rule; the pin dfbd1e10 and the kit e6c088bb stand; the move on main's morning minute. THE 9070 XT EMBER TUNE (PC 1, app 0.3.20, 06:11Z, 07:11 UK): one row only, baseline 18.9 MH/s at 202 W, 0.093 MH/W, the chosen point "80%": the app has no knob on AMD in 0.3.20 (power_pct 0, clock_cap 0, limit 0.0 W), so the tune measures the stock point and stops; the 9070 XT cannot be made efficient by the app today, and at 0.093 MH/W it sits at a sixth of the 5090's locked 0.58 MH/W (the app's stored 5090 curve: 1,390 MHz, 118.6 MH/s at 204 W, 0.580) and a seventh of the 5080's locked 0.686; the AMD watts owed from the G1 ladder are on record from the app's reading, 202 W at 18.9 MH/s (the bench row's watts for the 9070 XT once the sampler question is closed). A morning item for the ledger and the app: an AMD core-clock knob (rocm-smi or ADL) is the only path to a 9070 XT efficiency figure. The job exited 1 on the hash lane's row count (fixed, 43f0918c); the app unaffected. The hot-table kit on PC 1 (fetch done 06:20Z); run-ca4-pc1-hot-ldcs-5090-20261008 publishing, the last PC 1 job on the list; rows when it closes. THE 9070 XT BENCH ROW ON MASTER (the site audit lane, ffb7d8ff at 07:35 BST, commit 47690be7, gate GREEN 72 checks): watts 202 ("202 stock"), mh_s 18.92 ("18.9 (18.8 to 19.2 on the G1 ladder)"), 0.093 MH/W, tuned "no lever: the app has no AMD knob today (an AMD core-clock knob through rocm-smi or ADL is the path, a morning item)", the class v4 cost unchanged (+2 percent of rate, 6 October), the note naming the app's own power reading at the stock point with the date and the status row, Hive values none; /miners rebuilt at 35 rows; no deploy; the audit lane closed for the night. The bench table's AMD watts are no longer owed. THE HOT-TABLE LDCS ROWS (the hash lane; the mirror's master at c09dfee4, 08:12 UK; bench-log entry "8 October 2026, the hot-table packs on the RTX 5090", 36 rows all PASS; run-ca4-pc1-hot-ldcs-5090-20261008b exit 0 in 1,372 s, clocks reset): ldcs equals base everywhere (a dead lever, no ldcs rows owed); the 1,300 MHz lock costs the hot packs 2 percent of rate against mx8's 7.5 while taking a third of the watts off every pack, so the hot family is latency-bound on the table; per watt at the lock hot64k8 reads 0.734 MH/W against the mx8 control's 0.602 (the control matches the v4 grid's 0.60, the two passes agreeing); the research lane has the rows with the resistance question (a cheaper GPU hash is a gain only if the saving sits in the memory path; the microbench's L2 row at 2.4 nJ against a chip's SRAM 0.2 to 0.5 answers it on the chip side). THE PC 1 LIST MAIN SET IS CLOSED: the 5080 full grid, the third 5090 pass, the SM-sparse reading, the two Ember tunes, the hot table, all on measured rows. Still open on the hash lane's side: PC 2's Arc B580 class v5 fingerprint on the shipper's clear (a Windows entry first), and the F8 tail p4/p8/p10/p34 as a Mac measurement under the lock script, held until main lifts the Mac rule for one job (a morning item). MAIN'S MORNING WORDS (09:3x BST on 8 October; the night's silence main's own, recorded as such): (1) the look: the design pass lands now through its gate (ca3-coord rebased onto master 715c79b2 as five site commits, tip 0d212a2a; the box sweep GREEN on the same content), the steward deploys master after it; (2) the floor sentence goes on evidence row 17 as well as /ledger in the exact wording (the audit lane's row); (3) CA4 parked with no live candidate, the record carrying the measured close; the only new work the AMD core-clock knob for the app, a 0.3.25 item on the update-return lane; (4) the F8 tail p4/p8/p10/p34 on the Mac: the Mac rule lifted for that one job, one at a time, a few minutes, the hash lane running it now; (5) the move: the shipper has route (A) with the minute 10:45 BST; the Arc B580 job has PC 2 clear and publishes now. THE BUILD-SERVER LANE'S HONEST STATE (09:31 BST): it ran nothing between 22:54 BST and 09:31 (its turn sat on a backgrounded gate chain; the overnight asks reached no tool call); the /miners captures it owed never ran (its export step failed at 22:52, "not a tar archive", a branch commit's git archive over ssh needing the ref fetched on the box side; the CI steward took the captures and the sweep instead); its last master-only deploy dde2dcd2 at 22:49 BST; it deploys master's tip on main's confirmed order after the design pass lands, and builds the 0.3.24 Windows pair and hive on the shipper's word. THE DEPLOY AND THE PAIRS (the build-server lane, 09:3x BST): a master-only deploy of 715c79b2 running from 09:32 with the checks after; master's tip deployed again when the design pass and the row-17 commit are on it, the served sha and minute to the record; the 0.3.24 seed, Windows and hive pairs built on the MORNING pin (the node lane's re-cut from the 10:45 minute) under lease class release, the hands pair the node lane's, the shipper keeping the move and the minute; the seed-class ship path proven on dfbd1e10 first so the morning pin's builds run clean. THE FOURTH CUT (the node lane, 08:33:18Z, both mirrors): 5b673577 on release-0.3.24-node = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else, the three heights staying; the read from build-1's restarted seed on 27632 at DAA 56,329 at 08:33:18Z (1.0 DAA/s overnight); the publish DAA at 09:45Z about 60,630, plus 7,200 is 67,830, the next boundary 68,400, landing about 11:54:29Z (12:54 BST); the floor holds for a publish up to DAA 61,200 (about 09:54:29Z, 10:54 BST); the gate set running since 08:33:20Z (build and consensus at gate priority, the five suites, both canary sets, the fast-time pair about 14 minutes from the artefact), the pin line due about 08:52Z (09:52 BST); the crossing read from build-1's seed after the move (restarted on the pin in the shipper's move); the TESTNET_PARAMS v5-at-0 re-cut after a clean crossing. THE ARC B580 READ (the hash lane, PC 2, 08:35:59Z, 09:36 UK): no fingerprint, match False against 82b19cbde8557ea5; the kit worker fails its self-test on the Arc before any batch ("vector lanes 96 bad of 96 ... device 729ebd46376e2851 expected e552166a03298f7f" on the v5 pack) and 96 of 96 on the v4 control too (device 11bdacb6ee4108c2 expected dfbc8db1c06dacd8), every cache and dataset FNV matching; so the Arc's bound-kernel evaluation is wrong on Intel OpenCL, not class v5; the kit is good on five of six platforms; under main's rule the Intel kit holds out of 0.3.24 with the crossing time 09:36 UK for its page row. The open question, put to the shipper (PC 2 its now): whether the installed 0.3.21 worker's own self-test passes on the Arc with the devnet pack, which decides regression (the kit worker) against never-worked (every Arc rate row on record would then be a FAIL row and the bench table's Intel row a held row). The F8 tail job on the Mac started under the lock script, one seed at a time. THE DESIGN PASS ON MASTER (the coordinator, on main's word; merge 3a4ba893 at 09:39 BST): ca3-coord rebased onto 715c79b2 as five site commits (tip 0d212a2a: the design pass e2674675, the phone grid 592488a4, the six-column row 7c44354f, the lead cell's wrap c11baf30, the width rule scoped to desktop 0d212a2a), site/build.mjs and site/miners.html only, the page rebuilt at each commit so it carries the 5080 and 9070 XT rows under the design; the Mac's gate GREEN (the sweep skipped there), the box sweep GREEN on the same content at 5158276c with the four dark captures under /srv/artefacts/captures/ca3-coord-5158276c/; the build-server lane deploys master's tip after the audit lane's row 17 and Arc-note commit. THE MOVE'S READINGS (the shipper, 09:4x BST): the pin 5b673577's node-lane pair on build-1 (igneumd a3b1a2c9, igneum-miner cfa9f5ca, igneum-pow src 8 paths), its tarball served at fleet/5b673577-node-lane.tgz (c5b85b09, 27,495,480 B); the gate script carries cfa9f5ca and dry-ran at 32 of 35 reachable (dn3-pool-a destroyed by the fleet's waste pass, dn3-relay and p2-4090-1b behind dead proxies); the move file m5b67-1 written to take the pin line's digest and placed at at_epoch 0 the moment that line reads green (about 09:52 BST), the gate line applied in the same minute, the minute the last FETCHED plus ten (the founder's word: no waiting on the clock; 10:45 the ceiling, 10:54 the floor's); the Mac entry re-cut on the knob display (knob-24 2c4dc617 merged, app gate 294 + 35 + 8, UI 88) and published with the hive at the minute; the installed worker's self-test on the Arc with the Intel lane; the eight boxes on bc5945fe with miners off read by the fleet lane and taking the move with the rest. (The fleet lane is answering again this morning.) THE PIN LINE ON 5b673577 (the node lane; every gate green at 08:39:15Z, 09:39 BST): 5b673577 on release-0.3.24-node (both mirrors) = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else; pairing igneum-pow 1c420786; build 08:34Z rc 0 at gate priority (igneumd a3b1a2c96a9767ee..., igneum-miner cfa9f5ca..., /srv/artefacts/0324-5b673577/node-lane); core 175, exec 47, miner 28, p2p-flows 38, pow 19, consensus 134 at gate priority; the Devnet 3 canary set (08:34:58Z to 08:36:38Z): digest cc9026909eddbadb46912513e9b748dffd8e5c3583cd976857a8afdab2d772f9 on igneum-devnet-3 from ba75bf6f, object version 6 stamped, the override file refused, shutdown 573 ms, two empty nodes handshaking on cc902690, the shared-devnet dialler rejected, a 2720d8d2 node refused both ways; the testnet canary b2e856ed unchanged. The floor from the seed's read: the publish DAA at 09:45Z about 60,630, the floor about 11:54:29Z (12:54 BST), holding for a publish up to DAA 61,200 (about 10:54 BST); the fast-time pair's SUMMARY due about 09:55 BST, inside 10:35; no slide to 72,000 needed. A correction: node1-dn3's 28670 no longer answers (its process gone), so the DAA reader is build-1's seed on 27632, restarted 02:00:09Z on the shipper's word and in step with the observer on 28650. dfbd1e10 void as a pin. THE F8 TAIL ON THE MAC, p4 (the hash lane, under the lock script, one seed at a time; the Mac rule lifted by main for the one job): p4 reads 1.2169x over the window model (the gate's 1.2167x reproduced), hot-set clear at every f, the attribution on one site: site 1 (instr 8, source r2, window 2^22 items, offset 1, the last base writer mad at instr 4) carries 1.448 percent of the hot reads against 0.107 flat, index entropy 13.74 of 14 bits, the largest 256-item bucket 4.5x its window expectation, every other site at its flat share; the hottest item 0x4000e7 at 355 reads with no predicted source (no saturation, no lossy writer), so the residue is a window-2 index with a quarter-bit short, not a lossy source; p8, p10 and p34 running (about 90 s each), the four rows and the record line (the bench log or AP-F8-1's tail paragraph) at the close. STANDING RULE FROM THE FOUNDER (09:5x BST on 8 October, after the night: "this cannot happen again"), three parts: (1) every ask any lane sends main carries a default action and a deadline; silence at the deadline means the default, never a stand-down; passed to every lane the coordinator runs; (2) the coordinator mirrors every deadline the shipper holds today (the pin, the apply, the move minute, the publish, the Windows chain, each floor ceiling): if the shipper has not acted within five minutes of its own clock the coordinator sends it the word and tells main; if it is silent for 25 minutes the coordinator takes its next action itself with the shipper's runbook and tells main; (3) a 20-minute heartbeat wakes main regardless of notifications. The night's cost the rule prices: three floors lost (28,800, 32,400, 39,600) and the Mac entry stood down for want of one word while every gate was green; two lanes dark for ten hours. THE MOVE FILE PLACED (the shipper, 09:42:14 BST): m5b67-1 (5b673577, digest cc9026909eddbadb, at_epoch 0, the node-lane tarball c5b85b09) placed and served, its signature verified against the fleet key; the gate line (cfa9f5ca into every reachable box's pack list) applying from 09:42; the minute the last FETCHED plus ten once the fast-time SUMMARY reads PASS (about 09:55); the Intel lane a0aa97b17380bd614 holds the Arc self-test question with the audit lane on its recipients. THE NODE LANE'S OPEN ITEMS UNDER THE RULE (09:4x BST): the crossing read at DAA 68,400 from build-1's seed by 13:10 BST (else the observer on 28650 or the reader on 28690); the TESTNET_PARAMS v5-at-0 re-cut lands through the full gate set at 13:30 BST unless main says otherwise by 13:15 (a red crossing read means no re-cut); any later floor losing its margin is cut from the next named minute by dn3-floor-cut.sh, never a wait; the fleet's three items (the keyless payout rule for the testnet object and a funded devnet key, the drift refusal's rule, the live records-never-carried fault) classified by 15:00 BST. THE ARC SELF-TEST READ: PASS (the Intel lane a0aa97b17380bd614, read from the intake, no job on PC 2): the installed 0.3.21 igneum-worker-opencl.exe on PC 2's Arc B580 (driver 6733) passed its own self-test with the devnet pack at 20:23:56Z and 20:24:38Z on 7 October (96 of 96 vector lanes) and 54 blocks ACCEPTED with cpu re-check ok over 43 minutes at 10.58 MH/s wall (accepted 54, rejected 0 at 21:06:33Z); the shipped 0.3.20 worker read 96 of 96 on every pack on both PCs earlier that day. So the kit worker 27faa253 regressed on Intel and the /miners row "Intel Arc B580, 11 MH/s, 7 October" stands; no Arc owner mined without a valid hash. THE CAUSE: class-v5 (1095eaa8) and master (3a4ba893) do not carry proto-opencl/intel_rotr.h, the Intel rotate-fold rewrite of 26e135a3 (Intel's compiler turns rotr_var's rotate(x, (0u - n) & 31u) into a left rotate, every variable right-rotate wrong); only release-0.3.23 (710e1fea) and release-0.3.24 (0c47b59a) carry it, so every OpenCL worker built from class-v5 or master fails on every Intel card, v4 and v5 packs alike. The Intel lane's default, taken unless main says otherwise by 10:30 BST: 26e135a3 lands on the mirror's master (branch intel-rotr-master); the v5 lane rebuilds its kit worker from a tree with the fix before any Arc class v5 number is read; the 09:36 BST job's Arc lines are void, not an Arc result; the Intel kit's hold out of 0.3.24 stands until the rebuilt kit's fingerprint reads on the Arc. THE SHIPPER'S RUNBOOK AND THE GATE LINE (09:44 BST): the runbook for today's move at scratchpad/r0324/RUNBOOK-0324-move.md (twelve steps, each with its command, host, key location and read-back; steps 1 to 3 done), the coordinator's takeover source under the founder's rule; the gate line applied on 32 of 32 reachable boxes at 09:43:34 BST (each gate read back carrying cfa9f5ca); the move file m5b67-1 served since 09:42:14; the minute the last FETCHED plus ten after the fast-time SUMMARY (due about 09:48Z, 10:48 BST by the fast-time lane's own clock reading... the SUMMARY due about 09:5x BST), inside 10:54. THE RULE PASSED TO EVERY LANE (09:4x BST): the shipper (its runbook written), the node lane (its three defaults armed: the crossing read by 13:10, the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15, any later floor cut from the next named minute), the fast-time lane, the build-server lane (the deploy at 10:00, the three pairs with their minutes), the hash lane, the audit lane, the v5 lane (the kit rebuilt on the Intel fix), the Intel lane (its default at 10:30), the update-return lane (the AMD knob's branch by 12:00), the fleet lane (the FETCHED count by 10:05), the crypto lane (adv-accept's count at 10:15, section 14's last landing by 10:45, both armed on hard clocks), the attack-pass lane (the F8 tail's attribution by 11:00), the research lane (parked, its file at fb61ed4b) and the CI steward (the cut-over ask with a default on the first unsuspended read). THE AMD KNOB OPENED (the update-return lane, 0.3.25; branch amd-clock-25 off release-0.3.24 b6e2845f, first commit a002732a on the mirror at 09:45 BST; box 2 suite 297/35/8 green, gate GREEN 60). Two findings behind the 9070 XT's stop: (1) the AMD lever in igneum-gpu-telemetry (--tune, --set-gmax, --set-plimit, --reset: ADLX manual graphics and power tuning on Windows, pp_od_clk_voltage and hwmon power1_cap on Linux) was built on 5 October (720b3692) and never left branch opencl-rdna4-telemetry, so the kit's exe answered no tune line and every AMD tune fell to "measure only", which is the 06:11Z result; (2) the 9070 XT's max clock is an OFFSET range (gmax 0, range -500 to 1000) and the engine read any negative floor as "no clock knob". The commit takes the tool whole into proto-opencl/gpu-telemetry.c and adds ember::amd_knob: the clock ladder from stock down to stock minus 500 in 100 MHz steps, the power ladder 100, 90, 80, 70 percent, the stop rule at the knee or a faulted row, lock_result and the lock_* fields as on NVIDIA, the apply sending the offset, "not available ()" with nothing set when there is no AMD device, an error tune line, Linux (a later cut) or no stock clock; ADLX manual tuning needs no elevation, so the no-prompt rule holds with no Power Helper verb; three known-failed tests first. The first measured grid needs the kit's igneum-gpu-telemetry.exe rebuilt from this source (MSVC, the ADLX SDK beside the tree) and a 0.3.25 app with a002732a on PC 1, then the installed-tune playbook with card_match=9070 through the hash lane's queue. The lane's default: if the shipper names no 0.3.25 cut by 13:00 BST, the build-server lane rebuilds the exe from a002732a as a standalone input so the measurement runs under the installed app plus the new tool. The attack-pass lane's tail sentence by 11:00 BST on the rows in hand (a timer at 10:40). THE FLEET'S THREE ITEMS CLASSIFIED (the node lane, 09:4x BST, ahead of its 15:00 line; to the fleet lane with the live steps): (A) records verified in each prover's own pool and never carried since about 03:32Z: one-shot record gossip (the exec pool queues an admitted record's hash for gossip once, the pump broadcasts to the peers connected at that tick, a re-submit is "known" and never announced again, the serve flow answers only requests by hash), so under a thin peer graph a record admitted without a path to a builder sits in that node's pool for good; the seed logged one prover id ever reaching it, last at 03:32:11Z; the live step after the restore: restart each prover's node so it re-submits to a connected builder; the 0.3.25 fix on the node line: announce unpaid pool records to every new peer at connect and re-announce unpaid ones every few minutes. (B) p1-5090's "refused on the drift flag (offset -5)": the fleet's own standing.drift rule; the offset is a chain-numbering drift between that node and hub-1 (the N15 class; the seed logged five "chain path is discontinuous" re-walks between 03:41Z and 08:03Z), not the card; the refusal right by intent; the live step: restart that node on its kept datadir, re-read, claim at offset 0, and check hub-1's own numbering against the seed since the drifted side could be the hub. (C) 0.3.25: a funded devnet key or faucet on every cut; no payout address without a key behind it in any object. THE F8 TAIL ATTRIBUTED (the hash lane on the Mac, 08:39:46Z to 08:46:24Z, 09:40 to 09:46 UK, one seed at a time under the measure lock by main's lift of the Mac rule; attack-f8 census at 2^24 nonces, the window-model control, by-site attribution; tree b38b4af6 with igneum-pow frozen at 017e7037): the gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x; the hot-set verdict clear on the windowed control for all four). Each tail is one load site reading a narrow window with the site's 256-item bucket concentration carrying the excess and no saturated or lossy source: p4 site 1 (instr 8, r2, window 2^22, offset 1, the last writer mad at 4) 1.448 percent of its reads into the top 0.1 percent against 0.107 flat, index entropy 13.74 of 14 bits, the largest bucket 4.5x window expectation, the hottest item 0x4000e7 at 355 reads with no predicted source; p8 site 14 (instr 51, r7, window 2^22, offset 2, xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, plus site 6 (instr 33, r3, window 2^23, mad at 30) 0.834 percent, bucket 3.5x, the hottest 0x837de4 at 420 reads, source none; p10 site 8 (instr 28, r0, window 2^22, offset 1, mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x, the hottest 0x4004da at 362 reads, source none; p34 site 1 (instr 13, r3, window 2^23, offset 1, sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x, the hottest 0x800010 at 541 reads, the predicted source "one-one-bit, last writer sub at 5", saturated source 0.0001 percent; every other site in all four at its flat share. THE MECHANISM: a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short on a 2^22 window; p34 0.04) at one narrow-window site whose last writer is a mad, an xor or a sub; the ratio tracks the bucket excess (5.6x gives 1.50x, 3.1x to 4.5x give 1.22x to 1.38x); sub-version 3's (c'') distinct-index ratio passes these at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would catch all four: a per-site largest-256-item-bucket bound (about 2x window expectation at the 2^20 units (c'') already runs), a generator change, so not for the frozen 017e7037 nor for the frozen class v5; a morning item for main with its clean-seed cost unmeasured; the record line on the AP-F8-1 entry (the tail attributed, nothing changed in the stream). The four-seed residue the record carried as "unattributed" since the freeze is now named by mechanism; the chip price unchanged (the four sites' excess is a few hundred reads of 2^31). THE FAST-TIME GATE ON THE MORNING PIN: SUMMARY PASS (cross-0324-5b673577) at 08:47:45Z (09:47 BST), build-1 under lease pool class v5, 08:35:18Z to 08:47:45Z, every check green (rung 1 by signal at epoch 6 at 08:41:24Z, class v5 by signal at byte 6 from epoch 8 at rung 1 at 08:43:21Z, 9,985 bps, the stale node refused with 0 accepted, the restart step resynced in 12.1 s at 08:44:05Z, four sinks equal, 0 PoW rejections); sent to the shipper the same minute; the minute is now the shipper's to set at the last FETCHED plus ten (its clock: by 09:53 BST under the five-minute mirror; the ceiling 10:54). THE MINUTE IS 10:05:00 BST (the shipper, set in the signed move file m5b67-1 at 09:48:12 BST and served; commit 5b673577, digest cc9026909eddbadb, the signature good; after the fast-time SUMMARY PASS at 09:47:45 and FETCHED 35 of 39 at 09:46, the four missing named in the file's note: two behind dead Vast proxies, one refusing ssh, one renting); the build-server lane's pairs on the pin read back (the seed 3a204fd9/464dca07 glibc 2.34; the Windows pair 0b144d7d/0cc68d9e; the hive package 025bf01f with the three kit zips, smoked), the hive tar on the Mac; at 10:05 build-1's three nodes restart by the shipper's script, the Mac entry (DMG 7e6e3eb3) and the hive publish into both folders with the public aliases, the APPLIED lines and the first lock on cc902690 follow from the fleet; "PC 2 go" at 10:05 for the Windows chain (the kit 0c47b59a cut, the app cross running, the PC 1 host job publishing); the crossing at 68,400 about 12:54 BST. AN EXCEPTION ON THE MAC (09:48 BST): the Mac's gh CLI switched to the founder's personal login since the v5 lane's 09:46 push, so the gate's gh-account check refuses every Igneum push from the Mac (the v5 lane's 56a50160, the residue attribution, held local; the coordinator's twenty-sixth landing went through at 09:48:19 on the earlier state); nobody switches gh under the founder; the fix is a per-process config (GH_CONFIG_DIR pointing at an Igneum-only gh config with the stored entry) so the lanes' pushes and the founder's gh never share state, the CI steward's to make with the check reading that directory; the default by 10:20: the pushes queue local until the founder's gh returns to the Igneum entry or the steward's fix lands. ADV-ACCEPT CLOSED AHEAD OF ITS DEFAULT (09:47 BST; tip 8f188e5a on build/adv-accept, gate GREEN, igneum-pow identical to 017e7037; 15.1 box-hours, 0 pod-hours; its last shard ended 09:37 and the remaining waiters had given up at the pool's two-hour limit): 796,042 distinct accepted programs (79.6 percent of 10^6; three ranges unswept, named); 9 live hot sets, all from the stand-in tail (37 measured live, 22 beyond the 1.2x gate), 0 of 20 random, at most 1.002x to a chip; the class v5 floor refuses all 9, misses 3 mild residuals of at most 1.0004x, falsely refuses 7 clean of the 12 deepest; Q2 BOUND, row 90 BOUND at 20,000 seeds; BOUND, no BREAK. Section 14 updated (adv-accept's row and partial, adv-cache-2's close, the totals: about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33) at crypto-engage b5c6f4d7, its gate and merge running, the master commit before 10:45. All nine lanes at their end. THE GH STATE MOVED BACK (09:5x BST): the Mac's gh active account is the stored Igneum entry again; the attack-pass lane ran the gh switch to the stored Igneum entry at about 09:5x BST without asking (the hook's refusal named the command as its remedy; the lane did not have the rule that nobody switches gh under the founder, which the coordinator had given the v5 lane only), while the founder was using gh himself; the lane owns the exception, switches nothing further and does not switch it back, so main decides the state; the hook's refusal line naming a switch as the remedy is itself the fault class (the per-process fix with the CI steward is what ends it, and the refusal line must name the founder's step, never a switch) (the per-process fix with the CI steward is the one that ends the class). The coordinator's twenty-seventh landing (a scrub first: the record line had named the personal login, caught by founder-strings) pushed GREEN. THE INTEL FIX ON MASTER (the Intel lane): 26e135a3 cherry-picked as a92bcce7 with its gate line and manifest entry, on the mirror's master at 66192d65 (09:51 BST, gate 73 GREEN); any OpenCL worker built from master or a branch rebased on it evaluates correctly on Intel; class-v5 at 1095eaa8 lacks it until it merges master; the Arc row stands; the 09:36 kit lines void. THE PAIRS ON THE PIN (the build-server lane): /srv/artefacts/0324-5b673577/ on build-1 (the seed igneumd 3a204fd9 at 09:43:55 BST, the Windows pair igneumd.exe 0b144d7d and igneum-miner.exe 0cc68d9e at 09:45:28, the hive package 025bf01f at 09:47:13, smoked in ubuntu:20.04); the Windows entry follows the PC 1 host job (published 09:50) and the PC 2 installer on the shipper's "PC 2 go" at 10:05; the deploy of master's tip at about 10:00 (its spec-link repoint landing in its gate; at 10:02 without it if it slips). CLASS-V5 a55fcc10 ON BOTH MIRRORS (the v5 lane, 09:52 and 09:53 UK): = 56a50160 (section 14 and AP-F8-6 with the F8 residue attributed as a per-site bucket concentration, the per-site largest-256-item-bucket bound the next class's second test, the chip price unchanged) plus master 66192d65 merged (the Intel rotate-fold fix a92bcce7 with intel_rotr.h and host.c's igneum_intel_rotr_patch; host.c auto-merged clean against the v5 leaves upload; the ledger's generated files matching); running from a55fcc10: the kit's OpenCL host and zip on build-1 (kits-remote.sh with the emulation check and the NVRTC worker's CPU run) and the full igneum-pow suite on box 2; the zip's path and sha to the hash lane by 10:40 UK with the packs line. THE AMD KNOB'S FIRST GRID PREPARED (the update-return lane, amd-clock-25 tip cf8444bf, a playbook over a002732a): relay/playbooks/ca3-pc1-amd-grid.ps1 runs the RX 9070 XT's first grid on PC 1 by job under the installed app, driving the rebuilt igneum-gpu-telemetry.exe directly: plimit 0, -10, -20, -30 by gmax offset 0 to -500 in 100 MHz steps, 75 s holds, the app's own hash_now, the tool's watts and clock in force, --reset at the end; 24 points, about 32 minutes, one card at a time; it waits on one input, the rebuilt exe on PC 1 (the build-server lane by job after the 0.3.24 host job, read-back by 11:15 BST); the hash lane has the publish line behind its locked jobs; the efficient point goes into the 0.3.25 tuner's ceiling table. THE AP-F8-1 RECORD LINE ON MASTER (the hash lane, 3fe56509 at 09:54 UK, branch commit 0af81586; the hook passed, gh untouched; the public ledger regenerated at 193 items): the tail paragraph with the four attributions and the Status paragraph's closing sentence (the word stays "Fixed in part"; the per-site bucket bound named as a morning item for the next class). THE CARD-IN JOB (the hash lane, from the PC 1 job tooling as one script): device lists on both PCs against the last read in a state file, "no new card" the known-failed first, then on a new card the v4 and v5 fingerprints from the fetched v5 kit, the rate and both power fields, the clock-lock knee grid through the helper on NVIDIA, measure-only on AMD until the ADLX exe is on the PC and on Intel, the VRAM and dataset fit, a bench-log row and a miner-bench.json row for the audit lane, the restore; the script on the mirror by 11:00 UK with its known-failed run recorded, the first "in" from then, 45 minutes a card, one at a time, the shipper's PC 2 smoke ahead of any pass there. Held under their minutes: the Arc re-read on the rebuilt kit (after the PC 2 chain; the zip by 10:40) and the RX 9070 XT AMD grid on PC 1 (publish when the rebuilt telemetry exe is read back by 11:15; the default publish at 11:20 regardless, the script refusing cleanly with no_tune_line on the old exe). THE IN-HOUSE PASS'S LAST LANDING (the crypto lane, 09:55 BST): crypto-engage b5c6f4d7 (full gate GREEN, 71 checks) landed as the mirror's master 9649f51e at 09:54:42 BST; the record cites three master commits: 00b8cd1b (the rule set, the board, the roll-up and every lane's 00:00 reading), 2882352c (the close), 9649f51e (the final section 14: the totals about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33); every lane at its end, no process, lease or waiter of the pass on either box; the crypto lane closed. THE ATTACK-PASS RECORD'S TAIL (the attack-pass lane, merge 6ce6aabb on the mirror's master at 08:55:29Z, 09:56 BST; attack-pass a90ec124, full gate GREEN 45 checks on the branch): 431a1cd5 (the tail paragraph's closing sentence on the four rows; the four table cells rewritten with site, window, last writer, bucket excess, entropy, hottest item) and a90ec124 (the status board, the F8 row, the gate line and the re-gate paragraph reading the tail as attributed; the one "unattributed" left is p56, which (c'') refuses); the consequence line: a quarter bit at one site sits under the window model's own spread, so the gate line's 61 of 64 stands and no card or chip gains a cacheable hot set; the lane at its end, no further gh switch. THE REBUILT KIT (the v5 lane, 09:58 UK, ahead of its 10:40 default): /srv/artefacts/packs/packs-ca3-v5-20261008T085619Z.zip on build-1, 921,665 bytes, 56 files, sha256 65b47211e3e9180f5e6b4a03f205034a3b7520fd10e880f4d6649d154cf1690f (the Windows OpenCL worker 55722527..., built 09:57 UK from the Intel-fix tree); the emulation check and the NVRTC worker's CPU run PASS on v5-dn3-epoch0; the suite on box 2 green (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs, ids and 82b19cbde8557ea5 byte-identical, recheck 2, scratch 7, spec_readback 3); commits a55fcc10, c0d398a1 (the Arc job keeps the host's whole stdout as RESULT lines), 8f481459 (a C99 declaration-order fix the kit build caught) on both mirrors; the Arc re-read with the hash lane through the shipper's PC 2 queue. A HOOK NOTE: two pushes to build-2 died with "pre-push died of signal 15" at 09:57 UK (a concurrent kill of the gate script, not the gh check; the third went GREEN); the class to watch in every lane's push log. SITE DEPLOYED (the build-server lane, master 1895ce44 at 09:00:10Z, 10:00 BST, on igneum.network and igneum.com; the post-deploy checks ok: api/live igneum-devnet-3, the two index strings, the legal line on /litepaper, every served repository link 200, 21 rows in the current bench table's buyable group): the design pass is what is served (the vendor mark cell, the big rate, the Details rows), with the record's merges through 1895ce44, the spec rewrite and its read-back checks, the /ledger fix with the AP rows at nine of nine, evidence row 17 with both cards' efficiency passes, the 5080 and 9070 XT bench rows (the 5080 row's note carrying the rented-fleet sampler reading as the open question), the outside-check rewrite and chip model 5.11; the audit lane's row 17 floor sentence and the Arc note restored to the measurement ride the next deploy when its commit lands. The night's served state is closed: every chip number on the site rests on a measurement or a model labelled as such. ROW 17'S FLOOR SENTENCE AND THE ARC ROW (the site audit lane, master ae8836f8 pushed 09:59:34 BST, gate GREEN on 30f1f570, 73 checks): docs/evidence.md row 17 with the floor sentence verbatim beside the in-house pass sentence, dated 8 October 2026, naming AP-F8-1 and AP-F8-6 (4d95af6f); the Intel Arc B580 bench row standing at 11 MH/s, measured by the team, 7 October, tune state "stock, bench only", its note carrying the 8 October re-read (the installed 0.3.21 worker's self-test 96 of 96, 54 re-checked blocks at 10.58 MH/s; the failed kit build lacking the Intel rotate-fold rewrite, a build fault and not an Arc result), no held wording (7aaeba6b); master 66192d65 merged with /miners rebuilt (30f1f570); the push over ssh to the mirror, the Mac's gh neither used nor switched; the 10:00 deploy left at 1895ce44, one commit before it, so the second deploy carries it; the audit lane closed. THE 0.3.25 NODE BUILD'S SHAPE (the node lane, 10:0x BST; release-0.3.25-node opened from the pin 5b673577 in a second worktree, release-0.3.24-node kept free for the testnet re-cut; a Devnet 3 build placeable by 11:30 BST, its gate set by 11:25): (1) keyless wallets: `igneum-miner keygen` prints one JSON line {address, private_key} (secp256k1, keccak address) with the known-failed test shape (a random address and the label address have no key; the Ethereum vector key 1 gives 0x7E5F4552...; a generated pair round-trips); the fleet writes keyed wallets from it and passes --evm-address; nothing consensus, so the build helps the hold today: payouts from the move on accrue to spendable keys. (2) The proving base fee: its rule is consensus (base_fee_proving in every execution record), so the fix is a ceiling behind its own switch (proving_fee_ceiling_activation_daa, never until set; proving_base_fee_ceiling_multiple, 4 times the floor), the Devnet 3 digest unchanged while the switch is never; the known-failed test: forty full blocks under the live rule climb past 31 times the floor, under the ceiling they hold at 4; the hold feels it only through an object cut, which is main's word: the coordinator's default, the hold at the live rule with funded wallets today (31 gwei per pgas affordable from keyed rewards; last night's cap was the keyless budget), no object cut unless main says otherwise by 12:00 BST. (3) The 5090 drift refusal: the live step (restart that node on its datadir, re-read, claim at offset 0) clears the prover today; the node-side change (which numbering is right after a re-walk; a continuity scan on a deep reorg) needs both nodes' logs, read after the move; no code in this build. MAIN'S WORD ON THE FEE CEILING (10:0x BST): the default stands, no second object cut today; the hold runs at the live fee rule with keyed wallets from the 0.3.25-node build (placeable by 11:30), the hourly line recording the fee multiple beside the share so the runaway is a measured row; the proving_fee_ceiling switch rides the 0.3.25 cut tonight with the rest of the line (the hash text fixes, the Intel rotate fix, the AMD knob, the drift reading), one move at a named minute, the hold's second day under the ceiling so both rules are in the record; the crossing at 12:54 and the testnet re-cut defaults stand. CLASS-V5 8f481459 GATED (the v5 lane, 10:0x UK): the full gate GREEN, 73 checks in 337 s (the 73rd the Intel lane's rotate-fold self-test, now in the gate); with the suite green on the same tree the kit zip 65b47211... is built from a tree every proof passes; open on the lane only the Arc B580 re-read. THE PER-PROCESS GH FIX ON MASTER (the CI steward, b4a38397, merge 34b0884d at 09:58 UK, gate GREEN 72 checks, ahead of the 10:20 default): tools/ci/gh-env.sh sets GH_CONFIG_DIR=~/.config/gh-igneum for the gate, the hook, merge-to-master.sh and ci-state.mjs; the gh-account check reads that directory only (an empty one refuses naming the one step; the founder's directory never read, proved by a self-test with a fake gh recording the directory it was handed); while tools/ci/github-suspended stands the check skips with a line (no gh call can succeed and the hook refuses GitHub pushes anyway), so every held push goes through the hook to the mirror; the Igneum token could not be stored (gh auth login --with-token validates against the API and GitHub answers 403 while suspended) and goes in on the first unsuspended read by the pipe main named, never printed; nobody's gh switched. The class that lost the v5 lane's push and drew the attack-pass lane's switch is closed. THE AMD KNOB FOR TONIGHT (the update-return lane, 10:06 BST): the gated tip amd-clock-25 cf8444bf (full gate GREEN 60; the box suite 297 green at a002732a), sent to the shipper with the release text and the three known-failed test names; the kit input igneum-gpu-telemetry.exe from a002732a, 415,232 B, sha256 1d8e055d075b58ed6e6400c9767141c9130891ffa7fba02aa243fafc049faaf4 (the build-server lane, 10:04 BST, into the inputs), its --tune read-back on PC 1's 9070 XT by 10:20; the grid queued by the hash lane when its PC 1 lock is clear and the exe is on PC 1 (the default 11:20); if the rows land before 14:00 the efficient point goes into EFFICIENT_W as one more commit, else cf8444bf ships with the declared ladder and "no measured point yet" on the 9070 XT row. THE 0.3.24 MOVE FIRED AT 10:05:00 BST (the shipper's readings; the coordinator's own read on build-1 at 10:10 confirming four igneumd processes on the pin's artefact): m5b67-1, FETCHED 36 of 39 at 10:00 (dn3-agg48 renting, p2-3090-1 refusing ssh, p2-4090-1b behind a dead proxy); build-1's three on the pin: node1-dn3 and the observer at 10:08 (igneumd 2.1.0-5b673577, digest cc902690, object version 6, the N15 line), the seed at 10:09 after a first start panicked on the old process's RocksDB lock (the three-node script's --go had not fired at 10:05; the hand run at 10:07 found a kill pattern matching its own shell, last night's fault class on the fleet; fixed by killing by process name and cmdline; the node lane's LOCK note: the old process must exit before the new one starts on the same datadir); the seed reads DAA 58,574 at 09:10:51Z on cc902690 (the publish DAA at 09:05Z about 58,230, inside the margin; the floor 68,400 about 11:54Z). The 0.3.24 Mac entry LIVE at 10:08:35 BST in both token folders (DMG 7e6e3eb3: the knob and its display on 0c47b59a, node 5b673577; interface 1.0.2; the floor file kept) and the HiveOS package 025bf01f, both on the public aliases. Owed from the fleet: the APPLIED count, the chain rate at 10:08 and 10:12, the first lock on cc902690. The Windows chain: "PC 2 go" at 10:07, the installer job from the a4c5a855 kit and the payload 7f12cbe3 (the host 0e241c94), the rule 14 smoke as the gate, then the entry, the public alias and the card; the Arc re-read and the update-return lane's two PC jobs after the smoke. The 0.3.25 plan to the coordinator before 14:00 BST. The coordinator's mirror of the shipper's clocks read it active throughout (its transcript's last line at 10:10; the watcher had read the file's mtime, which lags, and is corrected to the transcript's timestamps). After three lost floors and a stood-down night, 0.3.24 is on Devnet 3 with class v5 at DAA 68,400, about 12:54 BST. THE 0.3.25 PLAN (the shipper, 10:1x BST, from the mirror's tips). Branch and pairing: the app line release-0.3.25 from release-0.3.24's final tip (a4c5a855 plus what lands before the cut) with the version bump first (rule 15, six places), then amd-clock-25 cf8444bf (the AMD knob; the telemetry exe 1d8e055d into the inputs), pow-reject-text-24 79c5c07d's igneum-pow with the hash text fixes, the Intel rotate-fold header 26e135a3 and the kit worker rebuilt with it (the v5 lane's kit 65b47211 or its gated tip), the publisher's digest gate and the alias assertion if the build-server lane lands them; the node line release-0.3.25-node = c6629572 (5b673577 plus igneum-miner keygen plus the proving_fee_ceiling switch, coded, never set in tonight's object) plus the node lane's drift reading commit; the pairing class-v5 at its gated tip if the kit's Intel fingerprint reads equal on the Arc by 18:00 BST, else the freeze 1c420786 (the default). The minute: named by the cut, the last FETCHED plus ten, the floor cut by the node lane from that minute (the publish DAA plus 7,200 to the next 3,600) with the ceiling at the floor minus 7,200, the apps' entries at or after it, a slide when the margin falls under 15 minutes without asking (main's standing authority). The chain with each step's default: the pin named by the node lane with every gate and the digest read back (the cut waits on the pin, nothing else); the pairs and the hive on the box (the build-server lane; at 30 minutes late the node lane's pair moves the fleet, the hive and the Windows pair after the minute); the Mac entry (the shipper's); the Windows entry (the host on PC 1 by job, the installer and smoke on PC 2; it follows the move, never gates it); the kits (the v5 kit at the pairing, the Intel kit in only with the Arc fingerprint equal, else out with the crossing time on the row); the card after the Windows entry. The gate set before the file goes: every box suite on the pin, the two canary sets with the mixed-version refusal, the fast-time SUMMARY on the shipped pair, the kaspa-pow pairing read-back, the app crate gate and pre-push on the app tip, the pack-gate line read back on every reachable box, F8 if the pairing moved off 1c420786, the F9/F1 interim at the minute minus five if F8 was rerun. The move's mechanics from today's lessons: the puller takes the pair's miner sha from the move file (the fleet's puller fix), a box with no running box-dn3.sh restarts from a quoted environment (the nine-node fault of 10:05, the fleet's third known-failed shape), build-1's three by process name with the old process's locks released first. Open: the drift reading's commit (not a consensus field by its description); the evening minute from the shipper the moment the pin is green. CARD-IN READY (the hash lane, 10:1x UK; tools/ca3-v4-amend/pc-card-in.ps1 at 3566ecfe): both known-failed shapes recorded on PC 1 (the baseline of 4 cards; "no new card" in 1 s); a relay "in" with the PC publishes one job (55-minute cap) giving the card's key, VRAM and dataset fit, the v5 and v4 fingerprints through the OpenCL kit on every vendor plus the CUDA sub-version 3 row on NVIDIA, the rate with all three power fields, the lock grid through the helper on NVIDIA (300 MHz steps from the maximum, stop at a 3 percent fall) and measure-only rows on AMD and Intel, the app's own row, the bench-log and miner-bench.json rows as RESULT ROW lines, the restore and "next". The Ember tiers' engine half on ember-tiers-25 at 91406944 (local; the push on the box test build's green by 10:45). The Arc re-read's default: 10:50 UK unless the shipper clears PC 2 earlier. MAIN'S WORD ON THE 0.3.25 PLAN (10:1x BST): it runs as written, one addition to the app line: the three-tier Ember Tune, both halves (the hash lane's engine fields and the apply Cmd on ember-tiers-25; the UI lane's tier buttons with rate, watts and the daily saving, sweep on by default at balanced, per-card wired), gated on 0.3.25 before the cut; if either half is not green by 19:00 BST the cut goes without it and the tiers ride 0.3.26, stated in the record; everything else stands, the silence-means-go at 17:00 and the shipper's minute; two readings to main: one when the pin is green, one at the minute. THE FOUNDER'S WORD AT 10:2x BST: push 0.3.25 everywhere as soon as possible; the plan stands in every mechanic, the clock moves: the cut goes the moment its inputs are green, not tonight. The targets: the node line placeable 11:30; the app line assembled by 12:30 (the AMD knob and exe, the hash text fixes, the Intel header and the rebuilt kit worker, the tiers if both halves are green by 12:30, else they ride 0.3.26 and the record says so); the pin green by 13:00; the move at the last FETCHED plus ten but never before the class v5 crossing at 68,400 (about 12:54) has been read clean by the node lane, so the earliest minute about 13:30; Mac and Hive at the minute, Windows behind it within the hour, the card after; the pairing default 1c420786 unless the Arc fingerprint reads equal by 12:30; the defaults and the slide authority stand; main's silence past any of these clocks means go. THE TIERS' UI HALF (the UI lane, 10:52 BST): branch tiers-25 off release-0.3.24 a4c5a855 = the UI commit e6571f60 plus the merge of the hash lane's ember-tiers-25 3408db40 (d3d0704a); the UI tests known-failed first then 73 green on build-2; mock captures of the three states (the measured 5090 and 5080 at Balanced; the install's first minutes with nothing measured and Ember Tune on at Balanced; the M5 Max with no lever as Stock alone with the reason) under ~/Desktop/igneum-previews-2026-10-08/tiers/; the app crate gate and the full pre-push gate running on the merged tip, the gated tip by about 11:15, inside the 12:30 default; tiers-25 fast-forwards onto release-0.3.25 when the shipper opens it from a4c5a855; the live tier numbers come from the engine's own search, not from any table. THE BUILD-SERVER LANE'S CLOCKS (10:1x BST): the 0.3.25 pairs the moment the pin is named (the start script parameterised on the pin); the publisher's digest gate (publish-manifest.sh --node-bin, --network-digest, --move-clock; tools/digest-read.sh) landing on master before 12:30 and riding the app line (the alias assertion not its own); the telemetry exe's --tune read-back on PC 1 DONE at 09:07Z (the 9070 XT tune line: gmax 0 range -500 to +1000, plimit 0 range -30 to +10, factory 1); the second master-only deploy started 10:15 BST on master's tip. A FAULT: PC 2's 0.3.24 Windows installer failed at ISCC because release-0.3.24's .iss still carries the TDateTime line the 0.3.23 fix removed; the one-line fix with the shipper and the update-return lane, the republish on their tip (the Windows entry's default: it follows the move, never gates it). A SPEND TO SURFACE: two new Hetzner boxes provisioning (build-3 HEL1 32 threads, build-4 FSN1 96 threads, in the pool by 10:45), reported by the build-server lane; ordered on the founder's own word in chat ("re order", about 09:5x BST, after he added the credit himself; main clicked the order in his Chrome profile); the standing rule on purchases held; they stay. SITE DEPLOYED AGAIN (the build-server lane, master f98e8e7c at 09:15:33Z, 10:15 BST, on igneum.network and igneum.com; the checks ok): the tip carries ae8836f8 (row 17's floor sentence, the Arc row restored to its measurement) and the record through the twenty-eighth landing; the served state now carries every served change of the night and morning. THE 0.3.25 NODE LINE PLACEABLE (the node lane, 10:1x BST, ahead of 11:30): release-0.3.25-node = c6629572 on both mirrors (the pin 5b673577 plus igneum-miner keygen and the proving-fee ceiling switch coded and never set), pairing igneum-pow 1c420786; every gate green at 09:16:28Z (build 09:13Z rc 0, igneumd 3fadca49..., /srv/artefacts/0325-c6629572/node-lane; consensus 134, pow 19, miner 29 with the keygen test, p2p-flows 38, exec 48, core 177 at gate priority after a first run on a stale file on the box); the Devnet 3 canary (09:13:25Z to 09:15:04Z): digest cc902690 unchanged, byte 6, the override refused, two empty nodes handshaking, the shared-devnet dialler rejected, and the 0.3.24 pin's node handshaking with this build both ways, so the mixed fleet runs through the placement; the testnet canary b2e856ed unchanged. The keygen read-back from the artefact printed an address and a key (the key elided in every transcript and record; a printed private key never enters a message, a log the relay carries, or this file); the fleet writes keyed wallets from it. The defaults: the line's tip at 13:30 BST is c6629572 plus the drift reading's commit only if both nodes' logs reach the node lane by 12:30, else without it; the ceiling-switch field set in the 0.3.25 object from the shipper's minute by the one-go script (the digest moves then; the hold's second day under the ceiling, as main ruled; a re-cut without asking under a 15-minute margin); the crossing line the moment the DAA passes 68,400, a red first; the TESTNET_PARAMS v5-at-0 re-cut at 13:30 unless main says otherwise by 13:15. THE AMD KNOB'S GATED TIP MOVED (the update-return lane, 10:15 BST): amd-clock-25 e2962b89 (full gate GREEN 60, the box suite 298 green) in place of cf8444bf, with the shipper; from the exe's read-back on PC 1: the integrated Radeon's tune line carries every range as a dash and the knob had read it as an offset knob with a one-MHz ladder; it now reads "not available (the driver exposes no tuning interface for this card)", and the 9070 XT's real line (gmax 0, range -500 to 1000; plimit 0, range -30 to 10; stock 3,292 MHz under load) is the test's second half: the ladder 3,192 down to 2,792, the power 70 to 110 percent, offsets on the apply; the grid by 11:20, the efficient point into EFFICIENT_W before 12:30 or the declared ladder ships. THE MOVE'S READ-BACK (the fleet lane, late against its 10:20 minute): APPLIED on the relay at 09:07Z: 24 MATCH by the puller (igneumd 2.1.0-5b673577, digest cc9026909eddbadb, synced; dn3-g1 at peers 24), p1-3080 on cc902690 by 09:10Z; 2 FAILED (dn3-r01, dn3-r02: no saved environment, hand-started yesterday) moved by hand at 09:10:27Z; 9 MISMATCH with no node after the puller's restart (hub-1, dn3-g2, dn3-q04, dn3-q05, dn3-r04, dn3-p02, dn3-p04, dn3-p05, dn3-relay): the saved environment line NET_ARGS=--devnet --devnet-suffix=3 unquoted, so sourcing it ran "--devnet-suffix=3" as a command and the start never reached box-dn3.sh; all nine moved by hand 09:11:58Z to 09:12:24Z with every value quoted, the puller now quoting every value (redeployed 09:16Z on 34 boxes); so 36 of 36 fetched are on 5b673577 and cc902690 by 09:12:24Z (10:12 BST). The first lock on cc902690: checkpoint 1931, block 63510971..., blue score 57,930, at 09:06:32Z on dn3-g1 (4,803 signed, 69.8 percent of active, 66.7 of total); hub-1 logged the same checkpoint at 09:11:43Z after its hand restart and checkpoint 1944 (blue 58,321) at 09:12:39Z. The chain rate: hub-1 read 0 blocks a minute at 09:07Z because hub-1 was one of the nine down; from 09:12Z the tip moves at about 0.4 chain blocks a second as before, and paidShards moves again (11,821, frozen since 03:32Z, to 12,012 at 09:19Z, pool entries 47): carrying resumed with the move, the node lane's one-shot-gossip class confirmed. The proven share at 09:19Z 0.465 cumulative (the hour's own 0.000, the hour being the move); the proving fee 10,000 gwei per pgas last, 50,566 max over 60 blocks (1.0x and 5.1x the floor), the field now on the hourly line. The unfetched: dn3-agg48 (the L40S in its bring-up, applying at its first tick), p2-3090-1 (ssh refused since 21:48Z yesterday, on 2720d8d2 with 4 old-digest peers), p2-4090-1b (its Vast proxy dead, its node down); dn3-relay fetched at 08:48Z and is on cc902690. The eight "bc5945fe" boxes: no such binary (that sha was the reader's own shell); those boxes had no node at all (dn3-g2 dead since 22:49Z, dn3-g1 since 00:46Z, the others overnight, no panic or OOM on any), restarted 08:43Z to 08:53Z, took the move with the rest, and mine where they mine. The keyed-wallet write not started (the 0325 artefact's first mention to the lane at 10:20; box by box after the launch fleet's first boxes are up; the rent running since 09:16Z). p1-5090's drift reads offset -5 again at 09:21Z; hub-1's numbering against build-1's node the next read. Three fault classes for the record from one move: the unquoted environment line (fixed in the puller), the two hand-started boxes with no saved environment, and the eight boxes that had silently lost their nodes overnight with no panic (a watch for a node absent while its box is up is the fleet's next check). THE TIERS GATED FOR THE CUT (the UI lane, 10:20 BST by the Mac's clock): tiers-25 at d3d0704a on the mirror (the UI commit e6571f60 plus the engine half 3408db40 merged, both off release-0.3.24 a4c5a855, a fast-forward onto release-0.3.25): the app crate gate GREEN 299 + 35 + 8 on build-2, the full pre-push GREEN 60 checks with the stamp, the UI tests 73 green known-failed first, the push gate GREEN; the captures under ~/Desktop/igneum-previews-2026-10-08/tiers/; sent to the shipper; two hours inside the 12:30 default; a rebase and re-gate inside the hour if 0.3.25 opens from a later tip. Both halves of the three-tier Ember Tune are in the cut. THE 0.3.25 APP TIP (the shipper, 10:29 BST, two hours ahead of the 12:30 target): e0d4425f on release-0.3.25 (the box gate green): amd-clock-25 e2962b89, tiers-25 d3d0704a (both halves), the Intel header via 9088293a, the node-source pin c6629572; the node pin candidate c6629572 with the digest cc902690 unchanged; the cut list r0325-cut-list.md: the pin named by 13:00, the move no earlier than 13:30 after the 68,400 crossing reads clean; the pairing 1c420786 unless the Arc reads equal by 12:30, the Intel kit on that read. THE 0.3.25 NODE LINE'S TIP MOVED (the node lane, 7bd2940f on both mirrors at 09:24:03Z, every gate green at 09:29:48Z): c6629572 plus the one-shot gossip fix (unpaid proof records re-announced every 120 s; the class confirmed on the live chain after the 09:05Z move); nothing consensus, the Devnet 3 digest cc902690 unchanged on its canary, the 0.3.24 pin's node handshaking both ways, the testnet digest unchanged; build 09:26Z rc 0 (igneumd 16dee9f1..., /srv/artefacts/0325-7bd2940f/node-lane), exec 49, pow 19, core 177, p2p-flows 38, miner 29, consensus 134 at gate priority; it replaces c6629572 as the placeable keygen build and as the tip the ceiling-field cut lands on; the shipper has the line. The drift item is off this line: the fleet's reads were shared-devnet reads (hub-1's node on 26790 at chain block about 190,900; Devnet 3 at 25,900; both answering chain id 4463 below the floor), p1-5090 a shared-devnet prover, and the three numberings at one hash are the snapshot-inherited class (build-1's node1 itself resumed from a snapshot); the fleet rents a fresh-walk node under its standing ceiling to settle which numbering is right, hub-1's restart held until then, the loader change (re-number the resumed range against the DAG) after that read. THE 0.3.25 PAIRS ON 7bd2940f (the build-server lane, from 10:33:11 BST on build-1 under lease class release, /srv/artefacts/0325-7bd2940f/: the seed about 10:36, the Windows pair about 10:38, the hive package with the three kit zips about 10:41, each minute to the shipper and the coordinator); the c6629572 pairs already built (seed f913e3e7, win 42d0dd57, hive 14d86245) stand in their own folder and are not the cut; the publisher's digest gate on master since 10:17, riding the 0.3.25 app line. THE RE-POINTED APP TIP (the shipper): 92f004f1 on release-0.3.25 (e0d4425f plus the node-source pin to 7bd2940f), the push gate GREEN at 10:32 BST, the box gate GREEN at 10:33:25 (303 + 35 + 8); the cut list's pin candidate 7bd2940f; the kit re-cut from 92f004f1 and the pairs on 7bd2940f's artefact with the build-server lane; the Mac node pair and the DMG rebuilding on 7bd2940f under the lock from 10:32:31; the 13:00 pin and the 13:30 earliest minute standing. The 0.3.25 inputs are all green at 10:33 bar the pin's own gate set and the crossing. A SWEEP FINDING FROM MAIN (10:4x BST): on a rented, power-capped RTX A4000 (114 W cap) class v5 reads 26.0 MH/s against v4's 31.4, 17 percent under, the fingerprint equal; the A100 1.3 percent under; every uncapped consumer card level: v5 costs more compute per hash and a compute-limited card pays, which is what a knee lock makes of a card. Two orders with readings by 12:30: (1) the hash lane sends the 5090's v5 pack rows at the 1,300 lock against v4 at the same lock, and the 5080's if they exist; if v5 at the knee loses more than 2 percent, the knee is re-found under v5 and the tiers table says so; (2) the tiers' engine half: a class change (the chain's program class flipping) invalidates the stored tiers and re-runs the search within ten minutes of the crossing, the first-run line saying why; known-failed first (tiers stored under v4 must read "re-measuring for class v5" after the flip, never apply as if current); on 0.3.25 if it fits by the cut, else 0.3.26 with the record saying the v4 tiers may be off by the measured percentage until the re-tune. Per tier: a locked card may lose a few percent of rate at the class v5 crossing until Ember re-tunes; the number is the 5090 row. THE ORDERS PLACED (the coordinator, 10:4x BST): the hash lane's two readings by 12:30 (the 5090's v5 rows at the 1,300 lock against v4 at the same lock, the 5080's if they exist; the knee re-found under v5 if the loss is over 2 percent; the default if the PC 1 queue cannot run it: the A4000's 17 percent stated for a capped card and "unmeasured at the knee on the 5090"; and ember-tiers-25's class key: a class change invalidates the stored tiers and re-runs the search within ten minutes, known-failed first), the UI lane's class-flip state ("re-measuring for class v5", v4 tiers never applied as current after the flip) and knee note by 12:30, the shipper's cut list carrying both on 0.3.25 only if green by the pin at 13:00, else 0.3.26 with the record's sentence that the v4 tiers may be off by the measured percentage until the re-tune. THE 0.3.25 PAIRS ON build-1 (the build-server lane, /srv/artefacts/0325-7bd2940f/): the seed pair at 10:34:44 BST (igneumd c7fc542b, igneum-miner 4494ecc4, glibc 2.34), the Windows pair at 10:36:13 (igneumd.exe 5d1dea23, igneum-miner.exe eee7bdfa), the hive package igneum-hive-0.3.25-7bd2940f.tar.gz at 10:37:49 (sha d977797f..., the three kit zips, smoked in ubuntu:20.04); the kit re-cut from 92f004f1 (sha 676240f6, 424,540 B) staged in both folders, the PC 1 host from it bc8d4f79 (in host.sha256 at the shipper's 24680e1d), the 0.3.25 Windows payload from 24680e1d cutting. Every pair of the cut exists by 10:38; the pin's gate set and the crossing are the only waits. FOUR NEW LANES ON THE FOUNDER'S ORDER (11:00 BST, "build all this today to close this gap"), mirrored by the coordinator as the shipper's clocks are: the explorer (a5ef1d5801084005b; explorer.igneum.network by 16:00), the canonical DEX and the Sepolia certificate verifier (a74a8267813d6ea34; the AMM by 14:00, the swap UI by 17:00, the verifier by 20:00), the builder pages, faucet and grants (adb29da59baf27898; /build and /grants by 15:00, the faucet by 16:00), three reference apps that only work on a proven chain (a2060899d2a27d31c; /light by 16:00, /receipt by 18:00, the Sepolia oracle demo by 21:00); the build-server lane stands up rpc.devnet.igneum.network by 12:00; they do not touch the 0.3.25 cut, the crossing or the fleet, sharing the boxes' lease pools (class measure) and the master-only deploy; a lane silent past 25 minutes gets the word from the coordinator and then main. THE FAST-TIME GATE ON THE 0.3.25 PAIR: SUMMARY PASS (cross-0325-39f127a1) at 09:54:40Z (10:54 BST) on the pair 39f127a1 (the node code and object byte for byte e0644958's; igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 09:42:25Z to 09:54:40Z, every check green (rung 1 by signal at epoch 6, class v5 by signal at byte 6 from epoch 8 at rung 1 at 9,985 bps, the stale node refused, the restart step resynced in 8 s, four sinks equal, 0 PoW rejections); the ceiling's two new fields absent from the 60x file so the ceiling stayed at never there (the node lane's note); to the shipper the same minute; the pin line names e0644958 and its gates. THE FOUNDER'S WORD AT 11:0x BST ("can we add in any more layers? class rotating? things that would render an ASIC useless as soon as it dropped"): the class v6 design opens today as a rotating family, the research lane and the hash lane under the coordinator, the design doc docs/design/class-v6-rotating-family.md by 18:00 BST with the chip-model rows beside each layer (what it does to k and capex for a fixed-function chip and to the per-joule edge for a GPU-like chip; what it costs every GPU tier, Apple included): (1) per-era draws of the class parameters now fixed by release (the mixer round count within the tested margin, the op-mix weights within the measured safe band, the read width, the program length, the shadow placement), drawn from chain state like the program; (2) the state-derived dataset's size tracking chain-state growth with a floor, so fixed-memory silicon ages out; (3) scheduled family epochs by height (every 180 days by default) with no release; (4) the (c''') acceptance floor and the F8-form uniformity test generalised to each era's parameter draw, redraw on failure, so layers 1 and 3 need no per-era cryptanalysis. Per layer: the gate it needs (the family analysed as a family: the attack board's shape over the testnet period), the known-failed test, an honest line on what a fully general chip still gets. No consensus code this week; the document, the numbers and the gate plan. Per tier for the founder tonight: what each layer does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE ARC RE-READ IN ITS CHAIN (the hash lane, 10:57 UK): no clear came from the shipper, so the default ran at 10:50: the rotate-fold kit's fetch (sha 65b47211) published to PC 2 at 10:51:41, the run (run-ca3-pc2-v5-intel-bench-20261008, the v5 lane's script c0d398a1) in the publish chain behind another lane's publish-jobs.sh sign --deploy from the build-server worktree (the publisher serialises); the fingerprint line by 11:15 if the publisher frees inside ten minutes, else the blocking process named by 11:10. Queued on PC 1 behind the same publisher: run-ca3-pc1-v5lock-5090-20261008 (class v5 against v4 at unlocked, 1,300 and 1,200 MHz, the v5 kit's CUDA packs), its rows by 12:30; the AMD grid after it from about 11:25. The class-key work on ember-tiers-25 started; the v6 cost rows by 16:00 taken. THE TIERS' CLASS-FLIP STATE, THE UI HALF (the UI lane, 10:57 BST): tiers-class-25 at d949e274 on the mirror, off release-0.3.25's tip 24680e1d (the shipper having merged tiers-25 d3d0704a into release-0.3.25 at 111dae69), the crate gate GREEN 303 + 35 + 8 on build-1, the full pre-push GREEN 60, the UI tests 74 green known-failed first (the v4 tiers stayed on the buttons after the flip on d3d0704a); after the flip the table reads "re-measuring for class v5" on every button with the start minute or "queued (within ten minutes of the crossing)", the v4 watts never current, the strip's sentence naming the crossing; the knee note under the table when knee_loss_pct is over 2 percent; the captures tiers-flip-dark.png and -light.png; the fields tiers_class, program_class, tiers_remeasure_at, knee_loss_pct (the shape sent to the hash lane at 10:4x; the engine sha by 12:30); the default: the display rides 0.3.25 inert if the engine half is late and lights up on 0.3.26. THE FOUNDER'S WORD AT 11:1x BST: class v6 is DECLARED with the four layers as its spine (per-era parameter draws, the dataset tracking chain state, scheduled family epochs by height, the acceptance floor generalised to parameters), and deep past-and-future research opens now under the coordinator with serious resources ("see if anything can be optimised, added or invented"; reading public research is in-house, nothing paid or asked of anyone outside): four research lanes today, (A) history (every ASIC-resistant proof-of-work and how it fell or held: Ethash and the E3 and Linzhi chips, ProgPoW's review, RandomX and its chip analyses, Cuckoo, Equihash and the Z9, Argon2 and Scrypt and the Litecoin chips, KawPow, Autolykos, Octopus, kHeavyHash's chips; the exact mechanism each chip used and what the design missed, each mapped to Igneum's layers with "does v6 close it" as a sentence and a number), (B) the hardware future five years out (PIM and processing-near-memory, HBM3e and HBM4, LPDDR6, 3D DRAM, CXL memory pools, wafer-scale, chiplets, FPGA with HBM; for each the chip-model k band against a state-sized dataset and dependent random reads, and the one layer that would blunt it), (C) invention (layers beyond the four, each a paragraph, a known-failed test and a chip-model row: data-dependent program graphs, latency-bound dependent reads tied to the shard proof, randomised memory topology per era, VRAM-size ratchets, proof-carrying hashes sampled by the pool, time-locked parameter commitments, and what the lane invents; rejecting what costs GPUs more than chips), (D) the family gate (how a parameter family is cryptanalysed as a family: sampling bounds, coverage, the F8-form and (c''') tests over the parameter space, the attack board's shape over the testnet period, so layers 1, 3 and 4 can be automatic with a proof of what was tested). Resources: all four boxes under lease class measure, PC 1 by job for card rows, the rented fleet for one-shot measurements inside the ceiling. Deliverables: a first synthesis in docs/design/class-v6-rotating-family.md by 20:00 BST (the four layers priced, every finding from A to D with its number, a ranked list of what v6 adds beyond the four, the honest line on what a fully general chip still gets), the full report by 09:00 tomorrow, one line to main per lane as each lands; per tier at 20:00: what v6 does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE 0.3.25 APP TIP AND PIN CANDIDATE (the shipper, 10:58 BST): the app tip 9b93e649 (push gate GREEN; the crate unchanged from e0d4425f; the node-source pin to e0644958 and host.sha256 bc8d4f79); the pin candidate the node lane's ceiling cut e0644958 (digest 1b37cb9d, every gate green 10:53, the fast-time SUMMARY PASS 10:54, the floor at DAA 82,800 about 16:53 BST, a publish up to 14:53 without a second cut); the tiers' class-key halves: the UI lane's tiers-class-25 d949e274 green and inert alone, merged with the hash lane's engine sha the moment it lands (12:30), gated as a pair on the release tip, riding only if green by the 13:00 pin; the 0.3.24 Windows take 2 failed at a new place (Inno stopped the app and copied nothing); the update-return lane owns the fix on release-0.3.25 by 12:30, the default the 0.3.25 Windows entry waiting for a clean take 3 while Mac and HiveOS move at the minute. THE FOUR CLASS V6 RESEARCH LANES SPAWNED (the coordinator, 11:0x BST, each with its worktree, its box resources under lease class measure, its clocks and the rules): lane A history (a603a938582c43ab5; the first cut docs/analysis/class-v6/history.md by 15:00), lane B the hardware future (a4f73e2a6f2d1b757; hardware-future.md by 16:00), lane C invention (a5dfe95ee8c47cd0f; invention.md by 17:00), lane D the family gate (a07a99a3788566af2; family-gate.md by 17:00); each feeds the research lane's synthesis docs/design/class-v6-rotating-family.md by 20:00 (its outline by 13:00; the hash lane's per-tier rows by 16:00); the full reports by 09:00 tomorrow; the coordinator's lane mirror carries their clocks. A HELD PUSH AND ITS CAUSE (11:00 BST): the hash lane's push of ca3-v4-amend was refused at 10:58 by the gh-account hook reading the founder's gh (his personal login active again; nothing switched by any lane); the cause is the branch's own hook, which predates the per-process fix (34b0884d): the hook runs the branch's tools/ci, so every branch older than 09:58 must merge the mirror's master before its next push, under which the check reads Igneum's own gh directory and skips under the suspension marker; the rule to every lane. Live: the Arc re-read on PC 2 (published 10:59:47) and the v5lock job on PC 1 (published 10:53, about 12 minutes). THE CLASS V6 OUTLINE ON THE MIRROR (the research lane, docs/design/class-v6-rotating-family.md on counter-asic-4, the commit after fb61ed4b, pushed 10:5x UTC, two hours ahead of 13:00): section 0 the founder's table (per layer, what it does to a fixed-function chip and to a GPU-like chip on its release day, and the 5090, 5070 Ti and M5 Max columns, measured where the night's rows exist, the 5070 Ti scaled until the hash lane's row); the honest frame on top: the four layers render a FIXED-FUNCTION chip useless on the first era its wired value leaves (one tape-out lives one era) and move nothing for the stored-dataset chip with a programmable core except the core's size and the N5 project it forces; that chip keeps 3.6x at zero premium and 2.1x at k = 1 on a 5090 at its knee. The layer table (sections 1 and 2) names the bands each draw takes and the measured rows that set them: the mixer in {4, 8, 16} (x16 open), the op-mix weights within B = 4 with shuffle and mulhi capped (shfl 55.8 pJ per op), the read width in {1, 4} words (w64 excluded by the 5 October rows), the block shape 64 to 256 (never 1,024), N left to the ladder's signal (an unconditional draw retires the Apple tier at 200,000). Open numbers asked of the hash lane with defaults at 16:00: the 5070 Ti row (the rented 5070 scaled), the x16 mixer's verifier and build (the chip model's estimate), two re-weighted shadow packs for the op-mix band (the microbench arithmetic). Layers 2 to 4 and the gate plan are skeletons with their sources named, filling by 18:00 with the four research lanes' cuts, the synthesis by 20:00. THE FOUNDER'S WORD AT 11:2x BST ("all builders are idle, load them up"): build-1 to build-4 filled now and kept above 80 percent all day under the lease pool, class measure behind the release gates, in this order of value: (1) the class v6 family gate's sampling runs for lane D (the F8-form census and the (c''') floor over the parameter bands: the mixer {4, 8, 16}, the op-mix weights within B = 4 with shuffle and mulhi capped, the read width {1, 4}, the block 64 to 256; thousands of drawn eras, the uniformity and bucket tests on each, so the family document carries measured coverage tonight); (2) the attack families at scale on the 0.3.25 pin candidate's igneum-pow (F8 to 256 seeds, F9 and F1 to 10^6 on the frozen 1c420786, the day-key scan to 2^28) as the record's strengthening lines; (3) the invention lane's candidate layers measured as packs as fast as it writes them; (4) the full suite matrix of the 0.3.25 pin on every box as the pre-pin check; (5) the Windows and hive cross builds and the sweep's reruns; the lease tool's pre-emption giving release-class work the cores when the pin's gates need them; one line to main at 12:00 with the load on each box and what runs there, then hourly only if a box drops idle. THE DRIFT CLASS SETTLED (the node lane, from the fleet's fresh-walk node, a shared-devnet node synced from an empty datadir to 191,441 chain blocks at 10:03:45Z): hub-1 and five standing boxes number the fresh chain exactly; seven boxes carry numbering inherited from an exec snapshot taken on a chain that later re-walked (+2: p1-4090, p1-a5000, pool-1, build-1's node1; +3: p2-3090-2; +4: p2-3090-4; +5: p1-5090 and p2-3090-3), and a restart on the kept datadir does not re-walk (p1-5090 at 09:22Z stayed +5); the cost: a prover on drifted numbering signs statements the hub vetoes, so the seven earn nothing from proving until they re-walk, the drift refusal stopping the waste. The node lane's word to the fleet: p1-5090 first, both snapshot files moved aside so the executor re-walks from the DAG, the re-walk timed and read against the fresh node, then the other six in series, hub-1 untouched, build-1's node1 after the 12:40Z move; if the re-walk reads over two hours the six wait for the node-side fix on the next node line (the loader re-numbering a resumed range against the DAG before serving). THE 0.3.25 PIN CANDIDATE CONFIRMED (the node lane): e0644958 on both mirrors (keygen, the re-announce, the ceiling switch at 82,800 in the Devnet 3 object, digest 1b37cb9d, the 0.3.24 pin refused both ways), every gate green at 09:53:01Z, the fast-time SUMMARY PASS at 09:54:40Z on the same object; the publish ceiling DAA 75,600 (14:53 BST); waiting only on the 68,400 crossing reading clean (about 12:54; the node lane's line the moment the DAA passes it); the shipper names the pin at 13:00; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. LANE C'S FIRST PACK (the invention lane, 11:0x BST by the Mac's clock; its own line read "12:1x", a clock to correct): build-1 takes the igneum-pow build from counter-asic-4 at 5984ffab, then the per-load shadow in its sound form (mx8+shl6912x1: 16 sub-blocks of 432, one pass, the form 20.2a named and never drew) as the first candidate: the acceptance census over 64 seeds and 16 drawn eras against the 16x27 form and the class v4 shape, the pack export, the F8 read at 2^24 and the verifier bench on a leased core, the first read by 13:30; build-2 next for the second candidate (warp-uniform data-dependent block selection); the candidates with no pack form (the VDF commitment, the VRAM ratchet, the pool-sampled witness, the state-tied reads) stay modelled and the 17:00 cut says so; the worktree igneum-wt-v6-invention on class-v6-invention. THE WINDOWS INSTALLER CLASS AND THE 0.3.25 TIP (the shipper, 11:08 BST): the app tip 139c147a (9b93e649 plus install-detach-25 52a34111, packaging/windows and tools/ci only, the crate unchanged; push gate GREEN); the 0.3.24 take 2 class: an installer started under the app's job runner is a child of the engine, and the engine's kill_tree on quit ended it between PrepareToInstall and the copy; the fix re-launches the installer as a one-shot scheduled task outside the job's tree; the 0.3.24 Windows entry skipped; the rule-14 take on PC 2 is the 0.3.25 installer over the running 0.3.21 app, queued ahead of the Arc re-read; the pin candidate e0644958, the DMG 501ba293 staged, the 13:00 pin and the 13:40 provisional minute standing. THE ATTACK FAMILIES AT SCALE (the attack-pass lane, cores held at 11:08 BST, every run under lease pool class measure): box 2 (88 cores): F8 seeds p66 to p257 (192 new, 256 with the gate's p2 to p65) at 2^24 on class v5 at the freeze 1c420786 (the gated binary 0f5c98dc, pairing e5a4ac5978462156; the leaves re-run on 8f481459 if the kit pairing flips), the window-model control, by-site, as three thirds of 64 seeds; box 4 (80 cores held, 16 asked): F9 to 10^6 on 1c420786 (seeds 100,000 to 999,999 in six chunks of 150,000 at 8 threads, four running), F1 to 10^6 class v5 programs on 1c420786 (one census at 40 threads with the progress line and flushed partials, re-drawing the record's first 10^5 on the way as a reproduction check), the F4 day-key scan to 2^28 on 8ca66afa's redraw rule at 8 threads; nothing on build-1 or build-3 (lane D's); the projections: F4 about 2 to 3 hours, F8's 192 seeds about 9 hours, F9's 900,000 and F1's 10^6 about 30 hours each, so the 17:00 default is partials for those two with the lane (d) rows carrying counts so far; any pre-emption by release-class work reported. THE RPC AND THE 0.3.25 PAIRS ON THE PIN CANDIDATE (the build-server lane, 11:0x BST): rpc.devnet.igneum.network up since 11:08 BST (the first of the founder's builder clocks, 52 minutes ahead); the 0.3.25 pairs on e0644958 running on build-1 since 11:06 (the app tip 139c147a), the Windows and hive crosses on build-2, build-3 and build-4 as reproducibility rows at class release by about 12:40; the sweep reruns' list not held by the lane, the default at 12:30: last night's sweep logs on build-1 read for rows that ended without a result line and those rerun at class measure. THE SWEEP RERUNS' LIST (the fleet lane to the build-server lane, 11:1x BST): the fleet ran nothing under the build boxes' lease pool last night (every fleet bench a rented GPU one-shot), so the rows the lease kills cut short are the hash and class lanes' and the build-server lane's default read on build-1 is the right one; the fleet's own rows without a result (A10, A40, A100 40 GB, H100 NVL, H100 PCIe, MI250, RTX 3050, RX 7800 XT, 7900 XT, 7900 XTX, 6900 XT) are provider gaps needing a GPU host, rerun the moment a provider lists one. THE CLASS-FLIP TIERS, BOTH HALVES (the UI lane, 11:13 BST by the Mac's clock, 1 h 47 min inside the 13:00 pin): tiers-class-25 at 081b3ba7 (the display d949e274 plus the hash lane's ember-tiers-25 0a838072, on release-0.3.25's 9b93e649; the field names matched exactly): the crate gate GREEN 305 + 35 + 8 on build-1, the pre-push GREEN 60, the UI tests 78 green known-failed first, the push gate GREEN; with the shipper. A RED ON THE RELEASE TIP, for the shipper and the update-return lane: release-0.3.25's 139c147a is red on one crate test (ota::return_tests::no_relaunch_while_an_installer_runs_and_a_relaunch_when_it_clears, 304 of 305): install-detach's 0c588b09 reshaped the installer's clear step into a multi-line block while the test asserts the one-line literal at app/igneum-app/src/ota.rs:1348; 9b93e649 passes; the fix is the test's literal on the install-detach line; the UI lane built on 9b93e649 so its tip is green alone. A RED FROM THE PIN MATRIX (the CI steward, 11:13 UK): the core suite fails on the pair (the node e0644958 with the app tree 9b93e649): config::params::tests::fast_time_60x_file_is_the_devnet_at_60x panics "override-60x.json lacks the field base_unit_decimals"; the field was added by 0e4ec18a on ca3-v4-node yesterday at 21:45 UK and reached neither master, release-0.3.25 nor the app tip while the node line's test demands it; so every box reads red on core, and the fix is one line on release-0.3.25 (the cherry-pick of 0e4ec18a, or "base_unit_decimals": 8 in infra/fast-time/override-60x.json); sent to the shipper; green so far pow and app on build-1 and build-3; the two new boxes' toolchains read the same as build-1 (Ubuntu 24.04.5, glibc 2.39, the pinned rustc, sccache and lease, no nvcc). The founder's fourth load item paid in its first ten minutes: a red no single-box gate had read. MAIN'S WORD ON THE TWO REDS (11:1x BST): the install-detach fix belongs in 0.3.25 if it can make it, since a Windows install by any path that lets the engine's job runner kill the installer mid-copy is the plug-tune-play fault class (an update a user repairs by hand); the default order: the update-return lane fixes the ota.rs literal by 12:00; if 139c147a plus the fix is green on the crate gate by 12:15 the cut goes from it, else from 9b93e649 with the detach on 0.3.26 and the record saying Windows installs by job stay unreliable until then; the missing 60x field: the CI steward lands the one-line field on master and the release line by 11:45; the pin slides under the shipper's authority inside 14:53. THE DAY-KEY SCAN TO 2^28 (the attack-pass lane; class-v5 8ca66afa's redraw rule, build-4 under lease pool 8 class measure, 379.2 s, census-2p28.md at 10:15Z, 11:15 BST): days with any gain over 1.1x: 0 of 268,435,456 on M1 (median 226), 0 against the mean, 0 on M2, 0 on ROT and RC; the M1 cost mean 225.791, sd 6.073, min 206 (day 27,016 at 1.0971x, the redraw rule's floor: no day under 206 in 2^28), max 258; every weak class on its analytic expectation (ROT any pair summing to 32: 160,354,008 against 161,256,979; RC any zero: 1 against 1.0, at cost 234, no gain; RC with rk = 0: 87 against 72, 1.8 sigma; the two cells under expectation the rule's own refusals). PASS: no chip buys a weak day in the first 735,000 years of days; at most 1.097x on the best day. The row and f4-weakday.md section 10 committed on attack-pass at eabb4b0e, the push held by the branch's old hook (the fix: merge master, under which the check reads Igneum's own gh directory and skips under the suspension marker). THE SWEEP RERUNS' READ (the build-server lane, 11:18 BST): build-1's records hold no hash-lane or v5-lane run the pool cut short (preempt.log: three TERMs all night, every one to an adv-class holder pre-empted by a release gate, not reruns by rule; no reaped.log; builds.jsonl for 18:00Z to 09:00Z 150 rows with no signal end, the non-zero rows the fast-time gate's designed failed cases and build errors; the census and fingerprint suites leaving no builds.jsonl row and no output directory ending without its result); live at 11:17Z the family gate's v5_attempts_census holding 24 cores on build-1 at class measure; the default at 12:30 if neither lane names a run: no reruns, the boxes carrying the e0644958 reproducibility crosses (build-3's Windows pair already read: igneumd.exe 4b0c3aeb, igneum-miner.exe b3da4088) and the gates. The founder's fifth load item is therefore the crosses, not reruns. The attack-pass branch merged master and pushed (460fd9fa, the F4 2^28 row and f4-weakday.md section 10 on the mirror; the hook skipping the gh read with its suspended line; nothing switched). THE FAMILY GATE'S FIRST COVERAGE (lane D, 11:2x BST by the Mac's clock; its own line read "11:3x"): the harness live on build-1 under lease pool class measure (scripts and pinned binaries under /srv/builds/_adv-family-gate/): (1) the base control v5_attempts_census on the shipped class v5 draw over f8-label seeds 1,000 to 11,000, 24 cores since 11:16; (2) the family harness family_gate_era_census (branch family-gate-v5 = class-v5 8f481459 plus the harness, never a chain path; the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE): one drawn era per seed, every layer-1 parameter from the era's own stream (the shadow block {64, 128, 256} x {108, 54, 27}, the mixer {4, 8, 16} recorded, the read width over {1, 4} words, the ten weights within B = 4 with shfl and mulhi never raised), the chain draw through the real rule with every candidate's first failing part, then on the accepted program at the rule's own 2^20 sample the (c'')/(c''') ratio, the largest 256-item bucket per site (ratio and sigma), the index-bit bias per site in sigma; the 16-era smoke run PASSED at 11:21 (about 10 core-seconds per era; 10,000 eras about 28 core-hours). THE WORST READINGS IN THE 16: (a) the index-bit bias read fires HARD on 7 of 16 eras, |z| 130 to 511 at one site, every one at address bit R (the era's stride rotation) or R+1 (era 15 with R = 25 bit 25 z -511 at P(bit) 0.25, a product's bit 0; era 7 R = 17 z -468; era 5 R = 26 z -440; era 13 R = 1 bit 2 z -255, a product's bit 1 at 3/8; era 1 R = 6 z -224; era 12 R = 5 bit 6 z -130; era 6 R = 18 z +256, an or-shaped source at 5/8), the other 9 under |z| 3.8: adv-cache-2's era-stride class measured at the acceptance's own sample on class v5 accepted programs: not diffuse at the bit level, a 25 percent bias on one address bit of one site in about 40 percent of drawn eras, which (c''') does not see (min ratios 0.9954 to 1.0000); a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50, about 1.6 percent of a hash's reads at f = 1/2 for one site, which does not move the f = 1 verdict but is an auditor's flag on "uniform random reads"; the lever is load_index's form (fold the product's low bits before the rotation), not a floor (a 6-sigma refusal would redraw about 40 percent of epochs): a class v6 design row. (b) The (c'') ratio min 0.9954 (era 7), the rest 0.9965 to 1.0000. (c) Attempts: 14 of 16 accepted at attempt 0 or 1; era 9 (shape 64, width 4, mul 11 and or 8 of 75) took 24 candidates: the lossy corner raises r, the exhaustion number to read per stratum. (d) The largest 256-item bucket: ratios 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets, +4.4 sigma), so the F8-tail bound must be stated in sigma, not ratio (the sigma column in the rebuild). Next: the random stratum (10,000 eras) and the corner strata (the lossy cap, width 4, shape 64, 3,000 each) on build-1's free 64 cores, then build-3 and build-4; the first cut of family-gate.md drafted, the measured coverage table in at 16:xx for the 17:00 cut. THE OTA TEST LITERAL FIXED (the update-return lane, 11:23 BST, ahead of both clocks): ota-test-25 off release-0.3.25 139c147a, tip 53cb2f73 on the mirror, one test-only commit (the test reading the installer's clear step as the begin/end block the detach made it; the detach's behaviour kept), the box 2 crate suite 303 + 35 + 8 passed, 0 failed, the full gate GREEN 60; the shipper's cut tip 139c147a plus this commit, so the install-detach rides 0.3.25 and the PC 2 rule-14 take runs on it. THE 60x FILE, THE WHOLE FILE NOT ONE FIELD (the CI steward, 11:25 UK): the test names the first missing key in key order; with base_unit_decimals in it named emission; the file on master and release-0.3.25 lacks six keys the 0.3.25 node line's OverrideParams has (base_unit_decimals, pool_split_activation_daa, program_class_v5_activation_daa, proving_base_fee_ceiling_multiple, proving_fee_ceiling_activation_daa, subsidy_per_block_activation_daa); ca3-v4-node's copy (81 keys, master's 75 plus those six, no shared value differing) passes on build-3 by hand; release-0.3.25 got the one-field commit 907fdaf4 at 11:23 and the whole-file commit follows through the hook's gate, master the whole file behind the one-field landing; the known-failed on record on all four boxes; the green from the core re-runs in the 12:30 matrix; the risk named to the shipper: an older daemon reading the file with deny_unknown_fields. THE INDEX FOLD AS A CLASS V6 DESIGN ROW (the research lane, docs/design/class-v6-rotating-family.md on the mirror, the commit after 206e81e1): load_index folds a product's low bits before the stride rotation so no era's R lands a biased bit on an address bit (a design row, not a draw and not a floor); the evidence lane D's 7 of 16 drawn eras at |z| 130 to 511 on address bit R or R+1 with the (c''') ratio blind to it; the chip row 1.6 percent of a hash's reads at f = 1/2 for one site and zero at f = 1; the cost 0 on every card (one xor-rotate on the address path); the known-failed test lane D's 7 of 16 reading 0 of 16 with the fold; the value-level bias test in layer 4 ordered after the fold as its guard; the F8 tail's largest-bucket bound restated in sigma against its own window's Poisson expectation. The 60x commits: the one-field commit on both lines (master 7be52d76 at 11:24, release-0.3.25 907fdaf4 at 11:23), the whole-file commits in their gates behind it (release cbbaa8c4 pushing, master's queued). CLASS V5 AT THE KNEE ON THE 5090 (the hash lane, run-ca3-pc1-v5lock-5090-20261008-b, 11:09 to 11:21 UK, the 5090 alone, the v5 kit's CUDA worker on the rotate-fold build 8f481459, 60 s rows, the cleared helper sequence; an hour ahead of main's 12:30 clock): the same genesis seed, class v4 against class v5: unlocked v4 135.82 MH/s at 458.3 W (0.296 MH/W), v5 135.90 at 474.3 W (0.287); at 1,300 MHz v4 125.92 at 294.0 W (0.428), v5 125.93 at 299.8 W (0.420); at 1,200 MHz v4 115.69 at 273.3 W (0.423), v5 115.87 at 278.6 W (0.416); the Devnet 3 epoch-0 v5 pack (another seed, the fingerprint 82b19cbde8557ea5 matched on every row): unlocked 136.94 at 494.4 W, 1,300 134.10 at 315.6 W (0.425), 1,200 128.51 at 302.2 W (0.425). THE READING: at the knee class v5 loses 0.0 percent of rate against class v4 and costs 2.0 percent in watts (1.9 percent per hash), under main's 2 percent line, so the v4 knee stands, the tiers table says the class v5 rows are within it, and the UI lane's knee note stays off (knee_loss_pct 0 on the 5090); the A4000's 17 percent is a capped card's number: the 5090 at 1,200 MHz holds v5 level with v4 too, so the loss appears only where the power cap, not the clock, is the limit. Per tier for the founder: a 5090 or 5080 owner on a knee lock loses nothing at the class v5 crossing; a power-capped card (a datacentre card at its cap) loses up to 17 percent until its cap is raised or its class re-tuned. The 5080's rows after the v6 packs job if wanted; the AMD grid live on PC 1 since 11:25 (24 points, about 32 minutes). LANE B'S FIRST READING, RELAYED BY MAIN (11:2x BST), WHICH CHANGES THE CHIP MODEL AND LEADS THE 20:00 SYNTHESIS: a 2 GiB SRAM full store on one N2 die (about USD 500 of silicon, an N2 project of USD 100 M to 500 M) reads 13x to 17x the 5090 per joule at zero shadow and 2.7x to 4.8x with the shadow at the measured k band; layer 2 (the dataset tracking chain state) moves its capex, not its joules; the custom HBM4E base die (2027 to 2028) 6.5x to 14x, untouched by the four layers; PIM structurally blind to dependent random reads; and the M5 Max at 3.1x the 5090 per joule is the honest denominator. MAIN'S ORDERS: (1) chip-model-v3 gains the SRAM-store row and the HBM4E base-die row with lane B's figures and their claimed or measured marks; (2) the synthesis states the per-joule edge against the SRAM store honestly (3x to 5x with the shadow) and against the M5 Max, and prices the one layer that answers it: a dataset floor that grows on a schedule faster than SRAM cost falls, with the cost to a 12 GB and a 16 GB GPU and to 16 GB unified Apple memory stated; (3) the served chip line ("2.1x per joule at the knee") is reviewed at 20:00 with the measured basis for each clause; no served text changes before the synthesis, and if the SRAM-store reading stands the line becomes the honest range with the project cost and the clock beside it. THE SHIPPER'S THREE READINGS (11:2x BST): (1) override-60x.json: every reader in the tree is the fast-time harness, the sims and CI; no daemon on the fleet loads it; the app manifest's consensus.override is a separate 16-key object carried from the live manifest and untouched by the cut; the live chain's object is the digest's (1b37cb9d on e0644958); the harness's file only, the cut stands. (2) The cut tip cbbaa8c4 on release-0.3.25 (907fdaf4 plus the steward's whole-file commit; the crate and packaging trees byte-identical to 907fdaf4's, whose crate gate read 305 + 35 + 8 at 11:24; override-json-check passing): amd-clock-25 e2962b89, tiers-25 d3d0704a, the Intel header, the tiers class-flip pair 081b3ba7, install-detach-25 52a34111 with its test fix, the node-source pin e0644958, the host bc8d4f79, the fast-time file; the Mac DMG on it afa7f527 (45,766,741 B, the node pair 556926b1/d2dfe966), staging. (3) The knee note off on the 5090 rows. The pin at 13:00 on e0644958 and the 13:40 provisional minute standing; the matrix on cbbaa8c4 and e0644958 the steward's by 12:30. LANE B'S FIRST CUT ON MASTER (34f63b3c at 11:25 UK, four hours and thirty-five minutes ahead of its 16:00 clock): docs/analysis/class-v6/hardware-future.md with the three findings and the k bands (with the research lane, into the synthesis's section 7a on counter-asic-4 at ad37a50c); lane B's four decisions in its section 7 with defaults (the draw bounds by 20:00 via the synthesis; the dataset schedule unchanged; the M5 Max as the reference joule; the clock unchanged); nothing built or benchmarked, gh untouched; the full report by 09:00 adds detail only, no k band moving. LANE A'S FIRST CUT ON MASTER (docs/analysis/class-v6/history.md, 300 lines, merge 4c58ad65 at 11:26 UK, three and a half hours ahead of its 15:00 clock; the full gate GREEN 73 checks; primary documents read from the PDFs: the Least Authority and Bob Rao audits, Kik, EIP-1057, the RandomX design and v2, Tromp's README, the Fudan Equihash solver, Percival's lookup-gap note): 21 chip rows by mechanism (what each chip specialised, the miss, the timeline, the v6 layer, closed or not, the per-joule number), the in-depth sections (Ethash, ProgPoW, RandomX, Cuckoo, Equihash, Scrypt and Argon2, the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows), the four layers against the history layer by layer, the tier consequences. THE HONEST VERDICT WITH THE NUMBER: the chip that stores the dataset (class C: every Ethash chip, the E3 at 1.0x, the Linzhi at 2.1x, the Jasminer X4 at 5.1x via DRAM hybrid-bonded onto a 40 nm logic die, the E9 Pro at 4.1x) is NOT closed by any of the four layers, every per-era draw and family epoch being firmware to it; v6 inherits 5.1x per joule on GDDR7 at zero premium (3.6x at the 5090's knee, 2.1x with the class v4 shadow at k = 1), USD 2.8 against 14.7 per MH/s; classes A, B, D's governance half and E are closed, mostly since v2 and v3. THE THREE LESSONS THAT BIND: (1) the stored-dataset chip is firmware-immune to every draw; only joules and memory growth move it; (2) automatic change beats the human fork only where it costs the chip a redesign, and the one such parameter is the memory: layer 2 as declared is not an anti-chip rate (a 32 GB board lasts 60 years at 0.5 GiB a year; the 8 GB card is out at year 12; the E3 the only chip a growth rule ever killed, 20 to 27 months after shipping, at the fleet's own 4 GB limit), so its floor and a per-tier ceiling are the numbers to fix, not the rate; (3) a steered address pattern is always found after launch unless the test lives in the acceptance rule, and every drawn parameter changes layer 4's null, so the census re-derives per era (2.2 s per candidate). CORRECTIONS TO THE 5 OCTOBER FILE: the Antminer X9 withdrawn May 2026 with zero units (not "July 2026 delivery"); RandomX v2 released 25 March 2026 with activation pending (not "no fork"); CryptoNight's secret chips at about 33 months, not 43; Vorick's "survives forks at under 5x" and "13 months for a startup" on no fetched page, marked unverified. Two asks with defaults: layer 2's ceiling (if no word by 20:00 the full report drafts it as GB per tier per year keyed to card-lifetime-2026-10-05.md, with the flag that a dataset tracking state literally outgrows every card inside a decade if state grows as Ethereum's did); the hardware file cross-cited, not repeated. The lane's web-search budget spent (200 of 200); further additions by direct fetch. LANE D'S STATE (11:2x BST by the Mac's clock; its own line read "11:5x"): the first cut committed on class-v6-family-gate at 55c0dc6a with the full gate running; the census at 640 random eras, 298 lossy-cap, 327 width-4 on build-1 and about 500 shape-64 on build-3, the two build-4 corners queued behind a full pool; the landing on the gate's GREEN, the measured coverage table in the 17:00 cut. THE SNAPSHOT DIGEST STAMP (the node lane, 11:2x BST; a wip on release-0.3.25-node under its suites since 10:28Z): every snapshot a node writes carries its consensus digest as a new last field (the day-streams field's fallback shape, so 0.3.24 files decode with no stamp); a node with its digest set refuses a snapshot stamped under another digest ("re-executing from genesis") and one with no stamp ("written by a node before 0.3.25"), the follower starting at genesis; the daemon sets the digest from its params; the tests known-failed first (another digest refused, an unstamped file refused, nothing loaded; a matching stamp resumes, the written file carries the stamp, a digest-less process resumes as before, the wire round-trips); if the suites read green the full gate set runs and it is in the pin at 13:00 BST. THE CONSEQUENCE FOR THE MOVE: every Devnet 3 node restarted on 0.3.25 re-executes from genesis (no file written before 0.3.25 carries a stamp), so the restart takes the chain's re-execution time, which a fresh 0.3.25 node on build-1 since 10:24Z measures now (about 30,000 chain blocks; the rate in the pin line). TWO READINGS BESIDE THE CAUSE: (a) build-1's three nodes differ at 26247 (node1 0x3f53a7b9, the seed 0x717e7dc8, the observer 0x4548c319), and the seed and node1 differ at block 0 already (0x275b0cce against 0x7e37a9fb), which the ba75bf6f file alone does not explain (both resumed their own files across the same restart; the seed also restarted at 02:00Z on 2720d8d2 from a 0.3.22 file); the fresh node's genesis root and its first divergence from each decide whether a second class (an older-object file on the seed, or the resume itself) is in play; (b) the fleet asked for the roots at 26247 and 15611 on hub-1's Devnet 3 node, dn3-g1 and every prover by 12:30 BST with each node's resume line. The loud status for a vetoed node (a veto counter, the last veto's line on the explorer's status, "state not fresh") on the same line if the suites leave time, else 0.3.26, the node lane's word at 12:30. MAIN'S WORD ON LANE A'S ASK (11:2x BST): the default stands (the GB-per-tier-per-year table keyed to the card-lifetime file, with the flag), and one schedule to price beside it so the 20:00 reading carries a decision: a dataset floor of 6 GiB at the v6 epoch (every 8 GB card keeps mining with its cache; the 6 GB 2060 tier drops), 10 GiB two years on (the 8 GB tier drops), 14 GiB at four years (12 GB drops; 16 GB and Apple 16 GB unified hold), each step by height like a class epoch, the schedule itself a consensus field, with the cost per tier stated as the year each falls off and the share of today's measured cards that is; against the chips: the hybrid-bonded DRAM chip sized at launch (the E3 class) dies at the first step it cannot carry, the SRAM store pays capex only, both said. Lane A's corrections to the 5 October file go into the record and the served texts tonight. MAIN'S WORD ON THE STAMP AND THE GENESIS CLASS (11:3x BST): the stamp rides the pin; the re-execution time goes in the pin line and the move plan per tier; the fleet staggers the restarts in thirds so the proving share never reads zero, and the hourly line says "re-executing" with the count until the last prover is back. The second class is a GATE, not a note: the seed and node1 differing at block 0 means one of them runs a different execution genesis, and a hub node on a wrong genesis is worse than any snapshot drift; the pin is not named until the node lane says which file each of build-1's three nodes and hub-1 loaded at genesis, which root is the network's (the fleet's roots at 26247 and 15611 decide it), and the wrong one is corrected or re-walked; if that is not read by 13:00 the pin waits inside the 14:53 ceiling and the shipper slides by its authority. The vetoed-node status rides 0.3.25 if green, else 0.3.26. THE 60x FILE LANDED (the CI steward, 11:31 UK, ahead of 11:45): release-0.3.25 cbbaa8c4 (the whole 81-key file on 907fdaf4, the hook gate GREEN 60) and master e295c0d5 (the same file, the gate GREEN 73); known-failed to green on record: core RED on the one test on all four boxes before, core GREEN on the fixed pair on build-1, build-3 and build-4 after, build-2's re-run running; the full matrix by 12:30. A NEW GATE ON THE PIN (main, 11:3x BST, from the reference-apps lane's read): node1-dn3 and the re-executed observer diverge from chain block 26294 at DAA 60,578, the 10:05 move minute; node1 executed a block the selected chain later dropped and never unwound it, so its numbering runs one high and its state and records diverge; that is the drift class and the likely cause of last night's proving collapse after a move; the stamp does not cure it. The node lane's order: a known-failed reorg test under the exec follower, the fix on release-0.3.25-node if green by 13:30, else the move with the mitigation (every node re-executes from genesis after the minute, the vetoed-node status loud) and the fix as 0.3.26 tonight; plus the roots census to count stale nodes for the fleet's re-walk before the minute; the shipper's slide authority covers the pin inside 14:53; if the fix needs past 14:53, the floor re-cuts from the next minute by the same authority; the explorer lane reads block numbers from the observer node only (the chain the certificates follow) until the fix is live. THE FAMILY GATE'S 12:00 COVERAGE (lane D, 11:3x BST by the Mac's clock, ahead of its clock): 4,900 drawn eras through the per-era tests on three boxes (build-1 random 1,444 and lossy cap 663 at 10 core-seconds per era; build-3 shape 64 at 2,162; build-4's two lossy corners queued behind a full pool); the full gate on the first cut GREEN (73 checks, 381 s), the landing on one re-gate after a merge conflict on export-exclude.txt with the research lane's line (resolved, both kept). THE WORST ERA PER TEST: (1) THE EXHAUSTION BOUND BREAKS AT THE LOSSY CORNER: with or, mul and mulhi all at +4 points (30 of 75 lossy against the table's 18), r per candidate is 0.956 (the table's 0.681) and 8 of 663 eras EXHAUST the 256-attempt cap (mean attempt 18.6, max 252), so 1.2 percent of epochs at that corner would take the last-resort program, which adv-accept-3 showed fails rule (a) in 9 percent of seeds; B = 4 with the lossy ops free to rise is therefore outside the band; the random stratum at B = 4 (every weight drawn, lossy ones included) reads r = 0.718, max attempt 107 and 0 exhaustions in 1,444, but 107 attempts is 4x the shipped max of 28; the ring-A rule the cut carries: the sum or + mul + mulhi at most the table's 18 plus B, so r stays under 0.85 (r^256 under 1e-18); the default by 17:00: B = 4 on the injecting families only, the lossy families capped at their base. (2) THE ERA-STRIDE CLASS AT THE BIT LEVEL ON THOUSANDS OF ERAS: 52 to 58 percent of accepted programs in EVERY stratum carry one site whose address bit R (or R+1, R+2) is biased at over 6 sigma at 2^20, 33 to 40 percent at over 100 sigma, the worst z 1,024 at bit 7 of a site under R = 7 (a product's bit 0 at P = 1/4 landing at bit R): adv-cache-2's mechanism at half the family's epochs on programs (c''') passes (min ratios 0.9950 to 1.0000); the chip price per site about 1.6 percent of a hash's reads at f = 1/2 against the partial-store curve's 1.26x ops cost: the f = 1 verdict stands, the "uniform random reads" sentence does not; the catch structural (the index fold in load_index before the rotation, the class v6 design row), not a floor. (3) The largest-256-item-bucket excess: clean full-window sites +4.4 sigma; the worst eras +94 to +128 sigma at one site (the F8 tail's quarter-bit class at scale, the same mechanism: the bucket at the biased bit); the bound in sigma from the clean spread in the 17:00 cut. (4) The (c''') refuse rate per stratum: random 2.56 percent of candidates, shape 64 3.41, lossy 0.42 (the lossy rejections earlier at (a')); 0 accepted programs under 0.995 anywhere. (5) VOID and rerun: the width-4 stratum ran at width 1 (the era's one-entry allowed set redrawing to the base's width; fixed, the harness rebuilt, restarted at 11:5x with its own label space); the first corner strata sharing the random stratum's label space coincide with its draw a third of the time; the reruns use per-stratum labels; both stated in the cut. Coverage by 17:00 at about 1,000 eras per hour per 16 cores: random 10,000, shape 64 3,000, lossy cap 3,000, width 4 3,000 plus the two build-4 corners; the rule-of-three line for the random stratum at 10,000 eras a failing fraction under 3e-4 at 95 percent for every ring-B test. THE V6 COST ROWS (the hash lane, 11:4x BST by the Mac's clock, its own line reading "12:4x"; four hours ahead of 16:00): with the research lane at scratch v4/ca4-v6-cost-rows.md, every row labelled measured or modelled; the layer-2 headlines: VRAM 3.2, 5.4 and 9.9 GiB at the floor, 2x and 4x; a 12 GB card falls off at about 9.5 GiB (year 15), a 16 GB GPU at 13.5 GiB (year 23), a 16 GB unified Mac at 8 GiB (year 12), the 5090 at 29 GiB (year 54); the DRAM-read cost per hash size-independent (the 5090's 1.11 microjoules of 2.29), so the layer moves capex not joules, and the card rows allow a floor of 4 GiB in year 1 and 8 GiB by year 4 without retiring a 12 GB card (main's schedule of 6, 10 and 14 GiB at the epoch, two and four years sits above that: the 12 GB tier drops at 14 GiB, the 16 GB holds); the measured size rows (the v3 pack at 2, 4 and 8 GiB on the 5090, unlocked and at 1,300) ride the v6 packs job after the AMD grid. The AMD grid: the first run refused in 2 s at no_tune_line (the old installed exe, as designed); the rebuilt exe on PC 1 by the update-return lane's fetch at 11:33, the rerun from amd-clock-25 572c3ee0 live since 11:39 (about 32 minutes, the rows about 12:15). The class key on the mirror (ember-tiers-25 0a838072 in tiers-class-25 081b3ba7, with the shipper since 11:13, inside the 12:30 reading). The Arc read waits on the shipper's PC 2 take; the 12:30 default "no Arc read" stands unless it starts before. THE DRIFT CLASS READ FROM THE LOG (the node lane, 11:4x BST): at 09:42:09Z node1-dn3 accepted 0x6aa6 (DAA 60,578) and at 09:42:10Z 0xb708 (the same DAA and blue score 60,265, both children of 0x0fed at 26293: a tie at one height); its follower executed 0x6aa6 as chain block 26294 (28 transactions) and 1.1 s later 0xb708 as 26295 (the same 28 skipped as already included), with no reorg line between; every consensus view now (the seed, node1 itself, the observer) has 0xb708 as the chain block with the selected parent 0x0fed and 0x6aa6 off the chain, so node1's records hold an orphan at 26294 and number everything after it one high, and its state root diverged from there (the observer, re-executed from genesis, agrees with node1 to 26293). THE GAP: the 0.3.22 continuity rules (ledger N15) check the first appended block's selected parent against the tip at append time and scan the whole record set against the DAG's selected parents ONCE per state generation (a restart or a loaded snapshot); a break landing after that scan, as this one did ten minutes after node1's restart, is never looked for again until the next restart; the fleet's +2 on four shared-devnet boxes is the same gap. THE FIX on release-0.3.25-node (a wip under the exec suite since 10:41Z): the self-check runs every 30 s over the ring (the last 2,000 records) against the DAG's selected parents and in full on a generation change, a break handing the records above it to the reorg unwind (the existing branch restoring the ring state at the fork and re-walking); the test known-failed first on node1's exact shape; on the same commit the snapshot digest stamp (exec 51 of 51 green on its wip) and the vetoed-node status (vetoes counted on the status with the last veto's line, stateFresh false while any stands, on igneum_getNodeInfo and the status RPC); the exec suite's green about 11:46 BST, then the named commit, the full gate set, both canaries (the digest 1b37cb9d unchanged: nothing consensus) and the fast-time pair, the gated tip by about 12:30, inside 13:30. What the fix does not do: name why the tie-break flipped under node1 at 09:42Z (its DAG now reads 0xb708's parent as 0x0fed and the path at the time must have read otherwise; the second "PoW accepted 0xb708" line 0.4 s after the append says the block was processed twice), a reading for the record after the pin. The fresh 0.3.24-object node on build-1 past IBD and executing from genesis; its root at 26247, its rate and its memory peak in the pin line. MAIN'S WORD AT 11:4x BST: (1) lane D's band default stands (B = 4 on the injecting families only, or, mul and mulhi at base, the ring-A lossy-sum rule), and the index fold before the rotation with the bias test as its guard is layer 1's rule; (2) the served sentence "uniform random reads" is corrected today, not at the review: the audit lane rewrites it to the measured statement (reads spread over the whole dataset; a bit-level bias at one site appears in about half of epochs; it prices about 1.6 percent of reads to a chip storing half the dataset and nothing to a full store; the next class folds it out), through the gate and the master-only deploy, with the ledger row; (3) layer 2's table splits Apple by memory size (16 GB unified at its 8 GiB limit, 32 GB and 64 GB Macs holding every step), the M5 Max being the honest best per joule and the Mac tier a large audience; the schedule decision at 20:00 is the founder's with that column in front of him. THE EXPLORER'S SOURCE (the explorer lane, 11:4x BST): it reads one endpoint and always has, the Devnet 3 observer node on build-1 (the execution RPC on loopback 26850 through tools/observer/explorer-indexer.mjs, the observer's own dn3_ tables on 28650); it has never read node1-dn3, so there was no switch; the indexer on 26850 since 10:04 UTC with a full refill from genesis at 10:33 UTC after the root equality read at block 26,247; the pages now name the observer node as the one source, the chain the certificates follow (on explorer-dn3, in the gate; the merge and deploy follow). THE GENESIS GATE'S ANSWER ON build-1 (the shipper, 11:43 BST): the seed was the odd node (its block 0 from the 0.3.22 binary; the rule change for the node lane's record), re-walked from genesis at 11:35:30 by the shipper's hand (the evm moved aside, the same binary and flags, the kept datadir) and reading population A's roots at 11:43:00 (0x47983bd9 at 15611, 0x3f53a7b9 at 26247, head 26,478). THE MEASURED RE-EXECUTION: 26,478 chain blocks in 7 minutes 30 seconds (about 59 a second over the walk; 100 at the start, 30 past 15,000), RSS 5.5 GB; so the move plan's per-tier line: a prover's node is back about 8 to 10 minutes after its restart on 0.3.25 (30,000 blocks at the minute), a Mac or HiveOS app node the same at its update hour, miners unaffected; with the hub and the seed at the minute and the provers in two thirds at +0 and +25, the proving share never reads zero and the last prover is back about 35 minutes after the minute. The node lane's gated tip (the ring check, the stamp and the vetoed-node status in one commit, the digest 1b37cb9d unchanged) by 12:30; the pin after it and the fleet's census; the minute about 14:10 at the earliest if the fix rides, inside 14:53. LANE A'S SCHEDULE SECTION (history.md 4.2a, master 59963461 at 11:45 UK, five hours ahead of its 17:00 clock; three landings today: 4c58ad65, b645762d with the synthesis lane's six items folded in, 59963461): ONE FLAG on main's schedule with the number: under the standing budget rule (the working set under 6 GB on an 8 GB card, the 75 percent reading) a 6 GiB floor does not fit the 8 GB tier (6,398 to 6,744 MiB, 78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent); 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2 (not the 8 GB tier alone); 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above. The schedule that drops the tiers in the order main named, priced beside it: 5.5 GiB at the v6 epoch (6 GB falls, 3 percent of the 32 measured consumer cards), 8 GiB at two years (8 GB falls, 22 percent, with the 10 GB RTX 3080 and Apple 16 GB; 12 GB holds at 69 to 72 percent), 11 GiB at four years (12 GB falls, 22 percent; 16 GB holds at 70 to 73 percent); 24 GB and above hold throughout. Against the chips: the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 of GDDR7 on a USD 470 part); the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. So the schedule is a fleet-retirement rule with a USD 0 to 160 chip tax, killing only a chip whose maker ignores the field. The default by 20:00: the full report carries both schedules and recommends 5.5 GiB as the floor that keeps the 8 GB tier inside the rule. Owed: the fleet's hashrate-weighted card census (the shares are by count of the bench table's 32 measured consumer cards). LANE A'S CORRECTIONS SERVED (the site audit lane, master 2119e4f3 at 11:46 BST, gate green on 78166c6c, commit 14ad1a33; seven hours ahead of 19:00): every served "no chip shipped" and "seven years without a shipped chip" sentence (the litepaper's precedents row, the chip-model paragraph, the vs RandomX lead and its track-record row, the limits section; /claims and /randomx following) now carries the Antminer X5 (September 2023, 1.46x per joule over a desktop CPU, silicon believed mining privately from about 2021) and RandomX v2 released 25 March 2026 with its mainnet activation pending; the ledger rows X34 and C2 corrected with lane A's file cited, the pins moved, the public ledger and page regenerated; the X9 sentence already matched lane A's row (sales opened 26 December 2025, shipping scheduled July 2026, withdrawn mid-May with zero units), the precedents and track-record cells now reading "withdrawn in May 2026 with zero units"; the 43-month, 13-month and Vorick figures on no served page; the commit also carrying main's governance line beside the class v5 sentence and six class v4 watts rows; the "random reads" correction with its AP-F8 row next by 13:30; the build-server lane deploys on main's word. LANE C'S FIRST CUT ON MASTER (docs/analysis/class-v6/invention.md at a9f03598, 11:48 BST by the Mac's clock, five hours ahead of 17:00, with the census script under tools/attack/v6-invention/ and its two TSVs): build-1 ran the per-load acceptance census (11 forms x 256 seeds, twice: no era and drawn eras, 80 s each on 48 leased cores) and the verifier benches; the two packs exported and with the hash lane for PC 1; the second candidate (warp-uniform block selection) has no pack form without a generator change, which the no-code rule holds this week, so its row stays modelled. A CORRECTION TO THE CA4 FILE'S VERDICT, FOUND BY LANE C: the counter-asic-4 crate's per-load acceptance (BiasedIndexBit) counts the era window's fixed top index bits 26 and 27 as biased, so under any drawn era it refuses every per-load program (0 of 256 on every form today, 5,536 of 7,862 bias rejections naming those two bits); 20.2a-close's "1.4 percent accepted, 42 of 64 seeds exhaust" (the per-load class's death at 00:0x) was read across drawn eras and so measured the instrument on most rows; on the no-era census the sound form (16 x 256 x 1) reads 0.927 rejection per candidate and 234 of 256 seeds accepted, the iterated 16 x 27 form 0.989 and stays dead; the one-line instrument fix (skip bits at or above 28 minus the site's k_off) is a research-crate change, made today as a research-only change behind the pack by the coordinator's order, and the sound per-load form's verdict is REOPENED as a measured candidate (its energy and rate rows on the 5090 through the hash lane; chip-model-v3 5.11's note on the per-load closure to be re-worded when the re-read lands). THE REOPENING APPLIED (the research lane, 11:5x BST): the reopened wording in counter-asic-4-research.md (20.2a-close and rank 4), class-v6-rotating-family.md (section 7c as layer 5) and chip-model-v3.md 5.11's note, with one precision: the 22:5x UTC census ran the bare class with no era, so its 0.986 is the iterated form's own no-era figure (lane C's 0.989 agrees the 16 x 27 form is dead); the artefact in any drawn-era read before the fix; the fix already on counter-asic-4 as of 10:5x UTC (BiasedIndexBit judging only the bits inside each site's window mask through verify::window, per site), uncommitted until the suite's line lands (the box-2 slot since 10:31Z), so lane C re-reads on that branch once pushed, not making the change twice; the chip-model 5.12 rows (the SRAM store, the base die, PIM's blindness, the M5 Max denominator) in the same tree, riding the same commit before 15:00. A MIRROR NOTE (11:52 BST): lane B read silent 25 minutes by the mirror; its first cut landed at 11:25 and its next clock is the full report by 09:00 tomorrow, so the silence is its finished state, not a fault; the mirror now skips lanes whose clocks are done. A MASTER-ONLY DEPLOY AT 11:53 BST (the build-server lane, on main's own builder-programme landing d86ea00a: /build, /grants, /faucet, /swap asserted; the served sha a9f03598, master's tip; the checks ok; 38 miners rows): it carried the audit lane's 2119e4f3 (the RandomX history correction with the Antminer X5 and RandomX v2, the governance line, the first six class v4 watts rows), which main ordered served tonight and the audit lane cleared for the next scheduled deploy; the "random reads" sentences not yet corrected as served; the coordinator's trigger stands for the 13:30 correction. LANE C'S KNOWN-FAILED TEST FOR THE INSTRUMENT (11:5x BST): igneum-pow/tests/v6_window_bits.rs, the sound form (16 x 256 x 1) accepting on at least 4 of 8 seeds under drawn eras 0 to 7 with 0 window-bit refusals (0 of 8 before the fix), the no-era bit-0 refusal on seed 3 standing; 2 passed, 0 failed on build-1 against a local overlay of the same nine lines, the overlay reverted, the test file an offer to the research lane's suite; the re-read on the research lane's commit by 15:00; meanwhile build-1 runs the lane's uniformity read at 2^20 nonces on 64 seeds for the two sound per-load forms and the class v4 shape (the F8-form top-0.1-percent item share against a uniform control, the per-site distinct ratio) on a harness over the crate's trace_load_indices (the master F8 tool mirroring class v4's execution order), about 20 minutes on 24 leased cores. THE RANDOM-READS CORRECTION ON MASTER (the site audit lane, bf54b08d at 11:54 BST, gate green on db038279; an hour and a half ahead of 13:30): the litepaper's lead reads "dependent reads spread over a multi-gigabyte dataset that changes daily", the table row "the dependent reads are", the "chain of random reads into a table too big for a chip to carry" sentence standing with the measured clause after it (the 0.995 floor on every accepted program over 4,900 drawn eras; about half of epochs with one load site biased at the era's stride rotation bit; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold before the rotation in the next class); evidence row 18 with lane D's family-gate.md and adv-cache-2's section 2.3 as sources; the ledger row AP-F8-7 (AP-F8-6 taken on class-v5): "Open, priced: 1.6 percent at f = 1/2, nothing at f = 1; the served sentence corrected 8 October 2026", the disposition class v6 layer 1's fold with the bias test as guard; the public ledger and page regenerated; no pinned sentence touched; the fud-ledger's quoted history standing; the build-server lane deploys bf54b08d. BUILD-1 AT 11:55 BST (the coordinator's own read): load 107.6 on 96 cores; the lease table: the family gate 32 cores (the random stratum, 10,000 seeds), 16 (the lossy cap, 3,000), 16 (width 4, 3,000, restarted), lane C's uniformity read 24 of 48; 88 of 96 cores held, none waiting, no pre-emptions in the last ten minutes. THE 11:55 BST LOAD LINE (the build-server lane, all four boxes at the minute): build-1 (96 threads) load 113.7, the pool holding 32 for the family gate's random stratum plus 16 and 16 for its corners and 24 for lane C's uniformity read (88 of 96 held), the release and v5 builds outside the pool; build-2 (96) load 81.3, the pool holding 32 for the attack-pass F8 census (the thirds); build-3 (32) load 25.1, the pool holding 16 for the family gate's lossy-base stratum and 2 for the hash lane's x16 rows; build-4 (96) load 89.0, the pool holding 4 x 8 for the attack-pass F9 chunks 0 to 3 plus F1's 40 and F4 done; no release-class waiter on any box; the builders loaded, none idle. The founder's order at 11:2x is met at the minute: every box above 80 percent of its threads bar build-3 at 78 percent of 32, which the two queued build-4 corners and the next v6 pack take. The build-server lane's deploy of bf54b08d served at 11:56 BST, two minutes after the landing: the post-deploy checks ok (api/live igneum-devnet-3, the index strings, the legal line, 38 miners rows, the four builder pages 200), and the litepaper's lead sentence read back from the served page carries the corrected wording (wide parallel integer maths, warp shuffles, dependent reads spread over a multi-gigabyte dataset that changes daily, the program waiting on memory latency); the old "random reads over a multi-gigabyte" is absent. The CI steward's 0.3.25 pre-pin matrix with the shipper at 11:59 BST, 31 minutes inside its 12:30 clock: seven suites on four boxes, every cell green but the one known core red on the pair before the fast-time file (the same single test on all four boxes, the six missing keys), and core green on the fixed tree on build-1, build-3 and build-4 (170 passed each); build-2's re-run queued behind three lanes' suites and lands on its own; counts identical across boxes (pow 113, app 346, exec 49, miner 29, p2p-flows 38, consensus 134); the Mac's full gate on the 9b93e649 tree GREEN, 60 checks; build-3 and build-4 toolchains read as build-1. The matrix worktree sits at cbbaa8c4 (81 keys, igneum-pow identical to the pin's tree); the second matrix waits on the node lane's gated tip (by 12:30), the line by 13:15. The RX 9070 XT's first measured grid on the AMD knob (job run-ca3-pc1-amd-grid-9070-20261008-b on PC 1, 11:40 to 12:10 BST, 24 of 24 rows ok, the card reset to factory at the end): the rate flat at 18.93 to 18.98 MH/s on every point, the knob moving watts only; stock 3,292 MHz 195.8 W (0.097 MH/W); the clock offset alone to 2,924 MHz 159.2 W at -400 (0.119), clamping about 2,920 at -500; the power limit alone does nothing until -30 (184.4 W); best -500 MHz with -30 percent: 2,921 MHz, 149.3 W, 18.96 MH/s, 0.127 MH/W, a 24 percent saving at the same rate. Per tier: a 16 GB AMD home card gains a quarter of its electricity cost at no rate loss once 0.3.25's knob ships; it stays 3.5x behind the 5090's 0.43 MH/W at the lock, so last night's AMD reading stands (the read path, not the clock, is AMD's cost). The v6 packs job live on the 5090 since 12:11 BST (eleven packs including the three dataset sizes, unlocked and at 1,300, about 40 minutes). The Arc re-read not started on PC 2 (the shipper's take holds the box); at 12:30 the default "no Arc read" stands, the pairing 1c420786. The Ember priors committed on ember-tiers-25 at 1e966170 with known-failed tests, its suite queued behind build-2's slots since 11:46; the sha to the UI lane and the shipper on its green; if not run by 12:45 the suite moves to build-1 through a lease. Two master-only deploys from the builder stream, checks ok (38 miners rows, the six asserted pages 200): 0c64b24f at 12:07 BST, the explorer landing (explorer.igneum.network, /proving, /tx/, the dn3_ APIs reading "Devnet 3"; the explorer indexer unit moved to the master checkout and restarted, reading the observer only as main set), and 3355c098 at 12:16 BST (site/vercel.json only: the explorer host's root 307 to /explorer, read live). No chip text changed in either. Still in the stream: the reference-apps lane's /light, /receipt and /oracle (its gate since 11:50, the 13:00 default) and the audit lane's watts rows 11 and 12. A third master-only deploy from the builder stream: f0418c8d at 12:19 BST (main's word via the explorer lane: EXPLORER_EVM_RPC on the production env, so /api/explorer balances read live from rpc.devnet.igneum.network; checks ok, 38 miners rows, six pages); the public RPC's allow list tightened the same minute to igneum_get* (the two igneum_submit* writes refused), reported to main. No chip text changed. The /build lane DONE with every clock beaten: landed on master as d86ea00a (11:47 BST), deployed as a9f03598 at 11:53; /build, /grants, /faucet (the Devnet 3 faucet page) and /swap serving in the nav's Build group; faucet.igneum.network/api/faucet live on build-1 behind Caddy, funded 2,000 IGN by the fleet lane (11:01 BST), the first drip 11:17 BST, 1,989.99 IGN left; the walkthrough PASS through the public RPC and faucet (a contract deployed at block 27055, 24 s end to end, Foundry 1.8.5, docs/build/first-contract.md); the RPC list read from the node in docs/build/rpc.md; the audit's four wording lines in. One open fact to the fleet lane: build-1's Devnet 3 seed at 27810 re-executing from genesis while the faucet reads the observer's 26850 (the re-execution class measured at 7 min 30 s this morning). Lane D's coverage at 12:2x BST, every launched stratum complete (the runs beat the 1,000-per-hour estimate once the pools freed): random 10,000 eras (0 exhausted), lossy cap 3,000 (37 at the 256 cap, 1.2 percent), width 4 at the fixed harness 3,000 (0), width 4 plus lossy cap 2,000 (24, 1.2 percent), shape 64 3,000 (0), the lossy-base band (B = 4 on the injecting families, or/mul/mulhi never raised) 3,000 (0); 24,000 drawn eras through the per-era ring-B tests on build-1 and build-3; build-4's shape-64-lossy and shape-256 strata still queued behind the attack pass's F9 chunks and not needed for the cut. The exhaustion finding confirmed at scale: 61 of 5,000 eras at the lossy corner reach the last resort against 0 of 19,000 everywhere else, so the band rule (lossy families capped at their base) stands on measured rows. The 17:00 clock holds; the cut (coverage table, per-axis table, union-bound arithmetic, harness patch series) likely lands by 14:30 BST. The node lane's gated tip missed its 12:30 clock: the combined wip (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the reorg-unwind fix on the same commit) sat in build-2's queue from 11:41 BST at normal priority behind a Counter ASIC 4 suite holding a slot since 11:31, found at 12:21 and moved to build-1 at gate priority; the exec suite about 12:25, the named commit on green, the full gate set (build and consensus at gate priority, five suites, both canaries, digest 1b37cb9d unchanged) about 12:50, the fast-time pair about 13:05, inside the 13:30 clock. The coordinator's default revised and taken by the lane and the steward: the second matrix starts on the named commit the minute its sha exists; no sha by 12:50 and the matrix runs on e0644958, the stamp and vetoed status slide to 0.3.26. The pin reads about 13:15 to 13:30 rather than 13:00; the minute about 14:10 holds if the fix rides; reported to main at 12:29. The seed's re-walk read equal to population A at 11:43 BST (0x47983bd9 at 15611, 0x3f53a7b9 at 26247; 26,478 blocks in 7 min 30 s, about 59 a second, RSS 5.49 GB); the fresh node on build-1 executing from genesis since 11:42:34 at about 100 a second at the start, its roots to follow. The lesson for the record: a release gate is dispatched at gate priority or it waits behind research suites; the node lane's wips were not. Main's correction at 12:3x BST on the fleet default: the 10:12 FETCHED count is not a census of state. If the stamp rides the pin, every node re-executes from genesis at the minute and the census is not a gate; if the stamp slides to 0.3.26, the census (block 26294's hash and the 26247 root on every prover) is a gate and the stale nodes re-walk before the minute. The fleet lane silent since 11:31: a one-shot at 12:36 starts a fresh fleet-move lane from the fleet root to take the census, the re-walks, the stagger and the pullers if it has not answered by then; the old lane keeps the hold and the hourly line. The 9070 XT reading goes to the audit lane for its row. Build-2's queued cell landed at 12:24 BST: core GREEN on the fixed tree (177 passed), so the first 0.3.25 matrix is green on every suite on all four boxes. The steward's gate-priority stream for the second matrix written (every suite at gate priority, its own results file), waiting on the node lane's sha with the 12:50 fallback armed; the line by 13:15. The AMD knob closed for the cut before 12:30: the 9070 XT grid's rows in and the efficient point in EFFICIENT_W as 149 W (both floors: clock offset -500 at about 2,920 MHz where ADLX clamps, power limit -30; 149.3 W at 18.96 MH/s, 0.127 MH/W, 24 percent under stock at the same rate); the rate flat over the whole ladder, so the knob is a watts lever only and the knee rule reaches the floor; amd-clock-25's gated tip 1be99aa0 (full gate GREEN 60, suite 298 green) with the shipper as the cut tip, the release section reading measured. The 5090 comparison carries two denominators, both real: 0.43 MH/W at the v4 1,200 MHz lock (133.8 MH/s at 305 W), 0.58 to 0.60 at the 1,300 knee (134.6 at 223 W); the 9070 XT at its floors is 3.5x behind the first and about a fifth of the second; a served row names its point. The Arc default taken at 12:30 BST: no B580 re-read reached the v5 lane, so the pairing line went to the shipper as the FREEZE 1c420786 (0.3.24's, as published) with the kit zip 65b47211 (packs-ca3-v5-20261008T085619Z.zip; its packs, ids and 82b19cbde8557ea5 byte-identical to 1c420786's by the packs test on both trees) and the Intel worker held out; 8f481459 (gate 73 GREEN, suite green, the Intel fix in) stands behind it and becomes the pairing with the Intel kit the minute an equal Arc read lands, with the page's Intel row moved. Nothing else of the v5 lane's in the cut. The shipper at 12:33 BST: (1) the 0.3.25 app tip is 89e83df2 (cbbaa8c4 plus amd-clock-25's gated tip 1be99aa0: the 9070 XT's efficient point 149 W at 18.96 MH/s in the ceiling table, the grid playbook; crate gate GREEN 12:28, 305+35+8, inside the 12:30 app window); the second matrix uses it with the node lane's sha. (2) On the node lane's hint, build-1's Devnet 3 seed and node1-dn3 were found dead since 12:06 and 11:54 BST (logs ending mid-line, no panic, no OOM; the observer and the fresh node lived): the network's seed was down 24 minutes; both restarted at 12:30 on their kept datadirs (the seed resumed its clean re-walk snapshot, node1-dn3 re-walking from genesis). Two reads before the pin: the build-server lane by 12:50 on whether any build-1 run kills igneumd by name (a cleanup that does so reaches the seed at the minute); the node lane by 13:00 on whether the line can die silently under the finality route flood the seed's log shows (a million drops on one peer). (3) The pairing the freeze 1c420786, kit 65b47211, the Intel kit out (PC 2 dark, no Arc read today); the genesis class closed on the fresh node's roots; the pin after the node lane's gate set, the matrix and the census; the minute inside 14:53. The hash lane at 12:4x BST: (1) the Ember search priors on the mirror as ember-tiers-25 1e966170, app suite green (307 + 35 + 8), with the UI lane and the shipper; the cut default stated to the shipper (in by the 13:00 pin or 0.3.26). (2) The v6 packs job on the 5090 (since 12:13): the four packs made on the box or pinned ran PASS unlocked (mx8-genesis 137.65 MH/s at 312.2 W; mx8_sh256x27 137.62 at 464.6; the invention lane's mx8_shl4096x1 135.99 at 428.6; mx8_shl2304x3 135.85 at 483.6; the 1,300 rows follow); the seven exported on the Mac this morning (today's x8 and x16, the two re-weighted, the three dataset sizes) were refused by the worker's seed check in 0 s ("IGNEUM_SEEDW_INIT is not attempt 0 of the epoch seed"): the string-seed export form derives different seed words from the byte-seed form the pinned packs use; re-exported in the byte form (the x8 reproduces the pinned id 73bcbfe8 and seed words exactly; the three sizes too; the x16 pair and the two re-weighted packs on generator 2 differing only in the era, the multiplier or the weight table); kit b and one more PC 1 job of those seven follow the running job's close, about 13:00 to 13:45, rows to the research lane, the invention lane and the coordinator. The invention lane's reading so far: the sound per-load form at class v4's instruction count (shl2304x3, 55,296 shadow ops) costs 483.6 W against sh256x27's 464.6 W unlocked, 19 W more, not under; the one-pass form (shl4096x1, 32,768 ops) 428.6 W; the lock rows decide the per-load candidate's GPU side. The export-form lesson for the record: packs for the worker are exported in the byte-seed form, never the string-seed form. Main's load order at 12:5x BST: lane D's two remaining strata (shape-64-lossy, shape-256) move from build-4's queue (behind the attack pass's pool) to build-3, idle after lane D's strata; build-3 kept fed with lane C's packs and the family census's next corners; nothing new on build-1 (load 142) until the pin is named, its gates at gate priority. Sent to lanes D and C with the 13:05 default. The node lane's two readings at 12:4x BST on the combined tip: (1) the build-1 deaths were the OOM killer (the build-server lane read the kernel ring: the seed at 44.6 GB anon-rss at 12:06:07 BST, node1 the same class at 11:54, two 31 GB attack binaries beside them); what grows is the proof pool's in-memory proof map: since the late-join rule (0.3.17) every proof a node receives is held by hash in memory and never removed (the entries leave the 600-block record window and the on-disk archive drops below the pruning point, the map did not); about 1.2 MB a proof, 14,107 proofs on the observer after a day (17 GB on disk, 13.6 GB RSS), the seed at 128 inpeers took the relays fastest; older than 7bd2940f; the fix (a proof leaves the map and the verdict cache with its record at the window's end unless another live entry names it; carried proofs served from the archive; known-failed test) on the tip under its exec suite at gate priority since 12:35:55. (2) The ring check's known-failed test on node1's shape green (exec 53 of 53 at 12:34:53 before the pruning went in). The named commit (the 30-s ring check, the snapshot digest stamp, the vetoed-node status, the proof-map window, over 7bd2940f's re-announce and keygen and the ceiling switch) follows the exec line about 12:40, inside the 12:50 fallback; the full gate set at gate priority on both boxes, both canaries (digest 1b37cb9d unchanged) and the fast-time pair after it. The fleet's census (12:31 BST): 36 nodes on population A, the network's genesis root 0x7e37a9fb; 21 stale nodes, each with a genesis root of its own, re-walking from 12:35 in thirds; dn3-g1 died a third time at 11:55:47 (the same OOM class on a rented box the likely reading; the fleet's hourly RSS per node with a restart above 32 GB is the guard until every node is on the tip). Lane D on main's order, done 12:36 BST: build-4's two entries cancelled before running; build-3 carries four strata on the fg6 harness (42f2c77f), 8 cores each under class measure: shape256 (3,000) and w4lossybase (3,000) running, shape64lossy (2,000) and w4shape64 (3,000) queued behind them on the 24-core pool; the lossy band at B = 4 across the injecting families is the complete lossy-base stratum (3,000 eras, 0 exhausted, r = 0.595). Build-1's queued attack-f8 rebuild chain cancelled (the point-B live census moves to build-3); what remains there started before the order (four lossy-share strata at +1 to +4 points, 16 cores each, about 900 of 3,000 eras; the point-A live census at 2^24 on 32 cores). The 17:00 cut committed at 2a595e1b with the 24,000-era coverage, its gate re-running. A shared-Mac fault class found at 12:3x to 12:4x BST: the class-v5 lane's shell command ran pkill -f "tools/ci/pre-push.sh" before its own gate, which killed every lane's gate on the Mac: the record's merge gate three times, the invention lane's landing twice (d6955381), the family gate's once (exit 144). The kill-by-name class the 6 October rule bans in scripts (kill-by-name-check.sh), applied by hand on a command line. The word to the lane: kill only your own gate by its pid; gates on the Mac do not share a lock. Reported to main. The research lane's commit 0ab27582 on counter-asic-4 (the mirror, 12:4x BST, ahead of the 15:00 clock; the crate suite green on the committed tree, 116 passed, 0 failed, build-2 12:38, master's new derivation test among them). It carries: (1) chip-model-v3.md section 5.12, the two chips with lane B's figures and marks (the 2 GiB SRAM store on one N2 reticle: 17x at zero shadow, 8x to 30x on the read band, 2.7x at k = 1 and 4.8x at k = 0.5 with the class v4 shadow, 3.7x and 2.0x at the card's whole shadow, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M and 18 to 24 months, a break-even cap of about USD 330 M to 1.7 B on the mission lane's model; layer 2 moving its capex, two dies at 4 GiB 15x and four at 8 GiB 13x; the custom HBM4E base die 6.5x to 14x untouched by the four layers; PIM structurally blind, 1.6 percent of reads in-bank at 2 GiB; the M5 Max at 0.78 microjoules the honest denominator, 3.1x the 5090) and 5.11's per-load note in the reopened wording; (2) the merge of master (the sub-version 3 line, the derivation recorder, the re-exported packs) and the per-load bias test's fix (judging only the bits inside each site's window mask; lane C re-reads on this id); (3) the class v6 document through section 9: the lead on the SRAM store, the per-tier schedule table with lane A's checked steps (6 GiB does not fit the 8 GB tier under the 75 percent rule; 5.5 / 8 / 11 GiB drops the tiers in the named order, about a quarter of today's measured consumer cards per step), the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB, the one card that pays rate for a larger working set), lane D's rings and band, the index fold as a layer-1 rule, the 5070 Ti pair, the x16 mixer at 11.4 ms loaded by the right method (admissible false on the measurement), lanes B, A and C taken in 7a to 7c, and section 9's served-line review with the wording proposed for the 20:00 word. Owed for 20:00: the 5090 size rows (the hash lane's v6 job), lane C's 15:00 re-read, lane D's 17:00 table, the two re-weighted packs' rows; each lands as a row with its label, or its default. Main's word at 12:5x BST on the kill class: the rule "no kill by name on the Mac, pid file only, ad-hoc shell lines included" lands in the agents' standing text with this record landing; the steward makes it a gate check that refuses pattern kills in scripts and logs the sender of every TERM a gate receives. The class-v5 lane's own line: the four pkill lines (12:3x to 12:37) stopped its own superseded gate runs as its tip moved under them; nothing of its uses a name or pattern kill again, its background gate started with its pid recorded and ended by that pid only; its current run (gate 17 on class-v5 79799452, 12:39) runs to its end. The census and the four-item pin taken by main; the clock as the shipper set it. Lane D's interim at 12:5x BST for the 09:00 report, the lossy-share curve at 1,000 to 1,300 eras per point: r rises 0.80, 0.88, 0.92, 0.96 as or, mul and mulhi go +1 to +4 points each; exhaustion appears at +3 (2 of 1,029) and reaches 1.4 percent at +4 (14 of 994); every exhausted era's class v5 last-resort scan passes at its first or second candidate (k = 256 or 257), so the band's edge is between +2 and +3 points of lossy weight and the scan does its job at the corner. Its cut 2a595e1b under the gate, then the mirror landing and the send to the research lane. The attack pass's F8 to 256 seeds landed at 12:37 BST: seeds p66 to p257 (192 new) at 2^24 on the freeze 1c420786 (binary 0f5c98dc, pairing e5a4ac5978462156), the window-model control, build-2 under class measure, validation 0 mismatches (hash_warp agreement on 37,440 warps). 184 of 192 within 1.2x at the top 0.1 percent (mean 1.023); 8 over (p110 1.3527x, p66 1.3403x, p234 1.3156x, p145 1.2750x, p77 1.2664x, p225 1.2457x, p248 1.2188x, p89 1.2065x), each with its hottest item at 263 to 432 reads of 2^31 and the hot-set verdict clear on the windowed control (largest excess X_f/f +0.60). Over all 256: 245 within (95.7 percent), 11 over; the rate at 256 (4.3 percent) is the gate's at 64 (4.7 percent) and the worst fell (1.3527x against p10's 1.5047x). The 6-sigma largest-bucket line flags 57 of 192 (p110 +61.67 sigma): the AP-F8-1 tail mechanism at its rate. Two seeds carry a predicted source, one-one-bit through a load, both passed by (c''') on the frozen tip: p212 (1.1915x, attempt 4, site instr 7, r5, last writer load at 2) and p225 (1.2457x, attempt 0, site instr 37, r5, last writer load at 36), to the hash lane for by-site attribution as the gate's tail was. Verdict PASS at the gate's reading: no card or chip gains a cacheable hot set on any of 256 epochs. The row and f8-uniform.md section (e) on the mirror's attack-pass. Still running: build-4's F9 (six chunks) and F1 (10^6), partials at 17:00. The node lane's named commit inside the 12:50 clock: 42ce0f07 on release-0.3.25-node, both mirrors, 12:39:37 BST, the sha with the steward and the shipper. Content: e0644958 (keygen, the record re-announce, the ceiling switch at 82,800; digest 1b37cb9d) plus four node fixes, nothing consensus: the ring self-check every 30 s over the last 2,000 records with the full scan on a generation change (node1's class, its known-failed test green); the snapshot digest stamp (a snapshot under another object or none refused, the node re-executing from genesis); the vetoed-node status (the count and the last veto on the status RPC and igneum_getNodeInfo, "stateFresh" false while any stands); the proof map's window (a proof leaves memory with its record at the 600-block window's end, the OOM class). Green before the squash on the same tree: exec 54 of 54, the kaspad check. The full gate set at gate priority on both boxes from 12:39:44 (every line by about 12:52), both canaries reading the Devnet 3 digest back at 1b37cb9d, the fast-time pair by about 13:00; the crossing watch at 68,400 on the seed from 12:50; the pin line after the last of those; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. The invention lane at 12:5x BST: the hash lane's 5090 rows for the two sound per-load packs reverse the GPU-side sign of rank 1: at class v4's own instruction count the per-load form costs the card 19 W MORE than the whole block unlocked (483.6 against 464.6 W) and 6.6 W more at the 1,300 lock, rate 1.3 percent under, 15 to 20 percent more per shadow instruction (19.7 to 20.8 pJ against 17.2); the dead 16 x 27 export's 13 to 14 W saving does not carry (a 16-instruction loop against a 144- or 256-instruction straight segment). Rank 1 keeps its place by the file's own rule (the chip's project cost about 2x against the card's 2 to 4 percent of watts) with the honest sign: the card pays, not saves. The second cut landed at 4315e992, the third (these rows) under the gate. The drawn-era re-read on 0ab27582 built on build-3 but starved (build-3's 16-core pool under lane D's three 24-core leases since 12:38): the coordinator moved it to build-4 at once through the lease pool under class measure (build-1 closed until the pin is named); the 15:00 numbers from build-4, the box named in the row. The class v5 lane's full gate on class-v5 79799452 (the tip on both mirrors) GREEN, 73 checks in 463 s at 12:47 BST, left to run to its end: 0.3.25's pairing row on the page (the freeze 1c420786, kit 65b47211 with the Intel worker held, the Arc read to 0.3.26 with the second PC dark), master merged through its latest (the 60x file taken whole from master after the merge reordered seven keys and duplicated three, values equal), the generated ledger files matching. Nothing of the lane's pending; the one future item the Arc B580 re-read on kit 65b47211 when the second PC is back, which moves the Intel row and sends the 0.3.26 upgrade line. 42ce0f07 reads every gate green at 12:48:10 BST: build 12:42 rc=0 (igneumd 8e17a60b, /srv/artefacts/0325-42ce0f07/node-lane), pow 19, consensus 134, core 177, miner 29, p2p-flows 38, exec 54, all at gate priority; the Devnet 3 canary set with digest 1b37cb9d unchanged, byte 6, the override refused, the 0.3.24 pin refused on the digest both ways; the testnet canary b2e856ed unchanged. The shipper has the line; the steward's matrix runs on it. Two inputs before the pin: the fast-time SUMMARY on 42ce0f07's artefact (about 13:00) and the 68,400 crossing on build-1's seed (the chain passes it about 12:54, the watch from 12:50). The reorg-unwind fix's 13:30 clock met at 12:48 on the same commit. The attack pass at 12:5x BST, the ends brought in: F1's 10^6 was one 40-thread census on build-4 (35 h); the harness now takes --start (attack-v5-frozen ebdb7d4a, smoke-tested: a 20-program census from index 5 writes rows 5 to 24), so the census is split by index range: build-4 keeps indices 0 to 349,999 (its running census, stopped by pid when its progress line reads 350,000; the flushed census.csv holds the lower range) and build-2 runs 350,000 to 999,999 at 80 threads under class measure (binary 42ee04c7, held since 12:48:40 BST after waiting 362 s for the pool to free on its own, no pre-emption). Both halves end about 23:30 BST. F9's six chunks hold on build-4 (48 cores); when build-2's F1 ends tonight the F9 remainder re-splits onto build-2 by seed range (rows keyed by seed, nothing lost), bringing F9's end from about 17:00 BST tomorrow to about 06:00 BST. Cores held: build-2 80 (F1 upper range), build-4 88 (F9 48, F1 40); build-1 and build-3 untouched. Partials at 17:00. RED, a first, at 12:48 BST: Devnet 3 STALLED AT THE CLASS V5 FLOOR. The seed's virtual DAA read 68,403 at 12:49:11, 12:50:23 and 12:51:09 with one sink (07055360), the last block accepted at DAA 68,399 as class v4 at 12:48:14; nothing at 68,400 or above reached the seed, node1 or the observer, no node logged a PoW rejection: no miner found an epoch-19 block on a chain that ran one a second. The nodes held epoch 19's state (the seed installed the streams for epochs 18 and 19 from its snapshot at 12:30). The cause (the fleet lane, 12:52): every miner's --worker is the hive package's igneum-worker-cuda, which runs generators 2, 3 and 4 only; the class v5 kit's worker (82b19cbde8557ea5, the one every v5 gate ran on) was never on any miner's worker path, only its packs were placed; the prepare of epoch 19 fails and the miner sits at 0 MH/s while the templates flow. The fast-time harness crossed this boundary green four times on pairs, which tests the node and the CPU engine, not the fleet's GPU workers or kits. The fleet places the kit worker on every box now; the 0.3.25 hive package and Windows payload rebuild with the kit's workers by 13:30 (the build-server lane); the Mac Metal worker's generator-5 read with the v5 lane by 13:10. The pin and the minute wait on the chain moving and the rebuilt packages; the 42ce0f07 gate set green, the matrix running, the ceiling cut's publish limit (DAA 75,600) standing still while the chain does. GATE RULE for the next cut (the record's and release-rules'): a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; the packs' presence and the kit's own tests never stand for it. The 0.3.24 move's read-back ("36 of 36 FETCHED on the pin") was a node reading; no reading of a worker preparing class v5 existed before the floor. The research lane at 12:5x BST: section 10 ("the floor") open in the class v6 document (counter-asic-4 after 91117093) with each floor lane's term, what the document holds measured for it, the default at 19:30 and the row owed; two measured rows the floor lanes start from rather than re-derive: the SM-sparse lane from 20.3b (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw, 460 against 451 W; 99.8 percent of class v3 at 4 W less; watts minus idle per MH/s never below base; the sparse shapes collapsing at the 1,300 lock; its new work the breakdown of the 99 W an idle SM does not save and whether an occupancy shape at full SM count moves it; the worker variants sp-w and the card-free --list-race check on counter-asic-4); the k lane from 15.1a (the GPU side measured per counted op: ARX 11.3 / 6.2 pJ, mul 13.9 / 8.3, mulhi 39.6 / 21.0, prmt 22.3 / 11.5, lop3 24.1 / 13.0, shfl 55.8 / 29.4, fp32 FMA 9.2 / 5.2, the int8 tile 1.4 to 4.1 per MAC; only the chip side claimed; the mix that maximises k priced against the GPU's own per-family cost, the shuffle 4.9x the add on the card). The thirty-ninth landing on master at 12:54 BST (26a3cbe6): the standing rule in CLAUDE.md. The node lane at 12:5x BST on the stall: the worker's refusal line is "program pack generator 5 is not a generator version this worker runs (2, 3 or 4)", faulting at 0 MH/s from the first epoch-19 template; the kit's class v5 worker was benched on 24 cards this morning and never placed on any miner's --worker path; the nodes read 0 PoW rejections and hand the right template (the CPU id-read from build-1 confirms epoch 19 as class v5). The fleet places the kit worker and its pack on every mining box, w-target first; the chain moves when the first card prepares. The record's lesson: a worker that cannot run the next class must refuse at the pack prepare, loudly, hours before the boundary (the plug, tune, play rule), and no hive tar ships without the class the object names. A second bug read off the stall: the pool admits at the next block's DAA (chain id 4464 past the floor) while eth_chainId answered the executed tip's id (4463 with the tip stalled at 68,399); the fix (eth_chainId and net_version answer the id a transaction sent now must carry, the status carrying both ids, the known-failed test on the stall's shape) a wip under its exec suite at gate priority since 12:54:27, landing as the SECOND commit on release-0.3.25-node over 42ce0f07 (nothing consensus, digest 1b37cb9d unchanged), its full gate set and fast-time pair by about 13:15; that commit the pin's node sha, 42ce0f07 if it reads red. THE CROSSING READS CLEAN. The first class v5 block (epoch 19, epoch seed a75c5624) was accepted on build-1's seed at 12:57:40 BST, 9 minutes 26 seconds after the last class v4 block, the minute the fleet's first kit worker prepared; then 13, 14, 71, 165 and 78 blocks a minute (the backlog clearing, the rate settling), DAA 68,547 at 13:01:37; seven stale-pack attempts refused between 12:59:24 and 13:01:10 (the harness's known-failed shape), none since; no state-wait, catch-up, stale-dataset or digest line on the seed, node1 or the observer; no honest block refused. Devnet 3 runs class v5 at byte 6 as the 0.3.24 object names (the v5 signal share 1,407 bps at the floor; the seed's template at 13:1x: epoch 19, class 5, version 1538, era the genesis, day 20,734; the executor serving epoch 19's stream, 869 records, root 0x1fd55139...4561). The pairing check holds three ways: the kit's igneum-pow (8f481459's tree, the freeze's hash object) names attempt 2, program id 3d375a55029e7e60 for epoch 19; the node lane's 0.3.24 pin miner (igneum-pow 1c420786) read the same id live at 12:56; the DMG's Metal worker on the Mac prepared epoch 19 against the live seed with the same id (869 leaves, 26 MH/s). The stall's two causes, both miner-side, neither in the object: every fleet miner's worker was the hive package's CUDA worker (generators 2, 3 and 4; it refuses a generator-5 pack with a line, the miner at 0 MH/s retrying, loud in the log and the plug-tune-play fault only on the dashboard), the DMG's Metal worker from the freeze's tree the same (the v5 worker path is the v5-kits lane's 5c9ed959, in class-v5 from e208dfea on; the freeze is the hash object, not the hosts); and a miner not told its node's exec RPC port cannot prepare class v5 at all, so every fleet loop needs --exec-rpc. The fix: the kit's workers (zip 65b47211) and --exec-rpc on every box; the hive, Windows and Mac packages from the kit tree (the hive and Windows payload carrying d84b1b6c / be23bc68 and e1bfd582 / 55722527 on the worker path; the Mac side closed on release-0.3.25 44d1815a, proto-metal from class-v5 79799452). The stall's cost: 9.5 minutes of blocks and every prover's share for that span. The standing rules from it (release rules 16 and 17 on ship-docs-0321 cb570365): the kit worker and --exec-rpc on every miner loop before any class boundary; a worker that cannot run the object's next class refuses at the pack prepare, hours ahead; a cut's packages are smoked by preparing the current epoch's pack on every worker binary they ship, on every platform, against the live object; memory against the container's cap. All of it on the class v5 page's section 0 at class-v5 2494f3f8 (both mirrors 12:59, master merged, its full gate running by pid). The second node commit 5f316c21 on release-0.3.25-node (both mirrors 12:56:22 BST) = 42ce0f07 plus the chain-id answer (eth_chainId and net_version return the id the pool admits at, the next block's DAA, 4464 past the floor; the status carrying both ids; the known-failed test on the stall's shape), nothing consensus, digest 1b37cb9d unchanged; EVERY GATE GREEN at 13:04:05 BST (build 12:58 rc=0, igneumd 3812b2a2, /srv/artefacts/0325-5f316c21/node-lane; consensus 134, exec 54, core 177, pow 19, p2p-flows 38, miner 29, all at gate priority; the Devnet 3 canary with digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged). 5f316c21 IS THE PIN'S NODE SHA. The one input before the pin line: the fast-time SUMMARY on 42ce0f07's artefact (the run waited 796 s for build-1's pool, 88 of 88 leased at or above v5, nothing to pre-empt; running since 12:55:54, v5 from epoch 8 at 13:04:19, the line about 13:10), a run on 5f316c21 after it. The shipper's close: the app tip 9a71e784 (crate 89e83df2), the DMG 43cd8c94 staged, the tarball 1ae1810d, move id m5f31-1; the pin about 13:25 after the SUMMARY, the matrix and the hive; the minute about 14:00 to 14:20 inside 14:53. The TESTNET_PARAMS v5-at-0 re-cut's default moved under the rule by the node lane: it lands through its full gate set on release-0.3.24-node 30 minutes after the seed reads the first ten class v5 blocks accepted clean, so at 13:32 BST unless main says otherwise before then; a red crossing would have meant no re-cut. The audit lane's 9070 XT row on master at f37f497b (12:55 BST, gate green on 33b0ad06), ahead of 13:30: 18.96 MH/s, watts "149.3 with the 0.3.25 knob (195.8 stock)", 0.127 MH per watt, the tuned text with the 24 points' flatness and the date, the source the status row with the job id; the note carries the grid's stock point beside the app's 202 W reading of 7 October, the two single-lever points, and names both 5090 denominators (3.5x behind at the class v4 1,200 MHz lock, 0.43; about a fifth at the 1,300 knee, 0.60); the qualifier drops when the cut serves. With f37f497b: the complete class v4 watts rerun (22 rows), the /income calculator, the /economics page, the governance line, the two served-text corrections with their ledger rows. The build-server lane has it to deploy. The hash lane's kit b on the 5090 (12:49 to 12:58 BST, all PASS; with the research lane and the floor lane): the mixer multiplier x8 against x16 costs the GPU nothing (137.73 against 137.72 MH/s, 320.2 against 320.1 W unlocked; 127.44 against 127.46, 212.0 against 211.7 W at 1,300), so the verifier's 1.86x per doubling is the whole cost of that draw; the shuffle-heavy table on the base program moves 7 W unlocked and nothing at the lock (a 2 percent term); the pinned class v3 program at 2, 4 and 8 GiB costs a tuned 5090 5, 11 and 14 percent of rate at the 1,300 lock (4, 8 and 10 percent per hash) and 3 to 4 percent unlocked, which corrects the layer 2 line: the size term is real at the knee (the page-walk cost the latency-bound regime exposes). Kit c (the multiply-heavy table) running; kit d (both tables inside the shadow block, the row layer 1 needs) exports on build-2 and runs after, about 13:45. W = 8 for the floor lane: the crate's width set is three fixed word widths (1, 4, 16; WIDTH_WORDS, the mix arrays, the emitters for CUDA, OpenCL and Metal, the verifier's fold), so a 32-byte load needs a generator and emitter change before any pack exists (two to three hours of crate work on the readwidth line plus the PC 1 row); the ask to main with its default: say so by 14:00 and the lane starts it on the readwidth branch (a research class, no consensus object); silence means W = 4 pins and the floor lane hears so at 17:30. The F8-256 attribution runs for p212 and p225 on build-3 (the attack-pass crate d08e1e0f built there at 13:01), rows by 16:00. Main's ids for the floor lanes, for the record: SM-sparse af65f8187569666d0, shadow k a3c9601a6d4686fe1, SRAM and dataset floor acecab7195ea66621, honest denominator a4d39e20a0762646d, invention a734c5330f17be3c2; the research lane delivered the two starting rows to each with their 19:30 defaults. Two more master-only deploys from the builder stream, checks ok (38 miners rows, 18 asserted pages, the checkpoint API and the explorer stats API): d28cf8fc at 12:50 BST (the explorer wording c4ca746f, the audit lane's ace5c294 with /economics, the /income calculator and the class v4 watts rows, the DEX lane's 9126e4d6 and 825d19bd) and f37f497b at 13:04 BST (the reference-apps b7f1e0d7 with /oracle's BLS-verified root, the 9070 XT knob row on /miners). No chip text changed beyond the audit lane's own landings. The fortieth landing on master at 13:14 BST (90b180f2). Main's word on W = 8 at 13:1x: start it, research class with no consensus object; the order on the hash lane: the 0.3.25 lock rows and kit b first, then the readwidth generator and emitter, the PC 1 row by 17:30; a miss means W = 4 pins, the floor lane told, the W = 8 row later as a v6 sub-version check. The 13:32 testnet re-cut on its default. A RED THE MOVE ITSELF WOULD TRIGGER, read on build-1 at 13:05 BST by the node lane: a node re-executing from genesis (the fleet's 21 re-walks now; every node at the move under the snapshot stamp rule) has its executor thousands of blocks below the chain, so its pool admits at the executor's next DAA, names the old chain id 4463 below the floor, refuses every relayed transaction signed with 4464 as a state-free fault and disconnects the relayer as misbehaving ("wrong chain id: expected 4463, got Some(4464)" on the seed and node1 from peers at 13:05); for the length of its walk, about 8 minutes, it drops every peer that relays a transaction, and at the move every node would do it to every other: a partition. The fix, a wip under its exec suite at gate priority since 13:08:06: the admission height is the larger of the executor's next DAA and the chain's virtual DAA plus one (eth_chainId, net_version, eth_sendRawTransaction and the relay read it), and a mismatch between the network's own two ids is a refusal, never a strike; the known-failed test is the re-walk's shape. It lands as the line's third commit over 5f316c21 (nothing consensus, digest 1b37cb9d), the full gate set and the fast-time pair on it by about 13:35; the pin waits on it. The second thing in those logs is the stale class, not a bug: the 21 nodes with a divergent execution state compute a divergent class v5 dataset, refuse every honest v5 block as invalid PoW and ban build-1's seed for an hour ("Reject(BlockInvalid)" on the fleet's side), cured by their re-walks in progress; a node that cannot check a v5 header for want of the epoch's state holds off, as designed. The crossing is clean on the honest side; the chain runs. The fast-time crossing on the 0.3.25 pair 42ce0f07 (12:55:54 to 13:08:50 BST) read green on every claim (rung 1 at 13:02:22, v5 at byte 6 from epoch 8 at 13:04:19, 12 of 12 ids equal to the CPU verifier's, the stale node refused, the restart step resynced in 19.1 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); its SUMMARY read FAIL on one harness check: the final epoch's row held one miner's line when the run ended at that epoch's boundary (the id equal to the CLI's); not a node finding; the check now reads the final row by its id (v5-fasttime 130562a2); the clean rerun on the same artefact from 13:1x, SUMMARY about 14 minutes after its lease. Lane D's 17:00 cut LANDED on master at 238100b0 (13:13 BST), gate GREEN (73 checks, 355 s) on 2a595e1b, four hours early; the research lane has the layer-4 line; docs/analysis/class-v6/family-gate.md carries the measured coverage (24,000 drawn eras, per stratum and per axis, the bound arithmetic), the rows, logs, scripts and the harness diff under docs/analysis/class-v6/logs/. Build-3: w4lossybase done (3,000, 0 exhausted), shape256 1,910 of 3,000, shape64lossy 1,895 of 2,000, w4shape64 queued, then the point-B live census on the family attack-f8 build (74784428); build-1 the four lossy-share strata near done and the point-A live census. The class v5 lane's full gate on class-v5 2494f3f8 (the crossing row, master merged) GREEN, 73 checks in 407 s at 13:06, run to its end by pid, nothing killed. The third node commit inside the shipper's 13:20 clock: d5b68fae on release-0.3.25-node, both mirrors, 13:14:12 BST = 5f316c21 plus the admission fix (a transaction admitted at the larger of the executor's next DAA and the chain's virtual DAA plus one on the relay, eth_chainId, net_version, eth_sendRawTransaction and the status; a mismatch between the network's own two chain ids a refusal, never a strike; the known-failed test on the re-walk's shape), nothing consensus, digest 1b37cb9d unchanged, pairing 1c420786; exec 54 of 54 and the kaspad check green on the same tree before the squash. The full gate set at gate priority from 13:14:19, every line by about 13:26; the fast-time pair asked on it; the 42ce0f07 rerun's SUMMARY (about 13:24) the gate's record on the same object. The pin's node sha d5b68fae if green, else 5f316c21. The steward's 0.3.25 matrix at 13:17 BST: node 5f316c21 with app tree 89e83df2 GREEN on all seven suites on build-2, build-3 and build-4 (no RED); 42ce0f07 complete green on the same three; build-1 out; at 13:21 the third sha d5b68fae core and exec GREEN on the three boxes, six of six: the pre-pin suite read closed. d5b68fae reads every gate green at 13:22:43 BST (build 13:15 rc=0, igneumd b0e7b8b5, /srv/artefacts/0325-d5b68fae/node-lane; p2p-flows 38, pow 19, consensus 134, exec 54, core 177, miner 29 at gate priority; the Devnet 3 canary digest 1b37cb9d unchanged, byte 6, the 0.3.24 pin refused both ways; the testnet canary b2e856ed unchanged): THE PIN'S NODE SHA IS d5b68fae. The fast-time SUMMARY PASS (cross-0325-42ce0f07-2) at 13:22:57 BST on the 0.3.25 pair 42ce0f07 (13:10:07 to 13:22:57 on build-1 under class v5: rung 1 at 13:16:33, v5 at byte 6 from epoch 8 at 13:18:43, the stale node refused, the restart step resynced in 11 s with the catch-up done, four sinks equal, 0 PoW rejections on honest nodes); the d5b68fae pair running side by side since 13:16:13 on its own cores and port base, SUMMARY about 13:30, the last input before the pin line. The reading behind the fleet's partition line at 13:17 BST (hub-1 at one sink, dn2-1 alone on its own branch, w-poison a third, dn3-g2 and dn3-q03 stuck at DAA 68,403 refusing every v5 block): epoch 19's class v5 dataset derives from the execution state after the epoch's reference block, the last chain block below the cut 19 x 3,600 - 600 = DAA 67,800: chain block 28,462, hash a75c5624 (the epoch seed), state root 0x1fd551393d (build-1's seed, node1-dn3 and the fresh node agree; the kit's stream names the same root). Any divergence of state OR numbering between 26,294 and 28,462 puts a node in a cluster that refuses the other clusters' proof of work and bans their relayers for an hour; root-equal at 26,247 was not the gate. The census now reads hash and root at 28,462 on every box (epoch 20's height moves to the last block at DAA at most 71,399); every cluster but the one on a75c5624 / 0x1fd55139 re-walks; build-1's observer node, the explorer's only source, is one of the drifted (its 28,462 another hash at DAA 67,787: the orphan-append class during its 11:22 re-walk, so the explorer's numbers are off by a few; the shipper has it). The cure is the move itself: every node restarted on the pin's binary re-executes from genesis under the snapshot stamp with the ring self-check running and lands on the one state; the gate on the minute is the fleet's census at 28,462 after the re-walks (31 boxes on the one state at 13:19:44, the rest the numbering class the move cures), with an unban of every held address per box once its root reads equal, since bans persist on disk across restarts; a box whose root there differs after a re-walk on the pin's binary is a new class and a stop. Lane D's measured correction at 13:2x BST for the full report: the lossy-corner exhaustion is a shape-256 interaction, not corner-wide: at the lossy cap the per-candidate rejection is 0.877 at shape 64 x 108 (0 of 2,000 and 0 of 1,000 eras exhaust), 0.923 at 128 x 54 (1 of 1,010), 0.980 at 256 x 27 (36 of 990, 3.6 percent; 24 of 670 at width 4); at r = 0.98 the independent-attempt figure is 0.98^256 = 0.6 percent, so the per-era correlation is about 6x, not the 1,000x the mixed-shape average suggested; the band rule stands either way (lossy families never raised), and the cheapest shape for the draw is also the fastest on the cards. The hash lane's attribution: run 2 (the attack-pass branch's own crate) reproduces p225's 1.2452x but not p212's (1.57x against the gate's 1.19x, a different draw, the crate differing from 1c420786); run 3 on the 1c420786 crate is the authoritative one, running. The W = 8 pow suite on build-2; the three state-term packs (w4, w32, w64 on +sh256x27+state, the node1 state file, --era-widths 4/8/16) export on its green; the read-width kit (those three, the v5-genesis pack, the two 5 October packs, which are string-seed class v2 packs the worker accepted on 5 October, no re-export) runs on PC 1 after kit d; the L2::64B hint variant is not in the worker exes, so it is lane 5's kernel line, nothing to build. STANDING RULE from the founder relayed by main at 13:2x BST, applied to every lane the coordinator runs and every default clock: work as fast as possible; anything doable in 30 minutes to 2 hours gets a clock inside that window, never a target hours out; fan work out (one pod per point, one box per variant) rather than queue it. The floor close is 15:45 BST. The coordinator's re-read of the 16:00, 16:30, 17:00 and 19:30 lines: the F8 attribution rows 14:00 (run 3 running, three minutes a census); lane C's drawn-era numbers 14:00 (an 80-s census on build-4) and its cut 15:00; the class v6 per-tier cost rows and layer 4's tests 14:30 (kit d about 13:45); the W = 8 PC 1 row 15:30 (the crate work fanned: the suite on build-2, the exports on build-2's slot, PC 1 the moment kit d closes); the floor lanes' rows 15:30 for the 15:45 close; the synthesis and the served-line review table 16:30; lane D's full report 16:30 with every stratum fanned across build-2's and build-4's free cores rather than queued on build-3; the DEX lane's swap UI 15:00 and the Sepolia verifier 16:00; the reference apps already served (b7f1e0d7 at 13:04). Main's word at 13:2x BST to every lane: while GitHub is suspended, landings go to the box mirror's master through the gate, never to Forgejo master, which is a rewritten copy replaced at cut-over by the box mirror's final tip; pushing a branch to Forgejo for safekeeping is fine, landing there is not. Relayed to every lane with the pulled clocks. The SRAM and dataset floor lane's row is complete at 13:18 BST, two hours inside its pulled 15:30 clock: the full row at 7bc9de4b and the clock references at 8e9588de on the box mirror's branch class-v6-floor-sram (safekeeping, no master landing), gate green on every push, all arithmetic on build-3; docs/analysis/class-v6/floor/sram-and-floor.md. What the 15:45 close carries: the capex wall on the corrected project floor (no chip project below about USD 23 M a year of miner revenue, IGN 0.03, USD 62 K a day; every DRAM-board project at a third of the network above about USD 340 M a year, IGN 0.44, USD 0.93 M a day, where the SRAM project also starts); the read width as the only wire lever on the SRAM die (66x at the hash's 4-byte width at zero shadow, 44x at W = 4, 31x at W = 8, 19x at W = 16 if the 5090 passes the PC 1 job, 36x at the measured w64 row); the shadowed die at 6x to 10x at the honest cards' whole latency shadow on the k lane's synthesised core, kept beside the k lane's sequencer-core row as the floor-k worst case, never under 2x by any shadow; the floor as a ticket lever (5.5 / 8.5 / 11.5 GiB = 3, 5, 6 reticles, USD 1,500 / 2,500 / 3,000; USD 5,000 per store is 20 GiB and retires every card under 32 GB; the 5090 pays 4 / 8 / 10 percent per hash at its knee and the M5 Max 12 / 20 / 22 percent of rate at 2 / 4 / 8 GiB, both measured); the four other candidates (per-era and per-block re-fill, straddling atoms, a second hot table) dead with numbers. Amendments after the close, each labelled with its time: the W = 8 or W = 16 PC 1 row (the hash lane), the k lane's shuffle row and its re-fold, the Apple rate curve past 8 GiB. The DEX lane closed with every clock met before the pull, all on the box mirror's master through the gate: the AMM live on Devnet 3 at 12:0x BST; the swap UI serving at igneum.network/swap since 11:36 with the Igneum Wallet bridge live from the 12:50 deploy; the Sepolia certificate verifier live at 13:3x (0xAf74f3F512081291D663Bb1d6b6d37E99e37D744, suite 10 of 10 on build-3, Devnet 3 checkpoint 2127 recorded final and one Devnet 3 balance proven on it); the one named gap: no on-chain link from checkpoint to state root yet (docs/bridge/light-client-bridge.md); final master 825d19bd. The forty-first landing on master at 13:35 BST (937cc82ae); during its branch push the hook "died of signal 15" once more (the merge's own gate ran green and landed), so a kill by name on the Mac still reached a gate at 13:3x: the steward's TERM-sender log is the read. STOP ON THE PIN d5b68fae at 13:29 BST, the fast-time pair: SUMMARY FAIL (cross-0325-d5b68fae), the failing check v5_ids_equal_the_cli_v5_id, a node finding: on epoch 9's attempt-3 seed ec0a8cf9 the d5b68fae miner and nodes drew program id 65b57e3b847d362e (its nodes accepting 4 of 4 on it) while the freeze CLI 1c420786 and the ab6f980b CLI both draw ebf64b32e2d84c5b, state or no state; the three other v5 epochs agree with the CLI. A node on the freeze's igneum-pow would refuse that epoch's blocks: a split on the first divergent seed, a chain split class. The 42ce0f07 and 39f127a1 PASSes met no such seed, so they do not clear it. The cause from the box's build log: the d5b68fae, 42ce0f07 and 5b673577 pairs were built "pairs_with": "igneum 05b21835 (detached) with uncommitted igneum-pow changes", not against the freeze 1c420786 (39f127a1 and c8f9b383 were, against ca3-v4-node commits 4c24903e and 0e4ec18a); every 0.3.25 node binary embeds "igneum-pow-v5/src", not the freeze's crate; rule 7's pairing broken in the node lane's build path. The orders: the node lane folds the freeze pairing (a clean rebuild from the freeze's exact igneum-pow, the build row's pairs_with read before any lease) and the ceiling re-cut to 90,000 into one commit (sha by 14:05, the gates and a new digest by 14:20, the SUMMARY with the seed in the set by 14:35); the build-server and fleet lanes read the live 0.3.24 miners' pairing path by 14:00 (if the live network carries the same divergence, the move is its cure before the first attempt-3 seed; 5b673577 is the live pin); the artefacts rebuild on the new sha; the pin about 14:35, the minute about 14:55 to 15:10 BST. The coordinator's order to the v5 lane: the pairing read-back on the rebuilt pair by 14:30 (the freeze CLI against the new sha's miner on ec0a8cf9 and the three other v5 epochs, id for id, and the live miner's path the same way). The record's rule for the pairing gate: the fast-time set carries an attempt-3 seed on every run (the epoch seeds of a run are its block hashes, so the divergent seed cannot be forced; the pairing row is the check that reads first); a pair's build row names its igneum-pow commit, and "uncommitted changes" in pairs_with is a refusal before any lease. Lane D's fan-out at 13:4x BST, one stratum per lease, class measure (every box's pool read 0 free at submission, each waiting in the measure class ahead of adv work): build-2 w1band (width 1 under the band, 3,000 eras, the fg7 harness with the refused-ratio column) at 16 cores, and the mixer verifier rows mx4m4g, mx4m8g, mx4m16g with the 256 x 27 shadow, one core each (the x16 row); build-4 w4shape64 (3,000) at 16 cores; build-3 the point-B live census (64 seeds at 2^24, shape 64 x 108 with a band era's weights) at 24 of 64 seeds PASS, and w4band (width 4 under the band, fg7) at 8 cores, 179 of 3,000; shape256 (3,000) and shape64lossy (2,000) COMPLETE; build-1 untouched (the point-A live census at 31 of 64 PASS, no test fired; the four lossy-share strata complete at 3,000 each); build-3's queued copies killed and their partial rows marked PARTIAL. The full report by 16:30 on the mirror's master through the gate; what has not finished by 16:00 goes in as a partial with its count. The corrected line for main: at the lossy cap r = 0.877 at shape 64 x 108 (0 of 3,000 across the strata), 0.923 at 128 x 54 (1 of 2,000), 0.980 at 256 x 27 (3.3 to 3.6 percent of eras in three strata). The hash lane's clocks at 13:4x BST: p225 reproduces on the 1c420786 crate (1.2452x against the gate's 1.2457x, by-site rows in hand, the close by 14:00); p212 does not: the tool at d08e1e0f over the 1c420786 crate draws a program at 1.5715x with a hot set ("site instr 5, r7, one-one-bit, last writer add at 4"), not the gate's 1.1915x attempt-4 program, because the gate ran a chain path (class v5 with the dn3 state) the pushed tool has no flag for; the attack-pass lane's exact command asked by 13:50, default: p212 reported as unreproduced on the pushed tool, labelled so. Kit d: the first two exports hung on a build-2 slot (a stale lock of the lane's own run, cleared); take 3 direct and bounded, packs about 13:45; PC 1 held by floor lane 1's two jobs, so kit d's job starts the minute the card frees and closes 8 minutes later (rows by 14:00 only if PC 1 frees by 13:50, else PC 1's free minute plus 10, inside 15:30; past 15:30 the microbench arithmetic stands). The per-tier cost rows and layer 4's tests delivered at 12:0x (scratch v4/ca4-v6-cost-rows.md), the kit b and c numbers folded in at 14:15. W = 8: the suite on build-2 (restarted 13:23 after a slot wait); the three state-term exports follow it on the same box; the PC 1 read-width job after kit d; the 15:30 row holds if the suite is green by 14:00 and PC 1 frees by 14:30, else W = 4 pins. The explorer lane's correction at 13:4x BST: the explorer's source is no longer the drifted observer: the build-server lane re-pointed the indexer unit, the observer and the public RPC at node1-dn3 (EVM 26870) at 13:25, and the three indexer tables were wiped and refilled from node1-dn3 from chain block 0 at 13:27 (about 3 min); balances, receipts and accounts are node1-dn3's, the DAG tables the observer process's reading of node1-dn3 since 13:25. The notice landing by 14:00: the header names node1-dn3 as the source since 13:25 BST, the observer drifted at DAA 67,787 and re-executes from genesis, a block list read before 13:27 may differ by a few blocks until the move; the same line on /block and /tx. eth_chainId on node1-dn3 answers 4464 since the floor, so the explorer's chain id is read from the node; every page printing 4463 as a fixed string (/build, /swap, /metamask, the nav's title) is one off, told to the build-server lane at 13:28. The attack pass's split under the fan-out rule, running from 13:30 BST, every lease class measure: F9 (900,000 seeds left on 1c420786) as twelve chunks: build-4 keeps the lower 85,000 of each of its six 150,000-seed ranges, restarted from each chunk's lowest missing seed (rows keyed by seed, a merge dedupes), six leases of 8 cores; build-2 takes the upper 65,000 of each range, six leases of 6 cores. F1 (10^6 class v5 programs): build-4 keeps indices 0 to 349,999 at 40 threads (at 76,000 at 13:19; stopped by pid at the 350,000 line), build-2 393,662 to 999,999 at 52 threads (its first 47,000 rows from 350,000 kept, merged by idx at the end). Cores held at 13:36: build-4 72 (F1 40, four F9 chunks of 8; two chunks waiting on lane D's 16-core w4shape64 lease there), build-2 24 (four F9 chunks of 6; F1's 52 and two chunks waiting): build-2 contested (lane D's w1band 16, the invention lane's per-load acceptance census on 0ab27582 48, the hash lane's attribution at class adv, the hash lane's igneum-pow suite at class release for 88 cores, which pre-empts every measure lease there when it starts; the class order decides). Ends at the measured rates if every lease holds: F9 build-4 halves about 04:45 BST, build-2 halves about 07:00; F1 build-4 range about 23:20, build-2 range about 05:40; the build-2 ends slip by their waits. The 15:30 reading carries the counts and re-stated ends. THE EXPOSURE READ at 13:50 BST (the node lane's fingerprints, the shipper's correction): THE LIVE NETWORK IS ON THE FREEZE. The igneum-pow tree each binary linked is the untracked igneum-pow-v5 copy beside its release worktree (the .cargo/config.toml paths override); every copy fingerprinted against git archive 1c420786 igneum-pow by two methods (the node lane's: find src -name '*.rs' | sort | xargs sha256sum | sha256sum; the build-server lane's: find . -name '*.rs' | sort | xargs cat | sha256sum | cut -c1-12): the freeze reads cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 and 29106189ca1e; the 0.3.24 line's worktree (vendor/igneum-node-0321, where 5b673577 and every 0.3.24 pin was built, the gate pair a3b1a2c9/cfa9f5ca, build-1's seed, node1 and the observer) reads the same on the Mac and both boxes; the fleet's shipped pairs the same (29106189ca1e); the kit workers on the freeze (the freeze CLI built at exactly 1c420786 on build-1, binary sha256 7ba781db, names Devnet 3's epoch 19 as attempt 2, program id 3d375a55029e7e60, equal to the 0.3.24 miner's live read). So no live node or worker diverges, no attempt-3 seed can part them, epochs 20, 21 and 22 are safe, no hub-side holding action; the shipper's 13:45 line to main withdrawn and corrected. What diverged: the 0.3.25 line's worktree (vendor/igneum-node-v5) carried a pre-freeze copy (fingerprint e01ea128fab1: accept.rs without the (c''') per-site distinct-index floor, MIN_DISTINCT_RATIO_V5 0.995 and its HotItemSite refusal; generator.rs and memhard.rs older); every 0.3.25 gate artefact c6629572 through d5b68fae was built on it, none shipped; on an attempt-3 seed it draws attempt 2's id where the freeze goes to attempt 3, the fast-time FAIL; replaced by the freeze's tree on the Mac and both boxes at 13:34 (fingerprints equal). The builds.jsonl pairs_with rows name the parent repo's HEAD, not the override copy, so they never said which tree was linked; the fingerprint is the only reading. The predictability: an epoch's attempt and program id are a deterministic function of its epoch seed, fixed 600 DAA (ten minutes) before the epoch starts, so any two trees compare ahead on every seed by both CLIs; across the freeze and the pre-freeze tree the hash lane's census puts the share of seeds that differ at 2.4 percent (112 of 4,600), a per-epoch roll that only matters where a pre-freeze binary is live, and none is. The boundaries at 1.0 DAA/s from the 13:01:37 read: epoch 20 at DAA 72,000 about 13:59 BST (seed fixed 13:49), epoch 21 at 75,600 about 14:59, epoch 22 at 79,200 about 15:59. RULE 19 and the rebuilt sha inside the shipper's 14:05 clock: 6ccaf9e9 on release-0.3.25-node, both mirrors, 13:41:28 BST = d5b68fae plus rule 19's build-time half (consensus/pow/build.rs fingerprints the linked igneum-pow tree by the shell's method and refuses the build unless it equals packaging/pow-freeze.txt, "cbc5bd0a… 1c420786 class-v5-freeze 2026-10-07", unless IGNEUM_POW_FREEZE_CHECK=0; IGNEUM_POW_FINGERPRINT in every binary's strings, on igneumd's start lines and igneum-miner's engine line; the handshake field on the next commit with its own gate) and the Devnet 3 ceiling re-cut to 90,000 (the publish limit DAA 82,800, about 16:53 BST; the digest moves, named by the canary). The wip's check, pow and core suites read "igneum-pow fingerprint cbc5bd0aa10585c8 (the freeze)" at 13:40. The full gate set at gate priority from 13:41:35 (the build on build-1 with the fingerprint strings read back from both binaries, six suites on build-2, both canary sets), every line by about 13:55; rule 19's known-failed case on build-2 beside it (the pre-freeze copy under the override must fail the build); the fast-time lane's watcher fires on the artefact (about 13:45), reads the fingerprint string before its lease, its SUMMARY with the attempt-3 seed about 14:05; the v5 lane's flip case (the harness taking POW_BIN, the freeze CLI, beside FORK_BIN) reads every v5 epoch's id on the pair against the freeze CLI, 13 minutes a case, within 15 minutes of the sha. The testnet v5-at-0 re-cut landed by its default at 13:32 as 3ffcf83b on release-0.3.24-node (its pairing the freeze), its gate set from 13:40:39, its digest from its canary. The pin line follows 6ccaf9e9's last gate and the SUMMARY. The v5 page's section 0 carries the STOP and the pairing rule's new line at 3b894a4d. The counter-asic-4 documents landed on the box mirror's master at 13:35 BST as 868fea52 (full gate GREEN 73, the stamp on c21f1f38): docs/analysis/counter-asic-4-research.md, docs/design/class-v6-rotating-family.md (the branch's text at 08641162), docs/analysis/chip-model-v3.md (5.12 and the capex correction), tools/ci/export-exclude.txt (+4); igneum-pow/src, igneum-pow/tests and proto-cuda stay on counter-asic-4; no served page changed. The research-landing lane's next: floor-sram (8e9588de) about 13:55 from the Mac on its green stamp (the full gate RED 5 of 73 on build-3, all box-environment classes, the steward told as owner: the gate is the Mac-side script that reaches the boxes from inside), floor-k with tools/chip-model/rtl about 15:45, floor-sm documents by 15:30, the denominator and invention lanes on their words. The 6a5fa763 deploy at 13:42 BST (the explorer's source notice and chain id from the node, b092fa17; /swap reading eth_chainId at load, 46eb9e4b; /metamask on 0x1170 and the public RPC, the nav pill, /faucet and /build on 4464 with the floor dated): Devnet 3's eth_chainId moved from 4463 to 4464 at the floor; checks ok, 19 asserted pages. Lane C's 14:00 numbers: the no-era half in hand on 0ab27582 (the sound form 0.927, 234 of 256, unchanged on the fixed instrument; the control sh256x27 now reads sub-version 3's own 0.682 because the merge brought master's (a') pass to that spelling, so the two sit on one instrument); the era sweep on build-2 on the first free cores; the 15:00 cut after it. The attack pass at 13:46 BST: build-4's F1 lower range stopped by its pid file (83,000 distinct rows kept from indices 0 to 349,999) and restarted at 8 threads from its lowest missing index 78,082 (the 4,900 interleaved rows above it redone and deduped by idx at the merge), freeing 32 cores for the census lane; at 15:30 the shard restarts at 40 threads the same way; its end moves from about 23:20 to about 00:15 BST. A print-only move of the sha at 13:45 BST: c9ad753a on release-0.3.25-node, both mirrors = 6ccaf9e9 plus igneum-miner embedding the full IGNEUM_POW_FINGERPRINT=<64 hex> string on its engine line (igneumd carried it; the miner's binary had only the sixteen-character start-line form, so the pair's read-back on both binaries failed on the miner); no code path, object or digest change. The Devnet 3 digest on the pin: 2066aa57505e5ecbd585d061364abb0032d5b5b29cc41c54f4b38cb81c2ba6eb (the ceiling at 90,000; the publish limit DAA 82,800, about 16:53 BST); the fingerprint cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 (the freeze); the 0.3.24 pin refused both ways on its canary. Its full gate set at gate priority from 13:45:59 (every line by about 14:00, both binaries' strings read back in the build log); 6ccaf9e9's own gate set and rule 19's known-failed self-test by about 13:55; the fast-time SUMMARY on 6ccaf9e9 (the same node code and object) about 13:59 stands as the gate's record; the v5 lane's flip case on the pair follows; the pin line after the last of those. The forty-second landing on master at 13:54 BST (c340a9d4a). The shipper's pin candidate: c9ad753a on release-0.3.25-node (d5b68fae plus rule 19's build fingerprint against the freeze, the ceiling re-cut to 90,000, the miner's full fingerprint line; digest 2066aa57; the publish limit DAA 82,800 about 16:53 BST; the fingerprint cbc5bd0aa10585c8 in both binaries' strings); the app tip b5be4edf (crate 89e83df2); the gate set on c9ad753a by about 14:00; the fast-time SUMMARY on 6ccaf9e9 (the same node code and object) about 13:59; the matrix cells on 6ccaf9e9 stand; the v5 lane's read-back on the 6ccaf9e9 pair stands for c9ad753a; the fleet's binary the build-server lane's seed pair on c9ad753a (the freeze's crate, 29106189ca1e); move id m9ad7-1; the pin about 14:35, the minute about 14:55 to 15:10. PC 1's queue at 13:5x BST: floor lane 1's two jobs (floor-pc1-build-2 "build patched sp1-gpu-server", floor-pc1-restore) hold the card since 13:06; queued behind them, published and signed: kit d's fetch and run (9 minutes) then the read-width run (W = 4, 8 and 16 under the class v5 state term, each its own draw on generator 5 with the era and the node1 state, plus the v5-genesis reference and the 5 October w4 and w64; the W = 8 pack exported at 13:48 on the w8-v5 branch, efb68fce on the mirror, suite green; about 20 minutes). The coordinator's order: floor lane 1 names its end minute by 14:10; an end past 14:30 means its job yields the card at 14:30 (pid file, state restored first), kit d and the read-width run take 30 minutes, its job resumes after; so kit d's rows and the W = 8 row by 15:00 at the latest, inside the 15:30 close. The F8-256 attribution rows at 14:00 BST. p225 (the gate's 1.2457x): reproduced on build-3 with the attack-f8 tool at d08e1e0f over the pow crate at 1c420786 exactly, 1.2452x over the window model at 2^24 nonces, the hot-set verdict clear on both controls, the hottest item 0xb7e000 at 332 reads with no saturated or lossy source. By site: the excess sits at site 4 (instr 23, source r7, window 2^23 items, offset 1, last base writer mad at 21), 1.30 percent of its reads into the top 0.1 percent of items against 0.103 flat (12.6x), with site 9 (instr 37, r5, window 2^22, offset 2, last writer load at 36; the gate's predicted one-one-bit source) second at 0.38 percent (3.7x); every other site at its flat share. Both sites read full index entropy (15 of 15 and 14 of 14 bits) and a largest 256-item bucket at its window expectation, so unlike the morning's tail (a bucket concentration) p225's residue is a value-level concentration on specific items from a mad-written index, the class the gate's one-one-bit prediction names, carried mainly by the mad site and a quarter by the load site it predicted. p212 (the gate's 1.1915x, attempt 4): not reproduced; the pushed tool has no class, state or day flag, so its default path draws a different program for seed 212 (1.5715x with a hot set, the string-seed class v4 draw); the run on the gate's own line (its binary, day 20733, class v5, the dn3 state) on build-2 never started (0 of 12 cores free 13:29 to 13:54 with a higher class ahead; build-1 closed); the attack-pass lane runs p212 with --diag 1 on its own harness when its lease frees; default, p212 stays "predicted source only" in the record. No consensus object moves. THE PIN IS NAMED AT 14:08 BST: release-0.3.25-node = c9ad753a (the 0.3.24 pin 5b673577 plus igneum-miner keygen, the proof-record re-announce, the proving-fee ceiling switch at DAA 90,000 in the Devnet 3 object, the ring self-check every 30 s, the snapshot digest stamp, the vetoed-node status, the proof map's window, eth_chainId and the admission at the chain's height with the network's other id a refusal, rule 19's fingerprint, the testnet re-cut beside it); pairing the class v5 freeze 1c420786, fingerprint cbc5bd0aa10585c8576e71e37a8ee47a045ae51754e9ddf749d0c21e6a535f88 read back in both binaries; Devnet 3 digest 2066aa57505e5ecbd585d061364abb0032d5b5b29cc41c54f4b38cb81c2ba6eb; the app tip b5be4edf. Every gate green at 14:01:14 BST (build 13:47 rc=0, igneumd 68526b25, igneum-miner d4f4c98d, /srv/artefacts/0325-c9ad753a/node-lane; miner 29, core 177, exec 54, pow 19, consensus 134, p2p-flows 38 at gate priority; the Devnet 3 canary with the digest, byte 6, override refused, the 0.3.24 pin refused both ways; the testnet canary b2e856ed). On the same node code and object (6ccaf9e9): every gate green at 14:00:56; the fast-time SUMMARY PASS (cross-0325-6ccaf9e9) at 13:57:35 with the pairing read before the lease as the freeze fingerprint on both binaries (13:44:45 to 13:57:35 on build-1: rung 1 at 13:51:10, class v5 by signal at byte 6 from epoch 8 at 13:53:28, 12 of 12 ids equal to the freeze CLI's, the stale node 73 of 73 refused, the restart step resynced in 10 s with the catch-up done after 5 s and nothing of its own mined during it, four sinks equal at 662, 0 PoW rejections and 0 submit timeouts); the v5 lane's read-back PASS id for id on epochs 8 to 10 (13a54a0dd793ca79 attempt 2, d35cd0e9cb186d00 attempt 1, 6104176723170d72 attempt 2, miners 3 of 3 against the freeze CLI at exactly 1c420786); the matrix green on build-3 (build-4's consensus cell unreadable under load 510, the steward's clean run once the load is under 96, its line by 14:25). The FAIL seed re-read: on ec0a8cf9 with the FAIL run's era, day and epoch-9 stream, igneum-pow at exactly 1c420786 draws attempt 3, program id 1f1cf82877f46ee6 (8f481459 the same), so NEITHER id in the FAIL was the freeze's ("cli v5 ebf64b32" came from the release worktree's pre-freeze copy, the pin miner's 65b57e3b from igneum-pow-v5/src); the fingerprint pairing is the gate that catches both; the miner's side of that seed cannot be re-read offline (igneum-miner reads ids from a node's template only), so the pin rests on the fingerprint equality and the record says the attempt-3 seed's miner id was not re-read. The ceiling lands at 90,000 (epoch 25) about 18:53 BST, the publish limit 82,800 about 16:53. The re-execution reading: 27,000 chain blocks in about 8 minutes, RSS peak 12.6 GB on IBD plus walk. The fleet fetches m9ad7-1; THE MINUTE = the last FETCHED plus ten, about 14:30 to 14:40 BST; the Mac and HiveOS entries at it; Windows on PC 2's return; the card after the Windows entry. The minute's gate on the fleet's side: the census at 28,462 (a75c5624 / 0x1fd55139) after the re-walks, the unban per box once equal, the first checkpoint lock after it. The attempt-3 rule's shape: the miner's half of a seeded read did not exist; today it is the v5 lane's kaspa-pow program-id binary on its fork branch (class-v5-node 22920380, the template prepare's own path); igneum-miner program-id with the same flags and output line is the first item on the next node line, after which the harness points at the miner. The testnet v5-at-0 re-cut, landed by the default and amended once for its pinned digest constant: 0d05e795 on release-0.3.24-node, every gate green at 14:03:47 (pow 19, exec 47, miner 28, consensus 134, p2p-flows 38, core 175; the testnet canary with digest 1da30c10e164784ffbf5bf216ef3bf84a2d5da212317b1e535c9850fe14aba2f, byte 6 from genesis, the old-object seeds refused; the Devnet 3 canary on that line cc902690 unchanged); the rows with the testnet lane, with the note that the go seeds should run the 0.3.25 pin's node code with that object (one merge commit onto c9ad753a and its gates after the move's read-backs). Rule 19's known-failed self-test waits on build-2's pool cores (it pre-empted the attack pass's F1 upper range at 14:03 by the class order, 48 cores, 2,023 s in, 4,000 fresh rows kept; re-queued from index 397,292 holding 52 cores; cost about 25 core-hours, the build-2 F1 end about 06:30 BST). The attack pass's p212 run alone on the gate's exact line with --diag 1 --by-site (build-4, 8 threads, 13:56 to 14:01; binary 0f5c98dc, day 20733, class v5, the dn3 state): ratio reproduced 1.1917x (the gate's 1.1915x); hot-set verdict clear; 6-sigma buckets64 flagged at +91 sigma. The excess is one site: site 9 (instr 35, src r6, k_off 2 offset 0, window 2^22) carries 1.789 percent of its reads into the top 0.1 percent, 16.4x its flat share, index entropy 13.981 of 14 bits, the largest 256-item bucket 1.75x the window expectation, saturated source 0; the eight hot positions are site 9 in iterations 0 to 7; every other site at full entropy and its bucket at expectation; the predicted-source site (site 1, instr 7, r5, one-one-bit through a load at 2) reads 0.237 percent, the ordinary 2x of a 2^23 window, so the prediction is not the excess; the hottest items (0x000010 at 296 reads, 0x00000d, 0x00000e, 0x3c001f, 0x18001a) low addresses near the window base. Verdict: p212 is the AP-F8-1 tail class (a per-site bucket concentration at one narrow-window site, 0.019 bits short), not a lossy source (the log at /srv/builds/igneum-wt-attack-v5/p212-diag/p212.log on build-4). The hash lane's reading of both: p212 the bucket class, p225 the value-level class the one-one-bit prediction names; in both the predicted-source line points at the wrong site, so the prediction stays a hint and the by-site histogram is the attribution. The consequence for class v6's layer 4 (to the research lane): the per-site bucket bound at about 2x that would refuse the morning's four refuses neither of these (1.75x and none); the value-level test catches p225; a bucket bound near 1.5x would take p212 at a clean-seed cost nearer 3 to 6 percent. The AP-F8-1 ledger paragraph amended with it on the hash lane's next gate run (ordered). The research-landing lane's landings: floor-sram documents on master as de3d32af (13:55 BST; the lane's text at 8e9588de; full gate GREEN 73, the light gate on the merge; the gate pid rule kept) and floor-invention documents as d28a7656 (14:03; the lane's text at 033ff8d8; full gate GREEN 73): docs/analysis/class-v6/floor/sram-and-floor.md and invention.md; waiting on floor-sm (15:30), floor-k (15:45, with tools/chip-model/rtl), floor-denominator (no word yet), then the counter-asic-4 close follow-up after 15:45. Two more deploys from the builder stream, checks ok (21 asserted pages): 9a029677 at 13:50 BST (/metamask reads eth_chainId at load, 0x1170 pinned as the fallback, read back equal to the public RPC's answer) and 7902e235 at 13:55 (/build's networks table and /faucet name 4464 since the class v5 floor; the faucet signs with the node's chain id); the build-server lane's lease-pool memory rule in its gate (a lease declares its GB, the box ceiling 100 GB with the hands' residents counted; the shipper's order after the 12:06 OOM kill of the seed). Lane C's drawn-era re-read on 0ab27582 at 14:0x BST, run on build-2 (build-4's pool never freed, the waiter withdrawn, named in the row): the sound per-load form (16 x 256 x 1) accepts 254 of 256 seeds under drawn eras at 0.819 rejection per candidate, mean accepted attempt 4.3 (no-era on the same binary 234 of 256 at 0.927); the form at class v4's count (16 x 144 x 3) 254 of 256 at 0.811; every sub-block of 36 instructions or longer 0.80 to 0.84 under eras; the iterated 16 x 27 form 66 of 256 at 0.991 under eras and 128 of 256 at 0.979 no-era, dead on both instruments; the class v4 shape through the same binary reads sub-version 3's own 0.666 and 0.682. So the per-load prototype's verdict of 00:0x was an instrument artefact as the record reopened it, and the sound form stands at 0.82 to 0.93 per candidate with the dataflow rule in execution order as the named fix. The cut with these rows and the 5090 rows lands by 15:00. Floor lane 1 (SM-sparse) at 14:00 BST: its PC 1 jobs are run-ca4-pc1-floorsm-5090-20261008 (the ladder at the 1,300 lock, since 13:07, a 66-minute cap, the card free by 14:13) and the memory-clock ladder at the lock (about 20 minutes); floor-pc1-build-2 and floor-pc1-restore are the prover-floor lane's; every rented pod of lane 1's destroyed (spend USD 27); the stock rows, the decomposition and the self-tune in docs/analysis/class-v6/floor/sm-sparse.md at ccafd9a4 on the mirror; the lock and memory-clock ladders the two rows owed for 15:30. The coordinator's PC 1 order at 14:12: floorsm to 14:13, kit d to about 14:22, the read-width run to about 14:42, memclk to about 15:05 (republished behind them), the 7600 card-in at 15:05 (the hash lane: any Thunderbolt housing on any PC 1 port, the job keys on the new card against the 10:04 baseline; the pass about 50 minutes, rows by 16:00: detect and VRAM, 8 GB: the 1 GiB prototype dataset and the genesis 2 GiB floor fit, 4 GiB fits at about 5.4 GiB needed, 8 GiB does not; the class v5 and v4 fingerprints and the stock bench on the OpenCL kit worker; the app's own rate and watts; the AMD knob grid as on the 9070 XT; the Efficiency, Balanced and Maximum rows; the dataset rows at 2 and 4 GiB from the class v3 packs ds29b, ds30b; the 5.5 GiB row by interpolation, labelled, since the exporter takes power-of-two datasets only; a 5.5 GiB pack is a crate change for tomorrow unless main wants it today, default not today). The founder's order through main at 14:4x BST: Devnet 3 comes back first, the users' cut second. The sink-age guard has no switch (service.rs:1131 hardcoded), so the node lane cuts the hotfix now; the fleet, hub-1 and build-1's four nodes move onto it by a +0 file on the fast-time PASS alone (about 15:00), the full gate set and both canaries running behind for the node-only 0.3.26, a re-move if the set finds a red (nothing risked, the chain being dead). release-0.3.26 open at 822f8767 (the version bump only, the app crate unchanged); its DMG, hive and Windows entries re-cut on the hotfix sha and published at a minute after the network is back. PC 2 back and mining as of 14:4x: its queued jobs run on logon (the 0.3.25 install take first, the sign.ps1 self-test, the UI lane's two, the hash lane's Arc read); the 0.3.25 Windows entry on a clean take, the 0.3.26 one on its own. The DEX lane's /swap fix in its gate at 14:4x (the pools table 640 px wide at 768 px with no overflow, the sentence in a wrapping line under the table). The record's forty-fourth landing's merge gate killed by signal 15 at 14:4x BST on the Mac, a second kill since the rule landed; the steward's TERM-sender log is the read; the merge re-run. THE HOTFIX landed at 14:42:44 BST as f8da7515 on release-0.3.25-node (cold_start_replays: Err only for a node that synced nothing or whose retention root is above genesis; a node holding the chain from genesis replays with a stale sink, one line said; the known-failed test cold_restart_tests::a_node_holding_the_chain_from_genesis_replays_whatever_the_sinks_age; nothing consensus, digest 2066aa57 unchanged); the guard was 10 * 60 * 1000 hard-coded at exec/src/service.rs:1131 with no env, flag or config field; the shipper's prepared 4831c372 dropped. release-0.3.26 = 602bce8c (the bump plus the pin f8da7515; the app crate unchanged). The clock: the seed pair and tarball about 14:52, the fleet fetching from then, the fast-time PASS about 15:27, the fleet, hub-1 and build-1's four on it at about 15:35, the gate set and canaries behind for 0.3.26, a re-move on a red; the users' 0.3.26 entries after the network is back; the testnet go cut re-cut on f8da7515 after. The first block's time to main from the shipper. The 1.5x test's measured row ahead of 15:30 (the fleet hand on RunPod secure cloud, 14:28 to 14:39 BST, pods destroyed, USD 0.62 of the 60 incl. a re-rent loop fault that rented five extra 4090s for 14 pod-minutes, all destroyed by 14:36): the class v5 base (v5-genesis) against knob 3 (hl-k3-sh1024: the 1,024-instruction shadow block at 27 passes, 4x the shadow ops, a class v5 research pack on generator 5), the kit worker d84b1b6c, --batches 250 --batch-log2 24 --block-warps 1, watts the mean of nvidia-smi power.draw over the busy window. RTX 5090 (driver 595.91.07, sm_120): base 140.83 MH/s at 442.7 W (3.14 µJ per hash, fingerprint ae74193ddad19e19 equal to PC 1's), knob 3 111.07 MH/s at 551.1 W (4.96 µJ; at the full 60 s it sits on the 575 W limit at 110.0 MH/s, 5.23 µJ), fingerprint d0d9eccde24b30af. RTX 4090 (driver 570.195.03, sm_89): base 62.41 at 279.3 W (4.48 µJ), knob 3 62.64 at 439.2 W (7.01 µJ), the same fingerprints. Reading: knob 3 costs the card 1.58x the energy per hash (5090) and 1.57x (4090), the same on both architectures; on the 5090 it is power-bound and reads as 21 percent fewer MH/s, on the 4090 the rate holds and the watts climb 61 percent; per shadow instruction the long block costs 0.40x the 256-block's (the per-pass overhead amortised); the 4090/5090 rate ratio 0.44 on the base, 0.56 on knob 3. For the founder's 1.5x: the GPU pays 1.58x for this knob while the k lane's chip-side figure for the same knob is its row; knobs 1, 2 and 4 not benched today (2 has no GPU knob, the k lane agrees; 1 and 4 are new ISA, priced by the microbench until a generator line exists). Logs under the scratchpad's 1p5x/fb-1p5x-5090 and -4090. The DEX lane's /swap fix committed on dex-devnet3 (the syncing and no-answer sentences out of the pools table into a wrapping line under it; both tables fixed layout and normal white space; the row reads "RPC syncing" or "no answer"), checked at 768 px with the public RPC at block 0: no overflow; its first landing's full gate killed at 14:4x by another lane's pkill -f tools/ci/pre-push.sh (the kill-by-name class again), the landing re-running, on master before 15:00 unless killed a third time. The record's forty-fourth landing's re-run merge gate read RED at 14:5x on that same /swap clip at 1600 px dark (the sweep renders the live page while the RPC re-executes), so the record lands after the DEX fix is on master. The forty-fourth landing on master at 14:5x BST (e694030f, after the DEX lane's /swap wrap 92b6da6f reached master at 14:48 and cleared the sweep's red). THE INTEL ROW CLOSES at 14:46 BST: the Arc B580 on the second PC reads the rebuilt kit 65b47211 EQUAL at its logon turn (run-ca3-pc2-v5-intel-bench-20261008: v5 fingerprint 82b19cbde8557ea5 = expected, match True, check PASS, 10.794 MH/s quiet; the v4 control 892b6d55a7ddcfcb PASS at 10.718; both self-tests 96 of 96; the host's "rotr_var rewritten to the shift form before the build" line present, sub-group size 32 with sub_group_shuffle_xor), so the rotate fold was the whole Intel fault, the sub-group patch stays unapplied, and the class v5 kit reads one fingerprint on six platforms: CUDA (RTX 4090), Metal and Apple OpenCL (M5 Max), AMD (RX 9070 XT), Intel (Arc B580), the CPU verifier. The page's Intel row at class-v5 916925f5 (both mirrors 14:51); the 0.3.26 line to the shipper by its rule: the post-freeze class-v5 line with the Intel kit in, 0.3.25 on 1c420786 as published; the shipper carries the Intel kit into the first app cut after 0.3.26. PC 1 at 14:50 BST: no job taken since 14:13 (kit d, the read-width run, the memclk ladder, the card-in detect all "no uploads"), the default ran at 14:48: the signed restart job kind for the app (restart-app-pc1-20261008-cardin); if the app is polling it restarts itself and the queue drains in order; if it is hung or gone only the founder's hand at PC 1 brings the runner back (the ask with main since 14:36). At 15:00 with no job started: kit d's rows and the W = 8 row miss the 15:30 close (the op mix the microbench arithmetic, W = 4 pins), the 7600 pass and the 5.5 GiB rows move to PC 1's return. Floor lane 1's close row to main and the research lane at 14:50 with the memclk ladder labelled owed; its file complete at 32132943. Floor lane 2 (shadow k), the design sweep at 14:5x BST (synthesis-only, 8 lanes, ASAP7 TC 0.70 V, gate-level random-input VCD at two run lengths with the steady state solved; k absolute at N3 against the 5090's 6.2 pJ at the 1,300 lock, 11.3 at stock, the M5 Max 6.9): base (32 regs, 256 imem) 186k cells, 6.9 pJ per lane-op (2.4 clocking), N3 3.5, N2 2.5, k 0.31 / 0.56 / 0.50 (stock / lock / M5 Max); (1) the 64-register file (40-bit word) 268k, 9.7 pJ, N3 4.8, k 0.43 / 0.78 / 0.70, a new ISA on the GPU side (in energy about free on NVIDIA, 255 registers per thread; rate paid only when occupancy drops below the latency-hiding point); (3) the 1,024-instruction imem as built (a flop array) 325k, 12.0 pJ, N3 6.0, k 0.53 / 0.97 / 0.87, measured on the GPU at 1.58x energy per hash for 4x the shadow instructions; (3) with the imem as a 4 KB SRAM macro (2 to 4 pJ per 32-bit read, shared by the lanes) about 7.2 pJ, k about 0.32 / 0.58 / 0.52; (4) the drawn select tree 187k, 6.85 pJ, k 0.30 / 0.55 / 0.50, nothing on either side; (2) 32 lanes and (2') 32 lanes at 16 regs in sim, clock 15:30; (5) all four together in ABC on build-3, clock about 16:00. The reading: the 64-register window is the one robust knob (+0.22 of k at the lock, per lane, not amortisable); the long block adds little once the imem is SRAM; the select tree adds nothing; (1) + (3) as built reaches k about 1.2 at the lock but a chip maker builds the imem as shared SRAM, bringing it to about 0.81 (0.45 at stock), and wider SIMD amortises the fetch further; k 0.85 is not reached by any knob a chip maker cannot amortise away; the DRAM board under 2x at the lock needs the register window AND the long block AND the honest card at its knee, and holds only if the chip's imem cost stays unamortised, which it does not. The node column (claimed from TSMC's headlines: N7 to N5 x0.70, N5 to N3E x0.72, N3E to N2 x0.72; the 5090 and 4090 on 4N, N5 class; the M5 Max N3): base 6.9 ASAP7 / 4.8 N5 / 3.5 N3 / 2.5 N2, k at the lock 0.78 / 0.56 / 0.40, the GDDR7 board at the lock 2.4x / 2.8x / 3.2x; the 64-register core 9.7 / 6.8 / 4.9 / 3.5, k 1.09 / 0.78 / 0.56, the board 2.0x / 2.4x / 2.8x. The one line: of the 2.8x at k 0.56, the N5-to-N3 node step is worth 0.4x (a factor 1.17, claimed); the rest is the memory system (3.6x at zero shadow at the lock) less what the class v4 shadow takes back on the card's own node; on the card's own node the base core sits at k 0.78 and the 64-register core at 1.09, so "near 0.9" is reached node-for-node by the window alone; what it does not survive is the node step a chip project buys (an N3 core gives back the 0.4x, an N2 core 0.8x). The placed 8-lane core in detailed route on build-4 at nice 19 (about 16:00). Branch class-v6-floor-k. The hash lane's reading of the 64-register window: not exportable inside 20 minutes: eight registers fixed in four places that must agree bit for bit (the generator's operand draw modulo 8 and the register init from one seed word each; the three kernel texts r0 to r7 selected by (i + 1) & 7; the CPU verifier's register array; the warp's hash fold over the eight), a 64-entry window needing an init rule for the 56 extra registers (a design choice) and a fold rule for the output, then the emitters, the verifier and the vector check: a half-day line; the GPU-side figure modelled: 64 live registers a lane on top of the kernel's forty-odd puts a thread at about 110 of its 255 registers, occupancy to about half, the rate expected to hold under the latency-bound read chain (the 5090 hides about 330,000 ops a hash, chip-model-v3 5.7), the energy per hash to move little, the per-lane register traffic the unmeasured term; the half-day line can start after the 7600 pass if main wants it tonight (default not tonight). The research-landing lane: class-v6-floor-denominator at fc265d8d landed on master as d461e365 (14:50 BST; denominator.md plus the three app/igneum-app/tiers files; full gate GREEN 73); floor-sm (32132943, sm-sparse.md only, 717 lines; the worker patch on the branch) in its gate, landing about 15:03; k by 15:45; the close rows within 30 minutes of 15:45. Two deploys at 14:53 BST, checks ok (21 asserted pages): d461e365 (the DEX lane's 92b6da6f: /swap's RPC-syncing and no-answer lines under the pools table, both tables wrapping) and c8ce4b52 (the UI lane's site-fee-words on main's order: the dev fee as the fixed 1% fee with the app's Settings sentence on /miner and /dev-fee, "switch" and "switchable" gone from the fee card, the "Off with" row and the description metas; no "switch" string served on /miner). No chip text changed. The hotfix f8da7515's full gate set and both canaries read green at 14:50 BST (exec 55 with the dead-chain test, the mixed-version step HANDSHAKE on the unchanged digest), so THE SECOND MINUTE IS 15:05:00 BST, named on the gates rather than waiting for the fast-time pair: every box at +0 (81 of 97 fetched at 14:57, the rest by the pull), hub-1 and build-1's four by hand; the fleet's tarball 29f11d85 (igneumd 07a522f3, the miner unchanged eead4d0c, both fingerprints the freeze's). The merge default taken: 33 solo miners stopped at 14:53 to 14:57 (the fastest branch 122 under the epoch 21 cliff at 75,600, past which branches never merge); they restart with the move and the branches merge inside epoch 20. The 0.3.25 Windows entry skipped for good (a 0.3.25 Windows node would deadlock); the Windows line lands with 0.3.26 (602bce8c; the installer's copy-step fix on that tree by 15:30). The next readings: the first block on the rejoined chain, the replay rate, the first lock. Floor-sm (32132943, sm-sparse.md only) landed on master as 69335fc1 at 14:58 BST (full gate GREEN 73); the landings today: 868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1; open: floor-k by 15:45 with tools/chip-model/rtl, the design document's close rows within 30 minutes of 15:45. PC 1 is back: kit d closed on the 5090 (run-ca4-pc1-v6d-packs-5090-20261008, 14:51 to 15:0x BST, all PASS; rows with the research lane and floor lane 5), the runner's stall 38 minutes (14:13 to 14:51, the founder's hand or the restart job). The op-mix row inside the shadow block: against the same worker's w4 base (119.95 MH/s at 308.2 W unlocked; 100.55 at 190.5 W at 1,300), the shuffle-heavy table costs the block 155.5 W unlocked and 80.6 W at the lock (level with the stock table's 152 and 84 this morning), the multiply-heavy table 104.6 W and 62.0 W (31 and 26 percent less), the rate flat within 0.4 percent: the weight table is a 30 percent lever on the block's watts on Blackwell, with the sign the microbench gave for the multiply end and smaller magnitudes than its arithmetic on both ends. Floor lane 5's hinted w64-l2: 92.35 MH/s at 369.1 W unlocked (23 percent under w4, 1.56x its energy per hash) and 37.59 at 164.1 W at the lock (2.3x), dead at the knee as at stock. PC 1's queue: the read-width run (the W = 8 row about 15:30), floor lane 1's memclk ladder, the 7600 detect about 15:5x and its pass (the first 7600 row about 16:00, the stall's slip); the register-window hand for 16:30; the 5.5 GiB kit from the worker lane at 16:00 with the rented 5090 row behind it. Lane D at 15:1x BST, every stratum COMPLETE: w1band 3,000 (build-2), w4band 3,000 (build-3), w4shape64 3,000 (build-4), shape256 3,000 and shape64lossy 2,000 (build-3), the four lossy-share points 3,000 each (build-1), the F8 label space's p2 to p65 and p212 to p225 through the sigma form (build-2); point A DONE on build-1 (64 seeds: 45 PASS, 3 beyond 1.2x, 2 hot sets p38 and p54, both REFUSED by the class v5 floor at 0.9932 and 0.9945 in the floor read on build-3); point B at 54 of 64 on build-3; the x4/x8/x16 verifier rows resubmitted on build-3's free cores after waiting on build-2's pool since 14:5x; 38,000 drawn eras in all today, about 90 core-hours; the 16:30 report holds with sections 6.4 (the lossy curve per shape), 6.5 (the width-4 floor decision), 6.6 (point A), 6.8 (the seven known-failed seeds through the sigma form, the bucket bound retired into the bit read) in the tree; point B and the verifier rows by 16:00, as partials if not. The floor-invention knee-row amendment (3951528d) landed as 66c3401e at 15:12 BST (full gate GREEN 73); the landings today: 868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1, 66c3401e. The fast-time SUMMARY PASS (cross-0325-f8da7515-2) at 15:17:51 BST on the hotfix f8da7515 (the freeze fingerprint on both binaries read before the lease; 15:04:51 to 15:17:51 on build-1: rung 1 at 15:11:28, class v5 by signal at byte 6 from epoch 8 at 15:13:20, 12 of 12 ids equal to the freeze CLI's, the stale node 78 of 78 refused, the restart step resynced in 6 s with the catch-up done after 3 s, four sinks equal at 662, 0 PoW rejections); the first run on the same artefact (15:03:21) read the crossing green too, its FAIL line the late joiner's wait letting two epochs past the observation window into the id rows (harness scope, fixed); the cold-restart class is the node lane's unit test, the pair cannot read it. The shipper's preview 1 at 15:1x BST: preview-26-1 at 57476931 on the mirror = the coordinator's f2781776 plus app-ia-26 e4773cf0 (item 4, the Tune page), release-0.3.26 f44baa25 (602bce8c plus install-detach-26 b39d5dd5, the take-3b copy-step fix) and the preview mark (state.preview from IGNEUM_PREVIEW at build time, appended after the version on the About line and the footer, empty on a public cut; no constant on any branch); the build-server lane cuts the kit, the cross with the env, the payload with the f8da7515 Windows pair and PC 1's host (host-0326 ahead in PC 1's queue), the install takes on PC 1 and PC 2; the Mac DMG by the Mac chain and the install over the founder's app by the shipper's hand; each machine's version and time to main. One red on e4773cf0: ui/heat-region.test.mjs:137 (a resting card's wording), the UI lane's by 15:35; the preview ships with it named, the public 0.3.26 app cut waits on green; take 3c (the public 0.3.26 Windows entry) on f44baa25 behind the preview takes. PC 1 at 15:14 BST: the founder's restart of the app at 15:06 ended the read-width run at 194 s (exit -1, "script was ended") after its three stock rows landed: v5-genesis 118.83 MH/s at 423.5 W, W = 4 under the state term 117.54 at 430.9 W, W = 8 117.54 at 451.5 W; so THE W = 8 ROW EXISTS AT STOCK (the rate equal to 0.01 MH/s, 4.8 percent more energy per hash; with floor lane 3 and the research lane); the 1,300 lock rows and the W = 16 state-term row owed from a republished run (run-ca3-pc1-readwidth-5090-20261008-b, behind the detect and the memclk ladder, about 16:30). The runner had already resumed at 14:51 on the signed restart job (kit d 14:51 to 15:02, the read-width run from 15:03), so the founder's hand restarted an app that was polling; no harm beyond the lost rows. PC 1's queue: the 7600 detect, the ds55 kit fetch, the memclk ladder (about 25 minutes), the read-width run b, the shipper's host preview build, then the 7600 pass (the OpenCL bench with --cards-off on the new key, the grid, the tier rows, the 5.5 GiB rows on the 7600 and the 5090). A caveat on every PC 1 row since 14:2x: the 5090 reads about 13 percent under the morning on the same packs and worker (v5-genesis 118.8 against 135.9), a host-side change with the eGPU swap; the next job's card line reads the PCIe link, the first suspect. The 5.5 GiB kit done (the worker lane, ds55-v5 at b57045fb, the emulated worker's self-test PASS on the 5.5 GiB pack; the kit on build-1, sha 2d7f55e8) and with the fleet lane for the rented 5090 row. The forty-fifth landing on master at 15:27 BST (6ae577e40). THE CLASS V6 FLOOR CLOSED at 15:28 BST, 17 minutes ahead of the 15:45 clock on the ship-on-green rule, every lane's last row in, on the mirror's counter-asic-4 (docs/design/class-v6-rotating-family.md section 10; the tip 725d2945 at 15:27; the full gate green on the branch; the landing on master by 16:30). THE TABLE (10.0 with 10.0e), the honest tier's measured class v4 joules per hash over the chip's modelled joules, the chip's core the k lane's synthesised sequencer core with the 64-register window (10.0c: the one knob a chip maker cannot amortise, k 0.78 at the lock at N3; the card's window cost modelled, labelled) and the per-unit floor (k 0.18) beside it as the worst case: the RTX 5090 at its 1,300 MHz knee (2.33 µJ): GDDR7 board 2.4x (2.8x without the window; 4.0x at the unit floor), HBM3 stack 2.9x, SRAM die at the genesis width 4.3x; the RTX 5080 at its 1,100 MHz lock, the honest NVIDIA floor (2.06, measured; lane 4's finding that the floor is the 16 GB Blackwell card, not the 5090): 2.2x, 2.5x, 3.8x; the Apple M5 Max (1.40): 1.5x, 1.7x, 2.6x; stock rows: the 5090 3.5x / 4.1x / 6.2x, the 4090 and H100 in 10.0. The node row: 2.0x against a chip on the GPU's own node, 2.4x a node ahead, 2.8x two nodes ahead (node-for-node the window core is k 1.09); the honest tier moves to the next node with every GPU generation while a chip must re-tape-out. SM-sparse: no change on any card (measured on the 5090, 4090, H100: 1.3 to 3.9 percent at best; the residual the clock domain). W = 16 killed on measured energy on four cards at stock and at the 5090's knee (+25 to +34 percent per hash on the card against the chip's +33). STATED PLAINLY: the GPU-tier floor is about 2.2x to 2.4x per joule at the knee against the chip anyone can build, under 2x only against the Apple tier; Monero's RandomX measured 1.0x to 1.5x beside it. THE CAPEX WALL (10.3): no rational chip project of any kind below about USD 23 M a year of miner revenue (IGN 0.03); every DRAM-board project at a third of the network above about USD 340 M a year (IGN 0.44); the project cost moves the threshold 5x, the chip's edge 1.4x. THE SERVED LINE in two units: under 3x per joule at the knee (2.2x to 2.4x with the window), under 1x per hash over its 180-day class life only above about USD 300 M a year of miner revenue (10.0a). THE FOUR CLASS V6 CHANGES: (1) the op mix stays class v4's with the lossy families capped at base (0 of 3,000 eras exhausted under the band; a multiply-heavy table lowers the card's premium a quarter but the chip's further, mul and mulhi k 0.03 to 0.08; the shuffle weight costless to the card and can rise inside B = 4 if the chip's butterfly k reads high); (2) no SM-sparse default (--sm-sparse auto off, on in Efficiency and Balanced at its measured 1 to 2.5 percent); (3) the dataset schedule 5.5 / 8.5 / 11.5 GiB (the 5.5 GiB step measured on a rented 5090 at stock: 3.5 percent of rate, about 4 percent of energy, the non-power-of-two mapping no cliff on sm_120, safe to adopt at the v6 epoch; about 9 percent at the knee, interpolated) with the read width pinned at 4 words (8 measured not free at +4.8 percent of the card's energy for 0.2x of the die's shadowed edge, 16 never); (4) the 64-register window per lane as the core shape, its GPU side modelled until measured. The rotation schedule adopted (10.0d): hourly 8,766 / weekly 52.18 / family 2.03 / vote at most 2.03 extra boundaries a year, the 6 h vote window. Precedents sourced (10.0b): RandomX 46 months to a chip at 1.0x to 1.5x; Ethash 36 months to a chip worse than a GPU, 14x today; Kaspa 21 months, 167x to 725x. MISSING AT THE CLOSE, each with its default in the document and owed as an amendment with its own minute: the k lane's 32-lane rows and placed core (about 16:00; the +30 percent placement and the register-file gating roughly cancel, provisional); the card's measured window cost (a half-day generator line); lane 1's memory-clock ladder; the W = 8 lock row (16:30) and the RX 7600 8 GB-tier row at 5.5 GiB (16:00 to 16:30); lane D's full report 16:30; lane C's drawn-era F8-form read. THE 5.5 GiB ROW measured two hours ahead of 17:30 (the fleet hand on a rented secure 5090, 15:19 to 15:23 BST, USD 0.32, the pod destroyed; the kit igneum-ca3-ds55-kit-20261008.zip sha 2d7f55e8 with its own worker d43be462, program id 73bcbfe8ccf988f1 in both packs): the pinned class v3 program at 1 GiB 141.48 MH/s at 325.6 W (2.30 µJ, fingerprint 90f794dd556f7a3b, the pin, 1,914 MiB used) against 1,476,395,008 words (92,274,688 items, not a power of two: loads are (src * words) >> 32) 136.56 MH/s at 305.3 W (327.6 steady; 2.24 to 2.40 µJ), fingerprint 23ced07a4d28b465 (the new pin, stable over two passes), the self-test PASS 96 of 96 lanes, 6,522 MiB used; the --batches 500 passes 141.38 and 136.54 with the same fingerprints. So the genesis floor costs a 5090 3.5 percent of its rate at stock, about 4 percent of energy per hash, no cliff from the mapping, on the 2 and 4 GiB stock rows where the interpolation put it. Caveat: that host capped the card at 328 W on both packs (the 1p5x 5090 on another host pulled 443 to 575 W), so the µJ figures are capped-card numbers; the rate and fingerprints stand. The emulated worker's known-failed counterpart reads 96 of 96 bad lanes on the old mapping. The 7600's 8 GB reading and the 5090's knee rows at 5.5 GiB from PC 1 after its queue, as amendments. The attack pass's 15:30 reading (counts at 15:21 BST), two non-zeros sent at once: F9 to 10^6 on 1c420786: 135,836 of the 900,000 new seeds drawn (build-4 99,456 across its six lower chunks, build-2 36,380 across its six upper), 0 exhausted, 0 panics, max attempt index 32: one seed, 718097 (build-4 chunk 4), accepted at index 32, past the record's "0 past 31" line but nowhere near the 256-attempt cap; the histogram tail 24: 5, 25: 2, 26: 2, 27: 1, 28: 1, 32: 1, the geometric tail at its rate (one in 136,000 at 32 against the 10^5 record's one at 30); not a finding: the exhaustion gate is the cap and the deterministic last resort, both untouched; the record carries the max as read. F1 to 10^6 class v5 programs: 172,310 distinct programs done (build-4 83,000 of its 350,000 lower range, build-2 89,310 of the upper on four 13-core parts), differential mismatches 0, verifier mismatches 0, 0 panics, programs over 5 percent: ONE, attack-f1/392513 (attempt 0, 6,912 to 6,561 per iteration, 5.0781 percent, 13 of 256 per pass), the same saving to the digit as the v4 10^5 letter miss attack-f1/37341 (AP-F1-1); the next worst 369298 at 4.6875, 373345 at 4.2969. Under the ruling on AP-F1-1 (gate (1) re-worded to compressible beyond the honest compiler's own simplification; a letter miss at honest-compiler parity is a PASS) a letter miss to be read at parity: the section 7.3 and 7.4 readings (explain, emit-c, the compiler pass) running, the parity verdict within the hour; if the compiler does not find the same 13 it is a finding on the v5 bound (AP-F1-1's v5 half reopens). Ends: F1 about 05:00 BST (build-4's lower range back at 40 threads from 15:30, about 01:30; build-2's parts about 04:40); F9 about 11:30 BST tomorrow (build-4's lower halves at 3,400 seeds per hour per chunk the long pole; build-2's upper halves about 08:30, taking more of build-4's range when F1's parts free their cores). Two pre-emptions on build-2, none on build-4. The shipper at 15:2x BST: the founder's Mac runs preview 1 since 15:21:53 (the DMG 94327b68 from preview-26-1 57476931, installed over 0.3.24 by the engine's own helper, the state reading version 0.3.26 preview "preview 1", the node on the f8da7515 pair replaying); PC 1 and PC 2 follow through the job runner once PC 1's host-0326 lands. Build-1's seed and node1 replayed on f8da7515 from 15:06:39 to the sink at 15:13:47 (7 min 8 s), 94 peers, the sink advertised again; the chain stands at 72,001 until one miner runs; the one-miner word to the fleet lane at 15:23 (the heaviest branch's box, the rest as their sinks converge; dn3-q03 and dn3-relay to a wipe and resync, their branch mined past the floor under the old rule). The 0.3.26 public stage complete (DMG 6f717c78, hive e3e4482c); its minute after the first block. MAIN'S CLASS V6 BUILD ORDER at 15:3x BST (the close 725d2945 in; the no-consensus-code hold lifted by the order), five lanes fanned under the founder's clock rule, each sent with its default: (1) the hash lane, the generator: the 64-register window per lane with its init and fold rule, the index fold (layer 1's remedy for the era-stride bit; the known-failed set p4, p8, p10, p15, p34, p212, p225), the op-mix re-weight table (13,11,6,10,8,8,7,2,6,4) behind the fold, W = 4 unchanged, the ds55 mapping as the dataset form; four packs (window, fold, re-weight, all together) exported by 21:00; (2) the census lane re-spawned on the four packs through the sub-version 3 harness on build-3 and build-4, PASS or FAIL by 22:30, a dry PASS on the freeze's pack by 18:00 as its readiness line; (3) the node lane, the object: the class v6 object with the dataset schedule 5.5 / 8.5 / 11.5 GiB tied to state at the era cut, the family bank's first entries as admissible flags, the floor DAA on Devnet 3, the digest, the worker-smoke rule and the fast-time crossing with the cold-restart and template cases, by 23:30; (4) the shipper, the cut: 0.3.27 as the class v6 line, the pin tomorrow morning on the gates, the Devnet 3 flip at a floor at least 90 minutes after the pin, the fleet on the kit workers first, Mac, HiveOS and Windows at the minute, the card after; release-0.3.27 opened tonight after 0.3.26's minute; (5) the audit lane, the served chip page rewritten to the close's sentence and the node column, the harness and the scoring rules published with it, on master by 17:30 (the 20:00 hold lifted by the order). The first packs and the census verdict to main with their times. Floor lane 2's remaining sweep rows at 15:2x BST (synthesis-only, ASAP7, N3 claimed, GPU measured; absolute k at the 1,300 lock): (2) 32 lanes, 32 registers: 5.55 pJ per lane-op ASAP7, 3.9 N5, 2.8 N3, 2.0 N2; k 0.63 / 0.45 / 0.32; the GDDR7 board at the lock 2.7x / 3.1x / 3.5x; (2') 32 lanes, 16 registers: 4.2 / 2.9 / 2.1 / 1.5, k 0.47 / 0.34 / 0.24. The register-file cost is linear in its entries (16 to 32 entries +1.35 pJ, 32 to 64 +2.8 pJ per lane-op at ASAP7), the one term a chip cannot amortise; the imem and sequencer amortise 1.35 pJ from 8 to 32 lanes. The shuffle (routed): 1.24 pJ per lane-op ASAP7 against the card's 29.4 at the lock, k 0.021, the lowest drawn family. The mix optimiser over the layer-1 band lifts the unit-floor k_eff from 0.097 to 0.137 (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0) and the core's k by about 15 percent. (5) all four together in ABC on build-3 (about 16:15); the placed 8-lane core in detailed route on build-4 (about 16:00); the crossbar, scratch and int8 tile rows after them. Amendment 1 to the class v6 floor close (15:3x BST, counter-asic-4 after 725d2945): the k lane's routed 32-lane butterfly reads k 0.011 to 0.021 (the card pays 29.4 pJ at the lock for a move the chip does for 0.63), the lowest of every drawn family, and its mix optimiser over lane D's band puts the best genesis table at add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0 (+42 percent of k_eff on the unit floors, +15 percent on the core: 0.56 to about 0.64, the window core 0.78 to about 0.9); change (1) moves from "the op mix held at class v4's" to "the band's best mix as the genesis table", subject to one acceptance pass through lane D's harness (ordered by 18:00; the census lane's neighbouring table at 256 of 256 both ways the fallback); the edge moves about 0.1x in the card's favour at the knee (2.4x to about 2.3x with the window); the core32 row in (k 0.45 at the lock at N3). The coordinator's default to the hash lane: the re-weight pack on the amended table unless main says otherwise by 17:00, both tables exported if free. The shipper took lane 4: release-0.3.27 opens tonight after 0.3.26's first block and minute (the bump only; the node line release-0.3.27-node from the object cut); the runbook at scratch r0327/RUNBOOK-0327.md: 0.3.25's twelve steps plus the worker smoke per platform and the attempt-3 read before the pin, the fleet on the kit workers first, the root gate off for a move after which executors start from nothing, every node with --unsaferpc, rules 16 to 19 in their places; tomorrow's pin clock stated as a time on the three inputs (packs 21:00, census 22:30, object 23:30), the flip's floor at least 90 minutes after it. The forty-sixth landing on master at 15:38 BST (3ce4fd7e5). MAIN'S AMENDMENTS to the class v6 build order at 15:5x BST, from two external reviews the founder accepted: (1) the generator's 64-register window carries the liveness rule (the fold forming each load address consumes all 64 registers; the result depends on the whole window; a liveness tool is an acceptance test beside the census) and the op-mix target is the k lane's optimiser split (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0); (2) the served chip text does NOT take the 725d2945 sentence: the close is amended by 17:00 into three separate statements, energy, economic and response capability, with the lifetime claim and the USD 300 M / 340 M safety-boundary wording withdrawn (a programmable chip survives epochs on firmware), and the audit lane serves the amended text by 18:00; (3) three research lanes beside the build (connected state a4d3518190ad011fc, mixed FP32 aa943688eaa06c538, multi-family adversary a1a9876a88f5a72fc) with rows from 18:30, feeding v7 not tonight's cut unless the connected-state row passes its gate before the object closes at 23:30. Relayed to the audit, research and hash lanes with the clocks. The five lanes' takes: lane 1 (the hash lane) fanned at 15:50: hand A (the window) on reg64-v5 off w8-v5 with the amended spec (the address fold consuming all 64 registers, the end fold over the whole window; ptxas registers, occupancy and spills on the 5090 and 4090 beside rate and watts for the k lane by 18:00), hand B on class-v6-fold off ds55-v5 (the index fold before the stride rotation with the known-failed seven as the per-site index-bit test; the re-weight on the k lane's split, 16,14,4,12,4,11,10,2,10,0 in draw order, sum 83, as hl-v6-rw, the census lane's 13,11,6,10,8,8,7,2,6,4 as hl-v6-rw2 if cheap, hl-v6-foldrw on the k lane's table; the suites on build-3; the packs byte-seed on the node1 state with a drawn era, generator 5, to build-1, the fold pack first); hand A's hl-v6-win and the all-together pack by 21:00. Lane 2 (the census lane afb2fb655385dc259) at 15:4x: per pack (1) the sub-version 3 acceptance with the (c''') per-site floor and the bit-level era-stride read (lane D's fg7 harness, the class v5 crate plus the family-gate diff), (2) attack-f8 at 2^24 on 64 seeds with the window control by site against the pack's state, the hot-set verdict and the known-failed set (p212 and p225 added for the fold pack), (3) the attempts census over the pack's epoch stream; fanned one pack per box, class v5; the f8 point the long pole (45 to 100 core-hours per 64-seed point, about 90 minutes on 48 cores; four packs on two boxes fit 21:00 to 22:30 only with 48 free cores each, which build-4 under the attack pass's 88 and build-3's 24-core pool do not give now); the dry PASS on the freeze's pack by 18:00 as the readiness line, the clock stated when it lands. Lane 3 (the node lane) at 15:4x: the object on the fork branch class-v6-node off release-0.3.25-node at 6e04f7fc (carrying the cold-restart and genesis-stream fixes), program-id first (lifted from the v5 lane's kaspa-pow bin as igneum-miner program-id by 19:00); the fields, each with its own digest arm entered only when set and a key in override-60x.json: program_class_v6_activation_daa (the floor; Devnet 3's value set tomorrow by the floor cut at the pin's publish minute + 7,200 rounded up, at least 90 minutes after the pin; tonight u64::MAX on every network, the devnet-suffix profile for the crossing at 60x), class_v6_dataset_steps ((height, GiB) pairs 5.5 / 8.5 / 11.5 with the state rule's constants: 64 bytes a record, the era-cut read, the genesis ceiling; the item count derived by the ds55 mapping's rule), class_v6_family_flags (a bitset: bit 0 the window, bit 1 the fold, bit 2 the re-weight, bit 3 the lossy band at base; off means not drawable), the class signal byte 7 (CLASS_SIGNAL_V6) stamped from the floor, packaging/pow-freeze.txt as a per-class list with the class v6 entry, tools/ci/worker-smoke.sh for the worker rule (reads the object's fields from the node binary, refuses a cut without one PASS line per platform), the fast-time crossing by the fast-time lane with the --cold and template-at-boundary cases (in its harness since 336639b1); its three questions to the hash lane by 21:00 with defaults (items = floor(GiB x 2^30 / 64); the four bits as listed; the freeze = the last green commit on ds55-v5 at 23:00, class-v6-freeze). The 6e04f7fc go-cut pair landed at 15:33 (the testnet lane's thread). Lane 4 (the shipper): release-0.3.27 opens after 0.3.26's minute; the runbook r0327/RUNBOOK-0327.md. Lane 5 (the audit lane): the old sentence's anchors on every served page staged (home, the litepaper's chip model and table, /miner, evidence row 17, the X35 and X36 ledger rows and pins), the 10.0 scoring definition (whole-card joules per hash over whole-chip joules per hash, the card measured under class v4 with the shadow on, the chip's memory modelled, the chip's shadow priced on the synthesised core and on the per-unit floor), the class v5 harness links to the class-v5 branch's sections 14, 13 and 0 on the git host (moving to master's path on a merge); waiting on the research lane's amended text by 17:00, the landing by 18:00. The register window's first measured row ahead of 17:00 (the hash lane's hand on a rented secure 5090, 16:1x BST): the pinned class v3 base 141.74 MH/s at 303.1 W (2.139 µJ, 30 registers a thread, 24 blocks per SM) against the arithmetic-only window pack hl-reg64 (two interleaved 32-register programs, twice the work per hash by construction) 80.38 MH/s at 308.6 W (3.839 µJ), 96 registers a thread by ptxas and the worker, 0 B spill, 20 blocks per SM (3,400 of 4,080 resident warps, 83 percent). Per unit of work the card is level with the base (160.8 base-equivalent MH/s against 141.7; 15.0 nJ a load against 16.7; the watts level): on Blackwell the 64-entry window costs no energy, no spill, and the 17 percent occupancy loss does not reach the rate under the latency-bound chain; the "half occupancy" model was pessimistic. The 4090 row and the full-chain form on both cards (the address fold over all 64 registers, hl-reg64c) before 17:00. The build-server lane's lease-pool memory rule on master as 5636a0d4 (15:36 BST) and installed on the four boxes at 15:37 (lease sha 82cc0564): a lease declares its resident memory (--mem N or "about N GB" in the label, default 8), the pool waits rather than take the box past 100 GB with the hands' residents counted, the holder line carries the figure; the cause the 12:06 OOM kill of the seed under a 31 GB attack binary. THE REGISTER WINDOW'S MEASURED SET, complete at 15:45 BST on the hash lane's rented secure 5090 and 4090 (the lane's own stamps read CEST; the record carries BST; USD 1.22, the pods destroyed): the 5090 arithmetic-only window pack hl-reg64 (two interleaved 32-register programs, twice the work per hash by construction) 80.38 MH/s at 308.6 W (3.839 µJ), 96 registers a thread, 0 B spill, 20 of 24 blocks per SM (83 percent occupancy), against the pinned class v3 base 141.74 at 303.1 W (2.139 µJ, 30 registers): per unit of work level (160.8 base-equivalent MH/s against 141.7; 15.0 nJ a load against 16.7; the watts level); the 4090: base 62.67 at 208.9 W (3.333 µJ, 29 registers) against the window 31.57 at 210.3 W (6.663 µJ), 104 registers, 0 B spill, 16 of 24 blocks (67 percent), per unit of work level to the digit (63.1 against 62.7; 26.0 nJ a load on both); the 5090 full-chain liveness form hl-reg64c (every load's address mixes all 64 registers, id 3deee2320e70e1bf, fingerprint 4e7cc25967eba280, PASS, on build-1): 70.96 MH/s at 320.3 W, 4.513 µJ, 88 registers, 0 B spill, 20 of 24 blocks; against the arithmetic-only window the 2,016 extra ALU ops an iteration cost 12 percent of rate and 4 percent of watts (the mix in the load latency shadow); against the base the loads a second level (18.2 against 18.1 G) at 17.6 nJ a load against 16.7; the 4090 full chain 31.38 MH/s at 216.5 W, 87 registers, 0 B spill, 20 of 24 blocks, fingerprint equal. THE SINGLE NUMBER THE SERVED LINE TURNS ON: the GPU loses at most 5 percent per load to the liveness window (5 percent on Blackwell, 4 on Ada) and no rate per unit of work, no spill, the occupancy cut (83 and 67 percent) never reaching the throughput; the "half occupancy" model was pessimistic; the 2.0x or 2.4x is the chip side's k, which the k lane holds. The sound class form (+reg64c, the full chain, the only form the liveness rule passes) exports as hl-v6-win on build-3 with its acceptance test in the suite. PC 1 at 15:44: the runner on floor lane 1's memclk ladder (from about 15:20, 25 minutes), the shipper's host-0326 preview build next, then the 7600 detect (about 16:10), the ds55 kit fetch and the read-width run b; the first 7600 row about 16:30, the grid 17:10, the ds55 rows after. Floor-k (bfccc26ed) landed on master as cc49bc6e at 15:39 BST (shadow-k.md plus tools/chip-model/rtl, 78 files; full gate GREEN 73): ALL FIVE FLOOR DOCUMENTS ARE ON MASTER (868fea52, de3d32af, d28a7656, 018a0877, cb71b766, d461e365, 69335fc1, 66c3401e, cc49bc6e). The 15:45 close landing dropped by the research-landing lane: nothing from 725d2945 lands; the close rows land as a documents-only delta from the research lane's amended "complete " by 17:00, replayed from 08641162 onward. Lane C's drawn-era F8-form row on master at 5cd69d3d (15:41 BST; invention.md section 3.5): under drawn eras the sound per-load form (16 x 256 x 1, 64 seeds, 2^20 nonces, build-2) is NOT the clean row the no-era read gave: 7 of 64 seeds carry a load site under the (c''') floor of 0.995 (min 0.940 at seed 50; seed 27 at 0.956 with one item at 1,938 reads, 67x the uniform control's maximum), the few-item hot-set class and the era-stride class the in-house pass bounded for class v4 at the same order, structurally because the per-load class as built runs neither (c'') nor (c'''); the share column against a uniform control (median 1.15x, max 1.49x) is the window layer, labelled so. Consequence: layer 5 must take the (c''') floor with the dataflow rule, layer 4's generalisation and nothing new; G5-draw's pass line now "0 of 64 seeds with a site under 0.995 under drawn eras" with the seven seeds as the known-failed case; the acceptance figures (0.819 under eras, 0.927 no-era) stand as the pre-floor rate; the chip model does not move (a 1 MB hot set at 0.3 percent of reads is the in-house pass's 1.002x). Lane C closed: five landings (a9f03598 to 5cd69d3d), the harnesses under tools/attack/v6-invention/, six TSVs; owed at 09:00: the Apple footprint of the 4,096-line block, the 4070 and 9070 XT rows, the F8 read under eras against the window-model null. LANE D'S FULL REPORT LANDED on master at 81b90128d (15:46 BST, gate GREEN 73; a first landing de184157a at 15:39 lacked the point-B row by an edit fault), 44 minutes ahead of 16:30: family-gate.md with every row measured and its log. The rows since 13:13: (1) the lossy-share curve per shape at 3,000 eras a point: the exhaustion a 256 x 27 interaction (3.3 percent of its eras at the +4 corner, r = 0.98, about 6x the independent-attempt figure; 0 of 5,015 shape-64 eras at any share), the band's edge at +2; every exhausted era passed class v5's last-resort scan at k = 256 to 258. (2) The width-4 floor: with W = 4 pinned at genesis, (c''') at 0.995 stays at its measured cost (14.6 percent of the candidates reaching the 2^20 pass, +0.3 attempts an epoch), because the width-4 pre-floor spread has a real tail (10 percent under 0.991 against 2 percent at width 1) no single floor removes at the width-1 cost, and the floor refused both hot sets of the live point-A census. (3) Ring C, 128 live epochs of the band at 2^24: point A (shape 256, a band table) 2 hot sets (p38, p54), both refused by the class v5 floor at 0.9932 and 0.9945; point B (shape 64, a band table) 0 hot sets, 5 over 1.2x (the shipped class's own tail seeds), the floor refusing 1 of 64; the bit-R bucket class on 36 of 128 live epochs against the shipped class's 4 of 64. (4) The seven known-failed seeds through the sigma form: p4, p8, p10, p212, p225 all at z = -511 to -567 at address bit R (the product's bit 0, z = -512 exactly), the bucket bound seeing only the three on narrow windows above bit 12; one value-level test ships (the per-site index-bit read as a per-era record and the structural fix's known-failed set), the bucket bound retired into it; a refusal band of 300 sigma catches five of seven at 16 percent of epochs redrawn, 6 sigma would redraw half. (5) The verifier rows on one build-3 core: x4 3.73 ms, x8 4.12, x16 7.13 per warp (1.73x), so x16 scales over the 10 ms gate on the 2019-class core and the half-core proxy: the mixer band is {4, 8}. (6) Bounds: 9,000 band eras with 0 exhaustions and 0 under the floor bound the failing fraction at 3.3e-4 at 95 percent; the floor's miss rate on hot sets under 0.27 on 11 of 11 cases. Running for the 18:00 amendment on build-3: the best-mix genesis table (renormalised 14,13,4,11,3,10,9,2,9,0) through attack-f8 at 2^20 on 64 seeds (16 cores) and the attempts census with the refused-ratio column at widths 4 and 1 (1,500 eras each, after the fg8 build; the fg7 harness could not hold a fixed non-base table at B = 0). Lane 5's served text at 15:4x BST on branch spec-accept-23 be21940f5, read by the coordinator (the IGN-price lines held out by the standing rule; one verb queried, "retains" against "adopts"; the landing by 18:00). The sentence from 10.0h, on the home line, the litepaper abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Beside it on /litepaper#chip-model: the labels paragraph (2.2x to 2.4x modelled; the GPU side measured, the RTX 5080 at its 1,100 MHz lock 2.06 µJ per hash, the 5090 at 1,300 2.33, class v4, 8 October 2026; the chip side claimed, the synthesised 8-lane sequencer core with the window, ASAP7 scaled to N3 on the foundry's headline factors, the window's k synthesis-derived and not a lower bound; the memory modelled; 2.0x node for node modelled, k 1.09; the 32-lane rows pending); the three-row table (energy resistance 2.2x to 2.4x a node ahead, 2.0x own node, 2.8x two nodes ahead on the 8-lane core, the honest tier moving with every GPU generation while a chip must tape out again; economic resistance on development cost, deployment economics and productive hardware lifetime, the first cut: the price at which a project pays scales as project cost over share times discounted life and moves by under 5 percent with the per-joule edge, a fixed-lane chip under rotation needing 4x the price a programmable one needs, "stated as the conditions under which development is attractive, not as a forecast"; response capability: a passed boundary proves the rotation works, not that hardware dies; the schedule hourly / weekly / 180-day family / emergency vote); the measured cost paragraph unchanged; the precedents as 10.0b sources them (the Antminer X5 46 months after the fork at 6.37 J per kH at the wall, "an observed comparison, not a ceiling"; the X9 pre-order, withdrawal, no benchmark; RandomX v2 released 25 March 2026, activation pending; Ethash 36 months, the iPollo V2H about 14x; Kaspa 21 months, 167x to 725x; the commodity cohort = discrete GPUs, the Apple row beside, never the headline); the scoring rule (min over workloads of max over free adversarial designs of E_GPU over E_adversary under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness, hardware accessibility; the rejected long program, select tree, wide read and scratchpad as negative controls with their rows; the next programme: connected state, mixed integer and FP32, the multi-family programmable adversary); the links to the close on master and the class-v5 branch's sections 14, 13 and 0. Struck from every served page: the 2.1x/3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x rung row, the USD 100 M pay-back row, the k about 0.33 column, the "band Igneum's model sits in" sentence; never served: the lifetime claim, USD 300 M/340 M, any chip-arrival probability, the 725d2945 sentence, W = 8. Evidence row 17, ledger X35/X36 and the ledger-text-check pins move with it; docs/plans/counter-asic-3-public-text-2026-10-07.md section 1 superseded on the served pages (the coordinator's to amend). The hash lane's clock corrected at 15:49 BST (its afternoon stamps about fifty minutes fast, the hands' and the box's CEST copied in; every minute read off TZ=Europe/London date from here). Its open minutes: the 7600 detect about 16:10 (PC 1's runner on the shipper's host-0326 preview build; the memclk ladder closed done at 15:4x), the first 7600 row about 16:30, the grid 16:40 to 17:10 with the tier rows, the ds55 rows on the 7600 and the 5090 by 17:40, the read-width lock rows between them; hand A's hl-v6-win and hand B's fold pack about 17:00, the re-weight packs by 18:00, the class-v6 merge, the all-together pack and the freeze sha to the node lane by 21:00. The forty-seventh landing on master at 15:58 BST (022bc52bd), the 7 October public-text file marked superseded. THE PUBLIC 0.3.26 CUT: release-0.3.26 = 1f4904e0 (app-ia-26 ebb20c46 whole, the audit's PASS, the detach fix, the node pin f8da7515; the preview mark empty; the push gate green 15:50; the crate gate green on d1edf2ad at 314+35+8 and running on 1f4904e0 on build-3). THE MINUTE for Mac and HiveOS is 16:00:00 BST on the founder's "push now" (the DMG building on the tip, the hive e3e4482c staged); Windows host-less by main's word about 16:15 (the PC 2 installer build on 1f4904e0), PC 1 and PC 2 by their update checks. The founder's Mac runs preview 2 (a96efbab = effc48e9 whole + the mark) since 15:40:22. The node side: the snapshot short-capture class (the node lane's read at 15:48: every converging node refused its own epoch's blocks after a mid-epoch resume) cured on the fleet by the snapshot-aside restarts running now (24-minute replays; the first hub block about 16:10), its fix acaf08b0 under gates for the fleet's +0 move and the users' next node-only OTA; 0.3.26 ships on f8da7515 since an updating user replays from genesis. release-0.3.27 opens after the 16:00 minute. THE FIRST TWO CLASS V6 PACKS on build-1 and with the census lane at 15:58 BST, an hour ahead of the 17:00 line: hl-v6-fold (id 482dc0dad937135b; the seven failing seeds fire at -58 to -567 sigma on the plain address and read under 3.5 sigma with the fold, the same attempt accepted both ways) and hl-v6-rw (id 30628f8adcf6035e, the k lane's table, the op counts within 0.1 point of the table over 1,000 draws, the plain path byte-identical to the pinned pack); hl-v6-foldrw and hl-v6-rw2 next, hl-v6-win from the window hand on its suite's green. THE CENSUS LANE'S READINESS LINE met at 15:53 BST, seven minutes inside 18:00: a dry PASS on the freeze's class v5 pack (v5-dn3-epoch0, program id e5a4ac5978462156 re-drawn from the pack's own seeds, class and era) through the whole pack harness on build-4, the known-failed set reproducing the record to three places. The harness (branch class-v6-census-fg at 3602d4ad on build-3 and build-4; ds55-v5 b57045fb plus lane D's family-gate diff 3dc3117c plus a sitestats command and the attack pass's f8 tool with a --load-class path; binaries pinned on both boxes, byte-identical): per pack (A) the program re-drawn and judged by the whole rule with (c'''), then per site over 2^20 evaluations the distinct ratio, the 256-item bucket sigma and the index-bit era-stride sigma (4 s on one core); (B) the attempts census over 256 chain-shaped seeds of the pack's class under its era and state (16 cores, 2 minutes); (C) the F8 census on the live state-keyed dataset: the known-failed set at 2^24 one program per 8-core job (4 to 5 minutes each) and 16 seeds at 2^22 on 16 cores (about 30 minutes); class v5, nice 19, pid files under /srv/builds/v6-census/pids/. The dry rows: (A) accepted, min site ratio 0.99923, bucket sigma max +5.5, one site at bit 9 at -448 sigma (the era-stride class on today's load_index, the record's own); (B) 256 of 256, 0 exhausted, r 0.716, (c''') 1.66 percent of candidates; (C) p4 1.2163x FLAGGED (+67.7 sigma bucket), p8 1.3787x, p10 1.5052x, p212 1.1917x (+91 sigma) FLAGGED, p225 1.2457x BEYOND the 1.2x gate, p15 and p34 PASS at 0.9999x, the hot set clear on all seven; the 16 seeds 2 of 16 done, both PASS, max 1.0064x. The per-pack pass line: (A) accepted with every site clear of 0.995; (B) 0 exhausted of 256 and r under 0.90; (C) every seed within 1.2x over the window model and no 6-sigma bucket outside the known-failed set, the known-failed set reading as it does here (the fold pack expected to move p212 and p225). Per pack one box, the next pack the other. Two defaults: the all pack's F8 point at 1,476,395,008 words needs the hash lane's DatasetGeom threaded through the tool (at 2^28 today), threaded after the three single-feature packs or named owed at 22:30; the 64 x 2^24 point per pack (45 to 100 core-hours) owed in every case, the 16 x 2^22 plus the known-failed set standing in. THE RX 7600 READ (the card-in run on PC 1, 15:46 to 15:50 BST; the detect script of 10:10 still switched the card through /api/cards before the morning's fix, so it ran the whole pass at once): the new key amd:gfx1102 "AMD Radeon RX 7600", 8,176 MB, discrete, the 9070 XT gone, the OpenCL device [1] gfx1102 on AMD-APP 3683.0 (a duplicate [3] on the older 3652.0 platform hidden); the class v5 and v4 fingerprints MATCH on the kit worker; the stock bench 13.88 MH/s at 113 W quiet (0.123 MH/W); the app's own row 13.4 MH/s at 113 W mining; the 1 GiB dataset fits. Per tier: an 8 GB AMD card at 0.123 MH/W sits level with the 9070 XT's 0.097 stock and 0.127 tuned, a quarter of a 5090's per watt; the knob grid (IGNEUM_GRID_CARD=7600) and the 2, 4 and 5.5 GiB rows follow on PC 1 behind the read-width run b (the grid about 16:50, the sizes and the ds55 rows by 17:40); the tier rows from the grid, to the denominator and UI lanes. Lane 5's landing state at 15:5x BST: the gate green on be21940f5; the "retains" verb with the research lane (the default: the review's text verbatim at 17:15; "adopts" re-gated as one word and landed by 18:00); the served link to the close points at the design document on master, so the landing waits for the research lane's master sha (its 17:00 line) and falls back at 17:30 to the branch path. The review's manifest order on the next branch (release-manifest-8, its gate running): site/release-manifest.json served at /release.json with the chain id (4464, 4463 below the floor), the node commit f8da7515 with the pin c9ad753a and acaf08b0 pending, igneum-pow 1c420786 with the freeze fingerprint, the mining class (v5 since DAA 68,400, v4 at genesis, the ladder at rung 0), the dataset parameters, finality rule v3 (two thirds of active and two thirds of total, the frozen table from checkpoint DAA 0), the SP1 program ids from the ELF manifest, the verifier off per P21, the fee schedule, the versions per platform with SHA-256, every block labelled; /build, /economics, /miner, /evidence and the litepaper's Devnet 3 line read from it at build (held by a new gate check); /light, /receipt and the light client now say two thirds of total weight; 4463 marked historical in spec 07 and six older docs; every dated /bench entry with a "Historical record of " line; the evidence page's sixth label "activated" and the reference-repository wording; landing after lane 5, before 19:30; the economics "who pays for proving" section by 21:00. The floor-sm amendment (66bc6ca7, the memory-clock ladder) landed as b1b8d833 at 15:57; the denominator amendment 6d0f11e5 about 16:07. THE AMENDED CLASS V6 CLOSE LANDED on master at 16:12 BST as cbf5aa46 (the merge of counter-asic-4 0c8a0625, full gate green 73, pushed to all three box mirrors), 48 minutes inside the 17:00 clock: docs/design/class-v6-rotating-family.md section 10: 10.0 the table; 10.0a the lifetime unit marked superseded; 10.0b the precedents sourced with the RandomX wording; 10.0c the sweep; 10.0d the rotation schedule; 10.0e the window with the card's cost MEASURED (within 5 percent per load, no spill, on a rented 5090 and 4090); 10.0f the first review's five corrections with lane 3's profitability surface; 10.0g the second review's seven; 10.0h the served text, the one word made honest with the audit lane ("Class v6 adopts the 64-register window and retains it across every rotation"); 10.0i the adversary's re-optimised core and the bracket the served figures sit in until the k lane's placed gated rows (17:30; the audit lane holds for them and serves once, 18:30 if late). The coordinator's earlier copy of the design file on master superseded in the merge. An amendment after the landing, on the branch for the next landing: the multi-family adversary lane's first core puts the 64-register window in a macro at k 0.40 node-for-node for the whole draw and reads that the window knob buys the card nothing against a macro file; the k lane's own SRAM-banked model says the opposite (8.5 to 10.5 pJ, not cheaper than its gated flops); carried as a disagreement the two lanes' placed rows settle (17:30 and 18:30), the served window line read as: measured cost under 5 percent, about 0.13 of k against a flop-file adversary, possibly nothing against a macro-file one. The multi-family adversary lane's first rows at 16:4x BST (synthesis only, ASAP7 TC, random-input gate-level VCD; the SRAM macro term modelled; node factors claimed): one in-order SIMD core with the 64-register window in an SRAM macro per 8 lanes and the imem in two macros, every unit operand-isolated, a 5-phase single-port slot, every bank entry as firmware (fold constants, select tree, shapes, W = 4, atoms as programs). The genesis-only variant (10 families, 8 lanes, 66,973 cells plus 3 macros) on the class v4 draw: 5.9 pJ per lane-op at ASAP7 (5.1 to 7.7), 4.1 at N5, 3.0 at N3; against the card's measured 10.3 pJ per op on the same draw at the 1,300 lock, k = 0.40 node-for-node (N5) and 0.29 a node ahead (N3); at stock 0.22 / 0.16. Per family at the lock (k N5 / N3): add, sub, xor, rotl, rotr 0.45 / 0.33; or 0.36 / 0.26; mul 0.32 / 0.23; mad 0.55 / 0.40; mulhi 0.12 / 0.09; shfl 0.083 / 0.060; the load with the fold 0.43 / 0.31. The whole-hash shadow at 102,612 ops: 0.42 µJ at N5, 0.31 at N3, so the GDDR7 board with this core reads 2.33 / (0.466 + 0.42) = 2.6x against the 5090 at its lock node-for-node (2.9x a node ahead), the 5080 at its lock 2.3x / 2.6x. Meaning: the adversary's re-optimised core (SRAM state, port time-multiplexing, operand isolation) sits 15 percent under the k lane's 32-register flop core and 40 percent under its 64-register flop core at the same node, so the 64-register window is not the robust knob it read as; the review's rule 5 holds. The full 18-family variant (95,678 cells, +43 percent) in the power step, the placed 8-lane core at CTS, the 32-lane cores in synthesis; six rented hosts, USD 1.2 an hour. The connected-state lane at 16:55 BST (class cs64s27x16, research, behind --class, never a chain class; branch class-v6-connected 69649ab45): a 64-register window per lane; per step a 4-byte load from a window register, then a block of 27 distinct instructions run 16 passes, the next address from the block's last instruction on a fresh spine, the result folding all 64 registers; 128 loads + 55,296 ALU per hash (v5: 128 + 55,680); text 448 per iteration (v5: 320). Liveness (seed igneum-v6c/0): 63 of 64 registers necessary for a later address at every one of the 128 addresses until the last iteration's tail, the result reading 64; per step an address depends on 1 to 15 registers of the previous address point (mean 11.2): the chain narrow per step, the whole window necessary over the hash; each block touches 16 to 24 registers, every register read 384 to 3,208 times and written 128 to 1,664 times per hash; a specialist must hold 64 x 32 bits live per lane and can bank them (about 20 hot per step, the set moving with the text). Census (the sub-version 3 harness, (c''') on): no era 256 of 256 accepted, 0 exhausted, 0.28 rejections per candidate (the control mx8+sh256x27 0.67), mean attempt 0.39 (control 2.0); eras 0 to 7 at 32 seeds each with the window-bit refusal on: 256 of 256, 0 exhausted, mean attempt 1.7 (control 4.9), 306 window-bit refusals (control 218): the product-bit class the layer-1 index fold removes, present as in v5; F8 form at 16 seeds x 2^20: the top 0.1 percent share 0.999 to 1.002 of the uniform control. GPU at stock on a rented 5090 at its 575 W cap (the class v5 nvcc harness, 250 batches of 2^24, both packs minutes apart): cs64 64.93 MH/s at 574.8 W against v5-genesis 65.30 at 574.8 W, energy per hash +0.6 percent (8.85 against 8.80 µJ in this harness); ptxas 80 registers per thread (v5 48), 0 spills, 24 resident blocks per SM; fingerprints cs64 ad0cec2a42c84aff, v5-genesis ae74193ddad19e19, vectors 3 of 3 PASS. Meaning: the window costs the card under 1 percent of energy per hash at stock, far inside the 10 percent budget, and a chip a 64-entry live file per lane. The 4090 row by 17:15, the PC 1 lock row owed (the bound emitter building); the k lane's score and KEEP or KILL at 18:00; connected-state.md with every row by 17:45. The 0.3.26 Windows entry live at 16:11:04 BST (installer 8e674bd5 from 1f4904e0, host-less, both folders and the public alias, read back live): EVERY PLATFORM ON 0.3.26 (Mac and HiveOS 16:02:53, Windows 16:11:04), the PCs by their update checks. The network: dn3-g1 refused dn2-1's branch at 16:06:55 with a genuine InvalidPoW after its full replay (dn2-1 sat in the held group and mined on 5b673577's object through the stall, so its branch's state past e1f65284 and its epoch 21 reference are foreign to every f8da7515 node); the fleet's default taken at 16:12: the chain is p1-4090's branch (sink 486a7cb6, mined on c9ad753a's object from 14:50, under the epoch 21 line), its miner at its sink, the rest by IBD, the hubs as they converge, dn2-1 wiped after. The rule candidate for the next line (the node lane's reading asked): a held box never mines on the old object past a digest-moving minute. The denominator RX 7600 delta (29df04cf, denominator.md plus class-v5-tiers.json at 31 classes) landed as c3911a8c at 16:12; twelve research landings today. The class v5 lane's ask at 16:4x: no class v6 order had reached it (the shipper's relay named its items second-hand); the coordinator sent the order's text at 16:45 with the lane's item: the class v6 kit, the six-platform fingerprint read on the hash lane's class-v6 merge on the all-together pack, the known-failed case first (the plain-address pack reading a different id from the fold pack on every worker), the kit zip on build-1 with its sha by 23:00, the Arc and the AMD through the PC job runners, the Mac by the Mac chain; a miss means the kit ships tomorrow morning on the merge's last green commit with the platforms read so far named, and 0.3.27's pin waits on six equal reads. The enforced-proving lane (ledger P21) at 16:15: the test set and the full crate suites green on build-2 ahead of 18:30 (igneum-exec 64/64, kaspa-consensus 138/138, kaspa-consensus-core 171/171): a valid SP1 proof a condition of payment in consensus behind the named switch verifier_in_consensus, false on every compiled object (the live Devnet 3 object unchanged; igneum-testnet-1 gains the payment rule on its DAA floor 0; the class v6 object carries the switch true); six consensus-side and seven executor-side tests named per refusal, known-failed first; branches enforced-proving (b6a538b65: docs/spec/proving-enforcement.md, the P21 and P22 rows, the 60x switch listing, infra/fast-time/proving-enforcement.mjs) and enforced-proving-node (the fork, edf45887 plus one import fix, off acaf08b0 with f8da7515). The coordinator's word at 17:00: the main-repo branch lands on master through the gate now; the node commits take release-0.3.27-node, the line the node lane cuts from the class v6 object tonight, the branch tip and its suite lines to the node lane for the merge under the object's gate set; the verify-cost row by 20:00 (the stated 0.26 to 0.53 s cold verify per record labelled stated if no core by 19:00). The record's forty-ninth landing's merge gate killed by signal 15 twice more at 16:1x BST on the Mac (rule 4 refuses the class in scripts; a hand command still reaches it); the third run in the background. The three gate kills at 16:14:24, 16:17:20 and 16:18:15 BST found by the coordinator in the lanes' transcripts: the site audit lane's shell ran pkill -f "tools/ci/pre-push.sh" in its spec-accept-23 scratch tree each time, the kill-by-name class the CLAUDE.md rule forbids since 12:5x; the lane told to end its own gate by its pid file only; the record's forty-ninth landing re-run a fourth time. The steward at 16:33: the class v6 matrix on the node lane's first sha 617cb441 (class-v6-node, app tree 89e83df2, the class v5 freeze tree linked, the parent's 60x file at bf2c878d's three keys) started 16:33 on build-2 and build-3 at gate priority, seven suites each, the line by 16:55; the object commit's matrix the same way the minute its sha lands. IGNEUM 2.0, decided by the founder (main's relay stamped 17:45 and 18:2x to 18:3x on a clock two hours ahead of the Mac; the Mac read 16:28 to 16:36 BST): "this is now Igneum 2.0, Miner v2.0.0, the testnet is scrapped (the go ran, nothing mined, seeds stopped and held), Devnet 3 is the network", then at 16:3x everything off and the network restarting as the Igneum 2.0 devnet (igneum-devnet-4, node 2.0.0, fresh genesis, enforced proving from block zero; the shipper leads, the fleet and build-server lanes execute); the reference docs/plans/igneum-2.0-reference.txt with the pins in docs/plans/igneum-2.0.md ("This is your reference, always, do not stray"), landed on the box mirror's master as the first act by the build-server lane (72a5f9bd on build-server; the coordinator's own landing of the same two files failed its gate on the site sweep's live /swap render and was dropped). The plan's objective: durable GPU competitiveness, not chip destruction; the positioning line on every served page: "A GPU-secured network for Ethereum-compatible applications and verifiable computation"; the three boundaries wherever the proof architecture is explained; the standing rules carried in (more layers is not more resistance; rejected knobs stay out as regression controls; the adversary re-optimised after every change, synthesis k never a lower bound, placed rows score; the 10 percent GPU-cost budget set before results; "every chip dies within a family epoch" out of the baseline economic model, no chip-arrival percentages; no ASIC detection, whitelists, attestation, quotas or self-reported bonuses; rotation optional to the security argument; energy, economic and response capability reported separately, the cohort = the discrete-GPU population; mining resistance, proving competitiveness and system stability three questions). D1 the frozen reproducible baseline (the coordinator with the hash and node lanes; the pass: an independent operator reproduces it from the served kit alone); D2 two experiments (a) CLOSED by the connected-state lane's KILL (1.10x against the 1.25x gate; window width the one robust knob; rearranging the same ops moves nothing) and (b) memory sharing, recomputation and data-local execution against v6 (the adversary lane); D3 the programmable survivor chip (the adversary and k lanes; placed rows, the three-year life, the next-generation matrix, the dataset schedule scored per step, state coupling justified or dropped; 1.5x energy a research goal, not the pass); D4 the five-year coexistence model replacing the capex wall (the research lane; the sunk-dev-cost case mandatory; miners react; the tip-share discrepancy resolved); D5 the no-rescue network exercise (the node and build-server lanes on the three ex-testnet seeds; enforced proving the prerequisite); pools, architecture and product, versioning (Miner v2.0.0 from the 0.3.26 line; node 2.0.0 once enforced proving is on the network), the leadership tests (benchmarks against Ravencoin KAWPOW, Ergo and Firo's reference miner; the ranking ceiling "serious contention for the top of the GPU-mining space on engineering and operator proposition"), and the site reset (the served site starts at 2.0; site-pre-2.0 tagged; the facts page wiped; the FUD ledger written fresh with every entry naming its pin). THE DRAIN at 16:37 to 16:50 BST (the Mac's clock), ordered by the founder ("have we pulled all current jobs from all builders and boxes? and spinning up 2.0 work?"), read-back to main at 16:50 and accepted. Stopped by pid file: the attack pass's ten leases on build-2 (five F9 upper chunks, three F1 parts, the chunk-5 and parity waiters) and seven on build-4 (six F9 lower chunks, the F1 lower-range waiter), rows kept (F9 135,836 seeds, max attempt 32, 0 exhausted; F1 172,310 programs, one letter miss at 5.0781 percent, parity unread), the partial landing on attack-pass as lane (d) rows; the build-server lane's two bs0322 zigbuilds on build-2; the node lane's Devnet 3 monitors on build-1; the steward's 617cb441 matrix; the shipper's host-0326 preview on PC 1 and the 0.3.25 takes on PC 2; the acaf08b0 move withdrawn; release-0.3.27 superseded; every rented pod of the hash, size, knob, connected-state and mixed FP32 lanes destroyed. One reversal by main: the finality-boundary lane's two build-3 runs (the v3.mjs split50 harness and the N1B/N2B sim), which the coordinator stopped by pid at 16:39 under the drain's default, are KEPT under D5's partition row; the lane restarted them at 16:40 (pids 866903 and 866905, class measure, pool 4) with rule v4 and the measured N1 to N6 on branch finality-boundary (286cb43e8). Kept with pin: D1 on build-1 (the node lane's object checks and crossing), build-2 (the hash lane's window suite and re-exports, the enforced-proving crossing on local nodes), build-3 (the census's rw2 points, lane D's best-mix acceptance at widths 1 and 4), build-4 (the census's control and foldrw points), PC 1 (the read-width lock rows as controls, the 7600 grid, sizes and ds55 rows); D2(b)/D3 the adversary's six hosts; D3 the k lane's pods; the enforced-proving suites on 74803660 (the devnet-4 cut). Started with pin: release-2.0.0-node (the node lane, devnet-4), the seven-refusal re-run on the cut sha, the D2(b) harness on build-2's freed cores, the 2.0.0 matrix on release-2.0.0, the coexistence harness on build-4. The pool vote-key commitment design doc assigned by main to the attack-pass seat (a first complete draft by 20:00); the second-prover pin held (no box work tonight). The consolidated map to main at 16:58. The afternoon's rows under the new pins. The census sheet (D1): hl-v6-fold PASS (the program accepted, min site ratio 0.99986, bucket +5.25 sigma, worst free index bit 2.84 sigma, no site over 6 sigma against the class v5 control's -448 at one site's bit 9; the attempts census 256 of 256, 0 exhausted, r 0.701, mean attempt 2.34, max 14, (c''') 0.35 percent; F8 at 2^22 on p18 to p33 16 PASS at most 1.0455x; the known-failed set at 2^24: p4 1.0057x from 1.2163x, p8 1.1663x within the gate with a +6.58 sigma bucket from 1.3787x, p10 1.1868x from 1.5052x, p15 PASS, p212 1.0411x with a +27.3 sigma bucket from 1.1917x, p225 1.2414x BEYOND the gate unmoved (the value-level class, not an address bit), p34 1.0486x with a +11.9 sigma bucket the fold creates, the one regression): the fold does what it was drawn for, the four tail ratios fall from 1.22 to 1.50x into 1.01 to 1.19x, the stride-bit bias gone from the address, and against the class v5 control on the same 16 seeds (5 of 16 flagged on the 6-sigma windowed bucket) the fold's 0 of 16 is a measured gain. hl-v6-rw PASS (accepted, min ratio 0.99990, r 0.117, the lowest per-candidate rejection ever measured on the family, 256 of 256, 0 exhausted, max attempt 2, (c''') 0.34 percent; F8 at most 1.1526x; its 4 of 16 bucket flags at the control's own rate of 5 of 16). foldrw (accepted, min ratio 0.99993, no biased bit, r 0.117) and rw2 (accepted, min ratio 0.99990, two sites with the stride bit at -64 sigma as expected without the fold, r 0.410, (c''') 1.15 percent) with their F8 points queued; hl-v6-win not yet on build-1; the all pack's 5.5 GiB geometry in the f8 tool, untested. The hash lane's D1 line: the window hand's suite and the hl-reg64c and hl-v6-win re-exports on build-2; PC 1 in order the read-width run b, the 7600 knob grid, the 7600's 2 and 4 GiB sizes, the 5.5 GiB rows on the 7600 and the 5090 (the 5090's 1,300 MHz row at 5.5 GiB = the PC 1 lock row), then the cs64 row at the tail. The research lane's third close landing d6bee526 at 16:38 BST (10.0m the adversary's whole-machine rows; coexistence-model.md as its own file, the sunk case first: the GDDR7 board passes all six conditions at a one to three year life, the N2 SRAM die fails five once built, the only condition holding it that nobody pays to build it; 10.0n the three statements re-read: energy whole-machine per tier, economic from the model with capex per accepted hash the main term, response capability as versatility not life), its second landing fc1f9b62 at 16:26 (10.0l the objective and the claim statement), and 10.0o on the branch: the mixed FP32 candidate KILLED (determinism bit-exact on CUDA and the CPU across three cards; the determinism tax the whole economics: +14.8 percent energy per hash for fp12 on the 5090, +19.0 on the 4090, +26.5 for fp24, against about 7 percent of chip edge, the operand confinement integer work at integer k; the exponent-byte bias on address bits 23 to 30 a new instrument reading worth a layer-4 rule; FP32 a negative control; docs/analysis/class-v6/mixed-fp32.md on class-v6-mixedfp 255be026). The app window audit lane: the window rebuild ebb20c46 already an ancestor of release-2.0.0 b891444f and 0.3.26's 1f4904e0, so the v2.0.0 clock starts from b891444f; its record on master at c86a7e23. The site audit lane: spec-accept-23 and release-manifest-8 landed as 2966599e at 16:33 (the chip serve with the claim statement and the bracket, /release.json, the economics proving section) and tagged site-pre-2.0 at 16:35, the pre-reset state closed; the reset on three branches (site-2.0-lite, site-2.0-pages, site-2.0-facts) on main's clocks: the wipe 17:15, the facts and ledger 17:45, the litepaper and positioning 18:00; its gate moved to build-2 under /srv/builds/_site-gate; the Devnet 3 manifest regeneration and the 2.1x placed-row swap stopped as superseded. The shipper: the copy pass its own hand (the session's concurrent-subagent cap of twenty reached, so no opus hand spawns from any lane until one closes): the About and footer positioning line, proving on NVIDIA against mining on AMD and Apple, "the Igneum 2.0 devnet" wherever the app names the chain, the engine's network move to igneum-devnet-4 with the testnet choice gone, on release-2.0.0 by 17:05; the readiness clock to main at 17:00 on the UI lane's network step 17:10, the update-return lane's prover-host install 17:20, the devnet-4 node artefact 17:15, the chain about 70 minutes behind the last. The attack pass's partial on the mirror's attack-pass at d7943c8a (feature gate GREEN, 16:4x BST): F9 206,980 new seeds (306,980 with the record), 0 exhausted, 0 panics, max attempt index 37 (seed 421302; 718097 at 32); F1 217,310 programs, 0 mismatches, TWO letter misses at 5.0781 percent (attack-f1/392513 and 865158, both 13 of 256, the v4 miss's exact saving; rate 9e-6, the v4 rate), parity owed and not made, both named for the D1 harness on the class v6 generator; both boxes clear of its leases; the seat takes the pool vote-key commitment design doc (docs/design/pool-vote-key-commitment.md on master by 18:30, the sha and the surviving attack to main). Main's three additions to the map at 17:1x: D1 includes the spec (docs/spec/01-lottery-hash.md at 0.2 of 4 October, generator v2; the node lane re-cuts section 01 to the frozen object with the five digests in the 23:30 landing); the pool lane's 0.3.20 branches rebase whenever that lane next answers; the second-prover pin held; the finality lane's two D5 leases wait on build-3's pool, and at 17:30 the census's lowest-priority F8 run moves to build-4 to free them. Every active lane mapped and told by 17:16: the hash lane D1, the census lane D1, the node lane D1 and devnet-4, lane D D1 (the acceptance) with the rotation prototype paused, the k lane D3, the adversary lane D2(b) and D3, the research lane D4, the enforced-proving lane the devnet-4 cut, the steward the 2.0.0 gates, the site audit lane the site reset on main's three clocks, the reference-apps lane compatibility, the attack-pass seat the pool design, the finality lane D5, the shipper versioning and the devnet-4 move, the build-server lane execution and deploys. A BOX FAULT at 16:40 BST (the Mac's clock): build-3 (62.238.91.43) answers neither ssh nor ping (it answered at 16:37 with load 83 and 24 held cores; lane D lost its ssh at 16:4x); it carried the census's rw2 F8 points, lane D's exact-table acceptance (466 and 401 of 1,500 eras) and the finality lane's two D5 leases (restarted 16:40, pids 866903 and 866905); the build-server lane reading the Hetzner console with a hard reset as the default; lane D's two runs queued on build-2 as the fallback; the box out of the pool for tonight if not back by 17:00, the lanes re-queuing on build-2 and build-4. THE DEVNET-4 CUT on both node mirrors at 16:42 BST: release-2.0.0-node c04674fe (acaf08b0 plus the enforced-proving lane's two commits plus node 2.0.0: igneum-devnet-4 with its own genesis 7c36b83374a673e9 stamped 2026-10-08T15:00:00Z, digest 08aae61c0dc8cc1d1fa35f8cc776a924f3ec9d231ac2d15a53cf030191d378b9, every switch at 0, class v5 with byte 6 from genesis, verifier_in_consensus with proof_rule_active_from() 0 and the embedded ids pinned, chain id 4465, base unit 10^18, igneumd/2.0.0, the mid-epoch resume rule; the class v5 freeze pairing unchanged); the artefact, suites and canaries (with a devnet-4 step) running, the pair on build-1 by 17:05; none of the node lane's gates needs a live chain. Lane D under the pause: nothing to stop (every stratum, the lossy curve, both live censuses, the sigma reads and the verifier rows complete in 81b90128d); the or-floored copy of the best-mix acceptance complete (3,000 eras at width 4, 1,500 at width 1); the exact-table acceptance (add 14, xor 13, mul 4, mad 11, shfl 3, rotl 10, sub 9, mulhi 2, rotr 9, or 0; fg9) PASS so far on the F8 census (2^20 x 64 seeds, 0 hot sets, 0 over 1.2x), the attempts rows as the verdict by 18:00 from whichever box answers. Two v7 documents on master through the research-landing lane: multi-family-adversary.md as f6bab871 (16:36 BST; tools/chip-model/mf on the branch) and connected-state.md with its logs as 3919d430 (16:44; igneum-pow on the branch), both full gates GREEN 73; fourteen research landings today. The reference-apps lane's pin line at 16:52: /light, /receipt and /oracle serve as the network's (84c33a4f); the read service and the eth_getProof reader on build-1 re-point to devnet-4 the minute the pin and genesis are named (the reader rebuilt on c04674fe, the service an environment change); the pages re-run against devnet-4 once block one and a paid segment record exist; the oracle's Devnet 3 certificates kept as a record; the compatibility pin served as /compatibility from docs/build/compatibility.md plus a results file from a runner (tools/reference-apps/compat/run.mjs executing every row against the devnet RPC with a funded sender; a row a landed test with its evidence or "untested" with the reason): representative contracts, wallet fee estimation, indexing, failed transactions, receipts, application assumptions, and the measured differences (coinbase the including block's miner; prevrandao's source; the two-dimensional fee fields); nothing of its mines, votes or holds weight; the draft on master by 20:00 with the rows run on devnet-4 from 18:00. The fiftieth landing on master at 16:50 BST (f29dae620: the decision, the drain, the map); the plan and reference files were not on master (the build-server lane's 72a5f9bd chain never arrived), so the fifty-first landing carries them from the Mac checkout, byte-identical. The census sheet at 16:50: hl-v6-foldrw PASS (accepted, min site ratio 0.99993, largest bucket +5.75 sigma, worst free bit 3.49 sigma; 256 of 256, 0 exhausted, r 0.117, mean attempt 0.13, max 2, (c''') 0.34 percent; F8 at 2^22 15 PASS, 1 flagged (p18, against the control's 5 of 16), ratio at most 1.0932x; the known-failed set every ratio within the gate: p4 1.0002x, p8 1.0138x, p10 1.0100x, p15 1.0088x, p34 1.0121x, p212 1.1111x, p225 1.0000x, buckets flagged on p15 (+9.3) and p212 (+24.5)): with the fold in front the table's programs carry no address-bit class and the tail reads as the fold pack's; the sheet fold PASS, rw PASS, foldrw PASS; rw2's F8 points stranded on build-3; hl-v6-win placed (program f42d4a743ce7d4fa), its harness build waiting on reg64-v5's sha. The steward at 16:45: build-3 unreachable from the Mac and from build-2 inside Hetzner (the host or its network, not a load state); its half of the 2.0.0 matrix on c04674fe died on the first suite, the matrix on build-2 alone, the verdict by 17:40 from build-2's seven; the GitHub poll stopped. The fast-time lane's rule (f) on the class v6 object 617cb441 (16:24 to 16:48 BST, the freeze fingerprint on both binaries): every reading green: v5 by floor at epoch 8, class v6 from epoch 9 at its floor with the object line on every node, byte 8 on every block from genesis, 12 of 12 ids equal to the CLI's, the template at every boundary, the stale node refused under v6, the restart step resynced in 8 s, the cold restart on 4 of 4 nodes (660 s stopped, snapshots removed, each restarted on its kept datadir with the cold-restart line, no wait line, one sink 15 s later, every miner accepted after); the known-failed shape (a 60 s wait) FAILED as it must; the SUMMARY's four harness-scope FAILs (counts and a read window the cold restart moved) fixed, the clean PASS from the rerun about 17:25; the object fact: with the v6 floor set the node stamps byte 8 from genesis, so v5 cannot flip by signal on a v6-enabled file and comes by its floor; the c04674fe pair's run armed on its artefact path. The k lane at 16:5x: the placed gated core8r64g slipped to about 18:30 (floorplan timing repair on the pod), the five other cores by 21:00; the row serving meanwhile on the synthesised gated 64-register core, the GDDR7 board against the 5090 at the lock 2.6x node-for-node, 3.0x a node ahead, 3.4x two nodes ahead, the placed figures expected at 2.1x to 2.4x and 2.5x to 2.8x with the placement uncertainty (+30 to +65 percent on the chip's pJ per lane-op), the served bracket tightening to its lower half. The research lane's D4 tip-share resolution written (counter-asic-4 1e183dc0: docs/design/proving-payment.md, spec 5.1 to 5.3, O-5.7 closed): the tip stays whole to the block (80 percent to the producer, 20 to the developer registrations), no part reaching the provers; the provers paid by the explicit user-funded congestion-priced proving payment (f_p times pgas used), 90 percent to the block's proving pool per shard by consensus proving cost and 10 percent burned instead of burned whole; the burn listed in one place; the hard cap and no development tax untouched; the one code pin (executor.rs at the proving base fee debit, behind an activation constant) assigned by the coordinator to the enforced-proving lane on a branch off release-2.0.0-node, never on devnet-4's object tonight, by 21:00; the served form of the coexistence result in four sentences (the IGN clause held out by the standing rule); the five-year run with miners reacting and the operator simulation on floor lane 3 (20:15 and 20:30), landed by 21:00. The adversary lane's jobs at 16:5x: six Vast hosts on D3 (adv-b the placed and routed 8-lane 18-family core plus its 29-tag power run; adv-e the placed 8-lane genesis core; adv-f the placed 32-lane 18-family core; adv-a and adv-d the 32-lane synthesis-only rows; adv-c idle, kept for the D2(b) harness's compute); the D2(b) harness to build-2 through the lease pool when its trace tool is cut, the first row by 19:00. The rotation lane's run 5 refused a build-2 window tonight (the run-4 results the control; run 5 tomorrow's amendment). The site audit lane: the wipe branch site-2.0-wipe df465d47 in the site gate on build-2, landing about 17:00; one fault of its own: a test push of release-manifest-8 ran the full gate on the Mac once (16:37 to 16:44, checks only); the 6.1 GiB and 7.5 GiB peak fact not served (no record); the research lane's four coexistence sentences and the k lane's tightened figures on the landing after the wipe. Correction at 16:5x BST: the 6.1 GiB miner and 7.5 GiB proof fact HAS a record, docs/analysis/class-v6/coexist-rows.md at 11653ece (the coexistence rows lane, landed 16:48): the RTX 3060 12 GB at 26.82 MH/s with 6,129 MiB resident and the compressed shard at 13.2 s with a 7,525 MiB peak (13,654 MiB against 12,288), the RTX 4060 8 GB at 6,116 MiB and 7,532 MiB, 8.2 s, both with the miner paused; the 3060's 8.9 GB row of 6 October stands as a 1 GiB-dataset row (1.4 + 7.5), reconciled in the file's section 4; it serves on the site lane's follow-up landing: 16 GB to mine and prove together at the 5.5 GiB floor, 8 and 12 GB time-share. The served chip figures are 10.0h's on master at the follow-up gate (the research lane's 17:5x form "2.5x to 3.0x, 2.1x to 2.6x on the GPU's own node" on the branch now). The v2.0.0 cut tip: release-2.0.0 a9e2df26 (b891444f plus the network move and the copy pass by the shipper's hand, net-20 775c6d87 whole with the blank-step fix, prove-host-20 2368dd7f, the 16 GB proving line), every push gate green, the crate gate on build-1; the window copy checked by the app audit lane PASS at 16:5x (two follow-ups after the cut: the positioning sentence twice, the one-card network step); rule (2) rides v2.0.0 as proving OFF by default under 16 GB with the switch labelled ("mining and proving together need a 16 GB card; this card does one at a time, mining continues"), the finer claim rule v2.0.1, rule (1) the node lane's 2.0.x queue; the floor lane's packer guard and sidecar in the build-server lane's packers; the shipper's clock: the node artefact 17:05, its gates 17:25, the hub-1 canary 17:30, block one about 17:40, Mac and HiveOS entries about 17:50, the RPC and explorer 18:00, Windows 18:05 host-less or 18:20 with PC 1's host. Enforced proving landed on master at 16:59 BST as 5423b3277 (the merge of enforced-proving 3d2c7b41, gate green; mirrored to build-2 and build-4, build-3 down); the node side on release-2.0.0-node under c04674fe; the fast-time crossing's fourth run on build-2 (the third observed the finding below the floor, then its ssh died). THE D4 CODE PIN built by the enforced-proving lane on branch proving-payment off release-2.0.0-node c04674fe: Params::proving_payment_activation_daa (u64::MAX on every object, in the digest once set, in the 60x file); the executor's two proving-charge sites split by proving_payment_split (off: the whole burn as today; on: 90 percent to PROVING_POOL_ADDRESS and the block's proving_pool_credit, so the per-shard payout of 5.3 carries it; 10 percent burned, the rounding wei to the burn); the receipt's proving_payment and burned_proving; the known-failed test the_proving_payment_burns_whole_below_the_floor_and_credits_90_percent_to_the_pool_from_it and the params test the_proving_payment_floor_is_never_on_every_compiled_object; suites on build-2 from 16:56. THE CONSEQUENCE FOR MAIN before any height is named: the shard guest (proving/igneum-prove/core/src/executor.rs lines 290 and 318) burns the whole proving charge exactly as the node did, so with the node's floor set and the guest unchanged every shard proof's post-root differs from the node's statement past the floor and no record verifies; the guest needs the same split behind the same switch in its fixture env, which changes the ELF and the pinned shard program id, before any object sets the floor; the node pin is safe at never until the guest ships with it. The pool vote-key commitment design doc on master at 637e508b (16:54 BST; branch pool-vote-key 611e9bf5, full gate GREEN): the header's vote_key_hash is under the pre-PoW hash already (header.rs:174), the reveal IGNK in the coinbase, weight reads headers, pool v0 names the member's key and pays the pool's IGNA, the open pool pays the window by IGNW with no operator; the litepaper's "vote keys stay with the pool" the one line contradicting the code (O-9.1, G6); the design keeps the commitment in the header (proof of work binds it, one 32-byte compare) and adds vote_key_hash to the job and the share so a pool cannot credit work on any other key; payment aggregation the pool's IGNA (operated) or the block's split (open), both verifiable; twelve attacks, the survivor A5 custody by consent (a pool's terms plus a client fork), answered by the refused-by-default custodial mode, one key per pool address on the explorer's concentration page, and the market; costs 0 new header bytes, 64 characters on share and job, one comparison per block; migration: the pool branches rebase onto release-2.0.0 first (pool-finish-22 1 ahead 112 behind, pool-finish 11 ahead 572 behind, pool-v0-rebase 4 ahead 925 behind); six open questions for main. The attack pass closed (its report: F4 PASS at 2^28 days, F8 PASS at 256 seeds, F9 and F1 partials; one exception of its own: a gh auth switch to the founder's personal login at about 10:0x BST under the hook's remedy, against the rule, reported). CLASS-V6 GREEN AND ON THE MIRROR at 17:0x BST: 3f25a8305 (the merge 6db297da1 of class-v6-fold 7880bc96 and reg64-v5 198d171d, one brace fix; build-2's suite 136 passed, 0 failed, 8 ignored); one class string carries every flag: mx8+sh256x27+state+reg64c+fold+rw; hl-v6-all exporting on build-2 at log2 28 (1 GiB; a state class refuses --dataset-words, the 5.5 GiB form the ds55 lane's, non-state). The D1 gap: reg64c has CUDA kernel text only (the OpenCL text a refusal stub, Metal the same), so hl-v6-all cannot read on AMD, Intel, Apple OpenCL or Metal tonight; the honest kit line "all pack: CUDA and CPU equal; the partner hl-v6-foldrw: six equal (fold f6c34aa6e87bf211, foldrw 5a6ad122a71a888f, rw 964ce3ba78b92a32 on the emulation, Metal and Apple OpenCL); the window texts owed"; the hash lane ordered to emit the window's OpenCL and Metal texts after hl-v6-all by 23:00. THE D2(b) FIRST ROW at 17:3x BST (modelled on the mf core's synthesised rows at N5, the record's memory figures and adv-cache-2's measured window-layer hit rates; harness tools/chip-model/mf/flow/d2b.py on the lane's rented host, build-2's pool full): the served convention, the 5090 at its lock over the chip machine on its own GDDR7 board: the baseline 1.82x (1.52 to 2.06); the bracket MOVES by one combination: the hottest half of the items in 1 GiB of SRAM beside the DRAM serves 72 percent of reads (the per-program hot set, refilled in 2 ms per epoch), so the activate-bound board runs 3.6x the hashes on the same devices: 2.69x per joule (2.20 to 3.03) and USD 1.88 per MH/s (8.5x the card per dollar) for USD 250 of SRAM (claimed); the uniform-store lower bound 2.30x (1.90 to 2.59) and USD 3.34; the hottest three quarters 3.10x; a node ahead 3.33x and 3.96x; moving nothing: data-local execution (2,112 bits of live state against an 80-bit read, 26x on every medium), memory sharing, recomputation (0.78x), selective participation (9 percent spread across 2,000 era draws; the best-half specialist gains 2 percent of ratio for half its revenue); the line: the served floor against a chip on the same node is the stored-half hybrid at 2.3x to 2.7x, not the DRAM board's 1.8x; the record's partial-store curve missed it by pricing the rest as recomputed. THE HOT-SET RECONCILE (the hash lane, 17:4x): both instruments right, different layers, the 72 one program not the mean: the per-program hot set is the era layout's layer 8 by design (era-layout.md 1.4: each of the 16 load sites reads the whole dataset, an aligned half or quarter at a drawn offset; the read set the union); inside a window the reads are uniform (the measured quarter shares equal the closed form to four digits), which F8 reads per site inside the window; the 72 percent is the Devnet 3 epoch 0 program alone (its top aligned half 0.71875 over 2^31 reads); over the draw the top-half share: median 0.5625, mean 0.5811, p90 0.6562, p99 0.75, max 0.875 (the closed form over 74,613 compositions; 4,096 drawn programs under 4,096 eras match at 0.5808), so Devnet 3's program sits at about p98 and the D2(b) row priced the hybrid on it; at the mean hit rate 0.58 the hybrid reads about 2.44x (linear interpolation; the exact row one rerun of d2b.py at hit 0.581); the rule that flattens it: win = 0 on every load site (layer 8 off; every window the whole dataset), exactly 0.50 at every program, GPU cost zero against the budget (a window is a mask and an offset in the text; the random footprint already the whole dataset beyond every card's cache); what it trades: layer 8 was written against an SRAM-only mirror, and against a DRAM-backed SRAM refilled per epoch the windows hand the attacker 8 points of hit rate at the mean and 22 at the tail; named as a D2 experiment "layer 8 off" for the v6 object (measured on the 5090 and 4090 at stock and the knee against the pinned pack; the chip side at hit 0.50); not a reopened knob (it removes a draw); nothing in it touches the 21:00 freeze. THE PLACED ROW (the adversary lane, 17:5x; the 8-lane genesis core placed and routed on ASAP7 with its SRAM macros, SPEF, gate-level VCD; the full core's routed run 38 of 58 tags): placement and the clock tree add 32 percent to the class v4 draw (7.78 pJ per lane-op routed against 5.91 synthesised at ASAP7; 5.44 against 4.13 at N5), inside the k lane's +20 to +40 band; node-for-node k 0.53 at the lock (0.38 a node ahead) for the genesis core, 0.59 and 0.42 for the full core scaled; the complete GDDR7 machine at the placed energy 1.6x the 5090 at its lock per joule node-for-node (1.4x to 1.8x), 1.9x a node ahead (1.5x to 2.1x); 1.4x / 1.7x the 5080; 2.5x / 2.9x the cohort; USD 4.84 per MH/s unchanged; the N2 SRAM die 2.4x / 3.3x; the stored-half hybrid about 2.4x / 2.9x; placement takes a tenth off every per-joule ratio and nothing off the per-dollar ones; THE HONEST BRACKET against a same-node chip 1.6x to 2.4x per joule (the DRAM board to the stored-half hybrid) and 3x to 9x per dollar; the served 2.0x same-node line sits inside it; the 32-lane genesis core (synthesis) 3.70 pJ at N5, k 0.36; the document 2b30cfd0 with sections 11 to 13 (the data-local cost model, the dataset comparison with the five-line recommendation, D2(b)), "complete" about 18:15. The build-server lane at 17:01 to 17:05: build-1's Devnet 3 nodes stopped by the shipper's pids at 16:34, the observer, the explorer indexer, the faucet and the RPC proxy by unit at 16:38 (rpc.devnet answering 503 "Igneum 2.0 devnet starting"), the light reader at 16:42; the artefacts kept; build-3 still dark at 17:05 (the Hetzner Robot console in the browser pane stuck on its "Security Check" page, no Robot API credential on the Mac); its 72a5f9bd landing of the plan files RED on the site sweep's overlap check from master's served content, so the coordinator lands them (the fifty-first landing, in its gate); the deploys 84c33a4f (16:30) and 5423b327 (17:00: the chip text serve and /release.json, /compatibility and the positioning line, under SITE_TRANSITION=1 with the chain-keyed checks skipped until the devnet-4 feeds exist). The census lane at 16:53: rw2's F8 chain and its acceptance read re-queued on build-4 at 16:54 (the 17:30 move taken early); hl-v6-win's harness building on reg64-v5 198d171d on build-4. THE PLAN ON MASTER at 17:02 BST: b943c0476 (docs/plans/igneum-2.0.md and igneum-2.0-reference.txt from the Mac checkout, byte-identical; the fifty-first landing); the complete 37-page PDF (docs/plans/igneum-2.0-plan.pdf with its text) lands beside it by 17:30 from the landing hand, and its pins sit in the plan's "Addendum from the complete plan": evidence classes and the wording ladder, the never-published list, the release evidence packet, the extra excluded knobs and the one acceptance rule, accepted work's definition, the bring-forward mechanism and seed-boundary behaviour, the adversary transition matrix, the evidence standard and the lifetime rule, the market-structure axis and the sensitivity workbook, operator experience with explicit update acceptance, the six negative proof tests, the D5 scenario table and the four user-facing states, the verification labels, the one machine-readable release manifest, reproducible builds and the signing-key procedure, the spend order (proof enforcement and finality boundaries first while the v6 evidence packet closes; hardware research and one narrow paid pilot in parallel; broad ecosystem expansion waits) and the mainnet prerequisites, the acceptance scorecard as a checklist, the brand kit. Mapped by the coordinator to owners with clocks and sent to main at 17:20 (the site lane 18:00 to 21:00; the hash and census lanes 23:00; the finality lane with the node lane 21:00; the adversary lane 21:30; the research lane 21:00; the shipper v2.0.1 and the manifest 19:30; the enforced-proving lane's map done at 17:06; the reference-apps lane 20:00; the node and fast-time lanes 21:00; the spend order and the prerequisites the coordinator's). The rotation lane closed with its control doc b0e7ba8c; run 5 tomorrow's amendment. THE SIX NEGATIVE TESTS mapped at 17:06 (the tree 019a12b1 on the 0.3.25 line, on release-2.0.0-node as dd84ed6a and f6cd2f00, green on build-2 at 16:15): (1) a correct statement with an invalid proof: enforced_a_record_whose_proof_fails_to_verify_invalidates_the_block and enforced_an_unverified_proof_pays_nothing_and_the_verified_honest_record_pays_once; (2) a wrong program or verifier identity: enforced_a_proof_for_another_program_id_invalidates_the_block, a_real_proof_verifies_and_a_wrong_statement_is_refused, the_embedded_keys_match_the_manifest, plus the daemon's start refusal (exit 3) when the embedded keys are not the object's; (3) wrong chain, epoch or statement binding: enforced_a_record_signed_for_another_network_pays_nothing, enforced_a_replayed_record_pays_nothing_the_second_time, assignment_follows_the_window_and_records_check_against_native_execution; (4) a changed payout identity: enforced_an_altered_payout_address_pays_nothing; (5) a duplicate proof reward: enforced_a_duplicate_of_a_paid_record_by_another_key_pays_nothing; (6) incorrect rewards or consensus inputs, the derivation authenticated: PENDING in the plan's sense, the native-veto test enforced_a_statement_over_altered_rewards_or_payouts_is_vetoed_native_derivation_is_the_check on build-2 (branch proving-payment), the proof-side closure P22's stages 1 to 3, the served label PENDING until stage 3; the boundary sentence in docs/spec/proving-enforcement.md's new section 3a and the P22 row. The node lane's two reads at 17:1x: the manifest block partly served today (igneum_getNodeInfo and the daemon's start lines); node 2.0.1 adds igneum_getManifest (one JSON block printed at start and served on the exec RPC, a test that both are the same bytes) by 20:30, and the four-word transaction state (included, executed, proven, finalised, plus paused with its reason; today igneum_getTransactionStatus hard-wires proven false and reports no pause) by 22:00 with the known-failed test asserting the pre-fix shape; both ride the D1 freeze entry's "what 2.0.1 adds" line. A FAULT: c04674fe's devnet-4 chain (born 16:59:53 BST) is dead by the node lane's re-cut 4cdcc488: its emission literal was Devnet 3's 8-decimal one in an 18-decimal unit, one ten-billionth of the schedule; the emission is in the digest, so be5f4068 replaces 08aae61c on the same genesis; the pair by 17:20, the fleet and build-1 restarting from wiped datadirs on the shipper's word, the first block again about 17:30 to 17:45. Build-3 out for the night (the Hetzner Robot console looping on its security check, no API credential on the Mac; the desk's one-line reset if wanted); the k lane's all-four synthesis relaunched on its pod. hl-v6-all on build-1 at 17:02 BST (the lane's "18:04" stamp wrong): /srv/artefacts/packs/hl-v6-all.tgz sha256 3fc7f75b0eefedd1845d914715c1d6d448bf716d0132a1dba8535e26281d36fe, 50,046 bytes; program id 0x9d40978601a7df2a; class string mx8-erad810f22d+sh256x27+state+reg64c+fold+rw; generator 5; the same era as hl-v6-foldrw (label d810f22d), era widths 4 bytes; state node1 (block 159357, root 1c583d35, 93 leaves); dataset log2 28 (1 GiB, the AND-mask path); program.h IGNEUM_REG64 1, IGNEUM_REG64_ADDRESS_MIX 1, IGNEUM_ERA_INDEX_FOLD 16, IGNEUM_OP_WEIGHTS_TABLE 1; program.json carries the reg64 object (64 registers, the window full chain, 128 statements per iteration, 256 loads per hash) and op_weights (rw1, sum 83); kernel.cu and kernel_bound.cu full (83 KB), the .cl and .metal texts the 169-byte refusal stub; branch class-v6 3f25a8305; the window's OpenCL and Metal texts start on class-v6 after the partner read-back, by 23:00. PC 1: the runner has taken nothing since the 15:50 app restart (the update-return lane has it with a default). The mixed FP32 lane's chip score at 17:1x BST (the k lane's synthesised rows, section 6.1 of mixed-fp32.md at class-v6-mixedfp e6d52e19): the FMA lane 3.4 pJ at N3, k 0.65 on the unit alone, 0.15 at the lock blended with the operand rule (which the chip does in wires and the card in instructions) against ARX's 0.18; the score under fp12 3.2x node-for-node, 3.5x a node ahead; KILL stands on the GPU budget and the full board; the Metal and AMD OpenCL rows owed, labelled; the lane closed on the spend order, its two v7 candidates named in the record (the exponent-fold injection form, the F8-form max-item rule), the document landing through the research-landing lane. The fifty-second landing on master at 17:15 BST (9ac9c195a). THE COMPLETE PLAN landed at 17:12 BST as 7b11fc7f (Merge igneum-2.0-plan-docs 2fb7a476; full gate GREEN 74): docs/plans/igneum-2.0-plan.pdf (257,211 bytes), igneum-2.0-plan.txt (2,292 lines), igneum-2.0.md (202 lines with the addendum); the research-landing lane's other landings: proving-pipeline-2026-10-08.md 8c5da92f (17:06), paid-pilot.md 1cd07adb (16:45), coexist-rows.md 11653ece (16:48); the D4 documents about 17:25 and mixed-fp32 e6d52e19 about 17:35 behind them. THE CENSUS SHEET at 18:1x on the lane's clock (about 17:1x on the Mac's): hl-v6-rw2 (the census lane's own table 13,11,6,10,8,8,7,2,6,4; program 09e91b0dcd458c77; run on build-4 after build-3 went down, about 70 minutes lost) FAIL on the F8 line: (A) accepted, min site ratio 0.99990, two sites with the era-stride bit at -64 sigma (no fold); (B) 256 of 256, 0 exhausted, r 0.410, (c''') 1.15 percent; (C) seed p30 1.3111x over the window model (the class v5 control on the same seed 1.0004x, its worst 1.0698x; hl-v6-rw's worst 1.1526x), beyond the 1.2x gate; the known-failed seeds under this table's draw p8 1.2507x (+42.8 sigma), p10 1.5044x (+100.9), p225 1.4049x beyond the gate, p34 +70.7 and p15 +13.2 sigma buckets: the table that keeps or at 4 and mul at 6 keeps the lossy writers F8's tails come from and adds weight to mad in front of them; the k lane's table (rw1: or never drawn, mul 4) is the one that reads clean; the re-weight is sound in the rw1 form only, rw2 is out. The sheet: fold PASS, rw PASS, foldrw PASS, rw2 FAIL, win and all in progress on build-4 (the 22:30 clock holds). An instrument finding on hl-v6-win (program f42d4a743ce7d4fa, reg64-v5 198d171d, the harness class-v6-census-reg64 1b676975): (A) and (B) read the class v5 control's rows on the same seeds to the digit (min ratio 0.99923, bucket +5.5, one site at bit 9 at -448; 256 of 256, r 0.716, mean attempt 2.52, (c''') 1.66 percent), because the window does not enter the draw and the acceptance's dynamic test interprets the eight-register program: the reg64 window changes the address path (src xor the rotate-xor chain over the other 63 registers) and neither the acceptance's run_unit nor the attack-f8 mirror models it; so (A) and (B) on the win and all packs say the base program under the rule, class v5's own verdict, and the window's address stream is read only through the crate's interpreter: a load-index trace on the reg64 liveness probe (verify::Probe, every load's index per lane; the reg64 line 3345f045e, the class-v6 line 1e6ffa6f9) and the F8-form uniform tool on it (per site the distinct ratio, the item histogram's top-0.1-percent share against a flat control, 16 seeds at 2^22, the era laid over, the closed-form dataset) building on build-4; the win and all packs' (C) from it, the known-failed set not applicable to the window (different addresses), the live-dataset f8 point owed for both; hl-v6-all (harness class-v6-census-all d7d441be, the id reproduced) steps A and B on build-4, its B rows 33 of 256 at r 0.154. THE CLASS V6 KIT at 17:14 BST: /srv/artefacts/packs/packs-class-v6-20261008T160432Z.zip on build-1, sha256 2c56bd063f1a8f60599c5a546c3e38bdf7b00c65adaa6852a0755fe641f0ec3b (847,590 bytes, 42 files), from class-v6 3f25a830 through the kit tree class-v6-kits d731991a (the Metal hosts sizing by the ds55 defines, the v6 kit script, the PC job scripts 6887a0cf); hl-v6-all (9d40978601a7df2a) reads on the CPU verifier (check PASS, 96 of 96 lanes) and on CUDA (the fleet hand's one-shot RTX 4090, 17:09 BST, USD 0.018: check PASS, cache FNV-1a 448274a57f508cbc, fingerprint 59e6708e46f1e87c at 31.4 MH/s, 87 registers, 20 of 24 blocks per SM) and REFUSES on Metal and Apple OpenCL by the stub, so AMD, Intel, Metal and Apple OpenCL wait on the window texts; the partner hl-v6-foldrw (605d06cabc489f94) reads 5a6ad122a71a888f on CUDA (62.6 MH/s, 27 registers), Metal and Apple OpenCL, three equal (the 7600 and the Arc through the PC queues after 21:15); the known-failed shape holds on every platform read; the page's class v6 row at class-v5 2cfe8513. A HAZARD found by the page push: master's counter-asic-4 merge at 6666e199 carries CA4's research changes to igneum-pow/src (the +mm tile and +shl classes, the AP-F4-1 constants in their OLD form, 163 and four rotations; 817 lines against class-v5's post-freeze igneum-pow), so a merge of master into class-v5 conflicts in generator.rs and memhard.rs and would put CA4's code into the class v5 hash object (the 0.3.26 pairing line); the lane aborted it and pushed the page alone; the coordinator's order: the research-landing lane reverts the igneum-pow/src, tests and proto-cuda changes on master from 6666e199 through the gate by 18:30 (the code stays on counter-asic-4), and until then class-v5 and class-v6 take no master merge touching igneum-pow/src. THE NEGATIVE TEST (6) green at 17:10 BST: proving::tests::enforced_a_statement_over_altered_rewards_or_payouts_is_vetoed_native_derivation_is_the_check, commit 421bb852 on proving-payment (on the D4 pin eaddbf83 off c04674fe), igneum-exec 67 passed on build-2 (the first cut failed on the lane's own reading: it altered the record's state root; the shard statement takes the plan's shard roots, so the test alters those); the six-test map and the boundary sentence on master at 17:13 as a6d3ead1d (docs/spec/proving-enforcement.md section 3a, the P22 row); the fourth fast-time run lost twenty minutes behind a worktree lock a dead ssh left on build-2 (its three nodes killed by the harness's pid file at 17:15), running, the result about 17:30. The steward at 17:13: class v6 380cd4eb (app tree 89e83df2, the freeze tree) all seven GREEN on build-2 at gate priority; release-2.0.0-node 4cdcc488's five node-side suites GREEN on build-4 with the miner side on the cut tip 7d82b71e (its pow and app cells green on both boxes, final); build-2's 4cdcc488 column from 17:12, the verdict by 17:28; c04674fe's record all seven green on build-2 and build-4. THE ADVERSARY LANE'S FINAL PLACED ROW at 17:1x BST ("complete 10b901a46" to the landing lane): the placed 18-family core (8 lanes, routed, SPEF, 58 tags) 9.36 pJ per lane-op on the class v4 draw at ASAP7 (8.6 to 11.1), 6.55 at N5, 4.72 at N3; placement +42 percent on this core, +32 on the genesis core, so the bank's placed cost is 20 percent of energy and 41 percent of cells; k 0.64 node-for-node, 0.46 a node ahead; the machine: the GDDR7 board 1.5x per joule node-for-node (1.3 to 1.7), 1.8x a node ahead (1.5 to 2.0), USD 4.84 per MH/s; the stored-half hybrid at the reconciled mean hit 0.581 1.93x (1.65 to 2.12) and USD 2.80, at the p98 hit 0.72 2.09x and USD 1.88, a node ahead 2.40x and 2.65x; the N2 SRAM die 2.3x / 3.1x; THE HONEST SAME-NODE BRACKET 1.5x to 1.9x per joule (the DRAM board to the stored-half hybrid), 1.8x to 2.4x a node ahead, 3x to 6x per dollar; the served 2.0x same-node line sits at its top and reads better as "1.5x to 2x"; the mm8 correction (the card's tile 32 MACs, the chip's op 4: the tile family at 4 points costs the chip +35 percent of lane-ops and +29 percent of energy, the card +29 percent of premium; the ratio holds, credit zero); THE TRANSITION MATRIX (section 14, six rows with bands and labels): firmware -9 to +1 percent per transition, emulation 1.3x to 1.45x while live (slower, not unprofitable), memory USD 0 on the 32 GB board through year 4 (24 Gb once at USD 1,000), the companion host +0.85 W and USD 15 per machine with the proving GPU on its own line, favourable-period mining 2 to 5 percent for 50 to 90 percent of revenue, a revision inside the bank refresh's 360-day notice; no row loses competitiveness, the three-year life holds; pending: the 32-lane full core synthesis (19:30) and placed (21:00), the k lane's crossbar and tile rows. THE RESEARCH LANE'S RE-SCORE at the final placed energies (the board 1.5x / 1.8x, the hybrid 1.93x / 2.4x at USD 2.80 per MH/s, the die 2.3x / 3.1x at USD 2.94): NO VERDICT MOVES: the board passes all seven conditions; the hybrid coexists only in a growing chain at cheap GPU electricity; the die fails once sunk; what moved is condition (b) (hardware per MH/s not under a quarter of the GPU entrant's): on the corrected tickets the hybrid (0.34 of the entrant's) and the die (0.36) now pass it, so the dollar condition no longer fails them; the fleet-cost condition (c) (a third of the chain USD 7 to 54 M against USD 12 to 400 M a year of revenue) and the margin condition (f) on flat and shrinking paths hold the verdicts, the die also failing (a); THE SERVED ENERGY SENTENCE now 1.5x to 3.1x as complete machines, 1.5x to 2.3x on the GPU's own node (10.0t); D4 complete on counter-asic-4 after 9402050e: lane 3's hybrid scoring with the sunk case, the market-structure axis (the board holds under every structure in growing and flat paths with no single supplier above 24 percent; the die under none but private supply in a growing chain), the sensitivity workbook (171 rows, every threshold with its assumptions, none served), the operator simulation, the proving-payment resolution with its code pin; the 21:00 landing at about 20:45. The update-return lane's restart-kind fix green and with the shipper as a v2.0.0 candidate (restart-kind-20 off release-2.0.0, tip da212ee2, suite 317 green, gate GREEN 60, 17:13: under the window host a remote app restart is the host's ladder after a plain EXIT, no helper racing it); the PC 1 desk ask standing with its 18:45 default. The pool design's cost line: the pool's per-share check 0.441 ms per 32-lane group on an M5 Max core, 1.35 to 2.1 ms on a rented 2 vCPU box, one BLS proof-of-possession check per key on its reveal block. The site audit lane's wipe in its gate on build-2 (site-2.0-wipe b9d4aa80 from 17:05; the first box run found a real 24 px padding fault on /light, /oracle and /receipt, the second its own half-fix; the landing inside 17:15 on the GREEN line). THE DIE TICKET PIN at 17:3x BST: at the adversary lane's final rows one coexistence verdict moves on a number two lanes price 5x apart: the N2 SRAM die's machine ticket, lane B and the chip model at USD 0.6 per MH/s (USD 0.25 to 0.4 of silicon plus the board), the adversary lane's complete machine at USD 2.94 (2.14 at the smaller ticket); the joules agree (2.3x to 3.3x per joule at the honest knee). At USD 0.6 the die fails conditions (a), (b), (c), (f) everywhere (a sunk USD 10 M fleet is 16 TH/s, 50 to 70 percent of the chain on landing, 100 percent of a flat chain by year 5); at USD 2.94 it passes (a) at 1.24x of the best GPU owner, (b) at 0.27 of the GPU entrant's hardware and (e), failing (c) (a third of the chain USD 9 M against USD 40 M a year at IGN 0.10) and (f): the hybrid's verdict, coexistence under private supply in a growing chain (16 / 14 / 8 percent of the chain, 13 to 16 GPU classes above water) and failure on flat or shrinking paths by year 5. The coordinator's ruling under the plan's evidence standard ("complete-board overhead"): the model's ticket is the complete-machine figure (USD 2.94), lane B's USD 0.6 row kept in the workbook labelled the silicon floor; the adversary lane asked for the one-line reconciliation of what its ticket includes by 18:30; the served form until then the range ("a sunk USD 10 M die fleet holds 16 to 70 percent of the chain on landing depending on whether its machine costs USD 3 or 0.6 per MH/s, and takes a flat or shrinking chain by year 5 at either"); the board's (c) tips to a fail at the final USD 4.84 ticket (six of seven), its coexistence rows unchanged (coexistence-model.md section 12b on class-v6-floor-sram 954db053, the rows in coexistence-workbook.md). THE IGNEUM 2.0 DEVNET IS BORN on the re-cut: block one f3dc319c83766310bbe7911252e6de6e357cdc9f280420ee8ce9dcc91ffaddc8 at DAA 0, mined by hub-1 at 17:14:21.531 BST on release-2.0.0-node 4cdcc488 (digest be5f406802cec1227a5ef50d42181ab42444f79af170775b22c85cb9a917273b, genesis 7c36b833, chain id 4465, every switch on from block zero, class v5 with byte 6 from genesis, enforced proving from block zero with the ids 0x2b1a81cb and 0x474678f3, base unit 10^18, the launch emission 31,688,087,810,000,000,000 base units a DAA second), accepted on build-1's seed at 17:17:40 with blocks two and three behind it; hub-1 311 blocks by 17:19:53; build-1's seed and hand on the chain with dn4-seed as a permanent peer, lp-4090-02 synced, lp-4090-01 up about 17:32; the first checkpoint lock when the 7,200-DAA window fills (about two hours at one block a second); c04674fe's chain of 16:59 dead with its datadirs. RULE 25 from main at 17:3x: the observer dropped every 2.0 block because the subsidy in wei (9,522,644,482,386,090,276) is past int64 (widened to numeric at 17:25): every wei-bearing column, field or JSON number is numeric, u128 or a decimal string, never i64 or a JavaScript Number; the sweep by 19:00 with owners named: the explorer indexer and API, the hub's hourly feed and the Discord webhook (the build-server lane), /api/live and the live page's JavaScript (the site lane), the relay's earnings feeds (the update-return lane), the app's earnings tab and the wallet's balances (the shipper, v2.0.0 if a Number sits in the path), the fleet tooling's tallies (the fleet lane). MASTER'S CRATE BROKEN since the testnet lane's landing 74254eb2 at 17:07 (lib.rs line 39 re-exports v5_class_at, v5_rung_reps, GENERATOR_VERSION_V5, V5_CLASS, defined only on class-v5's generator; the landing hand's proof: the untouched master 9ac9c195 fails cargo check on the box with that one error, independent of CA4's code); main's two orders: the fix is to land class-v5's generator onto master as its own gated commit by 18:30, not to delete the re-export (the class v5 object is the live network's object and master lagging it is the fault): the hash lane lands class-v6 c245d50b9 (the class v5 generator plus the window's OpenCL and Metal texts and one test fix; suite 136 passed on build-2 at 17:21, no counter-asic-4 merge in its history; the node lane's recommendation, the superset: master's igneum-pow becomes the D1 generator and the served kit and master read one fingerprint, a65e4c5ac0541095a01db9cbdc08e4cad8a07fe24efef3df736f41770acef6b1 as consensus/pow/build.rs computes it, the line already in the object's pow-freeze.txt and d1-freeze.txt), after the landing hand's ca4-code revert, with cargo check and the crate suite green on the box; the node lane lands it itself by 19:00 if the hash lane cannot; and a gate rule (RULE 24): any landing touching a .rs, Cargo.toml or build file runs cargo check and the crate suite on the box, documents-only landings excepted only when the diff is under docs/ and site/: the steward's tools/ci/rule24-crate-gate.sh (510740e0 on ci-rule24: every .rs, Cargo.toml, Cargo.lock, build.rs or .cargo/config in the diff mapped to its crate, cargo check then the crate suite on the box at gate priority; docs/ and site/ alone run nothing; merge-to-master.sh runs it against the merge base, the hook on a push of master or release-*; self-tested on a fixture repo), landing by 17:45. THE CA4 CODE REVERT (branch ca4-code-revert on master, one commit reverse-applying cbf5aa46's non-document diff, a clean three-way apply): igneum-pow/src accept.rs, emit.rs, generator.rs, lib.rs, verify.rs restored and mm8.rs removed; igneum-pow/tests ca4_trace.rs and v6_window_bits.rs removed, scratch.rs restored; proto-cuda/nvrtc cuda_api.h and worker.cpp restored, emu/list-race-stubs.cpp and emu/variant-test.cpp removed; proto-cuda/packs-ca4 (six packs, 72 files) removed; 85 files, 33,040 deletions; of the four direct counter-asic-4 merges on master (cbf5aa46 16:12, fc1f9b62 16:25, d6bee526 16:37, 6666e199 17:03) only cbf5aa46 carried anything outside docs/; the revert lands at the 17:35 default on its tree gate; the rule for the record: research landings are documents only, through the landing hand, never a direct merge; a lane that needs code on master lands it as its own gated commit named in the map. THE CUTS VERIFIED CLEAN by the steward (read, not argued): for every parent its matrices shipped (b891444f, a9e2df26, 7d82b71e and their 60x commits for 2.0.0; 89e83df2 and its 71e4786d, 01d2036b for class v6) cbf5aa46 is not an ancestor, none of its twelve paths exists in the tree, and igneum-pow/src is byte-identical across all seven (the class v5 freeze, fingerprint cbc5bd0a, rule 19 checking it at build time); the node forks (4cdcc488, c04674fe, 380cd4eb, 617cb441) carry no igneum-pow of their own and linked that tree; the D1 object on class-v6-node links the override copy from class-v6 (merge base with master f37f497b3, below 6666e1991). The window's OpenCL and Metal texts on class-v6 at c245d50b9 (17:22 BST; one schedule, one init, one full-chain mix line and one fold from shared helpers in the three dialects; the stub gone); hl-v6-all re-exported with them (sha256 22c64fa5a753b38206442fa42136956f10378e76c2d289f0e38d8c28c69976d4, 91,013 bytes; the same id; kernel.cl 93,248 bytes, program.metal 81,201; the stub pack kept as hl-v6-all-stub.tgz); the second kit zip packs-class-v6-20261008T162324Z.zip sha256 098e64c3e0dc1dc727c4ded34d16a31d1ae2802b76f9c09c06b2bea9720fa108 (891,160 bytes; class-v6-kits a9ea072d): THE ALL PACK READS 59e6708e46f1e87c ON FOUR PLATFORMS (the CPU verifier, CUDA on the fleet's 4090, Metal and Apple OpenCL on the M5 Max at 17:24, 12.6 and 8.9 MH/s), the partner 5a6ad122a71a888f on three; both known-failed pairs distinct on every platform read; the two remaining platforms per pack AMD (PC 1's RX 7600, stalled until the desk) and Intel (PC 2's Arc, about 18:30); the page's row at class-v5 7f4e1039; the 23:00 line six of six if the PCs answer, else four of six on the all pack with the two PC reads the morning's. The hot-set reading confirmed by the census lane: the bit read per site inside the window; the F8 verdict per item over the whole dataset against the window-model null; the flat-control ratio 1.1 to 1.7x on every pack, the adversary's number; the "layer 8 off" D2 experiment stands. The hash lane's clock correction: the stub all pack landed at 17:03, the merge line at 17:02 (its "18:04" and "17:4x" copied the box's CEST). THE DIE TICKET RECONCILED (the adversary lane's section 15 at d3ad15493; floor lane 3's 12c at 7b894eaf; the research lane's commit after 346c24c0): the gap was two machines, not two prices: lane B's USD 0.6 per MH/s is the 2 GiB die at zero shadow (2,100 MH/s at 300 W, no shadow core); the 2.94 the same die carrying the class v4 shadow on the placed core (13x the die's energy per hash) held at 270 W, 383 MH/s; the adversary raises the power budget until the power train and the core silicon bind: on the placed core 852 / 1,420 / 2,130 MH/s at 600 W / 1 kW / 1.5 kW, USD 1.63 / 1.20 / 0.98 per MH/s, with a pipelined core and an organic package 1.07 / 0.73 / 0.56 (the die USD 500, 400 to 600, claimed; the core silicon USD 0.11 to 0.55 per MH/s; the package USD 60 to 200; the board USD 150 plus USD 0.15 per W of PSU and cooling; the host USD 15); RECONCILED at about USD 1.0 per MH/s (0.5 to 1.6) at 1 to 1.5 kW, the joules unchanged (2.3x node-for-node, 3.1x a node ahead); a maker's first batch of 1,000 dies pays the project (1 to 2 TH/s several times the chain: USD 50 to 250 per MH/s of NRE) plus first-yield losses. Floor lane 3's re-run at it: THE DIE FAILS (a) at 2.06x of the best GPU owner, (b) at 0.09 of the GPU entrant's hardware, (c) by 12.6x at IGN 0.10, and (f), at the centre and both ends, passing only (d), (e) and (g); the 12b pass of (a) and (b) was the 300 W artefact; a sunk USD 10 M fleet (10 TH/s, 6 to 20) holds 42 percent of a growing chain and 62 of a flat one on landing (27 to 93 across the band) and 100 percent of every flat or shrinking chain by year 3 to 5; the one coexistence-shaped cell private supply in a growing chain at 24 percent by year 5 with 16 classes above water, the conditions still failing; the die's economics are project economics (NRE USD 47 to 352 per MH/s against USD 1 of unit cost; p* 0.50 / 1.24 / 2.48 at a third for C_dev 100 / 250 / 500 M); the board (six of seven at USD 4.84) and the hybrid (coexistence only in a growing chain at cheap electricity) unchanged; the site lane has the die sentence's final served form. The finality lane at 17:25: the D5 partition row complete, both build-4 runs in (cores released 16:16 and 17:20): branch finality-boundary 7d129358e with docs/spec/finality-guarantees.md (rule v4: the anchored table plus the majority-continuity recovery, safety and liveness with arguments, what is not guaranteed, seeds during a pause, the four words), the pointers in 03-finality.md, O-3.20 and the O-4.3 close, sim/finality_v2.py (rule v4, scenario N), the "Rule v4" section of sim/results_v2.md, and in the plan under D5 the partition row as the chain's behaviour, the six-scenario table mapped to the evidence with gaps and clocks, the bring-forward and seed pipeline pins, the user-facing rule; the rows: v3 known-failed reproduced (sim and real nodes), v4 pause 0 conflicts everywhere, v4 recovery 0 conflicts without an equivocator mining on both sides, the bound measured (2,800 to 2,889 conflicts at day 30.00 with one), silence, departure, bought and stolen keys, the heal; the word to land on the box mirror's master after the revert; the founder's one-switch choice (recovery as written, recommended, or pause only) open in section 6.5, the default at 20:00 the document as it stands; the node lane's 2.0.1 queue takes rule v4 by 22:00 (frozen_table without its time drop, continuity_met behind finality_v4_activation_daa, never on every network, both variants behind the one switch). The enforced-proving lane's fast-time crossing PASS at 17:22 BST on build-2 (local nodes, floor DAA 240): below the floor H1 paid the attacker's forged record (the finding observed); at the floor nothing paid, nothing of the attacker's carried, four new REFUSED verdicts on each honest node (0.000 to 0.003 s each from the relay-time cache); the attacker's trusting pool carried five of the seven shapes, its own unmodified pool refused the other two (wrong network id, altered payout); the amendment on enforced-proving 896ef93ab in the gate; row 6's served label moves from PENDING to team-tested for what the native-veto test holds, the proof-side part PENDING until P22's stage 3, on master by 17:50; the shard guest's mirror of the 90/10 split: the enforced-proving lane's, on proving-payment-guest, green by 10:00 tomorrow, the re-pinned ELF and program id in elf/manifest.json by 12:00 on a build box; proving_payment_activation_daa at never until then. The site lane's wipe on master at 9b432c97 (17:22 BST), the follow-up (the final chip sentence, the first block at 17:14 with the badge live, the labels, the tip-share rows) by 18:00. The node lane's 2.0.1 queue on release-2.0.0-node: the manifest block and igneum_getManifest by 20:30; rule v4 by 22:00; the four-state transaction RPC with the pause word by 23:00; the five-together integration harness as the fast-time lane's case by the morning's first cut; the D1 object by 23:30 after the revert and the generator landing. The mixed-fp32 document on master at 690b7c70 (17:21). The update-return lane's PC 1 reading: stalled since the 15:50 restart (the restart kind's relaunch race lost twice on 0.3.20); the desk brings it back; the restart-kind fix da212ee2 a v2.0.0 candidate. THE CA4 CODE REVERT ON MASTER at 17:2x BST: 4ee346303 (Merge ca4-code-revert 98976b31, the gate green); reported to main at 17:31 with the cuts' clean read and the rule. The finality lane's landing follows it (its merge running, MERGE_REMOTE=build, documents, sim and the plan only; section 9 of docs/spec/finality-guarantees.md "The four interface words" the site lane's link; the user-facing rule under D5 in the plan). The fifty-third landing on master at 17:37 BST (68b889ee2). The 2.0.0 pair's gates: every line green since 17:30 (build-2 at gate priority: igneum-exec 65, kaspa-consensus-core 180, kaspa-consensus 140, igneum-miner 30, kaspa-p2p-flows 38, kaspa-pow 19, 0 failed; build-1's devnet-4 canary on the pair, igneumd 60f45b65, printing digest be5f4068 on two empty nodes, the enforced-proving line with the two ids, eth_chainId 0x1171, the handshake); the fast-time SUMMARY PASS (cross-200-4cdcc488) at 17:29:58 BST (17:14:20 to 17:29:58 on build-1 under class v5, the freeze fingerprint on both binaries: rung 1 at 17:20:38, class v5 by signal at byte 6 from epoch 8 at 17:22:33, 12 of 12 ids equal to the freeze CLI's, the stale node 140 of 140 refused, the restart step resynced in 9 s with the catch-up done after 5 s, four sinks equal at 853, 0 PoW rejections and 0 submit timeouts); the mixed-version refusal between the two devnet-4 objects read on the live chain (build-1's seed refused the c04674fe light reader "local be5f4068 remote 08aae61c" at 17:18:33; hub-1 refused the old seed three times 17:13 to 17:15); the canary gains a devnet-4 mixed-version node for the next cut; the shipper's 17:50 fleet minute and the apps' entries ride 4cdcc488's pair (/srv/artefacts/200-4cdcc488/node-lane: igneumd 60f45b653bbb8ab0, igneum-miner c19913b5ea380054). The class v6 clean rerun SUMMARY PASS (cross-v6-617cb441-3) at 17:30:44 BST (every check green incl. the cold restart on 4 of 4 after 660 s; the known-failed shape FAILED as it must; v5-fasttime 92bf6a7f); the missing case: the dataset schedule's size step, unreadable until the v6 generator pairs. RULE 24 ON MASTER at 17:34 BST as 7f8177cf (on build-2 and build-4): the hash lane's c245d50b9 landing its first real crate-touching run. The 2.0.1 manifest item in ahead of 20:30: release-2.0.0-node d5981514 (4cdcc488 plus one commit): the node prints one "Manifest: {...}" line after its start lines and serves the same bytes on igneum_getManifest (the network id, consensus digest and genesis; the version string and source commit; the pow engine with the igneum-pow fingerprint and freeze status; the object byte and the mining class at genesis; the dataset parameters; the finality rule with its activation and window parameters; the verifier block with the shard and aggregator ids, the proof rule's activation DAA, the prover version, inConsensus; every switch by name with its activation DAA or null; the fee schedule; the blockrate; the listen addresses; the D1 baseline line empty until the class v6 line's d1-freeze.txt rides the 2.0 line); the test the_manifest_printed_and_served_are_the_same_bytes; 4cdcc488 stays the live pair until the shipper names 2.0.1's cut; the steward's matrix on d5981514 behind. Rule v4 into release-2.0.0-node from section 6.2 at 7d129358e: the anchored table never expiring by time (Q5's expiry clause removed from frozen_table, the two-thirds-of-T_f test while daa(C_i) < daa(C_f) + 2,592,000), the majority-continuity recovery (past a full window with no certificate a lock needs Q3 both tests AND 2 x signed_f > total_f), C_f an ancestor of C_i, a recovery lock re-anchoring T_f with finality_reason "recovered", no anchored table before the first certificate; behind Params::finality_v4_activation_daa (never on every object, the digest arm once set, the 60x key) with finality_v4_recovery: bool (true = items 1 to 5, false = the pause-only variant), so the founder's 20:00 choice sets the flag on the object that first activates it; the known-failed tests first; the commit by 22:00; the finality lane asked for its two test names and the v4 harness line by 20:00. THE FINALITY LANE'S LANDING ec9ea053d at 17:35:32 BST (Merge finality-boundary 9926d6ca; the full gate green, 74 checks; "docs/, sim/ and docs/plans only; no .rs, Cargo or build file; igneum-pow and proto-cuda equal master's after the revert"): docs/spec/finality-guarantees.md (section 6 rule v4, section 8 the seed answer, section 9 "The four interface words"), the pointers, O-3.20 and O-4.3, sim/finality_v2.py and the "Rule v4" tables, the D5 block in the plan; the lane closed with its report (the node change, the v4 harness line after it, the paused-epoch program-id read, the two 8 October regressions as harness rows and the five-together harness owed to the node and fast-time lanes). RULE 25's sweep: the build-server lane: the observer FIXED (0f5ee875: subsidy_sompi and paid_sompi numeric(40,0), the insert cast ::numeric; the box copy widened 17:25:27, the dn4_ observer inserting since), the explorer indexer CLEAN (value_wei, balance_wei, gas_price, effective_gas_price text columns through hexBig; hexInt's Number(BigInt) only on block numbers, nonces, gas, status and timestamps), the explorer API CLEAN (strings; the 24 h sums in SQL cast ::text; the 80 percent share BigInt), the live API CLEAN (payout_wei text through BigInt, IGN to four places), the hourly feed and the Discord webhook CLEAN (Number() on counts, weights and the scaled IGN floats); a naming note: the observer's columns still called *_sompi while the 2.0 chain writes wei; the site lane: CLEAN on /api/live, /api/explorer, /api/supply, the live page, the explorer strip, /address, /tx, /proving (every money field through ignFromWei, a BigInt divide by 10^18) and /income; ONE FAULT of its own: /block formats the coinbase through ign(), a BigInt divide by 10^8, so on the 18-decimal chain it shows the coinbase 10^10 too large; the fix (the 18-decimal formatter) in the 20:00 sweep; its follow-up on master at 3511bbca (17:31). The site lane's scorecard plan: /scorecard as a checklist page (page 25's twelve gates, the evidence required, "do not substitute") with every row's status read from the facts page's rows and labels, no completion mark; the release evidence packet on every facts row; the four-deliverable table (D1 to D5 with the evidence file beside each) on the litepaper's roadmap section by its 19:00 default (a /mission page only on the founder's word). The class v5 lane's full gate on class-v6-kits a9ea072d RED on one check, 72 of 73 (the /swap status cell's live-render clip again, "block 749 of at least 26,972" at 768 to 1280 px; the DEX lane's cell; the kit tree touches no site/ file; one master merge and one full gate each close class-v5 and class-v6-kits once the revert and the /swap fix are on master). The research lane's D4 documents on master at 859b3daa (17:34; coexistence-model.md, operator-simulation.md, proving-payment.md, 10.0h to 10.0r, spec 05 and 06); the commits since on counter-asic-4 at 884e4313 for the 21:00 landing (the sensitivity workbook, the market-structure axis, the die's reconciliation and 12c, the final placed energies, the block-one emission figure, the FP32 rows); the adversary amendment 10b901a46 on master as e59bc3bda (17:28); twenty research landings through 859b3daa. Rule 25 on the miner app: FIXED, aa354ed5 on release-2.0.0 (in the Mac v2.0.0 entry live since 17:37:09 BST, in the Windows payload to come): every wei field the engine holds is u128 serialised as a decimal string (paid_wei, segment_paid_wei, earned_all_wei, the window rows, balance_wei from the hex read); the window turned three into a JavaScript Number for the IGN figure (the proving paid line, the segment paid line, the wallet balance), the fault; the IGN figure now cut from the string (whole units and four decimals), no wei value in a Number anywhere; the earnings card's figures already Rust u128 to IGN; the fleet and relay paths report on their own; the block-one emission 3.168808781 IGN exact to main. MAC v2.0.0 LIVE at 17:37:09 BST. BUILD-3'S SILENCE EXPLAINED from the founder's inbox at 17:4x BST: Hetzner's switch fault hel1-dc12-sw_99, the outage identified at 16:44 BST on AX102-1 #3084968 (62.238.91.43); no reset; the box returns when Hetzner fixes the switch; the lanes stay on build-2 and build-4 and nothing re-queues back until it answers for ten minutes. RunPod reports a server issue on pods 6ly14yf2b9b7lw and ks8dx9r4wdiugt: the k lane's fk-adv and fk-tm are not them and answer (the core8r64g placement alive in CTS timing repair; the 18:30 row stands); the adversary lane asked by 18:00; a pod not answering by 18:15 is destroyed by its pid-file rule. RULE 26 from main for the gate (the steward, by 19:00): two landings today (the og lane's 16b3e140, the release-manifest 6fc57381) reverted the reference-apps lane's files on master (receipt.html, then all of site/lc), restored by its own merges: a landing that touches a path another lane has landed since the branch point must be a merge with master's copy, never a replace; the merge tool refuses a landing whose diff deletes or reverts lines on any site/ or docs/ path changed on master after the branch's merge base unless the landing's message names the path as intentional. For the node lane's record: on the 2.0 devnet a plain transfer's receipt gasUsed reads 21,000 against a quote of 59,650, so the proving dimension is not in gasUsed for a transfer; /compatibility serves it as a measured difference. THE D1 GENERATOR ON MASTER at 17:45 BST: 9ba4e0e43 = the merge of class-v6 13885e16f (c245d50b9 plus the merge of master 4ee346303 after the revert plus one fix dropping master's second copy of DatasetSource's leaves methods); igneum-pow on master byte-identical to c245d50b9's tree, so the class-v6-freeze fingerprint a65e4c5ac0541095a01db9cbdc08e4cad8a07fe24efef3df736f41770acef6b1 stands and master reads it; before the merge the build-2 suite on 13885e16f 136 passed, 0 failed, 8 ignored, the pre-push gate green on the branch and the merge; the conflicts resolved on the branch: igneum-pow memhard.rs, main.rs and tests/packs.rs kept class-v6's text (class v5's mixer-draw rule in the agreed AP-F4-1 form, cost 205 with w32, where master carried the first form, NAF sum 163; the ds55 and reg64 arms of epoch_of; the window tests), site/litepaper.html master's, docs/ledger-public.md and site/ledger.html regenerated from the merged fud-ledger-2.0.md; rule 24's crate gate ran on it as the first real diff; the mirrors build-2 and build-4 took it, build-3 down. The node lane's D1 close: master at 07e5fa680 with 9ba4e0e43 below; git diff --stat c245d50b9 master -- igneum-pow empty; proto-cuda on master the post-revert tree (98 files, 25,242 lines removed against 6666e1991); the D1 entry names the generator at class-v6 c245d50b9 = master 9ba4e0e43's igneum-pow, fingerprint a65e4c5a, no counter-asic-4 code path in the object; the parent-side landing (spec 01, the D1 section) cuts off 07e5fa680 by 23:30. RULE V4 ON release-2.0.0-node at bee41b5e (both mirrors, 17:45 BST, the 22:00 clock met four hours early): frozen_table never expiring by time, FinalityManager::anchored_test at the three sites (two thirds inside the window; past it strictly more than half with the recovery, nothing without), the recovery lock logged and reported "recovered" for one window and re-anchoring as the next lock, Params::finality_v4_activation_daa (never on every compiled object) and finality_v4_recovery (compiled true, the recommendation; the founder's choice by 20:00 sets the object that activates, default recovery), both in the digest once the floor is set, the manifest's switches carrying both, the 60x file's two keys (parent d9e15a2ae); the finality lane's two tests green with the known-failed line first (kaspa-consensus 142, consensus-core 180): rule_v4_the_anchored_table_never_expires_by_time (the M3 shape; A alone never locks past the window under the pause; a hand-built A-only certificate refused; B's return locks at once) and rule_v4_the_majority_continuity_recovery_locks_after_a_full_window_and_re_anchors (A at 60 percent locks at the first index a window past C_f, stamped recovered, the table re-anchoring; exactly half fails and 51 of 100 passes; an off-chain recovery certificate refused; a key under dust at C_i signs nothing); the four harness lines (split50 v3 known-failed, v4 pause, v4 recovery; split70 past the expiry where the recovery fires once; the same v3.mjs command with SPLIT=420 and the override JSON carrying finality_v3_activation_daa 0, finality_v4_activation_daa 0 and finality_v4_recovery false or true) under the lease pool on build-2 the minute bee41b5e's pair builds; the simulator has no --rule flag (scenario N runs rule_v3, rule_v4 and rule_v4r itself). The shard guest's mirror of the D4 split ahead of its clock: proving-payment-guest 6dbd5d2f8 (off master f29dae620), green on build-2 at 17:44 and 17:46 (fee_switch_tests 5 passed with the known-failed test the_proving_payment_flag_moves_90_percent_of_the_charge_to_the_pool; the core and host suites 8 and 10 passed): FixtureEnv::proving_payment_to_pool (serde default false), the split at both charge sites of core/src/executor.rs with the node's arithmetic, the exporter reading the node's segment JSON (provingPaymentToPool, from the receipts; proving-payment 930b6322 on the fork, igneum-exec 67 passed at 17:38); not done: the ELF, verifying key and program id re-pin (pin-guests.sh on a build box with the Succinct toolchain, by 12:00 tomorrow; the re-pin on build-1 running at 17:5x with a pid-file kill at 18:40 if it overruns); the rule stands: proving_payment_activation_daa at never on every object until the new id is pinned. The served 2.0 ledger's D5 row on master at 17:46 as 07e5fa680 (proofs as a condition of payment: fixed in the node behind verifier_in_consensus, team-tested, awaiting the live read on igneum-devnet-4, the "was" line kept); master's enforced-proving landings today 5423b3277, a6d3ead1d, 1beab15ed, e8d8067e, 07e5fa680. Rule 25 on the relay: CLEAN (every Number() in relay/lib/parse.mjs and relay/api/console.mjs on a count or an id; the relay's tables stamps, text and jsonb; the relay never reads a subsidy, balance, reward or payout). PC 1 BACK: the engine at 17:23 BST, the 0.3.26 engine at 17:26 after the queued update-install (run win-ae432dc7-20261008-162603, installed 0.3.26); the signed-jobs queue fetched again (the read-width job took first, then the kit fetch; the queue not strictly file order); the relay agent zip for PC 1 live at the tokened URL; the one-exe-per-PC bake to the shipper by 18:10. MAIN'S SESSION CRASHED AND RESTARTED at about 17:5x BST; the shipper lane stopped and resumed by main; the coordinator's roll call to every lane by 18:05, every lane alive bar the shipper, the list to main at 18:09. RULE 26 ON MASTER at 17:58 as d49d3f68 (tools/ci/rule26-no-revert.sh in merge-to-master.sh after rule 24: for every site/ or docs/ path master changed since the branch's merge base that the branch also touched, every line master added must be present in the branch's copy; a deleted path counts as every line lost; a commit message naming the path lets it through; self-tested on the fixture: a replace and a deletion refused, a merged branch, a disjoint path and a named path pass); bee41b5e's node-side suites five of five green on build-2 at 17:57. LANE D'S GENESIS-TABLE VERDICT at 18:00: PASS on the or-floored copy (add 13, xor 13, mul 4, mad 11, shfl 3, rotl 10, sub 9, mulhi 2, rotr 9, or 1) at both widths and on the exact table's F8 census: width 4, 2,497 eras: r = 0.329 per candidate (the band 0.62, the shipped draw 0.68), mean attempt 0.49, max 10, 0 past 31, 0 exhausted, (c''') refusing 15.6 percent of the candidates reaching the 2^20 pass, the accepted draw's minimum ratio p1 0.9960; width 1, 1,500 eras: r = 0.191, mean attempt 0.24, max 4, 0 exhausted, (c''') 1.0 percent; the index-bit read over 6 sigma in 40.5 percent of eras at width 4 (51.1 at width 1), over 300 sigma 9.3 (22.6): the bit-R mechanism unchanged by the table; attack-f8 at the exact table (or = 0) on 64 seeds at 2^20 on the Devnet 3 state: 0 hot sets, 0 over 1.2x (worst 1.103x), 12 of 64 on the bucket class; the table halves the draw's cost (the lossy share 6 of 75 cuts (a') from 76 to 58 percent of rejections), keeps the floors' costs at the width's level, adds no hot set; owed: the exact-table attempts rows at both widths (466 and 401 of 1,500 on build-3 at the outage, the build-2 fallback 70 minutes on a full pool; they differ from the or-floored copy by one point of or, 1.3 percent of instructions); section 6.9 landing by 18:10. THE CENSUS LANE'S FINAL SHEET at 17:55 (the lane closed): hl-v6-win PASS (A: accepted, min site ratio 0.99923, bucket +5.5 sigma, the base program's one stride-bit site at -448 sigma, no fold in this pack; B: 256 of 256, 0 exhausted, r 0.716, mean attempt 2.52, max 15, (c''') 1.66 percent, the window not entering the draw; C: the window's own address stream through the crate's interpreter under a tracing probe, 16 seeds at 2^22, all 32 sites of the interleaved schedule: the per-site distinct ratio 1.0026 to 1.0027, every site clear of 0.98 and 0.995, the item histogram's top-0.1-percent share 1.0645 to 1.5624x of a flat control against the control's 1.0738 to 1.5074x, paired by seed 0.968 to 1.036x: the layer-8 hot half the null and the window adding at most 3.6 percent to it); hl-v6-all PASS (A: accepted, min site ratio 0.99993, bucket +5.75 sigma, worst free bit 3.49 sigma, no site over 6 sigma; B: 256 of 256, 0 exhausted, r 0.117, mean attempt 0.13, max 2, (c''') 0.34 percent; C: per-site distinct ratio 1.0026 to 1.0027, the item share paired 1.004 to 1.035x of the foldrw control): the window changes nothing the rule or the F8 form sees at 2^22 on the closed form and carries the fold's and the table's rows unchanged; what it buys is the chip-side cost. THE FINAL SHEET: fold PASS, rw PASS, foldrw PASS, rw2 FAIL, win PASS, all PASS; owed on the window packs: the live-dataset F8 point at 2^24 (the attack-f8 mirror interprets eight registers; a two-window interpreter four to six hours) and the 64 x 2^24 point every pack owes; the record docs/analysis/class-v6/census-packs.md on class-v6-census-all 25098c1a2 (the six-pack sheet, the harness and its pinned digests, the exact commands, the four instrument faults found and fixed, the owed items) with the logs under docs/analysis/class-v6/logs/census-packs/, landing about 18:40; the harness branches for the freeze's digest: class-v6-census-fold 5b3486f0, class-v6-census-reg64 b29e690d2, class-v6-census-all 25098c1a2. THE D1 OP-MIX TABLE NAMED by the coordinator at 18:09: rw1 as exported in hl-v6-all (add 16, xor 14, mul 4, mad 12, shfl 4, rotl 11, sub 10, mulhi 2, rotr 10, or 0; sum 83, or never drawn), the k lane's optimiser split, the census PASS on rw, foldrw and all, lane D's acceptance PASS on the same mix in its or-floored and exact forms at both widths; lane D's renormalised sum-75 form differing by one shfl point, not a second table; the node and hash lanes told. THE READ-WIDTH LOCK ROWS on PC 1's 5090 (the read-width b job, closed green; PCIe gen 4 x16 since the eGPU swap, every row about 13 percent under the morning), the 1,300 lock: v5-genesis 132.7 MH/s at 314.8 W (2.37 µJ); rw-w4 (W = 4, the era class) 140.7 at 322.8 W (2.29 µJ); rw-w32 (W = 8 words) 119.1 at 303.7 W (2.55 µJ, +11 percent per hash); rw-w64 (W = 16) 67.7 at 277 W (4.09 µJ, +78 percent; 4 warps per block 64.5 at 269.5 W); the class v2 controls rw5-w4 133.9 at 221.3 W (1.65 µJ) and rw5-w64 48.7 at 206.2 W (4.24 µJ); unlocked: W = 4 141.3 at 471.9 W, W = 8 140.2 at 494.4 W (+5.6 percent per hash), W = 16 78.9 at 448.4 W (+70 percent); the w64 lane count 1 to 8 warps per block moving the rate under 3 percent; W = 8 and W = 16 stay out as regression controls, the lock widening the gap. THE 5.5 GiB ROWS on PC 1's 5090 (run-ca3-pc1-ds55-5090-20261008, closed 17:50; the pinned class v3 program at both sizes, the fingerprints PASS and equal to the rented card's): the 1,300 lock: 1 GiB 137.0 MH/s at 218.2 W (1.59 µJ); 5.5 GiB 116.5 at 212.1 W (1.82 µJ): +14.3 percent energy per hash, 15 percent less rate; unlocked: 1 GiB 140.7 at 316.3 W (2.25 µJ); 5.5 GiB 135.8 at 320.1 W (2.36 µJ): +4.8 percent: THE 5.5 GiB DATASET FAILS THE 10 PERCENT BUDGET ON THE 5090 AT THE KNEE while passing at stock. The research lane's 10.0u (the dataset schedule scored per step, in the 21:00 landing): the commodity burden at 5.5 GiB +14.3 percent at the Blackwell knee (over the budget), the 12 GB tier's loss of mine-and-prove co-residence, the 8 GB tier on 1.8 GB of headroom, Apple about -18 percent of rate; the adversary burden nothing on the pure DRAM board, 1.2x the hybrid's ticket (USD 250 to 690 of SRAM), about 1.5x to 1.7x the die's, no chip's joules moving; no coexistence verdict moves; the 5.5 GiB knee row sits 10 percent above the 8 GiB power-of-two row, so part of the cost is the non-power-of-two mapping's multiply in the dependent chain, which the lock exposes (the control: a 4 GiB power-of-two row beside a 5.5 row on the same card); change (3) revised to 4 GiB at genesis (+8 percent measured at the knee) with the 5.5 / 8.5 / 11.5 steps retired to the workbook as the costed alternative, later steps only when the chain's state outgrows them; the site's sentence sent; what would reverse it: a power-of-two-mapped 5.5 GiB control inside the budget at the knee. The coordinator's ask to main with its default: class_v6_dataset_steps is a consensus field, main's word by 20:00, the default 4 GiB at genesis with the ds55 mapping kept in the generator as the costed path; the node lane holds the field. THE 7600 OPENCL JOBS: the three (card-in, ds55, the class v6 kit) exited in 1 s on "no device matching 7600" (the RX 7600 reports as gfx1102; the scripts matched 7600, gfx1200 or gfx1201); fixed at a9f8c6fb8 and republished (run-ca3-pc1-amd-cardin-20261008T1649, run-ca3-pc1-ds55-7600-20261008T1649, run-ca3-pc1-v6all-7600-20261008-b); the 7600 knob grid failed on card_not_mining (the app has the 7600 enabled at hash 0.0, mining off under the Devnet 3 off order), its rows the morning's after the PC mines on the 2.0 devnet. "LAYER 8 OFF" assigned by the coordinator as a D2 experiment to the hash lane with the adversary lane on the chip side, clock 12:00 tomorrow (the 5090 and 4090 rows at stock and the knee against the pinned pack, the chip-side d2b.py rerun at hit 0.50, the acceptance on the draw with the layer removed through lane D's harness; the pass rule the one acceptance rule); tonight's object unchanged. THE GUEST RE-PIN done tonight ahead of the 12:00 clock: proving-payment-guest afd952e89, re-pinned on build-1 at 17:49 with the build-server lane's SP1 6.8.1 toolchain under lease pool 16 at nice 19, the host's pinned tests 10 passed; the new shard program id 0x282dcfce483565a358268a6228b32beb1c48f4ee58095950364f9e5e6f5122b4, the aggregator id 0x3fd721e8482357780fd55904101cbdc316a5a7ec07c0dac47040696d57a328bd; the rule now a two-step: an object may set proving_payment_activation_daa only when it also pins the new shard id and every prover and verifier runs the node and host built from this elf/ (a node release, not a flag); nothing landed on master from the branch, the crate landing under rule 24 by 19:00 through the landing hand. The fleet lane at 17:5x: 99 of 99 boxes on digest be5f4068 at 17:54, 36 miners, 12 miner keys on hub-1's chain in the last ten minutes, hub-1 RSS 694 MB at 2,478 blocks; the two RunPod pods: 6ly14yf2b9b7lw was ln-node-07, a bring-up that never completed (no puller, no devnet-4 node), destroyed at 17:55 by its id (USD 0.13/h stopped); ks8dx9r4wdiugt is ln-node-10, a devnet-4 voter on the new digest, restarted by pid after a double start, kept; RunPod's flag not seen from inside. The update-return lane: the one-exe-per-PC bake delivered to the shipper at 17:50 (the baked PC 1 and PC 2 agent folders with their own secrets, the silent install entry on agent-install-20 072b2e71, relay tests 65 green; the PC 2 exe folder on the dl site with no-store); PC 1 on 0.3.26 since 17:26 with both channels up (the relay agent polling since 17:45, its logon task registered 17:48); PC 2 on 0.3.21 with its relay agent polling; restart-kind-20 da212ee2 merged into v2.0.0 at 297a2662 by the shipper at 17:16 (the DMG re-cut on it). The reference-apps lane: /compatibility with 20 of 20 rows PASSED on igneum-devnet-4 (real transactions, 17:31 to 17:34) on master since 17:42 (merge 8e947c3b, tip aa01681d) with the labels, the proof boundary and the data-availability paragraph on /light, /receipt and /oracle; deploying; the oracle redeployed on Sepolia for chain id 4465 at 17:53 (0xbb3450049926da3572e6b67cb94df312fe349e34); the devnet-4 re-run rows at the chain's first finality lock and first paid segment (finality not active at 17:53, tipDaa 2,554). The build-server lane: devnet-4 on build-1's own public node (rpc.devnet.igneum.network, /ws, /light, the faucet funded, the dn4_ observer and explorer indexer since 17:22); the site at 3511bbca keyed on igneum-devnet-4 (/api/live reading dn4_ since 17:47); the observer's numeric fix on master as ec9ea053; the Windows 2.0.0 payload on aa354ed5 at 18:05, PC 2's installer by 18:15. The fast-time lane: nothing in flight; the "five-together integration case" read as the 617cb441 run (the ladder's rung step, the v5 crossing, the v6 object's crossing at its floor, the restart step across the boundary and the cold restart on every node, plus the stale node, in one 60x network), its PASS at 17:30:44 the line unless a different five is named by 18:30. The site lane: one landing about 18:05 (b45bf6d4 on site-2.0-followup, gated on build-2) carrying the litepaper and positioning items, the labels and the ladder, the rule-25 /block fix, the four-words sweep with section 9 linked, the die sentence, the coinbase row, the Mac first-open notice, /scorecard as a checklist with the do-not-substitute column, the evidence packet on every facts row, the five deliverables on the roadmap. The fifty-fourth landing on master at 18:00 BST (c6959010c, after two races with master moving under it). THE FOUNDER'S TWO ORDERS at 18:2x BST ("you need to build 2.0 leaving no feature out and no straying"): (1) COMPLETENESS: docs/plans/igneum-2.0-register.md, one numbered row per checkbox in the plan (the pins, the addendum, the finish line's ten missed pins) with the plan page, the owner lane, the clock, the status (open, in flight, landed, passed with its evidence file) and the pass condition; every row owned by 19:30, none blank; landed through the landing hand; the coverage line to main at 19:30 and every two hours after and on every landing that closes a row; nothing finished while a row is open; (2) NO STRAYING: every lane brief names the register row it closes; work naming no row stops and names a row or drops; a mechanism outside the plan refused unless it closes a row and passes the one acceptance rule; served text follows the wording ladder and the never-published list. The register built by the coordinator at 18:3x on the Mac's clock from the plan's 103 checkboxes: 103 pins, 103 owned, open 35, in flight 34, landed 29, passed 5; on the mirror as ca3-coord-record c1aa45bde, the landing hand landing it (the plan file merged three-way over master so the D5 block is kept under rule 26; the plan file about 18:20, the register about 18:32); confirmed to main at 18:17 with the ten missed pins' owners and clocks: (1) the reference population and cost-per-accepted-unit table (the research lane, IN HAND: reference-population.md at 2db4fe34 on counter-asic-4 for the 21:00 landing, every cell labelled: the plan's population as block 1, the other eleven classes plus the H100 and A100 as block 2; the floor and stock energy, the rate, MSRP / street / used, resale, the two tests at 0.06 / 0.12 / 0.25 per kWh; the cheapest honest owner the 5070 Ti at its knee at 156 / 263 / 493 micro-USD per accepted MH/s-hour, the cheapest entrant the same card at MSRP at 412 / 519 / 749; the RX 7600 owner 2.6x and entrant 1.4x at street, the B580 4x and 1.5x; the H100, A100 and the Mac never enter as entrants; the GDDR7 machine at 3 years and 0.06 between the Blackwell entrant at MSRP and at street and above every owner; owed: the 7600's ADLX grid and dataset rows, the Arc's metered watts, the Ada and Ampere knees; the site serves by 12:00 tomorrow); (2) the formal memory model (the adversary lane, 12:00 tomorrow); (3) the cryptographic review of the template, nonce, work and result binding (the attack seat with the hash lane, docs/analysis/binding-review-2026-10.md by 15:00 tomorrow); (4) the disclosure prize live (the site lane, /prize by 12:00 tomorrow; the terms from the coordinator: a placed or measured adversary beating the served bracket under the one acceptance rule, or a reproduced shortcut on the served harness; no confirmations, no synthesis-only rows, nothing outside the budget or on the excluded list; judged in-house with the finding served whatever the verdict; the amount the founder's line, served only when set); (5) the home-connection penalty (the fleet lane with PC 1 or PC 2 through the relay, a residential Vast box the stand-in until v2.0.0 is on a PC, 15:00 tomorrow); (6) published optimisations, compiler settings and tuning logic (the hash lane, docs/build/tuning.md by 15:00 tomorrow, served under /miner); (7) negative test six's proof side, P22 stage 3 (the enforced-proving lane, 18:00 tomorrow); (8) the proving benchmark with p50 and p99 per stage (the fleet lane, 15:00 tomorrow; the collector running against hub-1's devnet-4 node from block zero); (9) reproducible builds and the signing-key incident procedure (the shipper with the build-server lane, 15:00 tomorrow); (10) the maintenance plan and the committed-funding line (the founder's). THE 2.0.1 QUEUE COMPLETE on release-2.0.0-node at 18:02 BST: 9fc9f42a adds "state" to igneum_getTransactionStatus (absent, included, executed, proven, finalised: the highest reached; "proven" and "locked" computed, no longer hard-wired false) and "paused" with its cause whenever the executor is blocked, re-executing, vetoing a proven record or more than two blocks behind the sink; the finality lane's third test in (a recovery certificate off the certified chain refused, the re-anchor at the recovery lock, a key under dust absent from the bitmap); igneum-exec 67, kaspa-consensus 143; no params, object or digest change; the manifest d5981514, rule v4 bee41b5e, the four states 9fc9f42a: the shipper names 2.0.1's paired cut; the rule v4 harness on bee41b5e's pair on build-2 since 17:58 (four lines of about 15 minutes, the tables into sim/results_v2.md by about 19:15). Lane D's amendment 494fb9810 on master at 18:02 (section 6.9 with the PASS verdict and the owed exact-table line). THE GUEST CRATE LANDING's red at 18:02 and its split: tools/ci/release-manifest-check.mjs keeps site/release-manifest.json's proof ids equal to proving/igneum-prove/elf/manifest.json, and the served page names the ids the running release embeds (v2.0.0: 0x2b1a81cb, 0x474678f3), so landing the re-pinned elf/ tonight would make the served manifest claim ids no running node carries; the split taken and ruled: proving-payment-guest-src 69ddd5112 (the guest sources with the D4 split behind the fixture flag, the exporter flag, the known-failed test; elf/ at the served release's pin, every fixture reproducing its roots with the flag off) runs rule 24's crate gate and lands on master on green, so 2.0.1 cuts from a master that compiles the new guest; the re-pinned elf/ (afd952e89: shard 0x282dcfce, aggregator 0x3fd721e8) rides the node 2.0.1 and miner v2.0.1 paired cut with the served manifest's move to the new ids in one commit by the node lane (or pin-guests.sh re-run on build-1 at cut time, 90 s); the landing hand's manifest edit never made. The explorer's public name ruled: "the Igneum 2.0 devnet" on every served page (never "Devnet 4", never "Devnet 3"), the explorer deriving it from the node's network name with a map, landing by 19:00; the live APIs read the dn4_ tables since 17:01 (network igneum-devnet-4, chain id 4465). The kit on PC 1's 5090 (unlocked, 250 x 2^24): hl-v6-foldrw 140.6 MH/s at 440 W (3.13 µJ), fingerprint 5a6ad122a71a888f; hl-v6-all 70.5 MH/s at 409.1 W (5.80 µJ), fingerprint 59e6708e46f1e87c; both equal the CPU, CUDA pod, Metal and Apple OpenCL readings: THE ALL PACK AT FIVE PLATFORMS, the partner at four; the window halves the hash rate at 7 percent less card power (a window hash twice the work: 128 statements, 32 loads), so per unit of work the card is level with the partner; the 7600's class v5 fingerprint 82b19cbde8557ea5 matched at 15.83 MH/s and v4 892b6d55a7ddcfcb at 15.75, the card quiet; the sizes rows republished (run-ca3-pc1-amd-cardin-20261008T1703, run-ca3-pc1-ds55-7600-20261008T1703). "Layer 8 off" taken by the hash lane with lane D (its fg harness by 12:00) and the adversary lane: a class flag on class-v6 tonight (the window draw forced to win = 0 and off = 0 on every site, the stream still consuming its two draws so the base program's instructions are unchanged, the id carrying it) and the 5090 and 4090 rows at stock and the knee. The research lane's mapping control for the genesis floor (the 4 GiB mask path, 2^30 minus 2^16 words on the multiply-shift, 5.5 GiB again, the 5090 at the lock) exporting on build-2, clock 20:15. The adversary lane's 32-lane 18-family core synthesis row at 18:02: 393,036 cells and six macros, 5.73 pJ per lane-op on the class v4 draw at ASAP7 (5.09 to 7.20), 4.01 at N5, 2.89 at N3, k 0.39 same-node / 0.28 a node ahead at the lock, 13 percent under the 8-lane full core; the bank's cost at 32 lanes 8 percent of energy and 50 percent of cells; with the measured 8-lane placement factor 1.42 about 5.7 pJ at N5 placed (k 0.55 same-node), so the machine ratios move up about a sixth: the GDDR7 board about 1.6x same-node (1.4 to 1.9), 2.0x a node ahead; the stored-half hybrid about 2.1x and 2.6x; per dollar unchanged; the same-node honest bracket 1.5x to 2.1x across the lane-count choice (document 0be29c224); adv-a destroyed at 18:01, adv-f the one rented host left (USD 0.20 an hour), its placed 32-lane row by 21:00 or the morning's. The site lane at 18:01: the tip 58355893 (b45bf6d4's items plus the dataset policy sentence and the section 9 link) in its gate on build-2 since 17:59; the finality wording for the new chain ("not yet active, first lock expected about 23:00 UK" on every page mentioning finality, the badge "Devnet live") on the landing after, by 18:30, since the strip and the explorer would read "paused" before the first lock, which the D5 rule forbids. The five-together case ruled: the record names the 617cb441 run with the gap stated ("proof queues and seed transitions not exercised in the same network as the crossing and the finality attack; owed to the next harness commit, the fast-time lane's morning item"). THE RE-PIN RULING put to main by 19:00 (the node lane's reading, the enforced-proving lane agreeing): the re-pinned guest elf cannot ride node 2.0.1 as a node-only cut: on igneum-devnet-4 verifier_in_consensus is on from block zero and a node pins the ids it embeds (the daemon exits 3 when the embedded keys differ from pinned ids; with devnet-4's ids empty it pins its own), so a 2.0.1 node on the new elf and the 4cdcc488 population would verify different statements, each refusing the other's records, payments and the body rule diverging on one chain: a consensus change needing the next devnet genesis or a key-succession field in the object (a digest move with a minute); the default on silence: node 2.0.1 node-only on 9fc9f42a with the live keys and no manifest change; the re-pinned guest (afd952e89), its ids, the served manifest's proving block and any object setting proving_payment_activation_daa wait for the next genesis or the succession field; the miner v2.0.1 pairs with 9fc9f42a's node; what moves no key lands tonight: proving-payment-guest-src 69ddd5112 (the sources with the split behind a fixture flag no fixture sets, elf/ byte-for-byte the served pin) under rule 24, and proving-payment 930b6322 on the fork while the floor is never; the landing hand's guest landing branch 7f15312aa dropped (a fresh worktree's vendor/ path fact recorded: proving/igneum-prove/core's path dependency igneum-evm-types at ../../vendor/igneum-node-exec is gitignored, so a crate landing from a fresh worktree needs the vendor copy). The register row for negative test six's proof side on enforced-proving 610f07c01, landing. THE REGISTER ON MASTER at 18:13 BST as 2e9093ea (Merge igneum-2.0-register-docs f29cc42a; full gate GREEN 77), docs/plans/igneum-2.0-register.md whole from ca3-coord-record c1aa45bd; the plan file master's copy under rule 26 (the finish-line sections on master at 7f6c9289, 18:06; the branch's copy differed by one blank line). The census-packs record on master as 77f0c4b4 (18:15; the uniform crate on the branch under rule 24), the connected-state amendment 28506b25 as e5d1b03b (18:16); twenty-four research landings. MAIN'S RULING, ahead of 19:00: node 2.0.1 ships node-only on 9fc9f42a with the live keys and no manifest change; miner v2.0.1 pairs with it; the re-pinned guest, its ids and the D4 payment rule wait; the guest sources land tonight under rule 24; no third rebirth; and the plan's own pin becomes a register row: A KEY-SUCCESSION FIELD in the object (program identities, verifier versions and security parameters pinned with a versioned replacement path: an activation height at which nodes switch from the old pinned ids to the new, both verified across the window, designed and tested on the fast-time harness before any devnet carries it), owner the enforced-proving lane with the node lane, the design doc tonight (docs/design/key-succession.md: Params gets a succession field, pinned ids and an activation height with a window; below the height the old pair; across the window a record's proof accepted under either pair and the body rule verifying with whichever key the proof's claimed program id names; from the window's end only the new pair; the payment rule on the same floor; the manifest and the served manifest carrying both pairs with the height; the digest taking the field only once set; never on every network; the daemon refusing to start if it embeds neither pair the object names at its height), the node branch off release-2.0.0-node with the known-failed tests first (the seven refusals on both sides of the height, the switch test, the digest test) and the fast-time case across the height by 18:00 tomorrow; the register row 104. THE FOUNDER AT 18:1x BST: "execute, give it hell; if we need more builders or fleet get them": (1) every register row clocked by builder or pod capacity rather than a dependency pulled forward with capacity: the build-server lane provisions build-5 tonight (the AX102 class, from the hetzner token under ~/.config/igneum/, the mirror, the lease pool, the toolchains, the gate fan-out) and build-6 if the queue at 21:00 still holds a job waiting on cores; the fleet lane adds rented pods for any research lane whose next row waits on a pod, inside the standing USD 3,000 a day ceiling, warm pods preferred; (2) every row with a clock tomorrow afternoon re-clocked to the earliest hour its dependencies allow once the capacity is in, told to main in the 19:30 coverage line as old clock to new; (3) nothing waits on a calendar: a row whose gate is green ships; (4) the no-straying rule stands; the capacity read-back to main (build-5's first green gate and the pod count) by 20:00. The coordinator's capacity asks: the k lane a second 256-core CPU pod to fan the five placements (core8r64g slipped to 19:45 on its CTS timing repair; the five at 21:00); the adversary lane a second host for the 32-lane placement (adv-f restarted at 18:12 on a 30 ns SDC, its unpipelined crossbar path 27 ns); the hash lane a one-shot 5090 and 4090 for the layer-8-off rows tonight rather than 12:00 tomorrow; the fleet lane provisioning on each lane's shape (defaults at 19:30). The adversary lane's layer-8-off chip row at 3a8874fef: with the window layer removed the hottest half serves exactly 50 percent of reads at every program, so the stored-half hybrid on the placed rows reads 1.85x same-node (1.58 to 2.03) and 2.27x a node ahead at USD 3.34 per MH/s, against 1.93x / 2.40x at USD 2.80 on today's mean program (hit 0.581) and 2.09x / 2.65x at USD 1.88 on the p98: the layer's removal costs the hybrid 4 percent of per-joule edge at the mean and 11 at the tail and takes its capex edge from 5.7x to 4.8x of the card's, for one and-or per load on the honest side (the hash lane's 2.30x default line was the synthesised read, the placed read 1.85x); the formal memory model drafted as section 16 ahead of its 12:00 clock. The class v6 kit's PC job scripts fixed at class-v6-kits c98a42c2e (the class v5 one-pack leaves check and the gfx1201 match), the page row at class-v5 960088fb4; the 7600 read running on the hash lane's fixed copy, the Arc read on PC 2 the shipper's repoint (default past 19:00: the morning's). The site lane at 18:1x: the edge serves 3511bbca (70f8c871 with the labels on /evidence, /scorecard with its "Do not substitute" column, the packets, landed at 18:04, its deploy with the build-server lane); the facts page is /evidence ("Igneum facts"); no "Devnet 3" on master's or the edge's litepaper; fcda08ae serves "finality not yet active: the first lock comes when the weight window fills at DAA 7,200" with the live DAA beside it, landing about 18:22. + +THE STANDARD'S REGISTRY APPROVED AND THE FAST ORDER CARRIED (18:2x to 18:5x BST). The founder approved the Test and Acceptance Standard 1.0 as proposed, P13 deferred ("approve as proposed, forget P13"). The registry docs/plans/igneum-2.0-test-registry.json carries the approval block (by, at, word, the per-profile table, the four rules in force: P03 5 percent joules per accepted work and 2 percent throughput for candidate changes; P04 R_E at most 1.5 same-node and one node ahead, today's placed 1.5x to 2.1x bracket a FAIL to work against; P12 matched-tariff median 1.5, p90 1.75, no core cell above 2.0; P02 twelve retail configurations, three unaffiliated operators, seven-day soak), the live fields (run_status, owner_lane, evidence_path, run_id, updated) and an owner lane on every one of the 128 cases (GOV steward; GPU and POW hash; ADV adversary; ROT node; ECO and INC research; EVM and VER reference-apps; ZKP enforced-proving; CAP fleet; FIN finality; OPS build-server; UX shipper; COM and LEAD main); 63 cases RUNNING on tonight's evidence records, 64 NOT RUN, COM-07 DEFERRED. The register gained its Cases column and the standard's pass criteria. The landing hand had landed the PROPOSED copy first (b9af76b9, 815b27e4 with the PDF and text); the fifty-sixth landing's gate went green but master moved under it and the merge never ran; the record branch was rebuilt on master (df3604c74, the registry replacement named intentional under rule 26, the 104 rows kept) and sent through the gate at 18:42. Main's ruling on P03 and the dataset: P03's budget is per mandatory GPU cell against the paired tuned baseline, for production candidate changes; the genesis dataset size is the baseline being frozen, so P03 does not score it; P06, D3 and D4 score sizes by adversary burden against commodity burden. The research lane's curve on PC 1's 5090 against the 1 GiB control: 2 GiB about +1 percent at stock and +4 at the lock (paired read by 19:50), no exclusion, SRAM ticket USD 250, one reticle; 4 GiB +0.7 at stock and +11.7 at the lock, no card excluded by memory (the RX 7600 -2.6 percent of rate; the 12 GB tier mines and proves together at about 12.0 of 12.3 GB), USD 500, two reticles; 5.5 GiB +4.3 at stock and +13.4 at the lock, the 4060 and RX 7600 hold it but the 12 GB tier loses mine-and-prove co-residence (13.6 GB together on the 3060), USD 690, three reticles; the pure DRAM board pays nothing at any size. The recommendation 4 GiB (the largest size inside both constraints; twice 2 GiB's ticket for +11.7 percent of a locked 5090's energy, a baseline cost and not a P03 cost); the site serves the curve PROPOSED; the founder decides at 20:00, default 4 GiB. Key succession on the node branch: key-succession-node 291ee6ae rebased on 417c4a57, green on build-2 at 18:40 (igneum-exec 74, kaspa-consensus 141, kaspa-consensus-core 175); the main side key-succession 4f5dab9b5; the fast-time case across the height running from 18:40 with one stated limit (the harness embeds one pair until the node lane's first pin into prior/). The shipper moved the paired cut to tonight on main's ship-on-green order: node 2.0.1 = 417c4a57 heals the fleet by the one-box form first, miner v2.0.1 = release-2.0.1 2ea7b43f after through the full gate set and the canary (the Mac entry built on the Mac under the one-at-a-time exception, the mini off the network), HiveOS and Windows after; v2.0.2 tomorrow with its own clocks (explicit update acceptance, the 16 GB time-share copy, the apply helper stopping the old node by pid, the Mac signing pin, the guest elf re-pin afd952e89 unless the node lane lands it first); readiness clock to main by 20:00. The fleet at 18:40: ten TAS pods rented and armed (P01 on a 5090, a 4090 and a 3090; the P02 cohort on a 3060 12 GB, 4070 12 GB, 4070 Ti 12 GB, 4060 8 GB, 3070 8 GB, 2080 Ti and 1080 Ti), the hash lane's two one-shots and the adversary's adv-g (EPYC 7B13, 256 threads); AMD retail and Intel Arc not rentable tonight (PC 1, the mini and the Macs carry those rows); the day near USD 62/h with the TAS pods at 2.3/h, the ceiling not binding; 27 miner keys on hub-1's chain in ten minutes (12 at 18:06), the IBD state-stream class cured by cold restarts on 35 boxes. The P02 cohort's default: the 1p5x and ca4 row shapes on all ten pods at 20:00 unless the hash lane names the kit lines first. The pool seat (a3832b1c3b274b310) owes the node lane its wire shape by 23:00; the reference-apps, pool, shipper and adversary lanes were told their cases, the write-back form and the start-tonight order at 18:4x (defaults recorded if silent by 19:30). +BUILD-5 IN THE POOL (18:44 BST). igneum-build-5 = build@91.98.220.77, Hetzner Cloud ccx53 (32 dedicated vCPU, 122 GB, 563 GB, fsn1, server 169417035, hourly; not a Robot AX102, the Mac holding only a Cloud token), host file ~/.config/igneum/build-server-5 at 18:32; first gate GREEN at 18:44:14 in 229 s on master b15bde12 (cargo check, igneum-pow suites 136 passed, 0 failed, 8 ignored) under lease 82cc0564 (pool cores 8..31, class release, 24 of 24 held, waited 0 s); toolchain at the pins; slots 2; the CI runner registration owed to the steward by 19:15. The steward's pairing read on key-succession-node 291ee6ae: its cells died in five seconds over the cut-tip parent because the fork carries elf/prior (the prior verifying keys, PRIOR_*_VK_BYTES) that only the parent branches key-succession 4f5dab9b and key-succession-pin carry; a pairing fault, not the sha; re-run over 4f5dab9b with the verdict by 19:03; any roll of 291ee6ae builds its node artefact from key-succession's parent, never the cut tip's. The pool seat's clocks (18:4x): wire shape 21:00 (spec 09 sections 9.4.1, 9.5, 9.8, vote_key_hash on job and share, the refusal codes, protocol.rs beside it), pool-2.0 crate 21:30, vote-key commitment in code 23:00, share sidechain object 23:30 (dependency pool-tags-node 7455b8d5's codec and switch), UX-05 00:30, UX-04 01:30 (dependency a node binary with the split codec, two rented boxes). The shipper's UX clocks: UX-01 both PCs on the Windows 2.0.0 entry (live 18:44) by 19:10; the Mac fresh install on v2.0.1 by 22:00; the update over a running older app on every platform by 21:30; the Cards tab and first-block card on the canary by 21:30; reproducible build hive tarball build-2 against build-1 by 23:00, the Mac DMG on the mini by 23:30; the case ids corrected against the registry's titles (UX-04 and UX-05 the pool seat's, UX-06 the shipper's on the pool seat's evidence, UX-01 the update-return lane's). The enforced-proving lane stopped its registry landing by pid at 18:44 so nothing lands on the superseded copy; the P22 stages ride only on a key succession (both program ids change) and say so in a dependency field. +THE REGISTRY ON MASTER AND ECO-05's FAIL (18:50 BST). The approved registry landed as the fifty-seventh landing: master 6db270e8 (commit 50ff1611f; build-3's mirror did not take it, down since 16:40). ECO-05, the standard's P12 sweep, ran on a register frozen before any result (lane 3, 18:43, ad9eeb99 on counter-asic-4) and FAILED the envelope: under the frozen two-vendor rule one of sixteen revenue-tariff worlds is sustainable (10R at USD 0.03 per kWh), the measured AMD and Intel cards (9070 XT 7.9 microjoules at its knee, RX 7600 8.1 at stock, Arc B580 10.4 with estimated watts) costing 4x to 6x a Blackwell card per joule with no positive new-entry economics at list price; in the one sustainable world no specialist sits inside the envelope against the cohort (the GDDR7 machine's best core cell 1.46 to 1.70, cohort median 2.9 to 3.2; the hybrid 3.9 to 5.1; the die 5.3 to 9.8; the p90 failing everywhere on the dearest entrants at 9x to 50x). Nothing weakened; the coexistence model's seven-condition reading stands as the operating reading; what moves it is the hash's energy on AMD and Intel cards. Three defaults to main for 19:30: the served text carries the FAIL beside the operating reading (the registry row RUN: FAIL, the facts page citing it); the AMD and Intel energy a named lane tonight on the hash lane with the Arc hand (9070 XT and RX 7600 kernels and ADLX points on PC 1, the B580's metered watts and kernel on PC 2, first rows by 23:30, the PCs' availability the dependency); lane 3's second explorer read of R at 23:00. build-5 is a Hetzner Cloud ccx53, not a Robot AX102 (the Mac holds a Cloud token only; Robot 401; build-1 to 4 outside that project); its CI runner cannot register under the suspension (a GitHub registration token), so it carries gate, lease and matrix fan-out work; build-6 lands the same way; AX102s need Robot credentials from the founder. The reference-apps lane's first runs on devnet-4 at 18:45: EVM-02 to EVM-06 PASS (ra-20261008T1744-evm, 22 rows, /compatibility), VER-03, 04, 05, 06 and 08 PASS (ra-20261008T1746-ver), VER-01 and VER-02 FAIL by design and disclosed (the voter table as a node-supplied trust anchor, closing with a header commitment on the node lane; the client verifying no SP1 proof, closing with the permitted verifier in the client on the enforced-proving lane); re-runs at devnet-4's first lock (about 19:05); EVM-01, EVM-07 and VER-07 tomorrow with their dependencies named (the F0 pin, the workload W and a sender fleet, the wallet lane). The steward's pairing finding on key-succession-node 291ee6ae: over the key-succession parent 4f5dab9b the kaspa-pow build refuses by rule 19 (the parent's igneum-pow is the class-v6 tree a65e4c5a, the fork's freeze list names only the class v5 freeze cbc5bd0a); the read taken over the parent with 7d82b71e's igneum-pow and elf/prior kept, verdict by 19:03; any roll tonight links the freeze tree until the freeze list says otherwise. The node lane: pool-tags-node merged as 02312769 on release-2.0.0-node; the pool seat's binary at 23:30 with the 417c4a57 successor; build-1's stale 60x file (missing the four succession keys and the two rule v4 keys) replaced, 88 keys on both boxes; 417c4a57's five suites green 18:23 to 18:28 (143/180/30/38/19), its pair about 19:00 after a setsid fault on macOS (restarted 18:42); a rule v4 harness fault not in any live path, the pause-only variant staying paused for ever with 100 percent of the anchored table signing, fixed as acd9d067 (two thirds of the anchored table locks at any time; the majority test only past the window with the switch on; the recovery stamp gated on the switch), the recovery run as designed (side A 51.26 percent recovered at index 11, side B paused at 48.73, 0 conflicts, 0 disagreement; the harness's split50 pass line assumes the pause outcome). The hash lane: docs/build/tuning.md on master at fa1cca3db; its clocks were an hour ahead of the Mac's and were corrected; the P02 cohort additions (the class v6 packs with the fingerprint gate per cell, the sizes packs on the 8 and 12 GB cards); the fuzz tools (10,000 mutations per parser) on box 2 with a 20:30 verdict; the P01 vectors generating. +MAIN'S THREE RULINGS (18:5x BST): ECO-05 serves as FAIL now in the standard's words on /acceptance and the economics page, naming the one passing world (10R at USD 0.03 per kWh at the corrected R of USD 31.65 M a year from ETC's era-6 reward 1.6384 ETC, lane 3's second explorer read at 18:49 on the Blockscout stats endpoint and block 25,497,000's record; the first page's 2.56 stale) and the failure regions and what moves it (the specialist ticket, the honest side's efficiency, the dataset floor), nothing softened; the AMD and Intel energy lane is a GPU-suite row under GPU-03's cohort on the hash lane with the fleet lane's rented AMD cards and PC 1's RX 7600 and the Arc tonight, 23:30; the genesis size is the founder's word at 20:00, default 4 GiB, the curve as served. The cube re-ran at the corrected R on both proving efficiencies with the verdict unchanged (0 of 54 cells per specialist on all three lines; db424d20 on counter-asic-4). +A SECOND KILL BY NAME ON THE MAC (18:57 BST), THE REVIEW ROWS AND THE FINALITY AMENDMENT. The node lane, stopping its three Mac-side build chains for the shipper's version bump, killed every process matching "build-remote.sh --box" on the Mac, a kill by name against the standing rule (CLAUDE.md since 26a3cbe6), and took the pool seat's igneum-pool check on box 2, the hash lane's export and three hash-bound runs on the edc4fa84 epoch and its fuzz_parsers run on box 2, the enforced-proving lane's two prove-core and prove-host test runs on box 2 and the steward's 291ee6ae verdict runs on build-4 (the kaspa-p2p-flows run survived); every owner re-runs from its own log; the steward's verdict default moved to 19:25; the node lane's chains restart on the bumped sha; the node lane states its kills go by a pid file from now. The class stands as written on 8 October 12:5x: a lane's own convenience is never a reason; ad-hoc shell lines included. Main dispatched nine register rows (105 to 113) for an external source review of the mining algorithm (docs/analysis/review-2026-10-08/, landing; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so): findings A01 to A09 under the POW suite's cases as they fit, the review's harness the cross-check evidence, owners the hash lane (A02, A04, A06, A07, A08, A09 by 22:30), the census hand (A03 by 22:30), the attack seat (A05 by 23:00), the node lane carrying each verdict into the 23:30 freeze as fixed by construction, not applicable, or known open with a clock; RUNNING tonight, nothing PASS without the native test. The finality lane's amendment finality-boundary 29c8e86d8 (one clause: the two-thirds anchored test at any time, the majority test only past the window with the recovery on; the even split's jitter fact; the harness pass line per variant) given the word to land at 18:5x. Lane 3's registry write-back on class-v6-floor-sram 78a06c33 (ECO-05 FAIL, ECO-08 RUNNING, master's copy with two rows' live fields changed) lands through the research lane's 21:00 landing. The register's coverage at 19:0x: 113 pins, 113 owned; cases under the standard: 10 PASS (EVM-02 to 06; VER-03, 04, 05, 06, 08), ECO-05 FAIL, VER-01 and VER-02 FAIL by design, 62 RUNNING, 52 NOT RUN, 1 DEFERRED. + +A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) | ### AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule diff --git a/docs/plans/igneum-2.0-register.md b/docs/plans/igneum-2.0-register.md index 2bd117b93..7af372fbd 100644 --- a/docs/plans/igneum-2.0-register.md +++ b/docs/plans/igneum-2.0-register.md @@ -109,6 +109,16 @@ Built 8 October 2026, 18:3x BST (the founder's order: no feature left out, no st | 103 | Pins the finish line missed (checked against the 37 pages, 18:1x BST) (p. 8 to 24) | The funded maintenance plan and the committed-funding line (p. 24). Owner: the founder. | main / the founder | the founder's | open | | COM-07 (P13, DEFERRED) | | 104 | Architecture and product (review 2) (p. 15 to 17) | Key succession: a succession field in the object (the pinned program ids and verifier versions with an activation height and a window; below the height the old pair, across the window either pair, from its end the new pair; the payment rule on the same floor; the manifest carrying both pairs with the height; never on every network; the daemon refusing to start if it embeds neither pair the object names), designed and tested on the fast-time harness before any devnet carries it, so a re-pin is a scheduled transition and never a genesis (main's order, 18:1x BST) | enforced-proving lane (a6e8f84588b809d62) with the node lane (a283f5f0d364ceef0) | the design doc tonight; the node branch with its known-failed tests and the fast-time case by 18:00 tomorrow | in flight: docs/design/key-succession.md tonight; the re-pinned guest (afd952e89, shard 0x282dcfce, aggregator 0x3fd721e8) waits on it | docs/design/key-succession.md | ZKP-02, EVM-08 | -## Coverage at 18:3x BST: 104 pins, 104 owned, open 30, in flight 35, landed 34, passed 5. Cases: 128 in 16 suites, every case owned; run under the standard: 0 passed, 63 RUNNING (team-run tonight with evidence, not yet under the standard's procedure), 64 NOT RUN, 1 DEFERRED (P13). +| 105 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A01 "The supplied snapshot is not the planned v6" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | node lane (a283f5f0d364ceef0); the node lane carries the verdict into the 23:30 freeze | carried into the 23:30 freeze by the node lane | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-01 (the review's harness as cross-check; the native test decides) | +| 106 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A02 "Accepted short programs need not connect all 32 lanes" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | hash lane (a690540514aa453d7); the node lane carries the verdict into the 23:30 freeze | 22:30 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-02, POW-03 (the review's harness as cross-check; the native test decides) | +| 107 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A03 "Per-hash address diversity can conceal per-site concentration" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | census lane (the hash lane's harness hand); the node lane carries the verdict into the 23:30 freeze | 22:30 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-03 (the review's harness as cross-check; the native test decides) | +| 108 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A04 "The acceptance interpreter omits the shadow that runtime executes" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | hash lane (a690540514aa453d7); the node lane carries the verdict into the 23:30 freeze | 22:30 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-02 (the review's harness as cross-check; the native test decides) | +| 109 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A05 "Header binding and final digest deserve independent cryptographic review" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | attack seat (a3832b1c3b274b310); the node lane carries the verdict into the 23:30 freeze | 23:00 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-05, POW-06 (the review's harness as cross-check; the native test decides) | +| 110 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A06 "Different V3 eras can have the same program_id" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | hash lane (a690540514aa453d7); the node lane carries the verdict into the 23:30 freeze | 22:30 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-01 (the review's harness as cross-check; the native test decides) | +| 111 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A07 "CUDA dispatch needs explicit canonical-group constraints" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | hash lane (a690540514aa453d7); the node lane carries the verdict into the 23:30 freeze | 22:30 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-02 (the review's harness as cross-check; the native test decides) | +| 112 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A08 "An operation described as bijective is not always bijective" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | hash lane (a690540514aa453d7); the node lane carries the verdict into the 23:30 freeze | 22:30 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-02 (the review's harness as cross-check; the native test decides) | +| 113 | External source review of the mining algorithm (docs/analysis/review-2026-10-08/, on master at 0ae450bd; it examined the Mac checkout's older V2 to V4 crate, not class v6, and says so) | Finding A09 "A naive stronger rejection test can exhaust all candidates" (on master at 0ae450bd, the harness run on build-2 to its end with every anchor it asserts agreeing with the tree, the v5 and v6 vectors outside its model); the review's harness is the cross-check evidence; the verdict reads fixed by construction, not applicable, or known open with a clock, and nothing reads PASS without the native test | hash lane (a690540514aa453d7); the node lane carries the verdict into the 23:30 freeze | 22:30 | RUNNING tonight (main's dispatch, 18:5x BST) | docs/analysis/review-2026-10-08/ | POW-04 (the review's harness as cross-check; the native test decides) | + +## Coverage at 19:0x BST: 113 pins (104 of the plan, 9 of the review), 113 owned, open 30, in flight 44, landed 34, passed 5. Cases: 128 in 16 suites, every case owned; run under the standard: EVM-02 to 06 and VER-03, 04, 05, 06, 08 PASS (10), ECO-05 FAIL, VER-01 and VER-02 FAIL by design and disclosed, 62 RUNNING, 52 NOT RUN, 1 DEFERRED (P13). The pass criteria are the Test and Acceptance Standard's (docs/plans/igneum-2.0-test-standard.pdf, 128 cases, approved as proposed by the founder on 8 October 2026 with P13 deferred; the live registry docs/plans/igneum-2.0-test-registry.json): a row reads passed only when its cases pass under the standard. The plan's own conditions, per section: D1 an independent operator reproduces the baseline from the served kit alone; D2 the candidate improves against re-optimised adversaries within the preset limits, else published as a failure; D3 the best supported advantage inside the chosen envelope with uncertainty published; D4 the model names credible conditions for sustained commodity participation and where it fails; D5 specified behaviour with no emergency change and no privileged intervention; the launch requirements live; the claim ladder earned rung by rung. diff --git a/docs/plans/igneum-2.0-test-registry.json b/docs/plans/igneum-2.0-test-registry.json index 05e166efd..f1e3737cc 100644 --- a/docs/plans/igneum-2.0-test-registry.json +++ b/docs/plans/igneum-2.0-test-registry.json @@ -2,7 +2,7 @@ "title": "IGNEUM 2.0 - Test and Acceptance Standard", "version": "1.0", "date": "2026-10-08", - "status": "APPROVED 8 October 2026 (the founder, 18:2x BST): \"approve as proposed in the tests, forget P13 for now\"; the test design stands as PROPOSED, NOT EXECUTED until a case runs under it", + "status": "APPROVED 8 October 2026 (the founder, 18:2x UK): \"approve as proposed in the tests, forget P13 for now\"; the test design stands as PROPOSED, NOT EXECUTED until a case runs under it", "basis": "IGNEUM_2.0_Plan.pdf, 37 pages, 8 October 2026", "suites": [ { @@ -52,7 +52,7 @@ "run_status": "RUNNING", "evidence_path": "docs/plans/counter-asic-3-status.md; packaging/pow-freeze.txt", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the D1 freeze tonight (the five digests, packaging/pow-freeze.txt and d1-freeze.txt; the generator on master 9ba4e0e43, fingerprint a65e4c5a)", "run_by": "node lane (a283f5f0d364ceef0)", @@ -91,9 +91,9 @@ "run_status": "RUNNING", "evidence_path": "docs/plans/igneum-2.0-test-registry.json", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { - "what_was_run": "the profiles approved as proposed by the founder at 18:2x BST before any confirmatory run; P13 deferred", + "what_was_run": "the profiles approved as proposed by the founder at 18:2x UK before any confirmatory run; P13 deferred", "run_by": "CI steward (a2ecfa95d3206016c)", "under_the_standard": "no: team-run before the standard's procedure; the status is RUNNING until the case is re-run under its steps with the profile's numbers and an independent run where the profile asks one", "pass_or_fail_today": "not judged under the standard yet" @@ -130,7 +130,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "GOV-04", @@ -163,7 +163,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "GOV-05", @@ -196,7 +196,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "GOV-06", @@ -229,7 +229,7 @@ "run_status": "RUNNING", "evidence_path": "docs/plans/igneum-2.0.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the excluded-knob list and the one acceptance rule (the plan, the freeze text)", "run_by": "CI steward (a2ecfa95d3206016c)", @@ -268,7 +268,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "GOV-08", @@ -301,7 +301,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -352,7 +352,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "GPU-02", @@ -385,7 +385,7 @@ "run_status": "RUNNING", "evidence_path": "docs/plans/counter-asic-3-status.md; docs/analysis/class-v6/floor/sm-sparse.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the 5090 knee 1,300 MHz (134.6 MH/s at 223 W against 305 W stock), the 5080 1,100 MHz (71.2 at 146.6 W), the 9070 XT both floors (149 W at 18.96 MH/s); team-measured on the project rigs", "run_by": "hash lane (a690540514aa453d7)", @@ -424,7 +424,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/class-v6-rotating-family.md 10.0e", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the 64-register window measured on a rented 5090 and 4090: at most 5 percent per load, no spill, no rate per unit of work; the full-chain form hl-reg64c", "run_by": "hash lane (a690540514aa453d7)", @@ -463,7 +463,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/floor/sm-sparse.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the memory-clock ladder at the lock (floor lane 1, b1b8d833)", "run_by": "hash lane (a690540514aa453d7)", @@ -502,7 +502,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/coexist-rows.md; docs/design/class-v6-rotating-family.md 10.0u", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the 5.5 GiB rows: the 5090 +14.3 percent energy per hash at the lock (+4.8 at stock), the RX 7600 under 3 percent of rate; the 3060 and 4060 coexist rows", "run_by": "hash lane (a690540514aa453d7)", @@ -541,7 +541,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "GPU-07", @@ -574,7 +574,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/floor/sm-sparse.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the 5090 lock pass, 66 minutes at 1,300 MHz with the four-minute reserve (floor lane 1)", "run_by": "hash lane (a690540514aa453d7)", @@ -613,7 +613,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -660,7 +660,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/class-v5-stored-state.md section 0", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the class v6 all pack equal on six platforms (CPU, CUDA 4090, RTX 5090, Metal, Apple OpenCL, RX 7600; the Arc open), the class v5 kit on six; team-run, the 10^6-vector campaign not run", "run_by": "hash lane (a690540514aa453d7)", @@ -697,7 +697,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/census-packs.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the index fold: the known-failed set p4, p8, p10, p15, p34, p212, p225 under 3.5 sigma with the fold; the census sheet fold, rw, foldrw, win, all PASS", "run_by": "hash lane (a690540514aa453d7)", @@ -734,7 +734,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/connected-state.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the connected-state class KILLED (1.10x against the 1.25x gate; live state costs a clock-gated file nothing)", "run_by": "adversary lane (a1a9876a88f5a72fc)", @@ -771,7 +771,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/connected-state.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the same experiment, D2(a) closed", "run_by": "adversary lane (a1a9876a88f5a72fc)", @@ -808,7 +808,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/binding-review-2026-10.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the binding review: twelve reuse paths, none below the honest cost; five open questions B1 to B5", "run_by": "pool design seat (a3832b1c3b274b310)", @@ -845,7 +845,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "POW-07", @@ -876,7 +876,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/mixed-fp32.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "mixed FP32 KILLED (+15 to +26 percent card energy; determinism proved CPU against CUDA)", "run_by": "hash lane (a690540514aa453d7)", @@ -913,7 +913,7 @@ "run_status": "RUNNING", "evidence_path": "docs/plans/igneum-2.0.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the rejected knobs kept as regression controls (long programs, select trees, W = 8 and 16, SM count, memory clock, wider reads, sealed classes, random epoch lengths, per-tier scoring, VRF draws)", "run_by": "hash lane (a690540514aa453d7)", @@ -968,7 +968,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the 18-family programmable core placed and routed (9.36 pJ per lane-op, k 0.64 same-node)", "run_by": "adversary lane (a1a9876a88f5a72fc)", @@ -1006,7 +1006,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "D2(b): the stored-half hybrid, memory sharing, recomputation priced (the placed hybrid 1.93x same-node at the mean hit)", "run_by": "adversary lane (a1a9876a88f5a72fc)", @@ -1044,7 +1044,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "data-local execution moves nothing (2,112 bits of live state against an 80-bit read)", "run_by": "adversary lane (a1a9876a88f5a72fc)", @@ -1082,7 +1082,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "selective participation 9 percent spread across 2,000 era draws", "run_by": "adversary lane (a1a9876a88f5a72fc)", @@ -1120,7 +1120,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md; docs/analysis/class-v6/floor/shadow-k.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the complete GDDR7 machine 1.5x same-node, 1.8x a node ahead at the placed energy; the honest same-node bracket 1.5x to 2.1x: FAIL against P04 at R_E 1.5, served as such", "run_by": "k lane (a3c9601a6d4686fe1)", @@ -1158,7 +1158,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/floor/shadow-k.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the node column: same-node and a node ahead kept separate (k 0.78 / 0.56 / 0.40 at N5 / N3 / N2)", "run_by": "k lane (a3c9601a6d4686fe1)", @@ -1196,7 +1196,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/multi-family-adversary.md section 14", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the transition matrix: no row loses competitiveness, the three-year life holds, zero obsolescence credit", "run_by": "adversary lane (a1a9876a88f5a72fc)", @@ -1234,7 +1234,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -1281,7 +1281,7 @@ "run_status": "RUNNING", "evidence_path": "v5-fasttime 92bf6a7f", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the fast-time crossings PASS on 4cdcc488 (17:29:58) and 617cb441 (17:30:44) with the cold restart", "run_by": "fast-time lane (a8be71a0db962911c)", @@ -1318,7 +1318,7 @@ "run_status": "RUNNING", "evidence_path": "v5-fasttime 92bf6a7f", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the class v6 object crossing at its floor on 617cb441", "run_by": "fast-time lane (a8be71a0db962911c)", @@ -1355,7 +1355,7 @@ "run_status": "RUNNING", "evidence_path": "docs/plans/igneum-2.0.md D5", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the bring-forward mechanism specified in the D5 block", "run_by": "node lane (a283f5f0d364ceef0)", @@ -1392,7 +1392,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "ROT-05", @@ -1423,7 +1423,7 @@ "run_status": "RUNNING", "evidence_path": "docs/spec/finality-guarantees.md; sim/results_v2.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "rule v4 on release-2.0.0-node bee41b5e (the anchored table, the majority-continuity recovery), the simulator rows", "run_by": "finality lane (aca0f5ed924a2a99b)", @@ -1460,7 +1460,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/class-v6-rotating-family.md 10.0u", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the dataset schedule scored per step (10.0u); the floor decision the founder's at 20:00", "run_by": "hash lane (a690540514aa453d7)", @@ -1497,7 +1497,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/family-gate.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the family gate's coverage (38,000 eras) and the rotation prototype paused as the no-rescue control", "run_by": "lane D family gate (a07a99a3788566af2)", @@ -1534,7 +1534,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -1583,7 +1583,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/reference-population.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the cost per accepted unit in reference-population.md", "run_by": "research lane (ad6a2bd47d4a46105)", @@ -1621,7 +1621,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/reference-population.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the existing-owner and new-entrant tests per class at three electricity prices", "run_by": "research lane (ad6a2bd47d4a46105)", @@ -1659,7 +1659,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/coexistence-model.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the sunk-development case first in the coexistence model", "run_by": "research lane (ad6a2bd47d4a46105)", @@ -1697,7 +1697,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/coexistence-model.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "miners react through a per-class supply curve (the second cut, 21:00)", "run_by": "research lane (ad6a2bd47d4a46105)", @@ -1735,7 +1735,7 @@ "run_status": "RUNNING", "evidence_path": "docs/analysis/class-v6/coexistence-model.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the success, contraction and cheap-electricity paths in the model", "run_by": "research lane (ad6a2bd47d4a46105)", @@ -1773,7 +1773,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/proving-payment.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the proving-payment resolution (the 90/10 user-funded payment)", "run_by": "research lane (ad6a2bd47d4a46105)", @@ -1811,7 +1811,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/class-v6-rotating-family.md 10.0u", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the dataset schedule's commodity burden (10.0u)", "run_by": "research lane (ad6a2bd47d4a46105)", @@ -1849,7 +1849,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -1900,7 +1900,7 @@ "run_status": "RUNNING", "evidence_path": "docs/build/compatibility.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "/compatibility 20 of 20 rows PASSED on igneum-devnet-4", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -1939,7 +1939,7 @@ "run_status": "RUNNING", "evidence_path": "docs/build/compatibility.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the replay and chain-id rows in /compatibility", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -1978,7 +1978,7 @@ "run_status": "RUNNING", "evidence_path": "docs/build/compatibility.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the two-dimensional fee rows (the quote folds proving gas; gasUsed 21,000 against a quote of 59,650 for a transfer)", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -2017,7 +2017,7 @@ "run_status": "RUNNING", "evidence_path": "docs/build/compatibility.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the block-context and prevrandao rows", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -2056,7 +2056,7 @@ "run_status": "RUNNING", "evidence_path": "docs/build/compatibility.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the ERC-20, counter and block-context contracts", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -2095,7 +2095,7 @@ "run_status": "RUNNING", "evidence_path": "docs/build/compatibility.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the wallet fee estimation, indexing and receipt rows", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -2134,7 +2134,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "EVM-08", @@ -2167,7 +2167,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/key-succession.md; key-succession-node 291ee6ae, build-2 18:40 UK: igneum-exec 74, kaspa-consensus 141, kaspa-consensus-core 175 passed", "run_id": "key-succession-2026-10-08-1840", - "updated": "2026-10-08 18:5x BST", + "updated": "2026-10-08 18:5x UK", "evidence_record": { "what_was_run": "the controlled verifier upgrade as a scheduled transition: key succession (the object names the prior pair, the next pair, a height and a window; both pairs accepted in the window; the node embeds both; the daemon refuses to start without both; the digest moves once set), tests as ZKP-02's succession_* set; the mixed-client crossing with proofs from both versions and the failed-distribution step NOT RUN until the first pin into elf/prior/ and the fast-time case with a real next-pair proof", "run_by": "enforced-proving lane (a6e8f84588b809d62)", @@ -2225,7 +2225,7 @@ "run_status": "RUNNING", "evidence_path": "docs/spec/proving-enforcement.md sections 3, 3a and 6; build-2 suites at 16:15 UK (igneum-exec 64, kaspa-consensus 138, kaspa-consensus-core 171 passed; release-2.0.0-node dd84ed6a and f6cd2f00); build-2:/home/build/enforced-fixtures/floor-240-expect-refuse.json", "run_id": "enforced-proving-2026-10-08-1615", - "updated": "2026-10-08 18:5x BST", + "updated": "2026-10-08 18:5x UK", "evidence_record": { "what_was_run": "the seven refusals as named tests: consensus proving_enforcement_tests::enforced_* (no proof: never inserted; wrong proof and another program id: the block invalid; the honest verified record accepted; the finding with the switch off; the floor as a boundary) and executor proving::tests::enforced_* (no payment without a verified proof and the honest record paid once; replay; wrong network id; altered payout; duplicate of a paid record; the v0 shape below the floor; the verdict source); the fast-time crossing PASS at 17:22 UK (a modified producer's five shapes carried, paid below the floor, refused and unpaid at it)", "run_by": "enforced-proving lane (a6e8f84588b809d62)", @@ -2264,7 +2264,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/key-succession.md (master 68ab025c1); key-succession-node 291ee6ae on 417c4a57, build-2 18:40 UK: igneum-exec 74, kaspa-consensus 141, kaspa-consensus-core 175 passed, kaspad checks; the fast-time case across the height on the one-pair build started 18:40 UK", "run_id": "key-succession-2026-10-08-1840", - "updated": "2026-10-08 18:5x BST", + "updated": "2026-10-08 18:5x UK", "evidence_record": { "what_was_run": "the pinned-id refusal on a real proof (nativeverify::tests::a_real_proof_verifies_and_a_wrong_statement_is_refused: the aggregator key refused with 'pinned id'; the_embedded_keys_match_the_manifest) and the daemon's start refusal (exit 3 when the embedded keys are not the object's pinned ids); key succession as the authorised boundary transition: KeySuccession::epoch, succession_accepted_ids_follow_the_epoch, succession_a_verdict_under_a_pair_counts_only_where_that_pair_is_accepted, succession_the_seven_refusals_hold_on_both_sides_of_the_height, succession_a_binary_embedding_one_pair_refuses_to_start_under_a_succession_it_cannot_serve, verify_kind_refuses_a_pair_the_epoch_does_not_accept_before_verifying (on the real prior-pair proof); the downgrade step (an old node path) and the fast-time crossing with a real next-pair proof NOT RUN until the node lane's first pin into elf/prior/", "run_by": "enforced-proving lane (a6e8f84588b809d62)", @@ -2304,7 +2304,7 @@ "run_status": "RUNNING", "evidence_path": "docs/spec/proving-enforcement.md section 3a row 3; build-2 16:15 UK igneum-exec 64 passed", "run_id": "enforced-proving-2026-10-08-1615", - "updated": "2026-10-08 18:5x BST", + "updated": "2026-10-08 18:5x UK", "evidence_record": { "what_was_run": "enforced_a_record_signed_for_another_network_pays_nothing (the chain binding), enforced_a_replayed_record_pays_nothing_the_second_time, assignment_follows_the_window_and_records_check_against_native_execution (a wrong block, a wrong shard, a stale record outside the window, a wrong statement); the epoch binds through the sortition's epoch seed and the chain block in the statement; the fork and replayed-sync steps NOT RUN", "run_by": "enforced-proving lane (a6e8f84588b809d62)", @@ -2343,7 +2343,7 @@ "run_status": "RUNNING", "evidence_path": "docs/spec/proving-enforcement.md section 3a rows 4 and 6 and section 7; proving-payment 421bb852, build-2 17:10 UK igneum-exec 67 passed", "run_id": "enforced-proving-2026-10-08-1710", - "updated": "2026-10-08 18:5x BST", + "updated": "2026-10-08 18:5x UK", "evidence_record": { "what_was_run": "enforced_an_altered_payout_address_pays_nothing (altered after signing: the signature; re-signed: the statement binds the payout) and enforced_a_statement_over_altered_rewards_or_payouts_is_vetoed_native_derivation_is_the_check (a statement whose roots came from execution over other rewards or payouts pays nothing, whatever proof stands behind it: the native veto, every node's own derivation, team-tested); the proved derivation PENDING", "run_by": "enforced-proving lane (a6e8f84588b809d62)", @@ -2383,7 +2383,7 @@ "run_status": "RUNNING", "evidence_path": "docs/spec/proving-enforcement.md section 3a row 5; build-2 16:15 UK igneum-exec 64 passed", "run_id": "enforced-proving-2026-10-08-1615", - "updated": "2026-10-08 18:5x BST", + "updated": "2026-10-08 18:5x UK", "evidence_record": { "what_was_run": "enforced_a_duplicate_of_a_paid_record_by_another_key_pays_nothing and the honest record paid once in enforced_an_unverified_proof_pays_nothing_and_the_verified_honest_record_pays_once; the simultaneous-duplicate, reordered-receipt and crash-recover steps NOT RUN", "run_by": "enforced-proving lane (a6e8f84588b809d62)", @@ -2422,7 +2422,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "ZKP-07", @@ -2455,7 +2455,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "ZKP-08", @@ -2488,7 +2488,7 @@ "run_status": "RUNNING", "evidence_path": "docs/spec/proving-enforcement.md sections 1, 3a and 7; build-2:/home/build/enforced-fixtures/floor-240-expect-refuse.json", "run_id": "enforced-proving-2026-10-08-1722", - "updated": "2026-10-08 18:5x BST", + "updated": "2026-10-08 18:5x UK", "evidence_record": { "what_was_run": "the body rule and the payment rule read one floor (Params::proof_rule_active_from and ProvingConfig::verified_payout_from): the fast-time case's modified producer with its body rule off still pays nothing on honest nodes (PASS 17:22 UK); the replacement-prover and the ordering/voting authority steps NOT RUN; the proof side of the derivation PENDING, register row 'Negative test six, proof side: derivation inside the aggregator guest (P22 stage 3)'", "run_by": "enforced-proving lane (a6e8f84588b809d62)", @@ -2542,7 +2542,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "CAP-02", @@ -2573,7 +2573,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "CAP-03", @@ -2604,7 +2604,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "CAP-04", @@ -2635,7 +2635,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "CAP-05", @@ -2666,7 +2666,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "CAP-06", @@ -2697,7 +2697,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "CAP-07", @@ -2728,7 +2728,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "CAP-08", @@ -2759,7 +2759,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -2810,7 +2810,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "INC-02", @@ -2843,7 +2843,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "INC-03", @@ -2876,7 +2876,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "INC-04", @@ -2909,7 +2909,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "INC-05", @@ -2942,7 +2942,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "INC-06", @@ -2975,7 +2975,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "INC-07", @@ -3008,7 +3008,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "INC-08", @@ -3041,7 +3041,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -3088,7 +3088,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "FIN-02", @@ -3119,7 +3119,7 @@ "run_status": "RUNNING", "evidence_path": "sim/results_v2.md Rule v4", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "rule v4 pause 0 conflicts everywhere; the equivocator bound 2,800 to 2,889 at day 30", "run_by": "finality lane (aca0f5ed924a2a99b)", @@ -3156,7 +3156,7 @@ "run_status": "RUNNING", "evidence_path": "sim/results_v2.md Rule v4", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the v3 known-failed reproduced on the simulator and real nodes; the 31-day splits under v4", "run_by": "finality lane (aca0f5ed924a2a99b)", @@ -3193,7 +3193,7 @@ "run_status": "RUNNING", "evidence_path": "sim/results_v2.md Rule v4", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the 40/40/20 and silent-third pauses", "run_by": "finality lane (aca0f5ed924a2a99b)", @@ -3230,7 +3230,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/pool-vote-key-commitment.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the pool vote-key commitment design (the header's vote_key_hash under the pre-PoW hash)", "run_by": "finality lane (aca0f5ed924a2a99b)", @@ -3267,7 +3267,7 @@ "run_status": "RUNNING", "evidence_path": "sim/results_v2.md Rule v4", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "bought and stolen keys in the simulator rows", "run_by": "finality lane (aca0f5ed924a2a99b)", @@ -3304,7 +3304,7 @@ "run_status": "RUNNING", "evidence_path": "sim/results_v2.md; v5-fasttime 92bf6a7f", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the heal keeps every lock; the cold restart on 4 of 4 nodes in the fast-time run", "run_by": "finality lane (aca0f5ed924a2a99b)", @@ -3341,7 +3341,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -3388,7 +3388,7 @@ "run_status": "RUNNING", "evidence_path": "site/lc; docs/build/compatibility.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "/light with the trusted-inputs block and the data-availability paragraph", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -3425,7 +3425,7 @@ "run_status": "RUNNING", "evidence_path": "site/lc", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "/light's authority table and the execution-proof labels", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -3462,7 +3462,7 @@ "run_status": "RUNNING", "evidence_path": "site/lc", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "/receipt retitled the inclusion receipt; the payment receipt", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -3499,7 +3499,7 @@ "run_status": "RUNNING", "evidence_path": "site/lc; docs/bridge/light-client-bridge.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "/oracle's trust block; the Sepolia verifier redeployed for chain id 4465", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -3536,7 +3536,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "VER-06", @@ -3567,7 +3567,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "VER-07", @@ -3598,7 +3598,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "VER-08", @@ -3629,7 +3629,7 @@ "run_status": "RUNNING", "evidence_path": "docs/spec/finality-guarantees.md section 9", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the four states on igneum_getTransactionStatus (9fc9f42a) with the pause word; section 9 of finality-guarantees.md", "run_by": "reference-apps lane (a2060899d2a27d31c)", @@ -3682,7 +3682,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "OPS-02", @@ -3713,7 +3713,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "OPS-03", @@ -3744,7 +3744,7 @@ "run_status": "RUNNING", "evidence_path": "site/release-manifest.json", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the release manifest on igneum_getManifest (d5981514) and /release.json; the signing-key procedure owed", "run_by": "shipper (ae892a8b0f78fe31c)", @@ -3781,7 +3781,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "OPS-05", @@ -3812,7 +3812,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "OPS-06", @@ -3843,7 +3843,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "OPS-07", @@ -3874,7 +3874,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "OPS-08", @@ -3905,7 +3905,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -3952,7 +3952,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "UX-02", @@ -3983,7 +3983,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "UX-03", @@ -4014,7 +4014,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/app-audit-2026-10-08.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the 16 GB proving line and the dev fee in v2.0.0; the three income streams net of tariff owed (v2.0.1)", "run_by": "shipper (ae892a8b0f78fe31c)", @@ -4051,7 +4051,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "UX-05", @@ -4082,7 +4082,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/pool-vote-key-commitment.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the pool vote-key commitment design", "run_by": "pool design seat (a3832b1c3b274b310)", @@ -4119,7 +4119,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "UX-07", @@ -4150,7 +4150,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/app-audit-2026-10-08.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the restart-kind fix (da212ee2) and the update-return classes; explicit update acceptance owed (v2.0.1)", "run_by": "shipper (ae892a8b0f78fe31c)", @@ -4187,7 +4187,7 @@ "run_status": "RUNNING", "evidence_path": "docs/design/class-v5-stored-state.md", "run_id": "team-2026-10-08", - "updated": "2026-10-08 18:3x BST", + "updated": "2026-10-08 18:3x UK", "evidence_record": { "what_was_run": "the class v5 and v6 kits served with their fingerprints on six platforms", "run_by": "hash lane (a690540514aa453d7)", @@ -4250,7 +4250,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "COM-02", @@ -4286,7 +4286,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "COM-03", @@ -4322,7 +4322,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "COM-04", @@ -4358,7 +4358,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "COM-05", @@ -4394,7 +4394,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "COM-06", @@ -4430,7 +4430,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "COM-07", @@ -4466,7 +4466,7 @@ "run_status": "DEFERRED", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST (the founder: forget P13 for now)" + "updated": "2026-10-08 18:3x UK (the founder: forget P13 for now)" }, { "id": "COM-08", @@ -4502,7 +4502,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] }, @@ -4555,7 +4555,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "LEAD-02", @@ -4589,7 +4589,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "LEAD-03", @@ -4623,7 +4623,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "LEAD-04", @@ -4657,7 +4657,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "LEAD-05", @@ -4691,7 +4691,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "LEAD-06", @@ -4725,7 +4725,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "LEAD-07", @@ -4759,7 +4759,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" }, { "id": "LEAD-08", @@ -4793,7 +4793,7 @@ "run_status": "NOT RUN", "evidence_path": "", "run_id": "", - "updated": "2026-10-08 18:3x BST" + "updated": "2026-10-08 18:3x UK" } ] } @@ -5025,7 +5025,7 @@ "manual_page_count": 73, "approval": { "by": "the founder", - "at": "2026-10-08 18:2x BST", + "at": "2026-10-08 18:2x UK", "word": "approve as proposed in the tests, forget P13 for now", "profiles": { "P00": "APPROVED AS PROPOSED", @@ -5047,7 +5047,7 @@ "P16": "APPROVED AS PROPOSED" }, "rules_in_force": [ - "P03: a candidate change pays at most 5 percent of joules per accepted work and loses at most 2 percent of accepted throughput against the paired tuned baseline (replaces the 10 percent budget from 18:2x BST)", + "P03: a candidate change pays at most 5 percent of joules per accepted work and loses at most 2 percent of accepted throughput against the paired tuned baseline (replaces the 10 percent budget from 18:2x UK)", "P04: R_E at most 1.5 for every competitive-core cell at the same node and one node ahead against the lowest credible complete-system specialist; today's placed bracket (1.5x to 2.1x same-node) is a FAIL to work against and is served as such", "P12: the matched-tariff median at most 1.5, p90 at most 1.75, no core cell above 2.0", "P02: twelve retail configurations, three unaffiliated operators, the seven-day soak define D1's reproduction"